Commit | Line | Data |
---|---|---|
a66098da | 1 | /* |
ce9e2e1b LB |
2 | * drivers/net/wireless/mwl8k.c |
3 | * Driver for Marvell TOPDOG 802.11 Wireless cards | |
a66098da | 4 | * |
a145d575 | 5 | * Copyright (C) 2008-2009 Marvell Semiconductor Inc. |
a66098da LB |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
3d76e82c | 15 | #include <linux/sched.h> |
a66098da LB |
16 | #include <linux/spinlock.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/workqueue.h> | |
26 | ||
27 | #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" | |
28 | #define MWL8K_NAME KBUILD_MODNAME | |
a145d575 | 29 | #define MWL8K_VERSION "0.10" |
a66098da | 30 | |
a66098da LB |
31 | /* Register definitions */ |
32 | #define MWL8K_HIU_GEN_PTR 0x00000c10 | |
ce9e2e1b LB |
33 | #define MWL8K_MODE_STA 0x0000005a |
34 | #define MWL8K_MODE_AP 0x000000a5 | |
a66098da | 35 | #define MWL8K_HIU_INT_CODE 0x00000c14 |
ce9e2e1b LB |
36 | #define MWL8K_FWSTA_READY 0xf0f1f2f4 |
37 | #define MWL8K_FWAP_READY 0xf1f2f4a5 | |
38 | #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 | |
a66098da LB |
39 | #define MWL8K_HIU_SCRATCH 0x00000c40 |
40 | ||
41 | /* Host->device communications */ | |
42 | #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 | |
43 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c | |
44 | #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 | |
45 | #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 | |
46 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 | |
ce9e2e1b LB |
47 | #define MWL8K_H2A_INT_DUMMY (1 << 20) |
48 | #define MWL8K_H2A_INT_RESET (1 << 15) | |
49 | #define MWL8K_H2A_INT_DOORBELL (1 << 1) | |
50 | #define MWL8K_H2A_INT_PPA_READY (1 << 0) | |
a66098da LB |
51 | |
52 | /* Device->host communications */ | |
53 | #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c | |
54 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 | |
55 | #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 | |
56 | #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 | |
57 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c | |
ce9e2e1b LB |
58 | #define MWL8K_A2H_INT_DUMMY (1 << 20) |
59 | #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) | |
60 | #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) | |
61 | #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) | |
62 | #define MWL8K_A2H_INT_RADIO_ON (1 << 6) | |
63 | #define MWL8K_A2H_INT_RADIO_OFF (1 << 5) | |
64 | #define MWL8K_A2H_INT_MAC_EVENT (1 << 3) | |
65 | #define MWL8K_A2H_INT_OPC_DONE (1 << 2) | |
66 | #define MWL8K_A2H_INT_RX_READY (1 << 1) | |
67 | #define MWL8K_A2H_INT_TX_DONE (1 << 0) | |
a66098da LB |
68 | |
69 | #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ | |
70 | MWL8K_A2H_INT_CHNL_SWITCHED | \ | |
71 | MWL8K_A2H_INT_QUEUE_EMPTY | \ | |
72 | MWL8K_A2H_INT_RADAR_DETECT | \ | |
73 | MWL8K_A2H_INT_RADIO_ON | \ | |
74 | MWL8K_A2H_INT_RADIO_OFF | \ | |
75 | MWL8K_A2H_INT_MAC_EVENT | \ | |
76 | MWL8K_A2H_INT_OPC_DONE | \ | |
77 | MWL8K_A2H_INT_RX_READY | \ | |
78 | MWL8K_A2H_INT_TX_DONE) | |
79 | ||
a66098da LB |
80 | #define MWL8K_RX_QUEUES 1 |
81 | #define MWL8K_TX_QUEUES 4 | |
82 | ||
54bc3a0d LB |
83 | struct rxd_ops { |
84 | int rxd_size; | |
85 | void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); | |
86 | void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); | |
87 | int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status); | |
88 | }; | |
89 | ||
45a390dd | 90 | struct mwl8k_device_info { |
a74b295e LB |
91 | char *part_name; |
92 | char *helper_image; | |
93 | char *fw_image; | |
54bc3a0d | 94 | struct rxd_ops *rxd_ops; |
547810e3 | 95 | u16 modes; |
45a390dd LB |
96 | }; |
97 | ||
a66098da | 98 | struct mwl8k_rx_queue { |
45eb400d | 99 | int rxd_count; |
a66098da LB |
100 | |
101 | /* hw receives here */ | |
45eb400d | 102 | int head; |
a66098da LB |
103 | |
104 | /* refill descs here */ | |
45eb400d | 105 | int tail; |
a66098da | 106 | |
54bc3a0d | 107 | void *rxd; |
45eb400d | 108 | dma_addr_t rxd_dma; |
788838eb LB |
109 | struct { |
110 | struct sk_buff *skb; | |
111 | DECLARE_PCI_UNMAP_ADDR(dma) | |
112 | } *buf; | |
a66098da LB |
113 | }; |
114 | ||
a66098da LB |
115 | struct mwl8k_tx_queue { |
116 | /* hw transmits here */ | |
45eb400d | 117 | int head; |
a66098da LB |
118 | |
119 | /* sw appends here */ | |
45eb400d | 120 | int tail; |
a66098da | 121 | |
45eb400d LB |
122 | struct ieee80211_tx_queue_stats stats; |
123 | struct mwl8k_tx_desc *txd; | |
124 | dma_addr_t txd_dma; | |
125 | struct sk_buff **skb; | |
a66098da LB |
126 | }; |
127 | ||
128 | /* Pointers to the firmware data and meta information about it. */ | |
129 | struct mwl8k_firmware { | |
a66098da LB |
130 | /* Boot helper code */ |
131 | struct firmware *helper; | |
a74b295e LB |
132 | |
133 | /* Microcode */ | |
134 | struct firmware *ucode; | |
a66098da LB |
135 | }; |
136 | ||
137 | struct mwl8k_priv { | |
5b9482dd | 138 | void __iomem *sram; |
a66098da LB |
139 | void __iomem *regs; |
140 | struct ieee80211_hw *hw; | |
141 | ||
142 | struct pci_dev *pdev; | |
a66098da | 143 | |
45a390dd | 144 | struct mwl8k_device_info *device_info; |
eae74e65 | 145 | bool ap_fw; |
54bc3a0d | 146 | struct rxd_ops *rxd_ops; |
45a390dd | 147 | |
a66098da LB |
148 | /* firmware files and meta data */ |
149 | struct mwl8k_firmware fw; | |
a66098da | 150 | |
618952a7 LB |
151 | /* firmware access */ |
152 | struct mutex fw_mutex; | |
153 | struct task_struct *fw_mutex_owner; | |
154 | int fw_mutex_depth; | |
618952a7 LB |
155 | struct completion *hostcmd_wait; |
156 | ||
a66098da LB |
157 | /* lock held over TX and TX reap */ |
158 | spinlock_t tx_lock; | |
a66098da | 159 | |
88de754a LB |
160 | /* TX quiesce completion, protected by fw_mutex and tx_lock */ |
161 | struct completion *tx_wait; | |
162 | ||
a66098da | 163 | struct ieee80211_vif *vif; |
a66098da LB |
164 | |
165 | struct ieee80211_channel *current_channel; | |
166 | ||
167 | /* power management status cookie from firmware */ | |
168 | u32 *cookie; | |
169 | dma_addr_t cookie_dma; | |
170 | ||
171 | u16 num_mcaddrs; | |
a66098da | 172 | u8 hw_rev; |
2aa7b01f | 173 | u32 fw_rev; |
a66098da LB |
174 | |
175 | /* | |
176 | * Running count of TX packets in flight, to avoid | |
177 | * iterating over the transmit rings each time. | |
178 | */ | |
179 | int pending_tx_pkts; | |
180 | ||
181 | struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; | |
182 | struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES]; | |
183 | ||
184 | /* PHY parameters */ | |
185 | struct ieee80211_supported_band band; | |
186 | struct ieee80211_channel channels[14]; | |
5dfd3e2c | 187 | struct ieee80211_rate rates[13]; |
a66098da | 188 | |
c46563b7 | 189 | bool radio_on; |
68ce3884 | 190 | bool radio_short_preamble; |
a43c49a8 | 191 | bool sniffer_enabled; |
0439b1f5 | 192 | bool wmm_enabled; |
a66098da | 193 | |
a66098da LB |
194 | /* XXX need to convert this to handle multiple interfaces */ |
195 | bool capture_beacon; | |
d89173f2 | 196 | u8 capture_bssid[ETH_ALEN]; |
a66098da LB |
197 | struct sk_buff *beacon_skb; |
198 | ||
199 | /* | |
200 | * This FJ worker has to be global as it is scheduled from the | |
201 | * RX handler. At this point we don't know which interface it | |
202 | * belongs to until the list of bssids waiting to complete join | |
203 | * is checked. | |
204 | */ | |
205 | struct work_struct finalize_join_worker; | |
206 | ||
207 | /* Tasklet to reclaim TX descriptors and buffers after tx */ | |
208 | struct tasklet_struct tx_reclaim_task; | |
a66098da LB |
209 | }; |
210 | ||
211 | /* Per interface specific private data */ | |
212 | struct mwl8k_vif { | |
a66098da LB |
213 | /* backpointer to parent config block */ |
214 | struct mwl8k_priv *priv; | |
215 | ||
216 | /* BSS config of AP or IBSS from mac80211*/ | |
217 | struct ieee80211_bss_conf bss_info; | |
218 | ||
219 | /* BSSID of AP or IBSS */ | |
d89173f2 LB |
220 | u8 bssid[ETH_ALEN]; |
221 | u8 mac_addr[ETH_ALEN]; | |
a66098da LB |
222 | |
223 | /* | |
224 | * Subset of supported legacy rates. | |
225 | * Intersection of AP and STA supported rates. | |
226 | */ | |
5dfd3e2c | 227 | struct ieee80211_rate legacy_rates[13]; |
a66098da LB |
228 | |
229 | /* number of supported legacy rates */ | |
230 | u8 legacy_nrates; | |
231 | ||
a66098da LB |
232 | /* Index into station database.Returned by update_sta_db call */ |
233 | u8 peer_id; | |
234 | ||
235 | /* Non AMPDU sequence number assigned by driver */ | |
236 | u16 seqno; | |
a66098da LB |
237 | }; |
238 | ||
a94cc97e | 239 | #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) |
a66098da LB |
240 | |
241 | static const struct ieee80211_channel mwl8k_channels[] = { | |
242 | { .center_freq = 2412, .hw_value = 1, }, | |
243 | { .center_freq = 2417, .hw_value = 2, }, | |
244 | { .center_freq = 2422, .hw_value = 3, }, | |
245 | { .center_freq = 2427, .hw_value = 4, }, | |
246 | { .center_freq = 2432, .hw_value = 5, }, | |
247 | { .center_freq = 2437, .hw_value = 6, }, | |
248 | { .center_freq = 2442, .hw_value = 7, }, | |
249 | { .center_freq = 2447, .hw_value = 8, }, | |
250 | { .center_freq = 2452, .hw_value = 9, }, | |
251 | { .center_freq = 2457, .hw_value = 10, }, | |
252 | { .center_freq = 2462, .hw_value = 11, }, | |
253 | }; | |
254 | ||
255 | static const struct ieee80211_rate mwl8k_rates[] = { | |
256 | { .bitrate = 10, .hw_value = 2, }, | |
257 | { .bitrate = 20, .hw_value = 4, }, | |
258 | { .bitrate = 55, .hw_value = 11, }, | |
5dfd3e2c LB |
259 | { .bitrate = 110, .hw_value = 22, }, |
260 | { .bitrate = 220, .hw_value = 44, }, | |
a66098da LB |
261 | { .bitrate = 60, .hw_value = 12, }, |
262 | { .bitrate = 90, .hw_value = 18, }, | |
a66098da LB |
263 | { .bitrate = 120, .hw_value = 24, }, |
264 | { .bitrate = 180, .hw_value = 36, }, | |
265 | { .bitrate = 240, .hw_value = 48, }, | |
266 | { .bitrate = 360, .hw_value = 72, }, | |
267 | { .bitrate = 480, .hw_value = 96, }, | |
268 | { .bitrate = 540, .hw_value = 108, }, | |
269 | }; | |
270 | ||
a66098da LB |
271 | /* Set or get info from Firmware */ |
272 | #define MWL8K_CMD_SET 0x0001 | |
273 | #define MWL8K_CMD_GET 0x0000 | |
274 | ||
275 | /* Firmware command codes */ | |
276 | #define MWL8K_CMD_CODE_DNLD 0x0001 | |
277 | #define MWL8K_CMD_GET_HW_SPEC 0x0003 | |
42fba21d | 278 | #define MWL8K_CMD_SET_HW_SPEC 0x0004 |
a66098da LB |
279 | #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 |
280 | #define MWL8K_CMD_GET_STAT 0x0014 | |
ff45fc60 LB |
281 | #define MWL8K_CMD_RADIO_CONTROL 0x001c |
282 | #define MWL8K_CMD_RF_TX_POWER 0x001e | |
08b06347 | 283 | #define MWL8K_CMD_RF_ANTENNA 0x0020 |
a66098da LB |
284 | #define MWL8K_CMD_SET_PRE_SCAN 0x0107 |
285 | #define MWL8K_CMD_SET_POST_SCAN 0x0108 | |
ff45fc60 LB |
286 | #define MWL8K_CMD_SET_RF_CHANNEL 0x010a |
287 | #define MWL8K_CMD_SET_AID 0x010d | |
288 | #define MWL8K_CMD_SET_RATE 0x0110 | |
289 | #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 | |
290 | #define MWL8K_CMD_RTS_THRESHOLD 0x0113 | |
a66098da | 291 | #define MWL8K_CMD_SET_SLOT 0x0114 |
ff45fc60 LB |
292 | #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 |
293 | #define MWL8K_CMD_SET_WMM_MODE 0x0123 | |
a66098da | 294 | #define MWL8K_CMD_MIMO_CONFIG 0x0125 |
ff45fc60 | 295 | #define MWL8K_CMD_USE_FIXED_RATE 0x0126 |
a66098da | 296 | #define MWL8K_CMD_ENABLE_SNIFFER 0x0150 |
32060e1b | 297 | #define MWL8K_CMD_SET_MAC_ADDR 0x0202 |
a66098da | 298 | #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 |
ff45fc60 | 299 | #define MWL8K_CMD_UPDATE_STADB 0x1123 |
a66098da LB |
300 | |
301 | static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize) | |
302 | { | |
303 | #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ | |
304 | snprintf(buf, bufsize, "%s", #x);\ | |
305 | return buf;\ | |
306 | } while (0) | |
ce9e2e1b | 307 | switch (cmd & ~0x8000) { |
a66098da LB |
308 | MWL8K_CMDNAME(CODE_DNLD); |
309 | MWL8K_CMDNAME(GET_HW_SPEC); | |
42fba21d | 310 | MWL8K_CMDNAME(SET_HW_SPEC); |
a66098da LB |
311 | MWL8K_CMDNAME(MAC_MULTICAST_ADR); |
312 | MWL8K_CMDNAME(GET_STAT); | |
313 | MWL8K_CMDNAME(RADIO_CONTROL); | |
314 | MWL8K_CMDNAME(RF_TX_POWER); | |
08b06347 | 315 | MWL8K_CMDNAME(RF_ANTENNA); |
a66098da LB |
316 | MWL8K_CMDNAME(SET_PRE_SCAN); |
317 | MWL8K_CMDNAME(SET_POST_SCAN); | |
318 | MWL8K_CMDNAME(SET_RF_CHANNEL); | |
ff45fc60 LB |
319 | MWL8K_CMDNAME(SET_AID); |
320 | MWL8K_CMDNAME(SET_RATE); | |
321 | MWL8K_CMDNAME(SET_FINALIZE_JOIN); | |
322 | MWL8K_CMDNAME(RTS_THRESHOLD); | |
a66098da | 323 | MWL8K_CMDNAME(SET_SLOT); |
ff45fc60 LB |
324 | MWL8K_CMDNAME(SET_EDCA_PARAMS); |
325 | MWL8K_CMDNAME(SET_WMM_MODE); | |
a66098da | 326 | MWL8K_CMDNAME(MIMO_CONFIG); |
ff45fc60 | 327 | MWL8K_CMDNAME(USE_FIXED_RATE); |
a66098da | 328 | MWL8K_CMDNAME(ENABLE_SNIFFER); |
32060e1b | 329 | MWL8K_CMDNAME(SET_MAC_ADDR); |
a66098da | 330 | MWL8K_CMDNAME(SET_RATEADAPT_MODE); |
ff45fc60 | 331 | MWL8K_CMDNAME(UPDATE_STADB); |
a66098da LB |
332 | default: |
333 | snprintf(buf, bufsize, "0x%x", cmd); | |
334 | } | |
335 | #undef MWL8K_CMDNAME | |
336 | ||
337 | return buf; | |
338 | } | |
339 | ||
340 | /* Hardware and firmware reset */ | |
341 | static void mwl8k_hw_reset(struct mwl8k_priv *priv) | |
342 | { | |
343 | iowrite32(MWL8K_H2A_INT_RESET, | |
344 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
345 | iowrite32(MWL8K_H2A_INT_RESET, | |
346 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
347 | msleep(20); | |
348 | } | |
349 | ||
350 | /* Release fw image */ | |
351 | static void mwl8k_release_fw(struct firmware **fw) | |
352 | { | |
353 | if (*fw == NULL) | |
354 | return; | |
355 | release_firmware(*fw); | |
356 | *fw = NULL; | |
357 | } | |
358 | ||
359 | static void mwl8k_release_firmware(struct mwl8k_priv *priv) | |
360 | { | |
361 | mwl8k_release_fw(&priv->fw.ucode); | |
362 | mwl8k_release_fw(&priv->fw.helper); | |
363 | } | |
364 | ||
365 | /* Request fw image */ | |
366 | static int mwl8k_request_fw(struct mwl8k_priv *priv, | |
c2c357ce | 367 | const char *fname, struct firmware **fw) |
a66098da LB |
368 | { |
369 | /* release current image */ | |
370 | if (*fw != NULL) | |
371 | mwl8k_release_fw(fw); | |
372 | ||
373 | return request_firmware((const struct firmware **)fw, | |
c2c357ce | 374 | fname, &priv->pdev->dev); |
a66098da LB |
375 | } |
376 | ||
45a390dd | 377 | static int mwl8k_request_firmware(struct mwl8k_priv *priv) |
a66098da | 378 | { |
a74b295e | 379 | struct mwl8k_device_info *di = priv->device_info; |
a66098da LB |
380 | int rc; |
381 | ||
a74b295e LB |
382 | if (di->helper_image != NULL) { |
383 | rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper); | |
384 | if (rc) { | |
385 | printk(KERN_ERR "%s: Error requesting helper " | |
386 | "firmware file %s\n", pci_name(priv->pdev), | |
387 | di->helper_image); | |
388 | return rc; | |
389 | } | |
a66098da LB |
390 | } |
391 | ||
a74b295e | 392 | rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode); |
a66098da | 393 | if (rc) { |
c2c357ce | 394 | printk(KERN_ERR "%s: Error requesting firmware file %s\n", |
a74b295e | 395 | pci_name(priv->pdev), di->fw_image); |
a66098da LB |
396 | mwl8k_release_fw(&priv->fw.helper); |
397 | return rc; | |
398 | } | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
7e75b942 BH |
403 | MODULE_FIRMWARE("mwl8k/helper_8687.fw"); |
404 | MODULE_FIRMWARE("mwl8k/fmimage_8687.fw"); | |
405 | ||
a66098da LB |
406 | struct mwl8k_cmd_pkt { |
407 | __le16 code; | |
408 | __le16 length; | |
409 | __le16 seq_num; | |
410 | __le16 result; | |
411 | char payload[0]; | |
412 | } __attribute__((packed)); | |
413 | ||
414 | /* | |
415 | * Firmware loading. | |
416 | */ | |
417 | static int | |
418 | mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) | |
419 | { | |
420 | void __iomem *regs = priv->regs; | |
421 | dma_addr_t dma_addr; | |
a66098da LB |
422 | int loops; |
423 | ||
424 | dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); | |
425 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
426 | return -ENOMEM; | |
427 | ||
428 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
429 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
430 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
431 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
432 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
433 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
434 | ||
a66098da LB |
435 | loops = 1000; |
436 | do { | |
437 | u32 int_code; | |
438 | ||
439 | int_code = ioread32(regs + MWL8K_HIU_INT_CODE); | |
440 | if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { | |
441 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
a66098da LB |
442 | break; |
443 | } | |
444 | ||
3d76e82c | 445 | cond_resched(); |
a66098da LB |
446 | udelay(1); |
447 | } while (--loops); | |
448 | ||
449 | pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); | |
450 | ||
d4b70570 | 451 | return loops ? 0 : -ETIMEDOUT; |
a66098da LB |
452 | } |
453 | ||
454 | static int mwl8k_load_fw_image(struct mwl8k_priv *priv, | |
455 | const u8 *data, size_t length) | |
456 | { | |
457 | struct mwl8k_cmd_pkt *cmd; | |
458 | int done; | |
459 | int rc = 0; | |
460 | ||
461 | cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); | |
462 | if (cmd == NULL) | |
463 | return -ENOMEM; | |
464 | ||
465 | cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); | |
466 | cmd->seq_num = 0; | |
467 | cmd->result = 0; | |
468 | ||
469 | done = 0; | |
470 | while (length) { | |
471 | int block_size = length > 256 ? 256 : length; | |
472 | ||
473 | memcpy(cmd->payload, data + done, block_size); | |
474 | cmd->length = cpu_to_le16(block_size); | |
475 | ||
476 | rc = mwl8k_send_fw_load_cmd(priv, cmd, | |
477 | sizeof(*cmd) + block_size); | |
478 | if (rc) | |
479 | break; | |
480 | ||
481 | done += block_size; | |
482 | length -= block_size; | |
483 | } | |
484 | ||
485 | if (!rc) { | |
486 | cmd->length = 0; | |
487 | rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); | |
488 | } | |
489 | ||
490 | kfree(cmd); | |
491 | ||
492 | return rc; | |
493 | } | |
494 | ||
495 | static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, | |
496 | const u8 *data, size_t length) | |
497 | { | |
498 | unsigned char *buffer; | |
499 | int may_continue, rc = 0; | |
500 | u32 done, prev_block_size; | |
501 | ||
502 | buffer = kmalloc(1024, GFP_KERNEL); | |
503 | if (buffer == NULL) | |
504 | return -ENOMEM; | |
505 | ||
506 | done = 0; | |
507 | prev_block_size = 0; | |
508 | may_continue = 1000; | |
509 | while (may_continue > 0) { | |
510 | u32 block_size; | |
511 | ||
512 | block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); | |
513 | if (block_size & 1) { | |
514 | block_size &= ~1; | |
515 | may_continue--; | |
516 | } else { | |
517 | done += prev_block_size; | |
518 | length -= prev_block_size; | |
519 | } | |
520 | ||
521 | if (block_size > 1024 || block_size > length) { | |
522 | rc = -EOVERFLOW; | |
523 | break; | |
524 | } | |
525 | ||
526 | if (length == 0) { | |
527 | rc = 0; | |
528 | break; | |
529 | } | |
530 | ||
531 | if (block_size == 0) { | |
532 | rc = -EPROTO; | |
533 | may_continue--; | |
534 | udelay(1); | |
535 | continue; | |
536 | } | |
537 | ||
538 | prev_block_size = block_size; | |
539 | memcpy(buffer, data + done, block_size); | |
540 | ||
541 | rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); | |
542 | if (rc) | |
543 | break; | |
544 | } | |
545 | ||
546 | if (!rc && length != 0) | |
547 | rc = -EREMOTEIO; | |
548 | ||
549 | kfree(buffer); | |
550 | ||
551 | return rc; | |
552 | } | |
553 | ||
c2c357ce | 554 | static int mwl8k_load_firmware(struct ieee80211_hw *hw) |
a66098da | 555 | { |
c2c357ce LB |
556 | struct mwl8k_priv *priv = hw->priv; |
557 | struct firmware *fw = priv->fw.ucode; | |
eae74e65 | 558 | struct mwl8k_device_info *di = priv->device_info; |
c2c357ce LB |
559 | int rc; |
560 | int loops; | |
561 | ||
562 | if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) { | |
563 | struct firmware *helper = priv->fw.helper; | |
a66098da | 564 | |
c2c357ce LB |
565 | if (helper == NULL) { |
566 | printk(KERN_ERR "%s: helper image needed but none " | |
567 | "given\n", pci_name(priv->pdev)); | |
568 | return -EINVAL; | |
569 | } | |
a66098da | 570 | |
c2c357ce | 571 | rc = mwl8k_load_fw_image(priv, helper->data, helper->size); |
a66098da LB |
572 | if (rc) { |
573 | printk(KERN_ERR "%s: unable to load firmware " | |
c2c357ce | 574 | "helper image\n", pci_name(priv->pdev)); |
a66098da LB |
575 | return rc; |
576 | } | |
577 | msleep(1); | |
578 | ||
c2c357ce | 579 | rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); |
a66098da | 580 | } else { |
c2c357ce | 581 | rc = mwl8k_load_fw_image(priv, fw->data, fw->size); |
a66098da LB |
582 | } |
583 | ||
584 | if (rc) { | |
c2c357ce LB |
585 | printk(KERN_ERR "%s: unable to load firmware image\n", |
586 | pci_name(priv->pdev)); | |
a66098da LB |
587 | return rc; |
588 | } | |
589 | ||
eae74e65 LB |
590 | if (di->modes & BIT(NL80211_IFTYPE_AP)) |
591 | iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR); | |
592 | else | |
593 | iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); | |
a66098da LB |
594 | msleep(1); |
595 | ||
596 | loops = 200000; | |
597 | do { | |
eae74e65 LB |
598 | u32 ready_code; |
599 | ||
600 | ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
601 | if (ready_code == MWL8K_FWAP_READY) { | |
602 | priv->ap_fw = 1; | |
603 | break; | |
604 | } else if (ready_code == MWL8K_FWSTA_READY) { | |
605 | priv->ap_fw = 0; | |
a66098da | 606 | break; |
eae74e65 LB |
607 | } |
608 | ||
609 | cond_resched(); | |
a66098da LB |
610 | udelay(1); |
611 | } while (--loops); | |
612 | ||
613 | return loops ? 0 : -ETIMEDOUT; | |
614 | } | |
615 | ||
616 | ||
617 | /* | |
618 | * Defines shared between transmission and reception. | |
619 | */ | |
620 | /* HT control fields for firmware */ | |
621 | struct ewc_ht_info { | |
622 | __le16 control1; | |
623 | __le16 control2; | |
624 | __le16 control3; | |
625 | } __attribute__((packed)); | |
626 | ||
627 | /* Firmware Station database operations */ | |
628 | #define MWL8K_STA_DB_ADD_ENTRY 0 | |
629 | #define MWL8K_STA_DB_MODIFY_ENTRY 1 | |
630 | #define MWL8K_STA_DB_DEL_ENTRY 2 | |
631 | #define MWL8K_STA_DB_FLUSH 3 | |
632 | ||
633 | /* Peer Entry flags - used to define the type of the peer node */ | |
634 | #define MWL8K_PEER_TYPE_ACCESSPOINT 2 | |
a66098da | 635 | |
5dfd3e2c | 636 | #define MWL8K_IEEE_LEGACY_DATA_RATES 13 |
a66098da | 637 | #define MWL8K_MCS_BITMAP_SIZE 16 |
a66098da LB |
638 | |
639 | struct peer_capability_info { | |
640 | /* Peer type - AP vs. STA. */ | |
641 | __u8 peer_type; | |
642 | ||
643 | /* Basic 802.11 capabilities from assoc resp. */ | |
644 | __le16 basic_caps; | |
645 | ||
646 | /* Set if peer supports 802.11n high throughput (HT). */ | |
647 | __u8 ht_support; | |
648 | ||
649 | /* Valid if HT is supported. */ | |
650 | __le16 ht_caps; | |
651 | __u8 extended_ht_caps; | |
652 | struct ewc_ht_info ewc_info; | |
653 | ||
654 | /* Legacy rate table. Intersection of our rates and peer rates. */ | |
655 | __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES]; | |
656 | ||
657 | /* HT rate table. Intersection of our rates and peer rates. */ | |
658 | __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE]; | |
c23b5a69 | 659 | __u8 pad[16]; |
a66098da LB |
660 | |
661 | /* If set, interoperability mode, no proprietary extensions. */ | |
662 | __u8 interop; | |
663 | __u8 pad2; | |
664 | __u8 station_id; | |
665 | __le16 amsdu_enabled; | |
666 | } __attribute__((packed)); | |
667 | ||
668 | /* Inline functions to manipulate QoS field in data descriptor. */ | |
a66098da LB |
669 | static inline u16 mwl8k_qos_setbit_eosp(u16 qos) |
670 | { | |
671 | u16 val_mask = 1 << 4; | |
672 | ||
673 | /* End of Service Period Bit 4 */ | |
674 | return qos | val_mask; | |
675 | } | |
676 | ||
677 | static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy) | |
678 | { | |
679 | u16 val_mask = 0x3; | |
680 | u8 shift = 5; | |
681 | u16 qos_mask = ~(val_mask << shift); | |
682 | ||
683 | /* Ack Policy Bit 5-6 */ | |
684 | return (qos & qos_mask) | ((ack_policy & val_mask) << shift); | |
685 | } | |
686 | ||
687 | static inline u16 mwl8k_qos_setbit_amsdu(u16 qos) | |
688 | { | |
689 | u16 val_mask = 1 << 7; | |
690 | ||
691 | /* AMSDU present Bit 7 */ | |
692 | return qos | val_mask; | |
693 | } | |
694 | ||
695 | static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len) | |
696 | { | |
697 | u16 val_mask = 0xff; | |
698 | u8 shift = 8; | |
699 | u16 qos_mask = ~(val_mask << shift); | |
700 | ||
701 | /* Queue Length Bits 8-15 */ | |
702 | return (qos & qos_mask) | ((len & val_mask) << shift); | |
703 | } | |
704 | ||
705 | /* DMA header used by firmware and hardware. */ | |
706 | struct mwl8k_dma_data { | |
707 | __le16 fwlen; | |
708 | struct ieee80211_hdr wh; | |
709 | } __attribute__((packed)); | |
710 | ||
711 | /* Routines to add/remove DMA header from skb. */ | |
76266b2a | 712 | static inline void mwl8k_remove_dma_header(struct sk_buff *skb) |
a66098da | 713 | { |
76266b2a | 714 | struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data; |
a66098da | 715 | void *dst, *src = &tr->wh; |
76266b2a | 716 | int hdrlen = ieee80211_hdrlen(tr->wh.frame_control); |
a66098da LB |
717 | u16 space = sizeof(struct mwl8k_dma_data) - hdrlen; |
718 | ||
719 | dst = (void *)tr + space; | |
720 | if (dst != src) { | |
721 | memmove(dst, src, hdrlen); | |
722 | skb_pull(skb, space); | |
723 | } | |
a66098da LB |
724 | } |
725 | ||
76266b2a | 726 | static inline void mwl8k_add_dma_header(struct sk_buff *skb) |
a66098da LB |
727 | { |
728 | struct ieee80211_hdr *wh; | |
729 | u32 hdrlen, pktlen; | |
730 | struct mwl8k_dma_data *tr; | |
731 | ||
732 | wh = (struct ieee80211_hdr *)skb->data; | |
733 | hdrlen = ieee80211_hdrlen(wh->frame_control); | |
734 | pktlen = skb->len; | |
735 | ||
736 | /* | |
737 | * Copy up/down the 802.11 header; the firmware requires | |
738 | * we present a 2-byte payload length followed by a | |
739 | * 4-address header (w/o QoS), followed (optionally) by | |
740 | * any WEP/ExtIV header (but only filled in for CCMP). | |
741 | */ | |
742 | if (hdrlen != sizeof(struct mwl8k_dma_data)) | |
743 | skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen); | |
744 | ||
745 | tr = (struct mwl8k_dma_data *)skb->data; | |
746 | if (wh != &tr->wh) | |
747 | memmove(&tr->wh, wh, hdrlen); | |
748 | ||
749 | /* Clear addr4 */ | |
d89173f2 | 750 | memset(tr->wh.addr4, 0, ETH_ALEN); |
a66098da LB |
751 | |
752 | /* | |
753 | * Firmware length is the length of the fully formed "802.11 | |
754 | * payload". That is, everything except for the 802.11 header. | |
755 | * This includes all crypto material including the MIC. | |
756 | */ | |
757 | tr->fwlen = cpu_to_le16(pktlen - hdrlen); | |
a66098da LB |
758 | } |
759 | ||
760 | ||
761 | /* | |
6f6d1e9a LB |
762 | * Packet reception for 88w8366. |
763 | */ | |
764 | struct mwl8k_rxd_8366 { | |
765 | __le16 pkt_len; | |
766 | __u8 sq2; | |
767 | __u8 rate; | |
768 | __le32 pkt_phys_addr; | |
769 | __le32 next_rxd_phys_addr; | |
770 | __le16 qos_control; | |
771 | __le16 htsig2; | |
772 | __le32 hw_rssi_info; | |
773 | __le32 hw_noise_floor_info; | |
774 | __u8 noise_floor; | |
775 | __u8 pad0[3]; | |
776 | __u8 rssi; | |
777 | __u8 rx_status; | |
778 | __u8 channel; | |
779 | __u8 rx_ctrl; | |
780 | } __attribute__((packed)); | |
781 | ||
782 | #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80 | |
783 | ||
784 | static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr) | |
785 | { | |
786 | struct mwl8k_rxd_8366 *rxd = _rxd; | |
787 | ||
788 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
789 | rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST; | |
790 | } | |
791 | ||
792 | static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len) | |
793 | { | |
794 | struct mwl8k_rxd_8366 *rxd = _rxd; | |
795 | ||
796 | rxd->pkt_len = cpu_to_le16(len); | |
797 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
798 | wmb(); | |
799 | rxd->rx_ctrl = 0; | |
800 | } | |
801 | ||
802 | static int | |
803 | mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status) | |
804 | { | |
805 | struct mwl8k_rxd_8366 *rxd = _rxd; | |
806 | ||
807 | if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST)) | |
808 | return -1; | |
809 | rmb(); | |
810 | ||
811 | memset(status, 0, sizeof(*status)); | |
812 | ||
813 | status->signal = -rxd->rssi; | |
814 | status->noise = -rxd->noise_floor; | |
815 | ||
816 | if (rxd->rate & 0x80) { | |
817 | status->flag |= RX_FLAG_HT; | |
818 | status->rate_idx = rxd->rate & 0x7f; | |
819 | } else { | |
820 | int i; | |
821 | ||
822 | for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) { | |
823 | if (mwl8k_rates[i].hw_value == rxd->rate) { | |
824 | status->rate_idx = i; | |
825 | break; | |
826 | } | |
827 | } | |
828 | } | |
829 | ||
830 | status->band = IEEE80211_BAND_2GHZ; | |
831 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
832 | ||
833 | return le16_to_cpu(rxd->pkt_len); | |
834 | } | |
835 | ||
836 | static struct rxd_ops rxd_8366_ops = { | |
837 | .rxd_size = sizeof(struct mwl8k_rxd_8366), | |
838 | .rxd_init = mwl8k_rxd_8366_init, | |
839 | .rxd_refill = mwl8k_rxd_8366_refill, | |
840 | .rxd_process = mwl8k_rxd_8366_process, | |
841 | }; | |
842 | ||
843 | /* | |
844 | * Packet reception for 88w8687. | |
a66098da | 845 | */ |
54bc3a0d | 846 | struct mwl8k_rxd_8687 { |
a66098da LB |
847 | __le16 pkt_len; |
848 | __u8 link_quality; | |
849 | __u8 noise_level; | |
850 | __le32 pkt_phys_addr; | |
45eb400d | 851 | __le32 next_rxd_phys_addr; |
a66098da LB |
852 | __le16 qos_control; |
853 | __le16 rate_info; | |
854 | __le32 pad0[4]; | |
855 | __u8 rssi; | |
856 | __u8 channel; | |
857 | __le16 pad1; | |
858 | __u8 rx_ctrl; | |
859 | __u8 rx_status; | |
860 | __u8 pad2[2]; | |
861 | } __attribute__((packed)); | |
862 | ||
54bc3a0d LB |
863 | #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000 |
864 | #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) | |
865 | #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) | |
866 | #define MWL8K_8687_RATE_INFO_40MHZ 0x0004 | |
867 | #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002 | |
868 | #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001 | |
869 | ||
870 | #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02 | |
871 | ||
872 | static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr) | |
873 | { | |
874 | struct mwl8k_rxd_8687 *rxd = _rxd; | |
875 | ||
876 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
877 | rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST; | |
878 | } | |
879 | ||
880 | static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len) | |
881 | { | |
882 | struct mwl8k_rxd_8687 *rxd = _rxd; | |
883 | ||
884 | rxd->pkt_len = cpu_to_le16(len); | |
885 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
886 | wmb(); | |
887 | rxd->rx_ctrl = 0; | |
888 | } | |
889 | ||
890 | static int | |
891 | mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status) | |
892 | { | |
893 | struct mwl8k_rxd_8687 *rxd = _rxd; | |
894 | u16 rate_info; | |
895 | ||
896 | if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST)) | |
897 | return -1; | |
898 | rmb(); | |
899 | ||
900 | rate_info = le16_to_cpu(rxd->rate_info); | |
901 | ||
902 | memset(status, 0, sizeof(*status)); | |
903 | ||
904 | status->signal = -rxd->rssi; | |
905 | status->noise = -rxd->noise_level; | |
906 | status->qual = rxd->link_quality; | |
907 | status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info); | |
908 | status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info); | |
909 | ||
910 | if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE) | |
911 | status->flag |= RX_FLAG_SHORTPRE; | |
912 | if (rate_info & MWL8K_8687_RATE_INFO_40MHZ) | |
913 | status->flag |= RX_FLAG_40MHZ; | |
914 | if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI) | |
915 | status->flag |= RX_FLAG_SHORT_GI; | |
916 | if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT) | |
917 | status->flag |= RX_FLAG_HT; | |
918 | ||
919 | status->band = IEEE80211_BAND_2GHZ; | |
920 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
921 | ||
922 | return le16_to_cpu(rxd->pkt_len); | |
923 | } | |
924 | ||
925 | static struct rxd_ops rxd_8687_ops = { | |
926 | .rxd_size = sizeof(struct mwl8k_rxd_8687), | |
927 | .rxd_init = mwl8k_rxd_8687_init, | |
928 | .rxd_refill = mwl8k_rxd_8687_refill, | |
929 | .rxd_process = mwl8k_rxd_8687_process, | |
930 | }; | |
931 | ||
932 | ||
a66098da LB |
933 | #define MWL8K_RX_DESCS 256 |
934 | #define MWL8K_RX_MAXSZ 3800 | |
935 | ||
936 | static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) | |
937 | { | |
938 | struct mwl8k_priv *priv = hw->priv; | |
939 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
940 | int size; | |
941 | int i; | |
942 | ||
45eb400d LB |
943 | rxq->rxd_count = 0; |
944 | rxq->head = 0; | |
945 | rxq->tail = 0; | |
a66098da | 946 | |
54bc3a0d | 947 | size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; |
a66098da | 948 | |
45eb400d LB |
949 | rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); |
950 | if (rxq->rxd == NULL) { | |
a66098da | 951 | printk(KERN_ERR "%s: failed to alloc RX descriptors\n", |
c2c357ce | 952 | wiphy_name(hw->wiphy)); |
a66098da LB |
953 | return -ENOMEM; |
954 | } | |
45eb400d | 955 | memset(rxq->rxd, 0, size); |
a66098da | 956 | |
788838eb LB |
957 | rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL); |
958 | if (rxq->buf == NULL) { | |
a66098da | 959 | printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", |
c2c357ce | 960 | wiphy_name(hw->wiphy)); |
45eb400d | 961 | pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); |
a66098da LB |
962 | return -ENOMEM; |
963 | } | |
788838eb | 964 | memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf)); |
a66098da LB |
965 | |
966 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
54bc3a0d LB |
967 | int desc_size; |
968 | void *rxd; | |
a66098da | 969 | int nexti; |
54bc3a0d LB |
970 | dma_addr_t next_dma_addr; |
971 | ||
972 | desc_size = priv->rxd_ops->rxd_size; | |
973 | rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); | |
a66098da | 974 | |
54bc3a0d LB |
975 | nexti = i + 1; |
976 | if (nexti == MWL8K_RX_DESCS) | |
977 | nexti = 0; | |
978 | next_dma_addr = rxq->rxd_dma + (nexti * desc_size); | |
a66098da | 979 | |
54bc3a0d | 980 | priv->rxd_ops->rxd_init(rxd, next_dma_addr); |
a66098da LB |
981 | } |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
986 | static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) | |
987 | { | |
988 | struct mwl8k_priv *priv = hw->priv; | |
989 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
990 | int refilled; | |
991 | ||
992 | refilled = 0; | |
45eb400d | 993 | while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { |
a66098da | 994 | struct sk_buff *skb; |
788838eb | 995 | dma_addr_t addr; |
a66098da | 996 | int rx; |
54bc3a0d | 997 | void *rxd; |
a66098da LB |
998 | |
999 | skb = dev_alloc_skb(MWL8K_RX_MAXSZ); | |
1000 | if (skb == NULL) | |
1001 | break; | |
1002 | ||
788838eb LB |
1003 | addr = pci_map_single(priv->pdev, skb->data, |
1004 | MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); | |
a66098da | 1005 | |
54bc3a0d LB |
1006 | rxq->rxd_count++; |
1007 | rx = rxq->tail++; | |
1008 | if (rxq->tail == MWL8K_RX_DESCS) | |
1009 | rxq->tail = 0; | |
788838eb LB |
1010 | rxq->buf[rx].skb = skb; |
1011 | pci_unmap_addr_set(&rxq->buf[rx], dma, addr); | |
54bc3a0d LB |
1012 | |
1013 | rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); | |
1014 | priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); | |
a66098da LB |
1015 | |
1016 | refilled++; | |
1017 | } | |
1018 | ||
1019 | return refilled; | |
1020 | } | |
1021 | ||
1022 | /* Must be called only when the card's reception is completely halted */ | |
1023 | static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) | |
1024 | { | |
1025 | struct mwl8k_priv *priv = hw->priv; | |
1026 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
1027 | int i; | |
1028 | ||
1029 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
788838eb LB |
1030 | if (rxq->buf[i].skb != NULL) { |
1031 | pci_unmap_single(priv->pdev, | |
1032 | pci_unmap_addr(&rxq->buf[i], dma), | |
1033 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
1034 | pci_unmap_addr_set(&rxq->buf[i], dma, 0); | |
1035 | ||
1036 | kfree_skb(rxq->buf[i].skb); | |
1037 | rxq->buf[i].skb = NULL; | |
a66098da LB |
1038 | } |
1039 | } | |
1040 | ||
788838eb LB |
1041 | kfree(rxq->buf); |
1042 | rxq->buf = NULL; | |
a66098da LB |
1043 | |
1044 | pci_free_consistent(priv->pdev, | |
54bc3a0d | 1045 | MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, |
45eb400d LB |
1046 | rxq->rxd, rxq->rxd_dma); |
1047 | rxq->rxd = NULL; | |
a66098da LB |
1048 | } |
1049 | ||
1050 | ||
1051 | /* | |
1052 | * Scan a list of BSSIDs to process for finalize join. | |
1053 | * Allows for extension to process multiple BSSIDs. | |
1054 | */ | |
1055 | static inline int | |
1056 | mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) | |
1057 | { | |
1058 | return priv->capture_beacon && | |
1059 | ieee80211_is_beacon(wh->frame_control) && | |
1060 | !compare_ether_addr(wh->addr3, priv->capture_bssid); | |
1061 | } | |
1062 | ||
3779752d LB |
1063 | static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, |
1064 | struct sk_buff *skb) | |
a66098da | 1065 | { |
3779752d LB |
1066 | struct mwl8k_priv *priv = hw->priv; |
1067 | ||
a66098da | 1068 | priv->capture_beacon = false; |
d89173f2 | 1069 | memset(priv->capture_bssid, 0, ETH_ALEN); |
a66098da LB |
1070 | |
1071 | /* | |
1072 | * Use GFP_ATOMIC as rxq_process is called from | |
1073 | * the primary interrupt handler, memory allocation call | |
1074 | * must not sleep. | |
1075 | */ | |
1076 | priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); | |
1077 | if (priv->beacon_skb != NULL) | |
3779752d | 1078 | ieee80211_queue_work(hw, &priv->finalize_join_worker); |
a66098da LB |
1079 | } |
1080 | ||
1081 | static int rxq_process(struct ieee80211_hw *hw, int index, int limit) | |
1082 | { | |
1083 | struct mwl8k_priv *priv = hw->priv; | |
1084 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
1085 | int processed; | |
1086 | ||
1087 | processed = 0; | |
45eb400d | 1088 | while (rxq->rxd_count && limit--) { |
a66098da | 1089 | struct sk_buff *skb; |
54bc3a0d LB |
1090 | void *rxd; |
1091 | int pkt_len; | |
a66098da | 1092 | struct ieee80211_rx_status status; |
a66098da | 1093 | |
788838eb | 1094 | skb = rxq->buf[rxq->head].skb; |
d25f9f13 LB |
1095 | if (skb == NULL) |
1096 | break; | |
54bc3a0d LB |
1097 | |
1098 | rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); | |
1099 | ||
1100 | pkt_len = priv->rxd_ops->rxd_process(rxd, &status); | |
1101 | if (pkt_len < 0) | |
1102 | break; | |
1103 | ||
788838eb LB |
1104 | rxq->buf[rxq->head].skb = NULL; |
1105 | ||
1106 | pci_unmap_single(priv->pdev, | |
1107 | pci_unmap_addr(&rxq->buf[rxq->head], dma), | |
1108 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
1109 | pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); | |
a66098da | 1110 | |
54bc3a0d LB |
1111 | rxq->head++; |
1112 | if (rxq->head == MWL8K_RX_DESCS) | |
1113 | rxq->head = 0; | |
1114 | ||
45eb400d | 1115 | rxq->rxd_count--; |
a66098da | 1116 | |
54bc3a0d | 1117 | skb_put(skb, pkt_len); |
76266b2a | 1118 | mwl8k_remove_dma_header(skb); |
a66098da | 1119 | |
a66098da | 1120 | /* |
c2c357ce LB |
1121 | * Check for a pending join operation. Save a |
1122 | * copy of the beacon and schedule a tasklet to | |
1123 | * send a FINALIZE_JOIN command to the firmware. | |
a66098da | 1124 | */ |
54bc3a0d | 1125 | if (mwl8k_capture_bssid(priv, (void *)skb->data)) |
3779752d | 1126 | mwl8k_save_beacon(hw, skb); |
a66098da | 1127 | |
f1d58c25 JB |
1128 | memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); |
1129 | ieee80211_rx_irqsafe(hw, skb); | |
a66098da LB |
1130 | |
1131 | processed++; | |
1132 | } | |
1133 | ||
1134 | return processed; | |
1135 | } | |
1136 | ||
1137 | ||
1138 | /* | |
1139 | * Packet transmission. | |
1140 | */ | |
1141 | ||
a66098da LB |
1142 | /* Transmit packet ACK policy */ |
1143 | #define MWL8K_TXD_ACK_POLICY_NORMAL 0 | |
a66098da LB |
1144 | #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3 |
1145 | ||
a66098da LB |
1146 | #define MWL8K_TXD_STATUS_OK 0x00000001 |
1147 | #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 | |
1148 | #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 | |
1149 | #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 | |
a66098da | 1150 | #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 |
a66098da LB |
1151 | |
1152 | struct mwl8k_tx_desc { | |
1153 | __le32 status; | |
1154 | __u8 data_rate; | |
1155 | __u8 tx_priority; | |
1156 | __le16 qos_control; | |
1157 | __le32 pkt_phys_addr; | |
1158 | __le16 pkt_len; | |
d89173f2 | 1159 | __u8 dest_MAC_addr[ETH_ALEN]; |
45eb400d | 1160 | __le32 next_txd_phys_addr; |
a66098da LB |
1161 | __le32 reserved; |
1162 | __le16 rate_info; | |
1163 | __u8 peer_id; | |
1164 | __u8 tx_frag_cnt; | |
1165 | } __attribute__((packed)); | |
1166 | ||
1167 | #define MWL8K_TX_DESCS 128 | |
1168 | ||
1169 | static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) | |
1170 | { | |
1171 | struct mwl8k_priv *priv = hw->priv; | |
1172 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1173 | int size; | |
1174 | int i; | |
1175 | ||
45eb400d LB |
1176 | memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats)); |
1177 | txq->stats.limit = MWL8K_TX_DESCS; | |
1178 | txq->head = 0; | |
1179 | txq->tail = 0; | |
a66098da LB |
1180 | |
1181 | size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); | |
1182 | ||
45eb400d LB |
1183 | txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); |
1184 | if (txq->txd == NULL) { | |
a66098da | 1185 | printk(KERN_ERR "%s: failed to alloc TX descriptors\n", |
c2c357ce | 1186 | wiphy_name(hw->wiphy)); |
a66098da LB |
1187 | return -ENOMEM; |
1188 | } | |
45eb400d | 1189 | memset(txq->txd, 0, size); |
a66098da | 1190 | |
45eb400d LB |
1191 | txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL); |
1192 | if (txq->skb == NULL) { | |
a66098da | 1193 | printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", |
c2c357ce | 1194 | wiphy_name(hw->wiphy)); |
45eb400d | 1195 | pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); |
a66098da LB |
1196 | return -ENOMEM; |
1197 | } | |
45eb400d | 1198 | memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb)); |
a66098da LB |
1199 | |
1200 | for (i = 0; i < MWL8K_TX_DESCS; i++) { | |
1201 | struct mwl8k_tx_desc *tx_desc; | |
1202 | int nexti; | |
1203 | ||
45eb400d | 1204 | tx_desc = txq->txd + i; |
a66098da LB |
1205 | nexti = (i + 1) % MWL8K_TX_DESCS; |
1206 | ||
1207 | tx_desc->status = 0; | |
45eb400d LB |
1208 | tx_desc->next_txd_phys_addr = |
1209 | cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); | |
a66098da LB |
1210 | } |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
1215 | static inline void mwl8k_tx_start(struct mwl8k_priv *priv) | |
1216 | { | |
1217 | iowrite32(MWL8K_H2A_INT_PPA_READY, | |
1218 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1219 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1220 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1221 | ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
1222 | } | |
1223 | ||
a66098da LB |
1224 | struct mwl8k_txq_info { |
1225 | u32 fw_owned; | |
1226 | u32 drv_owned; | |
1227 | u32 unused; | |
1228 | u32 len; | |
1229 | u32 head; | |
1230 | u32 tail; | |
1231 | }; | |
1232 | ||
1233 | static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv, | |
c3f967d3 | 1234 | struct mwl8k_txq_info *txinfo) |
a66098da LB |
1235 | { |
1236 | int count, desc, status; | |
1237 | struct mwl8k_tx_queue *txq; | |
1238 | struct mwl8k_tx_desc *tx_desc; | |
1239 | int ndescs = 0; | |
1240 | ||
c3f967d3 LB |
1241 | memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info)); |
1242 | ||
c3f967d3 | 1243 | for (count = 0; count < MWL8K_TX_QUEUES; count++) { |
a66098da | 1244 | txq = priv->txq + count; |
45eb400d LB |
1245 | txinfo[count].len = txq->stats.len; |
1246 | txinfo[count].head = txq->head; | |
1247 | txinfo[count].tail = txq->tail; | |
a66098da | 1248 | for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { |
45eb400d | 1249 | tx_desc = txq->txd + desc; |
a66098da LB |
1250 | status = le32_to_cpu(tx_desc->status); |
1251 | ||
1252 | if (status & MWL8K_TXD_STATUS_FW_OWNED) | |
1253 | txinfo[count].fw_owned++; | |
1254 | else | |
1255 | txinfo[count].drv_owned++; | |
1256 | ||
1257 | if (tx_desc->pkt_len == 0) | |
1258 | txinfo[count].unused++; | |
1259 | } | |
1260 | } | |
a66098da LB |
1261 | |
1262 | return ndescs; | |
1263 | } | |
1264 | ||
618952a7 | 1265 | /* |
88de754a | 1266 | * Must be called with priv->fw_mutex held and tx queues stopped. |
618952a7 | 1267 | */ |
950d5b01 | 1268 | static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) |
a66098da | 1269 | { |
a66098da | 1270 | struct mwl8k_priv *priv = hw->priv; |
88de754a | 1271 | DECLARE_COMPLETION_ONSTACK(tx_wait); |
ce9e2e1b LB |
1272 | u32 count; |
1273 | unsigned long timeout; | |
a66098da LB |
1274 | |
1275 | might_sleep(); | |
1276 | ||
a66098da | 1277 | spin_lock_bh(&priv->tx_lock); |
88de754a LB |
1278 | count = priv->pending_tx_pkts; |
1279 | if (count) | |
1280 | priv->tx_wait = &tx_wait; | |
a66098da LB |
1281 | spin_unlock_bh(&priv->tx_lock); |
1282 | ||
1283 | if (count) { | |
c3f967d3 | 1284 | struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES]; |
a66098da LB |
1285 | int index; |
1286 | int newcount; | |
1287 | ||
88de754a | 1288 | timeout = wait_for_completion_timeout(&tx_wait, |
618952a7 | 1289 | msecs_to_jiffies(5000)); |
a66098da LB |
1290 | if (timeout) |
1291 | return 0; | |
1292 | ||
1293 | spin_lock_bh(&priv->tx_lock); | |
1294 | priv->tx_wait = NULL; | |
88de754a LB |
1295 | newcount = priv->pending_tx_pkts; |
1296 | mwl8k_scan_tx_ring(priv, txinfo); | |
a66098da LB |
1297 | spin_unlock_bh(&priv->tx_lock); |
1298 | ||
618952a7 | 1299 | printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n", |
950d5b01 | 1300 | __func__, __LINE__, count, newcount); |
a66098da | 1301 | |
c3f967d3 | 1302 | for (index = 0; index < MWL8K_TX_QUEUES; index++) |
c2c357ce LB |
1303 | printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u " |
1304 | "DRV:%u U:%u\n", | |
a66098da LB |
1305 | index, |
1306 | txinfo[index].len, | |
1307 | txinfo[index].head, | |
1308 | txinfo[index].tail, | |
1309 | txinfo[index].fw_owned, | |
1310 | txinfo[index].drv_owned, | |
1311 | txinfo[index].unused); | |
ce9e2e1b | 1312 | |
a66098da LB |
1313 | return -ETIMEDOUT; |
1314 | } | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
c23b5a69 LB |
1319 | #define MWL8K_TXD_SUCCESS(status) \ |
1320 | ((status) & (MWL8K_TXD_STATUS_OK | \ | |
1321 | MWL8K_TXD_STATUS_OK_RETRY | \ | |
1322 | MWL8K_TXD_STATUS_OK_MORE_RETRY)) | |
a66098da LB |
1323 | |
1324 | static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force) | |
1325 | { | |
1326 | struct mwl8k_priv *priv = hw->priv; | |
1327 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1328 | int wake = 0; | |
1329 | ||
45eb400d | 1330 | while (txq->stats.len > 0) { |
a66098da | 1331 | int tx; |
a66098da LB |
1332 | struct mwl8k_tx_desc *tx_desc; |
1333 | unsigned long addr; | |
ce9e2e1b | 1334 | int size; |
a66098da LB |
1335 | struct sk_buff *skb; |
1336 | struct ieee80211_tx_info *info; | |
1337 | u32 status; | |
1338 | ||
45eb400d LB |
1339 | tx = txq->head; |
1340 | tx_desc = txq->txd + tx; | |
a66098da LB |
1341 | |
1342 | status = le32_to_cpu(tx_desc->status); | |
1343 | ||
1344 | if (status & MWL8K_TXD_STATUS_FW_OWNED) { | |
1345 | if (!force) | |
1346 | break; | |
1347 | tx_desc->status &= | |
1348 | ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); | |
1349 | } | |
1350 | ||
45eb400d LB |
1351 | txq->head = (tx + 1) % MWL8K_TX_DESCS; |
1352 | BUG_ON(txq->stats.len == 0); | |
1353 | txq->stats.len--; | |
a66098da LB |
1354 | priv->pending_tx_pkts--; |
1355 | ||
1356 | addr = le32_to_cpu(tx_desc->pkt_phys_addr); | |
ce9e2e1b | 1357 | size = le16_to_cpu(tx_desc->pkt_len); |
45eb400d LB |
1358 | skb = txq->skb[tx]; |
1359 | txq->skb[tx] = NULL; | |
a66098da LB |
1360 | |
1361 | BUG_ON(skb == NULL); | |
1362 | pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); | |
1363 | ||
76266b2a | 1364 | mwl8k_remove_dma_header(skb); |
a66098da LB |
1365 | |
1366 | /* Mark descriptor as unused */ | |
1367 | tx_desc->pkt_phys_addr = 0; | |
1368 | tx_desc->pkt_len = 0; | |
1369 | ||
a66098da LB |
1370 | info = IEEE80211_SKB_CB(skb); |
1371 | ieee80211_tx_info_clear_status(info); | |
ce9e2e1b | 1372 | if (MWL8K_TXD_SUCCESS(status)) |
a66098da | 1373 | info->flags |= IEEE80211_TX_STAT_ACK; |
a66098da LB |
1374 | |
1375 | ieee80211_tx_status_irqsafe(hw, skb); | |
1376 | ||
618952a7 | 1377 | wake = 1; |
a66098da LB |
1378 | } |
1379 | ||
618952a7 | 1380 | if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex)) |
a66098da LB |
1381 | ieee80211_wake_queue(hw, index); |
1382 | } | |
1383 | ||
1384 | /* must be called only when the card's transmit is completely halted */ | |
1385 | static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) | |
1386 | { | |
1387 | struct mwl8k_priv *priv = hw->priv; | |
1388 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1389 | ||
1390 | mwl8k_txq_reclaim(hw, index, 1); | |
1391 | ||
45eb400d LB |
1392 | kfree(txq->skb); |
1393 | txq->skb = NULL; | |
a66098da LB |
1394 | |
1395 | pci_free_consistent(priv->pdev, | |
1396 | MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), | |
45eb400d LB |
1397 | txq->txd, txq->txd_dma); |
1398 | txq->txd = NULL; | |
a66098da LB |
1399 | } |
1400 | ||
1401 | static int | |
1402 | mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb) | |
1403 | { | |
1404 | struct mwl8k_priv *priv = hw->priv; | |
1405 | struct ieee80211_tx_info *tx_info; | |
23b33906 | 1406 | struct mwl8k_vif *mwl8k_vif; |
a66098da LB |
1407 | struct ieee80211_hdr *wh; |
1408 | struct mwl8k_tx_queue *txq; | |
1409 | struct mwl8k_tx_desc *tx; | |
a66098da | 1410 | dma_addr_t dma; |
23b33906 LB |
1411 | u32 txstatus; |
1412 | u8 txdatarate; | |
1413 | u16 qos; | |
a66098da | 1414 | |
23b33906 LB |
1415 | wh = (struct ieee80211_hdr *)skb->data; |
1416 | if (ieee80211_is_data_qos(wh->frame_control)) | |
1417 | qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); | |
1418 | else | |
1419 | qos = 0; | |
a66098da | 1420 | |
76266b2a | 1421 | mwl8k_add_dma_header(skb); |
23b33906 | 1422 | wh = &((struct mwl8k_dma_data *)skb->data)->wh; |
a66098da LB |
1423 | |
1424 | tx_info = IEEE80211_SKB_CB(skb); | |
1425 | mwl8k_vif = MWL8K_VIF(tx_info->control.vif); | |
a66098da LB |
1426 | |
1427 | if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
1428 | u16 seqno = mwl8k_vif->seqno; | |
23b33906 | 1429 | |
a66098da LB |
1430 | wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
1431 | wh->seq_ctrl |= cpu_to_le16(seqno << 4); | |
1432 | mwl8k_vif->seqno = seqno++ % 4096; | |
1433 | } | |
1434 | ||
23b33906 LB |
1435 | /* Setup firmware control bit fields for each frame type. */ |
1436 | txstatus = 0; | |
1437 | txdatarate = 0; | |
1438 | if (ieee80211_is_mgmt(wh->frame_control) || | |
1439 | ieee80211_is_ctl(wh->frame_control)) { | |
1440 | txdatarate = 0; | |
1441 | qos = mwl8k_qos_setbit_eosp(qos); | |
1442 | /* Set Queue size to unspecified */ | |
1443 | qos = mwl8k_qos_setbit_qlen(qos, 0xff); | |
1444 | } else if (ieee80211_is_data(wh->frame_control)) { | |
1445 | txdatarate = 1; | |
1446 | if (is_multicast_ether_addr(wh->addr1)) | |
1447 | txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; | |
1448 | ||
1449 | /* Send pkt in an aggregate if AMPDU frame. */ | |
1450 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) | |
1451 | qos = mwl8k_qos_setbit_ack(qos, | |
1452 | MWL8K_TXD_ACK_POLICY_BLOCKACK); | |
1453 | else | |
1454 | qos = mwl8k_qos_setbit_ack(qos, | |
1455 | MWL8K_TXD_ACK_POLICY_NORMAL); | |
1456 | ||
1457 | if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT) | |
1458 | qos = mwl8k_qos_setbit_amsdu(qos); | |
1459 | } | |
a66098da LB |
1460 | |
1461 | dma = pci_map_single(priv->pdev, skb->data, | |
1462 | skb->len, PCI_DMA_TODEVICE); | |
1463 | ||
1464 | if (pci_dma_mapping_error(priv->pdev, dma)) { | |
1465 | printk(KERN_DEBUG "%s: failed to dma map skb, " | |
c2c357ce | 1466 | "dropping TX frame.\n", wiphy_name(hw->wiphy)); |
23b33906 | 1467 | dev_kfree_skb(skb); |
a66098da LB |
1468 | return NETDEV_TX_OK; |
1469 | } | |
1470 | ||
23b33906 | 1471 | spin_lock_bh(&priv->tx_lock); |
a66098da | 1472 | |
23b33906 | 1473 | txq = priv->txq + index; |
a66098da | 1474 | |
45eb400d LB |
1475 | BUG_ON(txq->skb[txq->tail] != NULL); |
1476 | txq->skb[txq->tail] = skb; | |
a66098da | 1477 | |
45eb400d | 1478 | tx = txq->txd + txq->tail; |
23b33906 LB |
1479 | tx->data_rate = txdatarate; |
1480 | tx->tx_priority = index; | |
a66098da | 1481 | tx->qos_control = cpu_to_le16(qos); |
a66098da LB |
1482 | tx->pkt_phys_addr = cpu_to_le32(dma); |
1483 | tx->pkt_len = cpu_to_le16(skb->len); | |
23b33906 LB |
1484 | tx->rate_info = 0; |
1485 | tx->peer_id = mwl8k_vif->peer_id; | |
a66098da | 1486 | wmb(); |
23b33906 LB |
1487 | tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); |
1488 | ||
45eb400d LB |
1489 | txq->stats.count++; |
1490 | txq->stats.len++; | |
a66098da | 1491 | priv->pending_tx_pkts++; |
a66098da | 1492 | |
45eb400d LB |
1493 | txq->tail++; |
1494 | if (txq->tail == MWL8K_TX_DESCS) | |
1495 | txq->tail = 0; | |
23b33906 | 1496 | |
45eb400d | 1497 | if (txq->head == txq->tail) |
a66098da LB |
1498 | ieee80211_stop_queue(hw, index); |
1499 | ||
23b33906 | 1500 | mwl8k_tx_start(priv); |
a66098da LB |
1501 | |
1502 | spin_unlock_bh(&priv->tx_lock); | |
1503 | ||
1504 | return NETDEV_TX_OK; | |
1505 | } | |
1506 | ||
1507 | ||
618952a7 LB |
1508 | /* |
1509 | * Firmware access. | |
1510 | * | |
1511 | * We have the following requirements for issuing firmware commands: | |
1512 | * - Some commands require that the packet transmit path is idle when | |
1513 | * the command is issued. (For simplicity, we'll just quiesce the | |
1514 | * transmit path for every command.) | |
1515 | * - There are certain sequences of commands that need to be issued to | |
1516 | * the hardware sequentially, with no other intervening commands. | |
1517 | * | |
1518 | * This leads to an implementation of a "firmware lock" as a mutex that | |
1519 | * can be taken recursively, and which is taken by both the low-level | |
1520 | * command submission function (mwl8k_post_cmd) as well as any users of | |
1521 | * that function that require issuing of an atomic sequence of commands, | |
1522 | * and quiesces the transmit path whenever it's taken. | |
1523 | */ | |
1524 | static int mwl8k_fw_lock(struct ieee80211_hw *hw) | |
1525 | { | |
1526 | struct mwl8k_priv *priv = hw->priv; | |
1527 | ||
1528 | if (priv->fw_mutex_owner != current) { | |
1529 | int rc; | |
1530 | ||
1531 | mutex_lock(&priv->fw_mutex); | |
1532 | ieee80211_stop_queues(hw); | |
1533 | ||
1534 | rc = mwl8k_tx_wait_empty(hw); | |
1535 | if (rc) { | |
1536 | ieee80211_wake_queues(hw); | |
1537 | mutex_unlock(&priv->fw_mutex); | |
1538 | ||
1539 | return rc; | |
1540 | } | |
1541 | ||
1542 | priv->fw_mutex_owner = current; | |
1543 | } | |
1544 | ||
1545 | priv->fw_mutex_depth++; | |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
1550 | static void mwl8k_fw_unlock(struct ieee80211_hw *hw) | |
1551 | { | |
1552 | struct mwl8k_priv *priv = hw->priv; | |
1553 | ||
1554 | if (!--priv->fw_mutex_depth) { | |
1555 | ieee80211_wake_queues(hw); | |
1556 | priv->fw_mutex_owner = NULL; | |
1557 | mutex_unlock(&priv->fw_mutex); | |
1558 | } | |
1559 | } | |
1560 | ||
1561 | ||
a66098da LB |
1562 | /* |
1563 | * Command processing. | |
1564 | */ | |
1565 | ||
1566 | /* Timeout firmware commands after 2000ms */ | |
1567 | #define MWL8K_CMD_TIMEOUT_MS 2000 | |
1568 | ||
1569 | static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd) | |
1570 | { | |
1571 | DECLARE_COMPLETION_ONSTACK(cmd_wait); | |
1572 | struct mwl8k_priv *priv = hw->priv; | |
1573 | void __iomem *regs = priv->regs; | |
1574 | dma_addr_t dma_addr; | |
1575 | unsigned int dma_size; | |
1576 | int rc; | |
a66098da LB |
1577 | unsigned long timeout = 0; |
1578 | u8 buf[32]; | |
1579 | ||
c2c357ce | 1580 | cmd->result = 0xffff; |
a66098da LB |
1581 | dma_size = le16_to_cpu(cmd->length); |
1582 | dma_addr = pci_map_single(priv->pdev, cmd, dma_size, | |
1583 | PCI_DMA_BIDIRECTIONAL); | |
1584 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
1585 | return -ENOMEM; | |
1586 | ||
618952a7 | 1587 | rc = mwl8k_fw_lock(hw); |
39a1e42e LB |
1588 | if (rc) { |
1589 | pci_unmap_single(priv->pdev, dma_addr, dma_size, | |
1590 | PCI_DMA_BIDIRECTIONAL); | |
618952a7 | 1591 | return rc; |
39a1e42e | 1592 | } |
a66098da | 1593 | |
a66098da LB |
1594 | priv->hostcmd_wait = &cmd_wait; |
1595 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
1596 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
1597 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1598 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1599 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
a66098da LB |
1600 | |
1601 | timeout = wait_for_completion_timeout(&cmd_wait, | |
1602 | msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS)); | |
1603 | ||
618952a7 LB |
1604 | priv->hostcmd_wait = NULL; |
1605 | ||
1606 | mwl8k_fw_unlock(hw); | |
1607 | ||
37055bd4 LB |
1608 | pci_unmap_single(priv->pdev, dma_addr, dma_size, |
1609 | PCI_DMA_BIDIRECTIONAL); | |
1610 | ||
a66098da | 1611 | if (!timeout) { |
a66098da | 1612 | printk(KERN_ERR "%s: Command %s timeout after %u ms\n", |
c2c357ce | 1613 | wiphy_name(hw->wiphy), |
a66098da LB |
1614 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
1615 | MWL8K_CMD_TIMEOUT_MS); | |
1616 | rc = -ETIMEDOUT; | |
1617 | } else { | |
ce9e2e1b | 1618 | rc = cmd->result ? -EINVAL : 0; |
a66098da LB |
1619 | if (rc) |
1620 | printk(KERN_ERR "%s: Command %s error 0x%x\n", | |
c2c357ce | 1621 | wiphy_name(hw->wiphy), |
a66098da | 1622 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
76c962a2 | 1623 | le16_to_cpu(cmd->result)); |
a66098da LB |
1624 | } |
1625 | ||
a66098da LB |
1626 | return rc; |
1627 | } | |
1628 | ||
1629 | /* | |
04b147b1 | 1630 | * CMD_GET_HW_SPEC (STA version). |
a66098da | 1631 | */ |
04b147b1 | 1632 | struct mwl8k_cmd_get_hw_spec_sta { |
a66098da LB |
1633 | struct mwl8k_cmd_pkt header; |
1634 | __u8 hw_rev; | |
1635 | __u8 host_interface; | |
1636 | __le16 num_mcaddrs; | |
d89173f2 | 1637 | __u8 perm_addr[ETH_ALEN]; |
a66098da LB |
1638 | __le16 region_code; |
1639 | __le32 fw_rev; | |
1640 | __le32 ps_cookie; | |
1641 | __le32 caps; | |
1642 | __u8 mcs_bitmap[16]; | |
1643 | __le32 rx_queue_ptr; | |
1644 | __le32 num_tx_queues; | |
1645 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1646 | __le32 caps2; | |
1647 | __le32 num_tx_desc_per_queue; | |
45eb400d | 1648 | __le32 total_rxd; |
a66098da LB |
1649 | } __attribute__((packed)); |
1650 | ||
04b147b1 | 1651 | static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw) |
a66098da LB |
1652 | { |
1653 | struct mwl8k_priv *priv = hw->priv; | |
04b147b1 | 1654 | struct mwl8k_cmd_get_hw_spec_sta *cmd; |
a66098da LB |
1655 | int rc; |
1656 | int i; | |
1657 | ||
1658 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1659 | if (cmd == NULL) | |
1660 | return -ENOMEM; | |
1661 | ||
1662 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1663 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1664 | ||
1665 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1666 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
45eb400d | 1667 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); |
4ff6432e | 1668 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); |
a66098da | 1669 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
45eb400d | 1670 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); |
4ff6432e | 1671 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); |
45eb400d | 1672 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); |
a66098da LB |
1673 | |
1674 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1675 | ||
1676 | if (!rc) { | |
1677 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1678 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
4ff6432e | 1679 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); |
a66098da | 1680 | priv->hw_rev = cmd->hw_rev; |
a66098da LB |
1681 | } |
1682 | ||
1683 | kfree(cmd); | |
1684 | return rc; | |
1685 | } | |
1686 | ||
42fba21d LB |
1687 | /* |
1688 | * CMD_GET_HW_SPEC (AP version). | |
1689 | */ | |
1690 | struct mwl8k_cmd_get_hw_spec_ap { | |
1691 | struct mwl8k_cmd_pkt header; | |
1692 | __u8 hw_rev; | |
1693 | __u8 host_interface; | |
1694 | __le16 num_wcb; | |
1695 | __le16 num_mcaddrs; | |
1696 | __u8 perm_addr[ETH_ALEN]; | |
1697 | __le16 region_code; | |
1698 | __le16 num_antenna; | |
1699 | __le32 fw_rev; | |
1700 | __le32 wcbbase0; | |
1701 | __le32 rxwrptr; | |
1702 | __le32 rxrdptr; | |
1703 | __le32 ps_cookie; | |
1704 | __le32 wcbbase1; | |
1705 | __le32 wcbbase2; | |
1706 | __le32 wcbbase3; | |
1707 | } __attribute__((packed)); | |
1708 | ||
1709 | static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) | |
1710 | { | |
1711 | struct mwl8k_priv *priv = hw->priv; | |
1712 | struct mwl8k_cmd_get_hw_spec_ap *cmd; | |
1713 | int rc; | |
1714 | ||
1715 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1716 | if (cmd == NULL) | |
1717 | return -ENOMEM; | |
1718 | ||
1719 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1720 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1721 | ||
1722 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1723 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1724 | ||
1725 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1726 | ||
1727 | if (!rc) { | |
1728 | int off; | |
1729 | ||
1730 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1731 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
1732 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); | |
1733 | priv->hw_rev = cmd->hw_rev; | |
1734 | ||
1735 | off = le32_to_cpu(cmd->wcbbase0) & 0xffff; | |
1736 | iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off); | |
1737 | ||
1738 | off = le32_to_cpu(cmd->rxwrptr) & 0xffff; | |
1739 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1740 | ||
1741 | off = le32_to_cpu(cmd->rxrdptr) & 0xffff; | |
1742 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1743 | ||
1744 | off = le32_to_cpu(cmd->wcbbase1) & 0xffff; | |
1745 | iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off); | |
1746 | ||
1747 | off = le32_to_cpu(cmd->wcbbase2) & 0xffff; | |
1748 | iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off); | |
1749 | ||
1750 | off = le32_to_cpu(cmd->wcbbase3) & 0xffff; | |
1751 | iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off); | |
1752 | } | |
1753 | ||
1754 | kfree(cmd); | |
1755 | return rc; | |
1756 | } | |
1757 | ||
1758 | /* | |
1759 | * CMD_SET_HW_SPEC. | |
1760 | */ | |
1761 | struct mwl8k_cmd_set_hw_spec { | |
1762 | struct mwl8k_cmd_pkt header; | |
1763 | __u8 hw_rev; | |
1764 | __u8 host_interface; | |
1765 | __le16 num_mcaddrs; | |
1766 | __u8 perm_addr[ETH_ALEN]; | |
1767 | __le16 region_code; | |
1768 | __le32 fw_rev; | |
1769 | __le32 ps_cookie; | |
1770 | __le32 caps; | |
1771 | __le32 rx_queue_ptr; | |
1772 | __le32 num_tx_queues; | |
1773 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1774 | __le32 flags; | |
1775 | __le32 num_tx_desc_per_queue; | |
1776 | __le32 total_rxd; | |
1777 | } __attribute__((packed)); | |
1778 | ||
1779 | #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080 | |
1780 | ||
1781 | static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw) | |
1782 | { | |
1783 | struct mwl8k_priv *priv = hw->priv; | |
1784 | struct mwl8k_cmd_set_hw_spec *cmd; | |
1785 | int rc; | |
1786 | int i; | |
1787 | ||
1788 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1789 | if (cmd == NULL) | |
1790 | return -ENOMEM; | |
1791 | ||
1792 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC); | |
1793 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1794 | ||
1795 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1796 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); | |
1797 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); | |
1798 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
1799 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); | |
1800 | cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT); | |
1801 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); | |
1802 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); | |
1803 | ||
1804 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1805 | kfree(cmd); | |
1806 | ||
1807 | return rc; | |
1808 | } | |
1809 | ||
a66098da LB |
1810 | /* |
1811 | * CMD_MAC_MULTICAST_ADR. | |
1812 | */ | |
1813 | struct mwl8k_cmd_mac_multicast_adr { | |
1814 | struct mwl8k_cmd_pkt header; | |
1815 | __le16 action; | |
1816 | __le16 numaddr; | |
ce9e2e1b | 1817 | __u8 addr[0][ETH_ALEN]; |
a66098da LB |
1818 | }; |
1819 | ||
d5e30845 LB |
1820 | #define MWL8K_ENABLE_RX_DIRECTED 0x0001 |
1821 | #define MWL8K_ENABLE_RX_MULTICAST 0x0002 | |
1822 | #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004 | |
1823 | #define MWL8K_ENABLE_RX_BROADCAST 0x0008 | |
ce9e2e1b | 1824 | |
e81cd2d6 | 1825 | static struct mwl8k_cmd_pkt * |
447ced07 | 1826 | __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti, |
e81cd2d6 | 1827 | int mc_count, struct dev_addr_list *mclist) |
a66098da | 1828 | { |
e81cd2d6 | 1829 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1830 | struct mwl8k_cmd_mac_multicast_adr *cmd; |
e81cd2d6 | 1831 | int size; |
e81cd2d6 | 1832 | |
447ced07 | 1833 | if (allmulti || mc_count > priv->num_mcaddrs) { |
d5e30845 LB |
1834 | allmulti = 1; |
1835 | mc_count = 0; | |
1836 | } | |
e81cd2d6 LB |
1837 | |
1838 | size = sizeof(*cmd) + mc_count * ETH_ALEN; | |
ce9e2e1b | 1839 | |
e81cd2d6 | 1840 | cmd = kzalloc(size, GFP_ATOMIC); |
a66098da | 1841 | if (cmd == NULL) |
e81cd2d6 | 1842 | return NULL; |
a66098da LB |
1843 | |
1844 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); | |
1845 | cmd->header.length = cpu_to_le16(size); | |
d5e30845 LB |
1846 | cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED | |
1847 | MWL8K_ENABLE_RX_BROADCAST); | |
1848 | ||
1849 | if (allmulti) { | |
1850 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST); | |
1851 | } else if (mc_count) { | |
1852 | int i; | |
1853 | ||
1854 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); | |
1855 | cmd->numaddr = cpu_to_le16(mc_count); | |
1856 | for (i = 0; i < mc_count && mclist; i++) { | |
1857 | if (mclist->da_addrlen != ETH_ALEN) { | |
1858 | kfree(cmd); | |
1859 | return NULL; | |
1860 | } | |
1861 | memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN); | |
1862 | mclist = mclist->next; | |
a66098da | 1863 | } |
a66098da LB |
1864 | } |
1865 | ||
e81cd2d6 | 1866 | return &cmd->header; |
a66098da LB |
1867 | } |
1868 | ||
1869 | /* | |
1870 | * CMD_802_11_GET_STAT. | |
1871 | */ | |
1872 | struct mwl8k_cmd_802_11_get_stat { | |
1873 | struct mwl8k_cmd_pkt header; | |
a66098da LB |
1874 | __le32 stats[64]; |
1875 | } __attribute__((packed)); | |
1876 | ||
1877 | #define MWL8K_STAT_ACK_FAILURE 9 | |
1878 | #define MWL8K_STAT_RTS_FAILURE 12 | |
1879 | #define MWL8K_STAT_FCS_ERROR 24 | |
1880 | #define MWL8K_STAT_RTS_SUCCESS 11 | |
1881 | ||
1882 | static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw, | |
1883 | struct ieee80211_low_level_stats *stats) | |
1884 | { | |
1885 | struct mwl8k_cmd_802_11_get_stat *cmd; | |
1886 | int rc; | |
1887 | ||
1888 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1889 | if (cmd == NULL) | |
1890 | return -ENOMEM; | |
1891 | ||
1892 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); | |
1893 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
1894 | |
1895 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1896 | if (!rc) { | |
1897 | stats->dot11ACKFailureCount = | |
1898 | le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]); | |
1899 | stats->dot11RTSFailureCount = | |
1900 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]); | |
1901 | stats->dot11FCSErrorCount = | |
1902 | le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]); | |
1903 | stats->dot11RTSSuccessCount = | |
1904 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]); | |
1905 | } | |
1906 | kfree(cmd); | |
1907 | ||
1908 | return rc; | |
1909 | } | |
1910 | ||
1911 | /* | |
1912 | * CMD_802_11_RADIO_CONTROL. | |
1913 | */ | |
1914 | struct mwl8k_cmd_802_11_radio_control { | |
1915 | struct mwl8k_cmd_pkt header; | |
1916 | __le16 action; | |
1917 | __le16 control; | |
1918 | __le16 radio_on; | |
1919 | } __attribute__((packed)); | |
1920 | ||
c46563b7 LB |
1921 | static int |
1922 | mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force) | |
a66098da LB |
1923 | { |
1924 | struct mwl8k_priv *priv = hw->priv; | |
1925 | struct mwl8k_cmd_802_11_radio_control *cmd; | |
1926 | int rc; | |
1927 | ||
c46563b7 | 1928 | if (enable == priv->radio_on && !force) |
a66098da LB |
1929 | return 0; |
1930 | ||
a66098da LB |
1931 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
1932 | if (cmd == NULL) | |
1933 | return -ENOMEM; | |
1934 | ||
1935 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL); | |
1936 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1937 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
68ce3884 | 1938 | cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1); |
a66098da LB |
1939 | cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); |
1940 | ||
1941 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1942 | kfree(cmd); | |
1943 | ||
1944 | if (!rc) | |
c46563b7 | 1945 | priv->radio_on = enable; |
a66098da LB |
1946 | |
1947 | return rc; | |
1948 | } | |
1949 | ||
c46563b7 LB |
1950 | static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw) |
1951 | { | |
1952 | return mwl8k_cmd_802_11_radio_control(hw, 0, 0); | |
1953 | } | |
1954 | ||
1955 | static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw) | |
1956 | { | |
1957 | return mwl8k_cmd_802_11_radio_control(hw, 1, 0); | |
1958 | } | |
1959 | ||
a66098da LB |
1960 | static int |
1961 | mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble) | |
1962 | { | |
1963 | struct mwl8k_priv *priv; | |
1964 | ||
1965 | if (hw == NULL || hw->priv == NULL) | |
1966 | return -EINVAL; | |
1967 | priv = hw->priv; | |
1968 | ||
68ce3884 | 1969 | priv->radio_short_preamble = short_preamble; |
a66098da | 1970 | |
c46563b7 | 1971 | return mwl8k_cmd_802_11_radio_control(hw, 1, 1); |
a66098da LB |
1972 | } |
1973 | ||
1974 | /* | |
1975 | * CMD_802_11_RF_TX_POWER. | |
1976 | */ | |
1977 | #define MWL8K_TX_POWER_LEVEL_TOTAL 8 | |
1978 | ||
1979 | struct mwl8k_cmd_802_11_rf_tx_power { | |
1980 | struct mwl8k_cmd_pkt header; | |
1981 | __le16 action; | |
1982 | __le16 support_level; | |
1983 | __le16 current_level; | |
1984 | __le16 reserved; | |
1985 | __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL]; | |
1986 | } __attribute__((packed)); | |
1987 | ||
1988 | static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm) | |
1989 | { | |
1990 | struct mwl8k_cmd_802_11_rf_tx_power *cmd; | |
1991 | int rc; | |
1992 | ||
1993 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1994 | if (cmd == NULL) | |
1995 | return -ENOMEM; | |
1996 | ||
1997 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER); | |
1998 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1999 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2000 | cmd->support_level = cpu_to_le16(dBm); | |
2001 | ||
2002 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2003 | kfree(cmd); | |
2004 | ||
2005 | return rc; | |
2006 | } | |
2007 | ||
08b06347 LB |
2008 | /* |
2009 | * CMD_RF_ANTENNA. | |
2010 | */ | |
2011 | struct mwl8k_cmd_rf_antenna { | |
2012 | struct mwl8k_cmd_pkt header; | |
2013 | __le16 antenna; | |
2014 | __le16 mode; | |
2015 | } __attribute__((packed)); | |
2016 | ||
2017 | #define MWL8K_RF_ANTENNA_RX 1 | |
2018 | #define MWL8K_RF_ANTENNA_TX 2 | |
2019 | ||
2020 | static int | |
2021 | mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) | |
2022 | { | |
2023 | struct mwl8k_cmd_rf_antenna *cmd; | |
2024 | int rc; | |
2025 | ||
2026 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2027 | if (cmd == NULL) | |
2028 | return -ENOMEM; | |
2029 | ||
2030 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA); | |
2031 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2032 | cmd->antenna = cpu_to_le16(antenna); | |
2033 | cmd->mode = cpu_to_le16(mask); | |
2034 | ||
2035 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2036 | kfree(cmd); | |
2037 | ||
2038 | return rc; | |
2039 | } | |
2040 | ||
a66098da LB |
2041 | /* |
2042 | * CMD_SET_PRE_SCAN. | |
2043 | */ | |
2044 | struct mwl8k_cmd_set_pre_scan { | |
2045 | struct mwl8k_cmd_pkt header; | |
2046 | } __attribute__((packed)); | |
2047 | ||
2048 | static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw) | |
2049 | { | |
2050 | struct mwl8k_cmd_set_pre_scan *cmd; | |
2051 | int rc; | |
2052 | ||
2053 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2054 | if (cmd == NULL) | |
2055 | return -ENOMEM; | |
2056 | ||
2057 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN); | |
2058 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2059 | ||
2060 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2061 | kfree(cmd); | |
2062 | ||
2063 | return rc; | |
2064 | } | |
2065 | ||
2066 | /* | |
2067 | * CMD_SET_POST_SCAN. | |
2068 | */ | |
2069 | struct mwl8k_cmd_set_post_scan { | |
2070 | struct mwl8k_cmd_pkt header; | |
2071 | __le32 isibss; | |
d89173f2 | 2072 | __u8 bssid[ETH_ALEN]; |
a66098da LB |
2073 | } __attribute__((packed)); |
2074 | ||
2075 | static int | |
ce9e2e1b | 2076 | mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac) |
a66098da LB |
2077 | { |
2078 | struct mwl8k_cmd_set_post_scan *cmd; | |
2079 | int rc; | |
2080 | ||
2081 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2082 | if (cmd == NULL) | |
2083 | return -ENOMEM; | |
2084 | ||
2085 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN); | |
2086 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2087 | cmd->isibss = 0; | |
d89173f2 | 2088 | memcpy(cmd->bssid, mac, ETH_ALEN); |
a66098da LB |
2089 | |
2090 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2091 | kfree(cmd); | |
2092 | ||
2093 | return rc; | |
2094 | } | |
2095 | ||
2096 | /* | |
2097 | * CMD_SET_RF_CHANNEL. | |
2098 | */ | |
2099 | struct mwl8k_cmd_set_rf_channel { | |
2100 | struct mwl8k_cmd_pkt header; | |
2101 | __le16 action; | |
2102 | __u8 current_channel; | |
2103 | __le32 channel_flags; | |
2104 | } __attribute__((packed)); | |
2105 | ||
2106 | static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw, | |
2107 | struct ieee80211_channel *channel) | |
2108 | { | |
2109 | struct mwl8k_cmd_set_rf_channel *cmd; | |
2110 | int rc; | |
2111 | ||
2112 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2113 | if (cmd == NULL) | |
2114 | return -ENOMEM; | |
2115 | ||
2116 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL); | |
2117 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2118 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2119 | cmd->current_channel = channel->hw_value; | |
2120 | if (channel->band == IEEE80211_BAND_2GHZ) | |
2121 | cmd->channel_flags = cpu_to_le32(0x00000081); | |
2122 | else | |
2123 | cmd->channel_flags = cpu_to_le32(0x00000000); | |
2124 | ||
2125 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2126 | kfree(cmd); | |
2127 | ||
2128 | return rc; | |
2129 | } | |
2130 | ||
2131 | /* | |
2132 | * CMD_SET_SLOT. | |
2133 | */ | |
2134 | struct mwl8k_cmd_set_slot { | |
2135 | struct mwl8k_cmd_pkt header; | |
2136 | __le16 action; | |
2137 | __u8 short_slot; | |
2138 | } __attribute__((packed)); | |
2139 | ||
5539bb51 | 2140 | static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time) |
a66098da LB |
2141 | { |
2142 | struct mwl8k_cmd_set_slot *cmd; | |
2143 | int rc; | |
2144 | ||
2145 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2146 | if (cmd == NULL) | |
2147 | return -ENOMEM; | |
2148 | ||
2149 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT); | |
2150 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2151 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
5539bb51 | 2152 | cmd->short_slot = short_slot_time; |
a66098da LB |
2153 | |
2154 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2155 | kfree(cmd); | |
2156 | ||
2157 | return rc; | |
2158 | } | |
2159 | ||
2160 | /* | |
2161 | * CMD_MIMO_CONFIG. | |
2162 | */ | |
2163 | struct mwl8k_cmd_mimo_config { | |
2164 | struct mwl8k_cmd_pkt header; | |
2165 | __le32 action; | |
2166 | __u8 rx_antenna_map; | |
2167 | __u8 tx_antenna_map; | |
2168 | } __attribute__((packed)); | |
2169 | ||
2170 | static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx) | |
2171 | { | |
2172 | struct mwl8k_cmd_mimo_config *cmd; | |
2173 | int rc; | |
2174 | ||
2175 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2176 | if (cmd == NULL) | |
2177 | return -ENOMEM; | |
2178 | ||
2179 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG); | |
2180 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2181 | cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET); | |
2182 | cmd->rx_antenna_map = rx; | |
2183 | cmd->tx_antenna_map = tx; | |
2184 | ||
2185 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2186 | kfree(cmd); | |
2187 | ||
2188 | return rc; | |
2189 | } | |
2190 | ||
2191 | /* | |
2192 | * CMD_ENABLE_SNIFFER. | |
2193 | */ | |
2194 | struct mwl8k_cmd_enable_sniffer { | |
2195 | struct mwl8k_cmd_pkt header; | |
2196 | __le32 action; | |
2197 | } __attribute__((packed)); | |
2198 | ||
2199 | static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable) | |
2200 | { | |
2201 | struct mwl8k_cmd_enable_sniffer *cmd; | |
2202 | int rc; | |
2203 | ||
2204 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2205 | if (cmd == NULL) | |
2206 | return -ENOMEM; | |
2207 | ||
2208 | cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER); | |
2209 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
ce9e2e1b | 2210 | cmd->action = cpu_to_le32(!!enable); |
a66098da LB |
2211 | |
2212 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2213 | kfree(cmd); | |
2214 | ||
2215 | return rc; | |
2216 | } | |
2217 | ||
32060e1b LB |
2218 | /* |
2219 | * CMD_SET_MAC_ADDR. | |
2220 | */ | |
2221 | struct mwl8k_cmd_set_mac_addr { | |
2222 | struct mwl8k_cmd_pkt header; | |
259a8e7d LB |
2223 | union { |
2224 | struct { | |
2225 | __le16 mac_type; | |
2226 | __u8 mac_addr[ETH_ALEN]; | |
2227 | } mbss; | |
2228 | __u8 mac_addr[ETH_ALEN]; | |
2229 | }; | |
32060e1b LB |
2230 | } __attribute__((packed)); |
2231 | ||
2232 | static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac) | |
2233 | { | |
259a8e7d | 2234 | struct mwl8k_priv *priv = hw->priv; |
32060e1b LB |
2235 | struct mwl8k_cmd_set_mac_addr *cmd; |
2236 | int rc; | |
2237 | ||
2238 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2239 | if (cmd == NULL) | |
2240 | return -ENOMEM; | |
2241 | ||
2242 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR); | |
2243 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
259a8e7d LB |
2244 | if (priv->ap_fw) { |
2245 | cmd->mbss.mac_type = 0; | |
2246 | memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN); | |
2247 | } else { | |
2248 | memcpy(cmd->mac_addr, mac, ETH_ALEN); | |
2249 | } | |
32060e1b LB |
2250 | |
2251 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2252 | kfree(cmd); | |
2253 | ||
2254 | return rc; | |
2255 | } | |
2256 | ||
2257 | ||
a66098da | 2258 | /* |
ce9e2e1b | 2259 | * CMD_SET_RATEADAPT_MODE. |
a66098da LB |
2260 | */ |
2261 | struct mwl8k_cmd_set_rate_adapt_mode { | |
2262 | struct mwl8k_cmd_pkt header; | |
2263 | __le16 action; | |
2264 | __le16 mode; | |
2265 | } __attribute__((packed)); | |
2266 | ||
2267 | static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode) | |
2268 | { | |
2269 | struct mwl8k_cmd_set_rate_adapt_mode *cmd; | |
2270 | int rc; | |
2271 | ||
2272 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2273 | if (cmd == NULL) | |
2274 | return -ENOMEM; | |
2275 | ||
2276 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE); | |
2277 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2278 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2279 | cmd->mode = cpu_to_le16(mode); | |
2280 | ||
2281 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2282 | kfree(cmd); | |
2283 | ||
2284 | return rc; | |
2285 | } | |
2286 | ||
2287 | /* | |
2288 | * CMD_SET_WMM_MODE. | |
2289 | */ | |
2290 | struct mwl8k_cmd_set_wmm { | |
2291 | struct mwl8k_cmd_pkt header; | |
2292 | __le16 action; | |
2293 | } __attribute__((packed)); | |
2294 | ||
2295 | static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable) | |
2296 | { | |
2297 | struct mwl8k_priv *priv = hw->priv; | |
2298 | struct mwl8k_cmd_set_wmm *cmd; | |
2299 | int rc; | |
2300 | ||
2301 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2302 | if (cmd == NULL) | |
2303 | return -ENOMEM; | |
2304 | ||
2305 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE); | |
2306 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
0439b1f5 | 2307 | cmd->action = cpu_to_le16(!!enable); |
a66098da LB |
2308 | |
2309 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2310 | kfree(cmd); | |
2311 | ||
2312 | if (!rc) | |
0439b1f5 | 2313 | priv->wmm_enabled = enable; |
a66098da LB |
2314 | |
2315 | return rc; | |
2316 | } | |
2317 | ||
2318 | /* | |
2319 | * CMD_SET_RTS_THRESHOLD. | |
2320 | */ | |
2321 | struct mwl8k_cmd_rts_threshold { | |
2322 | struct mwl8k_cmd_pkt header; | |
2323 | __le16 action; | |
2324 | __le16 threshold; | |
2325 | } __attribute__((packed)); | |
2326 | ||
2327 | static int mwl8k_rts_threshold(struct ieee80211_hw *hw, | |
733d3067 | 2328 | u16 action, u16 threshold) |
a66098da LB |
2329 | { |
2330 | struct mwl8k_cmd_rts_threshold *cmd; | |
2331 | int rc; | |
2332 | ||
2333 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2334 | if (cmd == NULL) | |
2335 | return -ENOMEM; | |
2336 | ||
2337 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD); | |
2338 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2339 | cmd->action = cpu_to_le16(action); | |
733d3067 | 2340 | cmd->threshold = cpu_to_le16(threshold); |
a66098da LB |
2341 | |
2342 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2343 | kfree(cmd); | |
2344 | ||
2345 | return rc; | |
2346 | } | |
2347 | ||
2348 | /* | |
2349 | * CMD_SET_EDCA_PARAMS. | |
2350 | */ | |
2351 | struct mwl8k_cmd_set_edca_params { | |
2352 | struct mwl8k_cmd_pkt header; | |
2353 | ||
2354 | /* See MWL8K_SET_EDCA_XXX below */ | |
2355 | __le16 action; | |
2356 | ||
2357 | /* TX opportunity in units of 32 us */ | |
2358 | __le16 txop; | |
2359 | ||
2e484c89 LB |
2360 | union { |
2361 | struct { | |
2362 | /* Log exponent of max contention period: 0...15 */ | |
2363 | __le32 log_cw_max; | |
2364 | ||
2365 | /* Log exponent of min contention period: 0...15 */ | |
2366 | __le32 log_cw_min; | |
2367 | ||
2368 | /* Adaptive interframe spacing in units of 32us */ | |
2369 | __u8 aifs; | |
2370 | ||
2371 | /* TX queue to configure */ | |
2372 | __u8 txq; | |
2373 | } ap; | |
2374 | struct { | |
2375 | /* Log exponent of max contention period: 0...15 */ | |
2376 | __u8 log_cw_max; | |
a66098da | 2377 | |
2e484c89 LB |
2378 | /* Log exponent of min contention period: 0...15 */ |
2379 | __u8 log_cw_min; | |
a66098da | 2380 | |
2e484c89 LB |
2381 | /* Adaptive interframe spacing in units of 32us */ |
2382 | __u8 aifs; | |
a66098da | 2383 | |
2e484c89 LB |
2384 | /* TX queue to configure */ |
2385 | __u8 txq; | |
2386 | } sta; | |
2387 | }; | |
a66098da LB |
2388 | } __attribute__((packed)); |
2389 | ||
a66098da LB |
2390 | #define MWL8K_SET_EDCA_CW 0x01 |
2391 | #define MWL8K_SET_EDCA_TXOP 0x02 | |
2392 | #define MWL8K_SET_EDCA_AIFS 0x04 | |
2393 | ||
2394 | #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \ | |
2395 | MWL8K_SET_EDCA_TXOP | \ | |
2396 | MWL8K_SET_EDCA_AIFS) | |
2397 | ||
2398 | static int | |
2399 | mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum, | |
2400 | __u16 cw_min, __u16 cw_max, | |
2401 | __u8 aifs, __u16 txop) | |
2402 | { | |
2e484c89 | 2403 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 2404 | struct mwl8k_cmd_set_edca_params *cmd; |
a66098da LB |
2405 | int rc; |
2406 | ||
2407 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2408 | if (cmd == NULL) | |
2409 | return -ENOMEM; | |
2410 | ||
22995b24 LB |
2411 | /* |
2412 | * Queues 0 (BE) and 1 (BK) are swapped in hardware for | |
2413 | * this call. | |
2414 | */ | |
2415 | qnum ^= !(qnum >> 1); | |
2416 | ||
a66098da LB |
2417 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); |
2418 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
2419 | cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); |
2420 | cmd->txop = cpu_to_le16(txop); | |
2e484c89 LB |
2421 | if (priv->ap_fw) { |
2422 | cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1)); | |
2423 | cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1)); | |
2424 | cmd->ap.aifs = aifs; | |
2425 | cmd->ap.txq = qnum; | |
2426 | } else { | |
2427 | cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1); | |
2428 | cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1); | |
2429 | cmd->sta.aifs = aifs; | |
2430 | cmd->sta.txq = qnum; | |
2431 | } | |
a66098da LB |
2432 | |
2433 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2434 | kfree(cmd); | |
2435 | ||
2436 | return rc; | |
2437 | } | |
2438 | ||
2439 | /* | |
2440 | * CMD_FINALIZE_JOIN. | |
2441 | */ | |
2442 | ||
2443 | /* FJ beacon buffer size is compiled into the firmware. */ | |
2444 | #define MWL8K_FJ_BEACON_MAXLEN 128 | |
2445 | ||
2446 | struct mwl8k_cmd_finalize_join { | |
2447 | struct mwl8k_cmd_pkt header; | |
2448 | __le32 sleep_interval; /* Number of beacon periods to sleep */ | |
2449 | __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN]; | |
2450 | } __attribute__((packed)); | |
2451 | ||
2452 | static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame, | |
2453 | __u16 framelen, __u16 dtim) | |
2454 | { | |
2455 | struct mwl8k_cmd_finalize_join *cmd; | |
2456 | struct ieee80211_mgmt *payload = frame; | |
2457 | u16 hdrlen; | |
2458 | u32 payload_len; | |
2459 | int rc; | |
2460 | ||
2461 | if (frame == NULL) | |
2462 | return -EINVAL; | |
2463 | ||
2464 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2465 | if (cmd == NULL) | |
2466 | return -ENOMEM; | |
2467 | ||
2468 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN); | |
2469 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
ce9e2e1b | 2470 | cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1); |
a66098da LB |
2471 | |
2472 | hdrlen = ieee80211_hdrlen(payload->frame_control); | |
2473 | ||
2474 | payload_len = framelen > hdrlen ? framelen - hdrlen : 0; | |
2475 | ||
2476 | /* XXX TBD Might just have to abort and return an error */ | |
2477 | if (payload_len > MWL8K_FJ_BEACON_MAXLEN) | |
2478 | printk(KERN_ERR "%s(): WARNING: Incomplete beacon " | |
c2c357ce LB |
2479 | "sent to firmware. Sz=%u MAX=%u\n", __func__, |
2480 | payload_len, MWL8K_FJ_BEACON_MAXLEN); | |
a66098da | 2481 | |
ce9e2e1b LB |
2482 | if (payload_len > MWL8K_FJ_BEACON_MAXLEN) |
2483 | payload_len = MWL8K_FJ_BEACON_MAXLEN; | |
a66098da LB |
2484 | |
2485 | if (payload && payload_len) | |
2486 | memcpy(cmd->beacon_data, &payload->u.beacon, payload_len); | |
2487 | ||
2488 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2489 | kfree(cmd); | |
2490 | return rc; | |
2491 | } | |
2492 | ||
2493 | /* | |
2494 | * CMD_UPDATE_STADB. | |
2495 | */ | |
2496 | struct mwl8k_cmd_update_sta_db { | |
2497 | struct mwl8k_cmd_pkt header; | |
2498 | ||
2499 | /* See STADB_ACTION_TYPE */ | |
2500 | __le32 action; | |
2501 | ||
2502 | /* Peer MAC address */ | |
d89173f2 | 2503 | __u8 peer_addr[ETH_ALEN]; |
a66098da LB |
2504 | |
2505 | __le32 reserved; | |
2506 | ||
2507 | /* Peer info - valid during add/update. */ | |
2508 | struct peer_capability_info peer_info; | |
2509 | } __attribute__((packed)); | |
2510 | ||
2511 | static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw, | |
2512 | struct ieee80211_vif *vif, __u32 action) | |
2513 | { | |
2514 | struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); | |
2515 | struct ieee80211_bss_conf *info = &mv_vif->bss_info; | |
2516 | struct mwl8k_cmd_update_sta_db *cmd; | |
2517 | struct peer_capability_info *peer_info; | |
2518 | struct ieee80211_rate *bitrates = mv_vif->legacy_rates; | |
a66098da LB |
2519 | int rc; |
2520 | __u8 count, *rates; | |
2521 | ||
2522 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2523 | if (cmd == NULL) | |
2524 | return -ENOMEM; | |
2525 | ||
2526 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
2527 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2528 | ||
2529 | cmd->action = cpu_to_le32(action); | |
2530 | peer_info = &cmd->peer_info; | |
d89173f2 | 2531 | memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN); |
a66098da LB |
2532 | |
2533 | switch (action) { | |
2534 | case MWL8K_STA_DB_ADD_ENTRY: | |
2535 | case MWL8K_STA_DB_MODIFY_ENTRY: | |
2536 | /* Build peer_info block */ | |
2537 | peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT; | |
2538 | peer_info->basic_caps = cpu_to_le16(info->assoc_capability); | |
2539 | peer_info->interop = 1; | |
2540 | peer_info->amsdu_enabled = 0; | |
2541 | ||
2542 | rates = peer_info->legacy_rates; | |
ce9e2e1b | 2543 | for (count = 0; count < mv_vif->legacy_nrates; count++) |
a66098da LB |
2544 | rates[count] = bitrates[count].hw_value; |
2545 | ||
2546 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2547 | if (rc == 0) | |
2548 | mv_vif->peer_id = peer_info->station_id; | |
2549 | ||
2550 | break; | |
2551 | ||
2552 | case MWL8K_STA_DB_DEL_ENTRY: | |
2553 | case MWL8K_STA_DB_FLUSH: | |
2554 | default: | |
2555 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2556 | if (rc == 0) | |
2557 | mv_vif->peer_id = 0; | |
2558 | break; | |
2559 | } | |
2560 | kfree(cmd); | |
2561 | ||
2562 | return rc; | |
2563 | } | |
2564 | ||
2565 | /* | |
2566 | * CMD_SET_AID. | |
2567 | */ | |
a66098da LB |
2568 | #define MWL8K_RATE_INDEX_MAX_ARRAY 14 |
2569 | ||
2570 | #define MWL8K_FRAME_PROT_DISABLED 0x00 | |
2571 | #define MWL8K_FRAME_PROT_11G 0x07 | |
2572 | #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02 | |
2573 | #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06 | |
a66098da LB |
2574 | |
2575 | struct mwl8k_cmd_update_set_aid { | |
2576 | struct mwl8k_cmd_pkt header; | |
2577 | __le16 aid; | |
2578 | ||
2579 | /* AP's MAC address (BSSID) */ | |
d89173f2 | 2580 | __u8 bssid[ETH_ALEN]; |
a66098da LB |
2581 | __le16 protection_mode; |
2582 | __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY]; | |
2583 | } __attribute__((packed)); | |
2584 | ||
2585 | static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw, | |
2586 | struct ieee80211_vif *vif) | |
2587 | { | |
2588 | struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); | |
2589 | struct ieee80211_bss_conf *info = &mv_vif->bss_info; | |
2590 | struct mwl8k_cmd_update_set_aid *cmd; | |
2591 | struct ieee80211_rate *bitrates = mv_vif->legacy_rates; | |
2592 | int count; | |
2593 | u16 prot_mode; | |
2594 | int rc; | |
2595 | ||
2596 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2597 | if (cmd == NULL) | |
2598 | return -ENOMEM; | |
2599 | ||
2600 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID); | |
2601 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2602 | cmd->aid = cpu_to_le16(info->aid); | |
2603 | ||
d89173f2 | 2604 | memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN); |
a66098da | 2605 | |
a66098da LB |
2606 | if (info->use_cts_prot) { |
2607 | prot_mode = MWL8K_FRAME_PROT_11G; | |
2608 | } else { | |
9ed6bcce | 2609 | switch (info->ht_operation_mode & |
a66098da LB |
2610 | IEEE80211_HT_OP_MODE_PROTECTION) { |
2611 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
2612 | prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY; | |
2613 | break; | |
2614 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
2615 | prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL; | |
2616 | break; | |
2617 | default: | |
2618 | prot_mode = MWL8K_FRAME_PROT_DISABLED; | |
2619 | break; | |
2620 | } | |
2621 | } | |
a66098da LB |
2622 | cmd->protection_mode = cpu_to_le16(prot_mode); |
2623 | ||
2624 | for (count = 0; count < mv_vif->legacy_nrates; count++) | |
2625 | cmd->supp_rates[count] = bitrates[count].hw_value; | |
2626 | ||
2627 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2628 | kfree(cmd); | |
2629 | ||
2630 | return rc; | |
2631 | } | |
2632 | ||
2633 | /* | |
2634 | * CMD_SET_RATE. | |
2635 | */ | |
2636 | struct mwl8k_cmd_update_rateset { | |
2637 | struct mwl8k_cmd_pkt header; | |
2638 | __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY]; | |
2639 | ||
2640 | /* Bitmap for supported MCS codes. */ | |
2641 | __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES]; | |
2642 | __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES]; | |
2643 | } __attribute__((packed)); | |
2644 | ||
2645 | static int mwl8k_update_rateset(struct ieee80211_hw *hw, | |
2646 | struct ieee80211_vif *vif) | |
2647 | { | |
2648 | struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); | |
2649 | struct mwl8k_cmd_update_rateset *cmd; | |
2650 | struct ieee80211_rate *bitrates = mv_vif->legacy_rates; | |
2651 | int count; | |
2652 | int rc; | |
2653 | ||
2654 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2655 | if (cmd == NULL) | |
2656 | return -ENOMEM; | |
2657 | ||
2658 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE); | |
2659 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2660 | ||
2661 | for (count = 0; count < mv_vif->legacy_nrates; count++) | |
2662 | cmd->legacy_rates[count] = bitrates[count].hw_value; | |
2663 | ||
2664 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2665 | kfree(cmd); | |
2666 | ||
2667 | return rc; | |
2668 | } | |
2669 | ||
2670 | /* | |
2671 | * CMD_USE_FIXED_RATE. | |
2672 | */ | |
2673 | #define MWL8K_RATE_TABLE_SIZE 8 | |
2674 | #define MWL8K_UCAST_RATE 0 | |
a66098da LB |
2675 | #define MWL8K_USE_AUTO_RATE 0x0002 |
2676 | ||
2677 | struct mwl8k_rate_entry { | |
2678 | /* Set to 1 if HT rate, 0 if legacy. */ | |
2679 | __le32 is_ht_rate; | |
2680 | ||
2681 | /* Set to 1 to use retry_count field. */ | |
2682 | __le32 enable_retry; | |
2683 | ||
2684 | /* Specified legacy rate or MCS. */ | |
2685 | __le32 rate; | |
2686 | ||
2687 | /* Number of allowed retries. */ | |
2688 | __le32 retry_count; | |
2689 | } __attribute__((packed)); | |
2690 | ||
2691 | struct mwl8k_rate_table { | |
2692 | /* 1 to allow specified rate and below */ | |
2693 | __le32 allow_rate_drop; | |
2694 | __le32 num_rates; | |
2695 | struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE]; | |
2696 | } __attribute__((packed)); | |
2697 | ||
2698 | struct mwl8k_cmd_use_fixed_rate { | |
2699 | struct mwl8k_cmd_pkt header; | |
2700 | __le32 action; | |
2701 | struct mwl8k_rate_table rate_table; | |
2702 | ||
2703 | /* Unicast, Broadcast or Multicast */ | |
2704 | __le32 rate_type; | |
2705 | __le32 reserved1; | |
2706 | __le32 reserved2; | |
2707 | } __attribute__((packed)); | |
2708 | ||
2709 | static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw, | |
2710 | u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table) | |
2711 | { | |
2712 | struct mwl8k_cmd_use_fixed_rate *cmd; | |
2713 | int count; | |
2714 | int rc; | |
2715 | ||
2716 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2717 | if (cmd == NULL) | |
2718 | return -ENOMEM; | |
2719 | ||
2720 | cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); | |
2721 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2722 | ||
2723 | cmd->action = cpu_to_le32(action); | |
2724 | cmd->rate_type = cpu_to_le32(rate_type); | |
2725 | ||
2726 | if (rate_table != NULL) { | |
c2c357ce LB |
2727 | /* |
2728 | * Copy over each field manually so that endian | |
2729 | * conversion can be done. | |
2730 | */ | |
a66098da LB |
2731 | cmd->rate_table.allow_rate_drop = |
2732 | cpu_to_le32(rate_table->allow_rate_drop); | |
2733 | cmd->rate_table.num_rates = | |
2734 | cpu_to_le32(rate_table->num_rates); | |
2735 | ||
2736 | for (count = 0; count < rate_table->num_rates; count++) { | |
2737 | struct mwl8k_rate_entry *dst = | |
2738 | &cmd->rate_table.rate_entry[count]; | |
2739 | struct mwl8k_rate_entry *src = | |
2740 | &rate_table->rate_entry[count]; | |
2741 | ||
2742 | dst->is_ht_rate = cpu_to_le32(src->is_ht_rate); | |
2743 | dst->enable_retry = cpu_to_le32(src->enable_retry); | |
2744 | dst->rate = cpu_to_le32(src->rate); | |
2745 | dst->retry_count = cpu_to_le32(src->retry_count); | |
2746 | } | |
2747 | } | |
2748 | ||
2749 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2750 | kfree(cmd); | |
2751 | ||
2752 | return rc; | |
2753 | } | |
2754 | ||
2755 | ||
2756 | /* | |
2757 | * Interrupt handling. | |
2758 | */ | |
2759 | static irqreturn_t mwl8k_interrupt(int irq, void *dev_id) | |
2760 | { | |
2761 | struct ieee80211_hw *hw = dev_id; | |
2762 | struct mwl8k_priv *priv = hw->priv; | |
2763 | u32 status; | |
2764 | ||
2765 | status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2766 | iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2767 | ||
a66098da LB |
2768 | if (!status) |
2769 | return IRQ_NONE; | |
2770 | ||
2771 | if (status & MWL8K_A2H_INT_TX_DONE) | |
2772 | tasklet_schedule(&priv->tx_reclaim_task); | |
2773 | ||
2774 | if (status & MWL8K_A2H_INT_RX_READY) { | |
2775 | while (rxq_process(hw, 0, 1)) | |
2776 | rxq_refill(hw, 0, 1); | |
2777 | } | |
2778 | ||
2779 | if (status & MWL8K_A2H_INT_OPC_DONE) { | |
618952a7 | 2780 | if (priv->hostcmd_wait != NULL) |
a66098da | 2781 | complete(priv->hostcmd_wait); |
a66098da LB |
2782 | } |
2783 | ||
2784 | if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { | |
618952a7 | 2785 | if (!mutex_is_locked(&priv->fw_mutex) && |
88de754a | 2786 | priv->radio_on && priv->pending_tx_pkts) |
618952a7 | 2787 | mwl8k_tx_start(priv); |
a66098da LB |
2788 | } |
2789 | ||
2790 | return IRQ_HANDLED; | |
2791 | } | |
2792 | ||
2793 | ||
2794 | /* | |
2795 | * Core driver operations. | |
2796 | */ | |
2797 | static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |
2798 | { | |
2799 | struct mwl8k_priv *priv = hw->priv; | |
2800 | int index = skb_get_queue_mapping(skb); | |
2801 | int rc; | |
2802 | ||
2803 | if (priv->current_channel == NULL) { | |
2804 | printk(KERN_DEBUG "%s: dropped TX frame since radio " | |
c2c357ce | 2805 | "disabled\n", wiphy_name(hw->wiphy)); |
a66098da LB |
2806 | dev_kfree_skb(skb); |
2807 | return NETDEV_TX_OK; | |
2808 | } | |
2809 | ||
2810 | rc = mwl8k_txq_xmit(hw, index, skb); | |
2811 | ||
2812 | return rc; | |
2813 | } | |
2814 | ||
a66098da LB |
2815 | static int mwl8k_start(struct ieee80211_hw *hw) |
2816 | { | |
a66098da LB |
2817 | struct mwl8k_priv *priv = hw->priv; |
2818 | int rc; | |
2819 | ||
a0607fd3 | 2820 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
2821 | IRQF_SHARED, MWL8K_NAME, hw); |
2822 | if (rc) { | |
2823 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 2824 | wiphy_name(hw->wiphy)); |
2ec610cb | 2825 | return -EIO; |
a66098da LB |
2826 | } |
2827 | ||
2ec610cb LB |
2828 | /* Enable tx reclaim tasklet */ |
2829 | tasklet_enable(&priv->tx_reclaim_task); | |
2830 | ||
a66098da | 2831 | /* Enable interrupts */ |
c23b5a69 | 2832 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da | 2833 | |
2ec610cb LB |
2834 | rc = mwl8k_fw_lock(hw); |
2835 | if (!rc) { | |
2836 | rc = mwl8k_cmd_802_11_radio_enable(hw); | |
a66098da | 2837 | |
5e4cf166 LB |
2838 | if (!priv->ap_fw) { |
2839 | if (!rc) | |
2840 | rc = mwl8k_enable_sniffer(hw, 0); | |
a66098da | 2841 | |
5e4cf166 LB |
2842 | if (!rc) |
2843 | rc = mwl8k_cmd_set_pre_scan(hw); | |
2844 | ||
2845 | if (!rc) | |
2846 | rc = mwl8k_cmd_set_post_scan(hw, | |
2847 | "\x00\x00\x00\x00\x00\x00"); | |
2848 | } | |
2ec610cb LB |
2849 | |
2850 | if (!rc) | |
2851 | rc = mwl8k_cmd_setrateadaptmode(hw, 0); | |
a66098da | 2852 | |
2ec610cb LB |
2853 | if (!rc) |
2854 | rc = mwl8k_set_wmm(hw, 0); | |
a66098da | 2855 | |
2ec610cb LB |
2856 | mwl8k_fw_unlock(hw); |
2857 | } | |
2858 | ||
2859 | if (rc) { | |
2860 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); | |
2861 | free_irq(priv->pdev->irq, hw); | |
2862 | tasklet_disable(&priv->tx_reclaim_task); | |
2863 | } | |
a66098da LB |
2864 | |
2865 | return rc; | |
2866 | } | |
2867 | ||
a66098da LB |
2868 | static void mwl8k_stop(struct ieee80211_hw *hw) |
2869 | { | |
a66098da LB |
2870 | struct mwl8k_priv *priv = hw->priv; |
2871 | int i; | |
2872 | ||
d3cea0b8 | 2873 | mwl8k_cmd_802_11_radio_disable(hw); |
a66098da LB |
2874 | |
2875 | ieee80211_stop_queues(hw); | |
2876 | ||
a66098da | 2877 | /* Disable interrupts */ |
a66098da | 2878 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
2879 | free_irq(priv->pdev->irq, hw); |
2880 | ||
2881 | /* Stop finalize join worker */ | |
2882 | cancel_work_sync(&priv->finalize_join_worker); | |
2883 | if (priv->beacon_skb != NULL) | |
2884 | dev_kfree_skb(priv->beacon_skb); | |
2885 | ||
2886 | /* Stop tx reclaim tasklet */ | |
2887 | tasklet_disable(&priv->tx_reclaim_task); | |
2888 | ||
a66098da LB |
2889 | /* Return all skbs to mac80211 */ |
2890 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
2891 | mwl8k_txq_reclaim(hw, i, 1); | |
2892 | } | |
2893 | ||
2894 | static int mwl8k_add_interface(struct ieee80211_hw *hw, | |
2895 | struct ieee80211_if_init_conf *conf) | |
2896 | { | |
2897 | struct mwl8k_priv *priv = hw->priv; | |
2898 | struct mwl8k_vif *mwl8k_vif; | |
2899 | ||
2900 | /* | |
2901 | * We only support one active interface at a time. | |
2902 | */ | |
2903 | if (priv->vif != NULL) | |
2904 | return -EBUSY; | |
2905 | ||
2906 | /* | |
2907 | * We only support managed interfaces for now. | |
2908 | */ | |
240e86ef | 2909 | if (conf->type != NL80211_IFTYPE_STATION) |
a66098da LB |
2910 | return -EINVAL; |
2911 | ||
a43c49a8 LB |
2912 | /* |
2913 | * Reject interface creation if sniffer mode is active, as | |
2914 | * STA operation is mutually exclusive with hardware sniffer | |
2915 | * mode. | |
2916 | */ | |
2917 | if (priv->sniffer_enabled) { | |
2918 | printk(KERN_INFO "%s: unable to create STA " | |
2919 | "interface due to sniffer mode being enabled\n", | |
2920 | wiphy_name(hw->wiphy)); | |
2921 | return -EINVAL; | |
2922 | } | |
2923 | ||
a66098da LB |
2924 | /* Clean out driver private area */ |
2925 | mwl8k_vif = MWL8K_VIF(conf->vif); | |
2926 | memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); | |
2927 | ||
32060e1b LB |
2928 | /* Set and save the mac address */ |
2929 | mwl8k_set_mac_addr(hw, conf->mac_addr); | |
d89173f2 | 2930 | memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN); |
a66098da LB |
2931 | |
2932 | /* Back pointer to parent config block */ | |
2933 | mwl8k_vif->priv = priv; | |
2934 | ||
2935 | /* Setup initial PHY parameters */ | |
ce9e2e1b | 2936 | memcpy(mwl8k_vif->legacy_rates, |
a66098da LB |
2937 | priv->rates, sizeof(mwl8k_vif->legacy_rates)); |
2938 | mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates); | |
2939 | ||
2940 | /* Set Initial sequence number to zero */ | |
2941 | mwl8k_vif->seqno = 0; | |
2942 | ||
2943 | priv->vif = conf->vif; | |
2944 | priv->current_channel = NULL; | |
2945 | ||
2946 | return 0; | |
2947 | } | |
2948 | ||
2949 | static void mwl8k_remove_interface(struct ieee80211_hw *hw, | |
2950 | struct ieee80211_if_init_conf *conf) | |
2951 | { | |
2952 | struct mwl8k_priv *priv = hw->priv; | |
2953 | ||
2954 | if (priv->vif == NULL) | |
2955 | return; | |
2956 | ||
32060e1b LB |
2957 | mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
2958 | ||
a66098da LB |
2959 | priv->vif = NULL; |
2960 | } | |
2961 | ||
ee03a932 | 2962 | static int mwl8k_config(struct ieee80211_hw *hw, u32 changed) |
a66098da | 2963 | { |
a66098da LB |
2964 | struct ieee80211_conf *conf = &hw->conf; |
2965 | struct mwl8k_priv *priv = hw->priv; | |
ee03a932 | 2966 | int rc; |
a66098da | 2967 | |
7595d67a LB |
2968 | if (conf->flags & IEEE80211_CONF_IDLE) { |
2969 | mwl8k_cmd_802_11_radio_disable(hw); | |
2970 | priv->current_channel = NULL; | |
ee03a932 | 2971 | return 0; |
7595d67a LB |
2972 | } |
2973 | ||
ee03a932 LB |
2974 | rc = mwl8k_fw_lock(hw); |
2975 | if (rc) | |
2976 | return rc; | |
a66098da | 2977 | |
ee03a932 LB |
2978 | rc = mwl8k_cmd_802_11_radio_enable(hw); |
2979 | if (rc) | |
2980 | goto out; | |
a66098da | 2981 | |
ee03a932 LB |
2982 | rc = mwl8k_cmd_set_rf_channel(hw, conf->channel); |
2983 | if (rc) | |
2984 | goto out; | |
2985 | ||
2986 | priv->current_channel = conf->channel; | |
a66098da LB |
2987 | |
2988 | if (conf->power_level > 18) | |
2989 | conf->power_level = 18; | |
ee03a932 LB |
2990 | rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level); |
2991 | if (rc) | |
2992 | goto out; | |
a66098da | 2993 | |
08b06347 LB |
2994 | if (priv->ap_fw) { |
2995 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7); | |
2996 | if (!rc) | |
2997 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); | |
2998 | } else { | |
2999 | rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); | |
3000 | } | |
a66098da | 3001 | |
ee03a932 LB |
3002 | out: |
3003 | mwl8k_fw_unlock(hw); | |
a66098da | 3004 | |
ee03a932 | 3005 | return rc; |
a66098da LB |
3006 | } |
3007 | ||
3a980d0a LB |
3008 | static void mwl8k_bss_info_changed(struct ieee80211_hw *hw, |
3009 | struct ieee80211_vif *vif, | |
3010 | struct ieee80211_bss_conf *info, | |
3011 | u32 changed) | |
a66098da | 3012 | { |
a66098da LB |
3013 | struct mwl8k_priv *priv = hw->priv; |
3014 | struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif); | |
3a980d0a LB |
3015 | int rc; |
3016 | ||
3017 | if (changed & BSS_CHANGED_BSSID) | |
3018 | memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN); | |
3019 | ||
3020 | if ((changed & BSS_CHANGED_ASSOC) == 0) | |
3021 | return; | |
a66098da | 3022 | |
a66098da LB |
3023 | priv->capture_beacon = false; |
3024 | ||
3a980d0a | 3025 | rc = mwl8k_fw_lock(hw); |
942457d6 | 3026 | if (rc) |
3a980d0a LB |
3027 | return; |
3028 | ||
a66098da LB |
3029 | if (info->assoc) { |
3030 | memcpy(&mwl8k_vif->bss_info, info, | |
3031 | sizeof(struct ieee80211_bss_conf)); | |
3032 | ||
3033 | /* Install rates */ | |
3a980d0a LB |
3034 | rc = mwl8k_update_rateset(hw, vif); |
3035 | if (rc) | |
3036 | goto out; | |
a66098da LB |
3037 | |
3038 | /* Turn on rate adaptation */ | |
3a980d0a LB |
3039 | rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE, |
3040 | MWL8K_UCAST_RATE, NULL); | |
3041 | if (rc) | |
3042 | goto out; | |
a66098da LB |
3043 | |
3044 | /* Set radio preamble */ | |
3a980d0a LB |
3045 | rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble); |
3046 | if (rc) | |
3047 | goto out; | |
a66098da LB |
3048 | |
3049 | /* Set slot time */ | |
3a980d0a LB |
3050 | rc = mwl8k_cmd_set_slot(hw, info->use_short_slot); |
3051 | if (rc) | |
3052 | goto out; | |
a66098da LB |
3053 | |
3054 | /* Update peer rate info */ | |
3a980d0a LB |
3055 | rc = mwl8k_cmd_update_sta_db(hw, vif, |
3056 | MWL8K_STA_DB_MODIFY_ENTRY); | |
3057 | if (rc) | |
3058 | goto out; | |
a66098da LB |
3059 | |
3060 | /* Set AID */ | |
3a980d0a LB |
3061 | rc = mwl8k_cmd_set_aid(hw, vif); |
3062 | if (rc) | |
3063 | goto out; | |
a66098da LB |
3064 | |
3065 | /* | |
3066 | * Finalize the join. Tell rx handler to process | |
3067 | * next beacon from our BSSID. | |
3068 | */ | |
d89173f2 | 3069 | memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN); |
a66098da LB |
3070 | priv->capture_beacon = true; |
3071 | } else { | |
3a980d0a | 3072 | rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY); |
a66098da LB |
3073 | memset(&mwl8k_vif->bss_info, 0, |
3074 | sizeof(struct ieee80211_bss_conf)); | |
d89173f2 | 3075 | memset(mwl8k_vif->bssid, 0, ETH_ALEN); |
a66098da LB |
3076 | } |
3077 | ||
3a980d0a LB |
3078 | out: |
3079 | mwl8k_fw_unlock(hw); | |
a66098da LB |
3080 | } |
3081 | ||
e81cd2d6 LB |
3082 | static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw, |
3083 | int mc_count, struct dev_addr_list *mclist) | |
3084 | { | |
3085 | struct mwl8k_cmd_pkt *cmd; | |
3086 | ||
447ced07 LB |
3087 | /* |
3088 | * Synthesize and return a command packet that programs the | |
3089 | * hardware multicast address filter. At this point we don't | |
3090 | * know whether FIF_ALLMULTI is being requested, but if it is, | |
3091 | * we'll end up throwing this packet away and creating a new | |
3092 | * one in mwl8k_configure_filter(). | |
3093 | */ | |
3094 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist); | |
e81cd2d6 LB |
3095 | |
3096 | return (unsigned long)cmd; | |
3097 | } | |
3098 | ||
a43c49a8 LB |
3099 | static int |
3100 | mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw, | |
3101 | unsigned int changed_flags, | |
3102 | unsigned int *total_flags) | |
3103 | { | |
3104 | struct mwl8k_priv *priv = hw->priv; | |
3105 | ||
3106 | /* | |
3107 | * Hardware sniffer mode is mutually exclusive with STA | |
3108 | * operation, so refuse to enable sniffer mode if a STA | |
3109 | * interface is active. | |
3110 | */ | |
3111 | if (priv->vif != NULL) { | |
3112 | if (net_ratelimit()) | |
3113 | printk(KERN_INFO "%s: not enabling sniffer " | |
3114 | "mode because STA interface is active\n", | |
3115 | wiphy_name(hw->wiphy)); | |
3116 | return 0; | |
3117 | } | |
3118 | ||
3119 | if (!priv->sniffer_enabled) { | |
3120 | if (mwl8k_enable_sniffer(hw, 1)) | |
3121 | return 0; | |
3122 | priv->sniffer_enabled = true; | |
3123 | } | |
3124 | ||
3125 | *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI | | |
3126 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | | |
3127 | FIF_OTHER_BSS; | |
3128 | ||
3129 | return 1; | |
3130 | } | |
3131 | ||
e6935ea1 LB |
3132 | static void mwl8k_configure_filter(struct ieee80211_hw *hw, |
3133 | unsigned int changed_flags, | |
3134 | unsigned int *total_flags, | |
3135 | u64 multicast) | |
3136 | { | |
3137 | struct mwl8k_priv *priv = hw->priv; | |
a43c49a8 LB |
3138 | struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast; |
3139 | ||
c0adae2c LB |
3140 | /* |
3141 | * AP firmware doesn't allow fine-grained control over | |
3142 | * the receive filter. | |
3143 | */ | |
3144 | if (priv->ap_fw) { | |
3145 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; | |
3146 | kfree(cmd); | |
3147 | return; | |
3148 | } | |
3149 | ||
a43c49a8 LB |
3150 | /* |
3151 | * Enable hardware sniffer mode if FIF_CONTROL or | |
3152 | * FIF_OTHER_BSS is requested. | |
3153 | */ | |
3154 | if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) && | |
3155 | mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) { | |
3156 | kfree(cmd); | |
3157 | return; | |
3158 | } | |
a66098da | 3159 | |
e6935ea1 | 3160 | /* Clear unsupported feature flags */ |
447ced07 | 3161 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; |
a66098da | 3162 | |
e6935ea1 LB |
3163 | if (mwl8k_fw_lock(hw)) |
3164 | return; | |
a66098da | 3165 | |
a43c49a8 LB |
3166 | if (priv->sniffer_enabled) { |
3167 | mwl8k_enable_sniffer(hw, 0); | |
3168 | priv->sniffer_enabled = false; | |
3169 | } | |
3170 | ||
e6935ea1 | 3171 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
77165d88 LB |
3172 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { |
3173 | /* | |
3174 | * Disable the BSS filter. | |
3175 | */ | |
e6935ea1 | 3176 | mwl8k_cmd_set_pre_scan(hw); |
77165d88 | 3177 | } else { |
a94cc97e LB |
3178 | u8 *bssid; |
3179 | ||
77165d88 LB |
3180 | /* |
3181 | * Enable the BSS filter. | |
3182 | * | |
3183 | * If there is an active STA interface, use that | |
3184 | * interface's BSSID, otherwise use a dummy one | |
3185 | * (where the OUI part needs to be nonzero for | |
3186 | * the BSSID to be accepted by POST_SCAN). | |
3187 | */ | |
3188 | bssid = "\x01\x00\x00\x00\x00\x00"; | |
a94cc97e LB |
3189 | if (priv->vif != NULL) |
3190 | bssid = MWL8K_VIF(priv->vif)->bssid; | |
3191 | ||
e6935ea1 | 3192 | mwl8k_cmd_set_post_scan(hw, bssid); |
a66098da LB |
3193 | } |
3194 | } | |
3195 | ||
447ced07 LB |
3196 | /* |
3197 | * If FIF_ALLMULTI is being requested, throw away the command | |
3198 | * packet that ->prepare_multicast() built and replace it with | |
3199 | * a command packet that enables reception of all multicast | |
3200 | * packets. | |
3201 | */ | |
3202 | if (*total_flags & FIF_ALLMULTI) { | |
3203 | kfree(cmd); | |
3204 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL); | |
3205 | } | |
3206 | ||
3207 | if (cmd != NULL) { | |
3208 | mwl8k_post_cmd(hw, cmd); | |
3209 | kfree(cmd); | |
e6935ea1 | 3210 | } |
a66098da | 3211 | |
e6935ea1 | 3212 | mwl8k_fw_unlock(hw); |
a66098da LB |
3213 | } |
3214 | ||
a66098da LB |
3215 | static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
3216 | { | |
733d3067 | 3217 | return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value); |
a66098da LB |
3218 | } |
3219 | ||
a66098da LB |
3220 | static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
3221 | const struct ieee80211_tx_queue_params *params) | |
3222 | { | |
3e4f542c | 3223 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 3224 | int rc; |
a66098da | 3225 | |
3e4f542c LB |
3226 | rc = mwl8k_fw_lock(hw); |
3227 | if (!rc) { | |
3228 | if (!priv->wmm_enabled) | |
3229 | rc = mwl8k_set_wmm(hw, 1); | |
a66098da | 3230 | |
3e4f542c LB |
3231 | if (!rc) |
3232 | rc = mwl8k_set_edca_params(hw, queue, | |
3233 | params->cw_min, | |
3234 | params->cw_max, | |
3235 | params->aifs, | |
3236 | params->txop); | |
3237 | ||
3238 | mwl8k_fw_unlock(hw); | |
a66098da | 3239 | } |
3e4f542c | 3240 | |
a66098da LB |
3241 | return rc; |
3242 | } | |
3243 | ||
3244 | static int mwl8k_get_tx_stats(struct ieee80211_hw *hw, | |
3245 | struct ieee80211_tx_queue_stats *stats) | |
3246 | { | |
3247 | struct mwl8k_priv *priv = hw->priv; | |
3248 | struct mwl8k_tx_queue *txq; | |
3249 | int index; | |
3250 | ||
3251 | spin_lock_bh(&priv->tx_lock); | |
3252 | for (index = 0; index < MWL8K_TX_QUEUES; index++) { | |
3253 | txq = priv->txq + index; | |
45eb400d | 3254 | memcpy(&stats[index], &txq->stats, |
a66098da LB |
3255 | sizeof(struct ieee80211_tx_queue_stats)); |
3256 | } | |
3257 | spin_unlock_bh(&priv->tx_lock); | |
a66098da | 3258 | |
954ef509 | 3259 | return 0; |
a66098da LB |
3260 | } |
3261 | ||
3262 | static int mwl8k_get_stats(struct ieee80211_hw *hw, | |
3263 | struct ieee80211_low_level_stats *stats) | |
3264 | { | |
954ef509 | 3265 | return mwl8k_cmd_802_11_get_stat(hw, stats); |
a66098da LB |
3266 | } |
3267 | ||
3268 | static const struct ieee80211_ops mwl8k_ops = { | |
3269 | .tx = mwl8k_tx, | |
3270 | .start = mwl8k_start, | |
3271 | .stop = mwl8k_stop, | |
3272 | .add_interface = mwl8k_add_interface, | |
3273 | .remove_interface = mwl8k_remove_interface, | |
3274 | .config = mwl8k_config, | |
a66098da | 3275 | .bss_info_changed = mwl8k_bss_info_changed, |
3ac64bee | 3276 | .prepare_multicast = mwl8k_prepare_multicast, |
a66098da LB |
3277 | .configure_filter = mwl8k_configure_filter, |
3278 | .set_rts_threshold = mwl8k_set_rts_threshold, | |
3279 | .conf_tx = mwl8k_conf_tx, | |
3280 | .get_tx_stats = mwl8k_get_tx_stats, | |
3281 | .get_stats = mwl8k_get_stats, | |
3282 | }; | |
3283 | ||
3284 | static void mwl8k_tx_reclaim_handler(unsigned long data) | |
3285 | { | |
3286 | int i; | |
3287 | struct ieee80211_hw *hw = (struct ieee80211_hw *) data; | |
3288 | struct mwl8k_priv *priv = hw->priv; | |
3289 | ||
3290 | spin_lock_bh(&priv->tx_lock); | |
3291 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3292 | mwl8k_txq_reclaim(hw, i, 0); | |
3293 | ||
88de754a | 3294 | if (priv->tx_wait != NULL && !priv->pending_tx_pkts) { |
ce9e2e1b LB |
3295 | complete(priv->tx_wait); |
3296 | priv->tx_wait = NULL; | |
a66098da LB |
3297 | } |
3298 | spin_unlock_bh(&priv->tx_lock); | |
3299 | } | |
3300 | ||
3301 | static void mwl8k_finalize_join_worker(struct work_struct *work) | |
3302 | { | |
3303 | struct mwl8k_priv *priv = | |
3304 | container_of(work, struct mwl8k_priv, finalize_join_worker); | |
3305 | struct sk_buff *skb = priv->beacon_skb; | |
ce9e2e1b | 3306 | u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period; |
a66098da LB |
3307 | |
3308 | mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim); | |
3309 | dev_kfree_skb(skb); | |
3310 | ||
3311 | priv->beacon_skb = NULL; | |
3312 | } | |
3313 | ||
bcb628d5 JL |
3314 | enum { |
3315 | MWL8687 = 0, | |
3316 | MWL8366, | |
6f6d1e9a LB |
3317 | }; |
3318 | ||
bcb628d5 JL |
3319 | static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = { |
3320 | { | |
3321 | .part_name = "88w8687", | |
3322 | .helper_image = "mwl8k/helper_8687.fw", | |
3323 | .fw_image = "mwl8k/fmimage_8687.fw", | |
3324 | .rxd_ops = &rxd_8687_ops, | |
3325 | .modes = BIT(NL80211_IFTYPE_STATION), | |
3326 | }, | |
3327 | { | |
3328 | .part_name = "88w8366", | |
3329 | .helper_image = "mwl8k/helper_8366.fw", | |
3330 | .fw_image = "mwl8k/fmimage_8366.fw", | |
3331 | .rxd_ops = &rxd_8366_ops, | |
3332 | .modes = 0, | |
3333 | }, | |
45a390dd LB |
3334 | }; |
3335 | ||
3336 | static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = { | |
bcb628d5 JL |
3337 | { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, }, |
3338 | { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, }, | |
3339 | { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, }, | |
3340 | { }, | |
45a390dd LB |
3341 | }; |
3342 | MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table); | |
3343 | ||
a66098da LB |
3344 | static int __devinit mwl8k_probe(struct pci_dev *pdev, |
3345 | const struct pci_device_id *id) | |
3346 | { | |
2aa7b01f | 3347 | static int printed_version = 0; |
a66098da LB |
3348 | struct ieee80211_hw *hw; |
3349 | struct mwl8k_priv *priv; | |
a66098da LB |
3350 | int rc; |
3351 | int i; | |
2aa7b01f LB |
3352 | |
3353 | if (!printed_version) { | |
3354 | printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION); | |
3355 | printed_version = 1; | |
3356 | } | |
a66098da LB |
3357 | |
3358 | rc = pci_enable_device(pdev); | |
3359 | if (rc) { | |
3360 | printk(KERN_ERR "%s: Cannot enable new PCI device\n", | |
3361 | MWL8K_NAME); | |
3362 | return rc; | |
3363 | } | |
3364 | ||
3365 | rc = pci_request_regions(pdev, MWL8K_NAME); | |
3366 | if (rc) { | |
3367 | printk(KERN_ERR "%s: Cannot obtain PCI resources\n", | |
3368 | MWL8K_NAME); | |
3369 | return rc; | |
3370 | } | |
3371 | ||
3372 | pci_set_master(pdev); | |
3373 | ||
3374 | hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops); | |
3375 | if (hw == NULL) { | |
3376 | printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME); | |
3377 | rc = -ENOMEM; | |
3378 | goto err_free_reg; | |
3379 | } | |
3380 | ||
3381 | priv = hw->priv; | |
3382 | priv->hw = hw; | |
3383 | priv->pdev = pdev; | |
bcb628d5 | 3384 | priv->device_info = &mwl8k_info_tbl[id->driver_data]; |
54bc3a0d | 3385 | priv->rxd_ops = priv->device_info->rxd_ops; |
a43c49a8 | 3386 | priv->sniffer_enabled = false; |
0439b1f5 | 3387 | priv->wmm_enabled = false; |
a66098da | 3388 | priv->pending_tx_pkts = 0; |
a66098da | 3389 | |
a66098da LB |
3390 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3391 | pci_set_drvdata(pdev, hw); | |
3392 | ||
5b9482dd LB |
3393 | priv->sram = pci_iomap(pdev, 0, 0x10000); |
3394 | if (priv->sram == NULL) { | |
3395 | printk(KERN_ERR "%s: Cannot map device SRAM\n", | |
c2c357ce | 3396 | wiphy_name(hw->wiphy)); |
a66098da LB |
3397 | goto err_iounmap; |
3398 | } | |
3399 | ||
5b9482dd LB |
3400 | /* |
3401 | * If BAR0 is a 32 bit BAR, the register BAR will be BAR1. | |
3402 | * If BAR0 is a 64 bit BAR, the register BAR will be BAR2. | |
3403 | */ | |
3404 | priv->regs = pci_iomap(pdev, 1, 0x10000); | |
3405 | if (priv->regs == NULL) { | |
3406 | priv->regs = pci_iomap(pdev, 2, 0x10000); | |
3407 | if (priv->regs == NULL) { | |
3408 | printk(KERN_ERR "%s: Cannot map device registers\n", | |
3409 | wiphy_name(hw->wiphy)); | |
3410 | goto err_iounmap; | |
3411 | } | |
3412 | } | |
3413 | ||
a66098da LB |
3414 | memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels)); |
3415 | priv->band.band = IEEE80211_BAND_2GHZ; | |
3416 | priv->band.channels = priv->channels; | |
3417 | priv->band.n_channels = ARRAY_SIZE(mwl8k_channels); | |
3418 | priv->band.bitrates = priv->rates; | |
3419 | priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates); | |
3420 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
3421 | ||
3422 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates)); | |
3423 | memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates)); | |
3424 | ||
3425 | /* | |
3426 | * Extra headroom is the size of the required DMA header | |
3427 | * minus the size of the smallest 802.11 frame (CTS frame). | |
3428 | */ | |
3429 | hw->extra_tx_headroom = | |
3430 | sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts); | |
3431 | ||
3432 | hw->channel_change_time = 10; | |
3433 | ||
3434 | hw->queues = MWL8K_TX_QUEUES; | |
3435 | ||
547810e3 | 3436 | hw->wiphy->interface_modes = priv->device_info->modes; |
a66098da LB |
3437 | |
3438 | /* Set rssi and noise values to dBm */ | |
ce9e2e1b | 3439 | hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; |
a66098da LB |
3440 | hw->vif_data_size = sizeof(struct mwl8k_vif); |
3441 | priv->vif = NULL; | |
3442 | ||
3443 | /* Set default radio state and preamble */ | |
c46563b7 | 3444 | priv->radio_on = 0; |
68ce3884 | 3445 | priv->radio_short_preamble = 0; |
a66098da LB |
3446 | |
3447 | /* Finalize join worker */ | |
3448 | INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker); | |
3449 | ||
3450 | /* TX reclaim tasklet */ | |
3451 | tasklet_init(&priv->tx_reclaim_task, | |
3452 | mwl8k_tx_reclaim_handler, (unsigned long)hw); | |
3453 | tasklet_disable(&priv->tx_reclaim_task); | |
3454 | ||
a66098da LB |
3455 | /* Power management cookie */ |
3456 | priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); | |
3457 | if (priv->cookie == NULL) | |
3458 | goto err_iounmap; | |
3459 | ||
3460 | rc = mwl8k_rxq_init(hw, 0); | |
3461 | if (rc) | |
3462 | goto err_iounmap; | |
3463 | rxq_refill(hw, 0, INT_MAX); | |
3464 | ||
618952a7 LB |
3465 | mutex_init(&priv->fw_mutex); |
3466 | priv->fw_mutex_owner = NULL; | |
3467 | priv->fw_mutex_depth = 0; | |
618952a7 LB |
3468 | priv->hostcmd_wait = NULL; |
3469 | ||
a66098da LB |
3470 | spin_lock_init(&priv->tx_lock); |
3471 | ||
88de754a LB |
3472 | priv->tx_wait = NULL; |
3473 | ||
a66098da LB |
3474 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { |
3475 | rc = mwl8k_txq_init(hw, i); | |
3476 | if (rc) | |
3477 | goto err_free_queues; | |
3478 | } | |
3479 | ||
3480 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
c23b5a69 | 3481 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3482 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL); |
3483 | iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK); | |
3484 | ||
a0607fd3 | 3485 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
3486 | IRQF_SHARED, MWL8K_NAME, hw); |
3487 | if (rc) { | |
3488 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 3489 | wiphy_name(hw->wiphy)); |
a66098da LB |
3490 | goto err_free_queues; |
3491 | } | |
3492 | ||
3493 | /* Reset firmware and hardware */ | |
3494 | mwl8k_hw_reset(priv); | |
3495 | ||
3496 | /* Ask userland hotplug daemon for the device firmware */ | |
45a390dd | 3497 | rc = mwl8k_request_firmware(priv); |
a66098da | 3498 | if (rc) { |
c2c357ce LB |
3499 | printk(KERN_ERR "%s: Firmware files not found\n", |
3500 | wiphy_name(hw->wiphy)); | |
a66098da LB |
3501 | goto err_free_irq; |
3502 | } | |
3503 | ||
3504 | /* Load firmware into hardware */ | |
c2c357ce | 3505 | rc = mwl8k_load_firmware(hw); |
a66098da | 3506 | if (rc) { |
c2c357ce LB |
3507 | printk(KERN_ERR "%s: Cannot start firmware\n", |
3508 | wiphy_name(hw->wiphy)); | |
a66098da LB |
3509 | goto err_stop_firmware; |
3510 | } | |
3511 | ||
3512 | /* Reclaim memory once firmware is successfully loaded */ | |
3513 | mwl8k_release_firmware(priv); | |
3514 | ||
3515 | /* | |
3516 | * Temporarily enable interrupts. Initial firmware host | |
3517 | * commands use interrupts and avoids polling. Disable | |
3518 | * interrupts when done. | |
3519 | */ | |
c23b5a69 | 3520 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3521 | |
3522 | /* Get config data, mac addrs etc */ | |
42fba21d LB |
3523 | if (priv->ap_fw) { |
3524 | rc = mwl8k_cmd_get_hw_spec_ap(hw); | |
3525 | if (!rc) | |
3526 | rc = mwl8k_cmd_set_hw_spec(hw); | |
3527 | } else { | |
3528 | rc = mwl8k_cmd_get_hw_spec_sta(hw); | |
3529 | } | |
a66098da | 3530 | if (rc) { |
c2c357ce LB |
3531 | printk(KERN_ERR "%s: Cannot initialise firmware\n", |
3532 | wiphy_name(hw->wiphy)); | |
a66098da LB |
3533 | goto err_stop_firmware; |
3534 | } | |
3535 | ||
3536 | /* Turn radio off */ | |
c46563b7 | 3537 | rc = mwl8k_cmd_802_11_radio_disable(hw); |
a66098da | 3538 | if (rc) { |
c2c357ce | 3539 | printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy)); |
a66098da LB |
3540 | goto err_stop_firmware; |
3541 | } | |
3542 | ||
32060e1b LB |
3543 | /* Clear MAC address */ |
3544 | rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); | |
3545 | if (rc) { | |
3546 | printk(KERN_ERR "%s: Cannot clear MAC address\n", | |
3547 | wiphy_name(hw->wiphy)); | |
3548 | goto err_stop_firmware; | |
3549 | } | |
3550 | ||
a66098da | 3551 | /* Disable interrupts */ |
a66098da | 3552 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3553 | free_irq(priv->pdev->irq, hw); |
3554 | ||
3555 | rc = ieee80211_register_hw(hw); | |
3556 | if (rc) { | |
c2c357ce LB |
3557 | printk(KERN_ERR "%s: Cannot register device\n", |
3558 | wiphy_name(hw->wiphy)); | |
a66098da LB |
3559 | goto err_stop_firmware; |
3560 | } | |
3561 | ||
eae74e65 | 3562 | printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n", |
a74b295e | 3563 | wiphy_name(hw->wiphy), priv->device_info->part_name, |
45a390dd | 3564 | priv->hw_rev, hw->wiphy->perm_addr, |
eae74e65 | 3565 | priv->ap_fw ? "AP" : "STA", |
2aa7b01f LB |
3566 | (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, |
3567 | (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); | |
a66098da LB |
3568 | |
3569 | return 0; | |
3570 | ||
3571 | err_stop_firmware: | |
3572 | mwl8k_hw_reset(priv); | |
3573 | mwl8k_release_firmware(priv); | |
3574 | ||
3575 | err_free_irq: | |
a66098da | 3576 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3577 | free_irq(priv->pdev->irq, hw); |
3578 | ||
3579 | err_free_queues: | |
3580 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3581 | mwl8k_txq_deinit(hw, i); | |
3582 | mwl8k_rxq_deinit(hw, 0); | |
3583 | ||
3584 | err_iounmap: | |
3585 | if (priv->cookie != NULL) | |
3586 | pci_free_consistent(priv->pdev, 4, | |
3587 | priv->cookie, priv->cookie_dma); | |
3588 | ||
3589 | if (priv->regs != NULL) | |
3590 | pci_iounmap(pdev, priv->regs); | |
3591 | ||
5b9482dd LB |
3592 | if (priv->sram != NULL) |
3593 | pci_iounmap(pdev, priv->sram); | |
3594 | ||
a66098da LB |
3595 | pci_set_drvdata(pdev, NULL); |
3596 | ieee80211_free_hw(hw); | |
3597 | ||
3598 | err_free_reg: | |
3599 | pci_release_regions(pdev); | |
3600 | pci_disable_device(pdev); | |
3601 | ||
3602 | return rc; | |
3603 | } | |
3604 | ||
230f7af0 | 3605 | static void __devexit mwl8k_shutdown(struct pci_dev *pdev) |
a66098da LB |
3606 | { |
3607 | printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__); | |
3608 | } | |
3609 | ||
230f7af0 | 3610 | static void __devexit mwl8k_remove(struct pci_dev *pdev) |
a66098da LB |
3611 | { |
3612 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
3613 | struct mwl8k_priv *priv; | |
3614 | int i; | |
3615 | ||
3616 | if (hw == NULL) | |
3617 | return; | |
3618 | priv = hw->priv; | |
3619 | ||
3620 | ieee80211_stop_queues(hw); | |
3621 | ||
60aa569f LB |
3622 | ieee80211_unregister_hw(hw); |
3623 | ||
a66098da LB |
3624 | /* Remove tx reclaim tasklet */ |
3625 | tasklet_kill(&priv->tx_reclaim_task); | |
3626 | ||
a66098da LB |
3627 | /* Stop hardware */ |
3628 | mwl8k_hw_reset(priv); | |
3629 | ||
3630 | /* Return all skbs to mac80211 */ | |
3631 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3632 | mwl8k_txq_reclaim(hw, i, 1); | |
3633 | ||
a66098da LB |
3634 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
3635 | mwl8k_txq_deinit(hw, i); | |
3636 | ||
3637 | mwl8k_rxq_deinit(hw, 0); | |
3638 | ||
c2c357ce | 3639 | pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma); |
a66098da LB |
3640 | |
3641 | pci_iounmap(pdev, priv->regs); | |
5b9482dd | 3642 | pci_iounmap(pdev, priv->sram); |
a66098da LB |
3643 | pci_set_drvdata(pdev, NULL); |
3644 | ieee80211_free_hw(hw); | |
3645 | pci_release_regions(pdev); | |
3646 | pci_disable_device(pdev); | |
3647 | } | |
3648 | ||
3649 | static struct pci_driver mwl8k_driver = { | |
3650 | .name = MWL8K_NAME, | |
45a390dd | 3651 | .id_table = mwl8k_pci_id_table, |
a66098da LB |
3652 | .probe = mwl8k_probe, |
3653 | .remove = __devexit_p(mwl8k_remove), | |
3654 | .shutdown = __devexit_p(mwl8k_shutdown), | |
3655 | }; | |
3656 | ||
3657 | static int __init mwl8k_init(void) | |
3658 | { | |
3659 | return pci_register_driver(&mwl8k_driver); | |
3660 | } | |
3661 | ||
3662 | static void __exit mwl8k_exit(void) | |
3663 | { | |
3664 | pci_unregister_driver(&mwl8k_driver); | |
3665 | } | |
3666 | ||
3667 | module_init(mwl8k_init); | |
3668 | module_exit(mwl8k_exit); | |
c2c357ce LB |
3669 | |
3670 | MODULE_DESCRIPTION(MWL8K_DESC); | |
3671 | MODULE_VERSION(MWL8K_VERSION); | |
3672 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>"); | |
3673 | MODULE_LICENSE("GPL"); |