Commit | Line | Data |
---|---|---|
a66098da | 1 | /* |
ce9e2e1b LB |
2 | * drivers/net/wireless/mwl8k.c |
3 | * Driver for Marvell TOPDOG 802.11 Wireless cards | |
a66098da | 4 | * |
a145d575 | 5 | * Copyright (C) 2008-2009 Marvell Semiconductor Inc. |
a66098da LB |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
3d76e82c | 15 | #include <linux/sched.h> |
a66098da LB |
16 | #include <linux/spinlock.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/workqueue.h> | |
26 | ||
27 | #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" | |
28 | #define MWL8K_NAME KBUILD_MODNAME | |
a145d575 | 29 | #define MWL8K_VERSION "0.10" |
a66098da | 30 | |
a66098da LB |
31 | /* Register definitions */ |
32 | #define MWL8K_HIU_GEN_PTR 0x00000c10 | |
ce9e2e1b LB |
33 | #define MWL8K_MODE_STA 0x0000005a |
34 | #define MWL8K_MODE_AP 0x000000a5 | |
a66098da | 35 | #define MWL8K_HIU_INT_CODE 0x00000c14 |
ce9e2e1b LB |
36 | #define MWL8K_FWSTA_READY 0xf0f1f2f4 |
37 | #define MWL8K_FWAP_READY 0xf1f2f4a5 | |
38 | #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 | |
a66098da LB |
39 | #define MWL8K_HIU_SCRATCH 0x00000c40 |
40 | ||
41 | /* Host->device communications */ | |
42 | #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 | |
43 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c | |
44 | #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 | |
45 | #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 | |
46 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 | |
ce9e2e1b LB |
47 | #define MWL8K_H2A_INT_DUMMY (1 << 20) |
48 | #define MWL8K_H2A_INT_RESET (1 << 15) | |
49 | #define MWL8K_H2A_INT_DOORBELL (1 << 1) | |
50 | #define MWL8K_H2A_INT_PPA_READY (1 << 0) | |
a66098da LB |
51 | |
52 | /* Device->host communications */ | |
53 | #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c | |
54 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 | |
55 | #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 | |
56 | #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 | |
57 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c | |
ce9e2e1b LB |
58 | #define MWL8K_A2H_INT_DUMMY (1 << 20) |
59 | #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) | |
60 | #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) | |
61 | #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) | |
62 | #define MWL8K_A2H_INT_RADIO_ON (1 << 6) | |
63 | #define MWL8K_A2H_INT_RADIO_OFF (1 << 5) | |
64 | #define MWL8K_A2H_INT_MAC_EVENT (1 << 3) | |
65 | #define MWL8K_A2H_INT_OPC_DONE (1 << 2) | |
66 | #define MWL8K_A2H_INT_RX_READY (1 << 1) | |
67 | #define MWL8K_A2H_INT_TX_DONE (1 << 0) | |
a66098da LB |
68 | |
69 | #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ | |
70 | MWL8K_A2H_INT_CHNL_SWITCHED | \ | |
71 | MWL8K_A2H_INT_QUEUE_EMPTY | \ | |
72 | MWL8K_A2H_INT_RADAR_DETECT | \ | |
73 | MWL8K_A2H_INT_RADIO_ON | \ | |
74 | MWL8K_A2H_INT_RADIO_OFF | \ | |
75 | MWL8K_A2H_INT_MAC_EVENT | \ | |
76 | MWL8K_A2H_INT_OPC_DONE | \ | |
77 | MWL8K_A2H_INT_RX_READY | \ | |
78 | MWL8K_A2H_INT_TX_DONE) | |
79 | ||
a66098da LB |
80 | #define MWL8K_RX_QUEUES 1 |
81 | #define MWL8K_TX_QUEUES 4 | |
82 | ||
54bc3a0d LB |
83 | struct rxd_ops { |
84 | int rxd_size; | |
85 | void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); | |
86 | void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); | |
87 | int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status); | |
88 | }; | |
89 | ||
45a390dd | 90 | struct mwl8k_device_info { |
a74b295e LB |
91 | char *part_name; |
92 | char *helper_image; | |
93 | char *fw_image; | |
54bc3a0d | 94 | struct rxd_ops *rxd_ops; |
547810e3 | 95 | u16 modes; |
45a390dd LB |
96 | }; |
97 | ||
a66098da | 98 | struct mwl8k_rx_queue { |
45eb400d | 99 | int rxd_count; |
a66098da LB |
100 | |
101 | /* hw receives here */ | |
45eb400d | 102 | int head; |
a66098da LB |
103 | |
104 | /* refill descs here */ | |
45eb400d | 105 | int tail; |
a66098da | 106 | |
54bc3a0d | 107 | void *rxd; |
45eb400d | 108 | dma_addr_t rxd_dma; |
788838eb LB |
109 | struct { |
110 | struct sk_buff *skb; | |
111 | DECLARE_PCI_UNMAP_ADDR(dma) | |
112 | } *buf; | |
a66098da LB |
113 | }; |
114 | ||
a66098da LB |
115 | struct mwl8k_tx_queue { |
116 | /* hw transmits here */ | |
45eb400d | 117 | int head; |
a66098da LB |
118 | |
119 | /* sw appends here */ | |
45eb400d | 120 | int tail; |
a66098da | 121 | |
45eb400d LB |
122 | struct ieee80211_tx_queue_stats stats; |
123 | struct mwl8k_tx_desc *txd; | |
124 | dma_addr_t txd_dma; | |
125 | struct sk_buff **skb; | |
a66098da LB |
126 | }; |
127 | ||
128 | /* Pointers to the firmware data and meta information about it. */ | |
129 | struct mwl8k_firmware { | |
a66098da LB |
130 | /* Boot helper code */ |
131 | struct firmware *helper; | |
a74b295e LB |
132 | |
133 | /* Microcode */ | |
134 | struct firmware *ucode; | |
a66098da LB |
135 | }; |
136 | ||
137 | struct mwl8k_priv { | |
5b9482dd | 138 | void __iomem *sram; |
a66098da LB |
139 | void __iomem *regs; |
140 | struct ieee80211_hw *hw; | |
141 | ||
142 | struct pci_dev *pdev; | |
a66098da | 143 | |
45a390dd | 144 | struct mwl8k_device_info *device_info; |
eae74e65 | 145 | bool ap_fw; |
54bc3a0d | 146 | struct rxd_ops *rxd_ops; |
45a390dd | 147 | |
a66098da LB |
148 | /* firmware files and meta data */ |
149 | struct mwl8k_firmware fw; | |
a66098da | 150 | |
618952a7 LB |
151 | /* firmware access */ |
152 | struct mutex fw_mutex; | |
153 | struct task_struct *fw_mutex_owner; | |
154 | int fw_mutex_depth; | |
618952a7 LB |
155 | struct completion *hostcmd_wait; |
156 | ||
a66098da LB |
157 | /* lock held over TX and TX reap */ |
158 | spinlock_t tx_lock; | |
a66098da | 159 | |
88de754a LB |
160 | /* TX quiesce completion, protected by fw_mutex and tx_lock */ |
161 | struct completion *tx_wait; | |
162 | ||
a66098da | 163 | struct ieee80211_vif *vif; |
a66098da LB |
164 | |
165 | struct ieee80211_channel *current_channel; | |
166 | ||
167 | /* power management status cookie from firmware */ | |
168 | u32 *cookie; | |
169 | dma_addr_t cookie_dma; | |
170 | ||
171 | u16 num_mcaddrs; | |
a66098da | 172 | u8 hw_rev; |
2aa7b01f | 173 | u32 fw_rev; |
a66098da LB |
174 | |
175 | /* | |
176 | * Running count of TX packets in flight, to avoid | |
177 | * iterating over the transmit rings each time. | |
178 | */ | |
179 | int pending_tx_pkts; | |
180 | ||
181 | struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; | |
182 | struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES]; | |
183 | ||
184 | /* PHY parameters */ | |
185 | struct ieee80211_supported_band band; | |
186 | struct ieee80211_channel channels[14]; | |
5dfd3e2c | 187 | struct ieee80211_rate rates[13]; |
a66098da | 188 | |
c46563b7 | 189 | bool radio_on; |
68ce3884 | 190 | bool radio_short_preamble; |
a43c49a8 | 191 | bool sniffer_enabled; |
0439b1f5 | 192 | bool wmm_enabled; |
a66098da | 193 | |
a66098da LB |
194 | /* XXX need to convert this to handle multiple interfaces */ |
195 | bool capture_beacon; | |
d89173f2 | 196 | u8 capture_bssid[ETH_ALEN]; |
a66098da LB |
197 | struct sk_buff *beacon_skb; |
198 | ||
199 | /* | |
200 | * This FJ worker has to be global as it is scheduled from the | |
201 | * RX handler. At this point we don't know which interface it | |
202 | * belongs to until the list of bssids waiting to complete join | |
203 | * is checked. | |
204 | */ | |
205 | struct work_struct finalize_join_worker; | |
206 | ||
207 | /* Tasklet to reclaim TX descriptors and buffers after tx */ | |
208 | struct tasklet_struct tx_reclaim_task; | |
a66098da LB |
209 | }; |
210 | ||
211 | /* Per interface specific private data */ | |
212 | struct mwl8k_vif { | |
a66098da LB |
213 | /* backpointer to parent config block */ |
214 | struct mwl8k_priv *priv; | |
215 | ||
216 | /* BSS config of AP or IBSS from mac80211*/ | |
217 | struct ieee80211_bss_conf bss_info; | |
218 | ||
219 | /* BSSID of AP or IBSS */ | |
d89173f2 LB |
220 | u8 bssid[ETH_ALEN]; |
221 | u8 mac_addr[ETH_ALEN]; | |
a66098da LB |
222 | |
223 | /* | |
224 | * Subset of supported legacy rates. | |
225 | * Intersection of AP and STA supported rates. | |
226 | */ | |
5dfd3e2c | 227 | struct ieee80211_rate legacy_rates[13]; |
a66098da LB |
228 | |
229 | /* number of supported legacy rates */ | |
230 | u8 legacy_nrates; | |
231 | ||
a66098da LB |
232 | /* Index into station database.Returned by update_sta_db call */ |
233 | u8 peer_id; | |
234 | ||
235 | /* Non AMPDU sequence number assigned by driver */ | |
236 | u16 seqno; | |
a66098da LB |
237 | }; |
238 | ||
a94cc97e | 239 | #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) |
a66098da LB |
240 | |
241 | static const struct ieee80211_channel mwl8k_channels[] = { | |
242 | { .center_freq = 2412, .hw_value = 1, }, | |
243 | { .center_freq = 2417, .hw_value = 2, }, | |
244 | { .center_freq = 2422, .hw_value = 3, }, | |
245 | { .center_freq = 2427, .hw_value = 4, }, | |
246 | { .center_freq = 2432, .hw_value = 5, }, | |
247 | { .center_freq = 2437, .hw_value = 6, }, | |
248 | { .center_freq = 2442, .hw_value = 7, }, | |
249 | { .center_freq = 2447, .hw_value = 8, }, | |
250 | { .center_freq = 2452, .hw_value = 9, }, | |
251 | { .center_freq = 2457, .hw_value = 10, }, | |
252 | { .center_freq = 2462, .hw_value = 11, }, | |
253 | }; | |
254 | ||
255 | static const struct ieee80211_rate mwl8k_rates[] = { | |
256 | { .bitrate = 10, .hw_value = 2, }, | |
257 | { .bitrate = 20, .hw_value = 4, }, | |
258 | { .bitrate = 55, .hw_value = 11, }, | |
5dfd3e2c LB |
259 | { .bitrate = 110, .hw_value = 22, }, |
260 | { .bitrate = 220, .hw_value = 44, }, | |
a66098da LB |
261 | { .bitrate = 60, .hw_value = 12, }, |
262 | { .bitrate = 90, .hw_value = 18, }, | |
a66098da LB |
263 | { .bitrate = 120, .hw_value = 24, }, |
264 | { .bitrate = 180, .hw_value = 36, }, | |
265 | { .bitrate = 240, .hw_value = 48, }, | |
266 | { .bitrate = 360, .hw_value = 72, }, | |
267 | { .bitrate = 480, .hw_value = 96, }, | |
268 | { .bitrate = 540, .hw_value = 108, }, | |
269 | }; | |
270 | ||
a66098da LB |
271 | /* Set or get info from Firmware */ |
272 | #define MWL8K_CMD_SET 0x0001 | |
273 | #define MWL8K_CMD_GET 0x0000 | |
274 | ||
275 | /* Firmware command codes */ | |
276 | #define MWL8K_CMD_CODE_DNLD 0x0001 | |
277 | #define MWL8K_CMD_GET_HW_SPEC 0x0003 | |
42fba21d | 278 | #define MWL8K_CMD_SET_HW_SPEC 0x0004 |
a66098da LB |
279 | #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 |
280 | #define MWL8K_CMD_GET_STAT 0x0014 | |
ff45fc60 LB |
281 | #define MWL8K_CMD_RADIO_CONTROL 0x001c |
282 | #define MWL8K_CMD_RF_TX_POWER 0x001e | |
08b06347 | 283 | #define MWL8K_CMD_RF_ANTENNA 0x0020 |
a66098da LB |
284 | #define MWL8K_CMD_SET_PRE_SCAN 0x0107 |
285 | #define MWL8K_CMD_SET_POST_SCAN 0x0108 | |
ff45fc60 LB |
286 | #define MWL8K_CMD_SET_RF_CHANNEL 0x010a |
287 | #define MWL8K_CMD_SET_AID 0x010d | |
288 | #define MWL8K_CMD_SET_RATE 0x0110 | |
289 | #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 | |
290 | #define MWL8K_CMD_RTS_THRESHOLD 0x0113 | |
a66098da | 291 | #define MWL8K_CMD_SET_SLOT 0x0114 |
ff45fc60 LB |
292 | #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 |
293 | #define MWL8K_CMD_SET_WMM_MODE 0x0123 | |
a66098da | 294 | #define MWL8K_CMD_MIMO_CONFIG 0x0125 |
ff45fc60 | 295 | #define MWL8K_CMD_USE_FIXED_RATE 0x0126 |
a66098da | 296 | #define MWL8K_CMD_ENABLE_SNIFFER 0x0150 |
32060e1b | 297 | #define MWL8K_CMD_SET_MAC_ADDR 0x0202 |
a66098da | 298 | #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 |
ff45fc60 | 299 | #define MWL8K_CMD_UPDATE_STADB 0x1123 |
a66098da LB |
300 | |
301 | static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize) | |
302 | { | |
303 | #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ | |
304 | snprintf(buf, bufsize, "%s", #x);\ | |
305 | return buf;\ | |
306 | } while (0) | |
ce9e2e1b | 307 | switch (cmd & ~0x8000) { |
a66098da LB |
308 | MWL8K_CMDNAME(CODE_DNLD); |
309 | MWL8K_CMDNAME(GET_HW_SPEC); | |
42fba21d | 310 | MWL8K_CMDNAME(SET_HW_SPEC); |
a66098da LB |
311 | MWL8K_CMDNAME(MAC_MULTICAST_ADR); |
312 | MWL8K_CMDNAME(GET_STAT); | |
313 | MWL8K_CMDNAME(RADIO_CONTROL); | |
314 | MWL8K_CMDNAME(RF_TX_POWER); | |
08b06347 | 315 | MWL8K_CMDNAME(RF_ANTENNA); |
a66098da LB |
316 | MWL8K_CMDNAME(SET_PRE_SCAN); |
317 | MWL8K_CMDNAME(SET_POST_SCAN); | |
318 | MWL8K_CMDNAME(SET_RF_CHANNEL); | |
ff45fc60 LB |
319 | MWL8K_CMDNAME(SET_AID); |
320 | MWL8K_CMDNAME(SET_RATE); | |
321 | MWL8K_CMDNAME(SET_FINALIZE_JOIN); | |
322 | MWL8K_CMDNAME(RTS_THRESHOLD); | |
a66098da | 323 | MWL8K_CMDNAME(SET_SLOT); |
ff45fc60 LB |
324 | MWL8K_CMDNAME(SET_EDCA_PARAMS); |
325 | MWL8K_CMDNAME(SET_WMM_MODE); | |
a66098da | 326 | MWL8K_CMDNAME(MIMO_CONFIG); |
ff45fc60 | 327 | MWL8K_CMDNAME(USE_FIXED_RATE); |
a66098da | 328 | MWL8K_CMDNAME(ENABLE_SNIFFER); |
32060e1b | 329 | MWL8K_CMDNAME(SET_MAC_ADDR); |
a66098da | 330 | MWL8K_CMDNAME(SET_RATEADAPT_MODE); |
ff45fc60 | 331 | MWL8K_CMDNAME(UPDATE_STADB); |
a66098da LB |
332 | default: |
333 | snprintf(buf, bufsize, "0x%x", cmd); | |
334 | } | |
335 | #undef MWL8K_CMDNAME | |
336 | ||
337 | return buf; | |
338 | } | |
339 | ||
340 | /* Hardware and firmware reset */ | |
341 | static void mwl8k_hw_reset(struct mwl8k_priv *priv) | |
342 | { | |
343 | iowrite32(MWL8K_H2A_INT_RESET, | |
344 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
345 | iowrite32(MWL8K_H2A_INT_RESET, | |
346 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
347 | msleep(20); | |
348 | } | |
349 | ||
350 | /* Release fw image */ | |
351 | static void mwl8k_release_fw(struct firmware **fw) | |
352 | { | |
353 | if (*fw == NULL) | |
354 | return; | |
355 | release_firmware(*fw); | |
356 | *fw = NULL; | |
357 | } | |
358 | ||
359 | static void mwl8k_release_firmware(struct mwl8k_priv *priv) | |
360 | { | |
361 | mwl8k_release_fw(&priv->fw.ucode); | |
362 | mwl8k_release_fw(&priv->fw.helper); | |
363 | } | |
364 | ||
365 | /* Request fw image */ | |
366 | static int mwl8k_request_fw(struct mwl8k_priv *priv, | |
c2c357ce | 367 | const char *fname, struct firmware **fw) |
a66098da LB |
368 | { |
369 | /* release current image */ | |
370 | if (*fw != NULL) | |
371 | mwl8k_release_fw(fw); | |
372 | ||
373 | return request_firmware((const struct firmware **)fw, | |
c2c357ce | 374 | fname, &priv->pdev->dev); |
a66098da LB |
375 | } |
376 | ||
45a390dd | 377 | static int mwl8k_request_firmware(struct mwl8k_priv *priv) |
a66098da | 378 | { |
a74b295e | 379 | struct mwl8k_device_info *di = priv->device_info; |
a66098da LB |
380 | int rc; |
381 | ||
a74b295e LB |
382 | if (di->helper_image != NULL) { |
383 | rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper); | |
384 | if (rc) { | |
385 | printk(KERN_ERR "%s: Error requesting helper " | |
386 | "firmware file %s\n", pci_name(priv->pdev), | |
387 | di->helper_image); | |
388 | return rc; | |
389 | } | |
a66098da LB |
390 | } |
391 | ||
a74b295e | 392 | rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode); |
a66098da | 393 | if (rc) { |
c2c357ce | 394 | printk(KERN_ERR "%s: Error requesting firmware file %s\n", |
a74b295e | 395 | pci_name(priv->pdev), di->fw_image); |
a66098da LB |
396 | mwl8k_release_fw(&priv->fw.helper); |
397 | return rc; | |
398 | } | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | struct mwl8k_cmd_pkt { | |
404 | __le16 code; | |
405 | __le16 length; | |
406 | __le16 seq_num; | |
407 | __le16 result; | |
408 | char payload[0]; | |
409 | } __attribute__((packed)); | |
410 | ||
411 | /* | |
412 | * Firmware loading. | |
413 | */ | |
414 | static int | |
415 | mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) | |
416 | { | |
417 | void __iomem *regs = priv->regs; | |
418 | dma_addr_t dma_addr; | |
a66098da LB |
419 | int loops; |
420 | ||
421 | dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); | |
422 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
423 | return -ENOMEM; | |
424 | ||
425 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
426 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
427 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
428 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
429 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
430 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
431 | ||
a66098da LB |
432 | loops = 1000; |
433 | do { | |
434 | u32 int_code; | |
435 | ||
436 | int_code = ioread32(regs + MWL8K_HIU_INT_CODE); | |
437 | if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { | |
438 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
a66098da LB |
439 | break; |
440 | } | |
441 | ||
3d76e82c | 442 | cond_resched(); |
a66098da LB |
443 | udelay(1); |
444 | } while (--loops); | |
445 | ||
446 | pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); | |
447 | ||
d4b70570 | 448 | return loops ? 0 : -ETIMEDOUT; |
a66098da LB |
449 | } |
450 | ||
451 | static int mwl8k_load_fw_image(struct mwl8k_priv *priv, | |
452 | const u8 *data, size_t length) | |
453 | { | |
454 | struct mwl8k_cmd_pkt *cmd; | |
455 | int done; | |
456 | int rc = 0; | |
457 | ||
458 | cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); | |
459 | if (cmd == NULL) | |
460 | return -ENOMEM; | |
461 | ||
462 | cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); | |
463 | cmd->seq_num = 0; | |
464 | cmd->result = 0; | |
465 | ||
466 | done = 0; | |
467 | while (length) { | |
468 | int block_size = length > 256 ? 256 : length; | |
469 | ||
470 | memcpy(cmd->payload, data + done, block_size); | |
471 | cmd->length = cpu_to_le16(block_size); | |
472 | ||
473 | rc = mwl8k_send_fw_load_cmd(priv, cmd, | |
474 | sizeof(*cmd) + block_size); | |
475 | if (rc) | |
476 | break; | |
477 | ||
478 | done += block_size; | |
479 | length -= block_size; | |
480 | } | |
481 | ||
482 | if (!rc) { | |
483 | cmd->length = 0; | |
484 | rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); | |
485 | } | |
486 | ||
487 | kfree(cmd); | |
488 | ||
489 | return rc; | |
490 | } | |
491 | ||
492 | static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, | |
493 | const u8 *data, size_t length) | |
494 | { | |
495 | unsigned char *buffer; | |
496 | int may_continue, rc = 0; | |
497 | u32 done, prev_block_size; | |
498 | ||
499 | buffer = kmalloc(1024, GFP_KERNEL); | |
500 | if (buffer == NULL) | |
501 | return -ENOMEM; | |
502 | ||
503 | done = 0; | |
504 | prev_block_size = 0; | |
505 | may_continue = 1000; | |
506 | while (may_continue > 0) { | |
507 | u32 block_size; | |
508 | ||
509 | block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); | |
510 | if (block_size & 1) { | |
511 | block_size &= ~1; | |
512 | may_continue--; | |
513 | } else { | |
514 | done += prev_block_size; | |
515 | length -= prev_block_size; | |
516 | } | |
517 | ||
518 | if (block_size > 1024 || block_size > length) { | |
519 | rc = -EOVERFLOW; | |
520 | break; | |
521 | } | |
522 | ||
523 | if (length == 0) { | |
524 | rc = 0; | |
525 | break; | |
526 | } | |
527 | ||
528 | if (block_size == 0) { | |
529 | rc = -EPROTO; | |
530 | may_continue--; | |
531 | udelay(1); | |
532 | continue; | |
533 | } | |
534 | ||
535 | prev_block_size = block_size; | |
536 | memcpy(buffer, data + done, block_size); | |
537 | ||
538 | rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); | |
539 | if (rc) | |
540 | break; | |
541 | } | |
542 | ||
543 | if (!rc && length != 0) | |
544 | rc = -EREMOTEIO; | |
545 | ||
546 | kfree(buffer); | |
547 | ||
548 | return rc; | |
549 | } | |
550 | ||
c2c357ce | 551 | static int mwl8k_load_firmware(struct ieee80211_hw *hw) |
a66098da | 552 | { |
c2c357ce LB |
553 | struct mwl8k_priv *priv = hw->priv; |
554 | struct firmware *fw = priv->fw.ucode; | |
eae74e65 | 555 | struct mwl8k_device_info *di = priv->device_info; |
c2c357ce LB |
556 | int rc; |
557 | int loops; | |
558 | ||
559 | if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) { | |
560 | struct firmware *helper = priv->fw.helper; | |
a66098da | 561 | |
c2c357ce LB |
562 | if (helper == NULL) { |
563 | printk(KERN_ERR "%s: helper image needed but none " | |
564 | "given\n", pci_name(priv->pdev)); | |
565 | return -EINVAL; | |
566 | } | |
a66098da | 567 | |
c2c357ce | 568 | rc = mwl8k_load_fw_image(priv, helper->data, helper->size); |
a66098da LB |
569 | if (rc) { |
570 | printk(KERN_ERR "%s: unable to load firmware " | |
c2c357ce | 571 | "helper image\n", pci_name(priv->pdev)); |
a66098da LB |
572 | return rc; |
573 | } | |
574 | msleep(1); | |
575 | ||
c2c357ce | 576 | rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); |
a66098da | 577 | } else { |
c2c357ce | 578 | rc = mwl8k_load_fw_image(priv, fw->data, fw->size); |
a66098da LB |
579 | } |
580 | ||
581 | if (rc) { | |
c2c357ce LB |
582 | printk(KERN_ERR "%s: unable to load firmware image\n", |
583 | pci_name(priv->pdev)); | |
a66098da LB |
584 | return rc; |
585 | } | |
586 | ||
eae74e65 LB |
587 | if (di->modes & BIT(NL80211_IFTYPE_AP)) |
588 | iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR); | |
589 | else | |
590 | iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); | |
a66098da LB |
591 | msleep(1); |
592 | ||
593 | loops = 200000; | |
594 | do { | |
eae74e65 LB |
595 | u32 ready_code; |
596 | ||
597 | ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
598 | if (ready_code == MWL8K_FWAP_READY) { | |
599 | priv->ap_fw = 1; | |
600 | break; | |
601 | } else if (ready_code == MWL8K_FWSTA_READY) { | |
602 | priv->ap_fw = 0; | |
a66098da | 603 | break; |
eae74e65 LB |
604 | } |
605 | ||
606 | cond_resched(); | |
a66098da LB |
607 | udelay(1); |
608 | } while (--loops); | |
609 | ||
610 | return loops ? 0 : -ETIMEDOUT; | |
611 | } | |
612 | ||
613 | ||
614 | /* | |
615 | * Defines shared between transmission and reception. | |
616 | */ | |
617 | /* HT control fields for firmware */ | |
618 | struct ewc_ht_info { | |
619 | __le16 control1; | |
620 | __le16 control2; | |
621 | __le16 control3; | |
622 | } __attribute__((packed)); | |
623 | ||
624 | /* Firmware Station database operations */ | |
625 | #define MWL8K_STA_DB_ADD_ENTRY 0 | |
626 | #define MWL8K_STA_DB_MODIFY_ENTRY 1 | |
627 | #define MWL8K_STA_DB_DEL_ENTRY 2 | |
628 | #define MWL8K_STA_DB_FLUSH 3 | |
629 | ||
630 | /* Peer Entry flags - used to define the type of the peer node */ | |
631 | #define MWL8K_PEER_TYPE_ACCESSPOINT 2 | |
a66098da | 632 | |
5dfd3e2c | 633 | #define MWL8K_IEEE_LEGACY_DATA_RATES 13 |
a66098da | 634 | #define MWL8K_MCS_BITMAP_SIZE 16 |
a66098da LB |
635 | |
636 | struct peer_capability_info { | |
637 | /* Peer type - AP vs. STA. */ | |
638 | __u8 peer_type; | |
639 | ||
640 | /* Basic 802.11 capabilities from assoc resp. */ | |
641 | __le16 basic_caps; | |
642 | ||
643 | /* Set if peer supports 802.11n high throughput (HT). */ | |
644 | __u8 ht_support; | |
645 | ||
646 | /* Valid if HT is supported. */ | |
647 | __le16 ht_caps; | |
648 | __u8 extended_ht_caps; | |
649 | struct ewc_ht_info ewc_info; | |
650 | ||
651 | /* Legacy rate table. Intersection of our rates and peer rates. */ | |
652 | __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES]; | |
653 | ||
654 | /* HT rate table. Intersection of our rates and peer rates. */ | |
655 | __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE]; | |
c23b5a69 | 656 | __u8 pad[16]; |
a66098da LB |
657 | |
658 | /* If set, interoperability mode, no proprietary extensions. */ | |
659 | __u8 interop; | |
660 | __u8 pad2; | |
661 | __u8 station_id; | |
662 | __le16 amsdu_enabled; | |
663 | } __attribute__((packed)); | |
664 | ||
665 | /* Inline functions to manipulate QoS field in data descriptor. */ | |
a66098da LB |
666 | static inline u16 mwl8k_qos_setbit_eosp(u16 qos) |
667 | { | |
668 | u16 val_mask = 1 << 4; | |
669 | ||
670 | /* End of Service Period Bit 4 */ | |
671 | return qos | val_mask; | |
672 | } | |
673 | ||
674 | static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy) | |
675 | { | |
676 | u16 val_mask = 0x3; | |
677 | u8 shift = 5; | |
678 | u16 qos_mask = ~(val_mask << shift); | |
679 | ||
680 | /* Ack Policy Bit 5-6 */ | |
681 | return (qos & qos_mask) | ((ack_policy & val_mask) << shift); | |
682 | } | |
683 | ||
684 | static inline u16 mwl8k_qos_setbit_amsdu(u16 qos) | |
685 | { | |
686 | u16 val_mask = 1 << 7; | |
687 | ||
688 | /* AMSDU present Bit 7 */ | |
689 | return qos | val_mask; | |
690 | } | |
691 | ||
692 | static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len) | |
693 | { | |
694 | u16 val_mask = 0xff; | |
695 | u8 shift = 8; | |
696 | u16 qos_mask = ~(val_mask << shift); | |
697 | ||
698 | /* Queue Length Bits 8-15 */ | |
699 | return (qos & qos_mask) | ((len & val_mask) << shift); | |
700 | } | |
701 | ||
702 | /* DMA header used by firmware and hardware. */ | |
703 | struct mwl8k_dma_data { | |
704 | __le16 fwlen; | |
705 | struct ieee80211_hdr wh; | |
706 | } __attribute__((packed)); | |
707 | ||
708 | /* Routines to add/remove DMA header from skb. */ | |
76266b2a | 709 | static inline void mwl8k_remove_dma_header(struct sk_buff *skb) |
a66098da | 710 | { |
76266b2a | 711 | struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data; |
a66098da | 712 | void *dst, *src = &tr->wh; |
76266b2a | 713 | int hdrlen = ieee80211_hdrlen(tr->wh.frame_control); |
a66098da LB |
714 | u16 space = sizeof(struct mwl8k_dma_data) - hdrlen; |
715 | ||
716 | dst = (void *)tr + space; | |
717 | if (dst != src) { | |
718 | memmove(dst, src, hdrlen); | |
719 | skb_pull(skb, space); | |
720 | } | |
a66098da LB |
721 | } |
722 | ||
76266b2a | 723 | static inline void mwl8k_add_dma_header(struct sk_buff *skb) |
a66098da LB |
724 | { |
725 | struct ieee80211_hdr *wh; | |
726 | u32 hdrlen, pktlen; | |
727 | struct mwl8k_dma_data *tr; | |
728 | ||
729 | wh = (struct ieee80211_hdr *)skb->data; | |
730 | hdrlen = ieee80211_hdrlen(wh->frame_control); | |
731 | pktlen = skb->len; | |
732 | ||
733 | /* | |
734 | * Copy up/down the 802.11 header; the firmware requires | |
735 | * we present a 2-byte payload length followed by a | |
736 | * 4-address header (w/o QoS), followed (optionally) by | |
737 | * any WEP/ExtIV header (but only filled in for CCMP). | |
738 | */ | |
739 | if (hdrlen != sizeof(struct mwl8k_dma_data)) | |
740 | skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen); | |
741 | ||
742 | tr = (struct mwl8k_dma_data *)skb->data; | |
743 | if (wh != &tr->wh) | |
744 | memmove(&tr->wh, wh, hdrlen); | |
745 | ||
746 | /* Clear addr4 */ | |
d89173f2 | 747 | memset(tr->wh.addr4, 0, ETH_ALEN); |
a66098da LB |
748 | |
749 | /* | |
750 | * Firmware length is the length of the fully formed "802.11 | |
751 | * payload". That is, everything except for the 802.11 header. | |
752 | * This includes all crypto material including the MIC. | |
753 | */ | |
754 | tr->fwlen = cpu_to_le16(pktlen - hdrlen); | |
a66098da LB |
755 | } |
756 | ||
757 | ||
758 | /* | |
6f6d1e9a LB |
759 | * Packet reception for 88w8366. |
760 | */ | |
761 | struct mwl8k_rxd_8366 { | |
762 | __le16 pkt_len; | |
763 | __u8 sq2; | |
764 | __u8 rate; | |
765 | __le32 pkt_phys_addr; | |
766 | __le32 next_rxd_phys_addr; | |
767 | __le16 qos_control; | |
768 | __le16 htsig2; | |
769 | __le32 hw_rssi_info; | |
770 | __le32 hw_noise_floor_info; | |
771 | __u8 noise_floor; | |
772 | __u8 pad0[3]; | |
773 | __u8 rssi; | |
774 | __u8 rx_status; | |
775 | __u8 channel; | |
776 | __u8 rx_ctrl; | |
777 | } __attribute__((packed)); | |
778 | ||
779 | #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80 | |
780 | ||
781 | static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr) | |
782 | { | |
783 | struct mwl8k_rxd_8366 *rxd = _rxd; | |
784 | ||
785 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
786 | rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST; | |
787 | } | |
788 | ||
789 | static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len) | |
790 | { | |
791 | struct mwl8k_rxd_8366 *rxd = _rxd; | |
792 | ||
793 | rxd->pkt_len = cpu_to_le16(len); | |
794 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
795 | wmb(); | |
796 | rxd->rx_ctrl = 0; | |
797 | } | |
798 | ||
799 | static int | |
800 | mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status) | |
801 | { | |
802 | struct mwl8k_rxd_8366 *rxd = _rxd; | |
803 | ||
804 | if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST)) | |
805 | return -1; | |
806 | rmb(); | |
807 | ||
808 | memset(status, 0, sizeof(*status)); | |
809 | ||
810 | status->signal = -rxd->rssi; | |
811 | status->noise = -rxd->noise_floor; | |
812 | ||
813 | if (rxd->rate & 0x80) { | |
814 | status->flag |= RX_FLAG_HT; | |
815 | status->rate_idx = rxd->rate & 0x7f; | |
816 | } else { | |
817 | int i; | |
818 | ||
819 | for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) { | |
820 | if (mwl8k_rates[i].hw_value == rxd->rate) { | |
821 | status->rate_idx = i; | |
822 | break; | |
823 | } | |
824 | } | |
825 | } | |
826 | ||
827 | status->band = IEEE80211_BAND_2GHZ; | |
828 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
829 | ||
830 | return le16_to_cpu(rxd->pkt_len); | |
831 | } | |
832 | ||
833 | static struct rxd_ops rxd_8366_ops = { | |
834 | .rxd_size = sizeof(struct mwl8k_rxd_8366), | |
835 | .rxd_init = mwl8k_rxd_8366_init, | |
836 | .rxd_refill = mwl8k_rxd_8366_refill, | |
837 | .rxd_process = mwl8k_rxd_8366_process, | |
838 | }; | |
839 | ||
840 | /* | |
841 | * Packet reception for 88w8687. | |
a66098da | 842 | */ |
54bc3a0d | 843 | struct mwl8k_rxd_8687 { |
a66098da LB |
844 | __le16 pkt_len; |
845 | __u8 link_quality; | |
846 | __u8 noise_level; | |
847 | __le32 pkt_phys_addr; | |
45eb400d | 848 | __le32 next_rxd_phys_addr; |
a66098da LB |
849 | __le16 qos_control; |
850 | __le16 rate_info; | |
851 | __le32 pad0[4]; | |
852 | __u8 rssi; | |
853 | __u8 channel; | |
854 | __le16 pad1; | |
855 | __u8 rx_ctrl; | |
856 | __u8 rx_status; | |
857 | __u8 pad2[2]; | |
858 | } __attribute__((packed)); | |
859 | ||
54bc3a0d LB |
860 | #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000 |
861 | #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) | |
862 | #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) | |
863 | #define MWL8K_8687_RATE_INFO_40MHZ 0x0004 | |
864 | #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002 | |
865 | #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001 | |
866 | ||
867 | #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02 | |
868 | ||
869 | static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr) | |
870 | { | |
871 | struct mwl8k_rxd_8687 *rxd = _rxd; | |
872 | ||
873 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
874 | rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST; | |
875 | } | |
876 | ||
877 | static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len) | |
878 | { | |
879 | struct mwl8k_rxd_8687 *rxd = _rxd; | |
880 | ||
881 | rxd->pkt_len = cpu_to_le16(len); | |
882 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
883 | wmb(); | |
884 | rxd->rx_ctrl = 0; | |
885 | } | |
886 | ||
887 | static int | |
888 | mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status) | |
889 | { | |
890 | struct mwl8k_rxd_8687 *rxd = _rxd; | |
891 | u16 rate_info; | |
892 | ||
893 | if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST)) | |
894 | return -1; | |
895 | rmb(); | |
896 | ||
897 | rate_info = le16_to_cpu(rxd->rate_info); | |
898 | ||
899 | memset(status, 0, sizeof(*status)); | |
900 | ||
901 | status->signal = -rxd->rssi; | |
902 | status->noise = -rxd->noise_level; | |
903 | status->qual = rxd->link_quality; | |
904 | status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info); | |
905 | status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info); | |
906 | ||
907 | if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE) | |
908 | status->flag |= RX_FLAG_SHORTPRE; | |
909 | if (rate_info & MWL8K_8687_RATE_INFO_40MHZ) | |
910 | status->flag |= RX_FLAG_40MHZ; | |
911 | if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI) | |
912 | status->flag |= RX_FLAG_SHORT_GI; | |
913 | if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT) | |
914 | status->flag |= RX_FLAG_HT; | |
915 | ||
916 | status->band = IEEE80211_BAND_2GHZ; | |
917 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
918 | ||
919 | return le16_to_cpu(rxd->pkt_len); | |
920 | } | |
921 | ||
922 | static struct rxd_ops rxd_8687_ops = { | |
923 | .rxd_size = sizeof(struct mwl8k_rxd_8687), | |
924 | .rxd_init = mwl8k_rxd_8687_init, | |
925 | .rxd_refill = mwl8k_rxd_8687_refill, | |
926 | .rxd_process = mwl8k_rxd_8687_process, | |
927 | }; | |
928 | ||
929 | ||
a66098da LB |
930 | #define MWL8K_RX_DESCS 256 |
931 | #define MWL8K_RX_MAXSZ 3800 | |
932 | ||
933 | static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) | |
934 | { | |
935 | struct mwl8k_priv *priv = hw->priv; | |
936 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
937 | int size; | |
938 | int i; | |
939 | ||
45eb400d LB |
940 | rxq->rxd_count = 0; |
941 | rxq->head = 0; | |
942 | rxq->tail = 0; | |
a66098da | 943 | |
54bc3a0d | 944 | size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; |
a66098da | 945 | |
45eb400d LB |
946 | rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); |
947 | if (rxq->rxd == NULL) { | |
a66098da | 948 | printk(KERN_ERR "%s: failed to alloc RX descriptors\n", |
c2c357ce | 949 | wiphy_name(hw->wiphy)); |
a66098da LB |
950 | return -ENOMEM; |
951 | } | |
45eb400d | 952 | memset(rxq->rxd, 0, size); |
a66098da | 953 | |
788838eb LB |
954 | rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL); |
955 | if (rxq->buf == NULL) { | |
a66098da | 956 | printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", |
c2c357ce | 957 | wiphy_name(hw->wiphy)); |
45eb400d | 958 | pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); |
a66098da LB |
959 | return -ENOMEM; |
960 | } | |
788838eb | 961 | memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf)); |
a66098da LB |
962 | |
963 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
54bc3a0d LB |
964 | int desc_size; |
965 | void *rxd; | |
a66098da | 966 | int nexti; |
54bc3a0d LB |
967 | dma_addr_t next_dma_addr; |
968 | ||
969 | desc_size = priv->rxd_ops->rxd_size; | |
970 | rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); | |
a66098da | 971 | |
54bc3a0d LB |
972 | nexti = i + 1; |
973 | if (nexti == MWL8K_RX_DESCS) | |
974 | nexti = 0; | |
975 | next_dma_addr = rxq->rxd_dma + (nexti * desc_size); | |
a66098da | 976 | |
54bc3a0d | 977 | priv->rxd_ops->rxd_init(rxd, next_dma_addr); |
a66098da LB |
978 | } |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) | |
984 | { | |
985 | struct mwl8k_priv *priv = hw->priv; | |
986 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
987 | int refilled; | |
988 | ||
989 | refilled = 0; | |
45eb400d | 990 | while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { |
a66098da | 991 | struct sk_buff *skb; |
788838eb | 992 | dma_addr_t addr; |
a66098da | 993 | int rx; |
54bc3a0d | 994 | void *rxd; |
a66098da LB |
995 | |
996 | skb = dev_alloc_skb(MWL8K_RX_MAXSZ); | |
997 | if (skb == NULL) | |
998 | break; | |
999 | ||
788838eb LB |
1000 | addr = pci_map_single(priv->pdev, skb->data, |
1001 | MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); | |
a66098da | 1002 | |
54bc3a0d LB |
1003 | rxq->rxd_count++; |
1004 | rx = rxq->tail++; | |
1005 | if (rxq->tail == MWL8K_RX_DESCS) | |
1006 | rxq->tail = 0; | |
788838eb LB |
1007 | rxq->buf[rx].skb = skb; |
1008 | pci_unmap_addr_set(&rxq->buf[rx], dma, addr); | |
54bc3a0d LB |
1009 | |
1010 | rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); | |
1011 | priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); | |
a66098da LB |
1012 | |
1013 | refilled++; | |
1014 | } | |
1015 | ||
1016 | return refilled; | |
1017 | } | |
1018 | ||
1019 | /* Must be called only when the card's reception is completely halted */ | |
1020 | static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) | |
1021 | { | |
1022 | struct mwl8k_priv *priv = hw->priv; | |
1023 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
1024 | int i; | |
1025 | ||
1026 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
788838eb LB |
1027 | if (rxq->buf[i].skb != NULL) { |
1028 | pci_unmap_single(priv->pdev, | |
1029 | pci_unmap_addr(&rxq->buf[i], dma), | |
1030 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
1031 | pci_unmap_addr_set(&rxq->buf[i], dma, 0); | |
1032 | ||
1033 | kfree_skb(rxq->buf[i].skb); | |
1034 | rxq->buf[i].skb = NULL; | |
a66098da LB |
1035 | } |
1036 | } | |
1037 | ||
788838eb LB |
1038 | kfree(rxq->buf); |
1039 | rxq->buf = NULL; | |
a66098da LB |
1040 | |
1041 | pci_free_consistent(priv->pdev, | |
54bc3a0d | 1042 | MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, |
45eb400d LB |
1043 | rxq->rxd, rxq->rxd_dma); |
1044 | rxq->rxd = NULL; | |
a66098da LB |
1045 | } |
1046 | ||
1047 | ||
1048 | /* | |
1049 | * Scan a list of BSSIDs to process for finalize join. | |
1050 | * Allows for extension to process multiple BSSIDs. | |
1051 | */ | |
1052 | static inline int | |
1053 | mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) | |
1054 | { | |
1055 | return priv->capture_beacon && | |
1056 | ieee80211_is_beacon(wh->frame_control) && | |
1057 | !compare_ether_addr(wh->addr3, priv->capture_bssid); | |
1058 | } | |
1059 | ||
3779752d LB |
1060 | static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, |
1061 | struct sk_buff *skb) | |
a66098da | 1062 | { |
3779752d LB |
1063 | struct mwl8k_priv *priv = hw->priv; |
1064 | ||
a66098da | 1065 | priv->capture_beacon = false; |
d89173f2 | 1066 | memset(priv->capture_bssid, 0, ETH_ALEN); |
a66098da LB |
1067 | |
1068 | /* | |
1069 | * Use GFP_ATOMIC as rxq_process is called from | |
1070 | * the primary interrupt handler, memory allocation call | |
1071 | * must not sleep. | |
1072 | */ | |
1073 | priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); | |
1074 | if (priv->beacon_skb != NULL) | |
3779752d | 1075 | ieee80211_queue_work(hw, &priv->finalize_join_worker); |
a66098da LB |
1076 | } |
1077 | ||
1078 | static int rxq_process(struct ieee80211_hw *hw, int index, int limit) | |
1079 | { | |
1080 | struct mwl8k_priv *priv = hw->priv; | |
1081 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
1082 | int processed; | |
1083 | ||
1084 | processed = 0; | |
45eb400d | 1085 | while (rxq->rxd_count && limit--) { |
a66098da | 1086 | struct sk_buff *skb; |
54bc3a0d LB |
1087 | void *rxd; |
1088 | int pkt_len; | |
a66098da | 1089 | struct ieee80211_rx_status status; |
a66098da | 1090 | |
788838eb | 1091 | skb = rxq->buf[rxq->head].skb; |
d25f9f13 LB |
1092 | if (skb == NULL) |
1093 | break; | |
54bc3a0d LB |
1094 | |
1095 | rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); | |
1096 | ||
1097 | pkt_len = priv->rxd_ops->rxd_process(rxd, &status); | |
1098 | if (pkt_len < 0) | |
1099 | break; | |
1100 | ||
788838eb LB |
1101 | rxq->buf[rxq->head].skb = NULL; |
1102 | ||
1103 | pci_unmap_single(priv->pdev, | |
1104 | pci_unmap_addr(&rxq->buf[rxq->head], dma), | |
1105 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
1106 | pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); | |
a66098da | 1107 | |
54bc3a0d LB |
1108 | rxq->head++; |
1109 | if (rxq->head == MWL8K_RX_DESCS) | |
1110 | rxq->head = 0; | |
1111 | ||
45eb400d | 1112 | rxq->rxd_count--; |
a66098da | 1113 | |
54bc3a0d | 1114 | skb_put(skb, pkt_len); |
76266b2a | 1115 | mwl8k_remove_dma_header(skb); |
a66098da | 1116 | |
a66098da | 1117 | /* |
c2c357ce LB |
1118 | * Check for a pending join operation. Save a |
1119 | * copy of the beacon and schedule a tasklet to | |
1120 | * send a FINALIZE_JOIN command to the firmware. | |
a66098da | 1121 | */ |
54bc3a0d | 1122 | if (mwl8k_capture_bssid(priv, (void *)skb->data)) |
3779752d | 1123 | mwl8k_save_beacon(hw, skb); |
a66098da | 1124 | |
f1d58c25 JB |
1125 | memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); |
1126 | ieee80211_rx_irqsafe(hw, skb); | |
a66098da LB |
1127 | |
1128 | processed++; | |
1129 | } | |
1130 | ||
1131 | return processed; | |
1132 | } | |
1133 | ||
1134 | ||
1135 | /* | |
1136 | * Packet transmission. | |
1137 | */ | |
1138 | ||
a66098da LB |
1139 | /* Transmit packet ACK policy */ |
1140 | #define MWL8K_TXD_ACK_POLICY_NORMAL 0 | |
a66098da LB |
1141 | #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3 |
1142 | ||
a66098da LB |
1143 | #define MWL8K_TXD_STATUS_OK 0x00000001 |
1144 | #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 | |
1145 | #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 | |
1146 | #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 | |
a66098da | 1147 | #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 |
a66098da LB |
1148 | |
1149 | struct mwl8k_tx_desc { | |
1150 | __le32 status; | |
1151 | __u8 data_rate; | |
1152 | __u8 tx_priority; | |
1153 | __le16 qos_control; | |
1154 | __le32 pkt_phys_addr; | |
1155 | __le16 pkt_len; | |
d89173f2 | 1156 | __u8 dest_MAC_addr[ETH_ALEN]; |
45eb400d | 1157 | __le32 next_txd_phys_addr; |
a66098da LB |
1158 | __le32 reserved; |
1159 | __le16 rate_info; | |
1160 | __u8 peer_id; | |
1161 | __u8 tx_frag_cnt; | |
1162 | } __attribute__((packed)); | |
1163 | ||
1164 | #define MWL8K_TX_DESCS 128 | |
1165 | ||
1166 | static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) | |
1167 | { | |
1168 | struct mwl8k_priv *priv = hw->priv; | |
1169 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1170 | int size; | |
1171 | int i; | |
1172 | ||
45eb400d LB |
1173 | memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats)); |
1174 | txq->stats.limit = MWL8K_TX_DESCS; | |
1175 | txq->head = 0; | |
1176 | txq->tail = 0; | |
a66098da LB |
1177 | |
1178 | size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); | |
1179 | ||
45eb400d LB |
1180 | txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); |
1181 | if (txq->txd == NULL) { | |
a66098da | 1182 | printk(KERN_ERR "%s: failed to alloc TX descriptors\n", |
c2c357ce | 1183 | wiphy_name(hw->wiphy)); |
a66098da LB |
1184 | return -ENOMEM; |
1185 | } | |
45eb400d | 1186 | memset(txq->txd, 0, size); |
a66098da | 1187 | |
45eb400d LB |
1188 | txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL); |
1189 | if (txq->skb == NULL) { | |
a66098da | 1190 | printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", |
c2c357ce | 1191 | wiphy_name(hw->wiphy)); |
45eb400d | 1192 | pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); |
a66098da LB |
1193 | return -ENOMEM; |
1194 | } | |
45eb400d | 1195 | memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb)); |
a66098da LB |
1196 | |
1197 | for (i = 0; i < MWL8K_TX_DESCS; i++) { | |
1198 | struct mwl8k_tx_desc *tx_desc; | |
1199 | int nexti; | |
1200 | ||
45eb400d | 1201 | tx_desc = txq->txd + i; |
a66098da LB |
1202 | nexti = (i + 1) % MWL8K_TX_DESCS; |
1203 | ||
1204 | tx_desc->status = 0; | |
45eb400d LB |
1205 | tx_desc->next_txd_phys_addr = |
1206 | cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); | |
a66098da LB |
1207 | } |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
1212 | static inline void mwl8k_tx_start(struct mwl8k_priv *priv) | |
1213 | { | |
1214 | iowrite32(MWL8K_H2A_INT_PPA_READY, | |
1215 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1216 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1217 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1218 | ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
1219 | } | |
1220 | ||
a66098da LB |
1221 | struct mwl8k_txq_info { |
1222 | u32 fw_owned; | |
1223 | u32 drv_owned; | |
1224 | u32 unused; | |
1225 | u32 len; | |
1226 | u32 head; | |
1227 | u32 tail; | |
1228 | }; | |
1229 | ||
1230 | static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv, | |
c3f967d3 | 1231 | struct mwl8k_txq_info *txinfo) |
a66098da LB |
1232 | { |
1233 | int count, desc, status; | |
1234 | struct mwl8k_tx_queue *txq; | |
1235 | struct mwl8k_tx_desc *tx_desc; | |
1236 | int ndescs = 0; | |
1237 | ||
c3f967d3 LB |
1238 | memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info)); |
1239 | ||
c3f967d3 | 1240 | for (count = 0; count < MWL8K_TX_QUEUES; count++) { |
a66098da | 1241 | txq = priv->txq + count; |
45eb400d LB |
1242 | txinfo[count].len = txq->stats.len; |
1243 | txinfo[count].head = txq->head; | |
1244 | txinfo[count].tail = txq->tail; | |
a66098da | 1245 | for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { |
45eb400d | 1246 | tx_desc = txq->txd + desc; |
a66098da LB |
1247 | status = le32_to_cpu(tx_desc->status); |
1248 | ||
1249 | if (status & MWL8K_TXD_STATUS_FW_OWNED) | |
1250 | txinfo[count].fw_owned++; | |
1251 | else | |
1252 | txinfo[count].drv_owned++; | |
1253 | ||
1254 | if (tx_desc->pkt_len == 0) | |
1255 | txinfo[count].unused++; | |
1256 | } | |
1257 | } | |
a66098da LB |
1258 | |
1259 | return ndescs; | |
1260 | } | |
1261 | ||
618952a7 | 1262 | /* |
88de754a | 1263 | * Must be called with priv->fw_mutex held and tx queues stopped. |
618952a7 | 1264 | */ |
950d5b01 | 1265 | static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) |
a66098da | 1266 | { |
a66098da | 1267 | struct mwl8k_priv *priv = hw->priv; |
88de754a | 1268 | DECLARE_COMPLETION_ONSTACK(tx_wait); |
ce9e2e1b LB |
1269 | u32 count; |
1270 | unsigned long timeout; | |
a66098da LB |
1271 | |
1272 | might_sleep(); | |
1273 | ||
a66098da | 1274 | spin_lock_bh(&priv->tx_lock); |
88de754a LB |
1275 | count = priv->pending_tx_pkts; |
1276 | if (count) | |
1277 | priv->tx_wait = &tx_wait; | |
a66098da LB |
1278 | spin_unlock_bh(&priv->tx_lock); |
1279 | ||
1280 | if (count) { | |
c3f967d3 | 1281 | struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES]; |
a66098da LB |
1282 | int index; |
1283 | int newcount; | |
1284 | ||
88de754a | 1285 | timeout = wait_for_completion_timeout(&tx_wait, |
618952a7 | 1286 | msecs_to_jiffies(5000)); |
a66098da LB |
1287 | if (timeout) |
1288 | return 0; | |
1289 | ||
1290 | spin_lock_bh(&priv->tx_lock); | |
1291 | priv->tx_wait = NULL; | |
88de754a LB |
1292 | newcount = priv->pending_tx_pkts; |
1293 | mwl8k_scan_tx_ring(priv, txinfo); | |
a66098da LB |
1294 | spin_unlock_bh(&priv->tx_lock); |
1295 | ||
618952a7 | 1296 | printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n", |
950d5b01 | 1297 | __func__, __LINE__, count, newcount); |
a66098da | 1298 | |
c3f967d3 | 1299 | for (index = 0; index < MWL8K_TX_QUEUES; index++) |
c2c357ce LB |
1300 | printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u " |
1301 | "DRV:%u U:%u\n", | |
a66098da LB |
1302 | index, |
1303 | txinfo[index].len, | |
1304 | txinfo[index].head, | |
1305 | txinfo[index].tail, | |
1306 | txinfo[index].fw_owned, | |
1307 | txinfo[index].drv_owned, | |
1308 | txinfo[index].unused); | |
ce9e2e1b | 1309 | |
a66098da LB |
1310 | return -ETIMEDOUT; |
1311 | } | |
1312 | ||
1313 | return 0; | |
1314 | } | |
1315 | ||
c23b5a69 LB |
1316 | #define MWL8K_TXD_SUCCESS(status) \ |
1317 | ((status) & (MWL8K_TXD_STATUS_OK | \ | |
1318 | MWL8K_TXD_STATUS_OK_RETRY | \ | |
1319 | MWL8K_TXD_STATUS_OK_MORE_RETRY)) | |
a66098da LB |
1320 | |
1321 | static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force) | |
1322 | { | |
1323 | struct mwl8k_priv *priv = hw->priv; | |
1324 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1325 | int wake = 0; | |
1326 | ||
45eb400d | 1327 | while (txq->stats.len > 0) { |
a66098da | 1328 | int tx; |
a66098da LB |
1329 | struct mwl8k_tx_desc *tx_desc; |
1330 | unsigned long addr; | |
ce9e2e1b | 1331 | int size; |
a66098da LB |
1332 | struct sk_buff *skb; |
1333 | struct ieee80211_tx_info *info; | |
1334 | u32 status; | |
1335 | ||
45eb400d LB |
1336 | tx = txq->head; |
1337 | tx_desc = txq->txd + tx; | |
a66098da LB |
1338 | |
1339 | status = le32_to_cpu(tx_desc->status); | |
1340 | ||
1341 | if (status & MWL8K_TXD_STATUS_FW_OWNED) { | |
1342 | if (!force) | |
1343 | break; | |
1344 | tx_desc->status &= | |
1345 | ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); | |
1346 | } | |
1347 | ||
45eb400d LB |
1348 | txq->head = (tx + 1) % MWL8K_TX_DESCS; |
1349 | BUG_ON(txq->stats.len == 0); | |
1350 | txq->stats.len--; | |
a66098da LB |
1351 | priv->pending_tx_pkts--; |
1352 | ||
1353 | addr = le32_to_cpu(tx_desc->pkt_phys_addr); | |
ce9e2e1b | 1354 | size = le16_to_cpu(tx_desc->pkt_len); |
45eb400d LB |
1355 | skb = txq->skb[tx]; |
1356 | txq->skb[tx] = NULL; | |
a66098da LB |
1357 | |
1358 | BUG_ON(skb == NULL); | |
1359 | pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); | |
1360 | ||
76266b2a | 1361 | mwl8k_remove_dma_header(skb); |
a66098da LB |
1362 | |
1363 | /* Mark descriptor as unused */ | |
1364 | tx_desc->pkt_phys_addr = 0; | |
1365 | tx_desc->pkt_len = 0; | |
1366 | ||
a66098da LB |
1367 | info = IEEE80211_SKB_CB(skb); |
1368 | ieee80211_tx_info_clear_status(info); | |
ce9e2e1b | 1369 | if (MWL8K_TXD_SUCCESS(status)) |
a66098da | 1370 | info->flags |= IEEE80211_TX_STAT_ACK; |
a66098da LB |
1371 | |
1372 | ieee80211_tx_status_irqsafe(hw, skb); | |
1373 | ||
618952a7 | 1374 | wake = 1; |
a66098da LB |
1375 | } |
1376 | ||
618952a7 | 1377 | if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex)) |
a66098da LB |
1378 | ieee80211_wake_queue(hw, index); |
1379 | } | |
1380 | ||
1381 | /* must be called only when the card's transmit is completely halted */ | |
1382 | static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) | |
1383 | { | |
1384 | struct mwl8k_priv *priv = hw->priv; | |
1385 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1386 | ||
1387 | mwl8k_txq_reclaim(hw, index, 1); | |
1388 | ||
45eb400d LB |
1389 | kfree(txq->skb); |
1390 | txq->skb = NULL; | |
a66098da LB |
1391 | |
1392 | pci_free_consistent(priv->pdev, | |
1393 | MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), | |
45eb400d LB |
1394 | txq->txd, txq->txd_dma); |
1395 | txq->txd = NULL; | |
a66098da LB |
1396 | } |
1397 | ||
1398 | static int | |
1399 | mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb) | |
1400 | { | |
1401 | struct mwl8k_priv *priv = hw->priv; | |
1402 | struct ieee80211_tx_info *tx_info; | |
23b33906 | 1403 | struct mwl8k_vif *mwl8k_vif; |
a66098da LB |
1404 | struct ieee80211_hdr *wh; |
1405 | struct mwl8k_tx_queue *txq; | |
1406 | struct mwl8k_tx_desc *tx; | |
a66098da | 1407 | dma_addr_t dma; |
23b33906 LB |
1408 | u32 txstatus; |
1409 | u8 txdatarate; | |
1410 | u16 qos; | |
a66098da | 1411 | |
23b33906 LB |
1412 | wh = (struct ieee80211_hdr *)skb->data; |
1413 | if (ieee80211_is_data_qos(wh->frame_control)) | |
1414 | qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); | |
1415 | else | |
1416 | qos = 0; | |
a66098da | 1417 | |
76266b2a | 1418 | mwl8k_add_dma_header(skb); |
23b33906 | 1419 | wh = &((struct mwl8k_dma_data *)skb->data)->wh; |
a66098da LB |
1420 | |
1421 | tx_info = IEEE80211_SKB_CB(skb); | |
1422 | mwl8k_vif = MWL8K_VIF(tx_info->control.vif); | |
a66098da LB |
1423 | |
1424 | if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
1425 | u16 seqno = mwl8k_vif->seqno; | |
23b33906 | 1426 | |
a66098da LB |
1427 | wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
1428 | wh->seq_ctrl |= cpu_to_le16(seqno << 4); | |
1429 | mwl8k_vif->seqno = seqno++ % 4096; | |
1430 | } | |
1431 | ||
23b33906 LB |
1432 | /* Setup firmware control bit fields for each frame type. */ |
1433 | txstatus = 0; | |
1434 | txdatarate = 0; | |
1435 | if (ieee80211_is_mgmt(wh->frame_control) || | |
1436 | ieee80211_is_ctl(wh->frame_control)) { | |
1437 | txdatarate = 0; | |
1438 | qos = mwl8k_qos_setbit_eosp(qos); | |
1439 | /* Set Queue size to unspecified */ | |
1440 | qos = mwl8k_qos_setbit_qlen(qos, 0xff); | |
1441 | } else if (ieee80211_is_data(wh->frame_control)) { | |
1442 | txdatarate = 1; | |
1443 | if (is_multicast_ether_addr(wh->addr1)) | |
1444 | txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; | |
1445 | ||
1446 | /* Send pkt in an aggregate if AMPDU frame. */ | |
1447 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) | |
1448 | qos = mwl8k_qos_setbit_ack(qos, | |
1449 | MWL8K_TXD_ACK_POLICY_BLOCKACK); | |
1450 | else | |
1451 | qos = mwl8k_qos_setbit_ack(qos, | |
1452 | MWL8K_TXD_ACK_POLICY_NORMAL); | |
1453 | ||
1454 | if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT) | |
1455 | qos = mwl8k_qos_setbit_amsdu(qos); | |
1456 | } | |
a66098da LB |
1457 | |
1458 | dma = pci_map_single(priv->pdev, skb->data, | |
1459 | skb->len, PCI_DMA_TODEVICE); | |
1460 | ||
1461 | if (pci_dma_mapping_error(priv->pdev, dma)) { | |
1462 | printk(KERN_DEBUG "%s: failed to dma map skb, " | |
c2c357ce | 1463 | "dropping TX frame.\n", wiphy_name(hw->wiphy)); |
23b33906 | 1464 | dev_kfree_skb(skb); |
a66098da LB |
1465 | return NETDEV_TX_OK; |
1466 | } | |
1467 | ||
23b33906 | 1468 | spin_lock_bh(&priv->tx_lock); |
a66098da | 1469 | |
23b33906 | 1470 | txq = priv->txq + index; |
a66098da | 1471 | |
45eb400d LB |
1472 | BUG_ON(txq->skb[txq->tail] != NULL); |
1473 | txq->skb[txq->tail] = skb; | |
a66098da | 1474 | |
45eb400d | 1475 | tx = txq->txd + txq->tail; |
23b33906 LB |
1476 | tx->data_rate = txdatarate; |
1477 | tx->tx_priority = index; | |
a66098da | 1478 | tx->qos_control = cpu_to_le16(qos); |
a66098da LB |
1479 | tx->pkt_phys_addr = cpu_to_le32(dma); |
1480 | tx->pkt_len = cpu_to_le16(skb->len); | |
23b33906 LB |
1481 | tx->rate_info = 0; |
1482 | tx->peer_id = mwl8k_vif->peer_id; | |
a66098da | 1483 | wmb(); |
23b33906 LB |
1484 | tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); |
1485 | ||
45eb400d LB |
1486 | txq->stats.count++; |
1487 | txq->stats.len++; | |
a66098da | 1488 | priv->pending_tx_pkts++; |
a66098da | 1489 | |
45eb400d LB |
1490 | txq->tail++; |
1491 | if (txq->tail == MWL8K_TX_DESCS) | |
1492 | txq->tail = 0; | |
23b33906 | 1493 | |
45eb400d | 1494 | if (txq->head == txq->tail) |
a66098da LB |
1495 | ieee80211_stop_queue(hw, index); |
1496 | ||
23b33906 | 1497 | mwl8k_tx_start(priv); |
a66098da LB |
1498 | |
1499 | spin_unlock_bh(&priv->tx_lock); | |
1500 | ||
1501 | return NETDEV_TX_OK; | |
1502 | } | |
1503 | ||
1504 | ||
618952a7 LB |
1505 | /* |
1506 | * Firmware access. | |
1507 | * | |
1508 | * We have the following requirements for issuing firmware commands: | |
1509 | * - Some commands require that the packet transmit path is idle when | |
1510 | * the command is issued. (For simplicity, we'll just quiesce the | |
1511 | * transmit path for every command.) | |
1512 | * - There are certain sequences of commands that need to be issued to | |
1513 | * the hardware sequentially, with no other intervening commands. | |
1514 | * | |
1515 | * This leads to an implementation of a "firmware lock" as a mutex that | |
1516 | * can be taken recursively, and which is taken by both the low-level | |
1517 | * command submission function (mwl8k_post_cmd) as well as any users of | |
1518 | * that function that require issuing of an atomic sequence of commands, | |
1519 | * and quiesces the transmit path whenever it's taken. | |
1520 | */ | |
1521 | static int mwl8k_fw_lock(struct ieee80211_hw *hw) | |
1522 | { | |
1523 | struct mwl8k_priv *priv = hw->priv; | |
1524 | ||
1525 | if (priv->fw_mutex_owner != current) { | |
1526 | int rc; | |
1527 | ||
1528 | mutex_lock(&priv->fw_mutex); | |
1529 | ieee80211_stop_queues(hw); | |
1530 | ||
1531 | rc = mwl8k_tx_wait_empty(hw); | |
1532 | if (rc) { | |
1533 | ieee80211_wake_queues(hw); | |
1534 | mutex_unlock(&priv->fw_mutex); | |
1535 | ||
1536 | return rc; | |
1537 | } | |
1538 | ||
1539 | priv->fw_mutex_owner = current; | |
1540 | } | |
1541 | ||
1542 | priv->fw_mutex_depth++; | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | static void mwl8k_fw_unlock(struct ieee80211_hw *hw) | |
1548 | { | |
1549 | struct mwl8k_priv *priv = hw->priv; | |
1550 | ||
1551 | if (!--priv->fw_mutex_depth) { | |
1552 | ieee80211_wake_queues(hw); | |
1553 | priv->fw_mutex_owner = NULL; | |
1554 | mutex_unlock(&priv->fw_mutex); | |
1555 | } | |
1556 | } | |
1557 | ||
1558 | ||
a66098da LB |
1559 | /* |
1560 | * Command processing. | |
1561 | */ | |
1562 | ||
1563 | /* Timeout firmware commands after 2000ms */ | |
1564 | #define MWL8K_CMD_TIMEOUT_MS 2000 | |
1565 | ||
1566 | static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd) | |
1567 | { | |
1568 | DECLARE_COMPLETION_ONSTACK(cmd_wait); | |
1569 | struct mwl8k_priv *priv = hw->priv; | |
1570 | void __iomem *regs = priv->regs; | |
1571 | dma_addr_t dma_addr; | |
1572 | unsigned int dma_size; | |
1573 | int rc; | |
a66098da LB |
1574 | unsigned long timeout = 0; |
1575 | u8 buf[32]; | |
1576 | ||
c2c357ce | 1577 | cmd->result = 0xffff; |
a66098da LB |
1578 | dma_size = le16_to_cpu(cmd->length); |
1579 | dma_addr = pci_map_single(priv->pdev, cmd, dma_size, | |
1580 | PCI_DMA_BIDIRECTIONAL); | |
1581 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
1582 | return -ENOMEM; | |
1583 | ||
618952a7 | 1584 | rc = mwl8k_fw_lock(hw); |
39a1e42e LB |
1585 | if (rc) { |
1586 | pci_unmap_single(priv->pdev, dma_addr, dma_size, | |
1587 | PCI_DMA_BIDIRECTIONAL); | |
618952a7 | 1588 | return rc; |
39a1e42e | 1589 | } |
a66098da | 1590 | |
a66098da LB |
1591 | priv->hostcmd_wait = &cmd_wait; |
1592 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
1593 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
1594 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1595 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1596 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
a66098da LB |
1597 | |
1598 | timeout = wait_for_completion_timeout(&cmd_wait, | |
1599 | msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS)); | |
1600 | ||
618952a7 LB |
1601 | priv->hostcmd_wait = NULL; |
1602 | ||
1603 | mwl8k_fw_unlock(hw); | |
1604 | ||
37055bd4 LB |
1605 | pci_unmap_single(priv->pdev, dma_addr, dma_size, |
1606 | PCI_DMA_BIDIRECTIONAL); | |
1607 | ||
a66098da | 1608 | if (!timeout) { |
a66098da | 1609 | printk(KERN_ERR "%s: Command %s timeout after %u ms\n", |
c2c357ce | 1610 | wiphy_name(hw->wiphy), |
a66098da LB |
1611 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
1612 | MWL8K_CMD_TIMEOUT_MS); | |
1613 | rc = -ETIMEDOUT; | |
1614 | } else { | |
ce9e2e1b | 1615 | rc = cmd->result ? -EINVAL : 0; |
a66098da LB |
1616 | if (rc) |
1617 | printk(KERN_ERR "%s: Command %s error 0x%x\n", | |
c2c357ce | 1618 | wiphy_name(hw->wiphy), |
a66098da | 1619 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
76c962a2 | 1620 | le16_to_cpu(cmd->result)); |
a66098da LB |
1621 | } |
1622 | ||
a66098da LB |
1623 | return rc; |
1624 | } | |
1625 | ||
1626 | /* | |
04b147b1 | 1627 | * CMD_GET_HW_SPEC (STA version). |
a66098da | 1628 | */ |
04b147b1 | 1629 | struct mwl8k_cmd_get_hw_spec_sta { |
a66098da LB |
1630 | struct mwl8k_cmd_pkt header; |
1631 | __u8 hw_rev; | |
1632 | __u8 host_interface; | |
1633 | __le16 num_mcaddrs; | |
d89173f2 | 1634 | __u8 perm_addr[ETH_ALEN]; |
a66098da LB |
1635 | __le16 region_code; |
1636 | __le32 fw_rev; | |
1637 | __le32 ps_cookie; | |
1638 | __le32 caps; | |
1639 | __u8 mcs_bitmap[16]; | |
1640 | __le32 rx_queue_ptr; | |
1641 | __le32 num_tx_queues; | |
1642 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1643 | __le32 caps2; | |
1644 | __le32 num_tx_desc_per_queue; | |
45eb400d | 1645 | __le32 total_rxd; |
a66098da LB |
1646 | } __attribute__((packed)); |
1647 | ||
04b147b1 | 1648 | static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw) |
a66098da LB |
1649 | { |
1650 | struct mwl8k_priv *priv = hw->priv; | |
04b147b1 | 1651 | struct mwl8k_cmd_get_hw_spec_sta *cmd; |
a66098da LB |
1652 | int rc; |
1653 | int i; | |
1654 | ||
1655 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1656 | if (cmd == NULL) | |
1657 | return -ENOMEM; | |
1658 | ||
1659 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1660 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1661 | ||
1662 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1663 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
45eb400d | 1664 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); |
4ff6432e | 1665 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); |
a66098da | 1666 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
45eb400d | 1667 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); |
4ff6432e | 1668 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); |
45eb400d | 1669 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); |
a66098da LB |
1670 | |
1671 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1672 | ||
1673 | if (!rc) { | |
1674 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1675 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
4ff6432e | 1676 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); |
a66098da | 1677 | priv->hw_rev = cmd->hw_rev; |
a66098da LB |
1678 | } |
1679 | ||
1680 | kfree(cmd); | |
1681 | return rc; | |
1682 | } | |
1683 | ||
42fba21d LB |
1684 | /* |
1685 | * CMD_GET_HW_SPEC (AP version). | |
1686 | */ | |
1687 | struct mwl8k_cmd_get_hw_spec_ap { | |
1688 | struct mwl8k_cmd_pkt header; | |
1689 | __u8 hw_rev; | |
1690 | __u8 host_interface; | |
1691 | __le16 num_wcb; | |
1692 | __le16 num_mcaddrs; | |
1693 | __u8 perm_addr[ETH_ALEN]; | |
1694 | __le16 region_code; | |
1695 | __le16 num_antenna; | |
1696 | __le32 fw_rev; | |
1697 | __le32 wcbbase0; | |
1698 | __le32 rxwrptr; | |
1699 | __le32 rxrdptr; | |
1700 | __le32 ps_cookie; | |
1701 | __le32 wcbbase1; | |
1702 | __le32 wcbbase2; | |
1703 | __le32 wcbbase3; | |
1704 | } __attribute__((packed)); | |
1705 | ||
1706 | static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) | |
1707 | { | |
1708 | struct mwl8k_priv *priv = hw->priv; | |
1709 | struct mwl8k_cmd_get_hw_spec_ap *cmd; | |
1710 | int rc; | |
1711 | ||
1712 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1713 | if (cmd == NULL) | |
1714 | return -ENOMEM; | |
1715 | ||
1716 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1717 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1718 | ||
1719 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1720 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1721 | ||
1722 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1723 | ||
1724 | if (!rc) { | |
1725 | int off; | |
1726 | ||
1727 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1728 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
1729 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); | |
1730 | priv->hw_rev = cmd->hw_rev; | |
1731 | ||
1732 | off = le32_to_cpu(cmd->wcbbase0) & 0xffff; | |
1733 | iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off); | |
1734 | ||
1735 | off = le32_to_cpu(cmd->rxwrptr) & 0xffff; | |
1736 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1737 | ||
1738 | off = le32_to_cpu(cmd->rxrdptr) & 0xffff; | |
1739 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1740 | ||
1741 | off = le32_to_cpu(cmd->wcbbase1) & 0xffff; | |
1742 | iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off); | |
1743 | ||
1744 | off = le32_to_cpu(cmd->wcbbase2) & 0xffff; | |
1745 | iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off); | |
1746 | ||
1747 | off = le32_to_cpu(cmd->wcbbase3) & 0xffff; | |
1748 | iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off); | |
1749 | } | |
1750 | ||
1751 | kfree(cmd); | |
1752 | return rc; | |
1753 | } | |
1754 | ||
1755 | /* | |
1756 | * CMD_SET_HW_SPEC. | |
1757 | */ | |
1758 | struct mwl8k_cmd_set_hw_spec { | |
1759 | struct mwl8k_cmd_pkt header; | |
1760 | __u8 hw_rev; | |
1761 | __u8 host_interface; | |
1762 | __le16 num_mcaddrs; | |
1763 | __u8 perm_addr[ETH_ALEN]; | |
1764 | __le16 region_code; | |
1765 | __le32 fw_rev; | |
1766 | __le32 ps_cookie; | |
1767 | __le32 caps; | |
1768 | __le32 rx_queue_ptr; | |
1769 | __le32 num_tx_queues; | |
1770 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1771 | __le32 flags; | |
1772 | __le32 num_tx_desc_per_queue; | |
1773 | __le32 total_rxd; | |
1774 | } __attribute__((packed)); | |
1775 | ||
1776 | #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080 | |
1777 | ||
1778 | static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw) | |
1779 | { | |
1780 | struct mwl8k_priv *priv = hw->priv; | |
1781 | struct mwl8k_cmd_set_hw_spec *cmd; | |
1782 | int rc; | |
1783 | int i; | |
1784 | ||
1785 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1786 | if (cmd == NULL) | |
1787 | return -ENOMEM; | |
1788 | ||
1789 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC); | |
1790 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1791 | ||
1792 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1793 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); | |
1794 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); | |
1795 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
1796 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); | |
1797 | cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT); | |
1798 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); | |
1799 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); | |
1800 | ||
1801 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1802 | kfree(cmd); | |
1803 | ||
1804 | return rc; | |
1805 | } | |
1806 | ||
a66098da LB |
1807 | /* |
1808 | * CMD_MAC_MULTICAST_ADR. | |
1809 | */ | |
1810 | struct mwl8k_cmd_mac_multicast_adr { | |
1811 | struct mwl8k_cmd_pkt header; | |
1812 | __le16 action; | |
1813 | __le16 numaddr; | |
ce9e2e1b | 1814 | __u8 addr[0][ETH_ALEN]; |
a66098da LB |
1815 | }; |
1816 | ||
d5e30845 LB |
1817 | #define MWL8K_ENABLE_RX_DIRECTED 0x0001 |
1818 | #define MWL8K_ENABLE_RX_MULTICAST 0x0002 | |
1819 | #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004 | |
1820 | #define MWL8K_ENABLE_RX_BROADCAST 0x0008 | |
ce9e2e1b | 1821 | |
e81cd2d6 | 1822 | static struct mwl8k_cmd_pkt * |
447ced07 | 1823 | __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti, |
e81cd2d6 | 1824 | int mc_count, struct dev_addr_list *mclist) |
a66098da | 1825 | { |
e81cd2d6 | 1826 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1827 | struct mwl8k_cmd_mac_multicast_adr *cmd; |
e81cd2d6 | 1828 | int size; |
e81cd2d6 | 1829 | |
447ced07 | 1830 | if (allmulti || mc_count > priv->num_mcaddrs) { |
d5e30845 LB |
1831 | allmulti = 1; |
1832 | mc_count = 0; | |
1833 | } | |
e81cd2d6 LB |
1834 | |
1835 | size = sizeof(*cmd) + mc_count * ETH_ALEN; | |
ce9e2e1b | 1836 | |
e81cd2d6 | 1837 | cmd = kzalloc(size, GFP_ATOMIC); |
a66098da | 1838 | if (cmd == NULL) |
e81cd2d6 | 1839 | return NULL; |
a66098da LB |
1840 | |
1841 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); | |
1842 | cmd->header.length = cpu_to_le16(size); | |
d5e30845 LB |
1843 | cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED | |
1844 | MWL8K_ENABLE_RX_BROADCAST); | |
1845 | ||
1846 | if (allmulti) { | |
1847 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST); | |
1848 | } else if (mc_count) { | |
1849 | int i; | |
1850 | ||
1851 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); | |
1852 | cmd->numaddr = cpu_to_le16(mc_count); | |
1853 | for (i = 0; i < mc_count && mclist; i++) { | |
1854 | if (mclist->da_addrlen != ETH_ALEN) { | |
1855 | kfree(cmd); | |
1856 | return NULL; | |
1857 | } | |
1858 | memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN); | |
1859 | mclist = mclist->next; | |
a66098da | 1860 | } |
a66098da LB |
1861 | } |
1862 | ||
e81cd2d6 | 1863 | return &cmd->header; |
a66098da LB |
1864 | } |
1865 | ||
1866 | /* | |
1867 | * CMD_802_11_GET_STAT. | |
1868 | */ | |
1869 | struct mwl8k_cmd_802_11_get_stat { | |
1870 | struct mwl8k_cmd_pkt header; | |
a66098da LB |
1871 | __le32 stats[64]; |
1872 | } __attribute__((packed)); | |
1873 | ||
1874 | #define MWL8K_STAT_ACK_FAILURE 9 | |
1875 | #define MWL8K_STAT_RTS_FAILURE 12 | |
1876 | #define MWL8K_STAT_FCS_ERROR 24 | |
1877 | #define MWL8K_STAT_RTS_SUCCESS 11 | |
1878 | ||
1879 | static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw, | |
1880 | struct ieee80211_low_level_stats *stats) | |
1881 | { | |
1882 | struct mwl8k_cmd_802_11_get_stat *cmd; | |
1883 | int rc; | |
1884 | ||
1885 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1886 | if (cmd == NULL) | |
1887 | return -ENOMEM; | |
1888 | ||
1889 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); | |
1890 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
1891 | |
1892 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1893 | if (!rc) { | |
1894 | stats->dot11ACKFailureCount = | |
1895 | le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]); | |
1896 | stats->dot11RTSFailureCount = | |
1897 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]); | |
1898 | stats->dot11FCSErrorCount = | |
1899 | le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]); | |
1900 | stats->dot11RTSSuccessCount = | |
1901 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]); | |
1902 | } | |
1903 | kfree(cmd); | |
1904 | ||
1905 | return rc; | |
1906 | } | |
1907 | ||
1908 | /* | |
1909 | * CMD_802_11_RADIO_CONTROL. | |
1910 | */ | |
1911 | struct mwl8k_cmd_802_11_radio_control { | |
1912 | struct mwl8k_cmd_pkt header; | |
1913 | __le16 action; | |
1914 | __le16 control; | |
1915 | __le16 radio_on; | |
1916 | } __attribute__((packed)); | |
1917 | ||
c46563b7 LB |
1918 | static int |
1919 | mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force) | |
a66098da LB |
1920 | { |
1921 | struct mwl8k_priv *priv = hw->priv; | |
1922 | struct mwl8k_cmd_802_11_radio_control *cmd; | |
1923 | int rc; | |
1924 | ||
c46563b7 | 1925 | if (enable == priv->radio_on && !force) |
a66098da LB |
1926 | return 0; |
1927 | ||
a66098da LB |
1928 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
1929 | if (cmd == NULL) | |
1930 | return -ENOMEM; | |
1931 | ||
1932 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL); | |
1933 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1934 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
68ce3884 | 1935 | cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1); |
a66098da LB |
1936 | cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); |
1937 | ||
1938 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1939 | kfree(cmd); | |
1940 | ||
1941 | if (!rc) | |
c46563b7 | 1942 | priv->radio_on = enable; |
a66098da LB |
1943 | |
1944 | return rc; | |
1945 | } | |
1946 | ||
c46563b7 LB |
1947 | static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw) |
1948 | { | |
1949 | return mwl8k_cmd_802_11_radio_control(hw, 0, 0); | |
1950 | } | |
1951 | ||
1952 | static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw) | |
1953 | { | |
1954 | return mwl8k_cmd_802_11_radio_control(hw, 1, 0); | |
1955 | } | |
1956 | ||
a66098da LB |
1957 | static int |
1958 | mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble) | |
1959 | { | |
1960 | struct mwl8k_priv *priv; | |
1961 | ||
1962 | if (hw == NULL || hw->priv == NULL) | |
1963 | return -EINVAL; | |
1964 | priv = hw->priv; | |
1965 | ||
68ce3884 | 1966 | priv->radio_short_preamble = short_preamble; |
a66098da | 1967 | |
c46563b7 | 1968 | return mwl8k_cmd_802_11_radio_control(hw, 1, 1); |
a66098da LB |
1969 | } |
1970 | ||
1971 | /* | |
1972 | * CMD_802_11_RF_TX_POWER. | |
1973 | */ | |
1974 | #define MWL8K_TX_POWER_LEVEL_TOTAL 8 | |
1975 | ||
1976 | struct mwl8k_cmd_802_11_rf_tx_power { | |
1977 | struct mwl8k_cmd_pkt header; | |
1978 | __le16 action; | |
1979 | __le16 support_level; | |
1980 | __le16 current_level; | |
1981 | __le16 reserved; | |
1982 | __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL]; | |
1983 | } __attribute__((packed)); | |
1984 | ||
1985 | static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm) | |
1986 | { | |
1987 | struct mwl8k_cmd_802_11_rf_tx_power *cmd; | |
1988 | int rc; | |
1989 | ||
1990 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1991 | if (cmd == NULL) | |
1992 | return -ENOMEM; | |
1993 | ||
1994 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER); | |
1995 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1996 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
1997 | cmd->support_level = cpu_to_le16(dBm); | |
1998 | ||
1999 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2000 | kfree(cmd); | |
2001 | ||
2002 | return rc; | |
2003 | } | |
2004 | ||
08b06347 LB |
2005 | /* |
2006 | * CMD_RF_ANTENNA. | |
2007 | */ | |
2008 | struct mwl8k_cmd_rf_antenna { | |
2009 | struct mwl8k_cmd_pkt header; | |
2010 | __le16 antenna; | |
2011 | __le16 mode; | |
2012 | } __attribute__((packed)); | |
2013 | ||
2014 | #define MWL8K_RF_ANTENNA_RX 1 | |
2015 | #define MWL8K_RF_ANTENNA_TX 2 | |
2016 | ||
2017 | static int | |
2018 | mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) | |
2019 | { | |
2020 | struct mwl8k_cmd_rf_antenna *cmd; | |
2021 | int rc; | |
2022 | ||
2023 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2024 | if (cmd == NULL) | |
2025 | return -ENOMEM; | |
2026 | ||
2027 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA); | |
2028 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2029 | cmd->antenna = cpu_to_le16(antenna); | |
2030 | cmd->mode = cpu_to_le16(mask); | |
2031 | ||
2032 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2033 | kfree(cmd); | |
2034 | ||
2035 | return rc; | |
2036 | } | |
2037 | ||
a66098da LB |
2038 | /* |
2039 | * CMD_SET_PRE_SCAN. | |
2040 | */ | |
2041 | struct mwl8k_cmd_set_pre_scan { | |
2042 | struct mwl8k_cmd_pkt header; | |
2043 | } __attribute__((packed)); | |
2044 | ||
2045 | static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw) | |
2046 | { | |
2047 | struct mwl8k_cmd_set_pre_scan *cmd; | |
2048 | int rc; | |
2049 | ||
2050 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2051 | if (cmd == NULL) | |
2052 | return -ENOMEM; | |
2053 | ||
2054 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN); | |
2055 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2056 | ||
2057 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2058 | kfree(cmd); | |
2059 | ||
2060 | return rc; | |
2061 | } | |
2062 | ||
2063 | /* | |
2064 | * CMD_SET_POST_SCAN. | |
2065 | */ | |
2066 | struct mwl8k_cmd_set_post_scan { | |
2067 | struct mwl8k_cmd_pkt header; | |
2068 | __le32 isibss; | |
d89173f2 | 2069 | __u8 bssid[ETH_ALEN]; |
a66098da LB |
2070 | } __attribute__((packed)); |
2071 | ||
2072 | static int | |
ce9e2e1b | 2073 | mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac) |
a66098da LB |
2074 | { |
2075 | struct mwl8k_cmd_set_post_scan *cmd; | |
2076 | int rc; | |
2077 | ||
2078 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2079 | if (cmd == NULL) | |
2080 | return -ENOMEM; | |
2081 | ||
2082 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN); | |
2083 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2084 | cmd->isibss = 0; | |
d89173f2 | 2085 | memcpy(cmd->bssid, mac, ETH_ALEN); |
a66098da LB |
2086 | |
2087 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2088 | kfree(cmd); | |
2089 | ||
2090 | return rc; | |
2091 | } | |
2092 | ||
2093 | /* | |
2094 | * CMD_SET_RF_CHANNEL. | |
2095 | */ | |
2096 | struct mwl8k_cmd_set_rf_channel { | |
2097 | struct mwl8k_cmd_pkt header; | |
2098 | __le16 action; | |
2099 | __u8 current_channel; | |
2100 | __le32 channel_flags; | |
2101 | } __attribute__((packed)); | |
2102 | ||
2103 | static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw, | |
2104 | struct ieee80211_channel *channel) | |
2105 | { | |
2106 | struct mwl8k_cmd_set_rf_channel *cmd; | |
2107 | int rc; | |
2108 | ||
2109 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2110 | if (cmd == NULL) | |
2111 | return -ENOMEM; | |
2112 | ||
2113 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL); | |
2114 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2115 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2116 | cmd->current_channel = channel->hw_value; | |
2117 | if (channel->band == IEEE80211_BAND_2GHZ) | |
2118 | cmd->channel_flags = cpu_to_le32(0x00000081); | |
2119 | else | |
2120 | cmd->channel_flags = cpu_to_le32(0x00000000); | |
2121 | ||
2122 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2123 | kfree(cmd); | |
2124 | ||
2125 | return rc; | |
2126 | } | |
2127 | ||
2128 | /* | |
2129 | * CMD_SET_SLOT. | |
2130 | */ | |
2131 | struct mwl8k_cmd_set_slot { | |
2132 | struct mwl8k_cmd_pkt header; | |
2133 | __le16 action; | |
2134 | __u8 short_slot; | |
2135 | } __attribute__((packed)); | |
2136 | ||
5539bb51 | 2137 | static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time) |
a66098da LB |
2138 | { |
2139 | struct mwl8k_cmd_set_slot *cmd; | |
2140 | int rc; | |
2141 | ||
2142 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2143 | if (cmd == NULL) | |
2144 | return -ENOMEM; | |
2145 | ||
2146 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT); | |
2147 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2148 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
5539bb51 | 2149 | cmd->short_slot = short_slot_time; |
a66098da LB |
2150 | |
2151 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2152 | kfree(cmd); | |
2153 | ||
2154 | return rc; | |
2155 | } | |
2156 | ||
2157 | /* | |
2158 | * CMD_MIMO_CONFIG. | |
2159 | */ | |
2160 | struct mwl8k_cmd_mimo_config { | |
2161 | struct mwl8k_cmd_pkt header; | |
2162 | __le32 action; | |
2163 | __u8 rx_antenna_map; | |
2164 | __u8 tx_antenna_map; | |
2165 | } __attribute__((packed)); | |
2166 | ||
2167 | static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx) | |
2168 | { | |
2169 | struct mwl8k_cmd_mimo_config *cmd; | |
2170 | int rc; | |
2171 | ||
2172 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2173 | if (cmd == NULL) | |
2174 | return -ENOMEM; | |
2175 | ||
2176 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG); | |
2177 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2178 | cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET); | |
2179 | cmd->rx_antenna_map = rx; | |
2180 | cmd->tx_antenna_map = tx; | |
2181 | ||
2182 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2183 | kfree(cmd); | |
2184 | ||
2185 | return rc; | |
2186 | } | |
2187 | ||
2188 | /* | |
2189 | * CMD_ENABLE_SNIFFER. | |
2190 | */ | |
2191 | struct mwl8k_cmd_enable_sniffer { | |
2192 | struct mwl8k_cmd_pkt header; | |
2193 | __le32 action; | |
2194 | } __attribute__((packed)); | |
2195 | ||
2196 | static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable) | |
2197 | { | |
2198 | struct mwl8k_cmd_enable_sniffer *cmd; | |
2199 | int rc; | |
2200 | ||
2201 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2202 | if (cmd == NULL) | |
2203 | return -ENOMEM; | |
2204 | ||
2205 | cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER); | |
2206 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
ce9e2e1b | 2207 | cmd->action = cpu_to_le32(!!enable); |
a66098da LB |
2208 | |
2209 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2210 | kfree(cmd); | |
2211 | ||
2212 | return rc; | |
2213 | } | |
2214 | ||
32060e1b LB |
2215 | /* |
2216 | * CMD_SET_MAC_ADDR. | |
2217 | */ | |
2218 | struct mwl8k_cmd_set_mac_addr { | |
2219 | struct mwl8k_cmd_pkt header; | |
259a8e7d LB |
2220 | union { |
2221 | struct { | |
2222 | __le16 mac_type; | |
2223 | __u8 mac_addr[ETH_ALEN]; | |
2224 | } mbss; | |
2225 | __u8 mac_addr[ETH_ALEN]; | |
2226 | }; | |
32060e1b LB |
2227 | } __attribute__((packed)); |
2228 | ||
2229 | static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac) | |
2230 | { | |
259a8e7d | 2231 | struct mwl8k_priv *priv = hw->priv; |
32060e1b LB |
2232 | struct mwl8k_cmd_set_mac_addr *cmd; |
2233 | int rc; | |
2234 | ||
2235 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2236 | if (cmd == NULL) | |
2237 | return -ENOMEM; | |
2238 | ||
2239 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR); | |
2240 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
259a8e7d LB |
2241 | if (priv->ap_fw) { |
2242 | cmd->mbss.mac_type = 0; | |
2243 | memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN); | |
2244 | } else { | |
2245 | memcpy(cmd->mac_addr, mac, ETH_ALEN); | |
2246 | } | |
32060e1b LB |
2247 | |
2248 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2249 | kfree(cmd); | |
2250 | ||
2251 | return rc; | |
2252 | } | |
2253 | ||
2254 | ||
a66098da | 2255 | /* |
ce9e2e1b | 2256 | * CMD_SET_RATEADAPT_MODE. |
a66098da LB |
2257 | */ |
2258 | struct mwl8k_cmd_set_rate_adapt_mode { | |
2259 | struct mwl8k_cmd_pkt header; | |
2260 | __le16 action; | |
2261 | __le16 mode; | |
2262 | } __attribute__((packed)); | |
2263 | ||
2264 | static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode) | |
2265 | { | |
2266 | struct mwl8k_cmd_set_rate_adapt_mode *cmd; | |
2267 | int rc; | |
2268 | ||
2269 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2270 | if (cmd == NULL) | |
2271 | return -ENOMEM; | |
2272 | ||
2273 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE); | |
2274 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2275 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2276 | cmd->mode = cpu_to_le16(mode); | |
2277 | ||
2278 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2279 | kfree(cmd); | |
2280 | ||
2281 | return rc; | |
2282 | } | |
2283 | ||
2284 | /* | |
2285 | * CMD_SET_WMM_MODE. | |
2286 | */ | |
2287 | struct mwl8k_cmd_set_wmm { | |
2288 | struct mwl8k_cmd_pkt header; | |
2289 | __le16 action; | |
2290 | } __attribute__((packed)); | |
2291 | ||
2292 | static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable) | |
2293 | { | |
2294 | struct mwl8k_priv *priv = hw->priv; | |
2295 | struct mwl8k_cmd_set_wmm *cmd; | |
2296 | int rc; | |
2297 | ||
2298 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2299 | if (cmd == NULL) | |
2300 | return -ENOMEM; | |
2301 | ||
2302 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE); | |
2303 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
0439b1f5 | 2304 | cmd->action = cpu_to_le16(!!enable); |
a66098da LB |
2305 | |
2306 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2307 | kfree(cmd); | |
2308 | ||
2309 | if (!rc) | |
0439b1f5 | 2310 | priv->wmm_enabled = enable; |
a66098da LB |
2311 | |
2312 | return rc; | |
2313 | } | |
2314 | ||
2315 | /* | |
2316 | * CMD_SET_RTS_THRESHOLD. | |
2317 | */ | |
2318 | struct mwl8k_cmd_rts_threshold { | |
2319 | struct mwl8k_cmd_pkt header; | |
2320 | __le16 action; | |
2321 | __le16 threshold; | |
2322 | } __attribute__((packed)); | |
2323 | ||
2324 | static int mwl8k_rts_threshold(struct ieee80211_hw *hw, | |
733d3067 | 2325 | u16 action, u16 threshold) |
a66098da LB |
2326 | { |
2327 | struct mwl8k_cmd_rts_threshold *cmd; | |
2328 | int rc; | |
2329 | ||
2330 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2331 | if (cmd == NULL) | |
2332 | return -ENOMEM; | |
2333 | ||
2334 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD); | |
2335 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2336 | cmd->action = cpu_to_le16(action); | |
733d3067 | 2337 | cmd->threshold = cpu_to_le16(threshold); |
a66098da LB |
2338 | |
2339 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2340 | kfree(cmd); | |
2341 | ||
2342 | return rc; | |
2343 | } | |
2344 | ||
2345 | /* | |
2346 | * CMD_SET_EDCA_PARAMS. | |
2347 | */ | |
2348 | struct mwl8k_cmd_set_edca_params { | |
2349 | struct mwl8k_cmd_pkt header; | |
2350 | ||
2351 | /* See MWL8K_SET_EDCA_XXX below */ | |
2352 | __le16 action; | |
2353 | ||
2354 | /* TX opportunity in units of 32 us */ | |
2355 | __le16 txop; | |
2356 | ||
2e484c89 LB |
2357 | union { |
2358 | struct { | |
2359 | /* Log exponent of max contention period: 0...15 */ | |
2360 | __le32 log_cw_max; | |
2361 | ||
2362 | /* Log exponent of min contention period: 0...15 */ | |
2363 | __le32 log_cw_min; | |
2364 | ||
2365 | /* Adaptive interframe spacing in units of 32us */ | |
2366 | __u8 aifs; | |
2367 | ||
2368 | /* TX queue to configure */ | |
2369 | __u8 txq; | |
2370 | } ap; | |
2371 | struct { | |
2372 | /* Log exponent of max contention period: 0...15 */ | |
2373 | __u8 log_cw_max; | |
a66098da | 2374 | |
2e484c89 LB |
2375 | /* Log exponent of min contention period: 0...15 */ |
2376 | __u8 log_cw_min; | |
a66098da | 2377 | |
2e484c89 LB |
2378 | /* Adaptive interframe spacing in units of 32us */ |
2379 | __u8 aifs; | |
a66098da | 2380 | |
2e484c89 LB |
2381 | /* TX queue to configure */ |
2382 | __u8 txq; | |
2383 | } sta; | |
2384 | }; | |
a66098da LB |
2385 | } __attribute__((packed)); |
2386 | ||
a66098da LB |
2387 | #define MWL8K_SET_EDCA_CW 0x01 |
2388 | #define MWL8K_SET_EDCA_TXOP 0x02 | |
2389 | #define MWL8K_SET_EDCA_AIFS 0x04 | |
2390 | ||
2391 | #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \ | |
2392 | MWL8K_SET_EDCA_TXOP | \ | |
2393 | MWL8K_SET_EDCA_AIFS) | |
2394 | ||
2395 | static int | |
2396 | mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum, | |
2397 | __u16 cw_min, __u16 cw_max, | |
2398 | __u8 aifs, __u16 txop) | |
2399 | { | |
2e484c89 | 2400 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 2401 | struct mwl8k_cmd_set_edca_params *cmd; |
a66098da LB |
2402 | int rc; |
2403 | ||
2404 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2405 | if (cmd == NULL) | |
2406 | return -ENOMEM; | |
2407 | ||
22995b24 LB |
2408 | /* |
2409 | * Queues 0 (BE) and 1 (BK) are swapped in hardware for | |
2410 | * this call. | |
2411 | */ | |
2412 | qnum ^= !(qnum >> 1); | |
2413 | ||
a66098da LB |
2414 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); |
2415 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
2416 | cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); |
2417 | cmd->txop = cpu_to_le16(txop); | |
2e484c89 LB |
2418 | if (priv->ap_fw) { |
2419 | cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1)); | |
2420 | cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1)); | |
2421 | cmd->ap.aifs = aifs; | |
2422 | cmd->ap.txq = qnum; | |
2423 | } else { | |
2424 | cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1); | |
2425 | cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1); | |
2426 | cmd->sta.aifs = aifs; | |
2427 | cmd->sta.txq = qnum; | |
2428 | } | |
a66098da LB |
2429 | |
2430 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2431 | kfree(cmd); | |
2432 | ||
2433 | return rc; | |
2434 | } | |
2435 | ||
2436 | /* | |
2437 | * CMD_FINALIZE_JOIN. | |
2438 | */ | |
2439 | ||
2440 | /* FJ beacon buffer size is compiled into the firmware. */ | |
2441 | #define MWL8K_FJ_BEACON_MAXLEN 128 | |
2442 | ||
2443 | struct mwl8k_cmd_finalize_join { | |
2444 | struct mwl8k_cmd_pkt header; | |
2445 | __le32 sleep_interval; /* Number of beacon periods to sleep */ | |
2446 | __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN]; | |
2447 | } __attribute__((packed)); | |
2448 | ||
2449 | static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame, | |
2450 | __u16 framelen, __u16 dtim) | |
2451 | { | |
2452 | struct mwl8k_cmd_finalize_join *cmd; | |
2453 | struct ieee80211_mgmt *payload = frame; | |
2454 | u16 hdrlen; | |
2455 | u32 payload_len; | |
2456 | int rc; | |
2457 | ||
2458 | if (frame == NULL) | |
2459 | return -EINVAL; | |
2460 | ||
2461 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2462 | if (cmd == NULL) | |
2463 | return -ENOMEM; | |
2464 | ||
2465 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN); | |
2466 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
ce9e2e1b | 2467 | cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1); |
a66098da LB |
2468 | |
2469 | hdrlen = ieee80211_hdrlen(payload->frame_control); | |
2470 | ||
2471 | payload_len = framelen > hdrlen ? framelen - hdrlen : 0; | |
2472 | ||
2473 | /* XXX TBD Might just have to abort and return an error */ | |
2474 | if (payload_len > MWL8K_FJ_BEACON_MAXLEN) | |
2475 | printk(KERN_ERR "%s(): WARNING: Incomplete beacon " | |
c2c357ce LB |
2476 | "sent to firmware. Sz=%u MAX=%u\n", __func__, |
2477 | payload_len, MWL8K_FJ_BEACON_MAXLEN); | |
a66098da | 2478 | |
ce9e2e1b LB |
2479 | if (payload_len > MWL8K_FJ_BEACON_MAXLEN) |
2480 | payload_len = MWL8K_FJ_BEACON_MAXLEN; | |
a66098da LB |
2481 | |
2482 | if (payload && payload_len) | |
2483 | memcpy(cmd->beacon_data, &payload->u.beacon, payload_len); | |
2484 | ||
2485 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2486 | kfree(cmd); | |
2487 | return rc; | |
2488 | } | |
2489 | ||
2490 | /* | |
2491 | * CMD_UPDATE_STADB. | |
2492 | */ | |
2493 | struct mwl8k_cmd_update_sta_db { | |
2494 | struct mwl8k_cmd_pkt header; | |
2495 | ||
2496 | /* See STADB_ACTION_TYPE */ | |
2497 | __le32 action; | |
2498 | ||
2499 | /* Peer MAC address */ | |
d89173f2 | 2500 | __u8 peer_addr[ETH_ALEN]; |
a66098da LB |
2501 | |
2502 | __le32 reserved; | |
2503 | ||
2504 | /* Peer info - valid during add/update. */ | |
2505 | struct peer_capability_info peer_info; | |
2506 | } __attribute__((packed)); | |
2507 | ||
2508 | static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw, | |
2509 | struct ieee80211_vif *vif, __u32 action) | |
2510 | { | |
2511 | struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); | |
2512 | struct ieee80211_bss_conf *info = &mv_vif->bss_info; | |
2513 | struct mwl8k_cmd_update_sta_db *cmd; | |
2514 | struct peer_capability_info *peer_info; | |
2515 | struct ieee80211_rate *bitrates = mv_vif->legacy_rates; | |
a66098da LB |
2516 | int rc; |
2517 | __u8 count, *rates; | |
2518 | ||
2519 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2520 | if (cmd == NULL) | |
2521 | return -ENOMEM; | |
2522 | ||
2523 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
2524 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2525 | ||
2526 | cmd->action = cpu_to_le32(action); | |
2527 | peer_info = &cmd->peer_info; | |
d89173f2 | 2528 | memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN); |
a66098da LB |
2529 | |
2530 | switch (action) { | |
2531 | case MWL8K_STA_DB_ADD_ENTRY: | |
2532 | case MWL8K_STA_DB_MODIFY_ENTRY: | |
2533 | /* Build peer_info block */ | |
2534 | peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT; | |
2535 | peer_info->basic_caps = cpu_to_le16(info->assoc_capability); | |
2536 | peer_info->interop = 1; | |
2537 | peer_info->amsdu_enabled = 0; | |
2538 | ||
2539 | rates = peer_info->legacy_rates; | |
ce9e2e1b | 2540 | for (count = 0; count < mv_vif->legacy_nrates; count++) |
a66098da LB |
2541 | rates[count] = bitrates[count].hw_value; |
2542 | ||
2543 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2544 | if (rc == 0) | |
2545 | mv_vif->peer_id = peer_info->station_id; | |
2546 | ||
2547 | break; | |
2548 | ||
2549 | case MWL8K_STA_DB_DEL_ENTRY: | |
2550 | case MWL8K_STA_DB_FLUSH: | |
2551 | default: | |
2552 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2553 | if (rc == 0) | |
2554 | mv_vif->peer_id = 0; | |
2555 | break; | |
2556 | } | |
2557 | kfree(cmd); | |
2558 | ||
2559 | return rc; | |
2560 | } | |
2561 | ||
2562 | /* | |
2563 | * CMD_SET_AID. | |
2564 | */ | |
a66098da LB |
2565 | #define MWL8K_RATE_INDEX_MAX_ARRAY 14 |
2566 | ||
2567 | #define MWL8K_FRAME_PROT_DISABLED 0x00 | |
2568 | #define MWL8K_FRAME_PROT_11G 0x07 | |
2569 | #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02 | |
2570 | #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06 | |
a66098da LB |
2571 | |
2572 | struct mwl8k_cmd_update_set_aid { | |
2573 | struct mwl8k_cmd_pkt header; | |
2574 | __le16 aid; | |
2575 | ||
2576 | /* AP's MAC address (BSSID) */ | |
d89173f2 | 2577 | __u8 bssid[ETH_ALEN]; |
a66098da LB |
2578 | __le16 protection_mode; |
2579 | __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY]; | |
2580 | } __attribute__((packed)); | |
2581 | ||
2582 | static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw, | |
2583 | struct ieee80211_vif *vif) | |
2584 | { | |
2585 | struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); | |
2586 | struct ieee80211_bss_conf *info = &mv_vif->bss_info; | |
2587 | struct mwl8k_cmd_update_set_aid *cmd; | |
2588 | struct ieee80211_rate *bitrates = mv_vif->legacy_rates; | |
2589 | int count; | |
2590 | u16 prot_mode; | |
2591 | int rc; | |
2592 | ||
2593 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2594 | if (cmd == NULL) | |
2595 | return -ENOMEM; | |
2596 | ||
2597 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID); | |
2598 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2599 | cmd->aid = cpu_to_le16(info->aid); | |
2600 | ||
d89173f2 | 2601 | memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN); |
a66098da | 2602 | |
a66098da LB |
2603 | if (info->use_cts_prot) { |
2604 | prot_mode = MWL8K_FRAME_PROT_11G; | |
2605 | } else { | |
9ed6bcce | 2606 | switch (info->ht_operation_mode & |
a66098da LB |
2607 | IEEE80211_HT_OP_MODE_PROTECTION) { |
2608 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
2609 | prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY; | |
2610 | break; | |
2611 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
2612 | prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL; | |
2613 | break; | |
2614 | default: | |
2615 | prot_mode = MWL8K_FRAME_PROT_DISABLED; | |
2616 | break; | |
2617 | } | |
2618 | } | |
a66098da LB |
2619 | cmd->protection_mode = cpu_to_le16(prot_mode); |
2620 | ||
2621 | for (count = 0; count < mv_vif->legacy_nrates; count++) | |
2622 | cmd->supp_rates[count] = bitrates[count].hw_value; | |
2623 | ||
2624 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2625 | kfree(cmd); | |
2626 | ||
2627 | return rc; | |
2628 | } | |
2629 | ||
2630 | /* | |
2631 | * CMD_SET_RATE. | |
2632 | */ | |
2633 | struct mwl8k_cmd_update_rateset { | |
2634 | struct mwl8k_cmd_pkt header; | |
2635 | __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY]; | |
2636 | ||
2637 | /* Bitmap for supported MCS codes. */ | |
2638 | __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES]; | |
2639 | __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES]; | |
2640 | } __attribute__((packed)); | |
2641 | ||
2642 | static int mwl8k_update_rateset(struct ieee80211_hw *hw, | |
2643 | struct ieee80211_vif *vif) | |
2644 | { | |
2645 | struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); | |
2646 | struct mwl8k_cmd_update_rateset *cmd; | |
2647 | struct ieee80211_rate *bitrates = mv_vif->legacy_rates; | |
2648 | int count; | |
2649 | int rc; | |
2650 | ||
2651 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2652 | if (cmd == NULL) | |
2653 | return -ENOMEM; | |
2654 | ||
2655 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE); | |
2656 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2657 | ||
2658 | for (count = 0; count < mv_vif->legacy_nrates; count++) | |
2659 | cmd->legacy_rates[count] = bitrates[count].hw_value; | |
2660 | ||
2661 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2662 | kfree(cmd); | |
2663 | ||
2664 | return rc; | |
2665 | } | |
2666 | ||
2667 | /* | |
2668 | * CMD_USE_FIXED_RATE. | |
2669 | */ | |
2670 | #define MWL8K_RATE_TABLE_SIZE 8 | |
2671 | #define MWL8K_UCAST_RATE 0 | |
a66098da LB |
2672 | #define MWL8K_USE_AUTO_RATE 0x0002 |
2673 | ||
2674 | struct mwl8k_rate_entry { | |
2675 | /* Set to 1 if HT rate, 0 if legacy. */ | |
2676 | __le32 is_ht_rate; | |
2677 | ||
2678 | /* Set to 1 to use retry_count field. */ | |
2679 | __le32 enable_retry; | |
2680 | ||
2681 | /* Specified legacy rate or MCS. */ | |
2682 | __le32 rate; | |
2683 | ||
2684 | /* Number of allowed retries. */ | |
2685 | __le32 retry_count; | |
2686 | } __attribute__((packed)); | |
2687 | ||
2688 | struct mwl8k_rate_table { | |
2689 | /* 1 to allow specified rate and below */ | |
2690 | __le32 allow_rate_drop; | |
2691 | __le32 num_rates; | |
2692 | struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE]; | |
2693 | } __attribute__((packed)); | |
2694 | ||
2695 | struct mwl8k_cmd_use_fixed_rate { | |
2696 | struct mwl8k_cmd_pkt header; | |
2697 | __le32 action; | |
2698 | struct mwl8k_rate_table rate_table; | |
2699 | ||
2700 | /* Unicast, Broadcast or Multicast */ | |
2701 | __le32 rate_type; | |
2702 | __le32 reserved1; | |
2703 | __le32 reserved2; | |
2704 | } __attribute__((packed)); | |
2705 | ||
2706 | static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw, | |
2707 | u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table) | |
2708 | { | |
2709 | struct mwl8k_cmd_use_fixed_rate *cmd; | |
2710 | int count; | |
2711 | int rc; | |
2712 | ||
2713 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2714 | if (cmd == NULL) | |
2715 | return -ENOMEM; | |
2716 | ||
2717 | cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); | |
2718 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2719 | ||
2720 | cmd->action = cpu_to_le32(action); | |
2721 | cmd->rate_type = cpu_to_le32(rate_type); | |
2722 | ||
2723 | if (rate_table != NULL) { | |
c2c357ce LB |
2724 | /* |
2725 | * Copy over each field manually so that endian | |
2726 | * conversion can be done. | |
2727 | */ | |
a66098da LB |
2728 | cmd->rate_table.allow_rate_drop = |
2729 | cpu_to_le32(rate_table->allow_rate_drop); | |
2730 | cmd->rate_table.num_rates = | |
2731 | cpu_to_le32(rate_table->num_rates); | |
2732 | ||
2733 | for (count = 0; count < rate_table->num_rates; count++) { | |
2734 | struct mwl8k_rate_entry *dst = | |
2735 | &cmd->rate_table.rate_entry[count]; | |
2736 | struct mwl8k_rate_entry *src = | |
2737 | &rate_table->rate_entry[count]; | |
2738 | ||
2739 | dst->is_ht_rate = cpu_to_le32(src->is_ht_rate); | |
2740 | dst->enable_retry = cpu_to_le32(src->enable_retry); | |
2741 | dst->rate = cpu_to_le32(src->rate); | |
2742 | dst->retry_count = cpu_to_le32(src->retry_count); | |
2743 | } | |
2744 | } | |
2745 | ||
2746 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2747 | kfree(cmd); | |
2748 | ||
2749 | return rc; | |
2750 | } | |
2751 | ||
2752 | ||
2753 | /* | |
2754 | * Interrupt handling. | |
2755 | */ | |
2756 | static irqreturn_t mwl8k_interrupt(int irq, void *dev_id) | |
2757 | { | |
2758 | struct ieee80211_hw *hw = dev_id; | |
2759 | struct mwl8k_priv *priv = hw->priv; | |
2760 | u32 status; | |
2761 | ||
2762 | status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2763 | iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2764 | ||
a66098da LB |
2765 | if (!status) |
2766 | return IRQ_NONE; | |
2767 | ||
2768 | if (status & MWL8K_A2H_INT_TX_DONE) | |
2769 | tasklet_schedule(&priv->tx_reclaim_task); | |
2770 | ||
2771 | if (status & MWL8K_A2H_INT_RX_READY) { | |
2772 | while (rxq_process(hw, 0, 1)) | |
2773 | rxq_refill(hw, 0, 1); | |
2774 | } | |
2775 | ||
2776 | if (status & MWL8K_A2H_INT_OPC_DONE) { | |
618952a7 | 2777 | if (priv->hostcmd_wait != NULL) |
a66098da | 2778 | complete(priv->hostcmd_wait); |
a66098da LB |
2779 | } |
2780 | ||
2781 | if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { | |
618952a7 | 2782 | if (!mutex_is_locked(&priv->fw_mutex) && |
88de754a | 2783 | priv->radio_on && priv->pending_tx_pkts) |
618952a7 | 2784 | mwl8k_tx_start(priv); |
a66098da LB |
2785 | } |
2786 | ||
2787 | return IRQ_HANDLED; | |
2788 | } | |
2789 | ||
2790 | ||
2791 | /* | |
2792 | * Core driver operations. | |
2793 | */ | |
2794 | static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |
2795 | { | |
2796 | struct mwl8k_priv *priv = hw->priv; | |
2797 | int index = skb_get_queue_mapping(skb); | |
2798 | int rc; | |
2799 | ||
2800 | if (priv->current_channel == NULL) { | |
2801 | printk(KERN_DEBUG "%s: dropped TX frame since radio " | |
c2c357ce | 2802 | "disabled\n", wiphy_name(hw->wiphy)); |
a66098da LB |
2803 | dev_kfree_skb(skb); |
2804 | return NETDEV_TX_OK; | |
2805 | } | |
2806 | ||
2807 | rc = mwl8k_txq_xmit(hw, index, skb); | |
2808 | ||
2809 | return rc; | |
2810 | } | |
2811 | ||
a66098da LB |
2812 | static int mwl8k_start(struct ieee80211_hw *hw) |
2813 | { | |
a66098da LB |
2814 | struct mwl8k_priv *priv = hw->priv; |
2815 | int rc; | |
2816 | ||
a66098da LB |
2817 | rc = request_irq(priv->pdev->irq, &mwl8k_interrupt, |
2818 | IRQF_SHARED, MWL8K_NAME, hw); | |
2819 | if (rc) { | |
2820 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 2821 | wiphy_name(hw->wiphy)); |
2ec610cb | 2822 | return -EIO; |
a66098da LB |
2823 | } |
2824 | ||
2ec610cb LB |
2825 | /* Enable tx reclaim tasklet */ |
2826 | tasklet_enable(&priv->tx_reclaim_task); | |
2827 | ||
a66098da | 2828 | /* Enable interrupts */ |
c23b5a69 | 2829 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da | 2830 | |
2ec610cb LB |
2831 | rc = mwl8k_fw_lock(hw); |
2832 | if (!rc) { | |
2833 | rc = mwl8k_cmd_802_11_radio_enable(hw); | |
a66098da | 2834 | |
5e4cf166 LB |
2835 | if (!priv->ap_fw) { |
2836 | if (!rc) | |
2837 | rc = mwl8k_enable_sniffer(hw, 0); | |
a66098da | 2838 | |
5e4cf166 LB |
2839 | if (!rc) |
2840 | rc = mwl8k_cmd_set_pre_scan(hw); | |
2841 | ||
2842 | if (!rc) | |
2843 | rc = mwl8k_cmd_set_post_scan(hw, | |
2844 | "\x00\x00\x00\x00\x00\x00"); | |
2845 | } | |
2ec610cb LB |
2846 | |
2847 | if (!rc) | |
2848 | rc = mwl8k_cmd_setrateadaptmode(hw, 0); | |
a66098da | 2849 | |
2ec610cb LB |
2850 | if (!rc) |
2851 | rc = mwl8k_set_wmm(hw, 0); | |
a66098da | 2852 | |
2ec610cb LB |
2853 | mwl8k_fw_unlock(hw); |
2854 | } | |
2855 | ||
2856 | if (rc) { | |
2857 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); | |
2858 | free_irq(priv->pdev->irq, hw); | |
2859 | tasklet_disable(&priv->tx_reclaim_task); | |
2860 | } | |
a66098da LB |
2861 | |
2862 | return rc; | |
2863 | } | |
2864 | ||
a66098da LB |
2865 | static void mwl8k_stop(struct ieee80211_hw *hw) |
2866 | { | |
a66098da LB |
2867 | struct mwl8k_priv *priv = hw->priv; |
2868 | int i; | |
2869 | ||
d3cea0b8 | 2870 | mwl8k_cmd_802_11_radio_disable(hw); |
a66098da LB |
2871 | |
2872 | ieee80211_stop_queues(hw); | |
2873 | ||
a66098da | 2874 | /* Disable interrupts */ |
a66098da | 2875 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
2876 | free_irq(priv->pdev->irq, hw); |
2877 | ||
2878 | /* Stop finalize join worker */ | |
2879 | cancel_work_sync(&priv->finalize_join_worker); | |
2880 | if (priv->beacon_skb != NULL) | |
2881 | dev_kfree_skb(priv->beacon_skb); | |
2882 | ||
2883 | /* Stop tx reclaim tasklet */ | |
2884 | tasklet_disable(&priv->tx_reclaim_task); | |
2885 | ||
a66098da LB |
2886 | /* Return all skbs to mac80211 */ |
2887 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
2888 | mwl8k_txq_reclaim(hw, i, 1); | |
2889 | } | |
2890 | ||
2891 | static int mwl8k_add_interface(struct ieee80211_hw *hw, | |
2892 | struct ieee80211_if_init_conf *conf) | |
2893 | { | |
2894 | struct mwl8k_priv *priv = hw->priv; | |
2895 | struct mwl8k_vif *mwl8k_vif; | |
2896 | ||
2897 | /* | |
2898 | * We only support one active interface at a time. | |
2899 | */ | |
2900 | if (priv->vif != NULL) | |
2901 | return -EBUSY; | |
2902 | ||
2903 | /* | |
2904 | * We only support managed interfaces for now. | |
2905 | */ | |
240e86ef | 2906 | if (conf->type != NL80211_IFTYPE_STATION) |
a66098da LB |
2907 | return -EINVAL; |
2908 | ||
a43c49a8 LB |
2909 | /* |
2910 | * Reject interface creation if sniffer mode is active, as | |
2911 | * STA operation is mutually exclusive with hardware sniffer | |
2912 | * mode. | |
2913 | */ | |
2914 | if (priv->sniffer_enabled) { | |
2915 | printk(KERN_INFO "%s: unable to create STA " | |
2916 | "interface due to sniffer mode being enabled\n", | |
2917 | wiphy_name(hw->wiphy)); | |
2918 | return -EINVAL; | |
2919 | } | |
2920 | ||
a66098da LB |
2921 | /* Clean out driver private area */ |
2922 | mwl8k_vif = MWL8K_VIF(conf->vif); | |
2923 | memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); | |
2924 | ||
32060e1b LB |
2925 | /* Set and save the mac address */ |
2926 | mwl8k_set_mac_addr(hw, conf->mac_addr); | |
d89173f2 | 2927 | memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN); |
a66098da LB |
2928 | |
2929 | /* Back pointer to parent config block */ | |
2930 | mwl8k_vif->priv = priv; | |
2931 | ||
2932 | /* Setup initial PHY parameters */ | |
ce9e2e1b | 2933 | memcpy(mwl8k_vif->legacy_rates, |
a66098da LB |
2934 | priv->rates, sizeof(mwl8k_vif->legacy_rates)); |
2935 | mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates); | |
2936 | ||
2937 | /* Set Initial sequence number to zero */ | |
2938 | mwl8k_vif->seqno = 0; | |
2939 | ||
2940 | priv->vif = conf->vif; | |
2941 | priv->current_channel = NULL; | |
2942 | ||
2943 | return 0; | |
2944 | } | |
2945 | ||
2946 | static void mwl8k_remove_interface(struct ieee80211_hw *hw, | |
2947 | struct ieee80211_if_init_conf *conf) | |
2948 | { | |
2949 | struct mwl8k_priv *priv = hw->priv; | |
2950 | ||
2951 | if (priv->vif == NULL) | |
2952 | return; | |
2953 | ||
32060e1b LB |
2954 | mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
2955 | ||
a66098da LB |
2956 | priv->vif = NULL; |
2957 | } | |
2958 | ||
ee03a932 | 2959 | static int mwl8k_config(struct ieee80211_hw *hw, u32 changed) |
a66098da | 2960 | { |
a66098da LB |
2961 | struct ieee80211_conf *conf = &hw->conf; |
2962 | struct mwl8k_priv *priv = hw->priv; | |
ee03a932 | 2963 | int rc; |
a66098da | 2964 | |
7595d67a LB |
2965 | if (conf->flags & IEEE80211_CONF_IDLE) { |
2966 | mwl8k_cmd_802_11_radio_disable(hw); | |
2967 | priv->current_channel = NULL; | |
ee03a932 | 2968 | return 0; |
7595d67a LB |
2969 | } |
2970 | ||
ee03a932 LB |
2971 | rc = mwl8k_fw_lock(hw); |
2972 | if (rc) | |
2973 | return rc; | |
a66098da | 2974 | |
ee03a932 LB |
2975 | rc = mwl8k_cmd_802_11_radio_enable(hw); |
2976 | if (rc) | |
2977 | goto out; | |
a66098da | 2978 | |
ee03a932 LB |
2979 | rc = mwl8k_cmd_set_rf_channel(hw, conf->channel); |
2980 | if (rc) | |
2981 | goto out; | |
2982 | ||
2983 | priv->current_channel = conf->channel; | |
a66098da LB |
2984 | |
2985 | if (conf->power_level > 18) | |
2986 | conf->power_level = 18; | |
ee03a932 LB |
2987 | rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level); |
2988 | if (rc) | |
2989 | goto out; | |
a66098da | 2990 | |
08b06347 LB |
2991 | if (priv->ap_fw) { |
2992 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7); | |
2993 | if (!rc) | |
2994 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); | |
2995 | } else { | |
2996 | rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); | |
2997 | } | |
a66098da | 2998 | |
ee03a932 LB |
2999 | out: |
3000 | mwl8k_fw_unlock(hw); | |
a66098da | 3001 | |
ee03a932 | 3002 | return rc; |
a66098da LB |
3003 | } |
3004 | ||
3a980d0a LB |
3005 | static void mwl8k_bss_info_changed(struct ieee80211_hw *hw, |
3006 | struct ieee80211_vif *vif, | |
3007 | struct ieee80211_bss_conf *info, | |
3008 | u32 changed) | |
a66098da | 3009 | { |
a66098da LB |
3010 | struct mwl8k_priv *priv = hw->priv; |
3011 | struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif); | |
3a980d0a LB |
3012 | int rc; |
3013 | ||
3014 | if (changed & BSS_CHANGED_BSSID) | |
3015 | memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN); | |
3016 | ||
3017 | if ((changed & BSS_CHANGED_ASSOC) == 0) | |
3018 | return; | |
a66098da | 3019 | |
a66098da LB |
3020 | priv->capture_beacon = false; |
3021 | ||
3a980d0a | 3022 | rc = mwl8k_fw_lock(hw); |
942457d6 | 3023 | if (rc) |
3a980d0a LB |
3024 | return; |
3025 | ||
a66098da LB |
3026 | if (info->assoc) { |
3027 | memcpy(&mwl8k_vif->bss_info, info, | |
3028 | sizeof(struct ieee80211_bss_conf)); | |
3029 | ||
3030 | /* Install rates */ | |
3a980d0a LB |
3031 | rc = mwl8k_update_rateset(hw, vif); |
3032 | if (rc) | |
3033 | goto out; | |
a66098da LB |
3034 | |
3035 | /* Turn on rate adaptation */ | |
3a980d0a LB |
3036 | rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE, |
3037 | MWL8K_UCAST_RATE, NULL); | |
3038 | if (rc) | |
3039 | goto out; | |
a66098da LB |
3040 | |
3041 | /* Set radio preamble */ | |
3a980d0a LB |
3042 | rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble); |
3043 | if (rc) | |
3044 | goto out; | |
a66098da LB |
3045 | |
3046 | /* Set slot time */ | |
3a980d0a LB |
3047 | rc = mwl8k_cmd_set_slot(hw, info->use_short_slot); |
3048 | if (rc) | |
3049 | goto out; | |
a66098da LB |
3050 | |
3051 | /* Update peer rate info */ | |
3a980d0a LB |
3052 | rc = mwl8k_cmd_update_sta_db(hw, vif, |
3053 | MWL8K_STA_DB_MODIFY_ENTRY); | |
3054 | if (rc) | |
3055 | goto out; | |
a66098da LB |
3056 | |
3057 | /* Set AID */ | |
3a980d0a LB |
3058 | rc = mwl8k_cmd_set_aid(hw, vif); |
3059 | if (rc) | |
3060 | goto out; | |
a66098da LB |
3061 | |
3062 | /* | |
3063 | * Finalize the join. Tell rx handler to process | |
3064 | * next beacon from our BSSID. | |
3065 | */ | |
d89173f2 | 3066 | memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN); |
a66098da LB |
3067 | priv->capture_beacon = true; |
3068 | } else { | |
3a980d0a | 3069 | rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY); |
a66098da LB |
3070 | memset(&mwl8k_vif->bss_info, 0, |
3071 | sizeof(struct ieee80211_bss_conf)); | |
d89173f2 | 3072 | memset(mwl8k_vif->bssid, 0, ETH_ALEN); |
a66098da LB |
3073 | } |
3074 | ||
3a980d0a LB |
3075 | out: |
3076 | mwl8k_fw_unlock(hw); | |
a66098da LB |
3077 | } |
3078 | ||
e81cd2d6 LB |
3079 | static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw, |
3080 | int mc_count, struct dev_addr_list *mclist) | |
3081 | { | |
3082 | struct mwl8k_cmd_pkt *cmd; | |
3083 | ||
447ced07 LB |
3084 | /* |
3085 | * Synthesize and return a command packet that programs the | |
3086 | * hardware multicast address filter. At this point we don't | |
3087 | * know whether FIF_ALLMULTI is being requested, but if it is, | |
3088 | * we'll end up throwing this packet away and creating a new | |
3089 | * one in mwl8k_configure_filter(). | |
3090 | */ | |
3091 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist); | |
e81cd2d6 LB |
3092 | |
3093 | return (unsigned long)cmd; | |
3094 | } | |
3095 | ||
a43c49a8 LB |
3096 | static int |
3097 | mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw, | |
3098 | unsigned int changed_flags, | |
3099 | unsigned int *total_flags) | |
3100 | { | |
3101 | struct mwl8k_priv *priv = hw->priv; | |
3102 | ||
3103 | /* | |
3104 | * Hardware sniffer mode is mutually exclusive with STA | |
3105 | * operation, so refuse to enable sniffer mode if a STA | |
3106 | * interface is active. | |
3107 | */ | |
3108 | if (priv->vif != NULL) { | |
3109 | if (net_ratelimit()) | |
3110 | printk(KERN_INFO "%s: not enabling sniffer " | |
3111 | "mode because STA interface is active\n", | |
3112 | wiphy_name(hw->wiphy)); | |
3113 | return 0; | |
3114 | } | |
3115 | ||
3116 | if (!priv->sniffer_enabled) { | |
3117 | if (mwl8k_enable_sniffer(hw, 1)) | |
3118 | return 0; | |
3119 | priv->sniffer_enabled = true; | |
3120 | } | |
3121 | ||
3122 | *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI | | |
3123 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | | |
3124 | FIF_OTHER_BSS; | |
3125 | ||
3126 | return 1; | |
3127 | } | |
3128 | ||
e6935ea1 LB |
3129 | static void mwl8k_configure_filter(struct ieee80211_hw *hw, |
3130 | unsigned int changed_flags, | |
3131 | unsigned int *total_flags, | |
3132 | u64 multicast) | |
3133 | { | |
3134 | struct mwl8k_priv *priv = hw->priv; | |
a43c49a8 LB |
3135 | struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast; |
3136 | ||
c0adae2c LB |
3137 | /* |
3138 | * AP firmware doesn't allow fine-grained control over | |
3139 | * the receive filter. | |
3140 | */ | |
3141 | if (priv->ap_fw) { | |
3142 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; | |
3143 | kfree(cmd); | |
3144 | return; | |
3145 | } | |
3146 | ||
a43c49a8 LB |
3147 | /* |
3148 | * Enable hardware sniffer mode if FIF_CONTROL or | |
3149 | * FIF_OTHER_BSS is requested. | |
3150 | */ | |
3151 | if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) && | |
3152 | mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) { | |
3153 | kfree(cmd); | |
3154 | return; | |
3155 | } | |
a66098da | 3156 | |
e6935ea1 | 3157 | /* Clear unsupported feature flags */ |
447ced07 | 3158 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; |
a66098da | 3159 | |
e6935ea1 LB |
3160 | if (mwl8k_fw_lock(hw)) |
3161 | return; | |
a66098da | 3162 | |
a43c49a8 LB |
3163 | if (priv->sniffer_enabled) { |
3164 | mwl8k_enable_sniffer(hw, 0); | |
3165 | priv->sniffer_enabled = false; | |
3166 | } | |
3167 | ||
e6935ea1 | 3168 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
77165d88 LB |
3169 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { |
3170 | /* | |
3171 | * Disable the BSS filter. | |
3172 | */ | |
e6935ea1 | 3173 | mwl8k_cmd_set_pre_scan(hw); |
77165d88 | 3174 | } else { |
a94cc97e LB |
3175 | u8 *bssid; |
3176 | ||
77165d88 LB |
3177 | /* |
3178 | * Enable the BSS filter. | |
3179 | * | |
3180 | * If there is an active STA interface, use that | |
3181 | * interface's BSSID, otherwise use a dummy one | |
3182 | * (where the OUI part needs to be nonzero for | |
3183 | * the BSSID to be accepted by POST_SCAN). | |
3184 | */ | |
3185 | bssid = "\x01\x00\x00\x00\x00\x00"; | |
a94cc97e LB |
3186 | if (priv->vif != NULL) |
3187 | bssid = MWL8K_VIF(priv->vif)->bssid; | |
3188 | ||
e6935ea1 | 3189 | mwl8k_cmd_set_post_scan(hw, bssid); |
a66098da LB |
3190 | } |
3191 | } | |
3192 | ||
447ced07 LB |
3193 | /* |
3194 | * If FIF_ALLMULTI is being requested, throw away the command | |
3195 | * packet that ->prepare_multicast() built and replace it with | |
3196 | * a command packet that enables reception of all multicast | |
3197 | * packets. | |
3198 | */ | |
3199 | if (*total_flags & FIF_ALLMULTI) { | |
3200 | kfree(cmd); | |
3201 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL); | |
3202 | } | |
3203 | ||
3204 | if (cmd != NULL) { | |
3205 | mwl8k_post_cmd(hw, cmd); | |
3206 | kfree(cmd); | |
e6935ea1 | 3207 | } |
a66098da | 3208 | |
e6935ea1 | 3209 | mwl8k_fw_unlock(hw); |
a66098da LB |
3210 | } |
3211 | ||
a66098da LB |
3212 | static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
3213 | { | |
733d3067 | 3214 | return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value); |
a66098da LB |
3215 | } |
3216 | ||
a66098da LB |
3217 | static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
3218 | const struct ieee80211_tx_queue_params *params) | |
3219 | { | |
3e4f542c | 3220 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 3221 | int rc; |
a66098da | 3222 | |
3e4f542c LB |
3223 | rc = mwl8k_fw_lock(hw); |
3224 | if (!rc) { | |
3225 | if (!priv->wmm_enabled) | |
3226 | rc = mwl8k_set_wmm(hw, 1); | |
a66098da | 3227 | |
3e4f542c LB |
3228 | if (!rc) |
3229 | rc = mwl8k_set_edca_params(hw, queue, | |
3230 | params->cw_min, | |
3231 | params->cw_max, | |
3232 | params->aifs, | |
3233 | params->txop); | |
3234 | ||
3235 | mwl8k_fw_unlock(hw); | |
a66098da | 3236 | } |
3e4f542c | 3237 | |
a66098da LB |
3238 | return rc; |
3239 | } | |
3240 | ||
3241 | static int mwl8k_get_tx_stats(struct ieee80211_hw *hw, | |
3242 | struct ieee80211_tx_queue_stats *stats) | |
3243 | { | |
3244 | struct mwl8k_priv *priv = hw->priv; | |
3245 | struct mwl8k_tx_queue *txq; | |
3246 | int index; | |
3247 | ||
3248 | spin_lock_bh(&priv->tx_lock); | |
3249 | for (index = 0; index < MWL8K_TX_QUEUES; index++) { | |
3250 | txq = priv->txq + index; | |
45eb400d | 3251 | memcpy(&stats[index], &txq->stats, |
a66098da LB |
3252 | sizeof(struct ieee80211_tx_queue_stats)); |
3253 | } | |
3254 | spin_unlock_bh(&priv->tx_lock); | |
a66098da | 3255 | |
954ef509 | 3256 | return 0; |
a66098da LB |
3257 | } |
3258 | ||
3259 | static int mwl8k_get_stats(struct ieee80211_hw *hw, | |
3260 | struct ieee80211_low_level_stats *stats) | |
3261 | { | |
954ef509 | 3262 | return mwl8k_cmd_802_11_get_stat(hw, stats); |
a66098da LB |
3263 | } |
3264 | ||
3265 | static const struct ieee80211_ops mwl8k_ops = { | |
3266 | .tx = mwl8k_tx, | |
3267 | .start = mwl8k_start, | |
3268 | .stop = mwl8k_stop, | |
3269 | .add_interface = mwl8k_add_interface, | |
3270 | .remove_interface = mwl8k_remove_interface, | |
3271 | .config = mwl8k_config, | |
a66098da | 3272 | .bss_info_changed = mwl8k_bss_info_changed, |
3ac64bee | 3273 | .prepare_multicast = mwl8k_prepare_multicast, |
a66098da LB |
3274 | .configure_filter = mwl8k_configure_filter, |
3275 | .set_rts_threshold = mwl8k_set_rts_threshold, | |
3276 | .conf_tx = mwl8k_conf_tx, | |
3277 | .get_tx_stats = mwl8k_get_tx_stats, | |
3278 | .get_stats = mwl8k_get_stats, | |
3279 | }; | |
3280 | ||
3281 | static void mwl8k_tx_reclaim_handler(unsigned long data) | |
3282 | { | |
3283 | int i; | |
3284 | struct ieee80211_hw *hw = (struct ieee80211_hw *) data; | |
3285 | struct mwl8k_priv *priv = hw->priv; | |
3286 | ||
3287 | spin_lock_bh(&priv->tx_lock); | |
3288 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3289 | mwl8k_txq_reclaim(hw, i, 0); | |
3290 | ||
88de754a | 3291 | if (priv->tx_wait != NULL && !priv->pending_tx_pkts) { |
ce9e2e1b LB |
3292 | complete(priv->tx_wait); |
3293 | priv->tx_wait = NULL; | |
a66098da LB |
3294 | } |
3295 | spin_unlock_bh(&priv->tx_lock); | |
3296 | } | |
3297 | ||
3298 | static void mwl8k_finalize_join_worker(struct work_struct *work) | |
3299 | { | |
3300 | struct mwl8k_priv *priv = | |
3301 | container_of(work, struct mwl8k_priv, finalize_join_worker); | |
3302 | struct sk_buff *skb = priv->beacon_skb; | |
ce9e2e1b | 3303 | u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period; |
a66098da LB |
3304 | |
3305 | mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim); | |
3306 | dev_kfree_skb(skb); | |
3307 | ||
3308 | priv->beacon_skb = NULL; | |
3309 | } | |
3310 | ||
6f6d1e9a LB |
3311 | static struct mwl8k_device_info di_8366 = { |
3312 | .part_name = "88w8366", | |
3313 | .helper_image = "mwl8k/helper_8366.fw", | |
3314 | .fw_image = "mwl8k/fmimage_8366.fw", | |
3315 | .rxd_ops = &rxd_8366_ops, | |
3316 | .modes = 0, | |
3317 | }; | |
3318 | ||
45a390dd | 3319 | static struct mwl8k_device_info di_8687 = { |
a74b295e LB |
3320 | .part_name = "88w8687", |
3321 | .helper_image = "mwl8k/helper_8687.fw", | |
3322 | .fw_image = "mwl8k/fmimage_8687.fw", | |
54bc3a0d | 3323 | .rxd_ops = &rxd_8687_ops, |
547810e3 | 3324 | .modes = BIT(NL80211_IFTYPE_STATION), |
45a390dd LB |
3325 | }; |
3326 | ||
3327 | static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = { | |
3328 | { | |
3329 | PCI_VDEVICE(MARVELL, 0x2a2b), | |
3330 | .driver_data = (unsigned long)&di_8687, | |
3331 | }, { | |
3332 | PCI_VDEVICE(MARVELL, 0x2a30), | |
3333 | .driver_data = (unsigned long)&di_8687, | |
6f6d1e9a LB |
3334 | }, { |
3335 | PCI_VDEVICE(MARVELL, 0x2a40), | |
3336 | .driver_data = (unsigned long)&di_8366, | |
45a390dd LB |
3337 | }, { |
3338 | }, | |
3339 | }; | |
3340 | MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table); | |
3341 | ||
a66098da LB |
3342 | static int __devinit mwl8k_probe(struct pci_dev *pdev, |
3343 | const struct pci_device_id *id) | |
3344 | { | |
2aa7b01f | 3345 | static int printed_version = 0; |
a66098da LB |
3346 | struct ieee80211_hw *hw; |
3347 | struct mwl8k_priv *priv; | |
a66098da LB |
3348 | int rc; |
3349 | int i; | |
2aa7b01f LB |
3350 | |
3351 | if (!printed_version) { | |
3352 | printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION); | |
3353 | printed_version = 1; | |
3354 | } | |
a66098da LB |
3355 | |
3356 | rc = pci_enable_device(pdev); | |
3357 | if (rc) { | |
3358 | printk(KERN_ERR "%s: Cannot enable new PCI device\n", | |
3359 | MWL8K_NAME); | |
3360 | return rc; | |
3361 | } | |
3362 | ||
3363 | rc = pci_request_regions(pdev, MWL8K_NAME); | |
3364 | if (rc) { | |
3365 | printk(KERN_ERR "%s: Cannot obtain PCI resources\n", | |
3366 | MWL8K_NAME); | |
3367 | return rc; | |
3368 | } | |
3369 | ||
3370 | pci_set_master(pdev); | |
3371 | ||
3372 | hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops); | |
3373 | if (hw == NULL) { | |
3374 | printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME); | |
3375 | rc = -ENOMEM; | |
3376 | goto err_free_reg; | |
3377 | } | |
3378 | ||
3379 | priv = hw->priv; | |
3380 | priv->hw = hw; | |
3381 | priv->pdev = pdev; | |
45a390dd | 3382 | priv->device_info = (void *)id->driver_data; |
54bc3a0d | 3383 | priv->rxd_ops = priv->device_info->rxd_ops; |
a43c49a8 | 3384 | priv->sniffer_enabled = false; |
0439b1f5 | 3385 | priv->wmm_enabled = false; |
a66098da | 3386 | priv->pending_tx_pkts = 0; |
a66098da | 3387 | |
a66098da LB |
3388 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3389 | pci_set_drvdata(pdev, hw); | |
3390 | ||
5b9482dd LB |
3391 | priv->sram = pci_iomap(pdev, 0, 0x10000); |
3392 | if (priv->sram == NULL) { | |
3393 | printk(KERN_ERR "%s: Cannot map device SRAM\n", | |
c2c357ce | 3394 | wiphy_name(hw->wiphy)); |
a66098da LB |
3395 | goto err_iounmap; |
3396 | } | |
3397 | ||
5b9482dd LB |
3398 | /* |
3399 | * If BAR0 is a 32 bit BAR, the register BAR will be BAR1. | |
3400 | * If BAR0 is a 64 bit BAR, the register BAR will be BAR2. | |
3401 | */ | |
3402 | priv->regs = pci_iomap(pdev, 1, 0x10000); | |
3403 | if (priv->regs == NULL) { | |
3404 | priv->regs = pci_iomap(pdev, 2, 0x10000); | |
3405 | if (priv->regs == NULL) { | |
3406 | printk(KERN_ERR "%s: Cannot map device registers\n", | |
3407 | wiphy_name(hw->wiphy)); | |
3408 | goto err_iounmap; | |
3409 | } | |
3410 | } | |
3411 | ||
a66098da LB |
3412 | memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels)); |
3413 | priv->band.band = IEEE80211_BAND_2GHZ; | |
3414 | priv->band.channels = priv->channels; | |
3415 | priv->band.n_channels = ARRAY_SIZE(mwl8k_channels); | |
3416 | priv->band.bitrates = priv->rates; | |
3417 | priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates); | |
3418 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
3419 | ||
3420 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates)); | |
3421 | memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates)); | |
3422 | ||
3423 | /* | |
3424 | * Extra headroom is the size of the required DMA header | |
3425 | * minus the size of the smallest 802.11 frame (CTS frame). | |
3426 | */ | |
3427 | hw->extra_tx_headroom = | |
3428 | sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts); | |
3429 | ||
3430 | hw->channel_change_time = 10; | |
3431 | ||
3432 | hw->queues = MWL8K_TX_QUEUES; | |
3433 | ||
547810e3 | 3434 | hw->wiphy->interface_modes = priv->device_info->modes; |
a66098da LB |
3435 | |
3436 | /* Set rssi and noise values to dBm */ | |
ce9e2e1b | 3437 | hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; |
a66098da LB |
3438 | hw->vif_data_size = sizeof(struct mwl8k_vif); |
3439 | priv->vif = NULL; | |
3440 | ||
3441 | /* Set default radio state and preamble */ | |
c46563b7 | 3442 | priv->radio_on = 0; |
68ce3884 | 3443 | priv->radio_short_preamble = 0; |
a66098da LB |
3444 | |
3445 | /* Finalize join worker */ | |
3446 | INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker); | |
3447 | ||
3448 | /* TX reclaim tasklet */ | |
3449 | tasklet_init(&priv->tx_reclaim_task, | |
3450 | mwl8k_tx_reclaim_handler, (unsigned long)hw); | |
3451 | tasklet_disable(&priv->tx_reclaim_task); | |
3452 | ||
a66098da LB |
3453 | /* Power management cookie */ |
3454 | priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); | |
3455 | if (priv->cookie == NULL) | |
3456 | goto err_iounmap; | |
3457 | ||
3458 | rc = mwl8k_rxq_init(hw, 0); | |
3459 | if (rc) | |
3460 | goto err_iounmap; | |
3461 | rxq_refill(hw, 0, INT_MAX); | |
3462 | ||
618952a7 LB |
3463 | mutex_init(&priv->fw_mutex); |
3464 | priv->fw_mutex_owner = NULL; | |
3465 | priv->fw_mutex_depth = 0; | |
618952a7 LB |
3466 | priv->hostcmd_wait = NULL; |
3467 | ||
a66098da LB |
3468 | spin_lock_init(&priv->tx_lock); |
3469 | ||
88de754a LB |
3470 | priv->tx_wait = NULL; |
3471 | ||
a66098da LB |
3472 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { |
3473 | rc = mwl8k_txq_init(hw, i); | |
3474 | if (rc) | |
3475 | goto err_free_queues; | |
3476 | } | |
3477 | ||
3478 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
c23b5a69 | 3479 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3480 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL); |
3481 | iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK); | |
3482 | ||
3483 | rc = request_irq(priv->pdev->irq, &mwl8k_interrupt, | |
3484 | IRQF_SHARED, MWL8K_NAME, hw); | |
3485 | if (rc) { | |
3486 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 3487 | wiphy_name(hw->wiphy)); |
a66098da LB |
3488 | goto err_free_queues; |
3489 | } | |
3490 | ||
3491 | /* Reset firmware and hardware */ | |
3492 | mwl8k_hw_reset(priv); | |
3493 | ||
3494 | /* Ask userland hotplug daemon for the device firmware */ | |
45a390dd | 3495 | rc = mwl8k_request_firmware(priv); |
a66098da | 3496 | if (rc) { |
c2c357ce LB |
3497 | printk(KERN_ERR "%s: Firmware files not found\n", |
3498 | wiphy_name(hw->wiphy)); | |
a66098da LB |
3499 | goto err_free_irq; |
3500 | } | |
3501 | ||
3502 | /* Load firmware into hardware */ | |
c2c357ce | 3503 | rc = mwl8k_load_firmware(hw); |
a66098da | 3504 | if (rc) { |
c2c357ce LB |
3505 | printk(KERN_ERR "%s: Cannot start firmware\n", |
3506 | wiphy_name(hw->wiphy)); | |
a66098da LB |
3507 | goto err_stop_firmware; |
3508 | } | |
3509 | ||
3510 | /* Reclaim memory once firmware is successfully loaded */ | |
3511 | mwl8k_release_firmware(priv); | |
3512 | ||
3513 | /* | |
3514 | * Temporarily enable interrupts. Initial firmware host | |
3515 | * commands use interrupts and avoids polling. Disable | |
3516 | * interrupts when done. | |
3517 | */ | |
c23b5a69 | 3518 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3519 | |
3520 | /* Get config data, mac addrs etc */ | |
42fba21d LB |
3521 | if (priv->ap_fw) { |
3522 | rc = mwl8k_cmd_get_hw_spec_ap(hw); | |
3523 | if (!rc) | |
3524 | rc = mwl8k_cmd_set_hw_spec(hw); | |
3525 | } else { | |
3526 | rc = mwl8k_cmd_get_hw_spec_sta(hw); | |
3527 | } | |
a66098da | 3528 | if (rc) { |
c2c357ce LB |
3529 | printk(KERN_ERR "%s: Cannot initialise firmware\n", |
3530 | wiphy_name(hw->wiphy)); | |
a66098da LB |
3531 | goto err_stop_firmware; |
3532 | } | |
3533 | ||
3534 | /* Turn radio off */ | |
c46563b7 | 3535 | rc = mwl8k_cmd_802_11_radio_disable(hw); |
a66098da | 3536 | if (rc) { |
c2c357ce | 3537 | printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy)); |
a66098da LB |
3538 | goto err_stop_firmware; |
3539 | } | |
3540 | ||
32060e1b LB |
3541 | /* Clear MAC address */ |
3542 | rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); | |
3543 | if (rc) { | |
3544 | printk(KERN_ERR "%s: Cannot clear MAC address\n", | |
3545 | wiphy_name(hw->wiphy)); | |
3546 | goto err_stop_firmware; | |
3547 | } | |
3548 | ||
a66098da | 3549 | /* Disable interrupts */ |
a66098da | 3550 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3551 | free_irq(priv->pdev->irq, hw); |
3552 | ||
3553 | rc = ieee80211_register_hw(hw); | |
3554 | if (rc) { | |
c2c357ce LB |
3555 | printk(KERN_ERR "%s: Cannot register device\n", |
3556 | wiphy_name(hw->wiphy)); | |
a66098da LB |
3557 | goto err_stop_firmware; |
3558 | } | |
3559 | ||
eae74e65 | 3560 | printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n", |
a74b295e | 3561 | wiphy_name(hw->wiphy), priv->device_info->part_name, |
45a390dd | 3562 | priv->hw_rev, hw->wiphy->perm_addr, |
eae74e65 | 3563 | priv->ap_fw ? "AP" : "STA", |
2aa7b01f LB |
3564 | (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, |
3565 | (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); | |
a66098da LB |
3566 | |
3567 | return 0; | |
3568 | ||
3569 | err_stop_firmware: | |
3570 | mwl8k_hw_reset(priv); | |
3571 | mwl8k_release_firmware(priv); | |
3572 | ||
3573 | err_free_irq: | |
a66098da | 3574 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3575 | free_irq(priv->pdev->irq, hw); |
3576 | ||
3577 | err_free_queues: | |
3578 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3579 | mwl8k_txq_deinit(hw, i); | |
3580 | mwl8k_rxq_deinit(hw, 0); | |
3581 | ||
3582 | err_iounmap: | |
3583 | if (priv->cookie != NULL) | |
3584 | pci_free_consistent(priv->pdev, 4, | |
3585 | priv->cookie, priv->cookie_dma); | |
3586 | ||
3587 | if (priv->regs != NULL) | |
3588 | pci_iounmap(pdev, priv->regs); | |
3589 | ||
5b9482dd LB |
3590 | if (priv->sram != NULL) |
3591 | pci_iounmap(pdev, priv->sram); | |
3592 | ||
a66098da LB |
3593 | pci_set_drvdata(pdev, NULL); |
3594 | ieee80211_free_hw(hw); | |
3595 | ||
3596 | err_free_reg: | |
3597 | pci_release_regions(pdev); | |
3598 | pci_disable_device(pdev); | |
3599 | ||
3600 | return rc; | |
3601 | } | |
3602 | ||
230f7af0 | 3603 | static void __devexit mwl8k_shutdown(struct pci_dev *pdev) |
a66098da LB |
3604 | { |
3605 | printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__); | |
3606 | } | |
3607 | ||
230f7af0 | 3608 | static void __devexit mwl8k_remove(struct pci_dev *pdev) |
a66098da LB |
3609 | { |
3610 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
3611 | struct mwl8k_priv *priv; | |
3612 | int i; | |
3613 | ||
3614 | if (hw == NULL) | |
3615 | return; | |
3616 | priv = hw->priv; | |
3617 | ||
3618 | ieee80211_stop_queues(hw); | |
3619 | ||
60aa569f LB |
3620 | ieee80211_unregister_hw(hw); |
3621 | ||
a66098da LB |
3622 | /* Remove tx reclaim tasklet */ |
3623 | tasklet_kill(&priv->tx_reclaim_task); | |
3624 | ||
a66098da LB |
3625 | /* Stop hardware */ |
3626 | mwl8k_hw_reset(priv); | |
3627 | ||
3628 | /* Return all skbs to mac80211 */ | |
3629 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3630 | mwl8k_txq_reclaim(hw, i, 1); | |
3631 | ||
a66098da LB |
3632 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
3633 | mwl8k_txq_deinit(hw, i); | |
3634 | ||
3635 | mwl8k_rxq_deinit(hw, 0); | |
3636 | ||
c2c357ce | 3637 | pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma); |
a66098da LB |
3638 | |
3639 | pci_iounmap(pdev, priv->regs); | |
5b9482dd | 3640 | pci_iounmap(pdev, priv->sram); |
a66098da LB |
3641 | pci_set_drvdata(pdev, NULL); |
3642 | ieee80211_free_hw(hw); | |
3643 | pci_release_regions(pdev); | |
3644 | pci_disable_device(pdev); | |
3645 | } | |
3646 | ||
3647 | static struct pci_driver mwl8k_driver = { | |
3648 | .name = MWL8K_NAME, | |
45a390dd | 3649 | .id_table = mwl8k_pci_id_table, |
a66098da LB |
3650 | .probe = mwl8k_probe, |
3651 | .remove = __devexit_p(mwl8k_remove), | |
3652 | .shutdown = __devexit_p(mwl8k_shutdown), | |
3653 | }; | |
3654 | ||
3655 | static int __init mwl8k_init(void) | |
3656 | { | |
3657 | return pci_register_driver(&mwl8k_driver); | |
3658 | } | |
3659 | ||
3660 | static void __exit mwl8k_exit(void) | |
3661 | { | |
3662 | pci_unregister_driver(&mwl8k_driver); | |
3663 | } | |
3664 | ||
3665 | module_init(mwl8k_init); | |
3666 | module_exit(mwl8k_exit); | |
c2c357ce LB |
3667 | |
3668 | MODULE_DESCRIPTION(MWL8K_DESC); | |
3669 | MODULE_VERSION(MWL8K_VERSION); | |
3670 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>"); | |
3671 | MODULE_LICENSE("GPL"); |