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mwl8k: add AP firmware handling to ->start()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status);
88};
89
45a390dd 90struct mwl8k_device_info {
a74b295e
LB		 91 char *part_name;
92 char *helper_image;
93 char *fw_image;
54bc3a0d 94 struct rxd_ops *rxd_ops;
547810e3 95 u16 modes;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
128/* Pointers to the firmware data and meta information about it. */
129struct mwl8k_firmware {
a66098da
LB		 130 /* Boot helper code */
131 struct firmware *helper;
a74b295e
LB		 132
133 /* Microcode */
134 struct firmware *ucode;
a66098da
LB		 135};
136
137struct mwl8k_priv {
5b9482dd 138 void __iomem *sram;
a66098da
LB		 139 void __iomem *regs;
140 struct ieee80211_hw *hw;
141
142 struct pci_dev *pdev;
a66098da 143
45a390dd 144 struct mwl8k_device_info *device_info;
eae74e65 145 bool ap_fw;
54bc3a0d 146 struct rxd_ops *rxd_ops;
45a390dd 147
a66098da
LB		 148 /* firmware files and meta data */
149 struct mwl8k_firmware fw;
a66098da 150
618952a7
LB		 151 /* firmware access */
152 struct mutex fw_mutex;
153 struct task_struct *fw_mutex_owner;
154 int fw_mutex_depth;
618952a7
LB		 155 struct completion *hostcmd_wait;
156
a66098da
LB		 157 /* lock held over TX and TX reap */
158 spinlock_t tx_lock;
a66098da 159
88de754a
LB		 160 /* TX quiesce completion, protected by fw_mutex and tx_lock */
161 struct completion *tx_wait;
162
a66098da 163 struct ieee80211_vif *vif;
a66098da
LB		 164
165 struct ieee80211_channel *current_channel;
166
167 /* power management status cookie from firmware */
168 u32 *cookie;
169 dma_addr_t cookie_dma;
170
171 u16 num_mcaddrs;
a66098da 172 u8 hw_rev;
2aa7b01f 173 u32 fw_rev;
a66098da
LB		 174
175 /*
176 * Running count of TX packets in flight, to avoid
177 * iterating over the transmit rings each time.
178 */
179 int pending_tx_pkts;
180
181 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
182 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
183
184 /* PHY parameters */
185 struct ieee80211_supported_band band;
186 struct ieee80211_channel channels[14];
5dfd3e2c 187 struct ieee80211_rate rates[13];
a66098da 188
c46563b7 189 bool radio_on;
68ce3884 190 bool radio_short_preamble;
a43c49a8 191 bool sniffer_enabled;
0439b1f5 192 bool wmm_enabled;
a66098da 193
a66098da
LB		 194 /* XXX need to convert this to handle multiple interfaces */
195 bool capture_beacon;
d89173f2 196 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 197 struct sk_buff *beacon_skb;
198
199 /*
200 * This FJ worker has to be global as it is scheduled from the
201 * RX handler. At this point we don't know which interface it
202 * belongs to until the list of bssids waiting to complete join
203 * is checked.
204 */
205 struct work_struct finalize_join_worker;
206
207 /* Tasklet to reclaim TX descriptors and buffers after tx */
208 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 209};
210
211/* Per interface specific private data */
212struct mwl8k_vif {
a66098da
LB		 213 /* backpointer to parent config block */
214 struct mwl8k_priv *priv;
215
216 /* BSS config of AP or IBSS from mac80211*/
217 struct ieee80211_bss_conf bss_info;
218
219 /* BSSID of AP or IBSS */
d89173f2
LB		 220 u8 bssid[ETH_ALEN];
221 u8 mac_addr[ETH_ALEN];
a66098da
LB		 222
223 /*
224 * Subset of supported legacy rates.
225 * Intersection of AP and STA supported rates.
226 */
5dfd3e2c 227 struct ieee80211_rate legacy_rates[13];
a66098da
LB		 228
229 /* number of supported legacy rates */
230 u8 legacy_nrates;
231
a66098da
LB		 232 /* Index into station database.Returned by update_sta_db call */
233 u8 peer_id;
234
235 /* Non AMPDU sequence number assigned by driver */
236 u16 seqno;
a66098da
LB		 237};
238
a94cc97e 239#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 240
241static const struct ieee80211_channel mwl8k_channels[] = {
242 { .center_freq = 2412, .hw_value = 1, },
243 { .center_freq = 2417, .hw_value = 2, },
244 { .center_freq = 2422, .hw_value = 3, },
245 { .center_freq = 2427, .hw_value = 4, },
246 { .center_freq = 2432, .hw_value = 5, },
247 { .center_freq = 2437, .hw_value = 6, },
248 { .center_freq = 2442, .hw_value = 7, },
249 { .center_freq = 2447, .hw_value = 8, },
250 { .center_freq = 2452, .hw_value = 9, },
251 { .center_freq = 2457, .hw_value = 10, },
252 { .center_freq = 2462, .hw_value = 11, },
253};
254
255static const struct ieee80211_rate mwl8k_rates[] = {
256 { .bitrate = 10, .hw_value = 2, },
257 { .bitrate = 20, .hw_value = 4, },
258 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 259 { .bitrate = 110, .hw_value = 22, },
260 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 261 { .bitrate = 60, .hw_value = 12, },
262 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 263 { .bitrate = 120, .hw_value = 24, },
264 { .bitrate = 180, .hw_value = 36, },
265 { .bitrate = 240, .hw_value = 48, },
266 { .bitrate = 360, .hw_value = 72, },
267 { .bitrate = 480, .hw_value = 96, },
268 { .bitrate = 540, .hw_value = 108, },
269};
270
a66098da
LB		 271/* Set or get info from Firmware */
272#define MWL8K_CMD_SET 0x0001
273#define MWL8K_CMD_GET 0x0000
274
275/* Firmware command codes */
276#define MWL8K_CMD_CODE_DNLD 0x0001
277#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 278#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 279#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
280#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 281#define MWL8K_CMD_RADIO_CONTROL 0x001c
282#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 283#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 284#define MWL8K_CMD_SET_PRE_SCAN 0x0107
285#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 286#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
287#define MWL8K_CMD_SET_AID 0x010d
288#define MWL8K_CMD_SET_RATE 0x0110
289#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
290#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 291#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 292#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
293#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 294#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 295#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 296#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 297#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 298#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 299#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 300
301static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
302{
303#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
304 snprintf(buf, bufsize, "%s", #x);\
305 return buf;\
306 } while (0)
ce9e2e1b 307 switch (cmd & ~0x8000) {
a66098da
LB		 308 MWL8K_CMDNAME(CODE_DNLD);
309 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 310 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 311 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
312 MWL8K_CMDNAME(GET_STAT);
313 MWL8K_CMDNAME(RADIO_CONTROL);
314 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 315 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 316 MWL8K_CMDNAME(SET_PRE_SCAN);
317 MWL8K_CMDNAME(SET_POST_SCAN);
318 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 319 MWL8K_CMDNAME(SET_AID);
320 MWL8K_CMDNAME(SET_RATE);
321 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
322 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 323 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 324 MWL8K_CMDNAME(SET_EDCA_PARAMS);
325 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 326 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 327 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 328 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 329 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 330 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 331 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 332 default:
333 snprintf(buf, bufsize, "0x%x", cmd);
334 }
335#undef MWL8K_CMDNAME
336
337 return buf;
338}
339
340/* Hardware and firmware reset */
341static void mwl8k_hw_reset(struct mwl8k_priv *priv)
342{
343 iowrite32(MWL8K_H2A_INT_RESET,
344 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
345 iowrite32(MWL8K_H2A_INT_RESET,
346 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
347 msleep(20);
348}
349
350/* Release fw image */
351static void mwl8k_release_fw(struct firmware **fw)
352{
353 if (*fw == NULL)
354 return;
355 release_firmware(*fw);
356 *fw = NULL;
357}
358
359static void mwl8k_release_firmware(struct mwl8k_priv *priv)
360{
361 mwl8k_release_fw(&priv->fw.ucode);
362 mwl8k_release_fw(&priv->fw.helper);
363}
364
365/* Request fw image */
366static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 367 const char *fname, struct firmware **fw)
a66098da
LB		 368{
369 /* release current image */
370 if (*fw != NULL)
371 mwl8k_release_fw(fw);
372
373 return request_firmware((const struct firmware **)fw,
c2c357ce 374 fname, &priv->pdev->dev);
a66098da
LB		 375}
376
45a390dd 377static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 378{
a74b295e 379 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 380 int rc;
381
a74b295e
LB		 382 if (di->helper_image != NULL) {
383 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
384 if (rc) {
385 printk(KERN_ERR "%s: Error requesting helper "
386 "firmware file %s\n", pci_name(priv->pdev),
387 di->helper_image);
388 return rc;
389 }
a66098da
LB		 390 }
391
a74b295e 392 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 393 if (rc) {
c2c357ce 394 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 395 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 396 mwl8k_release_fw(&priv->fw.helper);
397 return rc;
398 }
399
400 return 0;
401}
402
403struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409} __attribute__((packed));
410
411/*
412 * Firmware loading.
413 */
414static int
415mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416{
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
a66098da
LB		 419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
a66098da
LB		 432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 439 break;
440 }
441
3d76e82c 442 cond_resched();
a66098da
LB		 443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
d4b70570 448 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 449}
450
451static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453{
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490}
491
492static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494{
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549}
550
c2c357ce 551static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 552{
c2c357ce
LB		 553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
eae74e65 555 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
a66098da 561
c2c357ce
LB		 562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
a66098da 567
c2c357ce 568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 571 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 572 return rc;
573 }
574 msleep(1);
575
c2c357ce 576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 577 } else {
c2c357ce 578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 579 }
580
581 if (rc) {
c2c357ce
LB		 582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
a66098da
LB		 584 return rc;
585 }
586
eae74e65
LB		 587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da
LB		 591 msleep(1);
592
593 loops = 200000;
594 do {
eae74e65
LB		 595 u32 ready_code;
596
597 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
598 if (ready_code == MWL8K_FWAP_READY) {
599 priv->ap_fw = 1;
600 break;
601 } else if (ready_code == MWL8K_FWSTA_READY) {
602 priv->ap_fw = 0;
a66098da 603 break;
eae74e65
LB		 604 }
605
606 cond_resched();
a66098da
LB		 607 udelay(1);
608 } while (--loops);
609
610 return loops ? 0 : -ETIMEDOUT;
611}
612
613
614/*
615 * Defines shared between transmission and reception.
616 */
617/* HT control fields for firmware */
618struct ewc_ht_info {
619 __le16 control1;
620 __le16 control2;
621 __le16 control3;
622} __attribute__((packed));
623
624/* Firmware Station database operations */
625#define MWL8K_STA_DB_ADD_ENTRY 0
626#define MWL8K_STA_DB_MODIFY_ENTRY 1
627#define MWL8K_STA_DB_DEL_ENTRY 2
628#define MWL8K_STA_DB_FLUSH 3
629
630/* Peer Entry flags - used to define the type of the peer node */
631#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 632
5dfd3e2c 633#define MWL8K_IEEE_LEGACY_DATA_RATES 13
a66098da 634#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 635
636struct peer_capability_info {
637 /* Peer type - AP vs. STA. */
638 __u8 peer_type;
639
640 /* Basic 802.11 capabilities from assoc resp. */
641 __le16 basic_caps;
642
643 /* Set if peer supports 802.11n high throughput (HT). */
644 __u8 ht_support;
645
646 /* Valid if HT is supported. */
647 __le16 ht_caps;
648 __u8 extended_ht_caps;
649 struct ewc_ht_info ewc_info;
650
651 /* Legacy rate table. Intersection of our rates and peer rates. */
652 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
653
654 /* HT rate table. Intersection of our rates and peer rates. */
655 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 656 __u8 pad[16];
a66098da
LB		 657
658 /* If set, interoperability mode, no proprietary extensions. */
659 __u8 interop;
660 __u8 pad2;
661 __u8 station_id;
662 __le16 amsdu_enabled;
663} __attribute__((packed));
664
665/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 666static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
667{
668 u16 val_mask = 1 << 4;
669
670 /* End of Service Period Bit 4 */
671 return qos | val_mask;
672}
673
674static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
675{
676 u16 val_mask = 0x3;
677 u8 shift = 5;
678 u16 qos_mask = ~(val_mask << shift);
679
680 /* Ack Policy Bit 5-6 */
681 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
682}
683
684static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
685{
686 u16 val_mask = 1 << 7;
687
688 /* AMSDU present Bit 7 */
689 return qos | val_mask;
690}
691
692static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
693{
694 u16 val_mask = 0xff;
695 u8 shift = 8;
696 u16 qos_mask = ~(val_mask << shift);
697
698 /* Queue Length Bits 8-15 */
699 return (qos & qos_mask) | ((len & val_mask) << shift);
700}
701
702/* DMA header used by firmware and hardware. */
703struct mwl8k_dma_data {
704 __le16 fwlen;
705 struct ieee80211_hdr wh;
706} __attribute__((packed));
707
708/* Routines to add/remove DMA header from skb. */
76266b2a 709static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
a66098da 710{
76266b2a 711 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
a66098da 712 void *dst, *src = &tr->wh;
76266b2a 713 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
a66098da
LB		 714 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
715
716 dst = (void *)tr + space;
717 if (dst != src) {
718 memmove(dst, src, hdrlen);
719 skb_pull(skb, space);
720 }
a66098da
LB		 721}
722
76266b2a 723static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 724{
725 struct ieee80211_hdr *wh;
726 u32 hdrlen, pktlen;
727 struct mwl8k_dma_data *tr;
728
729 wh = (struct ieee80211_hdr *)skb->data;
730 hdrlen = ieee80211_hdrlen(wh->frame_control);
731 pktlen = skb->len;
732
733 /*
734 * Copy up/down the 802.11 header; the firmware requires
735 * we present a 2-byte payload length followed by a
736 * 4-address header (w/o QoS), followed (optionally) by
737 * any WEP/ExtIV header (but only filled in for CCMP).
738 */
739 if (hdrlen != sizeof(struct mwl8k_dma_data))
740 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
741
742 tr = (struct mwl8k_dma_data *)skb->data;
743 if (wh != &tr->wh)
744 memmove(&tr->wh, wh, hdrlen);
745
746 /* Clear addr4 */
d89173f2 747 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 748
749 /*
750 * Firmware length is the length of the fully formed "802.11
751 * payload". That is, everything except for the 802.11 header.
752 * This includes all crypto material including the MIC.
753 */
754 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 755}
756
757
758/*
759 * Packet reception.
760 */
54bc3a0d 761struct mwl8k_rxd_8687 {
a66098da
LB		 762 __le16 pkt_len;
763 __u8 link_quality;
764 __u8 noise_level;
765 __le32 pkt_phys_addr;
45eb400d 766 __le32 next_rxd_phys_addr;
a66098da
LB		 767 __le16 qos_control;
768 __le16 rate_info;
769 __le32 pad0[4];
770 __u8 rssi;
771 __u8 channel;
772 __le16 pad1;
773 __u8 rx_ctrl;
774 __u8 rx_status;
775 __u8 pad2[2];
776} __attribute__((packed));
777
54bc3a0d
LB		 778#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
779#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
780#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
781#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
782#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
783#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
784
785#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
786
787static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
788{
789 struct mwl8k_rxd_8687 *rxd = _rxd;
790
791 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
792 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
793}
794
795static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
796{
797 struct mwl8k_rxd_8687 *rxd = _rxd;
798
799 rxd->pkt_len = cpu_to_le16(len);
800 rxd->pkt_phys_addr = cpu_to_le32(addr);
801 wmb();
802 rxd->rx_ctrl = 0;
803}
804
805static int
806mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status)
807{
808 struct mwl8k_rxd_8687 *rxd = _rxd;
809 u16 rate_info;
810
811 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
812 return -1;
813 rmb();
814
815 rate_info = le16_to_cpu(rxd->rate_info);
816
817 memset(status, 0, sizeof(*status));
818
819 status->signal = -rxd->rssi;
820 status->noise = -rxd->noise_level;
821 status->qual = rxd->link_quality;
822 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
823 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
824
825 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
826 status->flag |= RX_FLAG_SHORTPRE;
827 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
828 status->flag |= RX_FLAG_40MHZ;
829 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
830 status->flag |= RX_FLAG_SHORT_GI;
831 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
832 status->flag |= RX_FLAG_HT;
833
834 status->band = IEEE80211_BAND_2GHZ;
835 status->freq = ieee80211_channel_to_frequency(rxd->channel);
836
837 return le16_to_cpu(rxd->pkt_len);
838}
839
840static struct rxd_ops rxd_8687_ops = {
841 .rxd_size = sizeof(struct mwl8k_rxd_8687),
842 .rxd_init = mwl8k_rxd_8687_init,
843 .rxd_refill = mwl8k_rxd_8687_refill,
844 .rxd_process = mwl8k_rxd_8687_process,
845};
846
847
a66098da
LB		 848#define MWL8K_RX_DESCS 256
849#define MWL8K_RX_MAXSZ 3800
850
851static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
852{
853 struct mwl8k_priv *priv = hw->priv;
854 struct mwl8k_rx_queue *rxq = priv->rxq + index;
855 int size;
856 int i;
857
45eb400d
LB		 858 rxq->rxd_count = 0;
859 rxq->head = 0;
860 rxq->tail = 0;
a66098da 861
54bc3a0d 862 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 863
45eb400d
LB		 864 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
865 if (rxq->rxd == NULL) {
a66098da 866 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 867 wiphy_name(hw->wiphy));
a66098da
LB		 868 return -ENOMEM;
869 }
45eb400d 870 memset(rxq->rxd, 0, size);
a66098da 871
788838eb
LB		 872 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
873 if (rxq->buf == NULL) {
a66098da 874 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 875 wiphy_name(hw->wiphy));
45eb400d 876 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 877 return -ENOMEM;
878 }
788838eb 879 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 880
881 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 882 int desc_size;
883 void *rxd;
a66098da 884 int nexti;
54bc3a0d
LB		 885 dma_addr_t next_dma_addr;
886
887 desc_size = priv->rxd_ops->rxd_size;
888 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 889
54bc3a0d
LB		 890 nexti = i + 1;
891 if (nexti == MWL8K_RX_DESCS)
892 nexti = 0;
893 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 894
54bc3a0d 895 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 896 }
897
898 return 0;
899}
900
901static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
902{
903 struct mwl8k_priv *priv = hw->priv;
904 struct mwl8k_rx_queue *rxq = priv->rxq + index;
905 int refilled;
906
907 refilled = 0;
45eb400d 908 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 909 struct sk_buff *skb;
788838eb 910 dma_addr_t addr;
a66098da 911 int rx;
54bc3a0d 912 void *rxd;
a66098da
LB		 913
914 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
915 if (skb == NULL)
916 break;
917
788838eb
LB		 918 addr = pci_map_single(priv->pdev, skb->data,
919 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 920
54bc3a0d
LB		 921 rxq->rxd_count++;
922 rx = rxq->tail++;
923 if (rxq->tail == MWL8K_RX_DESCS)
924 rxq->tail = 0;
788838eb
LB		 925 rxq->buf[rx].skb = skb;
926 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 927
928 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
929 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 930
931 refilled++;
932 }
933
934 return refilled;
935}
936
937/* Must be called only when the card's reception is completely halted */
938static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
939{
940 struct mwl8k_priv *priv = hw->priv;
941 struct mwl8k_rx_queue *rxq = priv->rxq + index;
942 int i;
943
944 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 945 if (rxq->buf[i].skb != NULL) {
946 pci_unmap_single(priv->pdev,
947 pci_unmap_addr(&rxq->buf[i], dma),
948 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
949 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
950
951 kfree_skb(rxq->buf[i].skb);
952 rxq->buf[i].skb = NULL;
a66098da
LB		 953 }
954 }
955
788838eb
LB		 956 kfree(rxq->buf);
957 rxq->buf = NULL;
a66098da
LB		 958
959 pci_free_consistent(priv->pdev,
54bc3a0d 960 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 961 rxq->rxd, rxq->rxd_dma);
962 rxq->rxd = NULL;
a66098da
LB		 963}
964
965
966/*
967 * Scan a list of BSSIDs to process for finalize join.
968 * Allows for extension to process multiple BSSIDs.
969 */
970static inline int
971mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
972{
973 return priv->capture_beacon &&
974 ieee80211_is_beacon(wh->frame_control) &&
975 !compare_ether_addr(wh->addr3, priv->capture_bssid);
976}
977
3779752d
LB		 978static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
979 struct sk_buff *skb)
a66098da 980{
3779752d
LB		 981 struct mwl8k_priv *priv = hw->priv;
982
a66098da 983 priv->capture_beacon = false;
d89173f2 984 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 985
986 /*
987 * Use GFP_ATOMIC as rxq_process is called from
988 * the primary interrupt handler, memory allocation call
989 * must not sleep.
990 */
991 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
992 if (priv->beacon_skb != NULL)
3779752d 993 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 994}
995
996static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
997{
998 struct mwl8k_priv *priv = hw->priv;
999 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1000 int processed;
1001
1002 processed = 0;
45eb400d 1003 while (rxq->rxd_count && limit--) {
a66098da 1004 struct sk_buff *skb;
54bc3a0d
LB		 1005 void *rxd;
1006 int pkt_len;
a66098da 1007 struct ieee80211_rx_status status;
a66098da 1008
788838eb 1009 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1010 if (skb == NULL)
1011 break;
54bc3a0d
LB		 1012
1013 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1014
1015 pkt_len = priv->rxd_ops->rxd_process(rxd, &status);
1016 if (pkt_len < 0)
1017 break;
1018
788838eb
LB		 1019 rxq->buf[rxq->head].skb = NULL;
1020
1021 pci_unmap_single(priv->pdev,
1022 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1023 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1024 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1025
54bc3a0d
LB		 1026 rxq->head++;
1027 if (rxq->head == MWL8K_RX_DESCS)
1028 rxq->head = 0;
1029
45eb400d 1030 rxq->rxd_count--;
a66098da 1031
54bc3a0d 1032 skb_put(skb, pkt_len);
76266b2a 1033 mwl8k_remove_dma_header(skb);
a66098da 1034
a66098da 1035 /*
c2c357ce
LB		 1036 * Check for a pending join operation. Save a
1037 * copy of the beacon and schedule a tasklet to
1038 * send a FINALIZE_JOIN command to the firmware.
a66098da 1039 */
54bc3a0d 1040 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1041 mwl8k_save_beacon(hw, skb);
a66098da 1042
f1d58c25
JB		 1043 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1044 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1045
1046 processed++;
1047 }
1048
1049 return processed;
1050}
1051
1052
1053/*
1054 * Packet transmission.
1055 */
1056
a66098da
LB		 1057/* Transmit packet ACK policy */
1058#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1059#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1060
a66098da
LB		 1061#define MWL8K_TXD_STATUS_OK 0x00000001
1062#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1063#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1064#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1065#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1066
1067struct mwl8k_tx_desc {
1068 __le32 status;
1069 __u8 data_rate;
1070 __u8 tx_priority;
1071 __le16 qos_control;
1072 __le32 pkt_phys_addr;
1073 __le16 pkt_len;
d89173f2 1074 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1075 __le32 next_txd_phys_addr;
a66098da
LB		 1076 __le32 reserved;
1077 __le16 rate_info;
1078 __u8 peer_id;
1079 __u8 tx_frag_cnt;
1080} __attribute__((packed));
1081
1082#define MWL8K_TX_DESCS 128
1083
1084static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1085{
1086 struct mwl8k_priv *priv = hw->priv;
1087 struct mwl8k_tx_queue *txq = priv->txq + index;
1088 int size;
1089 int i;
1090
45eb400d
LB		 1091 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1092 txq->stats.limit = MWL8K_TX_DESCS;
1093 txq->head = 0;
1094 txq->tail = 0;
a66098da
LB		 1095
1096 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1097
45eb400d
LB		 1098 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1099 if (txq->txd == NULL) {
a66098da 1100 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1101 wiphy_name(hw->wiphy));
a66098da
LB		 1102 return -ENOMEM;
1103 }
45eb400d 1104 memset(txq->txd, 0, size);
a66098da 1105
45eb400d
LB		 1106 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1107 if (txq->skb == NULL) {
a66098da 1108 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1109 wiphy_name(hw->wiphy));
45eb400d 1110 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1111 return -ENOMEM;
1112 }
45eb400d 1113 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1114
1115 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1116 struct mwl8k_tx_desc *tx_desc;
1117 int nexti;
1118
45eb400d 1119 tx_desc = txq->txd + i;
a66098da
LB		 1120 nexti = (i + 1) % MWL8K_TX_DESCS;
1121
1122 tx_desc->status = 0;
45eb400d
LB		 1123 tx_desc->next_txd_phys_addr =
1124 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1125 }
1126
1127 return 0;
1128}
1129
1130static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1131{
1132 iowrite32(MWL8K_H2A_INT_PPA_READY,
1133 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1134 iowrite32(MWL8K_H2A_INT_DUMMY,
1135 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1136 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1137}
1138
a66098da
LB		 1139struct mwl8k_txq_info {
1140 u32 fw_owned;
1141 u32 drv_owned;
1142 u32 unused;
1143 u32 len;
1144 u32 head;
1145 u32 tail;
1146};
1147
1148static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1149 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1150{
1151 int count, desc, status;
1152 struct mwl8k_tx_queue *txq;
1153 struct mwl8k_tx_desc *tx_desc;
1154 int ndescs = 0;
1155
c3f967d3
LB		 1156 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1157
c3f967d3 1158 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da 1159 txq = priv->txq + count;
45eb400d
LB		 1160 txinfo[count].len = txq->stats.len;
1161 txinfo[count].head = txq->head;
1162 txinfo[count].tail = txq->tail;
a66098da 1163 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
45eb400d 1164 tx_desc = txq->txd + desc;
a66098da
LB		 1165 status = le32_to_cpu(tx_desc->status);
1166
1167 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1168 txinfo[count].fw_owned++;
1169 else
1170 txinfo[count].drv_owned++;
1171
1172 if (tx_desc->pkt_len == 0)
1173 txinfo[count].unused++;
1174 }
1175 }
a66098da
LB		 1176
1177 return ndescs;
1178}
1179
618952a7 1180/*
88de754a 1181 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1182 */
950d5b01 1183static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1184{
a66098da 1185 struct mwl8k_priv *priv = hw->priv;
88de754a 1186 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1187 u32 count;
1188 unsigned long timeout;
a66098da
LB		 1189
1190 might_sleep();
1191
a66098da 1192 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1193 count = priv->pending_tx_pkts;
1194 if (count)
1195 priv->tx_wait = &tx_wait;
a66098da
LB		 1196 spin_unlock_bh(&priv->tx_lock);
1197
1198 if (count) {
c3f967d3 1199 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1200 int index;
1201 int newcount;
1202
88de754a 1203 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1204 msecs_to_jiffies(5000));
a66098da
LB		 1205 if (timeout)
1206 return 0;
1207
1208 spin_lock_bh(&priv->tx_lock);
1209 priv->tx_wait = NULL;
88de754a
LB		 1210 newcount = priv->pending_tx_pkts;
1211 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1212 spin_unlock_bh(&priv->tx_lock);
1213
618952a7 1214 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1215 __func__, __LINE__, count, newcount);
a66098da 1216
c3f967d3 1217 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1218 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1219 "DRV:%u U:%u\n",
a66098da
LB		 1220 index,
1221 txinfo[index].len,
1222 txinfo[index].head,
1223 txinfo[index].tail,
1224 txinfo[index].fw_owned,
1225 txinfo[index].drv_owned,
1226 txinfo[index].unused);
ce9e2e1b 1227
a66098da
LB		 1228 return -ETIMEDOUT;
1229 }
1230
1231 return 0;
1232}
1233
c23b5a69
LB		 1234#define MWL8K_TXD_SUCCESS(status) \
1235 ((status) & (MWL8K_TXD_STATUS_OK | \
1236 MWL8K_TXD_STATUS_OK_RETRY | \
1237 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1238
1239static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1240{
1241 struct mwl8k_priv *priv = hw->priv;
1242 struct mwl8k_tx_queue *txq = priv->txq + index;
1243 int wake = 0;
1244
45eb400d 1245 while (txq->stats.len > 0) {
a66098da 1246 int tx;
a66098da
LB		 1247 struct mwl8k_tx_desc *tx_desc;
1248 unsigned long addr;
ce9e2e1b 1249 int size;
a66098da
LB		 1250 struct sk_buff *skb;
1251 struct ieee80211_tx_info *info;
1252 u32 status;
1253
45eb400d
LB		 1254 tx = txq->head;
1255 tx_desc = txq->txd + tx;
a66098da
LB		 1256
1257 status = le32_to_cpu(tx_desc->status);
1258
1259 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1260 if (!force)
1261 break;
1262 tx_desc->status &=
1263 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1264 }
1265
45eb400d
LB		 1266 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1267 BUG_ON(txq->stats.len == 0);
1268 txq->stats.len--;
a66098da
LB		 1269 priv->pending_tx_pkts--;
1270
1271 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1272 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1273 skb = txq->skb[tx];
1274 txq->skb[tx] = NULL;
a66098da
LB		 1275
1276 BUG_ON(skb == NULL);
1277 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1278
76266b2a 1279 mwl8k_remove_dma_header(skb);
a66098da
LB		 1280
1281 /* Mark descriptor as unused */
1282 tx_desc->pkt_phys_addr = 0;
1283 tx_desc->pkt_len = 0;
1284
a66098da
LB		 1285 info = IEEE80211_SKB_CB(skb);
1286 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1287 if (MWL8K_TXD_SUCCESS(status))
a66098da 1288 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1289
1290 ieee80211_tx_status_irqsafe(hw, skb);
1291
618952a7 1292 wake = 1;
a66098da
LB		 1293 }
1294
618952a7 1295 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1296 ieee80211_wake_queue(hw, index);
1297}
1298
1299/* must be called only when the card's transmit is completely halted */
1300static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1301{
1302 struct mwl8k_priv *priv = hw->priv;
1303 struct mwl8k_tx_queue *txq = priv->txq + index;
1304
1305 mwl8k_txq_reclaim(hw, index, 1);
1306
45eb400d
LB		 1307 kfree(txq->skb);
1308 txq->skb = NULL;
a66098da
LB		 1309
1310 pci_free_consistent(priv->pdev,
1311 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1312 txq->txd, txq->txd_dma);
1313 txq->txd = NULL;
a66098da
LB		 1314}
1315
1316static int
1317mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1318{
1319 struct mwl8k_priv *priv = hw->priv;
1320 struct ieee80211_tx_info *tx_info;
23b33906 1321 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1322 struct ieee80211_hdr *wh;
1323 struct mwl8k_tx_queue *txq;
1324 struct mwl8k_tx_desc *tx;
a66098da 1325 dma_addr_t dma;
23b33906
LB		 1326 u32 txstatus;
1327 u8 txdatarate;
1328 u16 qos;
a66098da 1329
23b33906
LB		 1330 wh = (struct ieee80211_hdr *)skb->data;
1331 if (ieee80211_is_data_qos(wh->frame_control))
1332 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1333 else
1334 qos = 0;
a66098da 1335
76266b2a 1336 mwl8k_add_dma_header(skb);
23b33906 1337 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1338
1339 tx_info = IEEE80211_SKB_CB(skb);
1340 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1341
1342 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1343 u16 seqno = mwl8k_vif->seqno;
23b33906 1344
a66098da
LB		 1345 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1346 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1347 mwl8k_vif->seqno = seqno++ % 4096;
1348 }
1349
23b33906
LB		 1350 /* Setup firmware control bit fields for each frame type. */
1351 txstatus = 0;
1352 txdatarate = 0;
1353 if (ieee80211_is_mgmt(wh->frame_control) ||
1354 ieee80211_is_ctl(wh->frame_control)) {
1355 txdatarate = 0;
1356 qos = mwl8k_qos_setbit_eosp(qos);
1357 /* Set Queue size to unspecified */
1358 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1359 } else if (ieee80211_is_data(wh->frame_control)) {
1360 txdatarate = 1;
1361 if (is_multicast_ether_addr(wh->addr1))
1362 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1363
1364 /* Send pkt in an aggregate if AMPDU frame. */
1365 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1366 qos = mwl8k_qos_setbit_ack(qos,
1367 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1368 else
1369 qos = mwl8k_qos_setbit_ack(qos,
1370 MWL8K_TXD_ACK_POLICY_NORMAL);
1371
1372 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1373 qos = mwl8k_qos_setbit_amsdu(qos);
1374 }
a66098da
LB		 1375
1376 dma = pci_map_single(priv->pdev, skb->data,
1377 skb->len, PCI_DMA_TODEVICE);
1378
1379 if (pci_dma_mapping_error(priv->pdev, dma)) {
1380 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1381 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1382 dev_kfree_skb(skb);
a66098da
LB		 1383 return NETDEV_TX_OK;
1384 }
1385
23b33906 1386 spin_lock_bh(&priv->tx_lock);
a66098da 1387
23b33906 1388 txq = priv->txq + index;
a66098da 1389
45eb400d
LB		 1390 BUG_ON(txq->skb[txq->tail] != NULL);
1391 txq->skb[txq->tail] = skb;
a66098da 1392
45eb400d 1393 tx = txq->txd + txq->tail;
23b33906
LB		 1394 tx->data_rate = txdatarate;
1395 tx->tx_priority = index;
a66098da 1396 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1397 tx->pkt_phys_addr = cpu_to_le32(dma);
1398 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1399 tx->rate_info = 0;
1400 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1401 wmb();
23b33906
LB		 1402 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1403
45eb400d
LB		 1404 txq->stats.count++;
1405 txq->stats.len++;
a66098da 1406 priv->pending_tx_pkts++;
a66098da 1407
45eb400d
LB		 1408 txq->tail++;
1409 if (txq->tail == MWL8K_TX_DESCS)
1410 txq->tail = 0;
23b33906 1411
45eb400d 1412 if (txq->head == txq->tail)
a66098da
LB		 1413 ieee80211_stop_queue(hw, index);
1414
23b33906 1415 mwl8k_tx_start(priv);
a66098da
LB		 1416
1417 spin_unlock_bh(&priv->tx_lock);
1418
1419 return NETDEV_TX_OK;
1420}
1421
1422
618952a7
LB		 1423/*
1424 * Firmware access.
1425 *
1426 * We have the following requirements for issuing firmware commands:
1427 * - Some commands require that the packet transmit path is idle when
1428 * the command is issued. (For simplicity, we'll just quiesce the
1429 * transmit path for every command.)
1430 * - There are certain sequences of commands that need to be issued to
1431 * the hardware sequentially, with no other intervening commands.
1432 *
1433 * This leads to an implementation of a "firmware lock" as a mutex that
1434 * can be taken recursively, and which is taken by both the low-level
1435 * command submission function (mwl8k_post_cmd) as well as any users of
1436 * that function that require issuing of an atomic sequence of commands,
1437 * and quiesces the transmit path whenever it's taken.
1438 */
1439static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1440{
1441 struct mwl8k_priv *priv = hw->priv;
1442
1443 if (priv->fw_mutex_owner != current) {
1444 int rc;
1445
1446 mutex_lock(&priv->fw_mutex);
1447 ieee80211_stop_queues(hw);
1448
1449 rc = mwl8k_tx_wait_empty(hw);
1450 if (rc) {
1451 ieee80211_wake_queues(hw);
1452 mutex_unlock(&priv->fw_mutex);
1453
1454 return rc;
1455 }
1456
1457 priv->fw_mutex_owner = current;
1458 }
1459
1460 priv->fw_mutex_depth++;
1461
1462 return 0;
1463}
1464
1465static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1466{
1467 struct mwl8k_priv *priv = hw->priv;
1468
1469 if (!--priv->fw_mutex_depth) {
1470 ieee80211_wake_queues(hw);
1471 priv->fw_mutex_owner = NULL;
1472 mutex_unlock(&priv->fw_mutex);
1473 }
1474}
1475
1476
a66098da
LB		 1477/*
1478 * Command processing.
1479 */
1480
1481/* Timeout firmware commands after 2000ms */
1482#define MWL8K_CMD_TIMEOUT_MS 2000
1483
1484static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1485{
1486 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1487 struct mwl8k_priv *priv = hw->priv;
1488 void __iomem *regs = priv->regs;
1489 dma_addr_t dma_addr;
1490 unsigned int dma_size;
1491 int rc;
a66098da
LB		 1492 unsigned long timeout = 0;
1493 u8 buf[32];
1494
c2c357ce 1495 cmd->result = 0xffff;
a66098da
LB		 1496 dma_size = le16_to_cpu(cmd->length);
1497 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1498 PCI_DMA_BIDIRECTIONAL);
1499 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1500 return -ENOMEM;
1501
618952a7 1502 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1503 if (rc) {
1504 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1505 PCI_DMA_BIDIRECTIONAL);
618952a7 1506 return rc;
39a1e42e 1507 }
a66098da 1508
a66098da
LB		 1509 priv->hostcmd_wait = &cmd_wait;
1510 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1511 iowrite32(MWL8K_H2A_INT_DOORBELL,
1512 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1513 iowrite32(MWL8K_H2A_INT_DUMMY,
1514 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1515
1516 timeout = wait_for_completion_timeout(&cmd_wait,
1517 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1518
618952a7
LB		 1519 priv->hostcmd_wait = NULL;
1520
1521 mwl8k_fw_unlock(hw);
1522
37055bd4
LB		 1523 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1524 PCI_DMA_BIDIRECTIONAL);
1525
a66098da 1526 if (!timeout) {
a66098da 1527 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1528 wiphy_name(hw->wiphy),
a66098da
LB		 1529 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1530 MWL8K_CMD_TIMEOUT_MS);
1531 rc = -ETIMEDOUT;
1532 } else {
ce9e2e1b 1533 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1534 if (rc)
1535 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1536 wiphy_name(hw->wiphy),
a66098da 1537 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1538 le16_to_cpu(cmd->result));
a66098da
LB		 1539 }
1540
a66098da
LB		 1541 return rc;
1542}
1543
1544/*
04b147b1 1545 * CMD_GET_HW_SPEC (STA version).
a66098da 1546 */
04b147b1 1547struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1548 struct mwl8k_cmd_pkt header;
1549 __u8 hw_rev;
1550 __u8 host_interface;
1551 __le16 num_mcaddrs;
d89173f2 1552 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1553 __le16 region_code;
1554 __le32 fw_rev;
1555 __le32 ps_cookie;
1556 __le32 caps;
1557 __u8 mcs_bitmap[16];
1558 __le32 rx_queue_ptr;
1559 __le32 num_tx_queues;
1560 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1561 __le32 caps2;
1562 __le32 num_tx_desc_per_queue;
45eb400d 1563 __le32 total_rxd;
a66098da
LB		 1564} __attribute__((packed));
1565
04b147b1 1566static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1567{
1568 struct mwl8k_priv *priv = hw->priv;
04b147b1 1569 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1570 int rc;
1571 int i;
1572
1573 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1574 if (cmd == NULL)
1575 return -ENOMEM;
1576
1577 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1578 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1579
1580 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1581 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1582 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1583 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1584 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1585 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1586 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1587 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1588
1589 rc = mwl8k_post_cmd(hw, &cmd->header);
1590
1591 if (!rc) {
1592 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1593 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1594 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1595 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1596 }
1597
1598 kfree(cmd);
1599 return rc;
1600}
1601
42fba21d
LB		 1602/*
1603 * CMD_GET_HW_SPEC (AP version).
1604 */
1605struct mwl8k_cmd_get_hw_spec_ap {
1606 struct mwl8k_cmd_pkt header;
1607 __u8 hw_rev;
1608 __u8 host_interface;
1609 __le16 num_wcb;
1610 __le16 num_mcaddrs;
1611 __u8 perm_addr[ETH_ALEN];
1612 __le16 region_code;
1613 __le16 num_antenna;
1614 __le32 fw_rev;
1615 __le32 wcbbase0;
1616 __le32 rxwrptr;
1617 __le32 rxrdptr;
1618 __le32 ps_cookie;
1619 __le32 wcbbase1;
1620 __le32 wcbbase2;
1621 __le32 wcbbase3;
1622} __attribute__((packed));
1623
1624static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1625{
1626 struct mwl8k_priv *priv = hw->priv;
1627 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1628 int rc;
1629
1630 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1631 if (cmd == NULL)
1632 return -ENOMEM;
1633
1634 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1635 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1636
1637 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1638 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1639
1640 rc = mwl8k_post_cmd(hw, &cmd->header);
1641
1642 if (!rc) {
1643 int off;
1644
1645 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1646 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1647 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1648 priv->hw_rev = cmd->hw_rev;
1649
1650 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1651 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1652
1653 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1654 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1655
1656 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1657 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1658
1659 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1660 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1661
1662 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1663 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1664
1665 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1666 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1667 }
1668
1669 kfree(cmd);
1670 return rc;
1671}
1672
1673/*
1674 * CMD_SET_HW_SPEC.
1675 */
1676struct mwl8k_cmd_set_hw_spec {
1677 struct mwl8k_cmd_pkt header;
1678 __u8 hw_rev;
1679 __u8 host_interface;
1680 __le16 num_mcaddrs;
1681 __u8 perm_addr[ETH_ALEN];
1682 __le16 region_code;
1683 __le32 fw_rev;
1684 __le32 ps_cookie;
1685 __le32 caps;
1686 __le32 rx_queue_ptr;
1687 __le32 num_tx_queues;
1688 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1689 __le32 flags;
1690 __le32 num_tx_desc_per_queue;
1691 __le32 total_rxd;
1692} __attribute__((packed));
1693
1694#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1695
1696static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1697{
1698 struct mwl8k_priv *priv = hw->priv;
1699 struct mwl8k_cmd_set_hw_spec *cmd;
1700 int rc;
1701 int i;
1702
1703 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1704 if (cmd == NULL)
1705 return -ENOMEM;
1706
1707 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1708 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1709
1710 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1711 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1712 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1713 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1714 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1715 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1716 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1717 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1718
1719 rc = mwl8k_post_cmd(hw, &cmd->header);
1720 kfree(cmd);
1721
1722 return rc;
1723}
1724
a66098da
LB		 1725/*
1726 * CMD_MAC_MULTICAST_ADR.
1727 */
1728struct mwl8k_cmd_mac_multicast_adr {
1729 struct mwl8k_cmd_pkt header;
1730 __le16 action;
1731 __le16 numaddr;
ce9e2e1b 1732 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1733};
1734
d5e30845
LB		 1735#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1736#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1737#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1738#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1739
e81cd2d6 1740static struct mwl8k_cmd_pkt *
447ced07 1741__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1742 int mc_count, struct dev_addr_list *mclist)
a66098da 1743{
e81cd2d6 1744 struct mwl8k_priv *priv = hw->priv;
a66098da 1745 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1746 int size;
e81cd2d6 1747
447ced07 1748 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1749 allmulti = 1;
1750 mc_count = 0;
1751 }
e81cd2d6
LB		 1752
1753 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1754
e81cd2d6 1755 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1756 if (cmd == NULL)
e81cd2d6 1757 return NULL;
a66098da
LB		 1758
1759 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1760 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1761 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1762 MWL8K_ENABLE_RX_BROADCAST);
1763
1764 if (allmulti) {
1765 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1766 } else if (mc_count) {
1767 int i;
1768
1769 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1770 cmd->numaddr = cpu_to_le16(mc_count);
1771 for (i = 0; i < mc_count && mclist; i++) {
1772 if (mclist->da_addrlen != ETH_ALEN) {
1773 kfree(cmd);
1774 return NULL;
1775 }
1776 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1777 mclist = mclist->next;
a66098da 1778 }
a66098da
LB		 1779 }
1780
e81cd2d6 1781 return &cmd->header;
a66098da
LB		 1782}
1783
1784/*
1785 * CMD_802_11_GET_STAT.
1786 */
1787struct mwl8k_cmd_802_11_get_stat {
1788 struct mwl8k_cmd_pkt header;
a66098da
LB		 1789 __le32 stats[64];
1790} __attribute__((packed));
1791
1792#define MWL8K_STAT_ACK_FAILURE 9
1793#define MWL8K_STAT_RTS_FAILURE 12
1794#define MWL8K_STAT_FCS_ERROR 24
1795#define MWL8K_STAT_RTS_SUCCESS 11
1796
1797static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1798 struct ieee80211_low_level_stats *stats)
1799{
1800 struct mwl8k_cmd_802_11_get_stat *cmd;
1801 int rc;
1802
1803 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1804 if (cmd == NULL)
1805 return -ENOMEM;
1806
1807 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1808 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1809
1810 rc = mwl8k_post_cmd(hw, &cmd->header);
1811 if (!rc) {
1812 stats->dot11ACKFailureCount =
1813 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1814 stats->dot11RTSFailureCount =
1815 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1816 stats->dot11FCSErrorCount =
1817 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1818 stats->dot11RTSSuccessCount =
1819 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1820 }
1821 kfree(cmd);
1822
1823 return rc;
1824}
1825
1826/*
1827 * CMD_802_11_RADIO_CONTROL.
1828 */
1829struct mwl8k_cmd_802_11_radio_control {
1830 struct mwl8k_cmd_pkt header;
1831 __le16 action;
1832 __le16 control;
1833 __le16 radio_on;
1834} __attribute__((packed));
1835
c46563b7
LB		 1836static int
1837mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1838{
1839 struct mwl8k_priv *priv = hw->priv;
1840 struct mwl8k_cmd_802_11_radio_control *cmd;
1841 int rc;
1842
c46563b7 1843 if (enable == priv->radio_on && !force)
a66098da
LB		 1844 return 0;
1845
a66098da
LB		 1846 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1847 if (cmd == NULL)
1848 return -ENOMEM;
1849
1850 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1851 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1852 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1853 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1854 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1855
1856 rc = mwl8k_post_cmd(hw, &cmd->header);
1857 kfree(cmd);
1858
1859 if (!rc)
c46563b7 1860 priv->radio_on = enable;
a66098da
LB		 1861
1862 return rc;
1863}
1864
c46563b7
LB		 1865static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1866{
1867 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1868}
1869
1870static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1871{
1872 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1873}
1874
a66098da
LB		 1875static int
1876mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1877{
1878 struct mwl8k_priv *priv;
1879
1880 if (hw == NULL || hw->priv == NULL)
1881 return -EINVAL;
1882 priv = hw->priv;
1883
68ce3884 1884 priv->radio_short_preamble = short_preamble;
a66098da 1885
c46563b7 1886 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1887}
1888
1889/*
1890 * CMD_802_11_RF_TX_POWER.
1891 */
1892#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1893
1894struct mwl8k_cmd_802_11_rf_tx_power {
1895 struct mwl8k_cmd_pkt header;
1896 __le16 action;
1897 __le16 support_level;
1898 __le16 current_level;
1899 __le16 reserved;
1900 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1901} __attribute__((packed));
1902
1903static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1904{
1905 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1906 int rc;
1907
1908 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1909 if (cmd == NULL)
1910 return -ENOMEM;
1911
1912 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1913 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1914 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1915 cmd->support_level = cpu_to_le16(dBm);
1916
1917 rc = mwl8k_post_cmd(hw, &cmd->header);
1918 kfree(cmd);
1919
1920 return rc;
1921}
1922
08b06347
LB		 1923/*
1924 * CMD_RF_ANTENNA.
1925 */
1926struct mwl8k_cmd_rf_antenna {
1927 struct mwl8k_cmd_pkt header;
1928 __le16 antenna;
1929 __le16 mode;
1930} __attribute__((packed));
1931
1932#define MWL8K_RF_ANTENNA_RX 1
1933#define MWL8K_RF_ANTENNA_TX 2
1934
1935static int
1936mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
1937{
1938 struct mwl8k_cmd_rf_antenna *cmd;
1939 int rc;
1940
1941 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1942 if (cmd == NULL)
1943 return -ENOMEM;
1944
1945 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
1946 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1947 cmd->antenna = cpu_to_le16(antenna);
1948 cmd->mode = cpu_to_le16(mask);
1949
1950 rc = mwl8k_post_cmd(hw, &cmd->header);
1951 kfree(cmd);
1952
1953 return rc;
1954}
1955
a66098da
LB		 1956/*
1957 * CMD_SET_PRE_SCAN.
1958 */
1959struct mwl8k_cmd_set_pre_scan {
1960 struct mwl8k_cmd_pkt header;
1961} __attribute__((packed));
1962
1963static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1964{
1965 struct mwl8k_cmd_set_pre_scan *cmd;
1966 int rc;
1967
1968 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1969 if (cmd == NULL)
1970 return -ENOMEM;
1971
1972 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1973 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1974
1975 rc = mwl8k_post_cmd(hw, &cmd->header);
1976 kfree(cmd);
1977
1978 return rc;
1979}
1980
1981/*
1982 * CMD_SET_POST_SCAN.
1983 */
1984struct mwl8k_cmd_set_post_scan {
1985 struct mwl8k_cmd_pkt header;
1986 __le32 isibss;
d89173f2 1987 __u8 bssid[ETH_ALEN];
a66098da
LB		 1988} __attribute__((packed));
1989
1990static int
ce9e2e1b 1991mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 1992{
1993 struct mwl8k_cmd_set_post_scan *cmd;
1994 int rc;
1995
1996 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1997 if (cmd == NULL)
1998 return -ENOMEM;
1999
2000 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2001 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2002 cmd->isibss = 0;
d89173f2 2003 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2004
2005 rc = mwl8k_post_cmd(hw, &cmd->header);
2006 kfree(cmd);
2007
2008 return rc;
2009}
2010
2011/*
2012 * CMD_SET_RF_CHANNEL.
2013 */
2014struct mwl8k_cmd_set_rf_channel {
2015 struct mwl8k_cmd_pkt header;
2016 __le16 action;
2017 __u8 current_channel;
2018 __le32 channel_flags;
2019} __attribute__((packed));
2020
2021static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2022 struct ieee80211_channel *channel)
2023{
2024 struct mwl8k_cmd_set_rf_channel *cmd;
2025 int rc;
2026
2027 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2028 if (cmd == NULL)
2029 return -ENOMEM;
2030
2031 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2032 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2033 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2034 cmd->current_channel = channel->hw_value;
2035 if (channel->band == IEEE80211_BAND_2GHZ)
2036 cmd->channel_flags = cpu_to_le32(0x00000081);
2037 else
2038 cmd->channel_flags = cpu_to_le32(0x00000000);
2039
2040 rc = mwl8k_post_cmd(hw, &cmd->header);
2041 kfree(cmd);
2042
2043 return rc;
2044}
2045
2046/*
2047 * CMD_SET_SLOT.
2048 */
2049struct mwl8k_cmd_set_slot {
2050 struct mwl8k_cmd_pkt header;
2051 __le16 action;
2052 __u8 short_slot;
2053} __attribute__((packed));
2054
5539bb51 2055static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 2056{
2057 struct mwl8k_cmd_set_slot *cmd;
2058 int rc;
2059
2060 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2061 if (cmd == NULL)
2062 return -ENOMEM;
2063
2064 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2065 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2066 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 2067 cmd->short_slot = short_slot_time;
a66098da
LB		 2068
2069 rc = mwl8k_post_cmd(hw, &cmd->header);
2070 kfree(cmd);
2071
2072 return rc;
2073}
2074
2075/*
2076 * CMD_MIMO_CONFIG.
2077 */
2078struct mwl8k_cmd_mimo_config {
2079 struct mwl8k_cmd_pkt header;
2080 __le32 action;
2081 __u8 rx_antenna_map;
2082 __u8 tx_antenna_map;
2083} __attribute__((packed));
2084
2085static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2086{
2087 struct mwl8k_cmd_mimo_config *cmd;
2088 int rc;
2089
2090 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2091 if (cmd == NULL)
2092 return -ENOMEM;
2093
2094 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2095 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2096 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2097 cmd->rx_antenna_map = rx;
2098 cmd->tx_antenna_map = tx;
2099
2100 rc = mwl8k_post_cmd(hw, &cmd->header);
2101 kfree(cmd);
2102
2103 return rc;
2104}
2105
2106/*
2107 * CMD_ENABLE_SNIFFER.
2108 */
2109struct mwl8k_cmd_enable_sniffer {
2110 struct mwl8k_cmd_pkt header;
2111 __le32 action;
2112} __attribute__((packed));
2113
2114static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2115{
2116 struct mwl8k_cmd_enable_sniffer *cmd;
2117 int rc;
2118
2119 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2120 if (cmd == NULL)
2121 return -ENOMEM;
2122
2123 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2124 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2125 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 2126
2127 rc = mwl8k_post_cmd(hw, &cmd->header);
2128 kfree(cmd);
2129
2130 return rc;
2131}
2132
32060e1b
LB		 2133/*
2134 * CMD_SET_MAC_ADDR.
2135 */
2136struct mwl8k_cmd_set_mac_addr {
2137 struct mwl8k_cmd_pkt header;
2138 __u8 mac_addr[ETH_ALEN];
2139} __attribute__((packed));
2140
2141static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2142{
2143 struct mwl8k_cmd_set_mac_addr *cmd;
2144 int rc;
2145
2146 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2147 if (cmd == NULL)
2148 return -ENOMEM;
2149
2150 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2151 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2152 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2153
2154 rc = mwl8k_post_cmd(hw, &cmd->header);
2155 kfree(cmd);
2156
2157 return rc;
2158}
2159
2160
a66098da 2161/*
ce9e2e1b 2162 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2163 */
2164struct mwl8k_cmd_set_rate_adapt_mode {
2165 struct mwl8k_cmd_pkt header;
2166 __le16 action;
2167 __le16 mode;
2168} __attribute__((packed));
2169
2170static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2171{
2172 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2173 int rc;
2174
2175 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2176 if (cmd == NULL)
2177 return -ENOMEM;
2178
2179 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2180 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2181 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2182 cmd->mode = cpu_to_le16(mode);
2183
2184 rc = mwl8k_post_cmd(hw, &cmd->header);
2185 kfree(cmd);
2186
2187 return rc;
2188}
2189
2190/*
2191 * CMD_SET_WMM_MODE.
2192 */
2193struct mwl8k_cmd_set_wmm {
2194 struct mwl8k_cmd_pkt header;
2195 __le16 action;
2196} __attribute__((packed));
2197
2198static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2199{
2200 struct mwl8k_priv *priv = hw->priv;
2201 struct mwl8k_cmd_set_wmm *cmd;
2202 int rc;
2203
2204 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2205 if (cmd == NULL)
2206 return -ENOMEM;
2207
2208 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2209 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2210 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2211
2212 rc = mwl8k_post_cmd(hw, &cmd->header);
2213 kfree(cmd);
2214
2215 if (!rc)
0439b1f5 2216 priv->wmm_enabled = enable;
a66098da
LB		 2217
2218 return rc;
2219}
2220
2221/*
2222 * CMD_SET_RTS_THRESHOLD.
2223 */
2224struct mwl8k_cmd_rts_threshold {
2225 struct mwl8k_cmd_pkt header;
2226 __le16 action;
2227 __le16 threshold;
2228} __attribute__((packed));
2229
2230static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2231 u16 action, u16 threshold)
a66098da
LB		 2232{
2233 struct mwl8k_cmd_rts_threshold *cmd;
2234 int rc;
2235
2236 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2237 if (cmd == NULL)
2238 return -ENOMEM;
2239
2240 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2241 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2242 cmd->action = cpu_to_le16(action);
733d3067 2243 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2244
2245 rc = mwl8k_post_cmd(hw, &cmd->header);
2246 kfree(cmd);
2247
2248 return rc;
2249}
2250
2251/*
2252 * CMD_SET_EDCA_PARAMS.
2253 */
2254struct mwl8k_cmd_set_edca_params {
2255 struct mwl8k_cmd_pkt header;
2256
2257 /* See MWL8K_SET_EDCA_XXX below */
2258 __le16 action;
2259
2260 /* TX opportunity in units of 32 us */
2261 __le16 txop;
2262
2263 /* Log exponent of max contention period: 0...15*/
2264 __u8 log_cw_max;
2265
2266 /* Log exponent of min contention period: 0...15 */
2267 __u8 log_cw_min;
2268
2269 /* Adaptive interframe spacing in units of 32us */
2270 __u8 aifs;
2271
2272 /* TX queue to configure */
2273 __u8 txq;
2274} __attribute__((packed));
2275
a66098da
LB		 2276#define MWL8K_SET_EDCA_CW 0x01
2277#define MWL8K_SET_EDCA_TXOP 0x02
2278#define MWL8K_SET_EDCA_AIFS 0x04
2279
2280#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2281 MWL8K_SET_EDCA_TXOP | \
2282 MWL8K_SET_EDCA_AIFS)
2283
2284static int
2285mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2286 __u16 cw_min, __u16 cw_max,
2287 __u8 aifs, __u16 txop)
2288{
2289 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2290 int rc;
2291
2292 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2293 if (cmd == NULL)
2294 return -ENOMEM;
2295
22995b24
LB		 2296 /*
2297 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2298 * this call.
2299 */
2300 qnum ^= !(qnum >> 1);
2301
a66098da
LB		 2302 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2303 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2304 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2305 cmd->txop = cpu_to_le16(txop);
ce9e2e1b
LB		 2306 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2307 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
a66098da
LB		 2308 cmd->aifs = aifs;
2309 cmd->txq = qnum;
2310
2311 rc = mwl8k_post_cmd(hw, &cmd->header);
2312 kfree(cmd);
2313
2314 return rc;
2315}
2316
2317/*
2318 * CMD_FINALIZE_JOIN.
2319 */
2320
2321/* FJ beacon buffer size is compiled into the firmware. */
2322#define MWL8K_FJ_BEACON_MAXLEN 128
2323
2324struct mwl8k_cmd_finalize_join {
2325 struct mwl8k_cmd_pkt header;
2326 __le32 sleep_interval; /* Number of beacon periods to sleep */
2327 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2328} __attribute__((packed));
2329
2330static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2331 __u16 framelen, __u16 dtim)
2332{
2333 struct mwl8k_cmd_finalize_join *cmd;
2334 struct ieee80211_mgmt *payload = frame;
2335 u16 hdrlen;
2336 u32 payload_len;
2337 int rc;
2338
2339 if (frame == NULL)
2340 return -EINVAL;
2341
2342 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2343 if (cmd == NULL)
2344 return -ENOMEM;
2345
2346 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2347 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2348 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2349
2350 hdrlen = ieee80211_hdrlen(payload->frame_control);
2351
2352 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2353
2354 /* XXX TBD Might just have to abort and return an error */
2355 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2356 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2357 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2358 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2359
ce9e2e1b
LB		 2360 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2361 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2362
2363 if (payload && payload_len)
2364 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2365
2366 rc = mwl8k_post_cmd(hw, &cmd->header);
2367 kfree(cmd);
2368 return rc;
2369}
2370
2371/*
2372 * CMD_UPDATE_STADB.
2373 */
2374struct mwl8k_cmd_update_sta_db {
2375 struct mwl8k_cmd_pkt header;
2376
2377 /* See STADB_ACTION_TYPE */
2378 __le32 action;
2379
2380 /* Peer MAC address */
d89173f2 2381 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2382
2383 __le32 reserved;
2384
2385 /* Peer info - valid during add/update. */
2386 struct peer_capability_info peer_info;
2387} __attribute__((packed));
2388
2389static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2390 struct ieee80211_vif *vif, __u32 action)
2391{
2392 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2393 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2394 struct mwl8k_cmd_update_sta_db *cmd;
2395 struct peer_capability_info *peer_info;
2396 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2397 int rc;
2398 __u8 count, *rates;
2399
2400 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2401 if (cmd == NULL)
2402 return -ENOMEM;
2403
2404 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2405 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2406
2407 cmd->action = cpu_to_le32(action);
2408 peer_info = &cmd->peer_info;
d89173f2 2409 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2410
2411 switch (action) {
2412 case MWL8K_STA_DB_ADD_ENTRY:
2413 case MWL8K_STA_DB_MODIFY_ENTRY:
2414 /* Build peer_info block */
2415 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2416 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2417 peer_info->interop = 1;
2418 peer_info->amsdu_enabled = 0;
2419
2420 rates = peer_info->legacy_rates;
ce9e2e1b 2421 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2422 rates[count] = bitrates[count].hw_value;
2423
2424 rc = mwl8k_post_cmd(hw, &cmd->header);
2425 if (rc == 0)
2426 mv_vif->peer_id = peer_info->station_id;
2427
2428 break;
2429
2430 case MWL8K_STA_DB_DEL_ENTRY:
2431 case MWL8K_STA_DB_FLUSH:
2432 default:
2433 rc = mwl8k_post_cmd(hw, &cmd->header);
2434 if (rc == 0)
2435 mv_vif->peer_id = 0;
2436 break;
2437 }
2438 kfree(cmd);
2439
2440 return rc;
2441}
2442
2443/*
2444 * CMD_SET_AID.
2445 */
a66098da
LB		 2446#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2447
2448#define MWL8K_FRAME_PROT_DISABLED 0x00
2449#define MWL8K_FRAME_PROT_11G 0x07
2450#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2451#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2452
2453struct mwl8k_cmd_update_set_aid {
2454 struct mwl8k_cmd_pkt header;
2455 __le16 aid;
2456
2457 /* AP's MAC address (BSSID) */
d89173f2 2458 __u8 bssid[ETH_ALEN];
a66098da
LB		 2459 __le16 protection_mode;
2460 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2461} __attribute__((packed));
2462
2463static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2464 struct ieee80211_vif *vif)
2465{
2466 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2467 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2468 struct mwl8k_cmd_update_set_aid *cmd;
2469 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2470 int count;
2471 u16 prot_mode;
2472 int rc;
2473
2474 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2475 if (cmd == NULL)
2476 return -ENOMEM;
2477
2478 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2479 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2480 cmd->aid = cpu_to_le16(info->aid);
2481
d89173f2 2482 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2483
a66098da
LB		 2484 if (info->use_cts_prot) {
2485 prot_mode = MWL8K_FRAME_PROT_11G;
2486 } else {
9ed6bcce 2487 switch (info->ht_operation_mode &
a66098da
LB		 2488 IEEE80211_HT_OP_MODE_PROTECTION) {
2489 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2490 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2491 break;
2492 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2493 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2494 break;
2495 default:
2496 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2497 break;
2498 }
2499 }
a66098da
LB		 2500 cmd->protection_mode = cpu_to_le16(prot_mode);
2501
2502 for (count = 0; count < mv_vif->legacy_nrates; count++)
2503 cmd->supp_rates[count] = bitrates[count].hw_value;
2504
2505 rc = mwl8k_post_cmd(hw, &cmd->header);
2506 kfree(cmd);
2507
2508 return rc;
2509}
2510
2511/*
2512 * CMD_SET_RATE.
2513 */
2514struct mwl8k_cmd_update_rateset {
2515 struct mwl8k_cmd_pkt header;
2516 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2517
2518 /* Bitmap for supported MCS codes. */
2519 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2520 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2521} __attribute__((packed));
2522
2523static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2524 struct ieee80211_vif *vif)
2525{
2526 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2527 struct mwl8k_cmd_update_rateset *cmd;
2528 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2529 int count;
2530 int rc;
2531
2532 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2533 if (cmd == NULL)
2534 return -ENOMEM;
2535
2536 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2537 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2538
2539 for (count = 0; count < mv_vif->legacy_nrates; count++)
2540 cmd->legacy_rates[count] = bitrates[count].hw_value;
2541
2542 rc = mwl8k_post_cmd(hw, &cmd->header);
2543 kfree(cmd);
2544
2545 return rc;
2546}
2547
2548/*
2549 * CMD_USE_FIXED_RATE.
2550 */
2551#define MWL8K_RATE_TABLE_SIZE 8
2552#define MWL8K_UCAST_RATE 0
a66098da
LB		 2553#define MWL8K_USE_AUTO_RATE 0x0002
2554
2555struct mwl8k_rate_entry {
2556 /* Set to 1 if HT rate, 0 if legacy. */
2557 __le32 is_ht_rate;
2558
2559 /* Set to 1 to use retry_count field. */
2560 __le32 enable_retry;
2561
2562 /* Specified legacy rate or MCS. */
2563 __le32 rate;
2564
2565 /* Number of allowed retries. */
2566 __le32 retry_count;
2567} __attribute__((packed));
2568
2569struct mwl8k_rate_table {
2570 /* 1 to allow specified rate and below */
2571 __le32 allow_rate_drop;
2572 __le32 num_rates;
2573 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2574} __attribute__((packed));
2575
2576struct mwl8k_cmd_use_fixed_rate {
2577 struct mwl8k_cmd_pkt header;
2578 __le32 action;
2579 struct mwl8k_rate_table rate_table;
2580
2581 /* Unicast, Broadcast or Multicast */
2582 __le32 rate_type;
2583 __le32 reserved1;
2584 __le32 reserved2;
2585} __attribute__((packed));
2586
2587static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2588 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2589{
2590 struct mwl8k_cmd_use_fixed_rate *cmd;
2591 int count;
2592 int rc;
2593
2594 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2595 if (cmd == NULL)
2596 return -ENOMEM;
2597
2598 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2599 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2600
2601 cmd->action = cpu_to_le32(action);
2602 cmd->rate_type = cpu_to_le32(rate_type);
2603
2604 if (rate_table != NULL) {
c2c357ce
LB		 2605 /*
2606 * Copy over each field manually so that endian
2607 * conversion can be done.
2608 */
a66098da
LB		 2609 cmd->rate_table.allow_rate_drop =
2610 cpu_to_le32(rate_table->allow_rate_drop);
2611 cmd->rate_table.num_rates =
2612 cpu_to_le32(rate_table->num_rates);
2613
2614 for (count = 0; count < rate_table->num_rates; count++) {
2615 struct mwl8k_rate_entry *dst =
2616 &cmd->rate_table.rate_entry[count];
2617 struct mwl8k_rate_entry *src =
2618 &rate_table->rate_entry[count];
2619
2620 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2621 dst->enable_retry = cpu_to_le32(src->enable_retry);
2622 dst->rate = cpu_to_le32(src->rate);
2623 dst->retry_count = cpu_to_le32(src->retry_count);
2624 }
2625 }
2626
2627 rc = mwl8k_post_cmd(hw, &cmd->header);
2628 kfree(cmd);
2629
2630 return rc;
2631}
2632
2633
2634/*
2635 * Interrupt handling.
2636 */
2637static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2638{
2639 struct ieee80211_hw *hw = dev_id;
2640 struct mwl8k_priv *priv = hw->priv;
2641 u32 status;
2642
2643 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2644 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2645
a66098da
LB		 2646 if (!status)
2647 return IRQ_NONE;
2648
2649 if (status & MWL8K_A2H_INT_TX_DONE)
2650 tasklet_schedule(&priv->tx_reclaim_task);
2651
2652 if (status & MWL8K_A2H_INT_RX_READY) {
2653 while (rxq_process(hw, 0, 1))
2654 rxq_refill(hw, 0, 1);
2655 }
2656
2657 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2658 if (priv->hostcmd_wait != NULL)
a66098da 2659 complete(priv->hostcmd_wait);
a66098da
LB		 2660 }
2661
2662 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2663 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2664 priv->radio_on && priv->pending_tx_pkts)
618952a7 2665 mwl8k_tx_start(priv);
a66098da
LB		 2666 }
2667
2668 return IRQ_HANDLED;
2669}
2670
2671
2672/*
2673 * Core driver operations.
2674 */
2675static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2676{
2677 struct mwl8k_priv *priv = hw->priv;
2678 int index = skb_get_queue_mapping(skb);
2679 int rc;
2680
2681 if (priv->current_channel == NULL) {
2682 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2683 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2684 dev_kfree_skb(skb);
2685 return NETDEV_TX_OK;
2686 }
2687
2688 rc = mwl8k_txq_xmit(hw, index, skb);
2689
2690 return rc;
2691}
2692
a66098da
LB		 2693static int mwl8k_start(struct ieee80211_hw *hw)
2694{
a66098da
LB		 2695 struct mwl8k_priv *priv = hw->priv;
2696 int rc;
2697
a66098da
LB		 2698 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2699 IRQF_SHARED, MWL8K_NAME, hw);
2700 if (rc) {
2701 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2702 wiphy_name(hw->wiphy));
2ec610cb 2703 return -EIO;
a66098da
LB		 2704 }
2705
2ec610cb
LB		 2706 /* Enable tx reclaim tasklet */
2707 tasklet_enable(&priv->tx_reclaim_task);
2708
a66098da 2709 /* Enable interrupts */
c23b5a69 2710 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2711
2ec610cb
LB		 2712 rc = mwl8k_fw_lock(hw);
2713 if (!rc) {
2714 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2715
5e4cf166
LB		 2716 if (!priv->ap_fw) {
2717 if (!rc)
2718 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2719
5e4cf166
LB		 2720 if (!rc)
2721 rc = mwl8k_cmd_set_pre_scan(hw);
2722
2723 if (!rc)
2724 rc = mwl8k_cmd_set_post_scan(hw,
2725 "\x00\x00\x00\x00\x00\x00");
2726 }
2ec610cb
LB		 2727
2728 if (!rc)
2729 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2730
2ec610cb
LB		 2731 if (!rc)
2732 rc = mwl8k_set_wmm(hw, 0);
a66098da 2733
2ec610cb
LB		 2734 mwl8k_fw_unlock(hw);
2735 }
2736
2737 if (rc) {
2738 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2739 free_irq(priv->pdev->irq, hw);
2740 tasklet_disable(&priv->tx_reclaim_task);
2741 }
a66098da
LB		 2742
2743 return rc;
2744}
2745
a66098da
LB		 2746static void mwl8k_stop(struct ieee80211_hw *hw)
2747{
a66098da
LB		 2748 struct mwl8k_priv *priv = hw->priv;
2749 int i;
2750
d3cea0b8 2751 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2752
2753 ieee80211_stop_queues(hw);
2754
a66098da 2755 /* Disable interrupts */
a66098da 2756 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2757 free_irq(priv->pdev->irq, hw);
2758
2759 /* Stop finalize join worker */
2760 cancel_work_sync(&priv->finalize_join_worker);
2761 if (priv->beacon_skb != NULL)
2762 dev_kfree_skb(priv->beacon_skb);
2763
2764 /* Stop tx reclaim tasklet */
2765 tasklet_disable(&priv->tx_reclaim_task);
2766
a66098da
LB		 2767 /* Return all skbs to mac80211 */
2768 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2769 mwl8k_txq_reclaim(hw, i, 1);
2770}
2771
2772static int mwl8k_add_interface(struct ieee80211_hw *hw,
2773 struct ieee80211_if_init_conf *conf)
2774{
2775 struct mwl8k_priv *priv = hw->priv;
2776 struct mwl8k_vif *mwl8k_vif;
2777
2778 /*
2779 * We only support one active interface at a time.
2780 */
2781 if (priv->vif != NULL)
2782 return -EBUSY;
2783
2784 /*
2785 * We only support managed interfaces for now.
2786 */
240e86ef 2787 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2788 return -EINVAL;
2789
a43c49a8
LB		 2790 /*
2791 * Reject interface creation if sniffer mode is active, as
2792 * STA operation is mutually exclusive with hardware sniffer
2793 * mode.
2794 */
2795 if (priv->sniffer_enabled) {
2796 printk(KERN_INFO "%s: unable to create STA "
2797 "interface due to sniffer mode being enabled\n",
2798 wiphy_name(hw->wiphy));
2799 return -EINVAL;
2800 }
2801
a66098da
LB		 2802 /* Clean out driver private area */
2803 mwl8k_vif = MWL8K_VIF(conf->vif);
2804 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2805
32060e1b
LB		 2806 /* Set and save the mac address */
2807 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2808 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2809
2810 /* Back pointer to parent config block */
2811 mwl8k_vif->priv = priv;
2812
2813 /* Setup initial PHY parameters */
ce9e2e1b 2814 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2815 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2816 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2817
2818 /* Set Initial sequence number to zero */
2819 mwl8k_vif->seqno = 0;
2820
2821 priv->vif = conf->vif;
2822 priv->current_channel = NULL;
2823
2824 return 0;
2825}
2826
2827static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2828 struct ieee80211_if_init_conf *conf)
2829{
2830 struct mwl8k_priv *priv = hw->priv;
2831
2832 if (priv->vif == NULL)
2833 return;
2834
32060e1b
LB		 2835 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2836
a66098da
LB		 2837 priv->vif = NULL;
2838}
2839
ee03a932 2840static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2841{
a66098da
LB		 2842 struct ieee80211_conf *conf = &hw->conf;
2843 struct mwl8k_priv *priv = hw->priv;
ee03a932 2844 int rc;
a66098da 2845
7595d67a
LB		 2846 if (conf->flags & IEEE80211_CONF_IDLE) {
2847 mwl8k_cmd_802_11_radio_disable(hw);
2848 priv->current_channel = NULL;
ee03a932 2849 return 0;
7595d67a
LB		 2850 }
2851
ee03a932
LB		 2852 rc = mwl8k_fw_lock(hw);
2853 if (rc)
2854 return rc;
a66098da 2855
ee03a932
LB		 2856 rc = mwl8k_cmd_802_11_radio_enable(hw);
2857 if (rc)
2858 goto out;
a66098da 2859
ee03a932
LB		 2860 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2861 if (rc)
2862 goto out;
2863
2864 priv->current_channel = conf->channel;
a66098da
LB		 2865
2866 if (conf->power_level > 18)
2867 conf->power_level = 18;
ee03a932
LB		 2868 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2869 if (rc)
2870 goto out;
a66098da 2871
08b06347
LB		 2872 if (priv->ap_fw) {
2873 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2874 if (!rc)
2875 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2876 } else {
2877 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2878 }
a66098da 2879
ee03a932
LB		 2880out:
2881 mwl8k_fw_unlock(hw);
a66098da 2882
ee03a932 2883 return rc;
a66098da
LB		 2884}
2885
3a980d0a
LB		 2886static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2887 struct ieee80211_vif *vif,
2888 struct ieee80211_bss_conf *info,
2889 u32 changed)
a66098da 2890{
a66098da
LB		 2891 struct mwl8k_priv *priv = hw->priv;
2892 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 2893 int rc;
2894
2895 if (changed & BSS_CHANGED_BSSID)
2896 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2897
2898 if ((changed & BSS_CHANGED_ASSOC) == 0)
2899 return;
a66098da 2900
a66098da
LB		 2901 priv->capture_beacon = false;
2902
3a980d0a 2903 rc = mwl8k_fw_lock(hw);
942457d6 2904 if (rc)
3a980d0a
LB		 2905 return;
2906
a66098da
LB		 2907 if (info->assoc) {
2908 memcpy(&mwl8k_vif->bss_info, info,
2909 sizeof(struct ieee80211_bss_conf));
2910
2911 /* Install rates */
3a980d0a
LB		 2912 rc = mwl8k_update_rateset(hw, vif);
2913 if (rc)
2914 goto out;
a66098da
LB		 2915
2916 /* Turn on rate adaptation */
3a980d0a
LB		 2917 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2918 MWL8K_UCAST_RATE, NULL);
2919 if (rc)
2920 goto out;
a66098da
LB		 2921
2922 /* Set radio preamble */
3a980d0a
LB		 2923 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2924 if (rc)
2925 goto out;
a66098da
LB		 2926
2927 /* Set slot time */
3a980d0a
LB		 2928 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2929 if (rc)
2930 goto out;
a66098da
LB		 2931
2932 /* Update peer rate info */
3a980d0a
LB		 2933 rc = mwl8k_cmd_update_sta_db(hw, vif,
2934 MWL8K_STA_DB_MODIFY_ENTRY);
2935 if (rc)
2936 goto out;
a66098da
LB		 2937
2938 /* Set AID */
3a980d0a
LB		 2939 rc = mwl8k_cmd_set_aid(hw, vif);
2940 if (rc)
2941 goto out;
a66098da
LB		 2942
2943 /*
2944 * Finalize the join. Tell rx handler to process
2945 * next beacon from our BSSID.
2946 */
d89173f2 2947 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 2948 priv->capture_beacon = true;
2949 } else {
3a980d0a 2950 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 2951 memset(&mwl8k_vif->bss_info, 0,
2952 sizeof(struct ieee80211_bss_conf));
d89173f2 2953 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 2954 }
2955
3a980d0a
LB		 2956out:
2957 mwl8k_fw_unlock(hw);
a66098da
LB		 2958}
2959
e81cd2d6
LB		 2960static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2961 int mc_count, struct dev_addr_list *mclist)
2962{
2963 struct mwl8k_cmd_pkt *cmd;
2964
447ced07
LB		 2965 /*
2966 * Synthesize and return a command packet that programs the
2967 * hardware multicast address filter. At this point we don't
2968 * know whether FIF_ALLMULTI is being requested, but if it is,
2969 * we'll end up throwing this packet away and creating a new
2970 * one in mwl8k_configure_filter().
2971 */
2972 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 2973
2974 return (unsigned long)cmd;
2975}
2976
a43c49a8
LB		 2977static int
2978mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2979 unsigned int changed_flags,
2980 unsigned int *total_flags)
2981{
2982 struct mwl8k_priv *priv = hw->priv;
2983
2984 /*
2985 * Hardware sniffer mode is mutually exclusive with STA
2986 * operation, so refuse to enable sniffer mode if a STA
2987 * interface is active.
2988 */
2989 if (priv->vif != NULL) {
2990 if (net_ratelimit())
2991 printk(KERN_INFO "%s: not enabling sniffer "
2992 "mode because STA interface is active\n",
2993 wiphy_name(hw->wiphy));
2994 return 0;
2995 }
2996
2997 if (!priv->sniffer_enabled) {
2998 if (mwl8k_enable_sniffer(hw, 1))
2999 return 0;
3000 priv->sniffer_enabled = true;
3001 }
3002
3003 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3004 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3005 FIF_OTHER_BSS;
3006
3007 return 1;
3008}
3009
e6935ea1
LB		 3010static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3011 unsigned int changed_flags,
3012 unsigned int *total_flags,
3013 u64 multicast)
3014{
3015 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3016 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3017
c0adae2c
LB		 3018 /*
3019 * AP firmware doesn't allow fine-grained control over
3020 * the receive filter.
3021 */
3022 if (priv->ap_fw) {
3023 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3024 kfree(cmd);
3025 return;
3026 }
3027
a43c49a8
LB		 3028 /*
3029 * Enable hardware sniffer mode if FIF_CONTROL or
3030 * FIF_OTHER_BSS is requested.
3031 */
3032 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3033 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3034 kfree(cmd);
3035 return;
3036 }
a66098da 3037
e6935ea1 3038 /* Clear unsupported feature flags */
447ced07 3039 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3040
e6935ea1
LB		 3041 if (mwl8k_fw_lock(hw))
3042 return;
a66098da 3043
a43c49a8
LB		 3044 if (priv->sniffer_enabled) {
3045 mwl8k_enable_sniffer(hw, 0);
3046 priv->sniffer_enabled = false;
3047 }
3048
e6935ea1 3049 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3050 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3051 /*
3052 * Disable the BSS filter.
3053 */
e6935ea1 3054 mwl8k_cmd_set_pre_scan(hw);
77165d88 3055 } else {
a94cc97e
LB		 3056 u8 *bssid;
3057
77165d88
LB		 3058 /*
3059 * Enable the BSS filter.
3060 *
3061 * If there is an active STA interface, use that
3062 * interface's BSSID, otherwise use a dummy one
3063 * (where the OUI part needs to be nonzero for
3064 * the BSSID to be accepted by POST_SCAN).
3065 */
3066 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 3067 if (priv->vif != NULL)
3068 bssid = MWL8K_VIF(priv->vif)->bssid;
3069
e6935ea1 3070 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3071 }
3072 }
3073
447ced07
LB		 3074 /*
3075 * If FIF_ALLMULTI is being requested, throw away the command
3076 * packet that ->prepare_multicast() built and replace it with
3077 * a command packet that enables reception of all multicast
3078 * packets.
3079 */
3080 if (*total_flags & FIF_ALLMULTI) {
3081 kfree(cmd);
3082 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3083 }
3084
3085 if (cmd != NULL) {
3086 mwl8k_post_cmd(hw, cmd);
3087 kfree(cmd);
e6935ea1 3088 }
a66098da 3089
e6935ea1 3090 mwl8k_fw_unlock(hw);
a66098da
LB		 3091}
3092
a66098da
LB		 3093static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3094{
733d3067 3095 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3096}
3097
a66098da
LB		 3098static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3099 const struct ieee80211_tx_queue_params *params)
3100{
3e4f542c 3101 struct mwl8k_priv *priv = hw->priv;
a66098da 3102 int rc;
a66098da 3103
3e4f542c
LB		 3104 rc = mwl8k_fw_lock(hw);
3105 if (!rc) {
3106 if (!priv->wmm_enabled)
3107 rc = mwl8k_set_wmm(hw, 1);
a66098da 3108
3e4f542c
LB		 3109 if (!rc)
3110 rc = mwl8k_set_edca_params(hw, queue,
3111 params->cw_min,
3112 params->cw_max,
3113 params->aifs,
3114 params->txop);
3115
3116 mwl8k_fw_unlock(hw);
a66098da 3117 }
3e4f542c 3118
a66098da
LB		 3119 return rc;
3120}
3121
3122static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3123 struct ieee80211_tx_queue_stats *stats)
3124{
3125 struct mwl8k_priv *priv = hw->priv;
3126 struct mwl8k_tx_queue *txq;
3127 int index;
3128
3129 spin_lock_bh(&priv->tx_lock);
3130 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3131 txq = priv->txq + index;
45eb400d 3132 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3133 sizeof(struct ieee80211_tx_queue_stats));
3134 }
3135 spin_unlock_bh(&priv->tx_lock);
a66098da 3136
954ef509 3137 return 0;
a66098da
LB		 3138}
3139
3140static int mwl8k_get_stats(struct ieee80211_hw *hw,
3141 struct ieee80211_low_level_stats *stats)
3142{
954ef509 3143 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 3144}
3145
3146static const struct ieee80211_ops mwl8k_ops = {
3147 .tx = mwl8k_tx,
3148 .start = mwl8k_start,
3149 .stop = mwl8k_stop,
3150 .add_interface = mwl8k_add_interface,
3151 .remove_interface = mwl8k_remove_interface,
3152 .config = mwl8k_config,
a66098da 3153 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3154 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3155 .configure_filter = mwl8k_configure_filter,
3156 .set_rts_threshold = mwl8k_set_rts_threshold,
3157 .conf_tx = mwl8k_conf_tx,
3158 .get_tx_stats = mwl8k_get_tx_stats,
3159 .get_stats = mwl8k_get_stats,
3160};
3161
3162static void mwl8k_tx_reclaim_handler(unsigned long data)
3163{
3164 int i;
3165 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3166 struct mwl8k_priv *priv = hw->priv;
3167
3168 spin_lock_bh(&priv->tx_lock);
3169 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3170 mwl8k_txq_reclaim(hw, i, 0);
3171
88de754a 3172 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3173 complete(priv->tx_wait);
3174 priv->tx_wait = NULL;
a66098da
LB		 3175 }
3176 spin_unlock_bh(&priv->tx_lock);
3177}
3178
3179static void mwl8k_finalize_join_worker(struct work_struct *work)
3180{
3181 struct mwl8k_priv *priv =
3182 container_of(work, struct mwl8k_priv, finalize_join_worker);
3183 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3184 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3185
3186 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3187 dev_kfree_skb(skb);
3188
3189 priv->beacon_skb = NULL;
3190}
3191
45a390dd 3192static struct mwl8k_device_info di_8687 = {
a74b295e
LB		 3193 .part_name = "88w8687",
3194 .helper_image = "mwl8k/helper_8687.fw",
3195 .fw_image = "mwl8k/fmimage_8687.fw",
54bc3a0d 3196 .rxd_ops = &rxd_8687_ops,
547810e3 3197 .modes = BIT(NL80211_IFTYPE_STATION),
45a390dd
LB		 3198};
3199
3200static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3201 {
3202 PCI_VDEVICE(MARVELL, 0x2a2b),
3203 .driver_data = (unsigned long)&di_8687,
3204 }, {
3205 PCI_VDEVICE(MARVELL, 0x2a30),
3206 .driver_data = (unsigned long)&di_8687,
3207 }, {
3208 },
3209};
3210MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3211
a66098da
LB		 3212static int __devinit mwl8k_probe(struct pci_dev *pdev,
3213 const struct pci_device_id *id)
3214{
2aa7b01f 3215 static int printed_version = 0;
a66098da
LB		 3216 struct ieee80211_hw *hw;
3217 struct mwl8k_priv *priv;
a66098da
LB		 3218 int rc;
3219 int i;
2aa7b01f
LB		 3220
3221 if (!printed_version) {
3222 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3223 printed_version = 1;
3224 }
a66098da
LB		 3225
3226 rc = pci_enable_device(pdev);
3227 if (rc) {
3228 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3229 MWL8K_NAME);
3230 return rc;
3231 }
3232
3233 rc = pci_request_regions(pdev, MWL8K_NAME);
3234 if (rc) {
3235 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3236 MWL8K_NAME);
3237 return rc;
3238 }
3239
3240 pci_set_master(pdev);
3241
3242 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3243 if (hw == NULL) {
3244 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3245 rc = -ENOMEM;
3246 goto err_free_reg;
3247 }
3248
3249 priv = hw->priv;
3250 priv->hw = hw;
3251 priv->pdev = pdev;
45a390dd 3252 priv->device_info = (void *)id->driver_data;
54bc3a0d 3253 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3254 priv->sniffer_enabled = false;
0439b1f5 3255 priv->wmm_enabled = false;
a66098da 3256 priv->pending_tx_pkts = 0;
a66098da 3257
a66098da
LB		 3258 SET_IEEE80211_DEV(hw, &pdev->dev);
3259 pci_set_drvdata(pdev, hw);
3260
5b9482dd
LB		 3261 priv->sram = pci_iomap(pdev, 0, 0x10000);
3262 if (priv->sram == NULL) {
3263 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3264 wiphy_name(hw->wiphy));
a66098da
LB		 3265 goto err_iounmap;
3266 }
3267
5b9482dd
LB		 3268 /*
3269 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3270 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3271 */
3272 priv->regs = pci_iomap(pdev, 1, 0x10000);
3273 if (priv->regs == NULL) {
3274 priv->regs = pci_iomap(pdev, 2, 0x10000);
3275 if (priv->regs == NULL) {
3276 printk(KERN_ERR "%s: Cannot map device registers\n",
3277 wiphy_name(hw->wiphy));
3278 goto err_iounmap;
3279 }
3280 }
3281
a66098da
LB		 3282 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3283 priv->band.band = IEEE80211_BAND_2GHZ;
3284 priv->band.channels = priv->channels;
3285 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3286 priv->band.bitrates = priv->rates;
3287 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3288 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3289
3290 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3291 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3292
3293 /*
3294 * Extra headroom is the size of the required DMA header
3295 * minus the size of the smallest 802.11 frame (CTS frame).
3296 */
3297 hw->extra_tx_headroom =
3298 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3299
3300 hw->channel_change_time = 10;
3301
3302 hw->queues = MWL8K_TX_QUEUES;
3303
547810e3 3304 hw->wiphy->interface_modes = priv->device_info->modes;
a66098da
LB		 3305
3306 /* Set rssi and noise values to dBm */
ce9e2e1b 3307 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3308 hw->vif_data_size = sizeof(struct mwl8k_vif);
3309 priv->vif = NULL;
3310
3311 /* Set default radio state and preamble */
c46563b7 3312 priv->radio_on = 0;
68ce3884 3313 priv->radio_short_preamble = 0;
a66098da
LB		 3314
3315 /* Finalize join worker */
3316 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3317
3318 /* TX reclaim tasklet */
3319 tasklet_init(&priv->tx_reclaim_task,
3320 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3321 tasklet_disable(&priv->tx_reclaim_task);
3322
a66098da
LB		 3323 /* Power management cookie */
3324 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3325 if (priv->cookie == NULL)
3326 goto err_iounmap;
3327
3328 rc = mwl8k_rxq_init(hw, 0);
3329 if (rc)
3330 goto err_iounmap;
3331 rxq_refill(hw, 0, INT_MAX);
3332
618952a7
LB		 3333 mutex_init(&priv->fw_mutex);
3334 priv->fw_mutex_owner = NULL;
3335 priv->fw_mutex_depth = 0;
618952a7
LB		 3336 priv->hostcmd_wait = NULL;
3337
a66098da
LB		 3338 spin_lock_init(&priv->tx_lock);
3339
88de754a
LB		 3340 priv->tx_wait = NULL;
3341
a66098da
LB		 3342 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3343 rc = mwl8k_txq_init(hw, i);
3344 if (rc)
3345 goto err_free_queues;
3346 }
3347
3348 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3349 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3350 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3351 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3352
3353 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3354 IRQF_SHARED, MWL8K_NAME, hw);
3355 if (rc) {
3356 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3357 wiphy_name(hw->wiphy));
a66098da
LB		 3358 goto err_free_queues;
3359 }
3360
3361 /* Reset firmware and hardware */
3362 mwl8k_hw_reset(priv);
3363
3364 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3365 rc = mwl8k_request_firmware(priv);
a66098da 3366 if (rc) {
c2c357ce
LB		 3367 printk(KERN_ERR "%s: Firmware files not found\n",
3368 wiphy_name(hw->wiphy));
a66098da
LB		 3369 goto err_free_irq;
3370 }
3371
3372 /* Load firmware into hardware */
c2c357ce 3373 rc = mwl8k_load_firmware(hw);
a66098da 3374 if (rc) {
c2c357ce
LB		 3375 printk(KERN_ERR "%s: Cannot start firmware\n",
3376 wiphy_name(hw->wiphy));
a66098da
LB		 3377 goto err_stop_firmware;
3378 }
3379
3380 /* Reclaim memory once firmware is successfully loaded */
3381 mwl8k_release_firmware(priv);
3382
3383 /*
3384 * Temporarily enable interrupts. Initial firmware host
3385 * commands use interrupts and avoids polling. Disable
3386 * interrupts when done.
3387 */
c23b5a69 3388 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3389
3390 /* Get config data, mac addrs etc */
42fba21d
LB		 3391 if (priv->ap_fw) {
3392 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3393 if (!rc)
3394 rc = mwl8k_cmd_set_hw_spec(hw);
3395 } else {
3396 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3397 }
a66098da 3398 if (rc) {
c2c357ce
LB		 3399 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3400 wiphy_name(hw->wiphy));
a66098da
LB		 3401 goto err_stop_firmware;
3402 }
3403
3404 /* Turn radio off */
c46563b7 3405 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3406 if (rc) {
c2c357ce 3407 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3408 goto err_stop_firmware;
3409 }
3410
32060e1b
LB		 3411 /* Clear MAC address */
3412 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3413 if (rc) {
3414 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3415 wiphy_name(hw->wiphy));
3416 goto err_stop_firmware;
3417 }
3418
a66098da 3419 /* Disable interrupts */
a66098da 3420 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3421 free_irq(priv->pdev->irq, hw);
3422
3423 rc = ieee80211_register_hw(hw);
3424 if (rc) {
c2c357ce
LB		 3425 printk(KERN_ERR "%s: Cannot register device\n",
3426 wiphy_name(hw->wiphy));
a66098da
LB		 3427 goto err_stop_firmware;
3428 }
3429
eae74e65 3430 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3431 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3432 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3433 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3434 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3435 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3436
3437 return 0;
3438
3439err_stop_firmware:
3440 mwl8k_hw_reset(priv);
3441 mwl8k_release_firmware(priv);
3442
3443err_free_irq:
a66098da 3444 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3445 free_irq(priv->pdev->irq, hw);
3446
3447err_free_queues:
3448 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3449 mwl8k_txq_deinit(hw, i);
3450 mwl8k_rxq_deinit(hw, 0);
3451
3452err_iounmap:
3453 if (priv->cookie != NULL)
3454 pci_free_consistent(priv->pdev, 4,
3455 priv->cookie, priv->cookie_dma);
3456
3457 if (priv->regs != NULL)
3458 pci_iounmap(pdev, priv->regs);
3459
5b9482dd
LB		 3460 if (priv->sram != NULL)
3461 pci_iounmap(pdev, priv->sram);
3462
a66098da
LB		 3463 pci_set_drvdata(pdev, NULL);
3464 ieee80211_free_hw(hw);
3465
3466err_free_reg:
3467 pci_release_regions(pdev);
3468 pci_disable_device(pdev);
3469
3470 return rc;
3471}
3472
230f7af0 3473static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3474{
3475 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3476}
3477
230f7af0 3478static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3479{
3480 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3481 struct mwl8k_priv *priv;
3482 int i;
3483
3484 if (hw == NULL)
3485 return;
3486 priv = hw->priv;
3487
3488 ieee80211_stop_queues(hw);
3489
60aa569f
LB		 3490 ieee80211_unregister_hw(hw);
3491
a66098da
LB		 3492 /* Remove tx reclaim tasklet */
3493 tasklet_kill(&priv->tx_reclaim_task);
3494
a66098da
LB		 3495 /* Stop hardware */
3496 mwl8k_hw_reset(priv);
3497
3498 /* Return all skbs to mac80211 */
3499 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3500 mwl8k_txq_reclaim(hw, i, 1);
3501
a66098da
LB		 3502 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3503 mwl8k_txq_deinit(hw, i);
3504
3505 mwl8k_rxq_deinit(hw, 0);
3506
c2c357ce 3507 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3508
3509 pci_iounmap(pdev, priv->regs);
5b9482dd 3510 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3511 pci_set_drvdata(pdev, NULL);
3512 ieee80211_free_hw(hw);
3513 pci_release_regions(pdev);
3514 pci_disable_device(pdev);
3515}
3516
3517static struct pci_driver mwl8k_driver = {
3518 .name = MWL8K_NAME,
45a390dd 3519 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3520 .probe = mwl8k_probe,
3521 .remove = __devexit_p(mwl8k_remove),
3522 .shutdown = __devexit_p(mwl8k_shutdown),
3523};
3524
3525static int __init mwl8k_init(void)
3526{
3527 return pci_register_driver(&mwl8k_driver);
3528}
3529
3530static void __exit mwl8k_exit(void)
3531{
3532 pci_unregister_driver(&mwl8k_driver);
3533}
3534
3535module_init(mwl8k_init);
3536module_exit(mwl8k_exit);
c2c357ce
LB		 3537
3538MODULE_DESCRIPTION(MWL8K_DESC);
3539MODULE_VERSION(MWL8K_VERSION);
3540MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3541MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)