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mwl8k: add various missing GET_HW_SPEC endian conversions
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da
LB		 1/*
2 * drivers/net/wireless/mwl8k.c driver for Marvell TOPDOG 802.11 Wireless cards
3 *
4 * Copyright (C) 2008 Marvell Semiconductor Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/completion.h>
19#include <linux/etherdevice.h>
20#include <net/mac80211.h>
21#include <linux/moduleparam.h>
22#include <linux/firmware.h>
23#include <linux/workqueue.h>
24
25#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
26#define MWL8K_NAME KBUILD_MODNAME
27#define MWL8K_VERSION "0.9.1"
28
29MODULE_DESCRIPTION(MWL8K_DESC);
30MODULE_VERSION(MWL8K_VERSION);
31MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
32MODULE_LICENSE("GPL");
33
34static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
35 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
36 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
37 { }
38};
39MODULE_DEVICE_TABLE(pci, mwl8k_table);
40
41#define IEEE80211_ADDR_LEN ETH_ALEN
42
43/* Register definitions */
44#define MWL8K_HIU_GEN_PTR 0x00000c10
45#define MWL8K_MODE_STA 0x0000005a
46#define MWL8K_MODE_AP 0x000000a5
47#define MWL8K_HIU_INT_CODE 0x00000c14
48#define MWL8K_FWSTA_READY 0xf0f1f2f4
49#define MWL8K_FWAP_READY 0xf1f2f4a5
50#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
51#define MWL8K_HIU_SCRATCH 0x00000c40
52
53/* Host->device communications */
54#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
55#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
56#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
57#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
58#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
59#define MWL8K_H2A_INT_DUMMY (1 << 20)
60#define MWL8K_H2A_INT_RESET (1 << 15)
61#define MWL8K_H2A_INT_PS (1 << 2)
62#define MWL8K_H2A_INT_DOORBELL (1 << 1)
63#define MWL8K_H2A_INT_PPA_READY (1 << 0)
64
65/* Device->host communications */
66#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
67#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
68#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
69#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
70#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
71#define MWL8K_A2H_INT_DUMMY (1 << 20)
72#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
73#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
74#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
75#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
76#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
77#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
78#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
79#define MWL8K_A2H_INT_RX_READY (1 << 1)
80#define MWL8K_A2H_INT_TX_DONE (1 << 0)
81
82#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
83 MWL8K_A2H_INT_CHNL_SWITCHED | \
84 MWL8K_A2H_INT_QUEUE_EMPTY | \
85 MWL8K_A2H_INT_RADAR_DETECT | \
86 MWL8K_A2H_INT_RADIO_ON | \
87 MWL8K_A2H_INT_RADIO_OFF | \
88 MWL8K_A2H_INT_MAC_EVENT | \
89 MWL8K_A2H_INT_OPC_DONE | \
90 MWL8K_A2H_INT_RX_READY | \
91 MWL8K_A2H_INT_TX_DONE)
92
93/* WME stream classes */
94#define WME_AC_BE 0 /* best effort */
95#define WME_AC_BK 1 /* background */
96#define WME_AC_VI 2 /* video */
97#define WME_AC_VO 3 /* voice */
98
99#define MWL8K_RX_QUEUES 1
100#define MWL8K_TX_QUEUES 4
101
102struct mwl8k_rx_queue {
103 int rx_desc_count;
104
105 /* hw receives here */
106 int rx_head;
107
108 /* refill descs here */
109 int rx_tail;
110
111 struct mwl8k_rx_desc *rx_desc_area;
112 dma_addr_t rx_desc_dma;
113 struct sk_buff **rx_skb;
114};
115
116struct mwl8k_skb {
117 /*
118 * The DMA engine requires a modification to the payload.
119 * If the skbuff is shared/cloned, it needs to be unshared.
120 * This method is used to ensure the stack always gets back
121 * the skbuff it sent for transmission.
122 */
123 struct sk_buff *clone;
124 struct sk_buff *skb;
125};
126
127struct mwl8k_tx_queue {
128 /* hw transmits here */
129 int tx_head;
130
131 /* sw appends here */
132 int tx_tail;
133
134 struct ieee80211_tx_queue_stats tx_stats;
135 struct mwl8k_tx_desc *tx_desc_area;
136 dma_addr_t tx_desc_dma;
137 struct mwl8k_skb *tx_skb;
138};
139
140/* Pointers to the firmware data and meta information about it. */
141struct mwl8k_firmware {
142 /* Microcode */
143 struct firmware *ucode;
144
145 /* Boot helper code */
146 struct firmware *helper;
147};
148
149struct mwl8k_priv {
150 void __iomem *regs;
151 struct ieee80211_hw *hw;
152
153 struct pci_dev *pdev;
154 u8 name[16];
155 /* firmware access lock */
156 spinlock_t fw_lock;
157
158 /* firmware files and meta data */
159 struct mwl8k_firmware fw;
160 u32 part_num;
161
162 /* lock held over TX and TX reap */
163 spinlock_t tx_lock;
164 u32 int_mask;
165
166 struct ieee80211_vif *vif;
167 struct list_head vif_list;
168
169 struct ieee80211_channel *current_channel;
170
171 /* power management status cookie from firmware */
172 u32 *cookie;
173 dma_addr_t cookie_dma;
174
175 u16 num_mcaddrs;
176 u16 region_code;
177 u8 hw_rev;
178 __le32 fw_rev;
179 u32 wep_enabled;
180
181 /*
182 * Running count of TX packets in flight, to avoid
183 * iterating over the transmit rings each time.
184 */
185 int pending_tx_pkts;
186
187 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
188 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
189
190 /* PHY parameters */
191 struct ieee80211_supported_band band;
192 struct ieee80211_channel channels[14];
193 struct ieee80211_rate rates[12];
194
195 /* RF preamble: Short, Long or Auto */
196 u8 radio_preamble;
197 u8 radio_state;
198
199 /* WMM MODE 1 for enabled; 0 for disabled */
200 bool wmm_mode;
201
202 /* Set if PHY config is in progress */
203 bool inconfig;
204
205 /* XXX need to convert this to handle multiple interfaces */
206 bool capture_beacon;
207 u8 capture_bssid[IEEE80211_ADDR_LEN];
208 struct sk_buff *beacon_skb;
209
210 /*
211 * This FJ worker has to be global as it is scheduled from the
212 * RX handler. At this point we don't know which interface it
213 * belongs to until the list of bssids waiting to complete join
214 * is checked.
215 */
216 struct work_struct finalize_join_worker;
217
218 /* Tasklet to reclaim TX descriptors and buffers after tx */
219 struct tasklet_struct tx_reclaim_task;
220
221 /* Work thread to serialize configuration requests */
222 struct workqueue_struct *config_wq;
223 struct completion *hostcmd_wait;
224 struct completion *tx_wait;
225};
226
227/* Per interface specific private data */
228struct mwl8k_vif {
229 struct list_head node;
230
231 /* backpointer to parent config block */
232 struct mwl8k_priv *priv;
233
234 /* BSS config of AP or IBSS from mac80211*/
235 struct ieee80211_bss_conf bss_info;
236
237 /* BSSID of AP or IBSS */
238 u8 bssid[IEEE80211_ADDR_LEN];
239 u8 mac_addr[IEEE80211_ADDR_LEN];
240
241 /*
242 * Subset of supported legacy rates.
243 * Intersection of AP and STA supported rates.
244 */
245 struct ieee80211_rate legacy_rates[12];
246
247 /* number of supported legacy rates */
248 u8 legacy_nrates;
249
250 /* Number of supported MCS rates. Work in progress */
251 u8 mcs_nrates;
252
253 /* Index into station database.Returned by update_sta_db call */
254 u8 peer_id;
255
256 /* Non AMPDU sequence number assigned by driver */
257 u16 seqno;
258
259 /* Note:There is no channel info,
260 * refer to the master channel info in priv
261 */
262};
263
264#define MWL8K_VIF(_vif) (struct mwl8k_vif *)(&((_vif)->drv_priv))
265
266static const struct ieee80211_channel mwl8k_channels[] = {
267 { .center_freq = 2412, .hw_value = 1, },
268 { .center_freq = 2417, .hw_value = 2, },
269 { .center_freq = 2422, .hw_value = 3, },
270 { .center_freq = 2427, .hw_value = 4, },
271 { .center_freq = 2432, .hw_value = 5, },
272 { .center_freq = 2437, .hw_value = 6, },
273 { .center_freq = 2442, .hw_value = 7, },
274 { .center_freq = 2447, .hw_value = 8, },
275 { .center_freq = 2452, .hw_value = 9, },
276 { .center_freq = 2457, .hw_value = 10, },
277 { .center_freq = 2462, .hw_value = 11, },
278};
279
280static const struct ieee80211_rate mwl8k_rates[] = {
281 { .bitrate = 10, .hw_value = 2, },
282 { .bitrate = 20, .hw_value = 4, },
283 { .bitrate = 55, .hw_value = 11, },
284 { .bitrate = 60, .hw_value = 12, },
285 { .bitrate = 90, .hw_value = 18, },
286 { .bitrate = 110, .hw_value = 22, },
287 { .bitrate = 120, .hw_value = 24, },
288 { .bitrate = 180, .hw_value = 36, },
289 { .bitrate = 240, .hw_value = 48, },
290 { .bitrate = 360, .hw_value = 72, },
291 { .bitrate = 480, .hw_value = 96, },
292 { .bitrate = 540, .hw_value = 108, },
293};
294
295/* Radio settings */
296#define MWL8K_RADIO_FORCE 0x2
297#define MWL8K_RADIO_ENABLE 0x1
298#define MWL8K_RADIO_DISABLE 0x0
299#define MWL8K_RADIO_AUTO_PREAMBLE 0x0005
300#define MWL8K_RADIO_SHORT_PREAMBLE 0x0003
301#define MWL8K_RADIO_LONG_PREAMBLE 0x0001
302
303/* WMM */
304#define MWL8K_WMM_ENABLE 1
305#define MWL8K_WMM_DISABLE 0
306
307#define MWL8K_RADIO_DEFAULT_PREAMBLE MWL8K_RADIO_LONG_PREAMBLE
308
309/* Slot time */
310
311/* Short Slot: 9us slot time */
312#define MWL8K_SHORT_SLOTTIME 1
313
314/* Long slot: 20us slot time */
315#define MWL8K_LONG_SLOTTIME 0
316
317/* Set or get info from Firmware */
318#define MWL8K_CMD_SET 0x0001
319#define MWL8K_CMD_GET 0x0000
320
321/* Firmware command codes */
322#define MWL8K_CMD_CODE_DNLD 0x0001
323#define MWL8K_CMD_GET_HW_SPEC 0x0003
324#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
325#define MWL8K_CMD_GET_STAT 0x0014
326#define MWL8K_CMD_RADIO_CONTROL 0x001C
327#define MWL8K_CMD_RF_TX_POWER 0x001E
328#define MWL8K_CMD_SET_PRE_SCAN 0x0107
329#define MWL8K_CMD_SET_POST_SCAN 0x0108
330#define MWL8K_CMD_SET_RF_CHANNEL 0x010A
331#define MWL8K_CMD_SET_SLOT 0x0114
332#define MWL8K_CMD_MIMO_CONFIG 0x0125
333#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
334#define MWL8K_CMD_SET_WMM_MODE 0x0123
335#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
336#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
337#define MWL8K_CMD_UPDATE_STADB 0x1123
338#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
339#define MWL8K_CMD_SET_LINKADAPT_MODE 0x0129
340#define MWL8K_CMD_SET_AID 0x010d
341#define MWL8K_CMD_SET_RATE 0x0110
342#define MWL8K_CMD_USE_FIXED_RATE 0x0126
343#define MWL8K_CMD_RTS_THRESHOLD 0x0113
344#define MWL8K_CMD_ENCRYPTION 0x1122
345
346static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
347{
348#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
349 snprintf(buf, bufsize, "%s", #x);\
350 return buf;\
351 } while (0)
352 switch (cmd & (~0x8000)) {
353 MWL8K_CMDNAME(CODE_DNLD);
354 MWL8K_CMDNAME(GET_HW_SPEC);
355 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
356 MWL8K_CMDNAME(GET_STAT);
357 MWL8K_CMDNAME(RADIO_CONTROL);
358 MWL8K_CMDNAME(RF_TX_POWER);
359 MWL8K_CMDNAME(SET_PRE_SCAN);
360 MWL8K_CMDNAME(SET_POST_SCAN);
361 MWL8K_CMDNAME(SET_RF_CHANNEL);
362 MWL8K_CMDNAME(SET_SLOT);
363 MWL8K_CMDNAME(MIMO_CONFIG);
364 MWL8K_CMDNAME(ENABLE_SNIFFER);
365 MWL8K_CMDNAME(SET_WMM_MODE);
366 MWL8K_CMDNAME(SET_EDCA_PARAMS);
367 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
368 MWL8K_CMDNAME(UPDATE_STADB);
369 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
370 MWL8K_CMDNAME(SET_LINKADAPT_MODE);
371 MWL8K_CMDNAME(SET_AID);
372 MWL8K_CMDNAME(SET_RATE);
373 MWL8K_CMDNAME(USE_FIXED_RATE);
374 MWL8K_CMDNAME(RTS_THRESHOLD);
375 MWL8K_CMDNAME(ENCRYPTION);
376 default:
377 snprintf(buf, bufsize, "0x%x", cmd);
378 }
379#undef MWL8K_CMDNAME
380
381 return buf;
382}
383
384/* Hardware and firmware reset */
385static void mwl8k_hw_reset(struct mwl8k_priv *priv)
386{
387 iowrite32(MWL8K_H2A_INT_RESET,
388 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
389 iowrite32(MWL8K_H2A_INT_RESET,
390 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
391 msleep(20);
392}
393
394/* Release fw image */
395static void mwl8k_release_fw(struct firmware **fw)
396{
397 if (*fw == NULL)
398 return;
399 release_firmware(*fw);
400 *fw = NULL;
401}
402
403static void mwl8k_release_firmware(struct mwl8k_priv *priv)
404{
405 mwl8k_release_fw(&priv->fw.ucode);
406 mwl8k_release_fw(&priv->fw.helper);
407}
408
409/* Request fw image */
410static int mwl8k_request_fw(struct mwl8k_priv *priv,
411 const char *fname, struct firmware **fw)
412{
413 /* release current image */
414 if (*fw != NULL)
415 mwl8k_release_fw(fw);
416
417 return request_firmware((const struct firmware **)fw,
418 fname, &priv->pdev->dev);
419}
420
421static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
422{
423 u8 filename[64];
424 int rc;
425
426 priv->part_num = part_num;
427
428 snprintf(filename, sizeof(filename),
429 "mwl8k/helper_%u.fw", priv->part_num);
430
431 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
432 if (rc) {
433 printk(KERN_ERR
434 "%s Error requesting helper firmware file %s\n",
435 pci_name(priv->pdev), filename);
436 return rc;
437 }
438
439 snprintf(filename, sizeof(filename),
440 "mwl8k/fmimage_%u.fw", priv->part_num);
441
442 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
443 if (rc) {
444 printk(KERN_ERR "%s Error requesting firmware file %s\n",
445 pci_name(priv->pdev), filename);
446 mwl8k_release_fw(&priv->fw.helper);
447 return rc;
448 }
449
450 return 0;
451}
452
453struct mwl8k_cmd_pkt {
454 __le16 code;
455 __le16 length;
456 __le16 seq_num;
457 __le16 result;
458 char payload[0];
459} __attribute__((packed));
460
461/*
462 * Firmware loading.
463 */
464static int
465mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
466{
467 void __iomem *regs = priv->regs;
468 dma_addr_t dma_addr;
469 int rc;
470 int loops;
471
472 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
473 if (pci_dma_mapping_error(priv->pdev, dma_addr))
474 return -ENOMEM;
475
476 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
477 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
478 iowrite32(MWL8K_H2A_INT_DOORBELL,
479 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
480 iowrite32(MWL8K_H2A_INT_DUMMY,
481 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
482
483 rc = -ETIMEDOUT;
484 loops = 1000;
485 do {
486 u32 int_code;
487
488 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
489 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
490 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
491 rc = 0;
492 break;
493 }
494
495 udelay(1);
496 } while (--loops);
497
498 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
499
500 /*
501 * Clear 'command done' interrupt bit.
502 */
503 loops = 1000;
504 do {
505 u32 status;
506
507 status = ioread32(priv->regs +
508 MWL8K_HIU_A2H_INTERRUPT_STATUS);
509 if (status & MWL8K_A2H_INT_OPC_DONE) {
510 iowrite32(~MWL8K_A2H_INT_OPC_DONE,
511 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
512 ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
513 break;
514 }
515
516 udelay(1);
517 } while (--loops);
518
519 return rc;
520}
521
522static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
523 const u8 *data, size_t length)
524{
525 struct mwl8k_cmd_pkt *cmd;
526 int done;
527 int rc = 0;
528
529 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
530 if (cmd == NULL)
531 return -ENOMEM;
532
533 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
534 cmd->seq_num = 0;
535 cmd->result = 0;
536
537 done = 0;
538 while (length) {
539 int block_size = length > 256 ? 256 : length;
540
541 memcpy(cmd->payload, data + done, block_size);
542 cmd->length = cpu_to_le16(block_size);
543
544 rc = mwl8k_send_fw_load_cmd(priv, cmd,
545 sizeof(*cmd) + block_size);
546 if (rc)
547 break;
548
549 done += block_size;
550 length -= block_size;
551 }
552
553 if (!rc) {
554 cmd->length = 0;
555 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
556 }
557
558 kfree(cmd);
559
560 return rc;
561}
562
563static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
564 const u8 *data, size_t length)
565{
566 unsigned char *buffer;
567 int may_continue, rc = 0;
568 u32 done, prev_block_size;
569
570 buffer = kmalloc(1024, GFP_KERNEL);
571 if (buffer == NULL)
572 return -ENOMEM;
573
574 done = 0;
575 prev_block_size = 0;
576 may_continue = 1000;
577 while (may_continue > 0) {
578 u32 block_size;
579
580 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
581 if (block_size & 1) {
582 block_size &= ~1;
583 may_continue--;
584 } else {
585 done += prev_block_size;
586 length -= prev_block_size;
587 }
588
589 if (block_size > 1024 || block_size > length) {
590 rc = -EOVERFLOW;
591 break;
592 }
593
594 if (length == 0) {
595 rc = 0;
596 break;
597 }
598
599 if (block_size == 0) {
600 rc = -EPROTO;
601 may_continue--;
602 udelay(1);
603 continue;
604 }
605
606 prev_block_size = block_size;
607 memcpy(buffer, data + done, block_size);
608
609 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
610 if (rc)
611 break;
612 }
613
614 if (!rc && length != 0)
615 rc = -EREMOTEIO;
616
617 kfree(buffer);
618
619 return rc;
620}
621
622static int mwl8k_load_firmware(struct mwl8k_priv *priv)
623{
624 int loops, rc;
625
626 const u8 *ucode = priv->fw.ucode->data;
627 size_t ucode_len = priv->fw.ucode->size;
628 const u8 *helper = priv->fw.helper->data;
629 size_t helper_len = priv->fw.helper->size;
630
631 if (!memcmp(ucode, "\x01\x00\x00\x00", 4)) {
632 rc = mwl8k_load_fw_image(priv, helper, helper_len);
633 if (rc) {
634 printk(KERN_ERR "%s: unable to load firmware "
635 "helper image\n", pci_name(priv->pdev));
636 return rc;
637 }
638 msleep(1);
639
640 rc = mwl8k_feed_fw_image(priv, ucode, ucode_len);
641 } else {
642 rc = mwl8k_load_fw_image(priv, ucode, ucode_len);
643 }
644
645 if (rc) {
646 printk(KERN_ERR "%s: unable to load firmware data\n",
647 pci_name(priv->pdev));
648 return rc;
649 }
650
651 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
652 msleep(1);
653
654 loops = 200000;
655 do {
656 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
657 == MWL8K_FWSTA_READY)
658 break;
659 udelay(1);
660 } while (--loops);
661
662 return loops ? 0 : -ETIMEDOUT;
663}
664
665
666/*
667 * Defines shared between transmission and reception.
668 */
669/* HT control fields for firmware */
670struct ewc_ht_info {
671 __le16 control1;
672 __le16 control2;
673 __le16 control3;
674} __attribute__((packed));
675
676/* Firmware Station database operations */
677#define MWL8K_STA_DB_ADD_ENTRY 0
678#define MWL8K_STA_DB_MODIFY_ENTRY 1
679#define MWL8K_STA_DB_DEL_ENTRY 2
680#define MWL8K_STA_DB_FLUSH 3
681
682/* Peer Entry flags - used to define the type of the peer node */
683#define MWL8K_PEER_TYPE_ACCESSPOINT 2
684#define MWL8K_PEER_TYPE_ADHOC_STATION 4
685
686#define MWL8K_IEEE_LEGACY_DATA_RATES 12
687#define MWL8K_MCS_BITMAP_SIZE 16
688#define pad_size 16
689
690struct peer_capability_info {
691 /* Peer type - AP vs. STA. */
692 __u8 peer_type;
693
694 /* Basic 802.11 capabilities from assoc resp. */
695 __le16 basic_caps;
696
697 /* Set if peer supports 802.11n high throughput (HT). */
698 __u8 ht_support;
699
700 /* Valid if HT is supported. */
701 __le16 ht_caps;
702 __u8 extended_ht_caps;
703 struct ewc_ht_info ewc_info;
704
705 /* Legacy rate table. Intersection of our rates and peer rates. */
706 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
707
708 /* HT rate table. Intersection of our rates and peer rates. */
709 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
710 __u8 pad[pad_size];
711
712 /* If set, interoperability mode, no proprietary extensions. */
713 __u8 interop;
714 __u8 pad2;
715 __u8 station_id;
716 __le16 amsdu_enabled;
717} __attribute__((packed));
718
719/* Inline functions to manipulate QoS field in data descriptor. */
720static inline u16 mwl8k_qos_setbit_tid(u16 qos, u8 tid)
721{
722 u16 val_mask = 0x000f;
723 u16 qos_mask = ~val_mask;
724
725 /* TID bits 0-3 */
726 return (qos & qos_mask) | (tid & val_mask);
727}
728
729static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
730{
731 u16 val_mask = 1 << 4;
732
733 /* End of Service Period Bit 4 */
734 return qos | val_mask;
735}
736
737static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
738{
739 u16 val_mask = 0x3;
740 u8 shift = 5;
741 u16 qos_mask = ~(val_mask << shift);
742
743 /* Ack Policy Bit 5-6 */
744 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
745}
746
747static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
748{
749 u16 val_mask = 1 << 7;
750
751 /* AMSDU present Bit 7 */
752 return qos | val_mask;
753}
754
755static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
756{
757 u16 val_mask = 0xff;
758 u8 shift = 8;
759 u16 qos_mask = ~(val_mask << shift);
760
761 /* Queue Length Bits 8-15 */
762 return (qos & qos_mask) | ((len & val_mask) << shift);
763}
764
765/* DMA header used by firmware and hardware. */
766struct mwl8k_dma_data {
767 __le16 fwlen;
768 struct ieee80211_hdr wh;
769} __attribute__((packed));
770
771/* Routines to add/remove DMA header from skb. */
772static inline int mwl8k_remove_dma_header(struct sk_buff *skb)
773{
774 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)(skb->data);
775 void *dst, *src = &tr->wh;
776 __le16 fc = tr->wh.frame_control;
777 int hdrlen = ieee80211_hdrlen(fc);
778 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
779
780 dst = (void *)tr + space;
781 if (dst != src) {
782 memmove(dst, src, hdrlen);
783 skb_pull(skb, space);
784 }
785
786 return 0;
787}
788
789static inline struct sk_buff *mwl8k_add_dma_header(struct sk_buff *skb)
790{
791 struct ieee80211_hdr *wh;
792 u32 hdrlen, pktlen;
793 struct mwl8k_dma_data *tr;
794
795 wh = (struct ieee80211_hdr *)skb->data;
796 hdrlen = ieee80211_hdrlen(wh->frame_control);
797 pktlen = skb->len;
798
799 /*
800 * Copy up/down the 802.11 header; the firmware requires
801 * we present a 2-byte payload length followed by a
802 * 4-address header (w/o QoS), followed (optionally) by
803 * any WEP/ExtIV header (but only filled in for CCMP).
804 */
805 if (hdrlen != sizeof(struct mwl8k_dma_data))
806 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
807
808 tr = (struct mwl8k_dma_data *)skb->data;
809 if (wh != &tr->wh)
810 memmove(&tr->wh, wh, hdrlen);
811
812 /* Clear addr4 */
813 memset(tr->wh.addr4, 0, IEEE80211_ADDR_LEN);
814
815 /*
816 * Firmware length is the length of the fully formed "802.11
817 * payload". That is, everything except for the 802.11 header.
818 * This includes all crypto material including the MIC.
819 */
820 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
821
822 return skb;
823}
824
825
826/*
827 * Packet reception.
828 */
829#define MWL8K_RX_CTRL_KEY_INDEX_MASK 0x30
830#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
831#define MWL8K_RX_CTRL_AMPDU 0x01
832
833struct mwl8k_rx_desc {
834 __le16 pkt_len;
835 __u8 link_quality;
836 __u8 noise_level;
837 __le32 pkt_phys_addr;
838 __le32 next_rx_desc_phys_addr;
839 __le16 qos_control;
840 __le16 rate_info;
841 __le32 pad0[4];
842 __u8 rssi;
843 __u8 channel;
844 __le16 pad1;
845 __u8 rx_ctrl;
846 __u8 rx_status;
847 __u8 pad2[2];
848} __attribute__((packed));
849
850#define MWL8K_RX_DESCS 256
851#define MWL8K_RX_MAXSZ 3800
852
853static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
854{
855 struct mwl8k_priv *priv = hw->priv;
856 struct mwl8k_rx_queue *rxq = priv->rxq + index;
857 int size;
858 int i;
859
860 rxq->rx_desc_count = 0;
861 rxq->rx_head = 0;
862 rxq->rx_tail = 0;
863
864 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
865
866 rxq->rx_desc_area =
867 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
868 if (rxq->rx_desc_area == NULL) {
869 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
870 priv->name);
871 return -ENOMEM;
872 }
873 memset(rxq->rx_desc_area, 0, size);
874
875 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
876 sizeof(*rxq->rx_skb), GFP_KERNEL);
877 if (rxq->rx_skb == NULL) {
878 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
879 priv->name);
880 pci_free_consistent(priv->pdev, size,
881 rxq->rx_desc_area, rxq->rx_desc_dma);
882 return -ENOMEM;
883 }
884 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
885
886 for (i = 0; i < MWL8K_RX_DESCS; i++) {
887 struct mwl8k_rx_desc *rx_desc;
888 int nexti;
889
890 rx_desc = rxq->rx_desc_area + i;
891 nexti = (i + 1) % MWL8K_RX_DESCS;
892
893 rx_desc->next_rx_desc_phys_addr =
894 cpu_to_le32(rxq->rx_desc_dma
895 + nexti * sizeof(*rx_desc));
c491bf12 896 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
a66098da
LB		 897 }
898
899 return 0;
900}
901
902static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
903{
904 struct mwl8k_priv *priv = hw->priv;
905 struct mwl8k_rx_queue *rxq = priv->rxq + index;
906 int refilled;
907
908 refilled = 0;
909 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
910 struct sk_buff *skb;
911 int rx;
912
913 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
914 if (skb == NULL)
915 break;
916
917 rxq->rx_desc_count++;
918
919 rx = rxq->rx_tail;
920 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
921
922 rxq->rx_desc_area[rx].pkt_phys_addr =
923 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
924 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
925
926 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
927 rxq->rx_skb[rx] = skb;
928 wmb();
929 rxq->rx_desc_area[rx].rx_ctrl = 0;
930
931 refilled++;
932 }
933
934 return refilled;
935}
936
937/* Must be called only when the card's reception is completely halted */
938static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
939{
940 struct mwl8k_priv *priv = hw->priv;
941 struct mwl8k_rx_queue *rxq = priv->rxq + index;
942 int i;
943
944 for (i = 0; i < MWL8K_RX_DESCS; i++) {
945 if (rxq->rx_skb[i] != NULL) {
946 unsigned long addr;
947
948 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
949 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
950 PCI_DMA_FROMDEVICE);
951 kfree_skb(rxq->rx_skb[i]);
952 rxq->rx_skb[i] = NULL;
953 }
954 }
955
956 kfree(rxq->rx_skb);
957 rxq->rx_skb = NULL;
958
959 pci_free_consistent(priv->pdev,
960 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
961 rxq->rx_desc_area, rxq->rx_desc_dma);
962 rxq->rx_desc_area = NULL;
963}
964
965
966/*
967 * Scan a list of BSSIDs to process for finalize join.
968 * Allows for extension to process multiple BSSIDs.
969 */
970static inline int
971mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
972{
973 return priv->capture_beacon &&
974 ieee80211_is_beacon(wh->frame_control) &&
975 !compare_ether_addr(wh->addr3, priv->capture_bssid);
976}
977
978static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
979 struct sk_buff *skb)
980{
981 priv->capture_beacon = false;
982 memset(priv->capture_bssid, 0, IEEE80211_ADDR_LEN);
983
984 /*
985 * Use GFP_ATOMIC as rxq_process is called from
986 * the primary interrupt handler, memory allocation call
987 * must not sleep.
988 */
989 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
990 if (priv->beacon_skb != NULL)
991 queue_work(priv->config_wq,
992 &priv->finalize_join_worker);
993}
994
995static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
996{
997 struct mwl8k_priv *priv = hw->priv;
998 struct mwl8k_rx_queue *rxq = priv->rxq + index;
999 int processed;
1000
1001 processed = 0;
1002 while (rxq->rx_desc_count && limit--) {
1003 struct mwl8k_rx_desc *rx_desc;
1004 struct sk_buff *skb;
1005 struct ieee80211_rx_status status;
1006 unsigned long addr;
1007 struct ieee80211_hdr *wh;
1008
1009 rx_desc = rxq->rx_desc_area + rxq->rx_head;
1010 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
1011 break;
1012 rmb();
1013
1014 skb = rxq->rx_skb[rxq->rx_head];
d25f9f13
LB		 1015 if (skb == NULL)
1016 break;
a66098da
LB		 1017 rxq->rx_skb[rxq->rx_head] = NULL;
1018
1019 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
1020 rxq->rx_desc_count--;
1021
1022 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
1023 pci_unmap_single(priv->pdev, addr,
1024 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1025
1026 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
1027 if (mwl8k_remove_dma_header(skb)) {
1028 dev_kfree_skb(skb);
1029 continue;
1030 }
1031
1032 wh = (struct ieee80211_hdr *)skb->data;
1033
1034 /*
1035 * Check for pending join operation. save a copy of
1036 * the beacon and schedule a tasklet to send finalize
1037 * join command to the firmware.
1038 */
1039 if (mwl8k_capture_bssid(priv, wh))
1040 mwl8k_save_beacon(priv, skb);
1041
1042 memset(&status, 0, sizeof(status));
1043 status.mactime = 0;
1044 status.signal = -rx_desc->rssi;
1045 status.noise = -rx_desc->noise_level;
1046 status.qual = rx_desc->link_quality;
1047 status.antenna = 1;
1048 status.rate_idx = 1;
1049 status.flag = 0;
1050 status.band = IEEE80211_BAND_2GHZ;
1051 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
1052 ieee80211_rx_irqsafe(hw, skb, &status);
1053
1054 processed++;
1055 }
1056
1057 return processed;
1058}
1059
1060
1061/*
1062 * Packet transmission.
1063 */
1064
1065/* Transmit queue assignment. */
1066enum {
1067 MWL8K_WME_AC_BK = 0, /* background access */
1068 MWL8K_WME_AC_BE = 1, /* best effort access */
1069 MWL8K_WME_AC_VI = 2, /* video access */
1070 MWL8K_WME_AC_VO = 3, /* voice access */
1071};
1072
1073/* Transmit packet ACK policy */
1074#define MWL8K_TXD_ACK_POLICY_NORMAL 0
1075#define MWL8K_TXD_ACK_POLICY_NONE 1
1076#define MWL8K_TXD_ACK_POLICY_NO_EXPLICIT 2
1077#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1078
1079#define GET_TXQ(_ac) (\
1080 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
1081 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
1082 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
1083 MWL8K_WME_AC_BE)
1084
1085#define MWL8K_TXD_STATUS_IDLE 0x00000000
1086#define MWL8K_TXD_STATUS_USED 0x00000001
1087#define MWL8K_TXD_STATUS_OK 0x00000001
1088#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1089#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1090#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1091#define MWL8K_TXD_STATUS_BROADCAST_TX 0x00000010
1092#define MWL8K_TXD_STATUS_FAILED_LINK_ERROR 0x00000020
1093#define MWL8K_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040
1094#define MWL8K_TXD_STATUS_FAILED_AGING 0x00000080
1095#define MWL8K_TXD_STATUS_HOST_CMD 0x40000000
1096#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1097#define MWL8K_TXD_SOFTSTALE 0x80
1098#define MWL8K_TXD_SOFTSTALE_MGMT_RETRY 0x01
1099
1100struct mwl8k_tx_desc {
1101 __le32 status;
1102 __u8 data_rate;
1103 __u8 tx_priority;
1104 __le16 qos_control;
1105 __le32 pkt_phys_addr;
1106 __le16 pkt_len;
1107 __u8 dest_MAC_addr[IEEE80211_ADDR_LEN];
1108 __le32 next_tx_desc_phys_addr;
1109 __le32 reserved;
1110 __le16 rate_info;
1111 __u8 peer_id;
1112 __u8 tx_frag_cnt;
1113} __attribute__((packed));
1114
1115#define MWL8K_TX_DESCS 128
1116
1117static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1118{
1119 struct mwl8k_priv *priv = hw->priv;
1120 struct mwl8k_tx_queue *txq = priv->txq + index;
1121 int size;
1122 int i;
1123
1124 memset(&txq->tx_stats, 0,
1125 sizeof(struct ieee80211_tx_queue_stats));
1126 txq->tx_stats.limit = MWL8K_TX_DESCS;
1127 txq->tx_head = 0;
1128 txq->tx_tail = 0;
1129
1130 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1131
1132 txq->tx_desc_area =
1133 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1134 if (txq->tx_desc_area == NULL) {
1135 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1136 priv->name);
1137 return -ENOMEM;
1138 }
1139 memset(txq->tx_desc_area, 0, size);
1140
1141 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1142 GFP_KERNEL);
1143 if (txq->tx_skb == NULL) {
1144 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1145 priv->name);
1146 pci_free_consistent(priv->pdev, size,
1147 txq->tx_desc_area, txq->tx_desc_dma);
1148 return -ENOMEM;
1149 }
1150 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1151
1152 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1153 struct mwl8k_tx_desc *tx_desc;
1154 int nexti;
1155
1156 tx_desc = txq->tx_desc_area + i;
1157 nexti = (i + 1) % MWL8K_TX_DESCS;
1158
1159 tx_desc->status = 0;
1160 tx_desc->next_tx_desc_phys_addr =
1161 cpu_to_le32(txq->tx_desc_dma +
1162 nexti * sizeof(*tx_desc));
1163 }
1164
1165 return 0;
1166}
1167
1168static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1169{
1170 iowrite32(MWL8K_H2A_INT_PPA_READY,
1171 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1172 iowrite32(MWL8K_H2A_INT_DUMMY,
1173 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1174 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1175}
1176
1177static inline int mwl8k_txq_busy(struct mwl8k_priv *priv)
1178{
1179 return priv->pending_tx_pkts;
1180}
1181
1182struct mwl8k_txq_info {
1183 u32 fw_owned;
1184 u32 drv_owned;
1185 u32 unused;
1186 u32 len;
1187 u32 head;
1188 u32 tail;
1189};
1190
1191static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1192 struct mwl8k_txq_info txinfo[],
1193 u32 num_queues)
1194{
1195 int count, desc, status;
1196 struct mwl8k_tx_queue *txq;
1197 struct mwl8k_tx_desc *tx_desc;
1198 int ndescs = 0;
1199
1200 memset(txinfo, 0, num_queues * sizeof(struct mwl8k_txq_info));
1201 spin_lock_bh(&priv->tx_lock);
1202 for (count = 0; count < num_queues; count++) {
1203 txq = priv->txq + count;
1204 txinfo[count].len = txq->tx_stats.len;
1205 txinfo[count].head = txq->tx_head;
1206 txinfo[count].tail = txq->tx_tail;
1207 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1208 tx_desc = txq->tx_desc_area + desc;
1209 status = le32_to_cpu(tx_desc->status);
1210
1211 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1212 txinfo[count].fw_owned++;
1213 else
1214 txinfo[count].drv_owned++;
1215
1216 if (tx_desc->pkt_len == 0)
1217 txinfo[count].unused++;
1218 }
1219 }
1220 spin_unlock_bh(&priv->tx_lock);
1221
1222 return ndescs;
1223}
1224
1225static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw, u32 delay_ms)
1226{
1227 u32 count = 0;
1228 unsigned long timeout = 0;
1229 struct mwl8k_priv *priv = hw->priv;
1230 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1231
1232 might_sleep();
1233
1234 if (priv->tx_wait != NULL)
1235 printk(KERN_ERR "WARNING Previous TXWaitEmpty instance\n");
1236
1237 spin_lock_bh(&priv->tx_lock);
1238 count = mwl8k_txq_busy(priv);
1239 if (count) {
1240 priv->tx_wait = &cmd_wait;
1241 if (priv->radio_state)
1242 mwl8k_tx_start(priv);
1243 }
1244 spin_unlock_bh(&priv->tx_lock);
1245
1246 if (count) {
1247 struct mwl8k_txq_info txinfo[4];
1248 int index;
1249 int newcount;
1250
1251 timeout = wait_for_completion_timeout(&cmd_wait,
1252 msecs_to_jiffies(delay_ms));
1253 if (timeout)
1254 return 0;
1255
1256 spin_lock_bh(&priv->tx_lock);
1257 priv->tx_wait = NULL;
1258 newcount = mwl8k_txq_busy(priv);
1259 spin_unlock_bh(&priv->tx_lock);
1260
1261 printk(KERN_ERR "%s(%u) TIMEDOUT:%ums Pend:%u-->%u\n",
1262 __func__, __LINE__, delay_ms, count, newcount);
1263
1264 mwl8k_scan_tx_ring(priv, txinfo, 4);
1265 for (index = 0 ; index < 4; index++)
1266 printk(KERN_ERR
1267 "TXQ:%u L:%u H:%u T:%u FW:%u DRV:%u U:%u\n",
1268 index,
1269 txinfo[index].len,
1270 txinfo[index].head,
1271 txinfo[index].tail,
1272 txinfo[index].fw_owned,
1273 txinfo[index].drv_owned,
1274 txinfo[index].unused);
1275 return -ETIMEDOUT;
1276 }
1277
1278 return 0;
1279}
1280
1281#define MWL8K_TXD_OK (MWL8K_TXD_STATUS_OK | \
1282 MWL8K_TXD_STATUS_OK_RETRY | \
1283 MWL8K_TXD_STATUS_OK_MORE_RETRY)
1284#define MWL8K_TXD_SUCCESS(stat) ((stat) & MWL8K_TXD_OK)
1285#define MWL8K_TXD_FAIL_RETRY(stat) \
1286 ((stat) & (MWL8K_TXD_STATUS_FAILED_EXCEED_LIMIT))
1287
1288static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1289{
1290 struct mwl8k_priv *priv = hw->priv;
1291 struct mwl8k_tx_queue *txq = priv->txq + index;
1292 int wake = 0;
1293
1294 while (txq->tx_stats.len > 0) {
1295 int tx;
1296 int rc;
1297 struct mwl8k_tx_desc *tx_desc;
1298 unsigned long addr;
1299 size_t size;
1300 struct sk_buff *skb;
1301 struct ieee80211_tx_info *info;
1302 u32 status;
1303
1304 rc = 0;
1305 tx = txq->tx_head;
1306 tx_desc = txq->tx_desc_area + tx;
1307
1308 status = le32_to_cpu(tx_desc->status);
1309
1310 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1311 if (!force)
1312 break;
1313 tx_desc->status &=
1314 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1315 }
1316
1317 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1318 BUG_ON(txq->tx_stats.len == 0);
1319 txq->tx_stats.len--;
1320 priv->pending_tx_pkts--;
1321
1322 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1323 size = (u32)(le16_to_cpu(tx_desc->pkt_len));
1324 skb = txq->tx_skb[tx].skb;
1325 txq->tx_skb[tx].skb = NULL;
1326
1327 BUG_ON(skb == NULL);
1328 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1329
1330 rc = mwl8k_remove_dma_header(skb);
1331
1332 /* Mark descriptor as unused */
1333 tx_desc->pkt_phys_addr = 0;
1334 tx_desc->pkt_len = 0;
1335
1336 if (txq->tx_skb[tx].clone) {
1337 /* Replace with original skb
1338 * before returning to stack
1339 * as buffer has been cloned
1340 */
1341 dev_kfree_skb(skb);
1342 skb = txq->tx_skb[tx].clone;
1343 txq->tx_skb[tx].clone = NULL;
1344 }
1345
1346 if (rc) {
1347 /* Something has gone wrong here.
1348 * Failed to remove DMA header.
1349 * Print error message and drop packet.
1350 */
1351 printk(KERN_ERR "%s: Error removing DMA header from "
1352 "tx skb 0x%p.\n", priv->name, skb);
1353
1354 dev_kfree_skb(skb);
1355 continue;
1356 }
1357
1358 info = IEEE80211_SKB_CB(skb);
1359 ieee80211_tx_info_clear_status(info);
1360
1361 /* Convert firmware status stuff into tx_status */
1362 if (MWL8K_TXD_SUCCESS(status)) {
1363 /* Transmit OK */
1364 info->flags |= IEEE80211_TX_STAT_ACK;
1365 }
1366
1367 ieee80211_tx_status_irqsafe(hw, skb);
1368
1369 wake = !priv->inconfig && priv->radio_state;
1370 }
1371
1372 if (wake)
1373 ieee80211_wake_queue(hw, index);
1374}
1375
1376/* must be called only when the card's transmit is completely halted */
1377static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1378{
1379 struct mwl8k_priv *priv = hw->priv;
1380 struct mwl8k_tx_queue *txq = priv->txq + index;
1381
1382 mwl8k_txq_reclaim(hw, index, 1);
1383
1384 kfree(txq->tx_skb);
1385 txq->tx_skb = NULL;
1386
1387 pci_free_consistent(priv->pdev,
1388 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1389 txq->tx_desc_area, txq->tx_desc_dma);
1390 txq->tx_desc_area = NULL;
1391}
1392
1393static int
1394mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1395{
1396 struct mwl8k_priv *priv = hw->priv;
1397 struct ieee80211_tx_info *tx_info;
1398 struct ieee80211_hdr *wh;
1399 struct mwl8k_tx_queue *txq;
1400 struct mwl8k_tx_desc *tx;
1401 struct mwl8k_dma_data *tr;
1402 struct mwl8k_vif *mwl8k_vif;
1403 struct sk_buff *org_skb = skb;
1404 dma_addr_t dma;
1405 u16 qos = 0;
1406 bool qosframe = false, ampduframe = false;
1407 bool mcframe = false, eapolframe = false;
1408 bool amsduframe = false;
1409 __le16 fc;
1410
1411 txq = priv->txq + index;
1412 tx = txq->tx_desc_area + txq->tx_tail;
1413
1414 BUG_ON(txq->tx_skb[txq->tx_tail].skb != NULL);
1415
1416 /*
1417 * Append HW DMA header to start of packet. Drop packet if
1418 * there is not enough space or a failure to unshare/unclone
1419 * the skb.
1420 */
1421 skb = mwl8k_add_dma_header(skb);
1422
1423 if (skb == NULL) {
1424 printk(KERN_DEBUG "%s: failed to prepend HW DMA "
1425 "header, dropping TX frame.\n", priv->name);
1426 dev_kfree_skb(org_skb);
1427 return NETDEV_TX_OK;
1428 }
1429
1430 tx_info = IEEE80211_SKB_CB(skb);
1431 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1432 tr = (struct mwl8k_dma_data *)skb->data;
1433 wh = &tr->wh;
1434 fc = wh->frame_control;
1435 qosframe = ieee80211_is_data_qos(fc);
1436 mcframe = is_multicast_ether_addr(wh->addr1);
1437 ampduframe = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1438
1439 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1440 u16 seqno = mwl8k_vif->seqno;
1441 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1442 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1443 mwl8k_vif->seqno = seqno++ % 4096;
1444 }
1445
1446 if (qosframe)
1447 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1448
1449 dma = pci_map_single(priv->pdev, skb->data,
1450 skb->len, PCI_DMA_TODEVICE);
1451
1452 if (pci_dma_mapping_error(priv->pdev, dma)) {
1453 printk(KERN_DEBUG "%s: failed to dma map skb, "
1454 "dropping TX frame.\n", priv->name);
1455
1456 if (org_skb != NULL)
1457 dev_kfree_skb(org_skb);
1458 if (skb != NULL)
1459 dev_kfree_skb(skb);
1460 return NETDEV_TX_OK;
1461 }
1462
1463 /* Set desc header, cpu bit order. */
1464 tx->status = 0;
1465 tx->data_rate = 0;
1466 tx->tx_priority = index;
1467 tx->qos_control = 0;
1468 tx->rate_info = 0;
1469 tx->peer_id = mwl8k_vif->peer_id;
1470
1471 amsduframe = !!(qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT);
1472
1473 /* Setup firmware control bit fields for each frame type. */
1474 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
1475 tx->data_rate = 0;
1476 qos = mwl8k_qos_setbit_eosp(qos);
1477 /* Set Queue size to unspecified */
1478 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1479 } else if (ieee80211_is_data(fc)) {
1480 tx->data_rate = 1;
1481 if (mcframe)
1482 tx->status |= MWL8K_TXD_STATUS_MULTICAST_TX;
1483
1484 /*
1485 * Tell firmware to not send EAPOL pkts in an
1486 * aggregate. Verify against mac80211 tx path. If
1487 * stack turns off AMPDU for an EAPOL frame this
1488 * check will be removed.
1489 */
1490 if (eapolframe) {
1491 qos = mwl8k_qos_setbit_ack(qos,
1492 MWL8K_TXD_ACK_POLICY_NORMAL);
1493 } else {
1494 /* Send pkt in an aggregate if AMPDU frame. */
1495 if (ampduframe)
1496 qos = mwl8k_qos_setbit_ack(qos,
1497 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1498 else
1499 qos = mwl8k_qos_setbit_ack(qos,
1500 MWL8K_TXD_ACK_POLICY_NORMAL);
1501
1502 if (amsduframe)
1503 qos = mwl8k_qos_setbit_amsdu(qos);
1504 }
1505 }
1506
1507 /* Convert to little endian */
1508 tx->qos_control = cpu_to_le16(qos);
1509 tx->status = cpu_to_le32(tx->status);
1510 tx->pkt_phys_addr = cpu_to_le32(dma);
1511 tx->pkt_len = cpu_to_le16(skb->len);
1512
1513 txq->tx_skb[txq->tx_tail].skb = skb;
1514 txq->tx_skb[txq->tx_tail].clone =
1515 skb == org_skb ? NULL : org_skb;
1516
1517 spin_lock_bh(&priv->tx_lock);
1518
1519 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_OK |
1520 MWL8K_TXD_STATUS_FW_OWNED);
1521 wmb();
1522 txq->tx_stats.len++;
1523 priv->pending_tx_pkts++;
1524 txq->tx_stats.count++;
1525 txq->tx_tail++;
1526
1527 if (txq->tx_tail == MWL8K_TX_DESCS)
1528 txq->tx_tail = 0;
1529 if (txq->tx_head == txq->tx_tail)
1530 ieee80211_stop_queue(hw, index);
1531
1532 if (priv->inconfig) {
1533 /*
1534 * Silently queue packet when we are in the middle of
1535 * a config cycle. Notify firmware only if we are
1536 * waiting for TXQs to empty. If a packet is sent
1537 * before .config() is complete, perhaps it is better
1538 * to drop the packet, as the channel is being changed
1539 * and the packet will end up on the wrong channel.
1540 */
1541 printk(KERN_ERR "%s(): WARNING TX activity while "
1542 "in config\n", __func__);
1543
1544 if (priv->tx_wait != NULL)
1545 mwl8k_tx_start(priv);
1546 } else
1547 mwl8k_tx_start(priv);
1548
1549 spin_unlock_bh(&priv->tx_lock);
1550
1551 return NETDEV_TX_OK;
1552}
1553
1554
1555/*
1556 * Command processing.
1557 */
1558
1559/* Timeout firmware commands after 2000ms */
1560#define MWL8K_CMD_TIMEOUT_MS 2000
1561
1562static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1563{
1564 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1565 struct mwl8k_priv *priv = hw->priv;
1566 void __iomem *regs = priv->regs;
1567 dma_addr_t dma_addr;
1568 unsigned int dma_size;
1569 int rc;
1570 u16 __iomem *result;
1571 unsigned long timeout = 0;
1572 u8 buf[32];
1573
1574 cmd->result = 0xFFFF;
1575 dma_size = le16_to_cpu(cmd->length);
1576 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1577 PCI_DMA_BIDIRECTIONAL);
1578 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1579 return -ENOMEM;
1580
1581 if (priv->hostcmd_wait != NULL)
1582 printk(KERN_ERR "WARNING host command in progress\n");
1583
1584 spin_lock_irq(&priv->fw_lock);
1585 priv->hostcmd_wait = &cmd_wait;
1586 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1587 iowrite32(MWL8K_H2A_INT_DOORBELL,
1588 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1589 iowrite32(MWL8K_H2A_INT_DUMMY,
1590 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1591 spin_unlock_irq(&priv->fw_lock);
1592
1593 timeout = wait_for_completion_timeout(&cmd_wait,
1594 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1595
1596 result = &cmd->result;
1597 if (!timeout) {
1598 spin_lock_irq(&priv->fw_lock);
1599 priv->hostcmd_wait = NULL;
1600 spin_unlock_irq(&priv->fw_lock);
1601 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1602 priv->name,
1603 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1604 MWL8K_CMD_TIMEOUT_MS);
1605 rc = -ETIMEDOUT;
1606 } else {
1607 rc = *result ? -EINVAL : 0;
1608 if (rc)
1609 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1610 priv->name,
1611 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1612 *result);
1613 }
1614
1615 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1616 PCI_DMA_BIDIRECTIONAL);
1617 return rc;
1618}
1619
1620/*
1621 * GET_HW_SPEC.
1622 */
1623struct mwl8k_cmd_get_hw_spec {
1624 struct mwl8k_cmd_pkt header;
1625 __u8 hw_rev;
1626 __u8 host_interface;
1627 __le16 num_mcaddrs;
1628 __u8 perm_addr[IEEE80211_ADDR_LEN];
1629 __le16 region_code;
1630 __le32 fw_rev;
1631 __le32 ps_cookie;
1632 __le32 caps;
1633 __u8 mcs_bitmap[16];
1634 __le32 rx_queue_ptr;
1635 __le32 num_tx_queues;
1636 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1637 __le32 caps2;
1638 __le32 num_tx_desc_per_queue;
1639 __le32 total_rx_desc;
1640} __attribute__((packed));
1641
1642static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1643{
1644 struct mwl8k_priv *priv = hw->priv;
1645 struct mwl8k_cmd_get_hw_spec *cmd;
1646 int rc;
1647 int i;
1648
1649 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1650 if (cmd == NULL)
1651 return -ENOMEM;
1652
1653 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1654 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1655
1656 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1657 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1658 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
4ff6432e 1659 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da
LB		 1660 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1661 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
4ff6432e
LB		 1662 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1663 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1664
1665 rc = mwl8k_post_cmd(hw, &cmd->header);
1666
1667 if (!rc) {
1668 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1669 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1670 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da
LB		 1671 priv->hw_rev = cmd->hw_rev;
1672 priv->region_code = le16_to_cpu(cmd->region_code);
1673 }
1674
1675 kfree(cmd);
1676 return rc;
1677}
1678
1679/*
1680 * CMD_MAC_MULTICAST_ADR.
1681 */
1682struct mwl8k_cmd_mac_multicast_adr {
1683 struct mwl8k_cmd_pkt header;
1684 __le16 action;
1685 __le16 numaddr;
1686 __u8 addr[1][IEEE80211_ADDR_LEN];
1687};
1688
1689#define MWL8K_ENABLE_RX_MULTICAST 0x000F
1690static int mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1691 int mc_count,
1692 struct dev_addr_list *mclist)
1693{
1694 struct mwl8k_cmd_mac_multicast_adr *cmd;
1695 int index = 0;
1696 int rc;
1697 int size = sizeof(*cmd) + ((mc_count - 1) * IEEE80211_ADDR_LEN);
1698 cmd = kzalloc(size, GFP_KERNEL);
1699 if (cmd == NULL)
1700 return -ENOMEM;
1701
1702 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1703 cmd->header.length = cpu_to_le16(size);
1704 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1705 cmd->numaddr = cpu_to_le16(mc_count);
1706 while ((index < mc_count) && mclist) {
1707 if (mclist->da_addrlen != IEEE80211_ADDR_LEN) {
1708 rc = -EINVAL;
1709 goto mwl8k_cmd_mac_multicast_adr_exit;
1710 }
1711 memcpy(cmd->addr[index], mclist->da_addr, IEEE80211_ADDR_LEN);
1712 index++;
1713 mclist = mclist->next;
1714 }
1715
1716 rc = mwl8k_post_cmd(hw, &cmd->header);
1717
1718mwl8k_cmd_mac_multicast_adr_exit:
1719 kfree(cmd);
1720 return rc;
1721}
1722
1723/*
1724 * CMD_802_11_GET_STAT.
1725 */
1726struct mwl8k_cmd_802_11_get_stat {
1727 struct mwl8k_cmd_pkt header;
1728 __le16 action;
1729 __le32 stats[64];
1730} __attribute__((packed));
1731
1732#define MWL8K_STAT_ACK_FAILURE 9
1733#define MWL8K_STAT_RTS_FAILURE 12
1734#define MWL8K_STAT_FCS_ERROR 24
1735#define MWL8K_STAT_RTS_SUCCESS 11
1736
1737static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1738 struct ieee80211_low_level_stats *stats)
1739{
1740 struct mwl8k_cmd_802_11_get_stat *cmd;
1741 int rc;
1742
1743 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1744 if (cmd == NULL)
1745 return -ENOMEM;
1746
1747 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1748 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1749 cmd->action = cpu_to_le16(MWL8K_CMD_GET);
1750
1751 rc = mwl8k_post_cmd(hw, &cmd->header);
1752 if (!rc) {
1753 stats->dot11ACKFailureCount =
1754 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1755 stats->dot11RTSFailureCount =
1756 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1757 stats->dot11FCSErrorCount =
1758 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1759 stats->dot11RTSSuccessCount =
1760 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1761 }
1762 kfree(cmd);
1763
1764 return rc;
1765}
1766
1767/*
1768 * CMD_802_11_RADIO_CONTROL.
1769 */
1770struct mwl8k_cmd_802_11_radio_control {
1771 struct mwl8k_cmd_pkt header;
1772 __le16 action;
1773 __le16 control;
1774 __le16 radio_on;
1775} __attribute__((packed));
1776
1777static int mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, int enable)
1778{
1779 struct mwl8k_priv *priv = hw->priv;
1780 struct mwl8k_cmd_802_11_radio_control *cmd;
1781 int rc;
1782
1783 if (((enable & MWL8K_RADIO_ENABLE) == priv->radio_state) &&
1784 !(enable & MWL8K_RADIO_FORCE))
1785 return 0;
1786
1787 enable &= MWL8K_RADIO_ENABLE;
1788
1789 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1790 if (cmd == NULL)
1791 return -ENOMEM;
1792
1793 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1794 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1795 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1796 cmd->control = cpu_to_le16(priv->radio_preamble);
1797 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1798
1799 rc = mwl8k_post_cmd(hw, &cmd->header);
1800 kfree(cmd);
1801
1802 if (!rc)
1803 priv->radio_state = enable;
1804
1805 return rc;
1806}
1807
1808static int
1809mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1810{
1811 struct mwl8k_priv *priv;
1812
1813 if (hw == NULL || hw->priv == NULL)
1814 return -EINVAL;
1815 priv = hw->priv;
1816
1817 priv->radio_preamble = (short_preamble ?
1818 MWL8K_RADIO_SHORT_PREAMBLE :
1819 MWL8K_RADIO_LONG_PREAMBLE);
1820
1821 return mwl8k_cmd_802_11_radio_control(hw,
1822 MWL8K_RADIO_ENABLE | MWL8K_RADIO_FORCE);
1823}
1824
1825/*
1826 * CMD_802_11_RF_TX_POWER.
1827 */
1828#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1829
1830struct mwl8k_cmd_802_11_rf_tx_power {
1831 struct mwl8k_cmd_pkt header;
1832 __le16 action;
1833 __le16 support_level;
1834 __le16 current_level;
1835 __le16 reserved;
1836 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1837} __attribute__((packed));
1838
1839static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1840{
1841 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1842 int rc;
1843
1844 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1845 if (cmd == NULL)
1846 return -ENOMEM;
1847
1848 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1849 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1850 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1851 cmd->support_level = cpu_to_le16(dBm);
1852
1853 rc = mwl8k_post_cmd(hw, &cmd->header);
1854 kfree(cmd);
1855
1856 return rc;
1857}
1858
1859/*
1860 * CMD_SET_PRE_SCAN.
1861 */
1862struct mwl8k_cmd_set_pre_scan {
1863 struct mwl8k_cmd_pkt header;
1864} __attribute__((packed));
1865
1866static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1867{
1868 struct mwl8k_cmd_set_pre_scan *cmd;
1869 int rc;
1870
1871 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1872 if (cmd == NULL)
1873 return -ENOMEM;
1874
1875 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1876 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1877
1878 rc = mwl8k_post_cmd(hw, &cmd->header);
1879 kfree(cmd);
1880
1881 return rc;
1882}
1883
1884/*
1885 * CMD_SET_POST_SCAN.
1886 */
1887struct mwl8k_cmd_set_post_scan {
1888 struct mwl8k_cmd_pkt header;
1889 __le32 isibss;
1890 __u8 bssid[IEEE80211_ADDR_LEN];
1891} __attribute__((packed));
1892
1893static int
1894mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 mac[IEEE80211_ADDR_LEN])
1895{
1896 struct mwl8k_cmd_set_post_scan *cmd;
1897 int rc;
1898
1899 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1900 if (cmd == NULL)
1901 return -ENOMEM;
1902
1903 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1904 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1905 cmd->isibss = 0;
1906 memcpy(cmd->bssid, mac, IEEE80211_ADDR_LEN);
1907
1908 rc = mwl8k_post_cmd(hw, &cmd->header);
1909 kfree(cmd);
1910
1911 return rc;
1912}
1913
1914/*
1915 * CMD_SET_RF_CHANNEL.
1916 */
1917struct mwl8k_cmd_set_rf_channel {
1918 struct mwl8k_cmd_pkt header;
1919 __le16 action;
1920 __u8 current_channel;
1921 __le32 channel_flags;
1922} __attribute__((packed));
1923
1924static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1925 struct ieee80211_channel *channel)
1926{
1927 struct mwl8k_cmd_set_rf_channel *cmd;
1928 int rc;
1929
1930 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1931 if (cmd == NULL)
1932 return -ENOMEM;
1933
1934 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1935 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1936 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1937 cmd->current_channel = channel->hw_value;
1938 if (channel->band == IEEE80211_BAND_2GHZ)
1939 cmd->channel_flags = cpu_to_le32(0x00000081);
1940 else
1941 cmd->channel_flags = cpu_to_le32(0x00000000);
1942
1943 rc = mwl8k_post_cmd(hw, &cmd->header);
1944 kfree(cmd);
1945
1946 return rc;
1947}
1948
1949/*
1950 * CMD_SET_SLOT.
1951 */
1952struct mwl8k_cmd_set_slot {
1953 struct mwl8k_cmd_pkt header;
1954 __le16 action;
1955 __u8 short_slot;
1956} __attribute__((packed));
1957
1958static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, int slot_time)
1959{
1960 struct mwl8k_cmd_set_slot *cmd;
1961 int rc;
1962
1963 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1964 if (cmd == NULL)
1965 return -ENOMEM;
1966
1967 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1968 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1969 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1970 cmd->short_slot = slot_time == MWL8K_SHORT_SLOTTIME ? 1 : 0;
1971
1972 rc = mwl8k_post_cmd(hw, &cmd->header);
1973 kfree(cmd);
1974
1975 return rc;
1976}
1977
1978/*
1979 * CMD_MIMO_CONFIG.
1980 */
1981struct mwl8k_cmd_mimo_config {
1982 struct mwl8k_cmd_pkt header;
1983 __le32 action;
1984 __u8 rx_antenna_map;
1985 __u8 tx_antenna_map;
1986} __attribute__((packed));
1987
1988static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1989{
1990 struct mwl8k_cmd_mimo_config *cmd;
1991 int rc;
1992
1993 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1994 if (cmd == NULL)
1995 return -ENOMEM;
1996
1997 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1998 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1999 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2000 cmd->rx_antenna_map = rx;
2001 cmd->tx_antenna_map = tx;
2002
2003 rc = mwl8k_post_cmd(hw, &cmd->header);
2004 kfree(cmd);
2005
2006 return rc;
2007}
2008
2009/*
2010 * CMD_ENABLE_SNIFFER.
2011 */
2012struct mwl8k_cmd_enable_sniffer {
2013 struct mwl8k_cmd_pkt header;
2014 __le32 action;
2015} __attribute__((packed));
2016
2017static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2018{
2019 struct mwl8k_cmd_enable_sniffer *cmd;
2020 int rc;
2021
2022 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2023 if (cmd == NULL)
2024 return -ENOMEM;
2025
2026 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2027 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2028 cmd->action = enable ? cpu_to_le32((u32)MWL8K_CMD_SET) : 0;
2029
2030 rc = mwl8k_post_cmd(hw, &cmd->header);
2031 kfree(cmd);
2032
2033 return rc;
2034}
2035
2036/*
2037 * CMD_SET_RATE_ADAPT_MODE.
2038 */
2039struct mwl8k_cmd_set_rate_adapt_mode {
2040 struct mwl8k_cmd_pkt header;
2041 __le16 action;
2042 __le16 mode;
2043} __attribute__((packed));
2044
2045static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2046{
2047 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2048 int rc;
2049
2050 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2051 if (cmd == NULL)
2052 return -ENOMEM;
2053
2054 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2055 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2056 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2057 cmd->mode = cpu_to_le16(mode);
2058
2059 rc = mwl8k_post_cmd(hw, &cmd->header);
2060 kfree(cmd);
2061
2062 return rc;
2063}
2064
2065/*
2066 * CMD_SET_WMM_MODE.
2067 */
2068struct mwl8k_cmd_set_wmm {
2069 struct mwl8k_cmd_pkt header;
2070 __le16 action;
2071} __attribute__((packed));
2072
2073static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2074{
2075 struct mwl8k_priv *priv = hw->priv;
2076 struct mwl8k_cmd_set_wmm *cmd;
2077 int rc;
2078
2079 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2080 if (cmd == NULL)
2081 return -ENOMEM;
2082
2083 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2084 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2085 cmd->action = enable ? cpu_to_le16(MWL8K_CMD_SET) : 0;
2086
2087 rc = mwl8k_post_cmd(hw, &cmd->header);
2088 kfree(cmd);
2089
2090 if (!rc)
2091 priv->wmm_mode = enable;
2092
2093 return rc;
2094}
2095
2096/*
2097 * CMD_SET_RTS_THRESHOLD.
2098 */
2099struct mwl8k_cmd_rts_threshold {
2100 struct mwl8k_cmd_pkt header;
2101 __le16 action;
2102 __le16 threshold;
2103} __attribute__((packed));
2104
2105static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2106 u16 action, u16 *threshold)
2107{
2108 struct mwl8k_cmd_rts_threshold *cmd;
2109 int rc;
2110
2111 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2112 if (cmd == NULL)
2113 return -ENOMEM;
2114
2115 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2116 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2117 cmd->action = cpu_to_le16(action);
2118 cmd->threshold = cpu_to_le16(*threshold);
2119
2120 rc = mwl8k_post_cmd(hw, &cmd->header);
2121 kfree(cmd);
2122
2123 return rc;
2124}
2125
2126/*
2127 * CMD_SET_EDCA_PARAMS.
2128 */
2129struct mwl8k_cmd_set_edca_params {
2130 struct mwl8k_cmd_pkt header;
2131
2132 /* See MWL8K_SET_EDCA_XXX below */
2133 __le16 action;
2134
2135 /* TX opportunity in units of 32 us */
2136 __le16 txop;
2137
2138 /* Log exponent of max contention period: 0...15*/
2139 __u8 log_cw_max;
2140
2141 /* Log exponent of min contention period: 0...15 */
2142 __u8 log_cw_min;
2143
2144 /* Adaptive interframe spacing in units of 32us */
2145 __u8 aifs;
2146
2147 /* TX queue to configure */
2148 __u8 txq;
2149} __attribute__((packed));
2150
2151#define MWL8K_GET_EDCA_ALL 0
2152#define MWL8K_SET_EDCA_CW 0x01
2153#define MWL8K_SET_EDCA_TXOP 0x02
2154#define MWL8K_SET_EDCA_AIFS 0x04
2155
2156#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2157 MWL8K_SET_EDCA_TXOP | \
2158 MWL8K_SET_EDCA_AIFS)
2159
2160static int
2161mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2162 __u16 cw_min, __u16 cw_max,
2163 __u8 aifs, __u16 txop)
2164{
2165 struct mwl8k_cmd_set_edca_params *cmd;
2166 u32 log_cw_min, log_cw_max;
2167 int rc;
2168
2169 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2170 if (cmd == NULL)
2171 return -ENOMEM;
2172
2173 log_cw_min = ilog2(cw_min+1);
2174 log_cw_max = ilog2(cw_max+1);
2175 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2176 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2177
2178 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2179 cmd->txop = cpu_to_le16(txop);
2180 cmd->log_cw_max = (u8)log_cw_max;
2181 cmd->log_cw_min = (u8)log_cw_min;
2182 cmd->aifs = aifs;
2183 cmd->txq = qnum;
2184
2185 rc = mwl8k_post_cmd(hw, &cmd->header);
2186 kfree(cmd);
2187
2188 return rc;
2189}
2190
2191/*
2192 * CMD_FINALIZE_JOIN.
2193 */
2194
2195/* FJ beacon buffer size is compiled into the firmware. */
2196#define MWL8K_FJ_BEACON_MAXLEN 128
2197
2198struct mwl8k_cmd_finalize_join {
2199 struct mwl8k_cmd_pkt header;
2200 __le32 sleep_interval; /* Number of beacon periods to sleep */
2201 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2202} __attribute__((packed));
2203
2204static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2205 __u16 framelen, __u16 dtim)
2206{
2207 struct mwl8k_cmd_finalize_join *cmd;
2208 struct ieee80211_mgmt *payload = frame;
2209 u16 hdrlen;
2210 u32 payload_len;
2211 int rc;
2212
2213 if (frame == NULL)
2214 return -EINVAL;
2215
2216 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2217 if (cmd == NULL)
2218 return -ENOMEM;
2219
2220 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2221 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2222
2223 if (dtim)
2224 cmd->sleep_interval = cpu_to_le32(dtim);
2225 else
2226 cmd->sleep_interval = cpu_to_le32(1);
2227
2228 hdrlen = ieee80211_hdrlen(payload->frame_control);
2229
2230 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2231
2232 /* XXX TBD Might just have to abort and return an error */
2233 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2234 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2235 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2236 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2237
2238 payload_len = payload_len > MWL8K_FJ_BEACON_MAXLEN ?
2239 MWL8K_FJ_BEACON_MAXLEN : payload_len;
2240
2241 if (payload && payload_len)
2242 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2243
2244 rc = mwl8k_post_cmd(hw, &cmd->header);
2245 kfree(cmd);
2246 return rc;
2247}
2248
2249/*
2250 * CMD_UPDATE_STADB.
2251 */
2252struct mwl8k_cmd_update_sta_db {
2253 struct mwl8k_cmd_pkt header;
2254
2255 /* See STADB_ACTION_TYPE */
2256 __le32 action;
2257
2258 /* Peer MAC address */
2259 __u8 peer_addr[IEEE80211_ADDR_LEN];
2260
2261 __le32 reserved;
2262
2263 /* Peer info - valid during add/update. */
2264 struct peer_capability_info peer_info;
2265} __attribute__((packed));
2266
2267static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2268 struct ieee80211_vif *vif, __u32 action)
2269{
2270 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2271 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2272 struct mwl8k_cmd_update_sta_db *cmd;
2273 struct peer_capability_info *peer_info;
2274 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2275 DECLARE_MAC_BUF(mac);
2276 int rc;
2277 __u8 count, *rates;
2278
2279 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2280 if (cmd == NULL)
2281 return -ENOMEM;
2282
2283 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2284 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2285
2286 cmd->action = cpu_to_le32(action);
2287 peer_info = &cmd->peer_info;
2288 memcpy(cmd->peer_addr, mv_vif->bssid, IEEE80211_ADDR_LEN);
2289
2290 switch (action) {
2291 case MWL8K_STA_DB_ADD_ENTRY:
2292 case MWL8K_STA_DB_MODIFY_ENTRY:
2293 /* Build peer_info block */
2294 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2295 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2296 peer_info->interop = 1;
2297 peer_info->amsdu_enabled = 0;
2298
2299 rates = peer_info->legacy_rates;
2300 for (count = 0 ; count < mv_vif->legacy_nrates; count++)
2301 rates[count] = bitrates[count].hw_value;
2302
2303 rc = mwl8k_post_cmd(hw, &cmd->header);
2304 if (rc == 0)
2305 mv_vif->peer_id = peer_info->station_id;
2306
2307 break;
2308
2309 case MWL8K_STA_DB_DEL_ENTRY:
2310 case MWL8K_STA_DB_FLUSH:
2311 default:
2312 rc = mwl8k_post_cmd(hw, &cmd->header);
2313 if (rc == 0)
2314 mv_vif->peer_id = 0;
2315 break;
2316 }
2317 kfree(cmd);
2318
2319 return rc;
2320}
2321
2322/*
2323 * CMD_SET_AID.
2324 */
2325#define IEEE80211_OPMODE_DISABLED 0x00
2326#define IEEE80211_OPMODE_NON_MEMBER_PROT_MODE 0x01
2327#define IEEE80211_OPMODE_ONE_20MHZ_STA_PROT_MODE 0x02
2328#define IEEE80211_OPMODE_HTMIXED_PROT_MODE 0x03
2329
2330#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2331
2332#define MWL8K_FRAME_PROT_DISABLED 0x00
2333#define MWL8K_FRAME_PROT_11G 0x07
2334#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2335#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2336#define MWL8K_FRAME_PROT_MASK 0x07
2337
2338struct mwl8k_cmd_update_set_aid {
2339 struct mwl8k_cmd_pkt header;
2340 __le16 aid;
2341
2342 /* AP's MAC address (BSSID) */
2343 __u8 bssid[IEEE80211_ADDR_LEN];
2344 __le16 protection_mode;
2345 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2346} __attribute__((packed));
2347
2348static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2349 struct ieee80211_vif *vif)
2350{
2351 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2352 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2353 struct mwl8k_cmd_update_set_aid *cmd;
2354 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2355 int count;
2356 u16 prot_mode;
2357 int rc;
2358
2359 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2360 if (cmd == NULL)
2361 return -ENOMEM;
2362
2363 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2364 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2365 cmd->aid = cpu_to_le16(info->aid);
2366
2367 memcpy(cmd->bssid, mv_vif->bssid, IEEE80211_ADDR_LEN);
2368
2369 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2370
2371 if (info->use_cts_prot) {
2372 prot_mode = MWL8K_FRAME_PROT_11G;
2373 } else {
9ed6bcce 2374 switch (info->ht_operation_mode &
a66098da
LB		 2375 IEEE80211_HT_OP_MODE_PROTECTION) {
2376 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2377 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2378 break;
2379 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2380 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2381 break;
2382 default:
2383 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2384 break;
2385 }
2386 }
2387
2388 cmd->protection_mode = cpu_to_le16(prot_mode);
2389
2390 for (count = 0; count < mv_vif->legacy_nrates; count++)
2391 cmd->supp_rates[count] = bitrates[count].hw_value;
2392
2393 rc = mwl8k_post_cmd(hw, &cmd->header);
2394 kfree(cmd);
2395
2396 return rc;
2397}
2398
2399/*
2400 * CMD_SET_RATE.
2401 */
2402struct mwl8k_cmd_update_rateset {
2403 struct mwl8k_cmd_pkt header;
2404 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2405
2406 /* Bitmap for supported MCS codes. */
2407 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2408 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2409} __attribute__((packed));
2410
2411static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2412 struct ieee80211_vif *vif)
2413{
2414 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2415 struct mwl8k_cmd_update_rateset *cmd;
2416 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2417 int count;
2418 int rc;
2419
2420 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2421 if (cmd == NULL)
2422 return -ENOMEM;
2423
2424 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2425 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2426
2427 for (count = 0; count < mv_vif->legacy_nrates; count++)
2428 cmd->legacy_rates[count] = bitrates[count].hw_value;
2429
2430 rc = mwl8k_post_cmd(hw, &cmd->header);
2431 kfree(cmd);
2432
2433 return rc;
2434}
2435
2436/*
2437 * CMD_USE_FIXED_RATE.
2438 */
2439#define MWL8K_RATE_TABLE_SIZE 8
2440#define MWL8K_UCAST_RATE 0
2441#define MWL8K_MCAST_RATE 1
2442#define MWL8K_BCAST_RATE 2
2443
2444#define MWL8K_USE_FIXED_RATE 0x0001
2445#define MWL8K_USE_AUTO_RATE 0x0002
2446
2447struct mwl8k_rate_entry {
2448 /* Set to 1 if HT rate, 0 if legacy. */
2449 __le32 is_ht_rate;
2450
2451 /* Set to 1 to use retry_count field. */
2452 __le32 enable_retry;
2453
2454 /* Specified legacy rate or MCS. */
2455 __le32 rate;
2456
2457 /* Number of allowed retries. */
2458 __le32 retry_count;
2459} __attribute__((packed));
2460
2461struct mwl8k_rate_table {
2462 /* 1 to allow specified rate and below */
2463 __le32 allow_rate_drop;
2464 __le32 num_rates;
2465 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2466} __attribute__((packed));
2467
2468struct mwl8k_cmd_use_fixed_rate {
2469 struct mwl8k_cmd_pkt header;
2470 __le32 action;
2471 struct mwl8k_rate_table rate_table;
2472
2473 /* Unicast, Broadcast or Multicast */
2474 __le32 rate_type;
2475 __le32 reserved1;
2476 __le32 reserved2;
2477} __attribute__((packed));
2478
2479static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2480 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2481{
2482 struct mwl8k_cmd_use_fixed_rate *cmd;
2483 int count;
2484 int rc;
2485
2486 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2487 if (cmd == NULL)
2488 return -ENOMEM;
2489
2490 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2491 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2492
2493 cmd->action = cpu_to_le32(action);
2494 cmd->rate_type = cpu_to_le32(rate_type);
2495
2496 if (rate_table != NULL) {
2497 /* Copy over each field manually so
2498 * that bitflipping can be done
2499 */
2500 cmd->rate_table.allow_rate_drop =
2501 cpu_to_le32(rate_table->allow_rate_drop);
2502 cmd->rate_table.num_rates =
2503 cpu_to_le32(rate_table->num_rates);
2504
2505 for (count = 0; count < rate_table->num_rates; count++) {
2506 struct mwl8k_rate_entry *dst =
2507 &cmd->rate_table.rate_entry[count];
2508 struct mwl8k_rate_entry *src =
2509 &rate_table->rate_entry[count];
2510
2511 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2512 dst->enable_retry = cpu_to_le32(src->enable_retry);
2513 dst->rate = cpu_to_le32(src->rate);
2514 dst->retry_count = cpu_to_le32(src->retry_count);
2515 }
2516 }
2517
2518 rc = mwl8k_post_cmd(hw, &cmd->header);
2519 kfree(cmd);
2520
2521 return rc;
2522}
2523
2524
2525/*
2526 * Interrupt handling.
2527 */
2528static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2529{
2530 struct ieee80211_hw *hw = dev_id;
2531 struct mwl8k_priv *priv = hw->priv;
2532 u32 status;
2533
2534 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2535 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2536
2537 status &= priv->int_mask;
2538 if (!status)
2539 return IRQ_NONE;
2540
2541 if (status & MWL8K_A2H_INT_TX_DONE)
2542 tasklet_schedule(&priv->tx_reclaim_task);
2543
2544 if (status & MWL8K_A2H_INT_RX_READY) {
2545 while (rxq_process(hw, 0, 1))
2546 rxq_refill(hw, 0, 1);
2547 }
2548
2549 if (status & MWL8K_A2H_INT_OPC_DONE) {
2550 if (priv->hostcmd_wait != NULL) {
2551 complete(priv->hostcmd_wait);
2552 priv->hostcmd_wait = NULL;
2553 }
2554 }
2555
2556 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2557 if (!priv->inconfig &&
2558 priv->radio_state &&
2559 mwl8k_txq_busy(priv))
2560 mwl8k_tx_start(priv);
2561 }
2562
2563 return IRQ_HANDLED;
2564}
2565
2566
2567/*
2568 * Core driver operations.
2569 */
2570static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2571{
2572 struct mwl8k_priv *priv = hw->priv;
2573 int index = skb_get_queue_mapping(skb);
2574 int rc;
2575
2576 if (priv->current_channel == NULL) {
2577 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2578 "disabled\n", priv->name);
2579 dev_kfree_skb(skb);
2580 return NETDEV_TX_OK;
2581 }
2582
2583 rc = mwl8k_txq_xmit(hw, index, skb);
2584
2585 return rc;
2586}
2587
2588struct mwl8k_work_struct {
2589 /* Initialized by mwl8k_queue_work(). */
2590 struct work_struct wt;
2591
2592 /* Required field passed in to mwl8k_queue_work(). */
2593 struct ieee80211_hw *hw;
2594
2595 /* Required field passed in to mwl8k_queue_work(). */
2596 int (*wfunc)(struct work_struct *w);
2597
2598 /* Initialized by mwl8k_queue_work(). */
2599 struct completion *cmd_wait;
2600
2601 /* Result code. */
2602 int rc;
2603
2604 /*
2605 * Optional field. Refer to explanation of MWL8K_WQ_XXX_XXX
2606 * flags for explanation. Defaults to MWL8K_WQ_DEFAULT_OPTIONS.
2607 */
2608 u32 options;
2609
2610 /* Optional field. Defaults to MWL8K_CONFIG_TIMEOUT_MS. */
2611 unsigned long timeout_ms;
2612
2613 /* Optional field. Defaults to MWL8K_WQ_TXWAIT_ATTEMPTS. */
2614 u32 txwait_attempts;
2615
2616 /* Optional field. Defaults to MWL8K_TXWAIT_MS. */
2617 u32 tx_timeout_ms;
2618 u32 step;
2619};
2620
2621/* Flags controlling behavior of config queue requests */
2622
2623/* Caller spins while waiting for completion. */
2624#define MWL8K_WQ_SPIN 0x00000001
2625
2626/* Wait for TX queues to empty before proceeding with configuration. */
2627#define MWL8K_WQ_TX_WAIT_EMPTY 0x00000002
2628
2629/* Queue request and return immediately. */
2630#define MWL8K_WQ_POST_REQUEST 0x00000004
2631
2632/*
2633 * Caller sleeps and waits for task complete notification.
2634 * Do not use in atomic context.
2635 */
2636#define MWL8K_WQ_SLEEP 0x00000008
2637
2638/* Free work struct when task is done. */
2639#define MWL8K_WQ_FREE_WORKSTRUCT 0x00000010
2640
2641/*
2642 * Config request is queued and returns to caller imediately. Use
2643 * this in atomic context. Work struct is freed by mwl8k_queue_work()
2644 * when this flag is set.
2645 */
2646#define MWL8K_WQ_QUEUE_ONLY (MWL8K_WQ_POST_REQUEST | \
2647 MWL8K_WQ_FREE_WORKSTRUCT)
2648
2649/* Default work queue behavior is to sleep and wait for tx completion. */
2650#define MWL8K_WQ_DEFAULT_OPTIONS (MWL8K_WQ_SLEEP | MWL8K_WQ_TX_WAIT_EMPTY)
2651
2652/*
2653 * Default config request timeout. Add adjustments to make sure the
2654 * config thread waits long enough for both tx wait and cmd wait before
2655 * timing out.
2656 */
2657
2658/* Time to wait for all TXQs to drain. TX Doorbell is pressed each time. */
2659#define MWL8K_TXWAIT_TIMEOUT_MS 1000
2660
2661/* Default number of TX wait attempts. */
2662#define MWL8K_WQ_TXWAIT_ATTEMPTS 4
2663
2664/* Total time to wait for TXQ to drain. */
2665#define MWL8K_TXWAIT_MS (MWL8K_TXWAIT_TIMEOUT_MS * \
2666 MWL8K_WQ_TXWAIT_ATTEMPTS)
2667
2668/* Scheduling slop. */
2669#define MWL8K_OS_SCHEDULE_OVERHEAD_MS 200
2670
2671#define MWL8K_CONFIG_TIMEOUT_MS (MWL8K_CMD_TIMEOUT_MS + \
2672 MWL8K_TXWAIT_MS + \
2673 MWL8K_OS_SCHEDULE_OVERHEAD_MS)
2674
2675static void mwl8k_config_thread(struct work_struct *wt)
2676{
2677 struct mwl8k_work_struct *worker = (struct mwl8k_work_struct *)wt;
2678 struct ieee80211_hw *hw = worker->hw;
2679 struct mwl8k_priv *priv = hw->priv;
2680 int rc = 0;
2681
2682 spin_lock_irq(&priv->tx_lock);
2683 priv->inconfig = true;
2684 spin_unlock_irq(&priv->tx_lock);
2685
2686 ieee80211_stop_queues(hw);
2687
2688 /*
2689 * Wait for host queues to drain before doing PHY
2690 * reconfiguration. This avoids interrupting any in-flight
2691 * DMA transfers to the hardware.
2692 */
2693 if (worker->options & MWL8K_WQ_TX_WAIT_EMPTY) {
2694 u32 timeout;
2695 u32 time_remaining;
2696 u32 iter;
2697 u32 tx_wait_attempts = worker->txwait_attempts;
2698
2699 time_remaining = worker->tx_timeout_ms;
2700 if (!tx_wait_attempts)
2701 tx_wait_attempts = 1;
2702
2703 timeout = worker->tx_timeout_ms/tx_wait_attempts;
2704 if (!timeout)
2705 timeout = 1;
2706
2707 iter = tx_wait_attempts;
2708 do {
2709 int wait_time;
2710
2711 if (time_remaining > timeout) {
2712 time_remaining -= timeout;
2713 wait_time = timeout;
2714 } else
2715 wait_time = time_remaining;
2716
2717 if (!wait_time)
2718 wait_time = 1;
2719
2720 rc = mwl8k_tx_wait_empty(hw, wait_time);
2721 if (rc)
2722 printk(KERN_ERR "%s() txwait timeout=%ums "
2723 "Retry:%u/%u\n", __func__, timeout,
2724 tx_wait_attempts - iter + 1,
2725 tx_wait_attempts);
2726
2727 } while (rc && --iter);
2728
2729 rc = iter ? 0 : -ETIMEDOUT;
2730 }
2731 if (!rc)
2732 rc = worker->wfunc(wt);
2733
2734 spin_lock_irq(&priv->tx_lock);
2735 priv->inconfig = false;
2736 if (priv->pending_tx_pkts && priv->radio_state)
2737 mwl8k_tx_start(priv);
2738 spin_unlock_irq(&priv->tx_lock);
2739 ieee80211_wake_queues(hw);
2740
2741 worker->rc = rc;
2742 if (worker->options & MWL8K_WQ_SLEEP)
2743 complete(worker->cmd_wait);
2744
2745 if (worker->options & MWL8K_WQ_FREE_WORKSTRUCT)
2746 kfree(wt);
2747}
2748
2749static int mwl8k_queue_work(struct ieee80211_hw *hw,
2750 struct mwl8k_work_struct *worker,
2751 struct workqueue_struct *wqueue,
2752 int (*wfunc)(struct work_struct *w))
2753{
2754 unsigned long timeout = 0;
2755 int rc = 0;
2756
2757 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2758
2759 if (!worker->timeout_ms)
2760 worker->timeout_ms = MWL8K_CONFIG_TIMEOUT_MS;
2761
2762 if (!worker->options)
2763 worker->options = MWL8K_WQ_DEFAULT_OPTIONS;
2764
2765 if (!worker->txwait_attempts)
2766 worker->txwait_attempts = MWL8K_WQ_TXWAIT_ATTEMPTS;
2767
2768 if (!worker->tx_timeout_ms)
2769 worker->tx_timeout_ms = MWL8K_TXWAIT_MS;
2770
2771 worker->hw = hw;
2772 worker->cmd_wait = &cmd_wait;
2773 worker->rc = 1;
2774 worker->wfunc = wfunc;
2775
2776 INIT_WORK(&worker->wt, mwl8k_config_thread);
2777 queue_work(wqueue, &worker->wt);
2778
2779 if (worker->options & MWL8K_WQ_POST_REQUEST) {
2780 rc = 0;
2781 } else {
2782 if (worker->options & MWL8K_WQ_SPIN) {
2783 timeout = worker->timeout_ms;
2784 while (timeout && (worker->rc > 0)) {
2785 mdelay(1);
2786 timeout--;
2787 }
2788 } else if (worker->options & MWL8K_WQ_SLEEP)
2789 timeout = wait_for_completion_timeout(&cmd_wait,
2790 msecs_to_jiffies(worker->timeout_ms));
2791
2792 if (timeout)
2793 rc = worker->rc;
2794 else {
2795 cancel_work_sync(&worker->wt);
2796 rc = -ETIMEDOUT;
2797 }
2798 }
2799
2800 return rc;
2801}
2802
2803struct mwl8k_start_worker {
2804 struct mwl8k_work_struct header;
2805};
2806
2807static int mwl8k_start_wt(struct work_struct *wt)
2808{
2809 struct mwl8k_start_worker *worker = (struct mwl8k_start_worker *)wt;
2810 struct ieee80211_hw *hw = worker->header.hw;
2811 struct mwl8k_priv *priv = hw->priv;
2812 int rc = 0;
2813
2814 if (priv->vif != NULL) {
2815 rc = -EIO;
2816 goto mwl8k_start_exit;
2817 }
2818
2819 /* Turn on radio */
2820 if (mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_ENABLE)) {
2821 rc = -EIO;
2822 goto mwl8k_start_exit;
2823 }
2824
2825 /* Purge TX/RX HW queues */
2826 if (mwl8k_cmd_set_pre_scan(hw)) {
2827 rc = -EIO;
2828 goto mwl8k_start_exit;
2829 }
2830
2831 if (mwl8k_cmd_set_post_scan(hw, "\x00\x00\x00\x00\x00\x00")) {
2832 rc = -EIO;
2833 goto mwl8k_start_exit;
2834 }
2835
2836 /* Enable firmware rate adaptation */
2837 if (mwl8k_cmd_setrateadaptmode(hw, 0)) {
2838 rc = -EIO;
2839 goto mwl8k_start_exit;
2840 }
2841
2842 /* Disable WMM. WMM gets enabled when stack sends WMM parms */
2843 if (mwl8k_set_wmm(hw, MWL8K_WMM_DISABLE)) {
2844 rc = -EIO;
2845 goto mwl8k_start_exit;
2846 }
2847
2848 /* Disable sniffer mode */
2849 if (mwl8k_enable_sniffer(hw, 0))
2850 rc = -EIO;
2851
2852mwl8k_start_exit:
2853 return rc;
2854}
2855
2856static int mwl8k_start(struct ieee80211_hw *hw)
2857{
2858 struct mwl8k_start_worker *worker;
2859 struct mwl8k_priv *priv = hw->priv;
2860 int rc;
2861
2862 /* Enable tx reclaim tasklet */
2863 tasklet_enable(&priv->tx_reclaim_task);
2864
2865 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2866 IRQF_SHARED, MWL8K_NAME, hw);
2867 if (rc) {
2868 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2869 priv->name);
2870 rc = -EIO;
2871 goto mwl8k_start_disable_tasklet;
2872 }
2873
2874 /* Enable interrupts */
2875 iowrite32(priv->int_mask, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2876
2877 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2878 if (worker == NULL) {
2879 rc = -ENOMEM;
2880 goto mwl8k_start_disable_irq;
2881 }
2882
2883 rc = mwl8k_queue_work(hw, &worker->header,
2884 priv->config_wq, mwl8k_start_wt);
2885 kfree(worker);
2886 if (!rc)
2887 return rc;
2888
2889 if (rc == -ETIMEDOUT)
2890 printk(KERN_ERR "%s() timed out\n", __func__);
2891
2892 rc = -EIO;
2893
2894mwl8k_start_disable_irq:
2895 spin_lock_irq(&priv->tx_lock);
2896 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2897 spin_unlock_irq(&priv->tx_lock);
2898 free_irq(priv->pdev->irq, hw);
2899
2900mwl8k_start_disable_tasklet:
2901 tasklet_disable(&priv->tx_reclaim_task);
2902
2903 return rc;
2904}
2905
2906struct mwl8k_stop_worker {
2907 struct mwl8k_work_struct header;
2908};
2909
2910static int mwl8k_stop_wt(struct work_struct *wt)
2911{
2912 struct mwl8k_stop_worker *worker = (struct mwl8k_stop_worker *)wt;
2913 struct ieee80211_hw *hw = worker->header.hw;
2914 int rc;
2915
2916 rc = mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_DISABLE);
2917
2918 return rc;
2919}
2920
2921static void mwl8k_stop(struct ieee80211_hw *hw)
2922{
2923 int rc;
2924 struct mwl8k_stop_worker *worker;
2925 struct mwl8k_priv *priv = hw->priv;
2926 int i;
2927
2928 if (priv->vif != NULL)
2929 return;
2930
2931 ieee80211_stop_queues(hw);
2932
2933 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2934 if (worker == NULL)
2935 return;
2936
2937 rc = mwl8k_queue_work(hw, &worker->header,
2938 priv->config_wq, mwl8k_stop_wt);
2939 kfree(worker);
2940 if (rc == -ETIMEDOUT)
2941 printk(KERN_ERR "%s() timed out\n", __func__);
2942
2943 /* Disable interrupts */
2944 spin_lock_irq(&priv->tx_lock);
2945 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2946 spin_unlock_irq(&priv->tx_lock);
2947 free_irq(priv->pdev->irq, hw);
2948
2949 /* Stop finalize join worker */
2950 cancel_work_sync(&priv->finalize_join_worker);
2951 if (priv->beacon_skb != NULL)
2952 dev_kfree_skb(priv->beacon_skb);
2953
2954 /* Stop tx reclaim tasklet */
2955 tasklet_disable(&priv->tx_reclaim_task);
2956
2957 /* Stop config thread */
2958 flush_workqueue(priv->config_wq);
2959
2960 /* Return all skbs to mac80211 */
2961 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2962 mwl8k_txq_reclaim(hw, i, 1);
2963}
2964
2965static int mwl8k_add_interface(struct ieee80211_hw *hw,
2966 struct ieee80211_if_init_conf *conf)
2967{
2968 struct mwl8k_priv *priv = hw->priv;
2969 struct mwl8k_vif *mwl8k_vif;
2970
2971 /*
2972 * We only support one active interface at a time.
2973 */
2974 if (priv->vif != NULL)
2975 return -EBUSY;
2976
2977 /*
2978 * We only support managed interfaces for now.
2979 */
2980 if (conf->type != NL80211_IFTYPE_STATION &&
2981 conf->type != NL80211_IFTYPE_MONITOR)
2982 return -EINVAL;
2983
2984 /* Clean out driver private area */
2985 mwl8k_vif = MWL8K_VIF(conf->vif);
2986 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2987
2988 /* Save the mac address */
2989 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, IEEE80211_ADDR_LEN);
2990
2991 /* Back pointer to parent config block */
2992 mwl8k_vif->priv = priv;
2993
2994 /* Setup initial PHY parameters */
2995 memcpy(mwl8k_vif->legacy_rates ,
2996 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2997 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2998
2999 /* Set Initial sequence number to zero */
3000 mwl8k_vif->seqno = 0;
3001
3002 priv->vif = conf->vif;
3003 priv->current_channel = NULL;
3004
3005 return 0;
3006}
3007
3008static void mwl8k_remove_interface(struct ieee80211_hw *hw,
3009 struct ieee80211_if_init_conf *conf)
3010{
3011 struct mwl8k_priv *priv = hw->priv;
3012
3013 if (priv->vif == NULL)
3014 return;
3015
3016 priv->vif = NULL;
3017}
3018
3019struct mwl8k_config_worker {
3020 struct mwl8k_work_struct header;
3021 u32 changed;
3022};
3023
3024static int mwl8k_config_wt(struct work_struct *wt)
3025{
3026 struct mwl8k_config_worker *worker =
3027 (struct mwl8k_config_worker *)wt;
3028 struct ieee80211_hw *hw = worker->header.hw;
3029 struct ieee80211_conf *conf = &hw->conf;
3030 struct mwl8k_priv *priv = hw->priv;
3031 int rc = 0;
3032
3033 if (!conf->radio_enabled) {
3034 mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_DISABLE);
3035 priv->current_channel = NULL;
3036 rc = 0;
3037 goto mwl8k_config_exit;
3038 }
3039
3040 if (mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_ENABLE)) {
3041 rc = -EINVAL;
3042 goto mwl8k_config_exit;
3043 }
3044
3045 priv->current_channel = conf->channel;
3046
3047 if (mwl8k_cmd_set_rf_channel(hw, conf->channel)) {
3048 rc = -EINVAL;
3049 goto mwl8k_config_exit;
3050 }
3051
3052 if (conf->power_level > 18)
3053 conf->power_level = 18;
3054 if (mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level)) {
3055 rc = -EINVAL;
3056 goto mwl8k_config_exit;
3057 }
3058
3059 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
3060 rc = -EINVAL;
3061
3062mwl8k_config_exit:
3063 return rc;
3064}
3065
3066static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
3067{
3068 int rc = 0;
3069 struct mwl8k_config_worker *worker;
3070 struct mwl8k_priv *priv = hw->priv;
3071
3072 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3073 if (worker == NULL)
3074 return -ENOMEM;
3075
3076 worker->changed = changed;
3077 rc = mwl8k_queue_work(hw, &worker->header,
3078 priv->config_wq, mwl8k_config_wt);
3079 if (rc == -ETIMEDOUT) {
3080 printk(KERN_ERR "%s() timed out.\n", __func__);
3081 rc = -EINVAL;
3082 }
3083
3084 kfree(worker);
3085
3086 /*
3087 * mac80211 will crash on anything other than -EINVAL on
3088 * error. Looks like wireless extensions which calls mac80211
3089 * may be the actual culprit...
3090 */
3091 return rc ? -EINVAL : 0;
3092}
3093
a66098da
LB		 3094struct mwl8k_bss_info_changed_worker {
3095 struct mwl8k_work_struct header;
3096 struct ieee80211_vif *vif;
3097 struct ieee80211_bss_conf *info;
3098 u32 changed;
3099};
3100
3101static int mwl8k_bss_info_changed_wt(struct work_struct *wt)
3102{
3103 struct mwl8k_bss_info_changed_worker *worker =
3104 (struct mwl8k_bss_info_changed_worker *)wt;
3105 struct ieee80211_hw *hw = worker->header.hw;
3106 struct ieee80211_vif *vif = worker->vif;
3107 struct ieee80211_bss_conf *info = worker->info;
3108 u32 changed;
3109 int rc;
3110
3111 struct mwl8k_priv *priv = hw->priv;
3112 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3113
3114 changed = worker->changed;
3115 priv->capture_beacon = false;
3116
3117 if (info->assoc) {
3118 memcpy(&mwl8k_vif->bss_info, info,
3119 sizeof(struct ieee80211_bss_conf));
3120
3121 /* Install rates */
3122 if (mwl8k_update_rateset(hw, vif))
3123 goto mwl8k_bss_info_changed_exit;
3124
3125 /* Turn on rate adaptation */
3126 if (mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3127 MWL8K_UCAST_RATE, NULL))
3128 goto mwl8k_bss_info_changed_exit;
3129
3130 /* Set radio preamble */
3131 if (mwl8k_set_radio_preamble(hw,
3132 info->use_short_preamble))
3133 goto mwl8k_bss_info_changed_exit;
3134
3135 /* Set slot time */
3136 if (mwl8k_cmd_set_slot(hw, info->use_short_slot ?
3137 MWL8K_SHORT_SLOTTIME : MWL8K_LONG_SLOTTIME))
3138 goto mwl8k_bss_info_changed_exit;
3139
3140 /* Update peer rate info */
3141 if (mwl8k_cmd_update_sta_db(hw, vif,
3142 MWL8K_STA_DB_MODIFY_ENTRY))
3143 goto mwl8k_bss_info_changed_exit;
3144
3145 /* Set AID */
3146 if (mwl8k_cmd_set_aid(hw, vif))
3147 goto mwl8k_bss_info_changed_exit;
3148
3149 /*
3150 * Finalize the join. Tell rx handler to process
3151 * next beacon from our BSSID.
3152 */
3153 memcpy(priv->capture_bssid,
3154 mwl8k_vif->bssid, IEEE80211_ADDR_LEN);
3155 priv->capture_beacon = true;
3156 } else {
3157 mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3158 memset(&mwl8k_vif->bss_info, 0,
3159 sizeof(struct ieee80211_bss_conf));
3160 memset(mwl8k_vif->bssid, 0, IEEE80211_ADDR_LEN);
3161 }
3162
3163mwl8k_bss_info_changed_exit:
3164 rc = 0;
3165 return rc;
3166}
3167
3168static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3169 struct ieee80211_vif *vif,
3170 struct ieee80211_bss_conf *info,
3171 u32 changed)
3172{
3173 struct mwl8k_bss_info_changed_worker *worker;
3174 struct mwl8k_priv *priv = hw->priv;
2d0ddec5 3175 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
a66098da
LB		 3176 int rc;
3177
2d0ddec5
JB		 3178 if (changed & BSS_CHANGED_BSSID)
3179 memcpy(mv_vif->bssid, info->bssid, IEEE80211_ADDR_LEN);
3180
a66098da
LB		 3181 if ((changed & BSS_CHANGED_ASSOC) == 0)
3182 return;
3183
3184 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3185 if (worker == NULL)
3186 return;
3187
3188 worker->vif = vif;
3189 worker->info = info;
3190 worker->changed = changed;
3191 rc = mwl8k_queue_work(hw, &worker->header,
3192 priv->config_wq,
3193 mwl8k_bss_info_changed_wt);
3194 kfree(worker);
3195 if (rc == -ETIMEDOUT)
3196 printk(KERN_ERR "%s() timed out\n", __func__);
3197}
3198
3199struct mwl8k_configure_filter_worker {
3200 struct mwl8k_work_struct header;
3201 unsigned int changed_flags;
3202 unsigned int *total_flags;
3203 int mc_count;
3204 struct dev_addr_list *mclist;
3205};
3206
3207#define MWL8K_SUPPORTED_IF_FLAGS FIF_BCN_PRBRESP_PROMISC
3208
3209static int mwl8k_configure_filter_wt(struct work_struct *wt)
3210{
3211 struct mwl8k_configure_filter_worker *worker =
3212 (struct mwl8k_configure_filter_worker *)wt;
3213
3214 struct ieee80211_hw *hw = worker->header.hw;
3215 unsigned int changed_flags = worker->changed_flags;
3216 unsigned int *total_flags = worker->total_flags;
3217 int mc_count = worker->mc_count;
3218 struct dev_addr_list *mclist = worker->mclist;
3219
3220 struct mwl8k_priv *priv = hw->priv;
3221 struct mwl8k_vif *mv_vif;
3222 int rc = 0;
3223
3224 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3225 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
3226 rc = mwl8k_cmd_set_pre_scan(hw);
3227 else {
3228 mv_vif = MWL8K_VIF(priv->vif);
3229 rc = mwl8k_cmd_set_post_scan(hw, mv_vif->bssid);
3230 }
3231 }
3232
3233 if (rc)
3234 goto mwl8k_configure_filter_exit;
3235 if (mc_count) {
3236 mc_count = mc_count < priv->num_mcaddrs ?
3237 mc_count : priv->num_mcaddrs;
3238 rc = mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist);
3239 if (rc)
3240 printk(KERN_ERR
3241 "%s()Error setting multicast addresses\n",
3242 __func__);
3243 }
3244
3245mwl8k_configure_filter_exit:
3246 return rc;
3247}
3248
3249static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3250 unsigned int changed_flags,
3251 unsigned int *total_flags,
3252 int mc_count,
3253 struct dev_addr_list *mclist)
3254{
3255
3256 struct mwl8k_configure_filter_worker *worker;
3257 struct mwl8k_priv *priv = hw->priv;
3258
3259 /* Clear unsupported feature flags */
3260 *total_flags &= MWL8K_SUPPORTED_IF_FLAGS;
3261
3262 if (!(changed_flags & MWL8K_SUPPORTED_IF_FLAGS) && !mc_count)
3263 return;
3264
3265 worker = kzalloc(sizeof(*worker), GFP_ATOMIC);
3266 if (worker == NULL)
3267 return;
3268
3269 worker->header.options = MWL8K_WQ_QUEUE_ONLY | MWL8K_WQ_TX_WAIT_EMPTY;
3270 worker->changed_flags = changed_flags;
3271 worker->total_flags = total_flags;
3272 worker->mc_count = mc_count;
3273 worker->mclist = mclist;
3274
3275 mwl8k_queue_work(hw, &worker->header, priv->config_wq,
3276 mwl8k_configure_filter_wt);
3277}
3278
3279struct mwl8k_set_rts_threshold_worker {
3280 struct mwl8k_work_struct header;
3281 u32 value;
3282};
3283
3284static int mwl8k_set_rts_threshold_wt(struct work_struct *wt)
3285{
3286 struct mwl8k_set_rts_threshold_worker *worker =
3287 (struct mwl8k_set_rts_threshold_worker *)wt;
3288
3289 struct ieee80211_hw *hw = worker->header.hw;
3290 u16 threshold = (u16)(worker->value);
3291 int rc;
3292
3293 rc = mwl8k_rts_threshold(hw, MWL8K_CMD_SET, &threshold);
3294
3295 return rc;
3296}
3297
3298static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3299{
3300 int rc;
3301 struct mwl8k_set_rts_threshold_worker *worker;
3302 struct mwl8k_priv *priv = hw->priv;
3303
3304 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3305 if (worker == NULL)
3306 return -ENOMEM;
3307
3308 worker->value = value;
3309
3310 rc = mwl8k_queue_work(hw, &worker->header,
3311 priv->config_wq,
3312 mwl8k_set_rts_threshold_wt);
3313 kfree(worker);
3314
3315 if (rc == -ETIMEDOUT) {
3316 printk(KERN_ERR "%s() timed out\n", __func__);
3317 rc = -EINVAL;
3318 }
3319
3320 return rc;
3321}
3322
3323struct mwl8k_conf_tx_worker {
3324 struct mwl8k_work_struct header;
3325 u16 queue;
3326 const struct ieee80211_tx_queue_params *params;
3327};
3328
3329static int mwl8k_conf_tx_wt(struct work_struct *wt)
3330{
3331 struct mwl8k_conf_tx_worker *worker =
3332 (struct mwl8k_conf_tx_worker *)wt;
3333
3334 struct ieee80211_hw *hw = worker->header.hw;
3335 u16 queue = worker->queue;
3336 const struct ieee80211_tx_queue_params *params = worker->params;
3337
3338 struct mwl8k_priv *priv = hw->priv;
3339 int rc = 0;
3340
3341 if (priv->wmm_mode == MWL8K_WMM_DISABLE)
3342 if (mwl8k_set_wmm(hw, MWL8K_WMM_ENABLE)) {
3343 rc = -EINVAL;
3344 goto mwl8k_conf_tx_exit;
3345 }
3346
3347 if (mwl8k_set_edca_params(hw, GET_TXQ(queue), params->cw_min,
3348 params->cw_max, params->aifs, params->txop))
3349 rc = -EINVAL;
3350mwl8k_conf_tx_exit:
3351 return rc;
3352}
3353
3354static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3355 const struct ieee80211_tx_queue_params *params)
3356{
3357 int rc;
3358 struct mwl8k_conf_tx_worker *worker;
3359 struct mwl8k_priv *priv = hw->priv;
3360
3361 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3362 if (worker == NULL)
3363 return -ENOMEM;
3364
3365 worker->queue = queue;
3366 worker->params = params;
3367 rc = mwl8k_queue_work(hw, &worker->header,
3368 priv->config_wq, mwl8k_conf_tx_wt);
3369 kfree(worker);
3370 if (rc == -ETIMEDOUT) {
3371 printk(KERN_ERR "%s() timed out\n", __func__);
3372 rc = -EINVAL;
3373 }
3374 return rc;
3375}
3376
3377static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3378 struct ieee80211_tx_queue_stats *stats)
3379{
3380 struct mwl8k_priv *priv = hw->priv;
3381 struct mwl8k_tx_queue *txq;
3382 int index;
3383
3384 spin_lock_bh(&priv->tx_lock);
3385 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3386 txq = priv->txq + index;
3387 memcpy(&stats[index], &txq->tx_stats,
3388 sizeof(struct ieee80211_tx_queue_stats));
3389 }
3390 spin_unlock_bh(&priv->tx_lock);
3391 return 0;
3392}
3393
3394struct mwl8k_get_stats_worker {
3395 struct mwl8k_work_struct header;
3396 struct ieee80211_low_level_stats *stats;
3397};
3398
3399static int mwl8k_get_stats_wt(struct work_struct *wt)
3400{
3401 struct mwl8k_get_stats_worker *worker =
3402 (struct mwl8k_get_stats_worker *)wt;
3403
3404 return mwl8k_cmd_802_11_get_stat(worker->header.hw, worker->stats);
3405}
3406
3407static int mwl8k_get_stats(struct ieee80211_hw *hw,
3408 struct ieee80211_low_level_stats *stats)
3409{
3410 int rc;
3411 struct mwl8k_get_stats_worker *worker;
3412 struct mwl8k_priv *priv = hw->priv;
3413
3414 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3415 if (worker == NULL)
3416 return -ENOMEM;
3417
3418 worker->stats = stats;
3419 rc = mwl8k_queue_work(hw, &worker->header,
3420 priv->config_wq, mwl8k_get_stats_wt);
3421
3422 kfree(worker);
3423 if (rc == -ETIMEDOUT) {
3424 printk(KERN_ERR "%s() timed out\n", __func__);
3425 rc = -EINVAL;
3426 }
3427
3428 return rc;
3429}
3430
3431static const struct ieee80211_ops mwl8k_ops = {
3432 .tx = mwl8k_tx,
3433 .start = mwl8k_start,
3434 .stop = mwl8k_stop,
3435 .add_interface = mwl8k_add_interface,
3436 .remove_interface = mwl8k_remove_interface,
3437 .config = mwl8k_config,
a66098da
LB		 3438 .bss_info_changed = mwl8k_bss_info_changed,
3439 .configure_filter = mwl8k_configure_filter,
3440 .set_rts_threshold = mwl8k_set_rts_threshold,
3441 .conf_tx = mwl8k_conf_tx,
3442 .get_tx_stats = mwl8k_get_tx_stats,
3443 .get_stats = mwl8k_get_stats,
3444};
3445
3446static void mwl8k_tx_reclaim_handler(unsigned long data)
3447{
3448 int i;
3449 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3450 struct mwl8k_priv *priv = hw->priv;
3451
3452 spin_lock_bh(&priv->tx_lock);
3453 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3454 mwl8k_txq_reclaim(hw, i, 0);
3455
3456 if (priv->tx_wait != NULL) {
3457 int count = mwl8k_txq_busy(priv);
3458 if (count == 0) {
3459 complete(priv->tx_wait);
3460 priv->tx_wait = NULL;
3461 }
3462 }
3463 spin_unlock_bh(&priv->tx_lock);
3464}
3465
3466static void mwl8k_finalize_join_worker(struct work_struct *work)
3467{
3468 struct mwl8k_priv *priv =
3469 container_of(work, struct mwl8k_priv, finalize_join_worker);
3470 struct sk_buff *skb = priv->beacon_skb;
3471 u8 dtim = (MWL8K_VIF(priv->vif))->bss_info.dtim_period;
3472
3473 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3474 dev_kfree_skb(skb);
3475
3476 priv->beacon_skb = NULL;
3477}
3478
3479static int __devinit mwl8k_probe(struct pci_dev *pdev,
3480 const struct pci_device_id *id)
3481{
3482 struct ieee80211_hw *hw;
3483 struct mwl8k_priv *priv;
3484 DECLARE_MAC_BUF(mac);
3485 int rc;
3486 int i;
3487 u8 *fw;
3488
3489 rc = pci_enable_device(pdev);
3490 if (rc) {
3491 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3492 MWL8K_NAME);
3493 return rc;
3494 }
3495
3496 rc = pci_request_regions(pdev, MWL8K_NAME);
3497 if (rc) {
3498 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3499 MWL8K_NAME);
3500 return rc;
3501 }
3502
3503 pci_set_master(pdev);
3504
3505 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3506 if (hw == NULL) {
3507 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3508 rc = -ENOMEM;
3509 goto err_free_reg;
3510 }
3511
3512 priv = hw->priv;
3513 priv->hw = hw;
3514 priv->pdev = pdev;
3515 priv->hostcmd_wait = NULL;
3516 priv->tx_wait = NULL;
3517 priv->inconfig = false;
3518 priv->wep_enabled = 0;
3519 priv->wmm_mode = false;
3520 priv->pending_tx_pkts = 0;
3521 strncpy(priv->name, MWL8K_NAME, sizeof(priv->name));
3522
3523 spin_lock_init(&priv->fw_lock);
3524
3525 SET_IEEE80211_DEV(hw, &pdev->dev);
3526 pci_set_drvdata(pdev, hw);
3527
3528 priv->regs = pci_iomap(pdev, 1, 0x10000);
3529 if (priv->regs == NULL) {
3530 printk(KERN_ERR "%s: Cannot map device memory\n", priv->name);
3531 goto err_iounmap;
3532 }
3533
3534 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3535 priv->band.band = IEEE80211_BAND_2GHZ;
3536 priv->band.channels = priv->channels;
3537 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3538 priv->band.bitrates = priv->rates;
3539 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3540 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3541
3542 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3543 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3544
3545 /*
3546 * Extra headroom is the size of the required DMA header
3547 * minus the size of the smallest 802.11 frame (CTS frame).
3548 */
3549 hw->extra_tx_headroom =
3550 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3551
3552 hw->channel_change_time = 10;
3553
3554 hw->queues = MWL8K_TX_QUEUES;
3555
3556 hw->wiphy->interface_modes =
3557 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_MONITOR);
3558
3559 /* Set rssi and noise values to dBm */
3560 hw->flags |= (IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM);
3561 hw->vif_data_size = sizeof(struct mwl8k_vif);
3562 priv->vif = NULL;
3563
3564 /* Set default radio state and preamble */
3565 priv->radio_preamble = MWL8K_RADIO_DEFAULT_PREAMBLE;
3566 priv->radio_state = MWL8K_RADIO_DISABLE;
3567
3568 /* Finalize join worker */
3569 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3570
3571 /* TX reclaim tasklet */
3572 tasklet_init(&priv->tx_reclaim_task,
3573 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3574 tasklet_disable(&priv->tx_reclaim_task);
3575
3576 /* Config workthread */
3577 priv->config_wq = create_singlethread_workqueue("mwl8k_config");
3578 if (priv->config_wq == NULL)
3579 goto err_iounmap;
3580
3581 /* Power management cookie */
3582 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3583 if (priv->cookie == NULL)
3584 goto err_iounmap;
3585
3586 rc = mwl8k_rxq_init(hw, 0);
3587 if (rc)
3588 goto err_iounmap;
3589 rxq_refill(hw, 0, INT_MAX);
3590
3591 spin_lock_init(&priv->tx_lock);
3592
3593 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3594 rc = mwl8k_txq_init(hw, i);
3595 if (rc)
3596 goto err_free_queues;
3597 }
3598
3599 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3600 priv->int_mask = 0;
3601 iowrite32(priv->int_mask, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3602 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3603 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3604
3605 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3606 IRQF_SHARED, MWL8K_NAME, hw);
3607 if (rc) {
3608 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3609 priv->name);
3610 goto err_free_queues;
3611 }
3612
3613 /* Reset firmware and hardware */
3614 mwl8k_hw_reset(priv);
3615
3616 /* Ask userland hotplug daemon for the device firmware */
3617 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3618 if (rc) {
3619 printk(KERN_ERR "%s: Firmware files not found\n", priv->name);
3620 goto err_free_irq;
3621 }
3622
3623 /* Load firmware into hardware */
3624 rc = mwl8k_load_firmware(priv);
3625 if (rc) {
3626 printk(KERN_ERR "%s: Cannot start firmware\n", priv->name);
3627 goto err_stop_firmware;
3628 }
3629
3630 /* Reclaim memory once firmware is successfully loaded */
3631 mwl8k_release_firmware(priv);
3632
3633 /*
3634 * Temporarily enable interrupts. Initial firmware host
3635 * commands use interrupts and avoids polling. Disable
3636 * interrupts when done.
3637 */
3638 priv->int_mask |= MWL8K_A2H_EVENTS;
3639
3640 iowrite32(priv->int_mask, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3641
3642 /* Get config data, mac addrs etc */
3643 rc = mwl8k_cmd_get_hw_spec(hw);
3644 if (rc) {
3645 printk(KERN_ERR "%s: Cannot initialise firmware\n", priv->name);
3646 goto err_stop_firmware;
3647 }
3648
3649 /* Turn radio off */
3650 rc = mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_DISABLE);
3651 if (rc) {
3652 printk(KERN_ERR "%s: Cannot disable\n", priv->name);
3653 goto err_stop_firmware;
3654 }
3655
3656 /* Disable interrupts */
3657 spin_lock_irq(&priv->tx_lock);
3658 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3659 spin_unlock_irq(&priv->tx_lock);
3660 free_irq(priv->pdev->irq, hw);
3661
3662 rc = ieee80211_register_hw(hw);
3663 if (rc) {
3664 printk(KERN_ERR "%s: Cannot register device\n", priv->name);
3665 goto err_stop_firmware;
3666 }
3667
3668 fw = (u8 *)&priv->fw_rev;
3669 printk(KERN_INFO "%s: 88W%u %s\n", priv->name, priv->part_num,
3670 MWL8K_DESC);
3671 printk(KERN_INFO "%s: Driver Ver:%s Firmware Ver:%u.%u.%u.%u\n",
3672 priv->name, MWL8K_VERSION, fw[3], fw[2], fw[1], fw[0]);
3673 printk(KERN_INFO "%s: MAC Address: %s\n", priv->name,
3674 print_mac(mac, hw->wiphy->perm_addr));
3675
3676 return 0;
3677
3678err_stop_firmware:
3679 mwl8k_hw_reset(priv);
3680 mwl8k_release_firmware(priv);
3681
3682err_free_irq:
3683 spin_lock_irq(&priv->tx_lock);
3684 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3685 spin_unlock_irq(&priv->tx_lock);
3686 free_irq(priv->pdev->irq, hw);
3687
3688err_free_queues:
3689 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3690 mwl8k_txq_deinit(hw, i);
3691 mwl8k_rxq_deinit(hw, 0);
3692
3693err_iounmap:
3694 if (priv->cookie != NULL)
3695 pci_free_consistent(priv->pdev, 4,
3696 priv->cookie, priv->cookie_dma);
3697
3698 if (priv->regs != NULL)
3699 pci_iounmap(pdev, priv->regs);
3700
3701 if (priv->config_wq != NULL)
3702 destroy_workqueue(priv->config_wq);
3703
3704 pci_set_drvdata(pdev, NULL);
3705 ieee80211_free_hw(hw);
3706
3707err_free_reg:
3708 pci_release_regions(pdev);
3709 pci_disable_device(pdev);
3710
3711 return rc;
3712}
3713
230f7af0 3714static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3715{
3716 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3717}
3718
230f7af0 3719static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3720{
3721 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3722 struct mwl8k_priv *priv;
3723 int i;
3724
3725 if (hw == NULL)
3726 return;
3727 priv = hw->priv;
3728
3729 ieee80211_stop_queues(hw);
3730
3731 /* Remove tx reclaim tasklet */
3732 tasklet_kill(&priv->tx_reclaim_task);
3733
3734 /* Stop config thread */
3735 destroy_workqueue(priv->config_wq);
3736
3737 /* Stop hardware */
3738 mwl8k_hw_reset(priv);
3739
3740 /* Return all skbs to mac80211 */
3741 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3742 mwl8k_txq_reclaim(hw, i, 1);
3743
3744 ieee80211_unregister_hw(hw);
3745
3746 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3747 mwl8k_txq_deinit(hw, i);
3748
3749 mwl8k_rxq_deinit(hw, 0);
3750
3751 pci_free_consistent(priv->pdev, 4,
3752 priv->cookie, priv->cookie_dma);
3753
3754 pci_iounmap(pdev, priv->regs);
3755 pci_set_drvdata(pdev, NULL);
3756 ieee80211_free_hw(hw);
3757 pci_release_regions(pdev);
3758 pci_disable_device(pdev);
3759}
3760
3761static struct pci_driver mwl8k_driver = {
3762 .name = MWL8K_NAME,
3763 .id_table = mwl8k_table,
3764 .probe = mwl8k_probe,
3765 .remove = __devexit_p(mwl8k_remove),
3766 .shutdown = __devexit_p(mwl8k_shutdown),
3767};
3768
3769static int __init mwl8k_init(void)
3770{
3771 return pci_register_driver(&mwl8k_driver);
3772}
3773
3774static void __exit mwl8k_exit(void)
3775{
3776 pci_unregister_driver(&mwl8k_driver);
3777}
3778
3779module_init(mwl8k_init);
3780module_exit(mwl8k_exit);
Motorola kernel-slsi