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mwl8k: use cond_resched() when loading firmware blocks
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
32 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
33 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
34 { }
35};
36MODULE_DEVICE_TABLE(pci, mwl8k_table);
37
a66098da
LB		 38/* Register definitions */
39#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 40#define MWL8K_MODE_STA 0x0000005a
41#define MWL8K_MODE_AP 0x000000a5
a66098da 42#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 43#define MWL8K_FWSTA_READY 0xf0f1f2f4
44#define MWL8K_FWAP_READY 0xf1f2f4a5
45#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 46#define MWL8K_HIU_SCRATCH 0x00000c40
47
48/* Host->device communications */
49#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 54#define MWL8K_H2A_INT_DUMMY (1 << 20)
55#define MWL8K_H2A_INT_RESET (1 << 15)
56#define MWL8K_H2A_INT_DOORBELL (1 << 1)
57#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 58
59/* Device->host communications */
60#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 65#define MWL8K_A2H_INT_DUMMY (1 << 20)
66#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
67#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
68#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
69#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
70#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
71#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
72#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
73#define MWL8K_A2H_INT_RX_READY (1 << 1)
74#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 75
76#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
77 MWL8K_A2H_INT_CHNL_SWITCHED | \
78 MWL8K_A2H_INT_QUEUE_EMPTY | \
79 MWL8K_A2H_INT_RADAR_DETECT | \
80 MWL8K_A2H_INT_RADIO_ON | \
81 MWL8K_A2H_INT_RADIO_OFF | \
82 MWL8K_A2H_INT_MAC_EVENT | \
83 MWL8K_A2H_INT_OPC_DONE | \
84 MWL8K_A2H_INT_RX_READY | \
85 MWL8K_A2H_INT_TX_DONE)
86
87/* WME stream classes */
88#define WME_AC_BE 0 /* best effort */
89#define WME_AC_BK 1 /* background */
90#define WME_AC_VI 2 /* video */
91#define WME_AC_VO 3 /* voice */
92
93#define MWL8K_RX_QUEUES 1
94#define MWL8K_TX_QUEUES 4
95
96struct mwl8k_rx_queue {
97 int rx_desc_count;
98
99 /* hw receives here */
100 int rx_head;
101
102 /* refill descs here */
103 int rx_tail;
104
105 struct mwl8k_rx_desc *rx_desc_area;
106 dma_addr_t rx_desc_dma;
107 struct sk_buff **rx_skb;
108};
109
a66098da
LB		 110struct mwl8k_tx_queue {
111 /* hw transmits here */
112 int tx_head;
113
114 /* sw appends here */
115 int tx_tail;
116
117 struct ieee80211_tx_queue_stats tx_stats;
118 struct mwl8k_tx_desc *tx_desc_area;
119 dma_addr_t tx_desc_dma;
76266b2a 120 struct sk_buff **tx_skb;
a66098da
LB		 121};
122
123/* Pointers to the firmware data and meta information about it. */
124struct mwl8k_firmware {
125 /* Microcode */
126 struct firmware *ucode;
127
128 /* Boot helper code */
129 struct firmware *helper;
130};
131
132struct mwl8k_priv {
133 void __iomem *regs;
134 struct ieee80211_hw *hw;
135
136 struct pci_dev *pdev;
a66098da
LB		 137
138 /* firmware files and meta data */
139 struct mwl8k_firmware fw;
140 u32 part_num;
141
618952a7
LB		 142 /* firmware access */
143 struct mutex fw_mutex;
144 struct task_struct *fw_mutex_owner;
145 int fw_mutex_depth;
618952a7
LB		 146 struct completion *hostcmd_wait;
147
a66098da
LB		 148 /* lock held over TX and TX reap */
149 spinlock_t tx_lock;
a66098da 150
88de754a
LB		 151 /* TX quiesce completion, protected by fw_mutex and tx_lock */
152 struct completion *tx_wait;
153
a66098da 154 struct ieee80211_vif *vif;
a66098da
LB		 155
156 struct ieee80211_channel *current_channel;
157
158 /* power management status cookie from firmware */
159 u32 *cookie;
160 dma_addr_t cookie_dma;
161
162 u16 num_mcaddrs;
a66098da 163 u8 hw_rev;
2aa7b01f 164 u32 fw_rev;
a66098da
LB		 165
166 /*
167 * Running count of TX packets in flight, to avoid
168 * iterating over the transmit rings each time.
169 */
170 int pending_tx_pkts;
171
172 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
173 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
174
175 /* PHY parameters */
176 struct ieee80211_supported_band band;
177 struct ieee80211_channel channels[14];
178 struct ieee80211_rate rates[12];
179
c46563b7 180 bool radio_on;
68ce3884 181 bool radio_short_preamble;
0439b1f5 182 bool wmm_enabled;
a66098da 183
a66098da
LB		 184 /* XXX need to convert this to handle multiple interfaces */
185 bool capture_beacon;
d89173f2 186 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 187 struct sk_buff *beacon_skb;
188
189 /*
190 * This FJ worker has to be global as it is scheduled from the
191 * RX handler. At this point we don't know which interface it
192 * belongs to until the list of bssids waiting to complete join
193 * is checked.
194 */
195 struct work_struct finalize_join_worker;
196
197 /* Tasklet to reclaim TX descriptors and buffers after tx */
198 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 199};
200
201/* Per interface specific private data */
202struct mwl8k_vif {
a66098da
LB		 203 /* backpointer to parent config block */
204 struct mwl8k_priv *priv;
205
206 /* BSS config of AP or IBSS from mac80211*/
207 struct ieee80211_bss_conf bss_info;
208
209 /* BSSID of AP or IBSS */
d89173f2
LB		 210 u8 bssid[ETH_ALEN];
211 u8 mac_addr[ETH_ALEN];
a66098da
LB		 212
213 /*
214 * Subset of supported legacy rates.
215 * Intersection of AP and STA supported rates.
216 */
217 struct ieee80211_rate legacy_rates[12];
218
219 /* number of supported legacy rates */
220 u8 legacy_nrates;
221
a66098da
LB		 222 /* Index into station database.Returned by update_sta_db call */
223 u8 peer_id;
224
225 /* Non AMPDU sequence number assigned by driver */
226 u16 seqno;
a66098da
LB		 227};
228
a94cc97e 229#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 230
231static const struct ieee80211_channel mwl8k_channels[] = {
232 { .center_freq = 2412, .hw_value = 1, },
233 { .center_freq = 2417, .hw_value = 2, },
234 { .center_freq = 2422, .hw_value = 3, },
235 { .center_freq = 2427, .hw_value = 4, },
236 { .center_freq = 2432, .hw_value = 5, },
237 { .center_freq = 2437, .hw_value = 6, },
238 { .center_freq = 2442, .hw_value = 7, },
239 { .center_freq = 2447, .hw_value = 8, },
240 { .center_freq = 2452, .hw_value = 9, },
241 { .center_freq = 2457, .hw_value = 10, },
242 { .center_freq = 2462, .hw_value = 11, },
243};
244
245static const struct ieee80211_rate mwl8k_rates[] = {
246 { .bitrate = 10, .hw_value = 2, },
247 { .bitrate = 20, .hw_value = 4, },
248 { .bitrate = 55, .hw_value = 11, },
249 { .bitrate = 60, .hw_value = 12, },
250 { .bitrate = 90, .hw_value = 18, },
251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 120, .hw_value = 24, },
253 { .bitrate = 180, .hw_value = 36, },
254 { .bitrate = 240, .hw_value = 48, },
255 { .bitrate = 360, .hw_value = 72, },
256 { .bitrate = 480, .hw_value = 96, },
257 { .bitrate = 540, .hw_value = 108, },
258};
259
a66098da
LB		 260/* Set or get info from Firmware */
261#define MWL8K_CMD_SET 0x0001
262#define MWL8K_CMD_GET 0x0000
263
264/* Firmware command codes */
265#define MWL8K_CMD_CODE_DNLD 0x0001
266#define MWL8K_CMD_GET_HW_SPEC 0x0003
267#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
268#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 269#define MWL8K_CMD_RADIO_CONTROL 0x001c
270#define MWL8K_CMD_RF_TX_POWER 0x001e
a66098da
LB		 271#define MWL8K_CMD_SET_PRE_SCAN 0x0107
272#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 273#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
274#define MWL8K_CMD_SET_AID 0x010d
275#define MWL8K_CMD_SET_RATE 0x0110
276#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
277#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 278#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 279#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
280#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 281#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 282#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 283#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 284#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 285#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 286#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 287
288static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
289{
290#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
291 snprintf(buf, bufsize, "%s", #x);\
292 return buf;\
293 } while (0)
ce9e2e1b 294 switch (cmd & ~0x8000) {
a66098da
LB		 295 MWL8K_CMDNAME(CODE_DNLD);
296 MWL8K_CMDNAME(GET_HW_SPEC);
297 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
298 MWL8K_CMDNAME(GET_STAT);
299 MWL8K_CMDNAME(RADIO_CONTROL);
300 MWL8K_CMDNAME(RF_TX_POWER);
301 MWL8K_CMDNAME(SET_PRE_SCAN);
302 MWL8K_CMDNAME(SET_POST_SCAN);
303 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 304 MWL8K_CMDNAME(SET_AID);
305 MWL8K_CMDNAME(SET_RATE);
306 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
307 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 308 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 309 MWL8K_CMDNAME(SET_EDCA_PARAMS);
310 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 311 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 312 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 313 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 314 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 315 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 316 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 317 default:
318 snprintf(buf, bufsize, "0x%x", cmd);
319 }
320#undef MWL8K_CMDNAME
321
322 return buf;
323}
324
325/* Hardware and firmware reset */
326static void mwl8k_hw_reset(struct mwl8k_priv *priv)
327{
328 iowrite32(MWL8K_H2A_INT_RESET,
329 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
330 iowrite32(MWL8K_H2A_INT_RESET,
331 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
332 msleep(20);
333}
334
335/* Release fw image */
336static void mwl8k_release_fw(struct firmware **fw)
337{
338 if (*fw == NULL)
339 return;
340 release_firmware(*fw);
341 *fw = NULL;
342}
343
344static void mwl8k_release_firmware(struct mwl8k_priv *priv)
345{
346 mwl8k_release_fw(&priv->fw.ucode);
347 mwl8k_release_fw(&priv->fw.helper);
348}
349
350/* Request fw image */
351static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 352 const char *fname, struct firmware **fw)
a66098da
LB		 353{
354 /* release current image */
355 if (*fw != NULL)
356 mwl8k_release_fw(fw);
357
358 return request_firmware((const struct firmware **)fw,
c2c357ce 359 fname, &priv->pdev->dev);
a66098da
LB		 360}
361
362static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
363{
364 u8 filename[64];
365 int rc;
366
367 priv->part_num = part_num;
368
369 snprintf(filename, sizeof(filename),
370 "mwl8k/helper_%u.fw", priv->part_num);
371
372 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
373 if (rc) {
c2c357ce
LB		 374 printk(KERN_ERR "%s: Error requesting helper firmware "
375 "file %s\n", pci_name(priv->pdev), filename);
a66098da
LB		 376 return rc;
377 }
378
379 snprintf(filename, sizeof(filename),
380 "mwl8k/fmimage_%u.fw", priv->part_num);
381
382 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
383 if (rc) {
c2c357ce
LB		 384 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
385 pci_name(priv->pdev), filename);
a66098da
LB		 386 mwl8k_release_fw(&priv->fw.helper);
387 return rc;
388 }
389
390 return 0;
391}
392
393struct mwl8k_cmd_pkt {
394 __le16 code;
395 __le16 length;
396 __le16 seq_num;
397 __le16 result;
398 char payload[0];
399} __attribute__((packed));
400
401/*
402 * Firmware loading.
403 */
404static int
405mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
406{
407 void __iomem *regs = priv->regs;
408 dma_addr_t dma_addr;
a66098da
LB		 409 int loops;
410
411 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
412 if (pci_dma_mapping_error(priv->pdev, dma_addr))
413 return -ENOMEM;
414
415 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
416 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
417 iowrite32(MWL8K_H2A_INT_DOORBELL,
418 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
419 iowrite32(MWL8K_H2A_INT_DUMMY,
420 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
421
a66098da
LB		 422 loops = 1000;
423 do {
424 u32 int_code;
425
426 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
427 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
428 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 429 break;
430 }
431
3d76e82c 432 cond_resched();
a66098da
LB		 433 udelay(1);
434 } while (--loops);
435
436 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
437
d4b70570 438 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 439}
440
441static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
442 const u8 *data, size_t length)
443{
444 struct mwl8k_cmd_pkt *cmd;
445 int done;
446 int rc = 0;
447
448 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
449 if (cmd == NULL)
450 return -ENOMEM;
451
452 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
453 cmd->seq_num = 0;
454 cmd->result = 0;
455
456 done = 0;
457 while (length) {
458 int block_size = length > 256 ? 256 : length;
459
460 memcpy(cmd->payload, data + done, block_size);
461 cmd->length = cpu_to_le16(block_size);
462
463 rc = mwl8k_send_fw_load_cmd(priv, cmd,
464 sizeof(*cmd) + block_size);
465 if (rc)
466 break;
467
468 done += block_size;
469 length -= block_size;
470 }
471
472 if (!rc) {
473 cmd->length = 0;
474 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
475 }
476
477 kfree(cmd);
478
479 return rc;
480}
481
482static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
483 const u8 *data, size_t length)
484{
485 unsigned char *buffer;
486 int may_continue, rc = 0;
487 u32 done, prev_block_size;
488
489 buffer = kmalloc(1024, GFP_KERNEL);
490 if (buffer == NULL)
491 return -ENOMEM;
492
493 done = 0;
494 prev_block_size = 0;
495 may_continue = 1000;
496 while (may_continue > 0) {
497 u32 block_size;
498
499 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
500 if (block_size & 1) {
501 block_size &= ~1;
502 may_continue--;
503 } else {
504 done += prev_block_size;
505 length -= prev_block_size;
506 }
507
508 if (block_size > 1024 || block_size > length) {
509 rc = -EOVERFLOW;
510 break;
511 }
512
513 if (length == 0) {
514 rc = 0;
515 break;
516 }
517
518 if (block_size == 0) {
519 rc = -EPROTO;
520 may_continue--;
521 udelay(1);
522 continue;
523 }
524
525 prev_block_size = block_size;
526 memcpy(buffer, data + done, block_size);
527
528 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
529 if (rc)
530 break;
531 }
532
533 if (!rc && length != 0)
534 rc = -EREMOTEIO;
535
536 kfree(buffer);
537
538 return rc;
539}
540
c2c357ce 541static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 542{
c2c357ce
LB		 543 struct mwl8k_priv *priv = hw->priv;
544 struct firmware *fw = priv->fw.ucode;
545 int rc;
546 int loops;
547
548 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
549 struct firmware *helper = priv->fw.helper;
a66098da 550
c2c357ce
LB		 551 if (helper == NULL) {
552 printk(KERN_ERR "%s: helper image needed but none "
553 "given\n", pci_name(priv->pdev));
554 return -EINVAL;
555 }
a66098da 556
c2c357ce 557 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 558 if (rc) {
559 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 560 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 561 return rc;
562 }
563 msleep(1);
564
c2c357ce 565 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 566 } else {
c2c357ce 567 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 568 }
569
570 if (rc) {
c2c357ce
LB		 571 printk(KERN_ERR "%s: unable to load firmware image\n",
572 pci_name(priv->pdev));
a66098da
LB		 573 return rc;
574 }
575
576 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
577 msleep(1);
578
579 loops = 200000;
580 do {
581 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
582 == MWL8K_FWSTA_READY)
583 break;
584 udelay(1);
585 } while (--loops);
586
587 return loops ? 0 : -ETIMEDOUT;
588}
589
590
591/*
592 * Defines shared between transmission and reception.
593 */
594/* HT control fields for firmware */
595struct ewc_ht_info {
596 __le16 control1;
597 __le16 control2;
598 __le16 control3;
599} __attribute__((packed));
600
601/* Firmware Station database operations */
602#define MWL8K_STA_DB_ADD_ENTRY 0
603#define MWL8K_STA_DB_MODIFY_ENTRY 1
604#define MWL8K_STA_DB_DEL_ENTRY 2
605#define MWL8K_STA_DB_FLUSH 3
606
607/* Peer Entry flags - used to define the type of the peer node */
608#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da
LB		 609
610#define MWL8K_IEEE_LEGACY_DATA_RATES 12
611#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 612
613struct peer_capability_info {
614 /* Peer type - AP vs. STA. */
615 __u8 peer_type;
616
617 /* Basic 802.11 capabilities from assoc resp. */
618 __le16 basic_caps;
619
620 /* Set if peer supports 802.11n high throughput (HT). */
621 __u8 ht_support;
622
623 /* Valid if HT is supported. */
624 __le16 ht_caps;
625 __u8 extended_ht_caps;
626 struct ewc_ht_info ewc_info;
627
628 /* Legacy rate table. Intersection of our rates and peer rates. */
629 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
630
631 /* HT rate table. Intersection of our rates and peer rates. */
632 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 633 __u8 pad[16];
a66098da
LB		 634
635 /* If set, interoperability mode, no proprietary extensions. */
636 __u8 interop;
637 __u8 pad2;
638 __u8 station_id;
639 __le16 amsdu_enabled;
640} __attribute__((packed));
641
642/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 643static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
644{
645 u16 val_mask = 1 << 4;
646
647 /* End of Service Period Bit 4 */
648 return qos | val_mask;
649}
650
651static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
652{
653 u16 val_mask = 0x3;
654 u8 shift = 5;
655 u16 qos_mask = ~(val_mask << shift);
656
657 /* Ack Policy Bit 5-6 */
658 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
659}
660
661static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
662{
663 u16 val_mask = 1 << 7;
664
665 /* AMSDU present Bit 7 */
666 return qos | val_mask;
667}
668
669static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
670{
671 u16 val_mask = 0xff;
672 u8 shift = 8;
673 u16 qos_mask = ~(val_mask << shift);
674
675 /* Queue Length Bits 8-15 */
676 return (qos & qos_mask) | ((len & val_mask) << shift);
677}
678
679/* DMA header used by firmware and hardware. */
680struct mwl8k_dma_data {
681 __le16 fwlen;
682 struct ieee80211_hdr wh;
683} __attribute__((packed));
684
685/* Routines to add/remove DMA header from skb. */
76266b2a 686static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
a66098da 687{
76266b2a 688 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
a66098da 689 void *dst, *src = &tr->wh;
76266b2a 690 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
a66098da
LB		 691 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
692
693 dst = (void *)tr + space;
694 if (dst != src) {
695 memmove(dst, src, hdrlen);
696 skb_pull(skb, space);
697 }
a66098da
LB		 698}
699
76266b2a 700static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 701{
702 struct ieee80211_hdr *wh;
703 u32 hdrlen, pktlen;
704 struct mwl8k_dma_data *tr;
705
706 wh = (struct ieee80211_hdr *)skb->data;
707 hdrlen = ieee80211_hdrlen(wh->frame_control);
708 pktlen = skb->len;
709
710 /*
711 * Copy up/down the 802.11 header; the firmware requires
712 * we present a 2-byte payload length followed by a
713 * 4-address header (w/o QoS), followed (optionally) by
714 * any WEP/ExtIV header (but only filled in for CCMP).
715 */
716 if (hdrlen != sizeof(struct mwl8k_dma_data))
717 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
718
719 tr = (struct mwl8k_dma_data *)skb->data;
720 if (wh != &tr->wh)
721 memmove(&tr->wh, wh, hdrlen);
722
723 /* Clear addr4 */
d89173f2 724 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 725
726 /*
727 * Firmware length is the length of the fully formed "802.11
728 * payload". That is, everything except for the 802.11 header.
729 * This includes all crypto material including the MIC.
730 */
731 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 732}
733
734
735/*
736 * Packet reception.
737 */
a66098da 738#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
a66098da
LB		 739
740struct mwl8k_rx_desc {
741 __le16 pkt_len;
742 __u8 link_quality;
743 __u8 noise_level;
744 __le32 pkt_phys_addr;
745 __le32 next_rx_desc_phys_addr;
746 __le16 qos_control;
747 __le16 rate_info;
748 __le32 pad0[4];
749 __u8 rssi;
750 __u8 channel;
751 __le16 pad1;
752 __u8 rx_ctrl;
753 __u8 rx_status;
754 __u8 pad2[2];
755} __attribute__((packed));
756
757#define MWL8K_RX_DESCS 256
758#define MWL8K_RX_MAXSZ 3800
759
760static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
761{
762 struct mwl8k_priv *priv = hw->priv;
763 struct mwl8k_rx_queue *rxq = priv->rxq + index;
764 int size;
765 int i;
766
767 rxq->rx_desc_count = 0;
768 rxq->rx_head = 0;
769 rxq->rx_tail = 0;
770
771 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
772
773 rxq->rx_desc_area =
774 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
775 if (rxq->rx_desc_area == NULL) {
776 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 777 wiphy_name(hw->wiphy));
a66098da
LB		 778 return -ENOMEM;
779 }
780 memset(rxq->rx_desc_area, 0, size);
781
782 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
783 sizeof(*rxq->rx_skb), GFP_KERNEL);
784 if (rxq->rx_skb == NULL) {
785 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 786 wiphy_name(hw->wiphy));
a66098da
LB		 787 pci_free_consistent(priv->pdev, size,
788 rxq->rx_desc_area, rxq->rx_desc_dma);
789 return -ENOMEM;
790 }
791 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
792
793 for (i = 0; i < MWL8K_RX_DESCS; i++) {
794 struct mwl8k_rx_desc *rx_desc;
795 int nexti;
796
797 rx_desc = rxq->rx_desc_area + i;
798 nexti = (i + 1) % MWL8K_RX_DESCS;
799
800 rx_desc->next_rx_desc_phys_addr =
801 cpu_to_le32(rxq->rx_desc_dma
802 + nexti * sizeof(*rx_desc));
c491bf12 803 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
a66098da
LB		 804 }
805
806 return 0;
807}
808
809static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
810{
811 struct mwl8k_priv *priv = hw->priv;
812 struct mwl8k_rx_queue *rxq = priv->rxq + index;
813 int refilled;
814
815 refilled = 0;
816 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
817 struct sk_buff *skb;
818 int rx;
819
820 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
821 if (skb == NULL)
822 break;
823
824 rxq->rx_desc_count++;
825
826 rx = rxq->rx_tail;
827 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
828
829 rxq->rx_desc_area[rx].pkt_phys_addr =
830 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
831 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
832
833 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
834 rxq->rx_skb[rx] = skb;
835 wmb();
836 rxq->rx_desc_area[rx].rx_ctrl = 0;
837
838 refilled++;
839 }
840
841 return refilled;
842}
843
844/* Must be called only when the card's reception is completely halted */
845static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
846{
847 struct mwl8k_priv *priv = hw->priv;
848 struct mwl8k_rx_queue *rxq = priv->rxq + index;
849 int i;
850
851 for (i = 0; i < MWL8K_RX_DESCS; i++) {
852 if (rxq->rx_skb[i] != NULL) {
853 unsigned long addr;
854
855 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
856 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
857 PCI_DMA_FROMDEVICE);
858 kfree_skb(rxq->rx_skb[i]);
859 rxq->rx_skb[i] = NULL;
860 }
861 }
862
863 kfree(rxq->rx_skb);
864 rxq->rx_skb = NULL;
865
866 pci_free_consistent(priv->pdev,
867 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
868 rxq->rx_desc_area, rxq->rx_desc_dma);
869 rxq->rx_desc_area = NULL;
870}
871
872
873/*
874 * Scan a list of BSSIDs to process for finalize join.
875 * Allows for extension to process multiple BSSIDs.
876 */
877static inline int
878mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
879{
880 return priv->capture_beacon &&
881 ieee80211_is_beacon(wh->frame_control) &&
882 !compare_ether_addr(wh->addr3, priv->capture_bssid);
883}
884
3779752d
LB		 885static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
886 struct sk_buff *skb)
a66098da 887{
3779752d
LB		 888 struct mwl8k_priv *priv = hw->priv;
889
a66098da 890 priv->capture_beacon = false;
d89173f2 891 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 892
893 /*
894 * Use GFP_ATOMIC as rxq_process is called from
895 * the primary interrupt handler, memory allocation call
896 * must not sleep.
897 */
898 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
899 if (priv->beacon_skb != NULL)
3779752d 900 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 901}
902
903static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
904{
905 struct mwl8k_priv *priv = hw->priv;
906 struct mwl8k_rx_queue *rxq = priv->rxq + index;
907 int processed;
908
909 processed = 0;
910 while (rxq->rx_desc_count && limit--) {
911 struct mwl8k_rx_desc *rx_desc;
912 struct sk_buff *skb;
913 struct ieee80211_rx_status status;
914 unsigned long addr;
915 struct ieee80211_hdr *wh;
916
917 rx_desc = rxq->rx_desc_area + rxq->rx_head;
918 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
919 break;
920 rmb();
921
922 skb = rxq->rx_skb[rxq->rx_head];
d25f9f13
LB		 923 if (skb == NULL)
924 break;
a66098da
LB		 925 rxq->rx_skb[rxq->rx_head] = NULL;
926
927 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
928 rxq->rx_desc_count--;
929
930 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
931 pci_unmap_single(priv->pdev, addr,
932 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
933
934 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
76266b2a 935 mwl8k_remove_dma_header(skb);
a66098da
LB		 936
937 wh = (struct ieee80211_hdr *)skb->data;
938
939 /*
c2c357ce
LB		 940 * Check for a pending join operation. Save a
941 * copy of the beacon and schedule a tasklet to
942 * send a FINALIZE_JOIN command to the firmware.
a66098da
LB		 943 */
944 if (mwl8k_capture_bssid(priv, wh))
3779752d 945 mwl8k_save_beacon(hw, skb);
a66098da
LB		 946
947 memset(&status, 0, sizeof(status));
948 status.mactime = 0;
949 status.signal = -rx_desc->rssi;
950 status.noise = -rx_desc->noise_level;
951 status.qual = rx_desc->link_quality;
952 status.antenna = 1;
953 status.rate_idx = 1;
954 status.flag = 0;
955 status.band = IEEE80211_BAND_2GHZ;
956 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
f1d58c25
JB		 957 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
958 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 959
960 processed++;
961 }
962
963 return processed;
964}
965
966
967/*
968 * Packet transmission.
969 */
970
971/* Transmit queue assignment. */
972enum {
973 MWL8K_WME_AC_BK = 0, /* background access */
974 MWL8K_WME_AC_BE = 1, /* best effort access */
975 MWL8K_WME_AC_VI = 2, /* video access */
976 MWL8K_WME_AC_VO = 3, /* voice access */
977};
978
979/* Transmit packet ACK policy */
980#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 981#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
982
983#define GET_TXQ(_ac) (\
984 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
985 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
986 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
987 MWL8K_WME_AC_BE)
988
a66098da
LB		 989#define MWL8K_TXD_STATUS_OK 0x00000001
990#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
991#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
992#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 993#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 994
995struct mwl8k_tx_desc {
996 __le32 status;
997 __u8 data_rate;
998 __u8 tx_priority;
999 __le16 qos_control;
1000 __le32 pkt_phys_addr;
1001 __le16 pkt_len;
d89173f2 1002 __u8 dest_MAC_addr[ETH_ALEN];
a66098da
LB		 1003 __le32 next_tx_desc_phys_addr;
1004 __le32 reserved;
1005 __le16 rate_info;
1006 __u8 peer_id;
1007 __u8 tx_frag_cnt;
1008} __attribute__((packed));
1009
1010#define MWL8K_TX_DESCS 128
1011
1012static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1013{
1014 struct mwl8k_priv *priv = hw->priv;
1015 struct mwl8k_tx_queue *txq = priv->txq + index;
1016 int size;
1017 int i;
1018
ce9e2e1b 1019 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
a66098da
LB		 1020 txq->tx_stats.limit = MWL8K_TX_DESCS;
1021 txq->tx_head = 0;
1022 txq->tx_tail = 0;
1023
1024 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1025
1026 txq->tx_desc_area =
1027 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1028 if (txq->tx_desc_area == NULL) {
1029 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1030 wiphy_name(hw->wiphy));
a66098da
LB		 1031 return -ENOMEM;
1032 }
1033 memset(txq->tx_desc_area, 0, size);
1034
1035 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1036 GFP_KERNEL);
1037 if (txq->tx_skb == NULL) {
1038 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1039 wiphy_name(hw->wiphy));
a66098da
LB		 1040 pci_free_consistent(priv->pdev, size,
1041 txq->tx_desc_area, txq->tx_desc_dma);
1042 return -ENOMEM;
1043 }
1044 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1045
1046 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1047 struct mwl8k_tx_desc *tx_desc;
1048 int nexti;
1049
1050 tx_desc = txq->tx_desc_area + i;
1051 nexti = (i + 1) % MWL8K_TX_DESCS;
1052
1053 tx_desc->status = 0;
1054 tx_desc->next_tx_desc_phys_addr =
1055 cpu_to_le32(txq->tx_desc_dma +
1056 nexti * sizeof(*tx_desc));
1057 }
1058
1059 return 0;
1060}
1061
1062static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1063{
1064 iowrite32(MWL8K_H2A_INT_PPA_READY,
1065 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1066 iowrite32(MWL8K_H2A_INT_DUMMY,
1067 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1068 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1069}
1070
a66098da
LB		 1071struct mwl8k_txq_info {
1072 u32 fw_owned;
1073 u32 drv_owned;
1074 u32 unused;
1075 u32 len;
1076 u32 head;
1077 u32 tail;
1078};
1079
1080static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1081 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1082{
1083 int count, desc, status;
1084 struct mwl8k_tx_queue *txq;
1085 struct mwl8k_tx_desc *tx_desc;
1086 int ndescs = 0;
1087
c3f967d3
LB		 1088 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1089
c3f967d3 1090 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da
LB		 1091 txq = priv->txq + count;
1092 txinfo[count].len = txq->tx_stats.len;
1093 txinfo[count].head = txq->tx_head;
1094 txinfo[count].tail = txq->tx_tail;
1095 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1096 tx_desc = txq->tx_desc_area + desc;
1097 status = le32_to_cpu(tx_desc->status);
1098
1099 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1100 txinfo[count].fw_owned++;
1101 else
1102 txinfo[count].drv_owned++;
1103
1104 if (tx_desc->pkt_len == 0)
1105 txinfo[count].unused++;
1106 }
1107 }
a66098da
LB		 1108
1109 return ndescs;
1110}
1111
618952a7 1112/*
88de754a 1113 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1114 */
950d5b01 1115static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1116{
a66098da 1117 struct mwl8k_priv *priv = hw->priv;
88de754a 1118 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1119 u32 count;
1120 unsigned long timeout;
a66098da
LB		 1121
1122 might_sleep();
1123
a66098da 1124 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1125 count = priv->pending_tx_pkts;
1126 if (count)
1127 priv->tx_wait = &tx_wait;
a66098da
LB		 1128 spin_unlock_bh(&priv->tx_lock);
1129
1130 if (count) {
c3f967d3 1131 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1132 int index;
1133 int newcount;
1134
88de754a 1135 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1136 msecs_to_jiffies(5000));
a66098da
LB		 1137 if (timeout)
1138 return 0;
1139
1140 spin_lock_bh(&priv->tx_lock);
1141 priv->tx_wait = NULL;
88de754a
LB		 1142 newcount = priv->pending_tx_pkts;
1143 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1144 spin_unlock_bh(&priv->tx_lock);
1145
618952a7 1146 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1147 __func__, __LINE__, count, newcount);
a66098da 1148
c3f967d3 1149 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1150 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1151 "DRV:%u U:%u\n",
a66098da
LB		 1152 index,
1153 txinfo[index].len,
1154 txinfo[index].head,
1155 txinfo[index].tail,
1156 txinfo[index].fw_owned,
1157 txinfo[index].drv_owned,
1158 txinfo[index].unused);
ce9e2e1b 1159
a66098da
LB		 1160 return -ETIMEDOUT;
1161 }
1162
1163 return 0;
1164}
1165
c23b5a69
LB		 1166#define MWL8K_TXD_SUCCESS(status) \
1167 ((status) & (MWL8K_TXD_STATUS_OK | \
1168 MWL8K_TXD_STATUS_OK_RETRY | \
1169 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1170
1171static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1172{
1173 struct mwl8k_priv *priv = hw->priv;
1174 struct mwl8k_tx_queue *txq = priv->txq + index;
1175 int wake = 0;
1176
1177 while (txq->tx_stats.len > 0) {
1178 int tx;
a66098da
LB		 1179 struct mwl8k_tx_desc *tx_desc;
1180 unsigned long addr;
ce9e2e1b 1181 int size;
a66098da
LB		 1182 struct sk_buff *skb;
1183 struct ieee80211_tx_info *info;
1184 u32 status;
1185
a66098da
LB		 1186 tx = txq->tx_head;
1187 tx_desc = txq->tx_desc_area + tx;
1188
1189 status = le32_to_cpu(tx_desc->status);
1190
1191 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1192 if (!force)
1193 break;
1194 tx_desc->status &=
1195 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1196 }
1197
1198 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1199 BUG_ON(txq->tx_stats.len == 0);
1200 txq->tx_stats.len--;
1201 priv->pending_tx_pkts--;
1202
1203 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1204 size = le16_to_cpu(tx_desc->pkt_len);
76266b2a
LB		 1205 skb = txq->tx_skb[tx];
1206 txq->tx_skb[tx] = NULL;
a66098da
LB		 1207
1208 BUG_ON(skb == NULL);
1209 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1210
76266b2a 1211 mwl8k_remove_dma_header(skb);
a66098da
LB		 1212
1213 /* Mark descriptor as unused */
1214 tx_desc->pkt_phys_addr = 0;
1215 tx_desc->pkt_len = 0;
1216
a66098da
LB		 1217 info = IEEE80211_SKB_CB(skb);
1218 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1219 if (MWL8K_TXD_SUCCESS(status))
a66098da 1220 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1221
1222 ieee80211_tx_status_irqsafe(hw, skb);
1223
618952a7 1224 wake = 1;
a66098da
LB		 1225 }
1226
618952a7 1227 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1228 ieee80211_wake_queue(hw, index);
1229}
1230
1231/* must be called only when the card's transmit is completely halted */
1232static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1233{
1234 struct mwl8k_priv *priv = hw->priv;
1235 struct mwl8k_tx_queue *txq = priv->txq + index;
1236
1237 mwl8k_txq_reclaim(hw, index, 1);
1238
1239 kfree(txq->tx_skb);
1240 txq->tx_skb = NULL;
1241
1242 pci_free_consistent(priv->pdev,
1243 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1244 txq->tx_desc_area, txq->tx_desc_dma);
1245 txq->tx_desc_area = NULL;
1246}
1247
1248static int
1249mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1250{
1251 struct mwl8k_priv *priv = hw->priv;
1252 struct ieee80211_tx_info *tx_info;
23b33906 1253 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1254 struct ieee80211_hdr *wh;
1255 struct mwl8k_tx_queue *txq;
1256 struct mwl8k_tx_desc *tx;
a66098da 1257 dma_addr_t dma;
23b33906
LB		 1258 u32 txstatus;
1259 u8 txdatarate;
1260 u16 qos;
a66098da 1261
23b33906
LB		 1262 wh = (struct ieee80211_hdr *)skb->data;
1263 if (ieee80211_is_data_qos(wh->frame_control))
1264 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1265 else
1266 qos = 0;
a66098da 1267
76266b2a 1268 mwl8k_add_dma_header(skb);
23b33906 1269 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1270
1271 tx_info = IEEE80211_SKB_CB(skb);
1272 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1273
1274 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1275 u16 seqno = mwl8k_vif->seqno;
23b33906 1276
a66098da
LB		 1277 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1278 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1279 mwl8k_vif->seqno = seqno++ % 4096;
1280 }
1281
23b33906
LB		 1282 /* Setup firmware control bit fields for each frame type. */
1283 txstatus = 0;
1284 txdatarate = 0;
1285 if (ieee80211_is_mgmt(wh->frame_control) ||
1286 ieee80211_is_ctl(wh->frame_control)) {
1287 txdatarate = 0;
1288 qos = mwl8k_qos_setbit_eosp(qos);
1289 /* Set Queue size to unspecified */
1290 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1291 } else if (ieee80211_is_data(wh->frame_control)) {
1292 txdatarate = 1;
1293 if (is_multicast_ether_addr(wh->addr1))
1294 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1295
1296 /* Send pkt in an aggregate if AMPDU frame. */
1297 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1298 qos = mwl8k_qos_setbit_ack(qos,
1299 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1300 else
1301 qos = mwl8k_qos_setbit_ack(qos,
1302 MWL8K_TXD_ACK_POLICY_NORMAL);
1303
1304 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1305 qos = mwl8k_qos_setbit_amsdu(qos);
1306 }
a66098da
LB		 1307
1308 dma = pci_map_single(priv->pdev, skb->data,
1309 skb->len, PCI_DMA_TODEVICE);
1310
1311 if (pci_dma_mapping_error(priv->pdev, dma)) {
1312 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1313 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1314 dev_kfree_skb(skb);
a66098da
LB		 1315 return NETDEV_TX_OK;
1316 }
1317
23b33906 1318 spin_lock_bh(&priv->tx_lock);
a66098da 1319
23b33906 1320 txq = priv->txq + index;
a66098da 1321
23b33906
LB		 1322 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1323 txq->tx_skb[txq->tx_tail] = skb;
a66098da 1324
23b33906
LB		 1325 tx = txq->tx_desc_area + txq->tx_tail;
1326 tx->data_rate = txdatarate;
1327 tx->tx_priority = index;
a66098da 1328 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1329 tx->pkt_phys_addr = cpu_to_le32(dma);
1330 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1331 tx->rate_info = 0;
1332 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1333 wmb();
23b33906
LB		 1334 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1335
1336 txq->tx_stats.count++;
a66098da
LB		 1337 txq->tx_stats.len++;
1338 priv->pending_tx_pkts++;
a66098da 1339
23b33906 1340 txq->tx_tail++;
a66098da
LB		 1341 if (txq->tx_tail == MWL8K_TX_DESCS)
1342 txq->tx_tail = 0;
23b33906 1343
a66098da
LB		 1344 if (txq->tx_head == txq->tx_tail)
1345 ieee80211_stop_queue(hw, index);
1346
23b33906 1347 mwl8k_tx_start(priv);
a66098da
LB		 1348
1349 spin_unlock_bh(&priv->tx_lock);
1350
1351 return NETDEV_TX_OK;
1352}
1353
1354
618952a7
LB		 1355/*
1356 * Firmware access.
1357 *
1358 * We have the following requirements for issuing firmware commands:
1359 * - Some commands require that the packet transmit path is idle when
1360 * the command is issued. (For simplicity, we'll just quiesce the
1361 * transmit path for every command.)
1362 * - There are certain sequences of commands that need to be issued to
1363 * the hardware sequentially, with no other intervening commands.
1364 *
1365 * This leads to an implementation of a "firmware lock" as a mutex that
1366 * can be taken recursively, and which is taken by both the low-level
1367 * command submission function (mwl8k_post_cmd) as well as any users of
1368 * that function that require issuing of an atomic sequence of commands,
1369 * and quiesces the transmit path whenever it's taken.
1370 */
1371static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1372{
1373 struct mwl8k_priv *priv = hw->priv;
1374
1375 if (priv->fw_mutex_owner != current) {
1376 int rc;
1377
1378 mutex_lock(&priv->fw_mutex);
1379 ieee80211_stop_queues(hw);
1380
1381 rc = mwl8k_tx_wait_empty(hw);
1382 if (rc) {
1383 ieee80211_wake_queues(hw);
1384 mutex_unlock(&priv->fw_mutex);
1385
1386 return rc;
1387 }
1388
1389 priv->fw_mutex_owner = current;
1390 }
1391
1392 priv->fw_mutex_depth++;
1393
1394 return 0;
1395}
1396
1397static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1398{
1399 struct mwl8k_priv *priv = hw->priv;
1400
1401 if (!--priv->fw_mutex_depth) {
1402 ieee80211_wake_queues(hw);
1403 priv->fw_mutex_owner = NULL;
1404 mutex_unlock(&priv->fw_mutex);
1405 }
1406}
1407
1408
a66098da
LB		 1409/*
1410 * Command processing.
1411 */
1412
1413/* Timeout firmware commands after 2000ms */
1414#define MWL8K_CMD_TIMEOUT_MS 2000
1415
1416static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1417{
1418 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1419 struct mwl8k_priv *priv = hw->priv;
1420 void __iomem *regs = priv->regs;
1421 dma_addr_t dma_addr;
1422 unsigned int dma_size;
1423 int rc;
a66098da
LB		 1424 unsigned long timeout = 0;
1425 u8 buf[32];
1426
c2c357ce 1427 cmd->result = 0xffff;
a66098da
LB		 1428 dma_size = le16_to_cpu(cmd->length);
1429 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1430 PCI_DMA_BIDIRECTIONAL);
1431 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1432 return -ENOMEM;
1433
618952a7 1434 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1435 if (rc) {
1436 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1437 PCI_DMA_BIDIRECTIONAL);
618952a7 1438 return rc;
39a1e42e 1439 }
a66098da 1440
a66098da
LB		 1441 priv->hostcmd_wait = &cmd_wait;
1442 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1443 iowrite32(MWL8K_H2A_INT_DOORBELL,
1444 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1445 iowrite32(MWL8K_H2A_INT_DUMMY,
1446 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1447
1448 timeout = wait_for_completion_timeout(&cmd_wait,
1449 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1450
618952a7
LB		 1451 priv->hostcmd_wait = NULL;
1452
1453 mwl8k_fw_unlock(hw);
1454
37055bd4
LB		 1455 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1456 PCI_DMA_BIDIRECTIONAL);
1457
a66098da 1458 if (!timeout) {
a66098da 1459 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1460 wiphy_name(hw->wiphy),
a66098da
LB		 1461 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1462 MWL8K_CMD_TIMEOUT_MS);
1463 rc = -ETIMEDOUT;
1464 } else {
ce9e2e1b 1465 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1466 if (rc)
1467 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1468 wiphy_name(hw->wiphy),
a66098da 1469 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1470 le16_to_cpu(cmd->result));
a66098da
LB		 1471 }
1472
a66098da
LB		 1473 return rc;
1474}
1475
1476/*
1477 * GET_HW_SPEC.
1478 */
1479struct mwl8k_cmd_get_hw_spec {
1480 struct mwl8k_cmd_pkt header;
1481 __u8 hw_rev;
1482 __u8 host_interface;
1483 __le16 num_mcaddrs;
d89173f2 1484 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1485 __le16 region_code;
1486 __le32 fw_rev;
1487 __le32 ps_cookie;
1488 __le32 caps;
1489 __u8 mcs_bitmap[16];
1490 __le32 rx_queue_ptr;
1491 __le32 num_tx_queues;
1492 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1493 __le32 caps2;
1494 __le32 num_tx_desc_per_queue;
1495 __le32 total_rx_desc;
1496} __attribute__((packed));
1497
1498static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1499{
1500 struct mwl8k_priv *priv = hw->priv;
1501 struct mwl8k_cmd_get_hw_spec *cmd;
1502 int rc;
1503 int i;
1504
1505 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1506 if (cmd == NULL)
1507 return -ENOMEM;
1508
1509 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1510 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1511
1512 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1513 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1514 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
4ff6432e 1515 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da
LB		 1516 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1517 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
4ff6432e
LB		 1518 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1519 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1520
1521 rc = mwl8k_post_cmd(hw, &cmd->header);
1522
1523 if (!rc) {
1524 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1525 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1526 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1527 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1528 }
1529
1530 kfree(cmd);
1531 return rc;
1532}
1533
1534/*
1535 * CMD_MAC_MULTICAST_ADR.
1536 */
1537struct mwl8k_cmd_mac_multicast_adr {
1538 struct mwl8k_cmd_pkt header;
1539 __le16 action;
1540 __le16 numaddr;
ce9e2e1b 1541 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1542};
1543
d5e30845
LB		 1544#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1545#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1546#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1547#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1548
e81cd2d6 1549static struct mwl8k_cmd_pkt *
447ced07 1550__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1551 int mc_count, struct dev_addr_list *mclist)
a66098da 1552{
e81cd2d6 1553 struct mwl8k_priv *priv = hw->priv;
a66098da 1554 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1555 int size;
e81cd2d6 1556
447ced07 1557 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1558 allmulti = 1;
1559 mc_count = 0;
1560 }
e81cd2d6
LB		 1561
1562 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1563
e81cd2d6 1564 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1565 if (cmd == NULL)
e81cd2d6 1566 return NULL;
a66098da
LB		 1567
1568 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1569 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1570 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1571 MWL8K_ENABLE_RX_BROADCAST);
1572
1573 if (allmulti) {
1574 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1575 } else if (mc_count) {
1576 int i;
1577
1578 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1579 cmd->numaddr = cpu_to_le16(mc_count);
1580 for (i = 0; i < mc_count && mclist; i++) {
1581 if (mclist->da_addrlen != ETH_ALEN) {
1582 kfree(cmd);
1583 return NULL;
1584 }
1585 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1586 mclist = mclist->next;
a66098da 1587 }
a66098da
LB		 1588 }
1589
e81cd2d6 1590 return &cmd->header;
a66098da
LB		 1591}
1592
1593/*
1594 * CMD_802_11_GET_STAT.
1595 */
1596struct mwl8k_cmd_802_11_get_stat {
1597 struct mwl8k_cmd_pkt header;
a66098da
LB		 1598 __le32 stats[64];
1599} __attribute__((packed));
1600
1601#define MWL8K_STAT_ACK_FAILURE 9
1602#define MWL8K_STAT_RTS_FAILURE 12
1603#define MWL8K_STAT_FCS_ERROR 24
1604#define MWL8K_STAT_RTS_SUCCESS 11
1605
1606static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1607 struct ieee80211_low_level_stats *stats)
1608{
1609 struct mwl8k_cmd_802_11_get_stat *cmd;
1610 int rc;
1611
1612 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1613 if (cmd == NULL)
1614 return -ENOMEM;
1615
1616 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1617 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1618
1619 rc = mwl8k_post_cmd(hw, &cmd->header);
1620 if (!rc) {
1621 stats->dot11ACKFailureCount =
1622 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1623 stats->dot11RTSFailureCount =
1624 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1625 stats->dot11FCSErrorCount =
1626 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1627 stats->dot11RTSSuccessCount =
1628 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1629 }
1630 kfree(cmd);
1631
1632 return rc;
1633}
1634
1635/*
1636 * CMD_802_11_RADIO_CONTROL.
1637 */
1638struct mwl8k_cmd_802_11_radio_control {
1639 struct mwl8k_cmd_pkt header;
1640 __le16 action;
1641 __le16 control;
1642 __le16 radio_on;
1643} __attribute__((packed));
1644
c46563b7
LB		 1645static int
1646mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1647{
1648 struct mwl8k_priv *priv = hw->priv;
1649 struct mwl8k_cmd_802_11_radio_control *cmd;
1650 int rc;
1651
c46563b7 1652 if (enable == priv->radio_on && !force)
a66098da
LB		 1653 return 0;
1654
a66098da
LB		 1655 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1656 if (cmd == NULL)
1657 return -ENOMEM;
1658
1659 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1660 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1661 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1662 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1663 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1664
1665 rc = mwl8k_post_cmd(hw, &cmd->header);
1666 kfree(cmd);
1667
1668 if (!rc)
c46563b7 1669 priv->radio_on = enable;
a66098da
LB		 1670
1671 return rc;
1672}
1673
c46563b7
LB		 1674static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1675{
1676 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1677}
1678
1679static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1680{
1681 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1682}
1683
a66098da
LB		 1684static int
1685mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1686{
1687 struct mwl8k_priv *priv;
1688
1689 if (hw == NULL || hw->priv == NULL)
1690 return -EINVAL;
1691 priv = hw->priv;
1692
68ce3884 1693 priv->radio_short_preamble = short_preamble;
a66098da 1694
c46563b7 1695 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1696}
1697
1698/*
1699 * CMD_802_11_RF_TX_POWER.
1700 */
1701#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1702
1703struct mwl8k_cmd_802_11_rf_tx_power {
1704 struct mwl8k_cmd_pkt header;
1705 __le16 action;
1706 __le16 support_level;
1707 __le16 current_level;
1708 __le16 reserved;
1709 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1710} __attribute__((packed));
1711
1712static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1713{
1714 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1715 int rc;
1716
1717 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1718 if (cmd == NULL)
1719 return -ENOMEM;
1720
1721 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1722 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1723 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1724 cmd->support_level = cpu_to_le16(dBm);
1725
1726 rc = mwl8k_post_cmd(hw, &cmd->header);
1727 kfree(cmd);
1728
1729 return rc;
1730}
1731
1732/*
1733 * CMD_SET_PRE_SCAN.
1734 */
1735struct mwl8k_cmd_set_pre_scan {
1736 struct mwl8k_cmd_pkt header;
1737} __attribute__((packed));
1738
1739static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1740{
1741 struct mwl8k_cmd_set_pre_scan *cmd;
1742 int rc;
1743
1744 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1745 if (cmd == NULL)
1746 return -ENOMEM;
1747
1748 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1749 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1750
1751 rc = mwl8k_post_cmd(hw, &cmd->header);
1752 kfree(cmd);
1753
1754 return rc;
1755}
1756
1757/*
1758 * CMD_SET_POST_SCAN.
1759 */
1760struct mwl8k_cmd_set_post_scan {
1761 struct mwl8k_cmd_pkt header;
1762 __le32 isibss;
d89173f2 1763 __u8 bssid[ETH_ALEN];
a66098da
LB		 1764} __attribute__((packed));
1765
1766static int
ce9e2e1b 1767mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 1768{
1769 struct mwl8k_cmd_set_post_scan *cmd;
1770 int rc;
1771
1772 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1773 if (cmd == NULL)
1774 return -ENOMEM;
1775
1776 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1777 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1778 cmd->isibss = 0;
d89173f2 1779 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 1780
1781 rc = mwl8k_post_cmd(hw, &cmd->header);
1782 kfree(cmd);
1783
1784 return rc;
1785}
1786
1787/*
1788 * CMD_SET_RF_CHANNEL.
1789 */
1790struct mwl8k_cmd_set_rf_channel {
1791 struct mwl8k_cmd_pkt header;
1792 __le16 action;
1793 __u8 current_channel;
1794 __le32 channel_flags;
1795} __attribute__((packed));
1796
1797static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1798 struct ieee80211_channel *channel)
1799{
1800 struct mwl8k_cmd_set_rf_channel *cmd;
1801 int rc;
1802
1803 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1804 if (cmd == NULL)
1805 return -ENOMEM;
1806
1807 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1808 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1809 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1810 cmd->current_channel = channel->hw_value;
1811 if (channel->band == IEEE80211_BAND_2GHZ)
1812 cmd->channel_flags = cpu_to_le32(0x00000081);
1813 else
1814 cmd->channel_flags = cpu_to_le32(0x00000000);
1815
1816 rc = mwl8k_post_cmd(hw, &cmd->header);
1817 kfree(cmd);
1818
1819 return rc;
1820}
1821
1822/*
1823 * CMD_SET_SLOT.
1824 */
1825struct mwl8k_cmd_set_slot {
1826 struct mwl8k_cmd_pkt header;
1827 __le16 action;
1828 __u8 short_slot;
1829} __attribute__((packed));
1830
5539bb51 1831static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 1832{
1833 struct mwl8k_cmd_set_slot *cmd;
1834 int rc;
1835
1836 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1837 if (cmd == NULL)
1838 return -ENOMEM;
1839
1840 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1841 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1842 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 1843 cmd->short_slot = short_slot_time;
a66098da
LB		 1844
1845 rc = mwl8k_post_cmd(hw, &cmd->header);
1846 kfree(cmd);
1847
1848 return rc;
1849}
1850
1851/*
1852 * CMD_MIMO_CONFIG.
1853 */
1854struct mwl8k_cmd_mimo_config {
1855 struct mwl8k_cmd_pkt header;
1856 __le32 action;
1857 __u8 rx_antenna_map;
1858 __u8 tx_antenna_map;
1859} __attribute__((packed));
1860
1861static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1862{
1863 struct mwl8k_cmd_mimo_config *cmd;
1864 int rc;
1865
1866 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1867 if (cmd == NULL)
1868 return -ENOMEM;
1869
1870 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1871 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1872 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1873 cmd->rx_antenna_map = rx;
1874 cmd->tx_antenna_map = tx;
1875
1876 rc = mwl8k_post_cmd(hw, &cmd->header);
1877 kfree(cmd);
1878
1879 return rc;
1880}
1881
1882/*
1883 * CMD_ENABLE_SNIFFER.
1884 */
1885struct mwl8k_cmd_enable_sniffer {
1886 struct mwl8k_cmd_pkt header;
1887 __le32 action;
1888} __attribute__((packed));
1889
1890static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1891{
1892 struct mwl8k_cmd_enable_sniffer *cmd;
1893 int rc;
1894
1895 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1896 if (cmd == NULL)
1897 return -ENOMEM;
1898
1899 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1900 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 1901 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 1902
1903 rc = mwl8k_post_cmd(hw, &cmd->header);
1904 kfree(cmd);
1905
1906 return rc;
1907}
1908
32060e1b
LB		 1909/*
1910 * CMD_SET_MAC_ADDR.
1911 */
1912struct mwl8k_cmd_set_mac_addr {
1913 struct mwl8k_cmd_pkt header;
1914 __u8 mac_addr[ETH_ALEN];
1915} __attribute__((packed));
1916
1917static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1918{
1919 struct mwl8k_cmd_set_mac_addr *cmd;
1920 int rc;
1921
1922 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1923 if (cmd == NULL)
1924 return -ENOMEM;
1925
1926 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1927 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1928 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1929
1930 rc = mwl8k_post_cmd(hw, &cmd->header);
1931 kfree(cmd);
1932
1933 return rc;
1934}
1935
1936
a66098da 1937/*
ce9e2e1b 1938 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 1939 */
1940struct mwl8k_cmd_set_rate_adapt_mode {
1941 struct mwl8k_cmd_pkt header;
1942 __le16 action;
1943 __le16 mode;
1944} __attribute__((packed));
1945
1946static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1947{
1948 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1949 int rc;
1950
1951 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1952 if (cmd == NULL)
1953 return -ENOMEM;
1954
1955 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1956 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1957 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1958 cmd->mode = cpu_to_le16(mode);
1959
1960 rc = mwl8k_post_cmd(hw, &cmd->header);
1961 kfree(cmd);
1962
1963 return rc;
1964}
1965
1966/*
1967 * CMD_SET_WMM_MODE.
1968 */
1969struct mwl8k_cmd_set_wmm {
1970 struct mwl8k_cmd_pkt header;
1971 __le16 action;
1972} __attribute__((packed));
1973
1974static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1975{
1976 struct mwl8k_priv *priv = hw->priv;
1977 struct mwl8k_cmd_set_wmm *cmd;
1978 int rc;
1979
1980 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1981 if (cmd == NULL)
1982 return -ENOMEM;
1983
1984 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1985 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 1986 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 1987
1988 rc = mwl8k_post_cmd(hw, &cmd->header);
1989 kfree(cmd);
1990
1991 if (!rc)
0439b1f5 1992 priv->wmm_enabled = enable;
a66098da
LB		 1993
1994 return rc;
1995}
1996
1997/*
1998 * CMD_SET_RTS_THRESHOLD.
1999 */
2000struct mwl8k_cmd_rts_threshold {
2001 struct mwl8k_cmd_pkt header;
2002 __le16 action;
2003 __le16 threshold;
2004} __attribute__((packed));
2005
2006static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2007 u16 action, u16 threshold)
a66098da
LB		 2008{
2009 struct mwl8k_cmd_rts_threshold *cmd;
2010 int rc;
2011
2012 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2013 if (cmd == NULL)
2014 return -ENOMEM;
2015
2016 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2017 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2018 cmd->action = cpu_to_le16(action);
733d3067 2019 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2020
2021 rc = mwl8k_post_cmd(hw, &cmd->header);
2022 kfree(cmd);
2023
2024 return rc;
2025}
2026
2027/*
2028 * CMD_SET_EDCA_PARAMS.
2029 */
2030struct mwl8k_cmd_set_edca_params {
2031 struct mwl8k_cmd_pkt header;
2032
2033 /* See MWL8K_SET_EDCA_XXX below */
2034 __le16 action;
2035
2036 /* TX opportunity in units of 32 us */
2037 __le16 txop;
2038
2039 /* Log exponent of max contention period: 0...15*/
2040 __u8 log_cw_max;
2041
2042 /* Log exponent of min contention period: 0...15 */
2043 __u8 log_cw_min;
2044
2045 /* Adaptive interframe spacing in units of 32us */
2046 __u8 aifs;
2047
2048 /* TX queue to configure */
2049 __u8 txq;
2050} __attribute__((packed));
2051
a66098da
LB		 2052#define MWL8K_SET_EDCA_CW 0x01
2053#define MWL8K_SET_EDCA_TXOP 0x02
2054#define MWL8K_SET_EDCA_AIFS 0x04
2055
2056#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2057 MWL8K_SET_EDCA_TXOP | \
2058 MWL8K_SET_EDCA_AIFS)
2059
2060static int
2061mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2062 __u16 cw_min, __u16 cw_max,
2063 __u8 aifs, __u16 txop)
2064{
2065 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2066 int rc;
2067
2068 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2069 if (cmd == NULL)
2070 return -ENOMEM;
2071
a66098da
LB		 2072 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2073 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2074 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2075 cmd->txop = cpu_to_le16(txop);
ce9e2e1b
LB		 2076 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2077 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
a66098da
LB		 2078 cmd->aifs = aifs;
2079 cmd->txq = qnum;
2080
2081 rc = mwl8k_post_cmd(hw, &cmd->header);
2082 kfree(cmd);
2083
2084 return rc;
2085}
2086
2087/*
2088 * CMD_FINALIZE_JOIN.
2089 */
2090
2091/* FJ beacon buffer size is compiled into the firmware. */
2092#define MWL8K_FJ_BEACON_MAXLEN 128
2093
2094struct mwl8k_cmd_finalize_join {
2095 struct mwl8k_cmd_pkt header;
2096 __le32 sleep_interval; /* Number of beacon periods to sleep */
2097 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2098} __attribute__((packed));
2099
2100static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2101 __u16 framelen, __u16 dtim)
2102{
2103 struct mwl8k_cmd_finalize_join *cmd;
2104 struct ieee80211_mgmt *payload = frame;
2105 u16 hdrlen;
2106 u32 payload_len;
2107 int rc;
2108
2109 if (frame == NULL)
2110 return -EINVAL;
2111
2112 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2113 if (cmd == NULL)
2114 return -ENOMEM;
2115
2116 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2117 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2118 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2119
2120 hdrlen = ieee80211_hdrlen(payload->frame_control);
2121
2122 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2123
2124 /* XXX TBD Might just have to abort and return an error */
2125 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2126 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2127 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2128 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2129
ce9e2e1b
LB		 2130 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2131 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2132
2133 if (payload && payload_len)
2134 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2135
2136 rc = mwl8k_post_cmd(hw, &cmd->header);
2137 kfree(cmd);
2138 return rc;
2139}
2140
2141/*
2142 * CMD_UPDATE_STADB.
2143 */
2144struct mwl8k_cmd_update_sta_db {
2145 struct mwl8k_cmd_pkt header;
2146
2147 /* See STADB_ACTION_TYPE */
2148 __le32 action;
2149
2150 /* Peer MAC address */
d89173f2 2151 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2152
2153 __le32 reserved;
2154
2155 /* Peer info - valid during add/update. */
2156 struct peer_capability_info peer_info;
2157} __attribute__((packed));
2158
2159static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2160 struct ieee80211_vif *vif, __u32 action)
2161{
2162 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2163 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2164 struct mwl8k_cmd_update_sta_db *cmd;
2165 struct peer_capability_info *peer_info;
2166 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2167 int rc;
2168 __u8 count, *rates;
2169
2170 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2171 if (cmd == NULL)
2172 return -ENOMEM;
2173
2174 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2175 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2176
2177 cmd->action = cpu_to_le32(action);
2178 peer_info = &cmd->peer_info;
d89173f2 2179 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2180
2181 switch (action) {
2182 case MWL8K_STA_DB_ADD_ENTRY:
2183 case MWL8K_STA_DB_MODIFY_ENTRY:
2184 /* Build peer_info block */
2185 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2186 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2187 peer_info->interop = 1;
2188 peer_info->amsdu_enabled = 0;
2189
2190 rates = peer_info->legacy_rates;
ce9e2e1b 2191 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2192 rates[count] = bitrates[count].hw_value;
2193
2194 rc = mwl8k_post_cmd(hw, &cmd->header);
2195 if (rc == 0)
2196 mv_vif->peer_id = peer_info->station_id;
2197
2198 break;
2199
2200 case MWL8K_STA_DB_DEL_ENTRY:
2201 case MWL8K_STA_DB_FLUSH:
2202 default:
2203 rc = mwl8k_post_cmd(hw, &cmd->header);
2204 if (rc == 0)
2205 mv_vif->peer_id = 0;
2206 break;
2207 }
2208 kfree(cmd);
2209
2210 return rc;
2211}
2212
2213/*
2214 * CMD_SET_AID.
2215 */
a66098da
LB		 2216#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2217
2218#define MWL8K_FRAME_PROT_DISABLED 0x00
2219#define MWL8K_FRAME_PROT_11G 0x07
2220#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2221#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2222
2223struct mwl8k_cmd_update_set_aid {
2224 struct mwl8k_cmd_pkt header;
2225 __le16 aid;
2226
2227 /* AP's MAC address (BSSID) */
d89173f2 2228 __u8 bssid[ETH_ALEN];
a66098da
LB		 2229 __le16 protection_mode;
2230 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2231} __attribute__((packed));
2232
2233static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2234 struct ieee80211_vif *vif)
2235{
2236 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2237 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2238 struct mwl8k_cmd_update_set_aid *cmd;
2239 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2240 int count;
2241 u16 prot_mode;
2242 int rc;
2243
2244 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2245 if (cmd == NULL)
2246 return -ENOMEM;
2247
2248 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2249 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2250 cmd->aid = cpu_to_le16(info->aid);
2251
d89173f2 2252 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2253
a66098da
LB		 2254 if (info->use_cts_prot) {
2255 prot_mode = MWL8K_FRAME_PROT_11G;
2256 } else {
9ed6bcce 2257 switch (info->ht_operation_mode &
a66098da
LB		 2258 IEEE80211_HT_OP_MODE_PROTECTION) {
2259 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2260 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2261 break;
2262 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2263 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2264 break;
2265 default:
2266 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2267 break;
2268 }
2269 }
a66098da
LB		 2270 cmd->protection_mode = cpu_to_le16(prot_mode);
2271
2272 for (count = 0; count < mv_vif->legacy_nrates; count++)
2273 cmd->supp_rates[count] = bitrates[count].hw_value;
2274
2275 rc = mwl8k_post_cmd(hw, &cmd->header);
2276 kfree(cmd);
2277
2278 return rc;
2279}
2280
2281/*
2282 * CMD_SET_RATE.
2283 */
2284struct mwl8k_cmd_update_rateset {
2285 struct mwl8k_cmd_pkt header;
2286 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2287
2288 /* Bitmap for supported MCS codes. */
2289 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2290 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2291} __attribute__((packed));
2292
2293static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2294 struct ieee80211_vif *vif)
2295{
2296 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2297 struct mwl8k_cmd_update_rateset *cmd;
2298 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2299 int count;
2300 int rc;
2301
2302 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2303 if (cmd == NULL)
2304 return -ENOMEM;
2305
2306 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2307 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2308
2309 for (count = 0; count < mv_vif->legacy_nrates; count++)
2310 cmd->legacy_rates[count] = bitrates[count].hw_value;
2311
2312 rc = mwl8k_post_cmd(hw, &cmd->header);
2313 kfree(cmd);
2314
2315 return rc;
2316}
2317
2318/*
2319 * CMD_USE_FIXED_RATE.
2320 */
2321#define MWL8K_RATE_TABLE_SIZE 8
2322#define MWL8K_UCAST_RATE 0
a66098da
LB		 2323#define MWL8K_USE_AUTO_RATE 0x0002
2324
2325struct mwl8k_rate_entry {
2326 /* Set to 1 if HT rate, 0 if legacy. */
2327 __le32 is_ht_rate;
2328
2329 /* Set to 1 to use retry_count field. */
2330 __le32 enable_retry;
2331
2332 /* Specified legacy rate or MCS. */
2333 __le32 rate;
2334
2335 /* Number of allowed retries. */
2336 __le32 retry_count;
2337} __attribute__((packed));
2338
2339struct mwl8k_rate_table {
2340 /* 1 to allow specified rate and below */
2341 __le32 allow_rate_drop;
2342 __le32 num_rates;
2343 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2344} __attribute__((packed));
2345
2346struct mwl8k_cmd_use_fixed_rate {
2347 struct mwl8k_cmd_pkt header;
2348 __le32 action;
2349 struct mwl8k_rate_table rate_table;
2350
2351 /* Unicast, Broadcast or Multicast */
2352 __le32 rate_type;
2353 __le32 reserved1;
2354 __le32 reserved2;
2355} __attribute__((packed));
2356
2357static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2358 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2359{
2360 struct mwl8k_cmd_use_fixed_rate *cmd;
2361 int count;
2362 int rc;
2363
2364 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2365 if (cmd == NULL)
2366 return -ENOMEM;
2367
2368 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2369 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2370
2371 cmd->action = cpu_to_le32(action);
2372 cmd->rate_type = cpu_to_le32(rate_type);
2373
2374 if (rate_table != NULL) {
c2c357ce
LB		 2375 /*
2376 * Copy over each field manually so that endian
2377 * conversion can be done.
2378 */
a66098da
LB		 2379 cmd->rate_table.allow_rate_drop =
2380 cpu_to_le32(rate_table->allow_rate_drop);
2381 cmd->rate_table.num_rates =
2382 cpu_to_le32(rate_table->num_rates);
2383
2384 for (count = 0; count < rate_table->num_rates; count++) {
2385 struct mwl8k_rate_entry *dst =
2386 &cmd->rate_table.rate_entry[count];
2387 struct mwl8k_rate_entry *src =
2388 &rate_table->rate_entry[count];
2389
2390 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2391 dst->enable_retry = cpu_to_le32(src->enable_retry);
2392 dst->rate = cpu_to_le32(src->rate);
2393 dst->retry_count = cpu_to_le32(src->retry_count);
2394 }
2395 }
2396
2397 rc = mwl8k_post_cmd(hw, &cmd->header);
2398 kfree(cmd);
2399
2400 return rc;
2401}
2402
2403
2404/*
2405 * Interrupt handling.
2406 */
2407static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2408{
2409 struct ieee80211_hw *hw = dev_id;
2410 struct mwl8k_priv *priv = hw->priv;
2411 u32 status;
2412
2413 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2414 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2415
a66098da
LB		 2416 if (!status)
2417 return IRQ_NONE;
2418
2419 if (status & MWL8K_A2H_INT_TX_DONE)
2420 tasklet_schedule(&priv->tx_reclaim_task);
2421
2422 if (status & MWL8K_A2H_INT_RX_READY) {
2423 while (rxq_process(hw, 0, 1))
2424 rxq_refill(hw, 0, 1);
2425 }
2426
2427 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2428 if (priv->hostcmd_wait != NULL)
a66098da 2429 complete(priv->hostcmd_wait);
a66098da
LB		 2430 }
2431
2432 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2433 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2434 priv->radio_on && priv->pending_tx_pkts)
618952a7 2435 mwl8k_tx_start(priv);
a66098da
LB		 2436 }
2437
2438 return IRQ_HANDLED;
2439}
2440
2441
2442/*
2443 * Core driver operations.
2444 */
2445static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2446{
2447 struct mwl8k_priv *priv = hw->priv;
2448 int index = skb_get_queue_mapping(skb);
2449 int rc;
2450
2451 if (priv->current_channel == NULL) {
2452 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2453 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2454 dev_kfree_skb(skb);
2455 return NETDEV_TX_OK;
2456 }
2457
2458 rc = mwl8k_txq_xmit(hw, index, skb);
2459
2460 return rc;
2461}
2462
a66098da
LB		 2463static int mwl8k_start(struct ieee80211_hw *hw)
2464{
a66098da
LB		 2465 struct mwl8k_priv *priv = hw->priv;
2466 int rc;
2467
a66098da
LB		 2468 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2469 IRQF_SHARED, MWL8K_NAME, hw);
2470 if (rc) {
2471 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2472 wiphy_name(hw->wiphy));
2ec610cb 2473 return -EIO;
a66098da
LB		 2474 }
2475
2ec610cb
LB		 2476 /* Enable tx reclaim tasklet */
2477 tasklet_enable(&priv->tx_reclaim_task);
2478
a66098da 2479 /* Enable interrupts */
c23b5a69 2480 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2481
2ec610cb
LB		 2482 rc = mwl8k_fw_lock(hw);
2483 if (!rc) {
2484 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2485
2ec610cb
LB		 2486 if (!rc)
2487 rc = mwl8k_cmd_set_pre_scan(hw);
a66098da 2488
2ec610cb
LB		 2489 if (!rc)
2490 rc = mwl8k_cmd_set_post_scan(hw,
2491 "\x00\x00\x00\x00\x00\x00");
2492
2493 if (!rc)
2494 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2495
2ec610cb
LB		 2496 if (!rc)
2497 rc = mwl8k_set_wmm(hw, 0);
a66098da 2498
2ec610cb
LB		 2499 if (!rc)
2500 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2501
2ec610cb
LB		 2502 mwl8k_fw_unlock(hw);
2503 }
2504
2505 if (rc) {
2506 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2507 free_irq(priv->pdev->irq, hw);
2508 tasklet_disable(&priv->tx_reclaim_task);
2509 }
a66098da
LB		 2510
2511 return rc;
2512}
2513
a66098da
LB		 2514static void mwl8k_stop(struct ieee80211_hw *hw)
2515{
a66098da
LB		 2516 struct mwl8k_priv *priv = hw->priv;
2517 int i;
2518
d3cea0b8 2519 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2520
2521 ieee80211_stop_queues(hw);
2522
a66098da 2523 /* Disable interrupts */
a66098da 2524 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2525 free_irq(priv->pdev->irq, hw);
2526
2527 /* Stop finalize join worker */
2528 cancel_work_sync(&priv->finalize_join_worker);
2529 if (priv->beacon_skb != NULL)
2530 dev_kfree_skb(priv->beacon_skb);
2531
2532 /* Stop tx reclaim tasklet */
2533 tasklet_disable(&priv->tx_reclaim_task);
2534
a66098da
LB		 2535 /* Return all skbs to mac80211 */
2536 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2537 mwl8k_txq_reclaim(hw, i, 1);
2538}
2539
2540static int mwl8k_add_interface(struct ieee80211_hw *hw,
2541 struct ieee80211_if_init_conf *conf)
2542{
2543 struct mwl8k_priv *priv = hw->priv;
2544 struct mwl8k_vif *mwl8k_vif;
2545
2546 /*
2547 * We only support one active interface at a time.
2548 */
2549 if (priv->vif != NULL)
2550 return -EBUSY;
2551
2552 /*
2553 * We only support managed interfaces for now.
2554 */
240e86ef 2555 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2556 return -EINVAL;
2557
2558 /* Clean out driver private area */
2559 mwl8k_vif = MWL8K_VIF(conf->vif);
2560 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2561
32060e1b
LB		 2562 /* Set and save the mac address */
2563 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2564 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2565
2566 /* Back pointer to parent config block */
2567 mwl8k_vif->priv = priv;
2568
2569 /* Setup initial PHY parameters */
ce9e2e1b 2570 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2571 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2572 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2573
2574 /* Set Initial sequence number to zero */
2575 mwl8k_vif->seqno = 0;
2576
2577 priv->vif = conf->vif;
2578 priv->current_channel = NULL;
2579
2580 return 0;
2581}
2582
2583static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2584 struct ieee80211_if_init_conf *conf)
2585{
2586 struct mwl8k_priv *priv = hw->priv;
2587
2588 if (priv->vif == NULL)
2589 return;
2590
32060e1b
LB		 2591 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2592
a66098da
LB		 2593 priv->vif = NULL;
2594}
2595
ee03a932 2596static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2597{
a66098da
LB		 2598 struct ieee80211_conf *conf = &hw->conf;
2599 struct mwl8k_priv *priv = hw->priv;
ee03a932 2600 int rc;
a66098da 2601
7595d67a
LB		 2602 if (conf->flags & IEEE80211_CONF_IDLE) {
2603 mwl8k_cmd_802_11_radio_disable(hw);
2604 priv->current_channel = NULL;
ee03a932 2605 return 0;
7595d67a
LB		 2606 }
2607
ee03a932
LB		 2608 rc = mwl8k_fw_lock(hw);
2609 if (rc)
2610 return rc;
a66098da 2611
ee03a932
LB		 2612 rc = mwl8k_cmd_802_11_radio_enable(hw);
2613 if (rc)
2614 goto out;
a66098da 2615
ee03a932
LB		 2616 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2617 if (rc)
2618 goto out;
2619
2620 priv->current_channel = conf->channel;
a66098da
LB		 2621
2622 if (conf->power_level > 18)
2623 conf->power_level = 18;
ee03a932
LB		 2624 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2625 if (rc)
2626 goto out;
a66098da
LB		 2627
2628 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2629 rc = -EINVAL;
2630
ee03a932
LB		 2631out:
2632 mwl8k_fw_unlock(hw);
a66098da 2633
ee03a932 2634 return rc;
a66098da
LB		 2635}
2636
3a980d0a
LB		 2637static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2638 struct ieee80211_vif *vif,
2639 struct ieee80211_bss_conf *info,
2640 u32 changed)
a66098da 2641{
a66098da
LB		 2642 struct mwl8k_priv *priv = hw->priv;
2643 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 2644 int rc;
2645
2646 if (changed & BSS_CHANGED_BSSID)
2647 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2648
2649 if ((changed & BSS_CHANGED_ASSOC) == 0)
2650 return;
a66098da 2651
a66098da
LB		 2652 priv->capture_beacon = false;
2653
3a980d0a 2654 rc = mwl8k_fw_lock(hw);
942457d6 2655 if (rc)
3a980d0a
LB		 2656 return;
2657
a66098da
LB		 2658 if (info->assoc) {
2659 memcpy(&mwl8k_vif->bss_info, info,
2660 sizeof(struct ieee80211_bss_conf));
2661
2662 /* Install rates */
3a980d0a
LB		 2663 rc = mwl8k_update_rateset(hw, vif);
2664 if (rc)
2665 goto out;
a66098da
LB		 2666
2667 /* Turn on rate adaptation */
3a980d0a
LB		 2668 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2669 MWL8K_UCAST_RATE, NULL);
2670 if (rc)
2671 goto out;
a66098da
LB		 2672
2673 /* Set radio preamble */
3a980d0a
LB		 2674 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2675 if (rc)
2676 goto out;
a66098da
LB		 2677
2678 /* Set slot time */
3a980d0a
LB		 2679 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2680 if (rc)
2681 goto out;
a66098da
LB		 2682
2683 /* Update peer rate info */
3a980d0a
LB		 2684 rc = mwl8k_cmd_update_sta_db(hw, vif,
2685 MWL8K_STA_DB_MODIFY_ENTRY);
2686 if (rc)
2687 goto out;
a66098da
LB		 2688
2689 /* Set AID */
3a980d0a
LB		 2690 rc = mwl8k_cmd_set_aid(hw, vif);
2691 if (rc)
2692 goto out;
a66098da
LB		 2693
2694 /*
2695 * Finalize the join. Tell rx handler to process
2696 * next beacon from our BSSID.
2697 */
d89173f2 2698 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 2699 priv->capture_beacon = true;
2700 } else {
3a980d0a 2701 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 2702 memset(&mwl8k_vif->bss_info, 0,
2703 sizeof(struct ieee80211_bss_conf));
d89173f2 2704 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 2705 }
2706
3a980d0a
LB		 2707out:
2708 mwl8k_fw_unlock(hw);
a66098da
LB		 2709}
2710
e81cd2d6
LB		 2711static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2712 int mc_count, struct dev_addr_list *mclist)
2713{
2714 struct mwl8k_cmd_pkt *cmd;
2715
447ced07
LB		 2716 /*
2717 * Synthesize and return a command packet that programs the
2718 * hardware multicast address filter. At this point we don't
2719 * know whether FIF_ALLMULTI is being requested, but if it is,
2720 * we'll end up throwing this packet away and creating a new
2721 * one in mwl8k_configure_filter().
2722 */
2723 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 2724
2725 return (unsigned long)cmd;
2726}
2727
e6935ea1
LB		 2728static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2729 unsigned int changed_flags,
2730 unsigned int *total_flags,
2731 u64 multicast)
2732{
2733 struct mwl8k_priv *priv = hw->priv;
447ced07 2734 struct mwl8k_cmd_pkt *cmd;
a66098da 2735
e6935ea1 2736 /* Clear unsupported feature flags */
447ced07 2737 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 2738
e6935ea1
LB		 2739 if (mwl8k_fw_lock(hw))
2740 return;
a66098da 2741
e6935ea1 2742 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 2743 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2744 /*
2745 * Disable the BSS filter.
2746 */
e6935ea1 2747 mwl8k_cmd_set_pre_scan(hw);
77165d88 2748 } else {
a94cc97e
LB		 2749 u8 *bssid;
2750
77165d88
LB		 2751 /*
2752 * Enable the BSS filter.
2753 *
2754 * If there is an active STA interface, use that
2755 * interface's BSSID, otherwise use a dummy one
2756 * (where the OUI part needs to be nonzero for
2757 * the BSSID to be accepted by POST_SCAN).
2758 */
2759 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 2760 if (priv->vif != NULL)
2761 bssid = MWL8K_VIF(priv->vif)->bssid;
2762
e6935ea1 2763 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 2764 }
2765 }
2766
447ced07
LB		 2767 cmd = (void *)(unsigned long)multicast;
2768
2769 /*
2770 * If FIF_ALLMULTI is being requested, throw away the command
2771 * packet that ->prepare_multicast() built and replace it with
2772 * a command packet that enables reception of all multicast
2773 * packets.
2774 */
2775 if (*total_flags & FIF_ALLMULTI) {
2776 kfree(cmd);
2777 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2778 }
2779
2780 if (cmd != NULL) {
2781 mwl8k_post_cmd(hw, cmd);
2782 kfree(cmd);
e6935ea1 2783 }
a66098da 2784
e6935ea1 2785 mwl8k_fw_unlock(hw);
a66098da
LB		 2786}
2787
a66098da
LB		 2788static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2789{
733d3067 2790 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 2791}
2792
a66098da
LB		 2793static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2794 const struct ieee80211_tx_queue_params *params)
2795{
3e4f542c 2796 struct mwl8k_priv *priv = hw->priv;
a66098da 2797 int rc;
a66098da 2798
3e4f542c
LB		 2799 rc = mwl8k_fw_lock(hw);
2800 if (!rc) {
2801 if (!priv->wmm_enabled)
2802 rc = mwl8k_set_wmm(hw, 1);
a66098da 2803
3e4f542c
LB		 2804 if (!rc)
2805 rc = mwl8k_set_edca_params(hw, queue,
2806 params->cw_min,
2807 params->cw_max,
2808 params->aifs,
2809 params->txop);
2810
2811 mwl8k_fw_unlock(hw);
a66098da 2812 }
3e4f542c 2813
a66098da
LB		 2814 return rc;
2815}
2816
2817static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2818 struct ieee80211_tx_queue_stats *stats)
2819{
2820 struct mwl8k_priv *priv = hw->priv;
2821 struct mwl8k_tx_queue *txq;
2822 int index;
2823
2824 spin_lock_bh(&priv->tx_lock);
2825 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2826 txq = priv->txq + index;
2827 memcpy(&stats[index], &txq->tx_stats,
2828 sizeof(struct ieee80211_tx_queue_stats));
2829 }
2830 spin_unlock_bh(&priv->tx_lock);
a66098da 2831
954ef509 2832 return 0;
a66098da
LB		 2833}
2834
2835static int mwl8k_get_stats(struct ieee80211_hw *hw,
2836 struct ieee80211_low_level_stats *stats)
2837{
954ef509 2838 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 2839}
2840
2841static const struct ieee80211_ops mwl8k_ops = {
2842 .tx = mwl8k_tx,
2843 .start = mwl8k_start,
2844 .stop = mwl8k_stop,
2845 .add_interface = mwl8k_add_interface,
2846 .remove_interface = mwl8k_remove_interface,
2847 .config = mwl8k_config,
a66098da 2848 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 2849 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 2850 .configure_filter = mwl8k_configure_filter,
2851 .set_rts_threshold = mwl8k_set_rts_threshold,
2852 .conf_tx = mwl8k_conf_tx,
2853 .get_tx_stats = mwl8k_get_tx_stats,
2854 .get_stats = mwl8k_get_stats,
2855};
2856
2857static void mwl8k_tx_reclaim_handler(unsigned long data)
2858{
2859 int i;
2860 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2861 struct mwl8k_priv *priv = hw->priv;
2862
2863 spin_lock_bh(&priv->tx_lock);
2864 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2865 mwl8k_txq_reclaim(hw, i, 0);
2866
88de754a 2867 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 2868 complete(priv->tx_wait);
2869 priv->tx_wait = NULL;
a66098da
LB		 2870 }
2871 spin_unlock_bh(&priv->tx_lock);
2872}
2873
2874static void mwl8k_finalize_join_worker(struct work_struct *work)
2875{
2876 struct mwl8k_priv *priv =
2877 container_of(work, struct mwl8k_priv, finalize_join_worker);
2878 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 2879 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 2880
2881 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2882 dev_kfree_skb(skb);
2883
2884 priv->beacon_skb = NULL;
2885}
2886
2887static int __devinit mwl8k_probe(struct pci_dev *pdev,
2888 const struct pci_device_id *id)
2889{
2aa7b01f 2890 static int printed_version = 0;
a66098da
LB		 2891 struct ieee80211_hw *hw;
2892 struct mwl8k_priv *priv;
a66098da
LB		 2893 int rc;
2894 int i;
2aa7b01f
LB		 2895
2896 if (!printed_version) {
2897 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2898 printed_version = 1;
2899 }
a66098da
LB		 2900
2901 rc = pci_enable_device(pdev);
2902 if (rc) {
2903 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2904 MWL8K_NAME);
2905 return rc;
2906 }
2907
2908 rc = pci_request_regions(pdev, MWL8K_NAME);
2909 if (rc) {
2910 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2911 MWL8K_NAME);
2912 return rc;
2913 }
2914
2915 pci_set_master(pdev);
2916
2917 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2918 if (hw == NULL) {
2919 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2920 rc = -ENOMEM;
2921 goto err_free_reg;
2922 }
2923
2924 priv = hw->priv;
2925 priv->hw = hw;
2926 priv->pdev = pdev;
0439b1f5 2927 priv->wmm_enabled = false;
a66098da 2928 priv->pending_tx_pkts = 0;
a66098da 2929
a66098da
LB		 2930 SET_IEEE80211_DEV(hw, &pdev->dev);
2931 pci_set_drvdata(pdev, hw);
2932
2933 priv->regs = pci_iomap(pdev, 1, 0x10000);
2934 if (priv->regs == NULL) {
c2c357ce
LB		 2935 printk(KERN_ERR "%s: Cannot map device memory\n",
2936 wiphy_name(hw->wiphy));
a66098da
LB		 2937 goto err_iounmap;
2938 }
2939
2940 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
2941 priv->band.band = IEEE80211_BAND_2GHZ;
2942 priv->band.channels = priv->channels;
2943 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
2944 priv->band.bitrates = priv->rates;
2945 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
2946 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
2947
2948 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
2949 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
2950
2951 /*
2952 * Extra headroom is the size of the required DMA header
2953 * minus the size of the smallest 802.11 frame (CTS frame).
2954 */
2955 hw->extra_tx_headroom =
2956 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
2957
2958 hw->channel_change_time = 10;
2959
2960 hw->queues = MWL8K_TX_QUEUES;
2961
240e86ef 2962 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
a66098da
LB		 2963
2964 /* Set rssi and noise values to dBm */
ce9e2e1b 2965 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 2966 hw->vif_data_size = sizeof(struct mwl8k_vif);
2967 priv->vif = NULL;
2968
2969 /* Set default radio state and preamble */
c46563b7 2970 priv->radio_on = 0;
68ce3884 2971 priv->radio_short_preamble = 0;
a66098da
LB		 2972
2973 /* Finalize join worker */
2974 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
2975
2976 /* TX reclaim tasklet */
2977 tasklet_init(&priv->tx_reclaim_task,
2978 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2979 tasklet_disable(&priv->tx_reclaim_task);
2980
a66098da
LB		 2981 /* Power management cookie */
2982 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2983 if (priv->cookie == NULL)
2984 goto err_iounmap;
2985
2986 rc = mwl8k_rxq_init(hw, 0);
2987 if (rc)
2988 goto err_iounmap;
2989 rxq_refill(hw, 0, INT_MAX);
2990
618952a7
LB		 2991 mutex_init(&priv->fw_mutex);
2992 priv->fw_mutex_owner = NULL;
2993 priv->fw_mutex_depth = 0;
618952a7
LB		 2994 priv->hostcmd_wait = NULL;
2995
a66098da
LB		 2996 spin_lock_init(&priv->tx_lock);
2997
88de754a
LB		 2998 priv->tx_wait = NULL;
2999
a66098da
LB		 3000 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3001 rc = mwl8k_txq_init(hw, i);
3002 if (rc)
3003 goto err_free_queues;
3004 }
3005
3006 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3007 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3008 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3009 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3010
3011 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3012 IRQF_SHARED, MWL8K_NAME, hw);
3013 if (rc) {
3014 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3015 wiphy_name(hw->wiphy));
a66098da
LB		 3016 goto err_free_queues;
3017 }
3018
3019 /* Reset firmware and hardware */
3020 mwl8k_hw_reset(priv);
3021
3022 /* Ask userland hotplug daemon for the device firmware */
3023 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3024 if (rc) {
c2c357ce
LB		 3025 printk(KERN_ERR "%s: Firmware files not found\n",
3026 wiphy_name(hw->wiphy));
a66098da
LB		 3027 goto err_free_irq;
3028 }
3029
3030 /* Load firmware into hardware */
c2c357ce 3031 rc = mwl8k_load_firmware(hw);
a66098da 3032 if (rc) {
c2c357ce
LB		 3033 printk(KERN_ERR "%s: Cannot start firmware\n",
3034 wiphy_name(hw->wiphy));
a66098da
LB		 3035 goto err_stop_firmware;
3036 }
3037
3038 /* Reclaim memory once firmware is successfully loaded */
3039 mwl8k_release_firmware(priv);
3040
3041 /*
3042 * Temporarily enable interrupts. Initial firmware host
3043 * commands use interrupts and avoids polling. Disable
3044 * interrupts when done.
3045 */
c23b5a69 3046 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3047
3048 /* Get config data, mac addrs etc */
3049 rc = mwl8k_cmd_get_hw_spec(hw);
3050 if (rc) {
c2c357ce
LB		 3051 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3052 wiphy_name(hw->wiphy));
a66098da
LB		 3053 goto err_stop_firmware;
3054 }
3055
3056 /* Turn radio off */
c46563b7 3057 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3058 if (rc) {
c2c357ce 3059 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3060 goto err_stop_firmware;
3061 }
3062
32060e1b
LB		 3063 /* Clear MAC address */
3064 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3065 if (rc) {
3066 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3067 wiphy_name(hw->wiphy));
3068 goto err_stop_firmware;
3069 }
3070
a66098da 3071 /* Disable interrupts */
a66098da 3072 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3073 free_irq(priv->pdev->irq, hw);
3074
3075 rc = ieee80211_register_hw(hw);
3076 if (rc) {
c2c357ce
LB		 3077 printk(KERN_ERR "%s: Cannot register device\n",
3078 wiphy_name(hw->wiphy));
a66098da
LB		 3079 goto err_stop_firmware;
3080 }
3081
2aa7b01f
LB		 3082 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3083 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3084 hw->wiphy->perm_addr,
3085 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3086 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3087
3088 return 0;
3089
3090err_stop_firmware:
3091 mwl8k_hw_reset(priv);
3092 mwl8k_release_firmware(priv);
3093
3094err_free_irq:
a66098da 3095 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3096 free_irq(priv->pdev->irq, hw);
3097
3098err_free_queues:
3099 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3100 mwl8k_txq_deinit(hw, i);
3101 mwl8k_rxq_deinit(hw, 0);
3102
3103err_iounmap:
3104 if (priv->cookie != NULL)
3105 pci_free_consistent(priv->pdev, 4,
3106 priv->cookie, priv->cookie_dma);
3107
3108 if (priv->regs != NULL)
3109 pci_iounmap(pdev, priv->regs);
3110
a66098da
LB		 3111 pci_set_drvdata(pdev, NULL);
3112 ieee80211_free_hw(hw);
3113
3114err_free_reg:
3115 pci_release_regions(pdev);
3116 pci_disable_device(pdev);
3117
3118 return rc;
3119}
3120
230f7af0 3121static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3122{
3123 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3124}
3125
230f7af0 3126static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3127{
3128 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3129 struct mwl8k_priv *priv;
3130 int i;
3131
3132 if (hw == NULL)
3133 return;
3134 priv = hw->priv;
3135
3136 ieee80211_stop_queues(hw);
3137
60aa569f
LB		 3138 ieee80211_unregister_hw(hw);
3139
a66098da
LB		 3140 /* Remove tx reclaim tasklet */
3141 tasklet_kill(&priv->tx_reclaim_task);
3142
a66098da
LB		 3143 /* Stop hardware */
3144 mwl8k_hw_reset(priv);
3145
3146 /* Return all skbs to mac80211 */
3147 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3148 mwl8k_txq_reclaim(hw, i, 1);
3149
a66098da
LB		 3150 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3151 mwl8k_txq_deinit(hw, i);
3152
3153 mwl8k_rxq_deinit(hw, 0);
3154
c2c357ce 3155 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3156
3157 pci_iounmap(pdev, priv->regs);
3158 pci_set_drvdata(pdev, NULL);
3159 ieee80211_free_hw(hw);
3160 pci_release_regions(pdev);
3161 pci_disable_device(pdev);
3162}
3163
3164static struct pci_driver mwl8k_driver = {
3165 .name = MWL8K_NAME,
3166 .id_table = mwl8k_table,
3167 .probe = mwl8k_probe,
3168 .remove = __devexit_p(mwl8k_remove),
3169 .shutdown = __devexit_p(mwl8k_shutdown),
3170};
3171
3172static int __init mwl8k_init(void)
3173{
3174 return pci_register_driver(&mwl8k_driver);
3175}
3176
3177static void __exit mwl8k_exit(void)
3178{
3179 pci_unregister_driver(&mwl8k_driver);
3180}
3181
3182module_init(mwl8k_init);
3183module_exit(mwl8k_exit);
c2c357ce
LB		 3184
3185MODULE_DESCRIPTION(MWL8K_DESC);
3186MODULE_VERSION(MWL8K_VERSION);
3187MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3188MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)