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mwl8k: clear hardware MAC address if no STA interface configured
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/completion.h>
20#include <linux/etherdevice.h>
21#include <net/mac80211.h>
22#include <linux/moduleparam.h>
23#include <linux/firmware.h>
24#include <linux/workqueue.h>
25
26#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
27#define MWL8K_NAME KBUILD_MODNAME
a145d575 28#define MWL8K_VERSION "0.10"
a66098da 29
a66098da
LB		 30static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
31 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
32 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
33 { }
34};
35MODULE_DEVICE_TABLE(pci, mwl8k_table);
36
a66098da
LB		 37/* Register definitions */
38#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 39#define MWL8K_MODE_STA 0x0000005a
40#define MWL8K_MODE_AP 0x000000a5
a66098da 41#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 42#define MWL8K_FWSTA_READY 0xf0f1f2f4
43#define MWL8K_FWAP_READY 0xf1f2f4a5
44#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 45#define MWL8K_HIU_SCRATCH 0x00000c40
46
47/* Host->device communications */
48#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
49#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
50#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
51#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
52#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 53#define MWL8K_H2A_INT_DUMMY (1 << 20)
54#define MWL8K_H2A_INT_RESET (1 << 15)
55#define MWL8K_H2A_INT_DOORBELL (1 << 1)
56#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 57
58/* Device->host communications */
59#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
60#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
61#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
62#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
63#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 64#define MWL8K_A2H_INT_DUMMY (1 << 20)
65#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
66#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
67#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
68#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
69#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
70#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
71#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
72#define MWL8K_A2H_INT_RX_READY (1 << 1)
73#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 74
75#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
76 MWL8K_A2H_INT_CHNL_SWITCHED | \
77 MWL8K_A2H_INT_QUEUE_EMPTY | \
78 MWL8K_A2H_INT_RADAR_DETECT | \
79 MWL8K_A2H_INT_RADIO_ON | \
80 MWL8K_A2H_INT_RADIO_OFF | \
81 MWL8K_A2H_INT_MAC_EVENT | \
82 MWL8K_A2H_INT_OPC_DONE | \
83 MWL8K_A2H_INT_RX_READY | \
84 MWL8K_A2H_INT_TX_DONE)
85
86/* WME stream classes */
87#define WME_AC_BE 0 /* best effort */
88#define WME_AC_BK 1 /* background */
89#define WME_AC_VI 2 /* video */
90#define WME_AC_VO 3 /* voice */
91
92#define MWL8K_RX_QUEUES 1
93#define MWL8K_TX_QUEUES 4
94
95struct mwl8k_rx_queue {
96 int rx_desc_count;
97
98 /* hw receives here */
99 int rx_head;
100
101 /* refill descs here */
102 int rx_tail;
103
104 struct mwl8k_rx_desc *rx_desc_area;
105 dma_addr_t rx_desc_dma;
106 struct sk_buff **rx_skb;
107};
108
a66098da
LB		 109struct mwl8k_tx_queue {
110 /* hw transmits here */
111 int tx_head;
112
113 /* sw appends here */
114 int tx_tail;
115
116 struct ieee80211_tx_queue_stats tx_stats;
117 struct mwl8k_tx_desc *tx_desc_area;
118 dma_addr_t tx_desc_dma;
76266b2a 119 struct sk_buff **tx_skb;
a66098da
LB		 120};
121
122/* Pointers to the firmware data and meta information about it. */
123struct mwl8k_firmware {
124 /* Microcode */
125 struct firmware *ucode;
126
127 /* Boot helper code */
128 struct firmware *helper;
129};
130
131struct mwl8k_priv {
132 void __iomem *regs;
133 struct ieee80211_hw *hw;
134
135 struct pci_dev *pdev;
a66098da
LB		 136
137 /* firmware files and meta data */
138 struct mwl8k_firmware fw;
139 u32 part_num;
140
618952a7
LB		 141 /* firmware access */
142 struct mutex fw_mutex;
143 struct task_struct *fw_mutex_owner;
144 int fw_mutex_depth;
618952a7
LB		 145 struct completion *hostcmd_wait;
146
a66098da
LB		 147 /* lock held over TX and TX reap */
148 spinlock_t tx_lock;
a66098da 149
88de754a
LB		 150 /* TX quiesce completion, protected by fw_mutex and tx_lock */
151 struct completion *tx_wait;
152
a66098da 153 struct ieee80211_vif *vif;
a66098da
LB		 154
155 struct ieee80211_channel *current_channel;
156
157 /* power management status cookie from firmware */
158 u32 *cookie;
159 dma_addr_t cookie_dma;
160
161 u16 num_mcaddrs;
a66098da 162 u8 hw_rev;
2aa7b01f 163 u32 fw_rev;
a66098da
LB		 164
165 /*
166 * Running count of TX packets in flight, to avoid
167 * iterating over the transmit rings each time.
168 */
169 int pending_tx_pkts;
170
171 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
172 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
173
174 /* PHY parameters */
175 struct ieee80211_supported_band band;
176 struct ieee80211_channel channels[14];
177 struct ieee80211_rate rates[12];
178
c46563b7 179 bool radio_on;
68ce3884 180 bool radio_short_preamble;
0439b1f5 181 bool wmm_enabled;
a66098da 182
a66098da
LB		 183 /* XXX need to convert this to handle multiple interfaces */
184 bool capture_beacon;
d89173f2 185 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 186 struct sk_buff *beacon_skb;
187
188 /*
189 * This FJ worker has to be global as it is scheduled from the
190 * RX handler. At this point we don't know which interface it
191 * belongs to until the list of bssids waiting to complete join
192 * is checked.
193 */
194 struct work_struct finalize_join_worker;
195
196 /* Tasklet to reclaim TX descriptors and buffers after tx */
197 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 198};
199
200/* Per interface specific private data */
201struct mwl8k_vif {
a66098da
LB		 202 /* backpointer to parent config block */
203 struct mwl8k_priv *priv;
204
205 /* BSS config of AP or IBSS from mac80211*/
206 struct ieee80211_bss_conf bss_info;
207
208 /* BSSID of AP or IBSS */
d89173f2
LB		 209 u8 bssid[ETH_ALEN];
210 u8 mac_addr[ETH_ALEN];
a66098da
LB		 211
212 /*
213 * Subset of supported legacy rates.
214 * Intersection of AP and STA supported rates.
215 */
216 struct ieee80211_rate legacy_rates[12];
217
218 /* number of supported legacy rates */
219 u8 legacy_nrates;
220
a66098da
LB		 221 /* Index into station database.Returned by update_sta_db call */
222 u8 peer_id;
223
224 /* Non AMPDU sequence number assigned by driver */
225 u16 seqno;
a66098da
LB		 226};
227
a94cc97e 228#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 229
230static const struct ieee80211_channel mwl8k_channels[] = {
231 { .center_freq = 2412, .hw_value = 1, },
232 { .center_freq = 2417, .hw_value = 2, },
233 { .center_freq = 2422, .hw_value = 3, },
234 { .center_freq = 2427, .hw_value = 4, },
235 { .center_freq = 2432, .hw_value = 5, },
236 { .center_freq = 2437, .hw_value = 6, },
237 { .center_freq = 2442, .hw_value = 7, },
238 { .center_freq = 2447, .hw_value = 8, },
239 { .center_freq = 2452, .hw_value = 9, },
240 { .center_freq = 2457, .hw_value = 10, },
241 { .center_freq = 2462, .hw_value = 11, },
242};
243
244static const struct ieee80211_rate mwl8k_rates[] = {
245 { .bitrate = 10, .hw_value = 2, },
246 { .bitrate = 20, .hw_value = 4, },
247 { .bitrate = 55, .hw_value = 11, },
248 { .bitrate = 60, .hw_value = 12, },
249 { .bitrate = 90, .hw_value = 18, },
250 { .bitrate = 110, .hw_value = 22, },
251 { .bitrate = 120, .hw_value = 24, },
252 { .bitrate = 180, .hw_value = 36, },
253 { .bitrate = 240, .hw_value = 48, },
254 { .bitrate = 360, .hw_value = 72, },
255 { .bitrate = 480, .hw_value = 96, },
256 { .bitrate = 540, .hw_value = 108, },
257};
258
a66098da
LB		 259/* Set or get info from Firmware */
260#define MWL8K_CMD_SET 0x0001
261#define MWL8K_CMD_GET 0x0000
262
263/* Firmware command codes */
264#define MWL8K_CMD_CODE_DNLD 0x0001
265#define MWL8K_CMD_GET_HW_SPEC 0x0003
266#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
267#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 268#define MWL8K_CMD_RADIO_CONTROL 0x001c
269#define MWL8K_CMD_RF_TX_POWER 0x001e
a66098da
LB		 270#define MWL8K_CMD_SET_PRE_SCAN 0x0107
271#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 272#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
273#define MWL8K_CMD_SET_AID 0x010d
274#define MWL8K_CMD_SET_RATE 0x0110
275#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
276#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 277#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 278#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
279#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 280#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 281#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 282#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 283#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 284#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 285#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 286
287static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
288{
289#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
290 snprintf(buf, bufsize, "%s", #x);\
291 return buf;\
292 } while (0)
ce9e2e1b 293 switch (cmd & ~0x8000) {
a66098da
LB		 294 MWL8K_CMDNAME(CODE_DNLD);
295 MWL8K_CMDNAME(GET_HW_SPEC);
296 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
297 MWL8K_CMDNAME(GET_STAT);
298 MWL8K_CMDNAME(RADIO_CONTROL);
299 MWL8K_CMDNAME(RF_TX_POWER);
300 MWL8K_CMDNAME(SET_PRE_SCAN);
301 MWL8K_CMDNAME(SET_POST_SCAN);
302 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 303 MWL8K_CMDNAME(SET_AID);
304 MWL8K_CMDNAME(SET_RATE);
305 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
306 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 307 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 308 MWL8K_CMDNAME(SET_EDCA_PARAMS);
309 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 310 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 311 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 312 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 313 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 314 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 315 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 316 default:
317 snprintf(buf, bufsize, "0x%x", cmd);
318 }
319#undef MWL8K_CMDNAME
320
321 return buf;
322}
323
324/* Hardware and firmware reset */
325static void mwl8k_hw_reset(struct mwl8k_priv *priv)
326{
327 iowrite32(MWL8K_H2A_INT_RESET,
328 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
329 iowrite32(MWL8K_H2A_INT_RESET,
330 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
331 msleep(20);
332}
333
334/* Release fw image */
335static void mwl8k_release_fw(struct firmware **fw)
336{
337 if (*fw == NULL)
338 return;
339 release_firmware(*fw);
340 *fw = NULL;
341}
342
343static void mwl8k_release_firmware(struct mwl8k_priv *priv)
344{
345 mwl8k_release_fw(&priv->fw.ucode);
346 mwl8k_release_fw(&priv->fw.helper);
347}
348
349/* Request fw image */
350static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 351 const char *fname, struct firmware **fw)
a66098da
LB		 352{
353 /* release current image */
354 if (*fw != NULL)
355 mwl8k_release_fw(fw);
356
357 return request_firmware((const struct firmware **)fw,
c2c357ce 358 fname, &priv->pdev->dev);
a66098da
LB		 359}
360
361static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
362{
363 u8 filename[64];
364 int rc;
365
366 priv->part_num = part_num;
367
368 snprintf(filename, sizeof(filename),
369 "mwl8k/helper_%u.fw", priv->part_num);
370
371 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
372 if (rc) {
c2c357ce
LB		 373 printk(KERN_ERR "%s: Error requesting helper firmware "
374 "file %s\n", pci_name(priv->pdev), filename);
a66098da
LB		 375 return rc;
376 }
377
378 snprintf(filename, sizeof(filename),
379 "mwl8k/fmimage_%u.fw", priv->part_num);
380
381 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
382 if (rc) {
c2c357ce
LB		 383 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
384 pci_name(priv->pdev), filename);
a66098da
LB		 385 mwl8k_release_fw(&priv->fw.helper);
386 return rc;
387 }
388
389 return 0;
390}
391
392struct mwl8k_cmd_pkt {
393 __le16 code;
394 __le16 length;
395 __le16 seq_num;
396 __le16 result;
397 char payload[0];
398} __attribute__((packed));
399
400/*
401 * Firmware loading.
402 */
403static int
404mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
405{
406 void __iomem *regs = priv->regs;
407 dma_addr_t dma_addr;
a66098da
LB		 408 int loops;
409
410 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
411 if (pci_dma_mapping_error(priv->pdev, dma_addr))
412 return -ENOMEM;
413
414 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
415 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
416 iowrite32(MWL8K_H2A_INT_DOORBELL,
417 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
418 iowrite32(MWL8K_H2A_INT_DUMMY,
419 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
420
a66098da
LB		 421 loops = 1000;
422 do {
423 u32 int_code;
424
425 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
426 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
427 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 428 break;
429 }
430
431 udelay(1);
432 } while (--loops);
433
434 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
435
d4b70570 436 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 437}
438
439static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
440 const u8 *data, size_t length)
441{
442 struct mwl8k_cmd_pkt *cmd;
443 int done;
444 int rc = 0;
445
446 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
447 if (cmd == NULL)
448 return -ENOMEM;
449
450 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
451 cmd->seq_num = 0;
452 cmd->result = 0;
453
454 done = 0;
455 while (length) {
456 int block_size = length > 256 ? 256 : length;
457
458 memcpy(cmd->payload, data + done, block_size);
459 cmd->length = cpu_to_le16(block_size);
460
461 rc = mwl8k_send_fw_load_cmd(priv, cmd,
462 sizeof(*cmd) + block_size);
463 if (rc)
464 break;
465
466 done += block_size;
467 length -= block_size;
468 }
469
470 if (!rc) {
471 cmd->length = 0;
472 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
473 }
474
475 kfree(cmd);
476
477 return rc;
478}
479
480static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
481 const u8 *data, size_t length)
482{
483 unsigned char *buffer;
484 int may_continue, rc = 0;
485 u32 done, prev_block_size;
486
487 buffer = kmalloc(1024, GFP_KERNEL);
488 if (buffer == NULL)
489 return -ENOMEM;
490
491 done = 0;
492 prev_block_size = 0;
493 may_continue = 1000;
494 while (may_continue > 0) {
495 u32 block_size;
496
497 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
498 if (block_size & 1) {
499 block_size &= ~1;
500 may_continue--;
501 } else {
502 done += prev_block_size;
503 length -= prev_block_size;
504 }
505
506 if (block_size > 1024 || block_size > length) {
507 rc = -EOVERFLOW;
508 break;
509 }
510
511 if (length == 0) {
512 rc = 0;
513 break;
514 }
515
516 if (block_size == 0) {
517 rc = -EPROTO;
518 may_continue--;
519 udelay(1);
520 continue;
521 }
522
523 prev_block_size = block_size;
524 memcpy(buffer, data + done, block_size);
525
526 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
527 if (rc)
528 break;
529 }
530
531 if (!rc && length != 0)
532 rc = -EREMOTEIO;
533
534 kfree(buffer);
535
536 return rc;
537}
538
c2c357ce 539static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 540{
c2c357ce
LB		 541 struct mwl8k_priv *priv = hw->priv;
542 struct firmware *fw = priv->fw.ucode;
543 int rc;
544 int loops;
545
546 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
547 struct firmware *helper = priv->fw.helper;
a66098da 548
c2c357ce
LB		 549 if (helper == NULL) {
550 printk(KERN_ERR "%s: helper image needed but none "
551 "given\n", pci_name(priv->pdev));
552 return -EINVAL;
553 }
a66098da 554
c2c357ce 555 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 556 if (rc) {
557 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 558 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 559 return rc;
560 }
561 msleep(1);
562
c2c357ce 563 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 564 } else {
c2c357ce 565 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 566 }
567
568 if (rc) {
c2c357ce
LB		 569 printk(KERN_ERR "%s: unable to load firmware image\n",
570 pci_name(priv->pdev));
a66098da
LB		 571 return rc;
572 }
573
574 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
575 msleep(1);
576
577 loops = 200000;
578 do {
579 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
580 == MWL8K_FWSTA_READY)
581 break;
582 udelay(1);
583 } while (--loops);
584
585 return loops ? 0 : -ETIMEDOUT;
586}
587
588
589/*
590 * Defines shared between transmission and reception.
591 */
592/* HT control fields for firmware */
593struct ewc_ht_info {
594 __le16 control1;
595 __le16 control2;
596 __le16 control3;
597} __attribute__((packed));
598
599/* Firmware Station database operations */
600#define MWL8K_STA_DB_ADD_ENTRY 0
601#define MWL8K_STA_DB_MODIFY_ENTRY 1
602#define MWL8K_STA_DB_DEL_ENTRY 2
603#define MWL8K_STA_DB_FLUSH 3
604
605/* Peer Entry flags - used to define the type of the peer node */
606#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da
LB		 607
608#define MWL8K_IEEE_LEGACY_DATA_RATES 12
609#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 610
611struct peer_capability_info {
612 /* Peer type - AP vs. STA. */
613 __u8 peer_type;
614
615 /* Basic 802.11 capabilities from assoc resp. */
616 __le16 basic_caps;
617
618 /* Set if peer supports 802.11n high throughput (HT). */
619 __u8 ht_support;
620
621 /* Valid if HT is supported. */
622 __le16 ht_caps;
623 __u8 extended_ht_caps;
624 struct ewc_ht_info ewc_info;
625
626 /* Legacy rate table. Intersection of our rates and peer rates. */
627 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
628
629 /* HT rate table. Intersection of our rates and peer rates. */
630 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 631 __u8 pad[16];
a66098da
LB		 632
633 /* If set, interoperability mode, no proprietary extensions. */
634 __u8 interop;
635 __u8 pad2;
636 __u8 station_id;
637 __le16 amsdu_enabled;
638} __attribute__((packed));
639
640/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 641static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
642{
643 u16 val_mask = 1 << 4;
644
645 /* End of Service Period Bit 4 */
646 return qos | val_mask;
647}
648
649static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
650{
651 u16 val_mask = 0x3;
652 u8 shift = 5;
653 u16 qos_mask = ~(val_mask << shift);
654
655 /* Ack Policy Bit 5-6 */
656 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
657}
658
659static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
660{
661 u16 val_mask = 1 << 7;
662
663 /* AMSDU present Bit 7 */
664 return qos | val_mask;
665}
666
667static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
668{
669 u16 val_mask = 0xff;
670 u8 shift = 8;
671 u16 qos_mask = ~(val_mask << shift);
672
673 /* Queue Length Bits 8-15 */
674 return (qos & qos_mask) | ((len & val_mask) << shift);
675}
676
677/* DMA header used by firmware and hardware. */
678struct mwl8k_dma_data {
679 __le16 fwlen;
680 struct ieee80211_hdr wh;
681} __attribute__((packed));
682
683/* Routines to add/remove DMA header from skb. */
76266b2a 684static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
a66098da 685{
76266b2a 686 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
a66098da 687 void *dst, *src = &tr->wh;
76266b2a 688 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
a66098da
LB		 689 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
690
691 dst = (void *)tr + space;
692 if (dst != src) {
693 memmove(dst, src, hdrlen);
694 skb_pull(skb, space);
695 }
a66098da
LB		 696}
697
76266b2a 698static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 699{
700 struct ieee80211_hdr *wh;
701 u32 hdrlen, pktlen;
702 struct mwl8k_dma_data *tr;
703
704 wh = (struct ieee80211_hdr *)skb->data;
705 hdrlen = ieee80211_hdrlen(wh->frame_control);
706 pktlen = skb->len;
707
708 /*
709 * Copy up/down the 802.11 header; the firmware requires
710 * we present a 2-byte payload length followed by a
711 * 4-address header (w/o QoS), followed (optionally) by
712 * any WEP/ExtIV header (but only filled in for CCMP).
713 */
714 if (hdrlen != sizeof(struct mwl8k_dma_data))
715 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
716
717 tr = (struct mwl8k_dma_data *)skb->data;
718 if (wh != &tr->wh)
719 memmove(&tr->wh, wh, hdrlen);
720
721 /* Clear addr4 */
d89173f2 722 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 723
724 /*
725 * Firmware length is the length of the fully formed "802.11
726 * payload". That is, everything except for the 802.11 header.
727 * This includes all crypto material including the MIC.
728 */
729 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 730}
731
732
733/*
734 * Packet reception.
735 */
a66098da 736#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
a66098da
LB		 737
738struct mwl8k_rx_desc {
739 __le16 pkt_len;
740 __u8 link_quality;
741 __u8 noise_level;
742 __le32 pkt_phys_addr;
743 __le32 next_rx_desc_phys_addr;
744 __le16 qos_control;
745 __le16 rate_info;
746 __le32 pad0[4];
747 __u8 rssi;
748 __u8 channel;
749 __le16 pad1;
750 __u8 rx_ctrl;
751 __u8 rx_status;
752 __u8 pad2[2];
753} __attribute__((packed));
754
755#define MWL8K_RX_DESCS 256
756#define MWL8K_RX_MAXSZ 3800
757
758static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
759{
760 struct mwl8k_priv *priv = hw->priv;
761 struct mwl8k_rx_queue *rxq = priv->rxq + index;
762 int size;
763 int i;
764
765 rxq->rx_desc_count = 0;
766 rxq->rx_head = 0;
767 rxq->rx_tail = 0;
768
769 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
770
771 rxq->rx_desc_area =
772 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
773 if (rxq->rx_desc_area == NULL) {
774 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 775 wiphy_name(hw->wiphy));
a66098da
LB		 776 return -ENOMEM;
777 }
778 memset(rxq->rx_desc_area, 0, size);
779
780 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
781 sizeof(*rxq->rx_skb), GFP_KERNEL);
782 if (rxq->rx_skb == NULL) {
783 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 784 wiphy_name(hw->wiphy));
a66098da
LB		 785 pci_free_consistent(priv->pdev, size,
786 rxq->rx_desc_area, rxq->rx_desc_dma);
787 return -ENOMEM;
788 }
789 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
790
791 for (i = 0; i < MWL8K_RX_DESCS; i++) {
792 struct mwl8k_rx_desc *rx_desc;
793 int nexti;
794
795 rx_desc = rxq->rx_desc_area + i;
796 nexti = (i + 1) % MWL8K_RX_DESCS;
797
798 rx_desc->next_rx_desc_phys_addr =
799 cpu_to_le32(rxq->rx_desc_dma
800 + nexti * sizeof(*rx_desc));
c491bf12 801 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
a66098da
LB		 802 }
803
804 return 0;
805}
806
807static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
808{
809 struct mwl8k_priv *priv = hw->priv;
810 struct mwl8k_rx_queue *rxq = priv->rxq + index;
811 int refilled;
812
813 refilled = 0;
814 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
815 struct sk_buff *skb;
816 int rx;
817
818 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
819 if (skb == NULL)
820 break;
821
822 rxq->rx_desc_count++;
823
824 rx = rxq->rx_tail;
825 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
826
827 rxq->rx_desc_area[rx].pkt_phys_addr =
828 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
829 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
830
831 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
832 rxq->rx_skb[rx] = skb;
833 wmb();
834 rxq->rx_desc_area[rx].rx_ctrl = 0;
835
836 refilled++;
837 }
838
839 return refilled;
840}
841
842/* Must be called only when the card's reception is completely halted */
843static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
844{
845 struct mwl8k_priv *priv = hw->priv;
846 struct mwl8k_rx_queue *rxq = priv->rxq + index;
847 int i;
848
849 for (i = 0; i < MWL8K_RX_DESCS; i++) {
850 if (rxq->rx_skb[i] != NULL) {
851 unsigned long addr;
852
853 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
854 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
855 PCI_DMA_FROMDEVICE);
856 kfree_skb(rxq->rx_skb[i]);
857 rxq->rx_skb[i] = NULL;
858 }
859 }
860
861 kfree(rxq->rx_skb);
862 rxq->rx_skb = NULL;
863
864 pci_free_consistent(priv->pdev,
865 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
866 rxq->rx_desc_area, rxq->rx_desc_dma);
867 rxq->rx_desc_area = NULL;
868}
869
870
871/*
872 * Scan a list of BSSIDs to process for finalize join.
873 * Allows for extension to process multiple BSSIDs.
874 */
875static inline int
876mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
877{
878 return priv->capture_beacon &&
879 ieee80211_is_beacon(wh->frame_control) &&
880 !compare_ether_addr(wh->addr3, priv->capture_bssid);
881}
882
3779752d
LB		 883static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
884 struct sk_buff *skb)
a66098da 885{
3779752d
LB		 886 struct mwl8k_priv *priv = hw->priv;
887
a66098da 888 priv->capture_beacon = false;
d89173f2 889 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 890
891 /*
892 * Use GFP_ATOMIC as rxq_process is called from
893 * the primary interrupt handler, memory allocation call
894 * must not sleep.
895 */
896 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
897 if (priv->beacon_skb != NULL)
3779752d 898 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 899}
900
901static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
902{
903 struct mwl8k_priv *priv = hw->priv;
904 struct mwl8k_rx_queue *rxq = priv->rxq + index;
905 int processed;
906
907 processed = 0;
908 while (rxq->rx_desc_count && limit--) {
909 struct mwl8k_rx_desc *rx_desc;
910 struct sk_buff *skb;
911 struct ieee80211_rx_status status;
912 unsigned long addr;
913 struct ieee80211_hdr *wh;
914
915 rx_desc = rxq->rx_desc_area + rxq->rx_head;
916 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
917 break;
918 rmb();
919
920 skb = rxq->rx_skb[rxq->rx_head];
d25f9f13
LB		 921 if (skb == NULL)
922 break;
a66098da
LB		 923 rxq->rx_skb[rxq->rx_head] = NULL;
924
925 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
926 rxq->rx_desc_count--;
927
928 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
929 pci_unmap_single(priv->pdev, addr,
930 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
931
932 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
76266b2a 933 mwl8k_remove_dma_header(skb);
a66098da
LB		 934
935 wh = (struct ieee80211_hdr *)skb->data;
936
937 /*
c2c357ce
LB		 938 * Check for a pending join operation. Save a
939 * copy of the beacon and schedule a tasklet to
940 * send a FINALIZE_JOIN command to the firmware.
a66098da
LB		 941 */
942 if (mwl8k_capture_bssid(priv, wh))
3779752d 943 mwl8k_save_beacon(hw, skb);
a66098da
LB		 944
945 memset(&status, 0, sizeof(status));
946 status.mactime = 0;
947 status.signal = -rx_desc->rssi;
948 status.noise = -rx_desc->noise_level;
949 status.qual = rx_desc->link_quality;
950 status.antenna = 1;
951 status.rate_idx = 1;
952 status.flag = 0;
953 status.band = IEEE80211_BAND_2GHZ;
954 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
f1d58c25
JB		 955 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
956 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 957
958 processed++;
959 }
960
961 return processed;
962}
963
964
965/*
966 * Packet transmission.
967 */
968
969/* Transmit queue assignment. */
970enum {
971 MWL8K_WME_AC_BK = 0, /* background access */
972 MWL8K_WME_AC_BE = 1, /* best effort access */
973 MWL8K_WME_AC_VI = 2, /* video access */
974 MWL8K_WME_AC_VO = 3, /* voice access */
975};
976
977/* Transmit packet ACK policy */
978#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 979#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
980
981#define GET_TXQ(_ac) (\
982 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
983 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
984 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
985 MWL8K_WME_AC_BE)
986
a66098da
LB		 987#define MWL8K_TXD_STATUS_OK 0x00000001
988#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
989#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
990#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 991#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 992
993struct mwl8k_tx_desc {
994 __le32 status;
995 __u8 data_rate;
996 __u8 tx_priority;
997 __le16 qos_control;
998 __le32 pkt_phys_addr;
999 __le16 pkt_len;
d89173f2 1000 __u8 dest_MAC_addr[ETH_ALEN];
a66098da
LB		 1001 __le32 next_tx_desc_phys_addr;
1002 __le32 reserved;
1003 __le16 rate_info;
1004 __u8 peer_id;
1005 __u8 tx_frag_cnt;
1006} __attribute__((packed));
1007
1008#define MWL8K_TX_DESCS 128
1009
1010static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1011{
1012 struct mwl8k_priv *priv = hw->priv;
1013 struct mwl8k_tx_queue *txq = priv->txq + index;
1014 int size;
1015 int i;
1016
ce9e2e1b 1017 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
a66098da
LB		 1018 txq->tx_stats.limit = MWL8K_TX_DESCS;
1019 txq->tx_head = 0;
1020 txq->tx_tail = 0;
1021
1022 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1023
1024 txq->tx_desc_area =
1025 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1026 if (txq->tx_desc_area == NULL) {
1027 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1028 wiphy_name(hw->wiphy));
a66098da
LB		 1029 return -ENOMEM;
1030 }
1031 memset(txq->tx_desc_area, 0, size);
1032
1033 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1034 GFP_KERNEL);
1035 if (txq->tx_skb == NULL) {
1036 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1037 wiphy_name(hw->wiphy));
a66098da
LB		 1038 pci_free_consistent(priv->pdev, size,
1039 txq->tx_desc_area, txq->tx_desc_dma);
1040 return -ENOMEM;
1041 }
1042 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1043
1044 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1045 struct mwl8k_tx_desc *tx_desc;
1046 int nexti;
1047
1048 tx_desc = txq->tx_desc_area + i;
1049 nexti = (i + 1) % MWL8K_TX_DESCS;
1050
1051 tx_desc->status = 0;
1052 tx_desc->next_tx_desc_phys_addr =
1053 cpu_to_le32(txq->tx_desc_dma +
1054 nexti * sizeof(*tx_desc));
1055 }
1056
1057 return 0;
1058}
1059
1060static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1061{
1062 iowrite32(MWL8K_H2A_INT_PPA_READY,
1063 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1064 iowrite32(MWL8K_H2A_INT_DUMMY,
1065 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1066 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1067}
1068
a66098da
LB		 1069struct mwl8k_txq_info {
1070 u32 fw_owned;
1071 u32 drv_owned;
1072 u32 unused;
1073 u32 len;
1074 u32 head;
1075 u32 tail;
1076};
1077
1078static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1079 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1080{
1081 int count, desc, status;
1082 struct mwl8k_tx_queue *txq;
1083 struct mwl8k_tx_desc *tx_desc;
1084 int ndescs = 0;
1085
c3f967d3
LB		 1086 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1087
c3f967d3 1088 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da
LB		 1089 txq = priv->txq + count;
1090 txinfo[count].len = txq->tx_stats.len;
1091 txinfo[count].head = txq->tx_head;
1092 txinfo[count].tail = txq->tx_tail;
1093 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1094 tx_desc = txq->tx_desc_area + desc;
1095 status = le32_to_cpu(tx_desc->status);
1096
1097 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1098 txinfo[count].fw_owned++;
1099 else
1100 txinfo[count].drv_owned++;
1101
1102 if (tx_desc->pkt_len == 0)
1103 txinfo[count].unused++;
1104 }
1105 }
a66098da
LB		 1106
1107 return ndescs;
1108}
1109
618952a7 1110/*
88de754a 1111 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1112 */
950d5b01 1113static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1114{
a66098da 1115 struct mwl8k_priv *priv = hw->priv;
88de754a 1116 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1117 u32 count;
1118 unsigned long timeout;
a66098da
LB		 1119
1120 might_sleep();
1121
a66098da 1122 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1123 count = priv->pending_tx_pkts;
1124 if (count)
1125 priv->tx_wait = &tx_wait;
a66098da
LB		 1126 spin_unlock_bh(&priv->tx_lock);
1127
1128 if (count) {
c3f967d3 1129 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1130 int index;
1131 int newcount;
1132
88de754a 1133 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1134 msecs_to_jiffies(5000));
a66098da
LB		 1135 if (timeout)
1136 return 0;
1137
1138 spin_lock_bh(&priv->tx_lock);
1139 priv->tx_wait = NULL;
88de754a
LB		 1140 newcount = priv->pending_tx_pkts;
1141 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1142 spin_unlock_bh(&priv->tx_lock);
1143
618952a7 1144 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1145 __func__, __LINE__, count, newcount);
a66098da 1146
c3f967d3 1147 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1148 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1149 "DRV:%u U:%u\n",
a66098da
LB		 1150 index,
1151 txinfo[index].len,
1152 txinfo[index].head,
1153 txinfo[index].tail,
1154 txinfo[index].fw_owned,
1155 txinfo[index].drv_owned,
1156 txinfo[index].unused);
ce9e2e1b 1157
a66098da
LB		 1158 return -ETIMEDOUT;
1159 }
1160
1161 return 0;
1162}
1163
c23b5a69
LB		 1164#define MWL8K_TXD_SUCCESS(status) \
1165 ((status) & (MWL8K_TXD_STATUS_OK | \
1166 MWL8K_TXD_STATUS_OK_RETRY | \
1167 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1168
1169static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1170{
1171 struct mwl8k_priv *priv = hw->priv;
1172 struct mwl8k_tx_queue *txq = priv->txq + index;
1173 int wake = 0;
1174
1175 while (txq->tx_stats.len > 0) {
1176 int tx;
a66098da
LB		 1177 struct mwl8k_tx_desc *tx_desc;
1178 unsigned long addr;
ce9e2e1b 1179 int size;
a66098da
LB		 1180 struct sk_buff *skb;
1181 struct ieee80211_tx_info *info;
1182 u32 status;
1183
a66098da
LB		 1184 tx = txq->tx_head;
1185 tx_desc = txq->tx_desc_area + tx;
1186
1187 status = le32_to_cpu(tx_desc->status);
1188
1189 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1190 if (!force)
1191 break;
1192 tx_desc->status &=
1193 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1194 }
1195
1196 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1197 BUG_ON(txq->tx_stats.len == 0);
1198 txq->tx_stats.len--;
1199 priv->pending_tx_pkts--;
1200
1201 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1202 size = le16_to_cpu(tx_desc->pkt_len);
76266b2a
LB		 1203 skb = txq->tx_skb[tx];
1204 txq->tx_skb[tx] = NULL;
a66098da
LB		 1205
1206 BUG_ON(skb == NULL);
1207 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1208
76266b2a 1209 mwl8k_remove_dma_header(skb);
a66098da
LB		 1210
1211 /* Mark descriptor as unused */
1212 tx_desc->pkt_phys_addr = 0;
1213 tx_desc->pkt_len = 0;
1214
a66098da
LB		 1215 info = IEEE80211_SKB_CB(skb);
1216 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1217 if (MWL8K_TXD_SUCCESS(status))
a66098da 1218 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1219
1220 ieee80211_tx_status_irqsafe(hw, skb);
1221
618952a7 1222 wake = 1;
a66098da
LB		 1223 }
1224
618952a7 1225 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1226 ieee80211_wake_queue(hw, index);
1227}
1228
1229/* must be called only when the card's transmit is completely halted */
1230static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1231{
1232 struct mwl8k_priv *priv = hw->priv;
1233 struct mwl8k_tx_queue *txq = priv->txq + index;
1234
1235 mwl8k_txq_reclaim(hw, index, 1);
1236
1237 kfree(txq->tx_skb);
1238 txq->tx_skb = NULL;
1239
1240 pci_free_consistent(priv->pdev,
1241 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1242 txq->tx_desc_area, txq->tx_desc_dma);
1243 txq->tx_desc_area = NULL;
1244}
1245
1246static int
1247mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1248{
1249 struct mwl8k_priv *priv = hw->priv;
1250 struct ieee80211_tx_info *tx_info;
23b33906 1251 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1252 struct ieee80211_hdr *wh;
1253 struct mwl8k_tx_queue *txq;
1254 struct mwl8k_tx_desc *tx;
a66098da 1255 dma_addr_t dma;
23b33906
LB		 1256 u32 txstatus;
1257 u8 txdatarate;
1258 u16 qos;
a66098da 1259
23b33906
LB		 1260 wh = (struct ieee80211_hdr *)skb->data;
1261 if (ieee80211_is_data_qos(wh->frame_control))
1262 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1263 else
1264 qos = 0;
a66098da 1265
76266b2a 1266 mwl8k_add_dma_header(skb);
23b33906 1267 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1268
1269 tx_info = IEEE80211_SKB_CB(skb);
1270 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1271
1272 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1273 u16 seqno = mwl8k_vif->seqno;
23b33906 1274
a66098da
LB		 1275 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1276 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1277 mwl8k_vif->seqno = seqno++ % 4096;
1278 }
1279
23b33906
LB		 1280 /* Setup firmware control bit fields for each frame type. */
1281 txstatus = 0;
1282 txdatarate = 0;
1283 if (ieee80211_is_mgmt(wh->frame_control) ||
1284 ieee80211_is_ctl(wh->frame_control)) {
1285 txdatarate = 0;
1286 qos = mwl8k_qos_setbit_eosp(qos);
1287 /* Set Queue size to unspecified */
1288 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1289 } else if (ieee80211_is_data(wh->frame_control)) {
1290 txdatarate = 1;
1291 if (is_multicast_ether_addr(wh->addr1))
1292 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1293
1294 /* Send pkt in an aggregate if AMPDU frame. */
1295 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1296 qos = mwl8k_qos_setbit_ack(qos,
1297 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1298 else
1299 qos = mwl8k_qos_setbit_ack(qos,
1300 MWL8K_TXD_ACK_POLICY_NORMAL);
1301
1302 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1303 qos = mwl8k_qos_setbit_amsdu(qos);
1304 }
a66098da
LB		 1305
1306 dma = pci_map_single(priv->pdev, skb->data,
1307 skb->len, PCI_DMA_TODEVICE);
1308
1309 if (pci_dma_mapping_error(priv->pdev, dma)) {
1310 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1311 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1312 dev_kfree_skb(skb);
a66098da
LB		 1313 return NETDEV_TX_OK;
1314 }
1315
23b33906 1316 spin_lock_bh(&priv->tx_lock);
a66098da 1317
23b33906 1318 txq = priv->txq + index;
a66098da 1319
23b33906
LB		 1320 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1321 txq->tx_skb[txq->tx_tail] = skb;
a66098da 1322
23b33906
LB		 1323 tx = txq->tx_desc_area + txq->tx_tail;
1324 tx->data_rate = txdatarate;
1325 tx->tx_priority = index;
a66098da 1326 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1327 tx->pkt_phys_addr = cpu_to_le32(dma);
1328 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1329 tx->rate_info = 0;
1330 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1331 wmb();
23b33906
LB		 1332 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1333
1334 txq->tx_stats.count++;
a66098da
LB		 1335 txq->tx_stats.len++;
1336 priv->pending_tx_pkts++;
a66098da 1337
23b33906 1338 txq->tx_tail++;
a66098da
LB		 1339 if (txq->tx_tail == MWL8K_TX_DESCS)
1340 txq->tx_tail = 0;
23b33906 1341
a66098da
LB		 1342 if (txq->tx_head == txq->tx_tail)
1343 ieee80211_stop_queue(hw, index);
1344
23b33906 1345 mwl8k_tx_start(priv);
a66098da
LB		 1346
1347 spin_unlock_bh(&priv->tx_lock);
1348
1349 return NETDEV_TX_OK;
1350}
1351
1352
618952a7
LB		 1353/*
1354 * Firmware access.
1355 *
1356 * We have the following requirements for issuing firmware commands:
1357 * - Some commands require that the packet transmit path is idle when
1358 * the command is issued. (For simplicity, we'll just quiesce the
1359 * transmit path for every command.)
1360 * - There are certain sequences of commands that need to be issued to
1361 * the hardware sequentially, with no other intervening commands.
1362 *
1363 * This leads to an implementation of a "firmware lock" as a mutex that
1364 * can be taken recursively, and which is taken by both the low-level
1365 * command submission function (mwl8k_post_cmd) as well as any users of
1366 * that function that require issuing of an atomic sequence of commands,
1367 * and quiesces the transmit path whenever it's taken.
1368 */
1369static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1370{
1371 struct mwl8k_priv *priv = hw->priv;
1372
1373 if (priv->fw_mutex_owner != current) {
1374 int rc;
1375
1376 mutex_lock(&priv->fw_mutex);
1377 ieee80211_stop_queues(hw);
1378
1379 rc = mwl8k_tx_wait_empty(hw);
1380 if (rc) {
1381 ieee80211_wake_queues(hw);
1382 mutex_unlock(&priv->fw_mutex);
1383
1384 return rc;
1385 }
1386
1387 priv->fw_mutex_owner = current;
1388 }
1389
1390 priv->fw_mutex_depth++;
1391
1392 return 0;
1393}
1394
1395static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1396{
1397 struct mwl8k_priv *priv = hw->priv;
1398
1399 if (!--priv->fw_mutex_depth) {
1400 ieee80211_wake_queues(hw);
1401 priv->fw_mutex_owner = NULL;
1402 mutex_unlock(&priv->fw_mutex);
1403 }
1404}
1405
1406
a66098da
LB		 1407/*
1408 * Command processing.
1409 */
1410
1411/* Timeout firmware commands after 2000ms */
1412#define MWL8K_CMD_TIMEOUT_MS 2000
1413
1414static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1415{
1416 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1417 struct mwl8k_priv *priv = hw->priv;
1418 void __iomem *regs = priv->regs;
1419 dma_addr_t dma_addr;
1420 unsigned int dma_size;
1421 int rc;
a66098da
LB		 1422 unsigned long timeout = 0;
1423 u8 buf[32];
1424
c2c357ce 1425 cmd->result = 0xffff;
a66098da
LB		 1426 dma_size = le16_to_cpu(cmd->length);
1427 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1428 PCI_DMA_BIDIRECTIONAL);
1429 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1430 return -ENOMEM;
1431
618952a7 1432 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1433 if (rc) {
1434 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1435 PCI_DMA_BIDIRECTIONAL);
618952a7 1436 return rc;
39a1e42e 1437 }
a66098da 1438
a66098da
LB		 1439 priv->hostcmd_wait = &cmd_wait;
1440 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1441 iowrite32(MWL8K_H2A_INT_DOORBELL,
1442 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1443 iowrite32(MWL8K_H2A_INT_DUMMY,
1444 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1445
1446 timeout = wait_for_completion_timeout(&cmd_wait,
1447 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1448
618952a7
LB		 1449 priv->hostcmd_wait = NULL;
1450
1451 mwl8k_fw_unlock(hw);
1452
37055bd4
LB		 1453 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1454 PCI_DMA_BIDIRECTIONAL);
1455
a66098da 1456 if (!timeout) {
a66098da 1457 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1458 wiphy_name(hw->wiphy),
a66098da
LB		 1459 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1460 MWL8K_CMD_TIMEOUT_MS);
1461 rc = -ETIMEDOUT;
1462 } else {
ce9e2e1b 1463 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1464 if (rc)
1465 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1466 wiphy_name(hw->wiphy),
a66098da 1467 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1468 le16_to_cpu(cmd->result));
a66098da
LB		 1469 }
1470
a66098da
LB		 1471 return rc;
1472}
1473
1474/*
1475 * GET_HW_SPEC.
1476 */
1477struct mwl8k_cmd_get_hw_spec {
1478 struct mwl8k_cmd_pkt header;
1479 __u8 hw_rev;
1480 __u8 host_interface;
1481 __le16 num_mcaddrs;
d89173f2 1482 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1483 __le16 region_code;
1484 __le32 fw_rev;
1485 __le32 ps_cookie;
1486 __le32 caps;
1487 __u8 mcs_bitmap[16];
1488 __le32 rx_queue_ptr;
1489 __le32 num_tx_queues;
1490 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1491 __le32 caps2;
1492 __le32 num_tx_desc_per_queue;
1493 __le32 total_rx_desc;
1494} __attribute__((packed));
1495
1496static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1497{
1498 struct mwl8k_priv *priv = hw->priv;
1499 struct mwl8k_cmd_get_hw_spec *cmd;
1500 int rc;
1501 int i;
1502
1503 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1504 if (cmd == NULL)
1505 return -ENOMEM;
1506
1507 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1508 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1509
1510 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1511 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1512 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
4ff6432e 1513 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da
LB		 1514 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1515 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
4ff6432e
LB		 1516 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1517 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1518
1519 rc = mwl8k_post_cmd(hw, &cmd->header);
1520
1521 if (!rc) {
1522 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1523 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1524 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1525 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1526 }
1527
1528 kfree(cmd);
1529 return rc;
1530}
1531
1532/*
1533 * CMD_MAC_MULTICAST_ADR.
1534 */
1535struct mwl8k_cmd_mac_multicast_adr {
1536 struct mwl8k_cmd_pkt header;
1537 __le16 action;
1538 __le16 numaddr;
ce9e2e1b 1539 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1540};
1541
d5e30845
LB		 1542#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1543#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1544#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1545#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1546
e81cd2d6 1547static struct mwl8k_cmd_pkt *
447ced07 1548__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1549 int mc_count, struct dev_addr_list *mclist)
a66098da 1550{
e81cd2d6 1551 struct mwl8k_priv *priv = hw->priv;
a66098da 1552 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1553 int size;
e81cd2d6 1554
447ced07 1555 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1556 allmulti = 1;
1557 mc_count = 0;
1558 }
e81cd2d6
LB		 1559
1560 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1561
e81cd2d6 1562 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1563 if (cmd == NULL)
e81cd2d6 1564 return NULL;
a66098da
LB		 1565
1566 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1567 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1568 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1569 MWL8K_ENABLE_RX_BROADCAST);
1570
1571 if (allmulti) {
1572 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1573 } else if (mc_count) {
1574 int i;
1575
1576 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1577 cmd->numaddr = cpu_to_le16(mc_count);
1578 for (i = 0; i < mc_count && mclist; i++) {
1579 if (mclist->da_addrlen != ETH_ALEN) {
1580 kfree(cmd);
1581 return NULL;
1582 }
1583 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1584 mclist = mclist->next;
a66098da 1585 }
a66098da
LB		 1586 }
1587
e81cd2d6 1588 return &cmd->header;
a66098da
LB		 1589}
1590
1591/*
1592 * CMD_802_11_GET_STAT.
1593 */
1594struct mwl8k_cmd_802_11_get_stat {
1595 struct mwl8k_cmd_pkt header;
a66098da
LB		 1596 __le32 stats[64];
1597} __attribute__((packed));
1598
1599#define MWL8K_STAT_ACK_FAILURE 9
1600#define MWL8K_STAT_RTS_FAILURE 12
1601#define MWL8K_STAT_FCS_ERROR 24
1602#define MWL8K_STAT_RTS_SUCCESS 11
1603
1604static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1605 struct ieee80211_low_level_stats *stats)
1606{
1607 struct mwl8k_cmd_802_11_get_stat *cmd;
1608 int rc;
1609
1610 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1611 if (cmd == NULL)
1612 return -ENOMEM;
1613
1614 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1615 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1616
1617 rc = mwl8k_post_cmd(hw, &cmd->header);
1618 if (!rc) {
1619 stats->dot11ACKFailureCount =
1620 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1621 stats->dot11RTSFailureCount =
1622 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1623 stats->dot11FCSErrorCount =
1624 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1625 stats->dot11RTSSuccessCount =
1626 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1627 }
1628 kfree(cmd);
1629
1630 return rc;
1631}
1632
1633/*
1634 * CMD_802_11_RADIO_CONTROL.
1635 */
1636struct mwl8k_cmd_802_11_radio_control {
1637 struct mwl8k_cmd_pkt header;
1638 __le16 action;
1639 __le16 control;
1640 __le16 radio_on;
1641} __attribute__((packed));
1642
c46563b7
LB		 1643static int
1644mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1645{
1646 struct mwl8k_priv *priv = hw->priv;
1647 struct mwl8k_cmd_802_11_radio_control *cmd;
1648 int rc;
1649
c46563b7 1650 if (enable == priv->radio_on && !force)
a66098da
LB		 1651 return 0;
1652
a66098da
LB		 1653 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1654 if (cmd == NULL)
1655 return -ENOMEM;
1656
1657 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1658 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1659 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1660 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1661 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1662
1663 rc = mwl8k_post_cmd(hw, &cmd->header);
1664 kfree(cmd);
1665
1666 if (!rc)
c46563b7 1667 priv->radio_on = enable;
a66098da
LB		 1668
1669 return rc;
1670}
1671
c46563b7
LB		 1672static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1673{
1674 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1675}
1676
1677static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1678{
1679 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1680}
1681
a66098da
LB		 1682static int
1683mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1684{
1685 struct mwl8k_priv *priv;
1686
1687 if (hw == NULL || hw->priv == NULL)
1688 return -EINVAL;
1689 priv = hw->priv;
1690
68ce3884 1691 priv->radio_short_preamble = short_preamble;
a66098da 1692
c46563b7 1693 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1694}
1695
1696/*
1697 * CMD_802_11_RF_TX_POWER.
1698 */
1699#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1700
1701struct mwl8k_cmd_802_11_rf_tx_power {
1702 struct mwl8k_cmd_pkt header;
1703 __le16 action;
1704 __le16 support_level;
1705 __le16 current_level;
1706 __le16 reserved;
1707 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1708} __attribute__((packed));
1709
1710static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1711{
1712 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1713 int rc;
1714
1715 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1716 if (cmd == NULL)
1717 return -ENOMEM;
1718
1719 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1720 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1721 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1722 cmd->support_level = cpu_to_le16(dBm);
1723
1724 rc = mwl8k_post_cmd(hw, &cmd->header);
1725 kfree(cmd);
1726
1727 return rc;
1728}
1729
1730/*
1731 * CMD_SET_PRE_SCAN.
1732 */
1733struct mwl8k_cmd_set_pre_scan {
1734 struct mwl8k_cmd_pkt header;
1735} __attribute__((packed));
1736
1737static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1738{
1739 struct mwl8k_cmd_set_pre_scan *cmd;
1740 int rc;
1741
1742 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1743 if (cmd == NULL)
1744 return -ENOMEM;
1745
1746 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1747 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1748
1749 rc = mwl8k_post_cmd(hw, &cmd->header);
1750 kfree(cmd);
1751
1752 return rc;
1753}
1754
1755/*
1756 * CMD_SET_POST_SCAN.
1757 */
1758struct mwl8k_cmd_set_post_scan {
1759 struct mwl8k_cmd_pkt header;
1760 __le32 isibss;
d89173f2 1761 __u8 bssid[ETH_ALEN];
a66098da
LB		 1762} __attribute__((packed));
1763
1764static int
ce9e2e1b 1765mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 1766{
1767 struct mwl8k_cmd_set_post_scan *cmd;
1768 int rc;
1769
1770 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1771 if (cmd == NULL)
1772 return -ENOMEM;
1773
1774 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1775 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1776 cmd->isibss = 0;
d89173f2 1777 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 1778
1779 rc = mwl8k_post_cmd(hw, &cmd->header);
1780 kfree(cmd);
1781
1782 return rc;
1783}
1784
1785/*
1786 * CMD_SET_RF_CHANNEL.
1787 */
1788struct mwl8k_cmd_set_rf_channel {
1789 struct mwl8k_cmd_pkt header;
1790 __le16 action;
1791 __u8 current_channel;
1792 __le32 channel_flags;
1793} __attribute__((packed));
1794
1795static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1796 struct ieee80211_channel *channel)
1797{
1798 struct mwl8k_cmd_set_rf_channel *cmd;
1799 int rc;
1800
1801 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1802 if (cmd == NULL)
1803 return -ENOMEM;
1804
1805 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1806 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1807 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1808 cmd->current_channel = channel->hw_value;
1809 if (channel->band == IEEE80211_BAND_2GHZ)
1810 cmd->channel_flags = cpu_to_le32(0x00000081);
1811 else
1812 cmd->channel_flags = cpu_to_le32(0x00000000);
1813
1814 rc = mwl8k_post_cmd(hw, &cmd->header);
1815 kfree(cmd);
1816
1817 return rc;
1818}
1819
1820/*
1821 * CMD_SET_SLOT.
1822 */
1823struct mwl8k_cmd_set_slot {
1824 struct mwl8k_cmd_pkt header;
1825 __le16 action;
1826 __u8 short_slot;
1827} __attribute__((packed));
1828
5539bb51 1829static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 1830{
1831 struct mwl8k_cmd_set_slot *cmd;
1832 int rc;
1833
1834 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1835 if (cmd == NULL)
1836 return -ENOMEM;
1837
1838 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1839 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1840 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 1841 cmd->short_slot = short_slot_time;
a66098da
LB		 1842
1843 rc = mwl8k_post_cmd(hw, &cmd->header);
1844 kfree(cmd);
1845
1846 return rc;
1847}
1848
1849/*
1850 * CMD_MIMO_CONFIG.
1851 */
1852struct mwl8k_cmd_mimo_config {
1853 struct mwl8k_cmd_pkt header;
1854 __le32 action;
1855 __u8 rx_antenna_map;
1856 __u8 tx_antenna_map;
1857} __attribute__((packed));
1858
1859static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1860{
1861 struct mwl8k_cmd_mimo_config *cmd;
1862 int rc;
1863
1864 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1865 if (cmd == NULL)
1866 return -ENOMEM;
1867
1868 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1869 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1870 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1871 cmd->rx_antenna_map = rx;
1872 cmd->tx_antenna_map = tx;
1873
1874 rc = mwl8k_post_cmd(hw, &cmd->header);
1875 kfree(cmd);
1876
1877 return rc;
1878}
1879
1880/*
1881 * CMD_ENABLE_SNIFFER.
1882 */
1883struct mwl8k_cmd_enable_sniffer {
1884 struct mwl8k_cmd_pkt header;
1885 __le32 action;
1886} __attribute__((packed));
1887
1888static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1889{
1890 struct mwl8k_cmd_enable_sniffer *cmd;
1891 int rc;
1892
1893 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1894 if (cmd == NULL)
1895 return -ENOMEM;
1896
1897 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1898 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 1899 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 1900
1901 rc = mwl8k_post_cmd(hw, &cmd->header);
1902 kfree(cmd);
1903
1904 return rc;
1905}
1906
32060e1b
LB		 1907/*
1908 * CMD_SET_MAC_ADDR.
1909 */
1910struct mwl8k_cmd_set_mac_addr {
1911 struct mwl8k_cmd_pkt header;
1912 __u8 mac_addr[ETH_ALEN];
1913} __attribute__((packed));
1914
1915static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1916{
1917 struct mwl8k_cmd_set_mac_addr *cmd;
1918 int rc;
1919
1920 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1921 if (cmd == NULL)
1922 return -ENOMEM;
1923
1924 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1925 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1926 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1927
1928 rc = mwl8k_post_cmd(hw, &cmd->header);
1929 kfree(cmd);
1930
1931 return rc;
1932}
1933
1934
a66098da 1935/*
ce9e2e1b 1936 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 1937 */
1938struct mwl8k_cmd_set_rate_adapt_mode {
1939 struct mwl8k_cmd_pkt header;
1940 __le16 action;
1941 __le16 mode;
1942} __attribute__((packed));
1943
1944static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1945{
1946 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1947 int rc;
1948
1949 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1950 if (cmd == NULL)
1951 return -ENOMEM;
1952
1953 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1954 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1955 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1956 cmd->mode = cpu_to_le16(mode);
1957
1958 rc = mwl8k_post_cmd(hw, &cmd->header);
1959 kfree(cmd);
1960
1961 return rc;
1962}
1963
1964/*
1965 * CMD_SET_WMM_MODE.
1966 */
1967struct mwl8k_cmd_set_wmm {
1968 struct mwl8k_cmd_pkt header;
1969 __le16 action;
1970} __attribute__((packed));
1971
1972static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1973{
1974 struct mwl8k_priv *priv = hw->priv;
1975 struct mwl8k_cmd_set_wmm *cmd;
1976 int rc;
1977
1978 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1979 if (cmd == NULL)
1980 return -ENOMEM;
1981
1982 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1983 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 1984 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 1985
1986 rc = mwl8k_post_cmd(hw, &cmd->header);
1987 kfree(cmd);
1988
1989 if (!rc)
0439b1f5 1990 priv->wmm_enabled = enable;
a66098da
LB		 1991
1992 return rc;
1993}
1994
1995/*
1996 * CMD_SET_RTS_THRESHOLD.
1997 */
1998struct mwl8k_cmd_rts_threshold {
1999 struct mwl8k_cmd_pkt header;
2000 __le16 action;
2001 __le16 threshold;
2002} __attribute__((packed));
2003
2004static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2005 u16 action, u16 threshold)
a66098da
LB		 2006{
2007 struct mwl8k_cmd_rts_threshold *cmd;
2008 int rc;
2009
2010 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2011 if (cmd == NULL)
2012 return -ENOMEM;
2013
2014 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2015 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2016 cmd->action = cpu_to_le16(action);
733d3067 2017 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2018
2019 rc = mwl8k_post_cmd(hw, &cmd->header);
2020 kfree(cmd);
2021
2022 return rc;
2023}
2024
2025/*
2026 * CMD_SET_EDCA_PARAMS.
2027 */
2028struct mwl8k_cmd_set_edca_params {
2029 struct mwl8k_cmd_pkt header;
2030
2031 /* See MWL8K_SET_EDCA_XXX below */
2032 __le16 action;
2033
2034 /* TX opportunity in units of 32 us */
2035 __le16 txop;
2036
2037 /* Log exponent of max contention period: 0...15*/
2038 __u8 log_cw_max;
2039
2040 /* Log exponent of min contention period: 0...15 */
2041 __u8 log_cw_min;
2042
2043 /* Adaptive interframe spacing in units of 32us */
2044 __u8 aifs;
2045
2046 /* TX queue to configure */
2047 __u8 txq;
2048} __attribute__((packed));
2049
a66098da
LB		 2050#define MWL8K_SET_EDCA_CW 0x01
2051#define MWL8K_SET_EDCA_TXOP 0x02
2052#define MWL8K_SET_EDCA_AIFS 0x04
2053
2054#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2055 MWL8K_SET_EDCA_TXOP | \
2056 MWL8K_SET_EDCA_AIFS)
2057
2058static int
2059mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2060 __u16 cw_min, __u16 cw_max,
2061 __u8 aifs, __u16 txop)
2062{
2063 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2064 int rc;
2065
2066 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2067 if (cmd == NULL)
2068 return -ENOMEM;
2069
a66098da
LB		 2070 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2071 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2072 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2073 cmd->txop = cpu_to_le16(txop);
ce9e2e1b
LB		 2074 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2075 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
a66098da
LB		 2076 cmd->aifs = aifs;
2077 cmd->txq = qnum;
2078
2079 rc = mwl8k_post_cmd(hw, &cmd->header);
2080 kfree(cmd);
2081
2082 return rc;
2083}
2084
2085/*
2086 * CMD_FINALIZE_JOIN.
2087 */
2088
2089/* FJ beacon buffer size is compiled into the firmware. */
2090#define MWL8K_FJ_BEACON_MAXLEN 128
2091
2092struct mwl8k_cmd_finalize_join {
2093 struct mwl8k_cmd_pkt header;
2094 __le32 sleep_interval; /* Number of beacon periods to sleep */
2095 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2096} __attribute__((packed));
2097
2098static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2099 __u16 framelen, __u16 dtim)
2100{
2101 struct mwl8k_cmd_finalize_join *cmd;
2102 struct ieee80211_mgmt *payload = frame;
2103 u16 hdrlen;
2104 u32 payload_len;
2105 int rc;
2106
2107 if (frame == NULL)
2108 return -EINVAL;
2109
2110 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2111 if (cmd == NULL)
2112 return -ENOMEM;
2113
2114 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2115 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2116 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2117
2118 hdrlen = ieee80211_hdrlen(payload->frame_control);
2119
2120 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2121
2122 /* XXX TBD Might just have to abort and return an error */
2123 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2124 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2125 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2126 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2127
ce9e2e1b
LB		 2128 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2129 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2130
2131 if (payload && payload_len)
2132 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2133
2134 rc = mwl8k_post_cmd(hw, &cmd->header);
2135 kfree(cmd);
2136 return rc;
2137}
2138
2139/*
2140 * CMD_UPDATE_STADB.
2141 */
2142struct mwl8k_cmd_update_sta_db {
2143 struct mwl8k_cmd_pkt header;
2144
2145 /* See STADB_ACTION_TYPE */
2146 __le32 action;
2147
2148 /* Peer MAC address */
d89173f2 2149 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2150
2151 __le32 reserved;
2152
2153 /* Peer info - valid during add/update. */
2154 struct peer_capability_info peer_info;
2155} __attribute__((packed));
2156
2157static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2158 struct ieee80211_vif *vif, __u32 action)
2159{
2160 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2161 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2162 struct mwl8k_cmd_update_sta_db *cmd;
2163 struct peer_capability_info *peer_info;
2164 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2165 int rc;
2166 __u8 count, *rates;
2167
2168 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2169 if (cmd == NULL)
2170 return -ENOMEM;
2171
2172 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2173 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2174
2175 cmd->action = cpu_to_le32(action);
2176 peer_info = &cmd->peer_info;
d89173f2 2177 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2178
2179 switch (action) {
2180 case MWL8K_STA_DB_ADD_ENTRY:
2181 case MWL8K_STA_DB_MODIFY_ENTRY:
2182 /* Build peer_info block */
2183 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2184 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2185 peer_info->interop = 1;
2186 peer_info->amsdu_enabled = 0;
2187
2188 rates = peer_info->legacy_rates;
ce9e2e1b 2189 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2190 rates[count] = bitrates[count].hw_value;
2191
2192 rc = mwl8k_post_cmd(hw, &cmd->header);
2193 if (rc == 0)
2194 mv_vif->peer_id = peer_info->station_id;
2195
2196 break;
2197
2198 case MWL8K_STA_DB_DEL_ENTRY:
2199 case MWL8K_STA_DB_FLUSH:
2200 default:
2201 rc = mwl8k_post_cmd(hw, &cmd->header);
2202 if (rc == 0)
2203 mv_vif->peer_id = 0;
2204 break;
2205 }
2206 kfree(cmd);
2207
2208 return rc;
2209}
2210
2211/*
2212 * CMD_SET_AID.
2213 */
a66098da
LB		 2214#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2215
2216#define MWL8K_FRAME_PROT_DISABLED 0x00
2217#define MWL8K_FRAME_PROT_11G 0x07
2218#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2219#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2220
2221struct mwl8k_cmd_update_set_aid {
2222 struct mwl8k_cmd_pkt header;
2223 __le16 aid;
2224
2225 /* AP's MAC address (BSSID) */
d89173f2 2226 __u8 bssid[ETH_ALEN];
a66098da
LB		 2227 __le16 protection_mode;
2228 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2229} __attribute__((packed));
2230
2231static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2232 struct ieee80211_vif *vif)
2233{
2234 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2235 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2236 struct mwl8k_cmd_update_set_aid *cmd;
2237 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2238 int count;
2239 u16 prot_mode;
2240 int rc;
2241
2242 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2243 if (cmd == NULL)
2244 return -ENOMEM;
2245
2246 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2247 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2248 cmd->aid = cpu_to_le16(info->aid);
2249
d89173f2 2250 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2251
a66098da
LB		 2252 if (info->use_cts_prot) {
2253 prot_mode = MWL8K_FRAME_PROT_11G;
2254 } else {
9ed6bcce 2255 switch (info->ht_operation_mode &
a66098da
LB		 2256 IEEE80211_HT_OP_MODE_PROTECTION) {
2257 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2258 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2259 break;
2260 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2261 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2262 break;
2263 default:
2264 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2265 break;
2266 }
2267 }
a66098da
LB		 2268 cmd->protection_mode = cpu_to_le16(prot_mode);
2269
2270 for (count = 0; count < mv_vif->legacy_nrates; count++)
2271 cmd->supp_rates[count] = bitrates[count].hw_value;
2272
2273 rc = mwl8k_post_cmd(hw, &cmd->header);
2274 kfree(cmd);
2275
2276 return rc;
2277}
2278
2279/*
2280 * CMD_SET_RATE.
2281 */
2282struct mwl8k_cmd_update_rateset {
2283 struct mwl8k_cmd_pkt header;
2284 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2285
2286 /* Bitmap for supported MCS codes. */
2287 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2288 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2289} __attribute__((packed));
2290
2291static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2292 struct ieee80211_vif *vif)
2293{
2294 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2295 struct mwl8k_cmd_update_rateset *cmd;
2296 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2297 int count;
2298 int rc;
2299
2300 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2301 if (cmd == NULL)
2302 return -ENOMEM;
2303
2304 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2305 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2306
2307 for (count = 0; count < mv_vif->legacy_nrates; count++)
2308 cmd->legacy_rates[count] = bitrates[count].hw_value;
2309
2310 rc = mwl8k_post_cmd(hw, &cmd->header);
2311 kfree(cmd);
2312
2313 return rc;
2314}
2315
2316/*
2317 * CMD_USE_FIXED_RATE.
2318 */
2319#define MWL8K_RATE_TABLE_SIZE 8
2320#define MWL8K_UCAST_RATE 0
a66098da
LB		 2321#define MWL8K_USE_AUTO_RATE 0x0002
2322
2323struct mwl8k_rate_entry {
2324 /* Set to 1 if HT rate, 0 if legacy. */
2325 __le32 is_ht_rate;
2326
2327 /* Set to 1 to use retry_count field. */
2328 __le32 enable_retry;
2329
2330 /* Specified legacy rate or MCS. */
2331 __le32 rate;
2332
2333 /* Number of allowed retries. */
2334 __le32 retry_count;
2335} __attribute__((packed));
2336
2337struct mwl8k_rate_table {
2338 /* 1 to allow specified rate and below */
2339 __le32 allow_rate_drop;
2340 __le32 num_rates;
2341 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2342} __attribute__((packed));
2343
2344struct mwl8k_cmd_use_fixed_rate {
2345 struct mwl8k_cmd_pkt header;
2346 __le32 action;
2347 struct mwl8k_rate_table rate_table;
2348
2349 /* Unicast, Broadcast or Multicast */
2350 __le32 rate_type;
2351 __le32 reserved1;
2352 __le32 reserved2;
2353} __attribute__((packed));
2354
2355static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2356 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2357{
2358 struct mwl8k_cmd_use_fixed_rate *cmd;
2359 int count;
2360 int rc;
2361
2362 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2363 if (cmd == NULL)
2364 return -ENOMEM;
2365
2366 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2367 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2368
2369 cmd->action = cpu_to_le32(action);
2370 cmd->rate_type = cpu_to_le32(rate_type);
2371
2372 if (rate_table != NULL) {
c2c357ce
LB		 2373 /*
2374 * Copy over each field manually so that endian
2375 * conversion can be done.
2376 */
a66098da
LB		 2377 cmd->rate_table.allow_rate_drop =
2378 cpu_to_le32(rate_table->allow_rate_drop);
2379 cmd->rate_table.num_rates =
2380 cpu_to_le32(rate_table->num_rates);
2381
2382 for (count = 0; count < rate_table->num_rates; count++) {
2383 struct mwl8k_rate_entry *dst =
2384 &cmd->rate_table.rate_entry[count];
2385 struct mwl8k_rate_entry *src =
2386 &rate_table->rate_entry[count];
2387
2388 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2389 dst->enable_retry = cpu_to_le32(src->enable_retry);
2390 dst->rate = cpu_to_le32(src->rate);
2391 dst->retry_count = cpu_to_le32(src->retry_count);
2392 }
2393 }
2394
2395 rc = mwl8k_post_cmd(hw, &cmd->header);
2396 kfree(cmd);
2397
2398 return rc;
2399}
2400
2401
2402/*
2403 * Interrupt handling.
2404 */
2405static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2406{
2407 struct ieee80211_hw *hw = dev_id;
2408 struct mwl8k_priv *priv = hw->priv;
2409 u32 status;
2410
2411 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2412 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2413
a66098da
LB		 2414 if (!status)
2415 return IRQ_NONE;
2416
2417 if (status & MWL8K_A2H_INT_TX_DONE)
2418 tasklet_schedule(&priv->tx_reclaim_task);
2419
2420 if (status & MWL8K_A2H_INT_RX_READY) {
2421 while (rxq_process(hw, 0, 1))
2422 rxq_refill(hw, 0, 1);
2423 }
2424
2425 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2426 if (priv->hostcmd_wait != NULL)
a66098da 2427 complete(priv->hostcmd_wait);
a66098da
LB		 2428 }
2429
2430 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2431 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2432 priv->radio_on && priv->pending_tx_pkts)
618952a7 2433 mwl8k_tx_start(priv);
a66098da
LB		 2434 }
2435
2436 return IRQ_HANDLED;
2437}
2438
2439
2440/*
2441 * Core driver operations.
2442 */
2443static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2444{
2445 struct mwl8k_priv *priv = hw->priv;
2446 int index = skb_get_queue_mapping(skb);
2447 int rc;
2448
2449 if (priv->current_channel == NULL) {
2450 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2451 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2452 dev_kfree_skb(skb);
2453 return NETDEV_TX_OK;
2454 }
2455
2456 rc = mwl8k_txq_xmit(hw, index, skb);
2457
2458 return rc;
2459}
2460
a66098da
LB		 2461static int mwl8k_start(struct ieee80211_hw *hw)
2462{
a66098da
LB		 2463 struct mwl8k_priv *priv = hw->priv;
2464 int rc;
2465
a66098da
LB		 2466 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2467 IRQF_SHARED, MWL8K_NAME, hw);
2468 if (rc) {
2469 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2470 wiphy_name(hw->wiphy));
2ec610cb 2471 return -EIO;
a66098da
LB		 2472 }
2473
2ec610cb
LB		 2474 /* Enable tx reclaim tasklet */
2475 tasklet_enable(&priv->tx_reclaim_task);
2476
a66098da 2477 /* Enable interrupts */
c23b5a69 2478 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2479
2ec610cb
LB		 2480 rc = mwl8k_fw_lock(hw);
2481 if (!rc) {
2482 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2483
2ec610cb
LB		 2484 if (!rc)
2485 rc = mwl8k_cmd_set_pre_scan(hw);
a66098da 2486
2ec610cb
LB		 2487 if (!rc)
2488 rc = mwl8k_cmd_set_post_scan(hw,
2489 "\x00\x00\x00\x00\x00\x00");
2490
2491 if (!rc)
2492 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2493
2ec610cb
LB		 2494 if (!rc)
2495 rc = mwl8k_set_wmm(hw, 0);
a66098da 2496
2ec610cb
LB		 2497 if (!rc)
2498 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2499
2ec610cb
LB		 2500 mwl8k_fw_unlock(hw);
2501 }
2502
2503 if (rc) {
2504 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2505 free_irq(priv->pdev->irq, hw);
2506 tasklet_disable(&priv->tx_reclaim_task);
2507 }
a66098da
LB		 2508
2509 return rc;
2510}
2511
a66098da
LB		 2512static void mwl8k_stop(struct ieee80211_hw *hw)
2513{
a66098da
LB		 2514 struct mwl8k_priv *priv = hw->priv;
2515 int i;
2516
d3cea0b8 2517 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2518
2519 ieee80211_stop_queues(hw);
2520
a66098da 2521 /* Disable interrupts */
a66098da 2522 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2523 free_irq(priv->pdev->irq, hw);
2524
2525 /* Stop finalize join worker */
2526 cancel_work_sync(&priv->finalize_join_worker);
2527 if (priv->beacon_skb != NULL)
2528 dev_kfree_skb(priv->beacon_skb);
2529
2530 /* Stop tx reclaim tasklet */
2531 tasklet_disable(&priv->tx_reclaim_task);
2532
a66098da
LB		 2533 /* Return all skbs to mac80211 */
2534 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2535 mwl8k_txq_reclaim(hw, i, 1);
2536}
2537
2538static int mwl8k_add_interface(struct ieee80211_hw *hw,
2539 struct ieee80211_if_init_conf *conf)
2540{
2541 struct mwl8k_priv *priv = hw->priv;
2542 struct mwl8k_vif *mwl8k_vif;
2543
2544 /*
2545 * We only support one active interface at a time.
2546 */
2547 if (priv->vif != NULL)
2548 return -EBUSY;
2549
2550 /*
2551 * We only support managed interfaces for now.
2552 */
240e86ef 2553 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2554 return -EINVAL;
2555
2556 /* Clean out driver private area */
2557 mwl8k_vif = MWL8K_VIF(conf->vif);
2558 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2559
32060e1b
LB		 2560 /* Set and save the mac address */
2561 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2562 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2563
2564 /* Back pointer to parent config block */
2565 mwl8k_vif->priv = priv;
2566
2567 /* Setup initial PHY parameters */
ce9e2e1b 2568 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2569 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2570 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2571
2572 /* Set Initial sequence number to zero */
2573 mwl8k_vif->seqno = 0;
2574
2575 priv->vif = conf->vif;
2576 priv->current_channel = NULL;
2577
2578 return 0;
2579}
2580
2581static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2582 struct ieee80211_if_init_conf *conf)
2583{
2584 struct mwl8k_priv *priv = hw->priv;
2585
2586 if (priv->vif == NULL)
2587 return;
2588
32060e1b
LB		 2589 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2590
a66098da
LB		 2591 priv->vif = NULL;
2592}
2593
ee03a932 2594static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2595{
a66098da
LB		 2596 struct ieee80211_conf *conf = &hw->conf;
2597 struct mwl8k_priv *priv = hw->priv;
ee03a932 2598 int rc;
a66098da 2599
7595d67a
LB		 2600 if (conf->flags & IEEE80211_CONF_IDLE) {
2601 mwl8k_cmd_802_11_radio_disable(hw);
2602 priv->current_channel = NULL;
ee03a932 2603 return 0;
7595d67a
LB		 2604 }
2605
ee03a932
LB		 2606 rc = mwl8k_fw_lock(hw);
2607 if (rc)
2608 return rc;
a66098da 2609
ee03a932
LB		 2610 rc = mwl8k_cmd_802_11_radio_enable(hw);
2611 if (rc)
2612 goto out;
a66098da 2613
ee03a932
LB		 2614 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2615 if (rc)
2616 goto out;
2617
2618 priv->current_channel = conf->channel;
a66098da
LB		 2619
2620 if (conf->power_level > 18)
2621 conf->power_level = 18;
ee03a932
LB		 2622 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2623 if (rc)
2624 goto out;
a66098da
LB		 2625
2626 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2627 rc = -EINVAL;
2628
ee03a932
LB		 2629out:
2630 mwl8k_fw_unlock(hw);
a66098da 2631
ee03a932 2632 return rc;
a66098da
LB		 2633}
2634
3a980d0a
LB		 2635static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2636 struct ieee80211_vif *vif,
2637 struct ieee80211_bss_conf *info,
2638 u32 changed)
a66098da 2639{
a66098da
LB		 2640 struct mwl8k_priv *priv = hw->priv;
2641 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 2642 int rc;
2643
2644 if (changed & BSS_CHANGED_BSSID)
2645 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2646
2647 if ((changed & BSS_CHANGED_ASSOC) == 0)
2648 return;
a66098da 2649
a66098da
LB		 2650 priv->capture_beacon = false;
2651
3a980d0a 2652 rc = mwl8k_fw_lock(hw);
942457d6 2653 if (rc)
3a980d0a
LB		 2654 return;
2655
a66098da
LB		 2656 if (info->assoc) {
2657 memcpy(&mwl8k_vif->bss_info, info,
2658 sizeof(struct ieee80211_bss_conf));
2659
2660 /* Install rates */
3a980d0a
LB		 2661 rc = mwl8k_update_rateset(hw, vif);
2662 if (rc)
2663 goto out;
a66098da
LB		 2664
2665 /* Turn on rate adaptation */
3a980d0a
LB		 2666 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2667 MWL8K_UCAST_RATE, NULL);
2668 if (rc)
2669 goto out;
a66098da
LB		 2670
2671 /* Set radio preamble */
3a980d0a
LB		 2672 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2673 if (rc)
2674 goto out;
a66098da
LB		 2675
2676 /* Set slot time */
3a980d0a
LB		 2677 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2678 if (rc)
2679 goto out;
a66098da
LB		 2680
2681 /* Update peer rate info */
3a980d0a
LB		 2682 rc = mwl8k_cmd_update_sta_db(hw, vif,
2683 MWL8K_STA_DB_MODIFY_ENTRY);
2684 if (rc)
2685 goto out;
a66098da
LB		 2686
2687 /* Set AID */
3a980d0a
LB		 2688 rc = mwl8k_cmd_set_aid(hw, vif);
2689 if (rc)
2690 goto out;
a66098da
LB		 2691
2692 /*
2693 * Finalize the join. Tell rx handler to process
2694 * next beacon from our BSSID.
2695 */
d89173f2 2696 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 2697 priv->capture_beacon = true;
2698 } else {
3a980d0a 2699 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 2700 memset(&mwl8k_vif->bss_info, 0,
2701 sizeof(struct ieee80211_bss_conf));
d89173f2 2702 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 2703 }
2704
3a980d0a
LB		 2705out:
2706 mwl8k_fw_unlock(hw);
a66098da
LB		 2707}
2708
e81cd2d6
LB		 2709static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2710 int mc_count, struct dev_addr_list *mclist)
2711{
2712 struct mwl8k_cmd_pkt *cmd;
2713
447ced07
LB		 2714 /*
2715 * Synthesize and return a command packet that programs the
2716 * hardware multicast address filter. At this point we don't
2717 * know whether FIF_ALLMULTI is being requested, but if it is,
2718 * we'll end up throwing this packet away and creating a new
2719 * one in mwl8k_configure_filter().
2720 */
2721 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 2722
2723 return (unsigned long)cmd;
2724}
2725
e6935ea1
LB		 2726static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2727 unsigned int changed_flags,
2728 unsigned int *total_flags,
2729 u64 multicast)
2730{
2731 struct mwl8k_priv *priv = hw->priv;
447ced07 2732 struct mwl8k_cmd_pkt *cmd;
a66098da 2733
e6935ea1 2734 /* Clear unsupported feature flags */
447ced07 2735 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 2736
e6935ea1
LB		 2737 if (mwl8k_fw_lock(hw))
2738 return;
a66098da 2739
e6935ea1 2740 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 2741 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2742 /*
2743 * Disable the BSS filter.
2744 */
e6935ea1 2745 mwl8k_cmd_set_pre_scan(hw);
77165d88 2746 } else {
a94cc97e
LB		 2747 u8 *bssid;
2748
77165d88
LB		 2749 /*
2750 * Enable the BSS filter.
2751 *
2752 * If there is an active STA interface, use that
2753 * interface's BSSID, otherwise use a dummy one
2754 * (where the OUI part needs to be nonzero for
2755 * the BSSID to be accepted by POST_SCAN).
2756 */
2757 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 2758 if (priv->vif != NULL)
2759 bssid = MWL8K_VIF(priv->vif)->bssid;
2760
e6935ea1 2761 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 2762 }
2763 }
2764
447ced07
LB		 2765 cmd = (void *)(unsigned long)multicast;
2766
2767 /*
2768 * If FIF_ALLMULTI is being requested, throw away the command
2769 * packet that ->prepare_multicast() built and replace it with
2770 * a command packet that enables reception of all multicast
2771 * packets.
2772 */
2773 if (*total_flags & FIF_ALLMULTI) {
2774 kfree(cmd);
2775 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2776 }
2777
2778 if (cmd != NULL) {
2779 mwl8k_post_cmd(hw, cmd);
2780 kfree(cmd);
e6935ea1 2781 }
a66098da 2782
e6935ea1 2783 mwl8k_fw_unlock(hw);
a66098da
LB		 2784}
2785
a66098da
LB		 2786static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2787{
733d3067 2788 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 2789}
2790
a66098da
LB		 2791static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2792 const struct ieee80211_tx_queue_params *params)
2793{
3e4f542c 2794 struct mwl8k_priv *priv = hw->priv;
a66098da 2795 int rc;
a66098da 2796
3e4f542c
LB		 2797 rc = mwl8k_fw_lock(hw);
2798 if (!rc) {
2799 if (!priv->wmm_enabled)
2800 rc = mwl8k_set_wmm(hw, 1);
a66098da 2801
3e4f542c
LB		 2802 if (!rc)
2803 rc = mwl8k_set_edca_params(hw, queue,
2804 params->cw_min,
2805 params->cw_max,
2806 params->aifs,
2807 params->txop);
2808
2809 mwl8k_fw_unlock(hw);
a66098da 2810 }
3e4f542c 2811
a66098da
LB		 2812 return rc;
2813}
2814
2815static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2816 struct ieee80211_tx_queue_stats *stats)
2817{
2818 struct mwl8k_priv *priv = hw->priv;
2819 struct mwl8k_tx_queue *txq;
2820 int index;
2821
2822 spin_lock_bh(&priv->tx_lock);
2823 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2824 txq = priv->txq + index;
2825 memcpy(&stats[index], &txq->tx_stats,
2826 sizeof(struct ieee80211_tx_queue_stats));
2827 }
2828 spin_unlock_bh(&priv->tx_lock);
a66098da 2829
954ef509 2830 return 0;
a66098da
LB		 2831}
2832
2833static int mwl8k_get_stats(struct ieee80211_hw *hw,
2834 struct ieee80211_low_level_stats *stats)
2835{
954ef509 2836 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 2837}
2838
2839static const struct ieee80211_ops mwl8k_ops = {
2840 .tx = mwl8k_tx,
2841 .start = mwl8k_start,
2842 .stop = mwl8k_stop,
2843 .add_interface = mwl8k_add_interface,
2844 .remove_interface = mwl8k_remove_interface,
2845 .config = mwl8k_config,
a66098da 2846 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 2847 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 2848 .configure_filter = mwl8k_configure_filter,
2849 .set_rts_threshold = mwl8k_set_rts_threshold,
2850 .conf_tx = mwl8k_conf_tx,
2851 .get_tx_stats = mwl8k_get_tx_stats,
2852 .get_stats = mwl8k_get_stats,
2853};
2854
2855static void mwl8k_tx_reclaim_handler(unsigned long data)
2856{
2857 int i;
2858 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2859 struct mwl8k_priv *priv = hw->priv;
2860
2861 spin_lock_bh(&priv->tx_lock);
2862 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2863 mwl8k_txq_reclaim(hw, i, 0);
2864
88de754a 2865 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 2866 complete(priv->tx_wait);
2867 priv->tx_wait = NULL;
a66098da
LB		 2868 }
2869 spin_unlock_bh(&priv->tx_lock);
2870}
2871
2872static void mwl8k_finalize_join_worker(struct work_struct *work)
2873{
2874 struct mwl8k_priv *priv =
2875 container_of(work, struct mwl8k_priv, finalize_join_worker);
2876 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 2877 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 2878
2879 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2880 dev_kfree_skb(skb);
2881
2882 priv->beacon_skb = NULL;
2883}
2884
2885static int __devinit mwl8k_probe(struct pci_dev *pdev,
2886 const struct pci_device_id *id)
2887{
2aa7b01f 2888 static int printed_version = 0;
a66098da
LB		 2889 struct ieee80211_hw *hw;
2890 struct mwl8k_priv *priv;
a66098da
LB		 2891 int rc;
2892 int i;
2aa7b01f
LB		 2893
2894 if (!printed_version) {
2895 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2896 printed_version = 1;
2897 }
a66098da
LB		 2898
2899 rc = pci_enable_device(pdev);
2900 if (rc) {
2901 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2902 MWL8K_NAME);
2903 return rc;
2904 }
2905
2906 rc = pci_request_regions(pdev, MWL8K_NAME);
2907 if (rc) {
2908 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2909 MWL8K_NAME);
2910 return rc;
2911 }
2912
2913 pci_set_master(pdev);
2914
2915 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2916 if (hw == NULL) {
2917 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2918 rc = -ENOMEM;
2919 goto err_free_reg;
2920 }
2921
2922 priv = hw->priv;
2923 priv->hw = hw;
2924 priv->pdev = pdev;
0439b1f5 2925 priv->wmm_enabled = false;
a66098da 2926 priv->pending_tx_pkts = 0;
a66098da 2927
a66098da
LB		 2928 SET_IEEE80211_DEV(hw, &pdev->dev);
2929 pci_set_drvdata(pdev, hw);
2930
2931 priv->regs = pci_iomap(pdev, 1, 0x10000);
2932 if (priv->regs == NULL) {
c2c357ce
LB		 2933 printk(KERN_ERR "%s: Cannot map device memory\n",
2934 wiphy_name(hw->wiphy));
a66098da
LB		 2935 goto err_iounmap;
2936 }
2937
2938 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
2939 priv->band.band = IEEE80211_BAND_2GHZ;
2940 priv->band.channels = priv->channels;
2941 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
2942 priv->band.bitrates = priv->rates;
2943 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
2944 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
2945
2946 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
2947 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
2948
2949 /*
2950 * Extra headroom is the size of the required DMA header
2951 * minus the size of the smallest 802.11 frame (CTS frame).
2952 */
2953 hw->extra_tx_headroom =
2954 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
2955
2956 hw->channel_change_time = 10;
2957
2958 hw->queues = MWL8K_TX_QUEUES;
2959
240e86ef 2960 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
a66098da
LB		 2961
2962 /* Set rssi and noise values to dBm */
ce9e2e1b 2963 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 2964 hw->vif_data_size = sizeof(struct mwl8k_vif);
2965 priv->vif = NULL;
2966
2967 /* Set default radio state and preamble */
c46563b7 2968 priv->radio_on = 0;
68ce3884 2969 priv->radio_short_preamble = 0;
a66098da
LB		 2970
2971 /* Finalize join worker */
2972 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
2973
2974 /* TX reclaim tasklet */
2975 tasklet_init(&priv->tx_reclaim_task,
2976 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2977 tasklet_disable(&priv->tx_reclaim_task);
2978
a66098da
LB		 2979 /* Power management cookie */
2980 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2981 if (priv->cookie == NULL)
2982 goto err_iounmap;
2983
2984 rc = mwl8k_rxq_init(hw, 0);
2985 if (rc)
2986 goto err_iounmap;
2987 rxq_refill(hw, 0, INT_MAX);
2988
618952a7
LB		 2989 mutex_init(&priv->fw_mutex);
2990 priv->fw_mutex_owner = NULL;
2991 priv->fw_mutex_depth = 0;
618952a7
LB		 2992 priv->hostcmd_wait = NULL;
2993
a66098da
LB		 2994 spin_lock_init(&priv->tx_lock);
2995
88de754a
LB		 2996 priv->tx_wait = NULL;
2997
a66098da
LB		 2998 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
2999 rc = mwl8k_txq_init(hw, i);
3000 if (rc)
3001 goto err_free_queues;
3002 }
3003
3004 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3005 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3006 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3007 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3008
3009 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3010 IRQF_SHARED, MWL8K_NAME, hw);
3011 if (rc) {
3012 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3013 wiphy_name(hw->wiphy));
a66098da
LB		 3014 goto err_free_queues;
3015 }
3016
3017 /* Reset firmware and hardware */
3018 mwl8k_hw_reset(priv);
3019
3020 /* Ask userland hotplug daemon for the device firmware */
3021 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3022 if (rc) {
c2c357ce
LB		 3023 printk(KERN_ERR "%s: Firmware files not found\n",
3024 wiphy_name(hw->wiphy));
a66098da
LB		 3025 goto err_free_irq;
3026 }
3027
3028 /* Load firmware into hardware */
c2c357ce 3029 rc = mwl8k_load_firmware(hw);
a66098da 3030 if (rc) {
c2c357ce
LB		 3031 printk(KERN_ERR "%s: Cannot start firmware\n",
3032 wiphy_name(hw->wiphy));
a66098da
LB		 3033 goto err_stop_firmware;
3034 }
3035
3036 /* Reclaim memory once firmware is successfully loaded */
3037 mwl8k_release_firmware(priv);
3038
3039 /*
3040 * Temporarily enable interrupts. Initial firmware host
3041 * commands use interrupts and avoids polling. Disable
3042 * interrupts when done.
3043 */
c23b5a69 3044 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3045
3046 /* Get config data, mac addrs etc */
3047 rc = mwl8k_cmd_get_hw_spec(hw);
3048 if (rc) {
c2c357ce
LB		 3049 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3050 wiphy_name(hw->wiphy));
a66098da
LB		 3051 goto err_stop_firmware;
3052 }
3053
3054 /* Turn radio off */
c46563b7 3055 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3056 if (rc) {
c2c357ce 3057 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3058 goto err_stop_firmware;
3059 }
3060
32060e1b
LB		 3061 /* Clear MAC address */
3062 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3063 if (rc) {
3064 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3065 wiphy_name(hw->wiphy));
3066 goto err_stop_firmware;
3067 }
3068
a66098da 3069 /* Disable interrupts */
a66098da 3070 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3071 free_irq(priv->pdev->irq, hw);
3072
3073 rc = ieee80211_register_hw(hw);
3074 if (rc) {
c2c357ce
LB		 3075 printk(KERN_ERR "%s: Cannot register device\n",
3076 wiphy_name(hw->wiphy));
a66098da
LB		 3077 goto err_stop_firmware;
3078 }
3079
2aa7b01f
LB		 3080 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3081 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3082 hw->wiphy->perm_addr,
3083 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3084 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3085
3086 return 0;
3087
3088err_stop_firmware:
3089 mwl8k_hw_reset(priv);
3090 mwl8k_release_firmware(priv);
3091
3092err_free_irq:
a66098da 3093 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3094 free_irq(priv->pdev->irq, hw);
3095
3096err_free_queues:
3097 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3098 mwl8k_txq_deinit(hw, i);
3099 mwl8k_rxq_deinit(hw, 0);
3100
3101err_iounmap:
3102 if (priv->cookie != NULL)
3103 pci_free_consistent(priv->pdev, 4,
3104 priv->cookie, priv->cookie_dma);
3105
3106 if (priv->regs != NULL)
3107 pci_iounmap(pdev, priv->regs);
3108
a66098da
LB		 3109 pci_set_drvdata(pdev, NULL);
3110 ieee80211_free_hw(hw);
3111
3112err_free_reg:
3113 pci_release_regions(pdev);
3114 pci_disable_device(pdev);
3115
3116 return rc;
3117}
3118
230f7af0 3119static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3120{
3121 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3122}
3123
230f7af0 3124static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3125{
3126 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3127 struct mwl8k_priv *priv;
3128 int i;
3129
3130 if (hw == NULL)
3131 return;
3132 priv = hw->priv;
3133
3134 ieee80211_stop_queues(hw);
3135
60aa569f
LB		 3136 ieee80211_unregister_hw(hw);
3137
a66098da
LB		 3138 /* Remove tx reclaim tasklet */
3139 tasklet_kill(&priv->tx_reclaim_task);
3140
a66098da
LB		 3141 /* Stop hardware */
3142 mwl8k_hw_reset(priv);
3143
3144 /* Return all skbs to mac80211 */
3145 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3146 mwl8k_txq_reclaim(hw, i, 1);
3147
a66098da
LB		 3148 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3149 mwl8k_txq_deinit(hw, i);
3150
3151 mwl8k_rxq_deinit(hw, 0);
3152
c2c357ce 3153 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3154
3155 pci_iounmap(pdev, priv->regs);
3156 pci_set_drvdata(pdev, NULL);
3157 ieee80211_free_hw(hw);
3158 pci_release_regions(pdev);
3159 pci_disable_device(pdev);
3160}
3161
3162static struct pci_driver mwl8k_driver = {
3163 .name = MWL8K_NAME,
3164 .id_table = mwl8k_table,
3165 .probe = mwl8k_probe,
3166 .remove = __devexit_p(mwl8k_remove),
3167 .shutdown = __devexit_p(mwl8k_shutdown),
3168};
3169
3170static int __init mwl8k_init(void)
3171{
3172 return pci_register_driver(&mwl8k_driver);
3173}
3174
3175static void __exit mwl8k_exit(void)
3176{
3177 pci_unregister_driver(&mwl8k_driver);
3178}
3179
3180module_init(mwl8k_init);
3181module_exit(mwl8k_exit);
c2c357ce
LB		 3182
3183MODULE_DESCRIPTION(MWL8K_DESC);
3184MODULE_VERSION(MWL8K_VERSION);
3185MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3186MODULE_LICENSE("GPL");
Motorola kernel-slsi