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mwl8k: rename mwl8k_cmd_get_hw_spec() to mwl8k_cmd_get_hw_spec_sta()
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status);
88};
89
45a390dd 90struct mwl8k_device_info {
a74b295e
LB		 91 char *part_name;
92 char *helper_image;
93 char *fw_image;
54bc3a0d 94 struct rxd_ops *rxd_ops;
547810e3 95 u16 modes;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
128/* Pointers to the firmware data and meta information about it. */
129struct mwl8k_firmware {
a66098da
LB		 130 /* Boot helper code */
131 struct firmware *helper;
a74b295e
LB		 132
133 /* Microcode */
134 struct firmware *ucode;
a66098da
LB		 135};
136
137struct mwl8k_priv {
5b9482dd 138 void __iomem *sram;
a66098da
LB		 139 void __iomem *regs;
140 struct ieee80211_hw *hw;
141
142 struct pci_dev *pdev;
a66098da 143
45a390dd 144 struct mwl8k_device_info *device_info;
eae74e65 145 bool ap_fw;
54bc3a0d 146 struct rxd_ops *rxd_ops;
45a390dd 147
a66098da
LB		 148 /* firmware files and meta data */
149 struct mwl8k_firmware fw;
a66098da 150
618952a7
LB		 151 /* firmware access */
152 struct mutex fw_mutex;
153 struct task_struct *fw_mutex_owner;
154 int fw_mutex_depth;
618952a7
LB		 155 struct completion *hostcmd_wait;
156
a66098da
LB		 157 /* lock held over TX and TX reap */
158 spinlock_t tx_lock;
a66098da 159
88de754a
LB		 160 /* TX quiesce completion, protected by fw_mutex and tx_lock */
161 struct completion *tx_wait;
162
a66098da 163 struct ieee80211_vif *vif;
a66098da
LB		 164
165 struct ieee80211_channel *current_channel;
166
167 /* power management status cookie from firmware */
168 u32 *cookie;
169 dma_addr_t cookie_dma;
170
171 u16 num_mcaddrs;
a66098da 172 u8 hw_rev;
2aa7b01f 173 u32 fw_rev;
a66098da
LB		 174
175 /*
176 * Running count of TX packets in flight, to avoid
177 * iterating over the transmit rings each time.
178 */
179 int pending_tx_pkts;
180
181 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
182 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
183
184 /* PHY parameters */
185 struct ieee80211_supported_band band;
186 struct ieee80211_channel channels[14];
5dfd3e2c 187 struct ieee80211_rate rates[13];
a66098da 188
c46563b7 189 bool radio_on;
68ce3884 190 bool radio_short_preamble;
a43c49a8 191 bool sniffer_enabled;
0439b1f5 192 bool wmm_enabled;
a66098da 193
a66098da
LB		 194 /* XXX need to convert this to handle multiple interfaces */
195 bool capture_beacon;
d89173f2 196 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 197 struct sk_buff *beacon_skb;
198
199 /*
200 * This FJ worker has to be global as it is scheduled from the
201 * RX handler. At this point we don't know which interface it
202 * belongs to until the list of bssids waiting to complete join
203 * is checked.
204 */
205 struct work_struct finalize_join_worker;
206
207 /* Tasklet to reclaim TX descriptors and buffers after tx */
208 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 209};
210
211/* Per interface specific private data */
212struct mwl8k_vif {
a66098da
LB		 213 /* backpointer to parent config block */
214 struct mwl8k_priv *priv;
215
216 /* BSS config of AP or IBSS from mac80211*/
217 struct ieee80211_bss_conf bss_info;
218
219 /* BSSID of AP or IBSS */
d89173f2
LB		 220 u8 bssid[ETH_ALEN];
221 u8 mac_addr[ETH_ALEN];
a66098da
LB		 222
223 /*
224 * Subset of supported legacy rates.
225 * Intersection of AP and STA supported rates.
226 */
5dfd3e2c 227 struct ieee80211_rate legacy_rates[13];
a66098da
LB		 228
229 /* number of supported legacy rates */
230 u8 legacy_nrates;
231
a66098da
LB		 232 /* Index into station database.Returned by update_sta_db call */
233 u8 peer_id;
234
235 /* Non AMPDU sequence number assigned by driver */
236 u16 seqno;
a66098da
LB		 237};
238
a94cc97e 239#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 240
241static const struct ieee80211_channel mwl8k_channels[] = {
242 { .center_freq = 2412, .hw_value = 1, },
243 { .center_freq = 2417, .hw_value = 2, },
244 { .center_freq = 2422, .hw_value = 3, },
245 { .center_freq = 2427, .hw_value = 4, },
246 { .center_freq = 2432, .hw_value = 5, },
247 { .center_freq = 2437, .hw_value = 6, },
248 { .center_freq = 2442, .hw_value = 7, },
249 { .center_freq = 2447, .hw_value = 8, },
250 { .center_freq = 2452, .hw_value = 9, },
251 { .center_freq = 2457, .hw_value = 10, },
252 { .center_freq = 2462, .hw_value = 11, },
253};
254
255static const struct ieee80211_rate mwl8k_rates[] = {
256 { .bitrate = 10, .hw_value = 2, },
257 { .bitrate = 20, .hw_value = 4, },
258 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 259 { .bitrate = 110, .hw_value = 22, },
260 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 261 { .bitrate = 60, .hw_value = 12, },
262 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 263 { .bitrate = 120, .hw_value = 24, },
264 { .bitrate = 180, .hw_value = 36, },
265 { .bitrate = 240, .hw_value = 48, },
266 { .bitrate = 360, .hw_value = 72, },
267 { .bitrate = 480, .hw_value = 96, },
268 { .bitrate = 540, .hw_value = 108, },
269};
270
a66098da
LB		 271/* Set or get info from Firmware */
272#define MWL8K_CMD_SET 0x0001
273#define MWL8K_CMD_GET 0x0000
274
275/* Firmware command codes */
276#define MWL8K_CMD_CODE_DNLD 0x0001
277#define MWL8K_CMD_GET_HW_SPEC 0x0003
278#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
279#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 280#define MWL8K_CMD_RADIO_CONTROL 0x001c
281#define MWL8K_CMD_RF_TX_POWER 0x001e
a66098da
LB		 282#define MWL8K_CMD_SET_PRE_SCAN 0x0107
283#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 284#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
285#define MWL8K_CMD_SET_AID 0x010d
286#define MWL8K_CMD_SET_RATE 0x0110
287#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
288#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 289#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 290#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
291#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 292#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 293#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 294#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 295#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 296#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 297#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 298
299static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
300{
301#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
302 snprintf(buf, bufsize, "%s", #x);\
303 return buf;\
304 } while (0)
ce9e2e1b 305 switch (cmd & ~0x8000) {
a66098da
LB		 306 MWL8K_CMDNAME(CODE_DNLD);
307 MWL8K_CMDNAME(GET_HW_SPEC);
308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
312 MWL8K_CMDNAME(SET_PRE_SCAN);
313 MWL8K_CMDNAME(SET_POST_SCAN);
314 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 315 MWL8K_CMDNAME(SET_AID);
316 MWL8K_CMDNAME(SET_RATE);
317 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
318 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 319 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 320 MWL8K_CMDNAME(SET_EDCA_PARAMS);
321 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 322 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 323 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 324 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 325 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 326 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 327 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 328 default:
329 snprintf(buf, bufsize, "0x%x", cmd);
330 }
331#undef MWL8K_CMDNAME
332
333 return buf;
334}
335
336/* Hardware and firmware reset */
337static void mwl8k_hw_reset(struct mwl8k_priv *priv)
338{
339 iowrite32(MWL8K_H2A_INT_RESET,
340 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
341 iowrite32(MWL8K_H2A_INT_RESET,
342 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
343 msleep(20);
344}
345
346/* Release fw image */
347static void mwl8k_release_fw(struct firmware **fw)
348{
349 if (*fw == NULL)
350 return;
351 release_firmware(*fw);
352 *fw = NULL;
353}
354
355static void mwl8k_release_firmware(struct mwl8k_priv *priv)
356{
357 mwl8k_release_fw(&priv->fw.ucode);
358 mwl8k_release_fw(&priv->fw.helper);
359}
360
361/* Request fw image */
362static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 363 const char *fname, struct firmware **fw)
a66098da
LB		 364{
365 /* release current image */
366 if (*fw != NULL)
367 mwl8k_release_fw(fw);
368
369 return request_firmware((const struct firmware **)fw,
c2c357ce 370 fname, &priv->pdev->dev);
a66098da
LB		 371}
372
45a390dd 373static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 374{
a74b295e 375 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 376 int rc;
377
a74b295e
LB		 378 if (di->helper_image != NULL) {
379 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
380 if (rc) {
381 printk(KERN_ERR "%s: Error requesting helper "
382 "firmware file %s\n", pci_name(priv->pdev),
383 di->helper_image);
384 return rc;
385 }
a66098da
LB		 386 }
387
a74b295e 388 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 389 if (rc) {
c2c357ce 390 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 391 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 392 mwl8k_release_fw(&priv->fw.helper);
393 return rc;
394 }
395
396 return 0;
397}
398
399struct mwl8k_cmd_pkt {
400 __le16 code;
401 __le16 length;
402 __le16 seq_num;
403 __le16 result;
404 char payload[0];
405} __attribute__((packed));
406
407/*
408 * Firmware loading.
409 */
410static int
411mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
412{
413 void __iomem *regs = priv->regs;
414 dma_addr_t dma_addr;
a66098da
LB		 415 int loops;
416
417 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
418 if (pci_dma_mapping_error(priv->pdev, dma_addr))
419 return -ENOMEM;
420
421 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
422 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
423 iowrite32(MWL8K_H2A_INT_DOORBELL,
424 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
425 iowrite32(MWL8K_H2A_INT_DUMMY,
426 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
427
a66098da
LB		 428 loops = 1000;
429 do {
430 u32 int_code;
431
432 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
433 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
434 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 435 break;
436 }
437
3d76e82c 438 cond_resched();
a66098da
LB		 439 udelay(1);
440 } while (--loops);
441
442 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
443
d4b70570 444 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 445}
446
447static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
448 const u8 *data, size_t length)
449{
450 struct mwl8k_cmd_pkt *cmd;
451 int done;
452 int rc = 0;
453
454 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
455 if (cmd == NULL)
456 return -ENOMEM;
457
458 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
459 cmd->seq_num = 0;
460 cmd->result = 0;
461
462 done = 0;
463 while (length) {
464 int block_size = length > 256 ? 256 : length;
465
466 memcpy(cmd->payload, data + done, block_size);
467 cmd->length = cpu_to_le16(block_size);
468
469 rc = mwl8k_send_fw_load_cmd(priv, cmd,
470 sizeof(*cmd) + block_size);
471 if (rc)
472 break;
473
474 done += block_size;
475 length -= block_size;
476 }
477
478 if (!rc) {
479 cmd->length = 0;
480 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
481 }
482
483 kfree(cmd);
484
485 return rc;
486}
487
488static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
489 const u8 *data, size_t length)
490{
491 unsigned char *buffer;
492 int may_continue, rc = 0;
493 u32 done, prev_block_size;
494
495 buffer = kmalloc(1024, GFP_KERNEL);
496 if (buffer == NULL)
497 return -ENOMEM;
498
499 done = 0;
500 prev_block_size = 0;
501 may_continue = 1000;
502 while (may_continue > 0) {
503 u32 block_size;
504
505 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
506 if (block_size & 1) {
507 block_size &= ~1;
508 may_continue--;
509 } else {
510 done += prev_block_size;
511 length -= prev_block_size;
512 }
513
514 if (block_size > 1024 || block_size > length) {
515 rc = -EOVERFLOW;
516 break;
517 }
518
519 if (length == 0) {
520 rc = 0;
521 break;
522 }
523
524 if (block_size == 0) {
525 rc = -EPROTO;
526 may_continue--;
527 udelay(1);
528 continue;
529 }
530
531 prev_block_size = block_size;
532 memcpy(buffer, data + done, block_size);
533
534 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
535 if (rc)
536 break;
537 }
538
539 if (!rc && length != 0)
540 rc = -EREMOTEIO;
541
542 kfree(buffer);
543
544 return rc;
545}
546
c2c357ce 547static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 548{
c2c357ce
LB		 549 struct mwl8k_priv *priv = hw->priv;
550 struct firmware *fw = priv->fw.ucode;
eae74e65 551 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 552 int rc;
553 int loops;
554
555 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
556 struct firmware *helper = priv->fw.helper;
a66098da 557
c2c357ce
LB		 558 if (helper == NULL) {
559 printk(KERN_ERR "%s: helper image needed but none "
560 "given\n", pci_name(priv->pdev));
561 return -EINVAL;
562 }
a66098da 563
c2c357ce 564 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 565 if (rc) {
566 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 567 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 568 return rc;
569 }
570 msleep(1);
571
c2c357ce 572 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 573 } else {
c2c357ce 574 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 575 }
576
577 if (rc) {
c2c357ce
LB		 578 printk(KERN_ERR "%s: unable to load firmware image\n",
579 pci_name(priv->pdev));
a66098da
LB		 580 return rc;
581 }
582
eae74e65
LB		 583 if (di->modes & BIT(NL80211_IFTYPE_AP))
584 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
585 else
586 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da
LB		 587 msleep(1);
588
589 loops = 200000;
590 do {
eae74e65
LB		 591 u32 ready_code;
592
593 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
594 if (ready_code == MWL8K_FWAP_READY) {
595 priv->ap_fw = 1;
596 break;
597 } else if (ready_code == MWL8K_FWSTA_READY) {
598 priv->ap_fw = 0;
a66098da 599 break;
eae74e65
LB		 600 }
601
602 cond_resched();
a66098da
LB		 603 udelay(1);
604 } while (--loops);
605
606 return loops ? 0 : -ETIMEDOUT;
607}
608
609
610/*
611 * Defines shared between transmission and reception.
612 */
613/* HT control fields for firmware */
614struct ewc_ht_info {
615 __le16 control1;
616 __le16 control2;
617 __le16 control3;
618} __attribute__((packed));
619
620/* Firmware Station database operations */
621#define MWL8K_STA_DB_ADD_ENTRY 0
622#define MWL8K_STA_DB_MODIFY_ENTRY 1
623#define MWL8K_STA_DB_DEL_ENTRY 2
624#define MWL8K_STA_DB_FLUSH 3
625
626/* Peer Entry flags - used to define the type of the peer node */
627#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 628
5dfd3e2c 629#define MWL8K_IEEE_LEGACY_DATA_RATES 13
a66098da 630#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 631
632struct peer_capability_info {
633 /* Peer type - AP vs. STA. */
634 __u8 peer_type;
635
636 /* Basic 802.11 capabilities from assoc resp. */
637 __le16 basic_caps;
638
639 /* Set if peer supports 802.11n high throughput (HT). */
640 __u8 ht_support;
641
642 /* Valid if HT is supported. */
643 __le16 ht_caps;
644 __u8 extended_ht_caps;
645 struct ewc_ht_info ewc_info;
646
647 /* Legacy rate table. Intersection of our rates and peer rates. */
648 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
649
650 /* HT rate table. Intersection of our rates and peer rates. */
651 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 652 __u8 pad[16];
a66098da
LB		 653
654 /* If set, interoperability mode, no proprietary extensions. */
655 __u8 interop;
656 __u8 pad2;
657 __u8 station_id;
658 __le16 amsdu_enabled;
659} __attribute__((packed));
660
661/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 662static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
663{
664 u16 val_mask = 1 << 4;
665
666 /* End of Service Period Bit 4 */
667 return qos | val_mask;
668}
669
670static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
671{
672 u16 val_mask = 0x3;
673 u8 shift = 5;
674 u16 qos_mask = ~(val_mask << shift);
675
676 /* Ack Policy Bit 5-6 */
677 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
678}
679
680static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
681{
682 u16 val_mask = 1 << 7;
683
684 /* AMSDU present Bit 7 */
685 return qos | val_mask;
686}
687
688static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
689{
690 u16 val_mask = 0xff;
691 u8 shift = 8;
692 u16 qos_mask = ~(val_mask << shift);
693
694 /* Queue Length Bits 8-15 */
695 return (qos & qos_mask) | ((len & val_mask) << shift);
696}
697
698/* DMA header used by firmware and hardware. */
699struct mwl8k_dma_data {
700 __le16 fwlen;
701 struct ieee80211_hdr wh;
702} __attribute__((packed));
703
704/* Routines to add/remove DMA header from skb. */
76266b2a 705static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
a66098da 706{
76266b2a 707 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
a66098da 708 void *dst, *src = &tr->wh;
76266b2a 709 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
a66098da
LB		 710 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
711
712 dst = (void *)tr + space;
713 if (dst != src) {
714 memmove(dst, src, hdrlen);
715 skb_pull(skb, space);
716 }
a66098da
LB		 717}
718
76266b2a 719static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 720{
721 struct ieee80211_hdr *wh;
722 u32 hdrlen, pktlen;
723 struct mwl8k_dma_data *tr;
724
725 wh = (struct ieee80211_hdr *)skb->data;
726 hdrlen = ieee80211_hdrlen(wh->frame_control);
727 pktlen = skb->len;
728
729 /*
730 * Copy up/down the 802.11 header; the firmware requires
731 * we present a 2-byte payload length followed by a
732 * 4-address header (w/o QoS), followed (optionally) by
733 * any WEP/ExtIV header (but only filled in for CCMP).
734 */
735 if (hdrlen != sizeof(struct mwl8k_dma_data))
736 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
737
738 tr = (struct mwl8k_dma_data *)skb->data;
739 if (wh != &tr->wh)
740 memmove(&tr->wh, wh, hdrlen);
741
742 /* Clear addr4 */
d89173f2 743 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 744
745 /*
746 * Firmware length is the length of the fully formed "802.11
747 * payload". That is, everything except for the 802.11 header.
748 * This includes all crypto material including the MIC.
749 */
750 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 751}
752
753
754/*
755 * Packet reception.
756 */
54bc3a0d 757struct mwl8k_rxd_8687 {
a66098da
LB		 758 __le16 pkt_len;
759 __u8 link_quality;
760 __u8 noise_level;
761 __le32 pkt_phys_addr;
45eb400d 762 __le32 next_rxd_phys_addr;
a66098da
LB		 763 __le16 qos_control;
764 __le16 rate_info;
765 __le32 pad0[4];
766 __u8 rssi;
767 __u8 channel;
768 __le16 pad1;
769 __u8 rx_ctrl;
770 __u8 rx_status;
771 __u8 pad2[2];
772} __attribute__((packed));
773
54bc3a0d
LB		 774#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
775#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
776#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
777#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
778#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
779#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
780
781#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
782
783static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
784{
785 struct mwl8k_rxd_8687 *rxd = _rxd;
786
787 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
788 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
789}
790
791static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
792{
793 struct mwl8k_rxd_8687 *rxd = _rxd;
794
795 rxd->pkt_len = cpu_to_le16(len);
796 rxd->pkt_phys_addr = cpu_to_le32(addr);
797 wmb();
798 rxd->rx_ctrl = 0;
799}
800
801static int
802mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status)
803{
804 struct mwl8k_rxd_8687 *rxd = _rxd;
805 u16 rate_info;
806
807 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
808 return -1;
809 rmb();
810
811 rate_info = le16_to_cpu(rxd->rate_info);
812
813 memset(status, 0, sizeof(*status));
814
815 status->signal = -rxd->rssi;
816 status->noise = -rxd->noise_level;
817 status->qual = rxd->link_quality;
818 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
819 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
820
821 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
822 status->flag |= RX_FLAG_SHORTPRE;
823 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
824 status->flag |= RX_FLAG_40MHZ;
825 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
826 status->flag |= RX_FLAG_SHORT_GI;
827 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
828 status->flag |= RX_FLAG_HT;
829
830 status->band = IEEE80211_BAND_2GHZ;
831 status->freq = ieee80211_channel_to_frequency(rxd->channel);
832
833 return le16_to_cpu(rxd->pkt_len);
834}
835
836static struct rxd_ops rxd_8687_ops = {
837 .rxd_size = sizeof(struct mwl8k_rxd_8687),
838 .rxd_init = mwl8k_rxd_8687_init,
839 .rxd_refill = mwl8k_rxd_8687_refill,
840 .rxd_process = mwl8k_rxd_8687_process,
841};
842
843
a66098da
LB		 844#define MWL8K_RX_DESCS 256
845#define MWL8K_RX_MAXSZ 3800
846
847static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
848{
849 struct mwl8k_priv *priv = hw->priv;
850 struct mwl8k_rx_queue *rxq = priv->rxq + index;
851 int size;
852 int i;
853
45eb400d
LB		 854 rxq->rxd_count = 0;
855 rxq->head = 0;
856 rxq->tail = 0;
a66098da 857
54bc3a0d 858 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 859
45eb400d
LB		 860 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
861 if (rxq->rxd == NULL) {
a66098da 862 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 863 wiphy_name(hw->wiphy));
a66098da
LB		 864 return -ENOMEM;
865 }
45eb400d 866 memset(rxq->rxd, 0, size);
a66098da 867
788838eb
LB		 868 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
869 if (rxq->buf == NULL) {
a66098da 870 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 871 wiphy_name(hw->wiphy));
45eb400d 872 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 873 return -ENOMEM;
874 }
788838eb 875 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 876
877 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 878 int desc_size;
879 void *rxd;
a66098da 880 int nexti;
54bc3a0d
LB		 881 dma_addr_t next_dma_addr;
882
883 desc_size = priv->rxd_ops->rxd_size;
884 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 885
54bc3a0d
LB		 886 nexti = i + 1;
887 if (nexti == MWL8K_RX_DESCS)
888 nexti = 0;
889 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 890
54bc3a0d 891 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 892 }
893
894 return 0;
895}
896
897static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
898{
899 struct mwl8k_priv *priv = hw->priv;
900 struct mwl8k_rx_queue *rxq = priv->rxq + index;
901 int refilled;
902
903 refilled = 0;
45eb400d 904 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 905 struct sk_buff *skb;
788838eb 906 dma_addr_t addr;
a66098da 907 int rx;
54bc3a0d 908 void *rxd;
a66098da
LB		 909
910 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
911 if (skb == NULL)
912 break;
913
788838eb
LB		 914 addr = pci_map_single(priv->pdev, skb->data,
915 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 916
54bc3a0d
LB		 917 rxq->rxd_count++;
918 rx = rxq->tail++;
919 if (rxq->tail == MWL8K_RX_DESCS)
920 rxq->tail = 0;
788838eb
LB		 921 rxq->buf[rx].skb = skb;
922 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 923
924 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
925 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 926
927 refilled++;
928 }
929
930 return refilled;
931}
932
933/* Must be called only when the card's reception is completely halted */
934static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
935{
936 struct mwl8k_priv *priv = hw->priv;
937 struct mwl8k_rx_queue *rxq = priv->rxq + index;
938 int i;
939
940 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 941 if (rxq->buf[i].skb != NULL) {
942 pci_unmap_single(priv->pdev,
943 pci_unmap_addr(&rxq->buf[i], dma),
944 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
945 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
946
947 kfree_skb(rxq->buf[i].skb);
948 rxq->buf[i].skb = NULL;
a66098da
LB		 949 }
950 }
951
788838eb
LB		 952 kfree(rxq->buf);
953 rxq->buf = NULL;
a66098da
LB		 954
955 pci_free_consistent(priv->pdev,
54bc3a0d 956 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 957 rxq->rxd, rxq->rxd_dma);
958 rxq->rxd = NULL;
a66098da
LB		 959}
960
961
962/*
963 * Scan a list of BSSIDs to process for finalize join.
964 * Allows for extension to process multiple BSSIDs.
965 */
966static inline int
967mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
968{
969 return priv->capture_beacon &&
970 ieee80211_is_beacon(wh->frame_control) &&
971 !compare_ether_addr(wh->addr3, priv->capture_bssid);
972}
973
3779752d
LB		 974static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
975 struct sk_buff *skb)
a66098da 976{
3779752d
LB		 977 struct mwl8k_priv *priv = hw->priv;
978
a66098da 979 priv->capture_beacon = false;
d89173f2 980 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 981
982 /*
983 * Use GFP_ATOMIC as rxq_process is called from
984 * the primary interrupt handler, memory allocation call
985 * must not sleep.
986 */
987 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
988 if (priv->beacon_skb != NULL)
3779752d 989 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 990}
991
992static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
993{
994 struct mwl8k_priv *priv = hw->priv;
995 struct mwl8k_rx_queue *rxq = priv->rxq + index;
996 int processed;
997
998 processed = 0;
45eb400d 999 while (rxq->rxd_count && limit--) {
a66098da 1000 struct sk_buff *skb;
54bc3a0d
LB		 1001 void *rxd;
1002 int pkt_len;
a66098da 1003 struct ieee80211_rx_status status;
a66098da 1004
788838eb 1005 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1006 if (skb == NULL)
1007 break;
54bc3a0d
LB		 1008
1009 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1010
1011 pkt_len = priv->rxd_ops->rxd_process(rxd, &status);
1012 if (pkt_len < 0)
1013 break;
1014
788838eb
LB		 1015 rxq->buf[rxq->head].skb = NULL;
1016
1017 pci_unmap_single(priv->pdev,
1018 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1019 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1020 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1021
54bc3a0d
LB		 1022 rxq->head++;
1023 if (rxq->head == MWL8K_RX_DESCS)
1024 rxq->head = 0;
1025
45eb400d 1026 rxq->rxd_count--;
a66098da 1027
54bc3a0d 1028 skb_put(skb, pkt_len);
76266b2a 1029 mwl8k_remove_dma_header(skb);
a66098da 1030
a66098da 1031 /*
c2c357ce
LB		 1032 * Check for a pending join operation. Save a
1033 * copy of the beacon and schedule a tasklet to
1034 * send a FINALIZE_JOIN command to the firmware.
a66098da 1035 */
54bc3a0d 1036 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1037 mwl8k_save_beacon(hw, skb);
a66098da 1038
f1d58c25
JB		 1039 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1040 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1041
1042 processed++;
1043 }
1044
1045 return processed;
1046}
1047
1048
1049/*
1050 * Packet transmission.
1051 */
1052
a66098da
LB		 1053/* Transmit packet ACK policy */
1054#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1055#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1056
a66098da
LB		 1057#define MWL8K_TXD_STATUS_OK 0x00000001
1058#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1059#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1060#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1061#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1062
1063struct mwl8k_tx_desc {
1064 __le32 status;
1065 __u8 data_rate;
1066 __u8 tx_priority;
1067 __le16 qos_control;
1068 __le32 pkt_phys_addr;
1069 __le16 pkt_len;
d89173f2 1070 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1071 __le32 next_txd_phys_addr;
a66098da
LB		 1072 __le32 reserved;
1073 __le16 rate_info;
1074 __u8 peer_id;
1075 __u8 tx_frag_cnt;
1076} __attribute__((packed));
1077
1078#define MWL8K_TX_DESCS 128
1079
1080static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1081{
1082 struct mwl8k_priv *priv = hw->priv;
1083 struct mwl8k_tx_queue *txq = priv->txq + index;
1084 int size;
1085 int i;
1086
45eb400d
LB		 1087 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1088 txq->stats.limit = MWL8K_TX_DESCS;
1089 txq->head = 0;
1090 txq->tail = 0;
a66098da
LB		 1091
1092 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1093
45eb400d
LB		 1094 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1095 if (txq->txd == NULL) {
a66098da 1096 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1097 wiphy_name(hw->wiphy));
a66098da
LB		 1098 return -ENOMEM;
1099 }
45eb400d 1100 memset(txq->txd, 0, size);
a66098da 1101
45eb400d
LB		 1102 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1103 if (txq->skb == NULL) {
a66098da 1104 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1105 wiphy_name(hw->wiphy));
45eb400d 1106 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1107 return -ENOMEM;
1108 }
45eb400d 1109 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1110
1111 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1112 struct mwl8k_tx_desc *tx_desc;
1113 int nexti;
1114
45eb400d 1115 tx_desc = txq->txd + i;
a66098da
LB		 1116 nexti = (i + 1) % MWL8K_TX_DESCS;
1117
1118 tx_desc->status = 0;
45eb400d
LB		 1119 tx_desc->next_txd_phys_addr =
1120 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1121 }
1122
1123 return 0;
1124}
1125
1126static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1127{
1128 iowrite32(MWL8K_H2A_INT_PPA_READY,
1129 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1130 iowrite32(MWL8K_H2A_INT_DUMMY,
1131 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1132 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1133}
1134
a66098da
LB		 1135struct mwl8k_txq_info {
1136 u32 fw_owned;
1137 u32 drv_owned;
1138 u32 unused;
1139 u32 len;
1140 u32 head;
1141 u32 tail;
1142};
1143
1144static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1145 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1146{
1147 int count, desc, status;
1148 struct mwl8k_tx_queue *txq;
1149 struct mwl8k_tx_desc *tx_desc;
1150 int ndescs = 0;
1151
c3f967d3
LB		 1152 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1153
c3f967d3 1154 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da 1155 txq = priv->txq + count;
45eb400d
LB		 1156 txinfo[count].len = txq->stats.len;
1157 txinfo[count].head = txq->head;
1158 txinfo[count].tail = txq->tail;
a66098da 1159 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
45eb400d 1160 tx_desc = txq->txd + desc;
a66098da
LB		 1161 status = le32_to_cpu(tx_desc->status);
1162
1163 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1164 txinfo[count].fw_owned++;
1165 else
1166 txinfo[count].drv_owned++;
1167
1168 if (tx_desc->pkt_len == 0)
1169 txinfo[count].unused++;
1170 }
1171 }
a66098da
LB		 1172
1173 return ndescs;
1174}
1175
618952a7 1176/*
88de754a 1177 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1178 */
950d5b01 1179static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1180{
a66098da 1181 struct mwl8k_priv *priv = hw->priv;
88de754a 1182 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1183 u32 count;
1184 unsigned long timeout;
a66098da
LB		 1185
1186 might_sleep();
1187
a66098da 1188 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1189 count = priv->pending_tx_pkts;
1190 if (count)
1191 priv->tx_wait = &tx_wait;
a66098da
LB		 1192 spin_unlock_bh(&priv->tx_lock);
1193
1194 if (count) {
c3f967d3 1195 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1196 int index;
1197 int newcount;
1198
88de754a 1199 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1200 msecs_to_jiffies(5000));
a66098da
LB		 1201 if (timeout)
1202 return 0;
1203
1204 spin_lock_bh(&priv->tx_lock);
1205 priv->tx_wait = NULL;
88de754a
LB		 1206 newcount = priv->pending_tx_pkts;
1207 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1208 spin_unlock_bh(&priv->tx_lock);
1209
618952a7 1210 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1211 __func__, __LINE__, count, newcount);
a66098da 1212
c3f967d3 1213 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1214 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1215 "DRV:%u U:%u\n",
a66098da
LB		 1216 index,
1217 txinfo[index].len,
1218 txinfo[index].head,
1219 txinfo[index].tail,
1220 txinfo[index].fw_owned,
1221 txinfo[index].drv_owned,
1222 txinfo[index].unused);
ce9e2e1b 1223
a66098da
LB		 1224 return -ETIMEDOUT;
1225 }
1226
1227 return 0;
1228}
1229
c23b5a69
LB		 1230#define MWL8K_TXD_SUCCESS(status) \
1231 ((status) & (MWL8K_TXD_STATUS_OK | \
1232 MWL8K_TXD_STATUS_OK_RETRY | \
1233 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1234
1235static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1236{
1237 struct mwl8k_priv *priv = hw->priv;
1238 struct mwl8k_tx_queue *txq = priv->txq + index;
1239 int wake = 0;
1240
45eb400d 1241 while (txq->stats.len > 0) {
a66098da 1242 int tx;
a66098da
LB		 1243 struct mwl8k_tx_desc *tx_desc;
1244 unsigned long addr;
ce9e2e1b 1245 int size;
a66098da
LB		 1246 struct sk_buff *skb;
1247 struct ieee80211_tx_info *info;
1248 u32 status;
1249
45eb400d
LB		 1250 tx = txq->head;
1251 tx_desc = txq->txd + tx;
a66098da
LB		 1252
1253 status = le32_to_cpu(tx_desc->status);
1254
1255 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1256 if (!force)
1257 break;
1258 tx_desc->status &=
1259 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1260 }
1261
45eb400d
LB		 1262 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1263 BUG_ON(txq->stats.len == 0);
1264 txq->stats.len--;
a66098da
LB		 1265 priv->pending_tx_pkts--;
1266
1267 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1268 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1269 skb = txq->skb[tx];
1270 txq->skb[tx] = NULL;
a66098da
LB		 1271
1272 BUG_ON(skb == NULL);
1273 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1274
76266b2a 1275 mwl8k_remove_dma_header(skb);
a66098da
LB		 1276
1277 /* Mark descriptor as unused */
1278 tx_desc->pkt_phys_addr = 0;
1279 tx_desc->pkt_len = 0;
1280
a66098da
LB		 1281 info = IEEE80211_SKB_CB(skb);
1282 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1283 if (MWL8K_TXD_SUCCESS(status))
a66098da 1284 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1285
1286 ieee80211_tx_status_irqsafe(hw, skb);
1287
618952a7 1288 wake = 1;
a66098da
LB		 1289 }
1290
618952a7 1291 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1292 ieee80211_wake_queue(hw, index);
1293}
1294
1295/* must be called only when the card's transmit is completely halted */
1296static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1297{
1298 struct mwl8k_priv *priv = hw->priv;
1299 struct mwl8k_tx_queue *txq = priv->txq + index;
1300
1301 mwl8k_txq_reclaim(hw, index, 1);
1302
45eb400d
LB		 1303 kfree(txq->skb);
1304 txq->skb = NULL;
a66098da
LB		 1305
1306 pci_free_consistent(priv->pdev,
1307 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1308 txq->txd, txq->txd_dma);
1309 txq->txd = NULL;
a66098da
LB		 1310}
1311
1312static int
1313mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1314{
1315 struct mwl8k_priv *priv = hw->priv;
1316 struct ieee80211_tx_info *tx_info;
23b33906 1317 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1318 struct ieee80211_hdr *wh;
1319 struct mwl8k_tx_queue *txq;
1320 struct mwl8k_tx_desc *tx;
a66098da 1321 dma_addr_t dma;
23b33906
LB		 1322 u32 txstatus;
1323 u8 txdatarate;
1324 u16 qos;
a66098da 1325
23b33906
LB		 1326 wh = (struct ieee80211_hdr *)skb->data;
1327 if (ieee80211_is_data_qos(wh->frame_control))
1328 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1329 else
1330 qos = 0;
a66098da 1331
76266b2a 1332 mwl8k_add_dma_header(skb);
23b33906 1333 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1334
1335 tx_info = IEEE80211_SKB_CB(skb);
1336 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1337
1338 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1339 u16 seqno = mwl8k_vif->seqno;
23b33906 1340
a66098da
LB		 1341 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1342 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1343 mwl8k_vif->seqno = seqno++ % 4096;
1344 }
1345
23b33906
LB		 1346 /* Setup firmware control bit fields for each frame type. */
1347 txstatus = 0;
1348 txdatarate = 0;
1349 if (ieee80211_is_mgmt(wh->frame_control) ||
1350 ieee80211_is_ctl(wh->frame_control)) {
1351 txdatarate = 0;
1352 qos = mwl8k_qos_setbit_eosp(qos);
1353 /* Set Queue size to unspecified */
1354 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1355 } else if (ieee80211_is_data(wh->frame_control)) {
1356 txdatarate = 1;
1357 if (is_multicast_ether_addr(wh->addr1))
1358 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1359
1360 /* Send pkt in an aggregate if AMPDU frame. */
1361 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1362 qos = mwl8k_qos_setbit_ack(qos,
1363 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1364 else
1365 qos = mwl8k_qos_setbit_ack(qos,
1366 MWL8K_TXD_ACK_POLICY_NORMAL);
1367
1368 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1369 qos = mwl8k_qos_setbit_amsdu(qos);
1370 }
a66098da
LB		 1371
1372 dma = pci_map_single(priv->pdev, skb->data,
1373 skb->len, PCI_DMA_TODEVICE);
1374
1375 if (pci_dma_mapping_error(priv->pdev, dma)) {
1376 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1377 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1378 dev_kfree_skb(skb);
a66098da
LB		 1379 return NETDEV_TX_OK;
1380 }
1381
23b33906 1382 spin_lock_bh(&priv->tx_lock);
a66098da 1383
23b33906 1384 txq = priv->txq + index;
a66098da 1385
45eb400d
LB		 1386 BUG_ON(txq->skb[txq->tail] != NULL);
1387 txq->skb[txq->tail] = skb;
a66098da 1388
45eb400d 1389 tx = txq->txd + txq->tail;
23b33906
LB		 1390 tx->data_rate = txdatarate;
1391 tx->tx_priority = index;
a66098da 1392 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1393 tx->pkt_phys_addr = cpu_to_le32(dma);
1394 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1395 tx->rate_info = 0;
1396 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1397 wmb();
23b33906
LB		 1398 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1399
45eb400d
LB		 1400 txq->stats.count++;
1401 txq->stats.len++;
a66098da 1402 priv->pending_tx_pkts++;
a66098da 1403
45eb400d
LB		 1404 txq->tail++;
1405 if (txq->tail == MWL8K_TX_DESCS)
1406 txq->tail = 0;
23b33906 1407
45eb400d 1408 if (txq->head == txq->tail)
a66098da
LB		 1409 ieee80211_stop_queue(hw, index);
1410
23b33906 1411 mwl8k_tx_start(priv);
a66098da
LB		 1412
1413 spin_unlock_bh(&priv->tx_lock);
1414
1415 return NETDEV_TX_OK;
1416}
1417
1418
618952a7
LB		 1419/*
1420 * Firmware access.
1421 *
1422 * We have the following requirements for issuing firmware commands:
1423 * - Some commands require that the packet transmit path is idle when
1424 * the command is issued. (For simplicity, we'll just quiesce the
1425 * transmit path for every command.)
1426 * - There are certain sequences of commands that need to be issued to
1427 * the hardware sequentially, with no other intervening commands.
1428 *
1429 * This leads to an implementation of a "firmware lock" as a mutex that
1430 * can be taken recursively, and which is taken by both the low-level
1431 * command submission function (mwl8k_post_cmd) as well as any users of
1432 * that function that require issuing of an atomic sequence of commands,
1433 * and quiesces the transmit path whenever it's taken.
1434 */
1435static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1436{
1437 struct mwl8k_priv *priv = hw->priv;
1438
1439 if (priv->fw_mutex_owner != current) {
1440 int rc;
1441
1442 mutex_lock(&priv->fw_mutex);
1443 ieee80211_stop_queues(hw);
1444
1445 rc = mwl8k_tx_wait_empty(hw);
1446 if (rc) {
1447 ieee80211_wake_queues(hw);
1448 mutex_unlock(&priv->fw_mutex);
1449
1450 return rc;
1451 }
1452
1453 priv->fw_mutex_owner = current;
1454 }
1455
1456 priv->fw_mutex_depth++;
1457
1458 return 0;
1459}
1460
1461static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1462{
1463 struct mwl8k_priv *priv = hw->priv;
1464
1465 if (!--priv->fw_mutex_depth) {
1466 ieee80211_wake_queues(hw);
1467 priv->fw_mutex_owner = NULL;
1468 mutex_unlock(&priv->fw_mutex);
1469 }
1470}
1471
1472
a66098da
LB		 1473/*
1474 * Command processing.
1475 */
1476
1477/* Timeout firmware commands after 2000ms */
1478#define MWL8K_CMD_TIMEOUT_MS 2000
1479
1480static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1481{
1482 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1483 struct mwl8k_priv *priv = hw->priv;
1484 void __iomem *regs = priv->regs;
1485 dma_addr_t dma_addr;
1486 unsigned int dma_size;
1487 int rc;
a66098da
LB		 1488 unsigned long timeout = 0;
1489 u8 buf[32];
1490
c2c357ce 1491 cmd->result = 0xffff;
a66098da
LB		 1492 dma_size = le16_to_cpu(cmd->length);
1493 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1494 PCI_DMA_BIDIRECTIONAL);
1495 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1496 return -ENOMEM;
1497
618952a7 1498 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1499 if (rc) {
1500 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1501 PCI_DMA_BIDIRECTIONAL);
618952a7 1502 return rc;
39a1e42e 1503 }
a66098da 1504
a66098da
LB		 1505 priv->hostcmd_wait = &cmd_wait;
1506 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1507 iowrite32(MWL8K_H2A_INT_DOORBELL,
1508 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1509 iowrite32(MWL8K_H2A_INT_DUMMY,
1510 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1511
1512 timeout = wait_for_completion_timeout(&cmd_wait,
1513 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1514
618952a7
LB		 1515 priv->hostcmd_wait = NULL;
1516
1517 mwl8k_fw_unlock(hw);
1518
37055bd4
LB		 1519 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1520 PCI_DMA_BIDIRECTIONAL);
1521
a66098da 1522 if (!timeout) {
a66098da 1523 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1524 wiphy_name(hw->wiphy),
a66098da
LB		 1525 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1526 MWL8K_CMD_TIMEOUT_MS);
1527 rc = -ETIMEDOUT;
1528 } else {
ce9e2e1b 1529 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1530 if (rc)
1531 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1532 wiphy_name(hw->wiphy),
a66098da 1533 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1534 le16_to_cpu(cmd->result));
a66098da
LB		 1535 }
1536
a66098da
LB		 1537 return rc;
1538}
1539
1540/*
04b147b1 1541 * CMD_GET_HW_SPEC (STA version).
a66098da 1542 */
04b147b1 1543struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1544 struct mwl8k_cmd_pkt header;
1545 __u8 hw_rev;
1546 __u8 host_interface;
1547 __le16 num_mcaddrs;
d89173f2 1548 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1549 __le16 region_code;
1550 __le32 fw_rev;
1551 __le32 ps_cookie;
1552 __le32 caps;
1553 __u8 mcs_bitmap[16];
1554 __le32 rx_queue_ptr;
1555 __le32 num_tx_queues;
1556 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1557 __le32 caps2;
1558 __le32 num_tx_desc_per_queue;
45eb400d 1559 __le32 total_rxd;
a66098da
LB		 1560} __attribute__((packed));
1561
04b147b1 1562static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1563{
1564 struct mwl8k_priv *priv = hw->priv;
04b147b1 1565 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1566 int rc;
1567 int i;
1568
1569 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1570 if (cmd == NULL)
1571 return -ENOMEM;
1572
1573 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1574 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1575
1576 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1577 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1578 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1579 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1580 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1581 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1582 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1583 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1584
1585 rc = mwl8k_post_cmd(hw, &cmd->header);
1586
1587 if (!rc) {
1588 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1589 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1590 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1591 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1592 }
1593
1594 kfree(cmd);
1595 return rc;
1596}
1597
1598/*
1599 * CMD_MAC_MULTICAST_ADR.
1600 */
1601struct mwl8k_cmd_mac_multicast_adr {
1602 struct mwl8k_cmd_pkt header;
1603 __le16 action;
1604 __le16 numaddr;
ce9e2e1b 1605 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1606};
1607
d5e30845
LB		 1608#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1609#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1610#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1611#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1612
e81cd2d6 1613static struct mwl8k_cmd_pkt *
447ced07 1614__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1615 int mc_count, struct dev_addr_list *mclist)
a66098da 1616{
e81cd2d6 1617 struct mwl8k_priv *priv = hw->priv;
a66098da 1618 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1619 int size;
e81cd2d6 1620
447ced07 1621 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1622 allmulti = 1;
1623 mc_count = 0;
1624 }
e81cd2d6
LB		 1625
1626 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1627
e81cd2d6 1628 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1629 if (cmd == NULL)
e81cd2d6 1630 return NULL;
a66098da
LB		 1631
1632 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1633 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1634 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1635 MWL8K_ENABLE_RX_BROADCAST);
1636
1637 if (allmulti) {
1638 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1639 } else if (mc_count) {
1640 int i;
1641
1642 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1643 cmd->numaddr = cpu_to_le16(mc_count);
1644 for (i = 0; i < mc_count && mclist; i++) {
1645 if (mclist->da_addrlen != ETH_ALEN) {
1646 kfree(cmd);
1647 return NULL;
1648 }
1649 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1650 mclist = mclist->next;
a66098da 1651 }
a66098da
LB		 1652 }
1653
e81cd2d6 1654 return &cmd->header;
a66098da
LB		 1655}
1656
1657/*
1658 * CMD_802_11_GET_STAT.
1659 */
1660struct mwl8k_cmd_802_11_get_stat {
1661 struct mwl8k_cmd_pkt header;
a66098da
LB		 1662 __le32 stats[64];
1663} __attribute__((packed));
1664
1665#define MWL8K_STAT_ACK_FAILURE 9
1666#define MWL8K_STAT_RTS_FAILURE 12
1667#define MWL8K_STAT_FCS_ERROR 24
1668#define MWL8K_STAT_RTS_SUCCESS 11
1669
1670static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1671 struct ieee80211_low_level_stats *stats)
1672{
1673 struct mwl8k_cmd_802_11_get_stat *cmd;
1674 int rc;
1675
1676 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1677 if (cmd == NULL)
1678 return -ENOMEM;
1679
1680 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1681 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1682
1683 rc = mwl8k_post_cmd(hw, &cmd->header);
1684 if (!rc) {
1685 stats->dot11ACKFailureCount =
1686 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1687 stats->dot11RTSFailureCount =
1688 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1689 stats->dot11FCSErrorCount =
1690 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1691 stats->dot11RTSSuccessCount =
1692 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1693 }
1694 kfree(cmd);
1695
1696 return rc;
1697}
1698
1699/*
1700 * CMD_802_11_RADIO_CONTROL.
1701 */
1702struct mwl8k_cmd_802_11_radio_control {
1703 struct mwl8k_cmd_pkt header;
1704 __le16 action;
1705 __le16 control;
1706 __le16 radio_on;
1707} __attribute__((packed));
1708
c46563b7
LB		 1709static int
1710mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1711{
1712 struct mwl8k_priv *priv = hw->priv;
1713 struct mwl8k_cmd_802_11_radio_control *cmd;
1714 int rc;
1715
c46563b7 1716 if (enable == priv->radio_on && !force)
a66098da
LB		 1717 return 0;
1718
a66098da
LB		 1719 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1720 if (cmd == NULL)
1721 return -ENOMEM;
1722
1723 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1724 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1725 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1726 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1727 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1728
1729 rc = mwl8k_post_cmd(hw, &cmd->header);
1730 kfree(cmd);
1731
1732 if (!rc)
c46563b7 1733 priv->radio_on = enable;
a66098da
LB		 1734
1735 return rc;
1736}
1737
c46563b7
LB		 1738static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1739{
1740 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1741}
1742
1743static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1744{
1745 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1746}
1747
a66098da
LB		 1748static int
1749mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1750{
1751 struct mwl8k_priv *priv;
1752
1753 if (hw == NULL || hw->priv == NULL)
1754 return -EINVAL;
1755 priv = hw->priv;
1756
68ce3884 1757 priv->radio_short_preamble = short_preamble;
a66098da 1758
c46563b7 1759 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1760}
1761
1762/*
1763 * CMD_802_11_RF_TX_POWER.
1764 */
1765#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1766
1767struct mwl8k_cmd_802_11_rf_tx_power {
1768 struct mwl8k_cmd_pkt header;
1769 __le16 action;
1770 __le16 support_level;
1771 __le16 current_level;
1772 __le16 reserved;
1773 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1774} __attribute__((packed));
1775
1776static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1777{
1778 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1779 int rc;
1780
1781 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1782 if (cmd == NULL)
1783 return -ENOMEM;
1784
1785 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1786 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1787 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1788 cmd->support_level = cpu_to_le16(dBm);
1789
1790 rc = mwl8k_post_cmd(hw, &cmd->header);
1791 kfree(cmd);
1792
1793 return rc;
1794}
1795
1796/*
1797 * CMD_SET_PRE_SCAN.
1798 */
1799struct mwl8k_cmd_set_pre_scan {
1800 struct mwl8k_cmd_pkt header;
1801} __attribute__((packed));
1802
1803static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1804{
1805 struct mwl8k_cmd_set_pre_scan *cmd;
1806 int rc;
1807
1808 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1809 if (cmd == NULL)
1810 return -ENOMEM;
1811
1812 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1813 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1814
1815 rc = mwl8k_post_cmd(hw, &cmd->header);
1816 kfree(cmd);
1817
1818 return rc;
1819}
1820
1821/*
1822 * CMD_SET_POST_SCAN.
1823 */
1824struct mwl8k_cmd_set_post_scan {
1825 struct mwl8k_cmd_pkt header;
1826 __le32 isibss;
d89173f2 1827 __u8 bssid[ETH_ALEN];
a66098da
LB		 1828} __attribute__((packed));
1829
1830static int
ce9e2e1b 1831mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 1832{
1833 struct mwl8k_cmd_set_post_scan *cmd;
1834 int rc;
1835
1836 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1837 if (cmd == NULL)
1838 return -ENOMEM;
1839
1840 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1841 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1842 cmd->isibss = 0;
d89173f2 1843 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 1844
1845 rc = mwl8k_post_cmd(hw, &cmd->header);
1846 kfree(cmd);
1847
1848 return rc;
1849}
1850
1851/*
1852 * CMD_SET_RF_CHANNEL.
1853 */
1854struct mwl8k_cmd_set_rf_channel {
1855 struct mwl8k_cmd_pkt header;
1856 __le16 action;
1857 __u8 current_channel;
1858 __le32 channel_flags;
1859} __attribute__((packed));
1860
1861static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1862 struct ieee80211_channel *channel)
1863{
1864 struct mwl8k_cmd_set_rf_channel *cmd;
1865 int rc;
1866
1867 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1868 if (cmd == NULL)
1869 return -ENOMEM;
1870
1871 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1872 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1873 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1874 cmd->current_channel = channel->hw_value;
1875 if (channel->band == IEEE80211_BAND_2GHZ)
1876 cmd->channel_flags = cpu_to_le32(0x00000081);
1877 else
1878 cmd->channel_flags = cpu_to_le32(0x00000000);
1879
1880 rc = mwl8k_post_cmd(hw, &cmd->header);
1881 kfree(cmd);
1882
1883 return rc;
1884}
1885
1886/*
1887 * CMD_SET_SLOT.
1888 */
1889struct mwl8k_cmd_set_slot {
1890 struct mwl8k_cmd_pkt header;
1891 __le16 action;
1892 __u8 short_slot;
1893} __attribute__((packed));
1894
5539bb51 1895static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 1896{
1897 struct mwl8k_cmd_set_slot *cmd;
1898 int rc;
1899
1900 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1901 if (cmd == NULL)
1902 return -ENOMEM;
1903
1904 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1905 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1906 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 1907 cmd->short_slot = short_slot_time;
a66098da
LB		 1908
1909 rc = mwl8k_post_cmd(hw, &cmd->header);
1910 kfree(cmd);
1911
1912 return rc;
1913}
1914
1915/*
1916 * CMD_MIMO_CONFIG.
1917 */
1918struct mwl8k_cmd_mimo_config {
1919 struct mwl8k_cmd_pkt header;
1920 __le32 action;
1921 __u8 rx_antenna_map;
1922 __u8 tx_antenna_map;
1923} __attribute__((packed));
1924
1925static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1926{
1927 struct mwl8k_cmd_mimo_config *cmd;
1928 int rc;
1929
1930 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1931 if (cmd == NULL)
1932 return -ENOMEM;
1933
1934 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1935 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1936 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1937 cmd->rx_antenna_map = rx;
1938 cmd->tx_antenna_map = tx;
1939
1940 rc = mwl8k_post_cmd(hw, &cmd->header);
1941 kfree(cmd);
1942
1943 return rc;
1944}
1945
1946/*
1947 * CMD_ENABLE_SNIFFER.
1948 */
1949struct mwl8k_cmd_enable_sniffer {
1950 struct mwl8k_cmd_pkt header;
1951 __le32 action;
1952} __attribute__((packed));
1953
1954static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1955{
1956 struct mwl8k_cmd_enable_sniffer *cmd;
1957 int rc;
1958
1959 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1960 if (cmd == NULL)
1961 return -ENOMEM;
1962
1963 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1964 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 1965 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 1966
1967 rc = mwl8k_post_cmd(hw, &cmd->header);
1968 kfree(cmd);
1969
1970 return rc;
1971}
1972
32060e1b
LB		 1973/*
1974 * CMD_SET_MAC_ADDR.
1975 */
1976struct mwl8k_cmd_set_mac_addr {
1977 struct mwl8k_cmd_pkt header;
1978 __u8 mac_addr[ETH_ALEN];
1979} __attribute__((packed));
1980
1981static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1982{
1983 struct mwl8k_cmd_set_mac_addr *cmd;
1984 int rc;
1985
1986 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1987 if (cmd == NULL)
1988 return -ENOMEM;
1989
1990 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1991 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1992 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1993
1994 rc = mwl8k_post_cmd(hw, &cmd->header);
1995 kfree(cmd);
1996
1997 return rc;
1998}
1999
2000
a66098da 2001/*
ce9e2e1b 2002 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2003 */
2004struct mwl8k_cmd_set_rate_adapt_mode {
2005 struct mwl8k_cmd_pkt header;
2006 __le16 action;
2007 __le16 mode;
2008} __attribute__((packed));
2009
2010static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2011{
2012 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2013 int rc;
2014
2015 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2016 if (cmd == NULL)
2017 return -ENOMEM;
2018
2019 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2020 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2021 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2022 cmd->mode = cpu_to_le16(mode);
2023
2024 rc = mwl8k_post_cmd(hw, &cmd->header);
2025 kfree(cmd);
2026
2027 return rc;
2028}
2029
2030/*
2031 * CMD_SET_WMM_MODE.
2032 */
2033struct mwl8k_cmd_set_wmm {
2034 struct mwl8k_cmd_pkt header;
2035 __le16 action;
2036} __attribute__((packed));
2037
2038static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2039{
2040 struct mwl8k_priv *priv = hw->priv;
2041 struct mwl8k_cmd_set_wmm *cmd;
2042 int rc;
2043
2044 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2045 if (cmd == NULL)
2046 return -ENOMEM;
2047
2048 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2049 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2050 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2051
2052 rc = mwl8k_post_cmd(hw, &cmd->header);
2053 kfree(cmd);
2054
2055 if (!rc)
0439b1f5 2056 priv->wmm_enabled = enable;
a66098da
LB		 2057
2058 return rc;
2059}
2060
2061/*
2062 * CMD_SET_RTS_THRESHOLD.
2063 */
2064struct mwl8k_cmd_rts_threshold {
2065 struct mwl8k_cmd_pkt header;
2066 __le16 action;
2067 __le16 threshold;
2068} __attribute__((packed));
2069
2070static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2071 u16 action, u16 threshold)
a66098da
LB		 2072{
2073 struct mwl8k_cmd_rts_threshold *cmd;
2074 int rc;
2075
2076 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2077 if (cmd == NULL)
2078 return -ENOMEM;
2079
2080 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2081 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2082 cmd->action = cpu_to_le16(action);
733d3067 2083 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2084
2085 rc = mwl8k_post_cmd(hw, &cmd->header);
2086 kfree(cmd);
2087
2088 return rc;
2089}
2090
2091/*
2092 * CMD_SET_EDCA_PARAMS.
2093 */
2094struct mwl8k_cmd_set_edca_params {
2095 struct mwl8k_cmd_pkt header;
2096
2097 /* See MWL8K_SET_EDCA_XXX below */
2098 __le16 action;
2099
2100 /* TX opportunity in units of 32 us */
2101 __le16 txop;
2102
2103 /* Log exponent of max contention period: 0...15*/
2104 __u8 log_cw_max;
2105
2106 /* Log exponent of min contention period: 0...15 */
2107 __u8 log_cw_min;
2108
2109 /* Adaptive interframe spacing in units of 32us */
2110 __u8 aifs;
2111
2112 /* TX queue to configure */
2113 __u8 txq;
2114} __attribute__((packed));
2115
a66098da
LB		 2116#define MWL8K_SET_EDCA_CW 0x01
2117#define MWL8K_SET_EDCA_TXOP 0x02
2118#define MWL8K_SET_EDCA_AIFS 0x04
2119
2120#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2121 MWL8K_SET_EDCA_TXOP | \
2122 MWL8K_SET_EDCA_AIFS)
2123
2124static int
2125mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2126 __u16 cw_min, __u16 cw_max,
2127 __u8 aifs, __u16 txop)
2128{
2129 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2130 int rc;
2131
2132 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2133 if (cmd == NULL)
2134 return -ENOMEM;
2135
22995b24
LB		 2136 /*
2137 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2138 * this call.
2139 */
2140 qnum ^= !(qnum >> 1);
2141
a66098da
LB		 2142 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2143 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2144 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2145 cmd->txop = cpu_to_le16(txop);
ce9e2e1b
LB		 2146 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2147 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
a66098da
LB		 2148 cmd->aifs = aifs;
2149 cmd->txq = qnum;
2150
2151 rc = mwl8k_post_cmd(hw, &cmd->header);
2152 kfree(cmd);
2153
2154 return rc;
2155}
2156
2157/*
2158 * CMD_FINALIZE_JOIN.
2159 */
2160
2161/* FJ beacon buffer size is compiled into the firmware. */
2162#define MWL8K_FJ_BEACON_MAXLEN 128
2163
2164struct mwl8k_cmd_finalize_join {
2165 struct mwl8k_cmd_pkt header;
2166 __le32 sleep_interval; /* Number of beacon periods to sleep */
2167 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2168} __attribute__((packed));
2169
2170static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2171 __u16 framelen, __u16 dtim)
2172{
2173 struct mwl8k_cmd_finalize_join *cmd;
2174 struct ieee80211_mgmt *payload = frame;
2175 u16 hdrlen;
2176 u32 payload_len;
2177 int rc;
2178
2179 if (frame == NULL)
2180 return -EINVAL;
2181
2182 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2183 if (cmd == NULL)
2184 return -ENOMEM;
2185
2186 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2187 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2188 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2189
2190 hdrlen = ieee80211_hdrlen(payload->frame_control);
2191
2192 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2193
2194 /* XXX TBD Might just have to abort and return an error */
2195 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2196 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2197 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2198 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2199
ce9e2e1b
LB		 2200 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2201 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2202
2203 if (payload && payload_len)
2204 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2205
2206 rc = mwl8k_post_cmd(hw, &cmd->header);
2207 kfree(cmd);
2208 return rc;
2209}
2210
2211/*
2212 * CMD_UPDATE_STADB.
2213 */
2214struct mwl8k_cmd_update_sta_db {
2215 struct mwl8k_cmd_pkt header;
2216
2217 /* See STADB_ACTION_TYPE */
2218 __le32 action;
2219
2220 /* Peer MAC address */
d89173f2 2221 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2222
2223 __le32 reserved;
2224
2225 /* Peer info - valid during add/update. */
2226 struct peer_capability_info peer_info;
2227} __attribute__((packed));
2228
2229static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2230 struct ieee80211_vif *vif, __u32 action)
2231{
2232 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2233 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2234 struct mwl8k_cmd_update_sta_db *cmd;
2235 struct peer_capability_info *peer_info;
2236 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2237 int rc;
2238 __u8 count, *rates;
2239
2240 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2241 if (cmd == NULL)
2242 return -ENOMEM;
2243
2244 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2245 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2246
2247 cmd->action = cpu_to_le32(action);
2248 peer_info = &cmd->peer_info;
d89173f2 2249 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2250
2251 switch (action) {
2252 case MWL8K_STA_DB_ADD_ENTRY:
2253 case MWL8K_STA_DB_MODIFY_ENTRY:
2254 /* Build peer_info block */
2255 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2256 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2257 peer_info->interop = 1;
2258 peer_info->amsdu_enabled = 0;
2259
2260 rates = peer_info->legacy_rates;
ce9e2e1b 2261 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2262 rates[count] = bitrates[count].hw_value;
2263
2264 rc = mwl8k_post_cmd(hw, &cmd->header);
2265 if (rc == 0)
2266 mv_vif->peer_id = peer_info->station_id;
2267
2268 break;
2269
2270 case MWL8K_STA_DB_DEL_ENTRY:
2271 case MWL8K_STA_DB_FLUSH:
2272 default:
2273 rc = mwl8k_post_cmd(hw, &cmd->header);
2274 if (rc == 0)
2275 mv_vif->peer_id = 0;
2276 break;
2277 }
2278 kfree(cmd);
2279
2280 return rc;
2281}
2282
2283/*
2284 * CMD_SET_AID.
2285 */
a66098da
LB		 2286#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2287
2288#define MWL8K_FRAME_PROT_DISABLED 0x00
2289#define MWL8K_FRAME_PROT_11G 0x07
2290#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2291#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2292
2293struct mwl8k_cmd_update_set_aid {
2294 struct mwl8k_cmd_pkt header;
2295 __le16 aid;
2296
2297 /* AP's MAC address (BSSID) */
d89173f2 2298 __u8 bssid[ETH_ALEN];
a66098da
LB		 2299 __le16 protection_mode;
2300 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2301} __attribute__((packed));
2302
2303static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2304 struct ieee80211_vif *vif)
2305{
2306 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2307 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2308 struct mwl8k_cmd_update_set_aid *cmd;
2309 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2310 int count;
2311 u16 prot_mode;
2312 int rc;
2313
2314 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2315 if (cmd == NULL)
2316 return -ENOMEM;
2317
2318 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2319 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2320 cmd->aid = cpu_to_le16(info->aid);
2321
d89173f2 2322 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2323
a66098da
LB		 2324 if (info->use_cts_prot) {
2325 prot_mode = MWL8K_FRAME_PROT_11G;
2326 } else {
9ed6bcce 2327 switch (info->ht_operation_mode &
a66098da
LB		 2328 IEEE80211_HT_OP_MODE_PROTECTION) {
2329 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2330 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2331 break;
2332 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2333 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2334 break;
2335 default:
2336 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2337 break;
2338 }
2339 }
a66098da
LB		 2340 cmd->protection_mode = cpu_to_le16(prot_mode);
2341
2342 for (count = 0; count < mv_vif->legacy_nrates; count++)
2343 cmd->supp_rates[count] = bitrates[count].hw_value;
2344
2345 rc = mwl8k_post_cmd(hw, &cmd->header);
2346 kfree(cmd);
2347
2348 return rc;
2349}
2350
2351/*
2352 * CMD_SET_RATE.
2353 */
2354struct mwl8k_cmd_update_rateset {
2355 struct mwl8k_cmd_pkt header;
2356 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2357
2358 /* Bitmap for supported MCS codes. */
2359 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2360 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2361} __attribute__((packed));
2362
2363static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2364 struct ieee80211_vif *vif)
2365{
2366 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2367 struct mwl8k_cmd_update_rateset *cmd;
2368 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2369 int count;
2370 int rc;
2371
2372 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2373 if (cmd == NULL)
2374 return -ENOMEM;
2375
2376 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2377 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2378
2379 for (count = 0; count < mv_vif->legacy_nrates; count++)
2380 cmd->legacy_rates[count] = bitrates[count].hw_value;
2381
2382 rc = mwl8k_post_cmd(hw, &cmd->header);
2383 kfree(cmd);
2384
2385 return rc;
2386}
2387
2388/*
2389 * CMD_USE_FIXED_RATE.
2390 */
2391#define MWL8K_RATE_TABLE_SIZE 8
2392#define MWL8K_UCAST_RATE 0
a66098da
LB		 2393#define MWL8K_USE_AUTO_RATE 0x0002
2394
2395struct mwl8k_rate_entry {
2396 /* Set to 1 if HT rate, 0 if legacy. */
2397 __le32 is_ht_rate;
2398
2399 /* Set to 1 to use retry_count field. */
2400 __le32 enable_retry;
2401
2402 /* Specified legacy rate or MCS. */
2403 __le32 rate;
2404
2405 /* Number of allowed retries. */
2406 __le32 retry_count;
2407} __attribute__((packed));
2408
2409struct mwl8k_rate_table {
2410 /* 1 to allow specified rate and below */
2411 __le32 allow_rate_drop;
2412 __le32 num_rates;
2413 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2414} __attribute__((packed));
2415
2416struct mwl8k_cmd_use_fixed_rate {
2417 struct mwl8k_cmd_pkt header;
2418 __le32 action;
2419 struct mwl8k_rate_table rate_table;
2420
2421 /* Unicast, Broadcast or Multicast */
2422 __le32 rate_type;
2423 __le32 reserved1;
2424 __le32 reserved2;
2425} __attribute__((packed));
2426
2427static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2428 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2429{
2430 struct mwl8k_cmd_use_fixed_rate *cmd;
2431 int count;
2432 int rc;
2433
2434 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2435 if (cmd == NULL)
2436 return -ENOMEM;
2437
2438 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2439 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2440
2441 cmd->action = cpu_to_le32(action);
2442 cmd->rate_type = cpu_to_le32(rate_type);
2443
2444 if (rate_table != NULL) {
c2c357ce
LB		 2445 /*
2446 * Copy over each field manually so that endian
2447 * conversion can be done.
2448 */
a66098da
LB		 2449 cmd->rate_table.allow_rate_drop =
2450 cpu_to_le32(rate_table->allow_rate_drop);
2451 cmd->rate_table.num_rates =
2452 cpu_to_le32(rate_table->num_rates);
2453
2454 for (count = 0; count < rate_table->num_rates; count++) {
2455 struct mwl8k_rate_entry *dst =
2456 &cmd->rate_table.rate_entry[count];
2457 struct mwl8k_rate_entry *src =
2458 &rate_table->rate_entry[count];
2459
2460 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2461 dst->enable_retry = cpu_to_le32(src->enable_retry);
2462 dst->rate = cpu_to_le32(src->rate);
2463 dst->retry_count = cpu_to_le32(src->retry_count);
2464 }
2465 }
2466
2467 rc = mwl8k_post_cmd(hw, &cmd->header);
2468 kfree(cmd);
2469
2470 return rc;
2471}
2472
2473
2474/*
2475 * Interrupt handling.
2476 */
2477static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2478{
2479 struct ieee80211_hw *hw = dev_id;
2480 struct mwl8k_priv *priv = hw->priv;
2481 u32 status;
2482
2483 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2484 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2485
a66098da
LB		 2486 if (!status)
2487 return IRQ_NONE;
2488
2489 if (status & MWL8K_A2H_INT_TX_DONE)
2490 tasklet_schedule(&priv->tx_reclaim_task);
2491
2492 if (status & MWL8K_A2H_INT_RX_READY) {
2493 while (rxq_process(hw, 0, 1))
2494 rxq_refill(hw, 0, 1);
2495 }
2496
2497 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2498 if (priv->hostcmd_wait != NULL)
a66098da 2499 complete(priv->hostcmd_wait);
a66098da
LB		 2500 }
2501
2502 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2503 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2504 priv->radio_on && priv->pending_tx_pkts)
618952a7 2505 mwl8k_tx_start(priv);
a66098da
LB		 2506 }
2507
2508 return IRQ_HANDLED;
2509}
2510
2511
2512/*
2513 * Core driver operations.
2514 */
2515static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2516{
2517 struct mwl8k_priv *priv = hw->priv;
2518 int index = skb_get_queue_mapping(skb);
2519 int rc;
2520
2521 if (priv->current_channel == NULL) {
2522 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2523 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2524 dev_kfree_skb(skb);
2525 return NETDEV_TX_OK;
2526 }
2527
2528 rc = mwl8k_txq_xmit(hw, index, skb);
2529
2530 return rc;
2531}
2532
a66098da
LB		 2533static int mwl8k_start(struct ieee80211_hw *hw)
2534{
a66098da
LB		 2535 struct mwl8k_priv *priv = hw->priv;
2536 int rc;
2537
a66098da
LB		 2538 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2539 IRQF_SHARED, MWL8K_NAME, hw);
2540 if (rc) {
2541 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2542 wiphy_name(hw->wiphy));
2ec610cb 2543 return -EIO;
a66098da
LB		 2544 }
2545
2ec610cb
LB		 2546 /* Enable tx reclaim tasklet */
2547 tasklet_enable(&priv->tx_reclaim_task);
2548
a66098da 2549 /* Enable interrupts */
c23b5a69 2550 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2551
2ec610cb
LB		 2552 rc = mwl8k_fw_lock(hw);
2553 if (!rc) {
2554 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2555
2ec610cb
LB		 2556 if (!rc)
2557 rc = mwl8k_cmd_set_pre_scan(hw);
a66098da 2558
2ec610cb
LB		 2559 if (!rc)
2560 rc = mwl8k_cmd_set_post_scan(hw,
2561 "\x00\x00\x00\x00\x00\x00");
2562
2563 if (!rc)
2564 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2565
2ec610cb
LB		 2566 if (!rc)
2567 rc = mwl8k_set_wmm(hw, 0);
a66098da 2568
2ec610cb
LB		 2569 if (!rc)
2570 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2571
2ec610cb
LB		 2572 mwl8k_fw_unlock(hw);
2573 }
2574
2575 if (rc) {
2576 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2577 free_irq(priv->pdev->irq, hw);
2578 tasklet_disable(&priv->tx_reclaim_task);
2579 }
a66098da
LB		 2580
2581 return rc;
2582}
2583
a66098da
LB		 2584static void mwl8k_stop(struct ieee80211_hw *hw)
2585{
a66098da
LB		 2586 struct mwl8k_priv *priv = hw->priv;
2587 int i;
2588
d3cea0b8 2589 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2590
2591 ieee80211_stop_queues(hw);
2592
a66098da 2593 /* Disable interrupts */
a66098da 2594 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2595 free_irq(priv->pdev->irq, hw);
2596
2597 /* Stop finalize join worker */
2598 cancel_work_sync(&priv->finalize_join_worker);
2599 if (priv->beacon_skb != NULL)
2600 dev_kfree_skb(priv->beacon_skb);
2601
2602 /* Stop tx reclaim tasklet */
2603 tasklet_disable(&priv->tx_reclaim_task);
2604
a66098da
LB		 2605 /* Return all skbs to mac80211 */
2606 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2607 mwl8k_txq_reclaim(hw, i, 1);
2608}
2609
2610static int mwl8k_add_interface(struct ieee80211_hw *hw,
2611 struct ieee80211_if_init_conf *conf)
2612{
2613 struct mwl8k_priv *priv = hw->priv;
2614 struct mwl8k_vif *mwl8k_vif;
2615
2616 /*
2617 * We only support one active interface at a time.
2618 */
2619 if (priv->vif != NULL)
2620 return -EBUSY;
2621
2622 /*
2623 * We only support managed interfaces for now.
2624 */
240e86ef 2625 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2626 return -EINVAL;
2627
a43c49a8
LB		 2628 /*
2629 * Reject interface creation if sniffer mode is active, as
2630 * STA operation is mutually exclusive with hardware sniffer
2631 * mode.
2632 */
2633 if (priv->sniffer_enabled) {
2634 printk(KERN_INFO "%s: unable to create STA "
2635 "interface due to sniffer mode being enabled\n",
2636 wiphy_name(hw->wiphy));
2637 return -EINVAL;
2638 }
2639
a66098da
LB		 2640 /* Clean out driver private area */
2641 mwl8k_vif = MWL8K_VIF(conf->vif);
2642 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2643
32060e1b
LB		 2644 /* Set and save the mac address */
2645 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2646 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2647
2648 /* Back pointer to parent config block */
2649 mwl8k_vif->priv = priv;
2650
2651 /* Setup initial PHY parameters */
ce9e2e1b 2652 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2653 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2654 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2655
2656 /* Set Initial sequence number to zero */
2657 mwl8k_vif->seqno = 0;
2658
2659 priv->vif = conf->vif;
2660 priv->current_channel = NULL;
2661
2662 return 0;
2663}
2664
2665static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2666 struct ieee80211_if_init_conf *conf)
2667{
2668 struct mwl8k_priv *priv = hw->priv;
2669
2670 if (priv->vif == NULL)
2671 return;
2672
32060e1b
LB		 2673 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2674
a66098da
LB		 2675 priv->vif = NULL;
2676}
2677
ee03a932 2678static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2679{
a66098da
LB		 2680 struct ieee80211_conf *conf = &hw->conf;
2681 struct mwl8k_priv *priv = hw->priv;
ee03a932 2682 int rc;
a66098da 2683
7595d67a
LB		 2684 if (conf->flags & IEEE80211_CONF_IDLE) {
2685 mwl8k_cmd_802_11_radio_disable(hw);
2686 priv->current_channel = NULL;
ee03a932 2687 return 0;
7595d67a
LB		 2688 }
2689
ee03a932
LB		 2690 rc = mwl8k_fw_lock(hw);
2691 if (rc)
2692 return rc;
a66098da 2693
ee03a932
LB		 2694 rc = mwl8k_cmd_802_11_radio_enable(hw);
2695 if (rc)
2696 goto out;
a66098da 2697
ee03a932
LB		 2698 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2699 if (rc)
2700 goto out;
2701
2702 priv->current_channel = conf->channel;
a66098da
LB		 2703
2704 if (conf->power_level > 18)
2705 conf->power_level = 18;
ee03a932
LB		 2706 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2707 if (rc)
2708 goto out;
a66098da
LB		 2709
2710 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2711 rc = -EINVAL;
2712
ee03a932
LB		 2713out:
2714 mwl8k_fw_unlock(hw);
a66098da 2715
ee03a932 2716 return rc;
a66098da
LB		 2717}
2718
3a980d0a
LB		 2719static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2720 struct ieee80211_vif *vif,
2721 struct ieee80211_bss_conf *info,
2722 u32 changed)
a66098da 2723{
a66098da
LB		 2724 struct mwl8k_priv *priv = hw->priv;
2725 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 2726 int rc;
2727
2728 if (changed & BSS_CHANGED_BSSID)
2729 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2730
2731 if ((changed & BSS_CHANGED_ASSOC) == 0)
2732 return;
a66098da 2733
a66098da
LB		 2734 priv->capture_beacon = false;
2735
3a980d0a 2736 rc = mwl8k_fw_lock(hw);
942457d6 2737 if (rc)
3a980d0a
LB		 2738 return;
2739
a66098da
LB		 2740 if (info->assoc) {
2741 memcpy(&mwl8k_vif->bss_info, info,
2742 sizeof(struct ieee80211_bss_conf));
2743
2744 /* Install rates */
3a980d0a
LB		 2745 rc = mwl8k_update_rateset(hw, vif);
2746 if (rc)
2747 goto out;
a66098da
LB		 2748
2749 /* Turn on rate adaptation */
3a980d0a
LB		 2750 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2751 MWL8K_UCAST_RATE, NULL);
2752 if (rc)
2753 goto out;
a66098da
LB		 2754
2755 /* Set radio preamble */
3a980d0a
LB		 2756 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2757 if (rc)
2758 goto out;
a66098da
LB		 2759
2760 /* Set slot time */
3a980d0a
LB		 2761 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2762 if (rc)
2763 goto out;
a66098da
LB		 2764
2765 /* Update peer rate info */
3a980d0a
LB		 2766 rc = mwl8k_cmd_update_sta_db(hw, vif,
2767 MWL8K_STA_DB_MODIFY_ENTRY);
2768 if (rc)
2769 goto out;
a66098da
LB		 2770
2771 /* Set AID */
3a980d0a
LB		 2772 rc = mwl8k_cmd_set_aid(hw, vif);
2773 if (rc)
2774 goto out;
a66098da
LB		 2775
2776 /*
2777 * Finalize the join. Tell rx handler to process
2778 * next beacon from our BSSID.
2779 */
d89173f2 2780 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 2781 priv->capture_beacon = true;
2782 } else {
3a980d0a 2783 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 2784 memset(&mwl8k_vif->bss_info, 0,
2785 sizeof(struct ieee80211_bss_conf));
d89173f2 2786 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 2787 }
2788
3a980d0a
LB		 2789out:
2790 mwl8k_fw_unlock(hw);
a66098da
LB		 2791}
2792
e81cd2d6
LB		 2793static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2794 int mc_count, struct dev_addr_list *mclist)
2795{
2796 struct mwl8k_cmd_pkt *cmd;
2797
447ced07
LB		 2798 /*
2799 * Synthesize and return a command packet that programs the
2800 * hardware multicast address filter. At this point we don't
2801 * know whether FIF_ALLMULTI is being requested, but if it is,
2802 * we'll end up throwing this packet away and creating a new
2803 * one in mwl8k_configure_filter().
2804 */
2805 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 2806
2807 return (unsigned long)cmd;
2808}
2809
a43c49a8
LB		 2810static int
2811mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2812 unsigned int changed_flags,
2813 unsigned int *total_flags)
2814{
2815 struct mwl8k_priv *priv = hw->priv;
2816
2817 /*
2818 * Hardware sniffer mode is mutually exclusive with STA
2819 * operation, so refuse to enable sniffer mode if a STA
2820 * interface is active.
2821 */
2822 if (priv->vif != NULL) {
2823 if (net_ratelimit())
2824 printk(KERN_INFO "%s: not enabling sniffer "
2825 "mode because STA interface is active\n",
2826 wiphy_name(hw->wiphy));
2827 return 0;
2828 }
2829
2830 if (!priv->sniffer_enabled) {
2831 if (mwl8k_enable_sniffer(hw, 1))
2832 return 0;
2833 priv->sniffer_enabled = true;
2834 }
2835
2836 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
2837 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
2838 FIF_OTHER_BSS;
2839
2840 return 1;
2841}
2842
e6935ea1
LB		 2843static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2844 unsigned int changed_flags,
2845 unsigned int *total_flags,
2846 u64 multicast)
2847{
2848 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 2849 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
2850
2851 /*
2852 * Enable hardware sniffer mode if FIF_CONTROL or
2853 * FIF_OTHER_BSS is requested.
2854 */
2855 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
2856 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
2857 kfree(cmd);
2858 return;
2859 }
a66098da 2860
e6935ea1 2861 /* Clear unsupported feature flags */
447ced07 2862 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 2863
e6935ea1
LB		 2864 if (mwl8k_fw_lock(hw))
2865 return;
a66098da 2866
a43c49a8
LB		 2867 if (priv->sniffer_enabled) {
2868 mwl8k_enable_sniffer(hw, 0);
2869 priv->sniffer_enabled = false;
2870 }
2871
e6935ea1 2872 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 2873 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2874 /*
2875 * Disable the BSS filter.
2876 */
e6935ea1 2877 mwl8k_cmd_set_pre_scan(hw);
77165d88 2878 } else {
a94cc97e
LB		 2879 u8 *bssid;
2880
77165d88
LB		 2881 /*
2882 * Enable the BSS filter.
2883 *
2884 * If there is an active STA interface, use that
2885 * interface's BSSID, otherwise use a dummy one
2886 * (where the OUI part needs to be nonzero for
2887 * the BSSID to be accepted by POST_SCAN).
2888 */
2889 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 2890 if (priv->vif != NULL)
2891 bssid = MWL8K_VIF(priv->vif)->bssid;
2892
e6935ea1 2893 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 2894 }
2895 }
2896
447ced07
LB		 2897 /*
2898 * If FIF_ALLMULTI is being requested, throw away the command
2899 * packet that ->prepare_multicast() built and replace it with
2900 * a command packet that enables reception of all multicast
2901 * packets.
2902 */
2903 if (*total_flags & FIF_ALLMULTI) {
2904 kfree(cmd);
2905 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2906 }
2907
2908 if (cmd != NULL) {
2909 mwl8k_post_cmd(hw, cmd);
2910 kfree(cmd);
e6935ea1 2911 }
a66098da 2912
e6935ea1 2913 mwl8k_fw_unlock(hw);
a66098da
LB		 2914}
2915
a66098da
LB		 2916static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2917{
733d3067 2918 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 2919}
2920
a66098da
LB		 2921static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2922 const struct ieee80211_tx_queue_params *params)
2923{
3e4f542c 2924 struct mwl8k_priv *priv = hw->priv;
a66098da 2925 int rc;
a66098da 2926
3e4f542c
LB		 2927 rc = mwl8k_fw_lock(hw);
2928 if (!rc) {
2929 if (!priv->wmm_enabled)
2930 rc = mwl8k_set_wmm(hw, 1);
a66098da 2931
3e4f542c
LB		 2932 if (!rc)
2933 rc = mwl8k_set_edca_params(hw, queue,
2934 params->cw_min,
2935 params->cw_max,
2936 params->aifs,
2937 params->txop);
2938
2939 mwl8k_fw_unlock(hw);
a66098da 2940 }
3e4f542c 2941
a66098da
LB		 2942 return rc;
2943}
2944
2945static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2946 struct ieee80211_tx_queue_stats *stats)
2947{
2948 struct mwl8k_priv *priv = hw->priv;
2949 struct mwl8k_tx_queue *txq;
2950 int index;
2951
2952 spin_lock_bh(&priv->tx_lock);
2953 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2954 txq = priv->txq + index;
45eb400d 2955 memcpy(&stats[index], &txq->stats,
a66098da
LB		 2956 sizeof(struct ieee80211_tx_queue_stats));
2957 }
2958 spin_unlock_bh(&priv->tx_lock);
a66098da 2959
954ef509 2960 return 0;
a66098da
LB		 2961}
2962
2963static int mwl8k_get_stats(struct ieee80211_hw *hw,
2964 struct ieee80211_low_level_stats *stats)
2965{
954ef509 2966 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 2967}
2968
2969static const struct ieee80211_ops mwl8k_ops = {
2970 .tx = mwl8k_tx,
2971 .start = mwl8k_start,
2972 .stop = mwl8k_stop,
2973 .add_interface = mwl8k_add_interface,
2974 .remove_interface = mwl8k_remove_interface,
2975 .config = mwl8k_config,
a66098da 2976 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 2977 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 2978 .configure_filter = mwl8k_configure_filter,
2979 .set_rts_threshold = mwl8k_set_rts_threshold,
2980 .conf_tx = mwl8k_conf_tx,
2981 .get_tx_stats = mwl8k_get_tx_stats,
2982 .get_stats = mwl8k_get_stats,
2983};
2984
2985static void mwl8k_tx_reclaim_handler(unsigned long data)
2986{
2987 int i;
2988 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2989 struct mwl8k_priv *priv = hw->priv;
2990
2991 spin_lock_bh(&priv->tx_lock);
2992 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2993 mwl8k_txq_reclaim(hw, i, 0);
2994
88de754a 2995 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 2996 complete(priv->tx_wait);
2997 priv->tx_wait = NULL;
a66098da
LB		 2998 }
2999 spin_unlock_bh(&priv->tx_lock);
3000}
3001
3002static void mwl8k_finalize_join_worker(struct work_struct *work)
3003{
3004 struct mwl8k_priv *priv =
3005 container_of(work, struct mwl8k_priv, finalize_join_worker);
3006 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3007 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3008
3009 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3010 dev_kfree_skb(skb);
3011
3012 priv->beacon_skb = NULL;
3013}
3014
45a390dd 3015static struct mwl8k_device_info di_8687 = {
a74b295e
LB		 3016 .part_name = "88w8687",
3017 .helper_image = "mwl8k/helper_8687.fw",
3018 .fw_image = "mwl8k/fmimage_8687.fw",
54bc3a0d 3019 .rxd_ops = &rxd_8687_ops,
547810e3 3020 .modes = BIT(NL80211_IFTYPE_STATION),
45a390dd
LB		 3021};
3022
3023static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3024 {
3025 PCI_VDEVICE(MARVELL, 0x2a2b),
3026 .driver_data = (unsigned long)&di_8687,
3027 }, {
3028 PCI_VDEVICE(MARVELL, 0x2a30),
3029 .driver_data = (unsigned long)&di_8687,
3030 }, {
3031 },
3032};
3033MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3034
a66098da
LB		 3035static int __devinit mwl8k_probe(struct pci_dev *pdev,
3036 const struct pci_device_id *id)
3037{
2aa7b01f 3038 static int printed_version = 0;
a66098da
LB		 3039 struct ieee80211_hw *hw;
3040 struct mwl8k_priv *priv;
a66098da
LB		 3041 int rc;
3042 int i;
2aa7b01f
LB		 3043
3044 if (!printed_version) {
3045 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3046 printed_version = 1;
3047 }
a66098da
LB		 3048
3049 rc = pci_enable_device(pdev);
3050 if (rc) {
3051 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3052 MWL8K_NAME);
3053 return rc;
3054 }
3055
3056 rc = pci_request_regions(pdev, MWL8K_NAME);
3057 if (rc) {
3058 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3059 MWL8K_NAME);
3060 return rc;
3061 }
3062
3063 pci_set_master(pdev);
3064
3065 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3066 if (hw == NULL) {
3067 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3068 rc = -ENOMEM;
3069 goto err_free_reg;
3070 }
3071
3072 priv = hw->priv;
3073 priv->hw = hw;
3074 priv->pdev = pdev;
45a390dd 3075 priv->device_info = (void *)id->driver_data;
54bc3a0d 3076 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3077 priv->sniffer_enabled = false;
0439b1f5 3078 priv->wmm_enabled = false;
a66098da 3079 priv->pending_tx_pkts = 0;
a66098da 3080
a66098da
LB		 3081 SET_IEEE80211_DEV(hw, &pdev->dev);
3082 pci_set_drvdata(pdev, hw);
3083
5b9482dd
LB		 3084 priv->sram = pci_iomap(pdev, 0, 0x10000);
3085 if (priv->sram == NULL) {
3086 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3087 wiphy_name(hw->wiphy));
a66098da
LB		 3088 goto err_iounmap;
3089 }
3090
5b9482dd
LB		 3091 /*
3092 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3093 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3094 */
3095 priv->regs = pci_iomap(pdev, 1, 0x10000);
3096 if (priv->regs == NULL) {
3097 priv->regs = pci_iomap(pdev, 2, 0x10000);
3098 if (priv->regs == NULL) {
3099 printk(KERN_ERR "%s: Cannot map device registers\n",
3100 wiphy_name(hw->wiphy));
3101 goto err_iounmap;
3102 }
3103 }
3104
a66098da
LB		 3105 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3106 priv->band.band = IEEE80211_BAND_2GHZ;
3107 priv->band.channels = priv->channels;
3108 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3109 priv->band.bitrates = priv->rates;
3110 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3111 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3112
3113 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3114 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3115
3116 /*
3117 * Extra headroom is the size of the required DMA header
3118 * minus the size of the smallest 802.11 frame (CTS frame).
3119 */
3120 hw->extra_tx_headroom =
3121 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3122
3123 hw->channel_change_time = 10;
3124
3125 hw->queues = MWL8K_TX_QUEUES;
3126
547810e3 3127 hw->wiphy->interface_modes = priv->device_info->modes;
a66098da
LB		 3128
3129 /* Set rssi and noise values to dBm */
ce9e2e1b 3130 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3131 hw->vif_data_size = sizeof(struct mwl8k_vif);
3132 priv->vif = NULL;
3133
3134 /* Set default radio state and preamble */
c46563b7 3135 priv->radio_on = 0;
68ce3884 3136 priv->radio_short_preamble = 0;
a66098da
LB		 3137
3138 /* Finalize join worker */
3139 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3140
3141 /* TX reclaim tasklet */
3142 tasklet_init(&priv->tx_reclaim_task,
3143 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3144 tasklet_disable(&priv->tx_reclaim_task);
3145
a66098da
LB		 3146 /* Power management cookie */
3147 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3148 if (priv->cookie == NULL)
3149 goto err_iounmap;
3150
3151 rc = mwl8k_rxq_init(hw, 0);
3152 if (rc)
3153 goto err_iounmap;
3154 rxq_refill(hw, 0, INT_MAX);
3155
618952a7
LB		 3156 mutex_init(&priv->fw_mutex);
3157 priv->fw_mutex_owner = NULL;
3158 priv->fw_mutex_depth = 0;
618952a7
LB		 3159 priv->hostcmd_wait = NULL;
3160
a66098da
LB		 3161 spin_lock_init(&priv->tx_lock);
3162
88de754a
LB		 3163 priv->tx_wait = NULL;
3164
a66098da
LB		 3165 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3166 rc = mwl8k_txq_init(hw, i);
3167 if (rc)
3168 goto err_free_queues;
3169 }
3170
3171 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3172 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3173 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3174 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3175
3176 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3177 IRQF_SHARED, MWL8K_NAME, hw);
3178 if (rc) {
3179 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3180 wiphy_name(hw->wiphy));
a66098da
LB		 3181 goto err_free_queues;
3182 }
3183
3184 /* Reset firmware and hardware */
3185 mwl8k_hw_reset(priv);
3186
3187 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3188 rc = mwl8k_request_firmware(priv);
a66098da 3189 if (rc) {
c2c357ce
LB		 3190 printk(KERN_ERR "%s: Firmware files not found\n",
3191 wiphy_name(hw->wiphy));
a66098da
LB		 3192 goto err_free_irq;
3193 }
3194
3195 /* Load firmware into hardware */
c2c357ce 3196 rc = mwl8k_load_firmware(hw);
a66098da 3197 if (rc) {
c2c357ce
LB		 3198 printk(KERN_ERR "%s: Cannot start firmware\n",
3199 wiphy_name(hw->wiphy));
a66098da
LB		 3200 goto err_stop_firmware;
3201 }
3202
3203 /* Reclaim memory once firmware is successfully loaded */
3204 mwl8k_release_firmware(priv);
3205
3206 /*
3207 * Temporarily enable interrupts. Initial firmware host
3208 * commands use interrupts and avoids polling. Disable
3209 * interrupts when done.
3210 */
c23b5a69 3211 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3212
3213 /* Get config data, mac addrs etc */
04b147b1 3214 rc = mwl8k_cmd_get_hw_spec_sta(hw);
a66098da 3215 if (rc) {
c2c357ce
LB		 3216 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3217 wiphy_name(hw->wiphy));
a66098da
LB		 3218 goto err_stop_firmware;
3219 }
3220
3221 /* Turn radio off */
c46563b7 3222 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3223 if (rc) {
c2c357ce 3224 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3225 goto err_stop_firmware;
3226 }
3227
32060e1b
LB		 3228 /* Clear MAC address */
3229 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3230 if (rc) {
3231 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3232 wiphy_name(hw->wiphy));
3233 goto err_stop_firmware;
3234 }
3235
a66098da 3236 /* Disable interrupts */
a66098da 3237 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3238 free_irq(priv->pdev->irq, hw);
3239
3240 rc = ieee80211_register_hw(hw);
3241 if (rc) {
c2c357ce
LB		 3242 printk(KERN_ERR "%s: Cannot register device\n",
3243 wiphy_name(hw->wiphy));
a66098da
LB		 3244 goto err_stop_firmware;
3245 }
3246
eae74e65 3247 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3248 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3249 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3250 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3251 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3252 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3253
3254 return 0;
3255
3256err_stop_firmware:
3257 mwl8k_hw_reset(priv);
3258 mwl8k_release_firmware(priv);
3259
3260err_free_irq:
a66098da 3261 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3262 free_irq(priv->pdev->irq, hw);
3263
3264err_free_queues:
3265 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3266 mwl8k_txq_deinit(hw, i);
3267 mwl8k_rxq_deinit(hw, 0);
3268
3269err_iounmap:
3270 if (priv->cookie != NULL)
3271 pci_free_consistent(priv->pdev, 4,
3272 priv->cookie, priv->cookie_dma);
3273
3274 if (priv->regs != NULL)
3275 pci_iounmap(pdev, priv->regs);
3276
5b9482dd
LB		 3277 if (priv->sram != NULL)
3278 pci_iounmap(pdev, priv->sram);
3279
a66098da
LB		 3280 pci_set_drvdata(pdev, NULL);
3281 ieee80211_free_hw(hw);
3282
3283err_free_reg:
3284 pci_release_regions(pdev);
3285 pci_disable_device(pdev);
3286
3287 return rc;
3288}
3289
230f7af0 3290static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3291{
3292 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3293}
3294
230f7af0 3295static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3296{
3297 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3298 struct mwl8k_priv *priv;
3299 int i;
3300
3301 if (hw == NULL)
3302 return;
3303 priv = hw->priv;
3304
3305 ieee80211_stop_queues(hw);
3306
60aa569f
LB		 3307 ieee80211_unregister_hw(hw);
3308
a66098da
LB		 3309 /* Remove tx reclaim tasklet */
3310 tasklet_kill(&priv->tx_reclaim_task);
3311
a66098da
LB		 3312 /* Stop hardware */
3313 mwl8k_hw_reset(priv);
3314
3315 /* Return all skbs to mac80211 */
3316 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3317 mwl8k_txq_reclaim(hw, i, 1);
3318
a66098da
LB		 3319 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3320 mwl8k_txq_deinit(hw, i);
3321
3322 mwl8k_rxq_deinit(hw, 0);
3323
c2c357ce 3324 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3325
3326 pci_iounmap(pdev, priv->regs);
5b9482dd 3327 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3328 pci_set_drvdata(pdev, NULL);
3329 ieee80211_free_hw(hw);
3330 pci_release_regions(pdev);
3331 pci_disable_device(pdev);
3332}
3333
3334static struct pci_driver mwl8k_driver = {
3335 .name = MWL8K_NAME,
45a390dd 3336 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3337 .probe = mwl8k_probe,
3338 .remove = __devexit_p(mwl8k_remove),
3339 .shutdown = __devexit_p(mwl8k_shutdown),
3340};
3341
3342static int __init mwl8k_init(void)
3343{
3344 return pci_register_driver(&mwl8k_driver);
3345}
3346
3347static void __exit mwl8k_exit(void)
3348{
3349 pci_unregister_driver(&mwl8k_driver);
3350}
3351
3352module_init(mwl8k_init);
3353module_exit(mwl8k_exit);
c2c357ce
LB		 3354
3355MODULE_DESCRIPTION(MWL8K_DESC);
3356MODULE_VERSION(MWL8K_VERSION);
3357MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3358MODULE_LICENSE("GPL");
Motorola kernel-slsi