Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
43 | #include <net/ieee80211_radiotap.h> | |
7e272fcf | 44 | #include <net/lib80211.h> |
b481de9c ZY |
45 | #include <net/mac80211.h> |
46 | ||
47 | #include <asm/div64.h> | |
48 | ||
a3139c59 SO |
49 | #define DRV_NAME "iwl3945" |
50 | ||
dbb6654c WT |
51 | #include "iwl-fh.h" |
52 | #include "iwl-3945-fh.h" | |
600c0e11 | 53 | #include "iwl-commands.h" |
b481de9c ZY |
54 | #include "iwl-3945.h" |
55 | #include "iwl-helpers.h" | |
5747d47f | 56 | #include "iwl-core.h" |
d20b3c65 | 57 | #include "iwl-dev.h" |
b481de9c | 58 | |
b481de9c ZY |
59 | /* |
60 | * module name, copyright, version, etc. | |
b481de9c ZY |
61 | */ |
62 | ||
63 | #define DRV_DESCRIPTION \ | |
64 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
65 | ||
c8b0e6e1 | 66 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
67 | #define VD "d" |
68 | #else | |
69 | #define VD | |
70 | #endif | |
71 | ||
c8b0e6e1 | 72 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
73 | #define VS "s" |
74 | #else | |
75 | #define VS | |
76 | #endif | |
77 | ||
eaa686c3 | 78 | #define IWL39_VERSION "1.2.26k" VD VS |
01f8162a | 79 | #define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation" |
a7b75207 | 80 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
eaa686c3 | 81 | #define DRV_VERSION IWL39_VERSION |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
87 | MODULE_LICENSE("GPL"); |
88 | ||
df878d8f KA |
89 | /* module parameters */ |
90 | struct iwl_mod_params iwl3945_mod_params = { | |
91 | .num_of_queues = IWL39_MAX_NUM_QUEUES, | |
9c74d9fb | 92 | .sw_crypto = 1, |
df878d8f KA |
93 | /* the rest are 0 by default */ |
94 | }; | |
95 | ||
b481de9c ZY |
96 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
97 | * DMA services | |
98 | * | |
99 | * Theory of operation | |
100 | * | |
6440adb5 BC |
101 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer |
102 | * of buffer descriptors, each of which points to one or more data buffers for | |
103 | * the device to read from or fill. Driver and device exchange status of each | |
104 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
105 | * entries in each circular buffer, to protect against confusing empty and full | |
106 | * queue states. | |
107 | * | |
108 | * The device reads or writes the data in the queues via the device's several | |
109 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
b481de9c ZY |
110 | * |
111 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
112 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
113 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
114 | * Tx queue resumed. | |
115 | * | |
6440adb5 BC |
116 | * The 3945 operates with six queues: One receive queue, one transmit queue |
117 | * (#4) for sending commands to the device firmware, and four transmit queues | |
118 | * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused. | |
b481de9c ZY |
119 | ***************************************************/ |
120 | ||
6440adb5 BC |
121 | /** |
122 | * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes | |
123 | */ | |
4a8a4322 | 124 | static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
b481de9c ZY |
125 | int count, int slots_num, u32 id) |
126 | { | |
127 | q->n_bd = count; | |
128 | q->n_window = slots_num; | |
129 | q->id = id; | |
130 | ||
c54b679d TW |
131 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap |
132 | * and iwl_queue_dec_wrap are broken. */ | |
b481de9c ZY |
133 | BUG_ON(!is_power_of_2(count)); |
134 | ||
135 | /* slots_num must be power-of-two size, otherwise | |
136 | * get_cmd_index is broken. */ | |
137 | BUG_ON(!is_power_of_2(slots_num)); | |
138 | ||
139 | q->low_mark = q->n_window / 4; | |
140 | if (q->low_mark < 4) | |
141 | q->low_mark = 4; | |
142 | ||
143 | q->high_mark = q->n_window / 8; | |
144 | if (q->high_mark < 2) | |
145 | q->high_mark = 2; | |
146 | ||
fc4b6853 | 147 | q->write_ptr = q->read_ptr = 0; |
b481de9c ZY |
148 | |
149 | return 0; | |
150 | } | |
151 | ||
6440adb5 BC |
152 | /** |
153 | * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
154 | */ | |
4a8a4322 | 155 | static int iwl3945_tx_queue_alloc(struct iwl_priv *priv, |
188cf6c7 | 156 | struct iwl_tx_queue *txq, u32 id) |
b481de9c ZY |
157 | { |
158 | struct pci_dev *dev = priv->pci_dev; | |
159 | ||
6440adb5 BC |
160 | /* Driver private data, only for Tx (not command) queues, |
161 | * not shared with device. */ | |
b481de9c ZY |
162 | if (id != IWL_CMD_QUEUE_NUM) { |
163 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
164 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
165 | if (!txq->txb) { | |
15b1687c | 166 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
b481de9c ZY |
167 | "structures failed\n"); |
168 | goto error; | |
169 | } | |
170 | } else | |
171 | txq->txb = NULL; | |
172 | ||
6440adb5 BC |
173 | /* Circular buffer of transmit frame descriptors (TFDs), |
174 | * shared with device */ | |
188cf6c7 SO |
175 | txq->tfds39 = pci_alloc_consistent(dev, |
176 | sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX, | |
b481de9c ZY |
177 | &txq->q.dma_addr); |
178 | ||
188cf6c7 | 179 | if (!txq->tfds39) { |
15b1687c | 180 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", |
188cf6c7 | 181 | sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX); |
b481de9c ZY |
182 | goto error; |
183 | } | |
184 | txq->q.id = id; | |
185 | ||
186 | return 0; | |
187 | ||
188 | error: | |
3ac7f146 TW |
189 | kfree(txq->txb); |
190 | txq->txb = NULL; | |
b481de9c ZY |
191 | |
192 | return -ENOMEM; | |
193 | } | |
194 | ||
6440adb5 BC |
195 | /** |
196 | * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue | |
197 | */ | |
4a8a4322 | 198 | int iwl3945_tx_queue_init(struct iwl_priv *priv, |
188cf6c7 | 199 | struct iwl_tx_queue *txq, int slots_num, u32 txq_id) |
b481de9c | 200 | { |
188cf6c7 | 201 | int len, i; |
b481de9c ZY |
202 | int rc = 0; |
203 | ||
6440adb5 BC |
204 | /* |
205 | * Alloc buffer array for commands (Tx or other types of commands). | |
206 | * For the command queue (#4), allocate command space + one big | |
207 | * command for scan, since scan command is very huge; the system will | |
208 | * not have two scans at the same time, so only one is needed. | |
209 | * For data Tx queues (all other queues), no super-size command | |
210 | * space is needed. | |
211 | */ | |
188cf6c7 SO |
212 | len = sizeof(struct iwl_cmd); |
213 | for (i = 0; i <= slots_num; i++) { | |
214 | if (i == slots_num) { | |
215 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
216 | len += IWL_MAX_SCAN_SIZE; | |
217 | else | |
218 | continue; | |
219 | } | |
220 | ||
221 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); | |
222 | if (!txq->cmd[i]) | |
223 | goto err; | |
224 | } | |
b481de9c | 225 | |
6440adb5 | 226 | /* Alloc driver data array and TFD circular buffer */ |
bb8c093b | 227 | rc = iwl3945_tx_queue_alloc(priv, txq, txq_id); |
188cf6c7 SO |
228 | if (rc) |
229 | goto err; | |
b481de9c | 230 | |
b481de9c ZY |
231 | txq->need_update = 0; |
232 | ||
233 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
c54b679d | 234 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
b481de9c | 235 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
6440adb5 BC |
236 | |
237 | /* Initialize queue high/low-water, head/tail indexes */ | |
bb8c093b | 238 | iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
b481de9c | 239 | |
6440adb5 | 240 | /* Tell device where to find queue, enable DMA channel. */ |
bb8c093b | 241 | iwl3945_hw_tx_queue_init(priv, txq); |
b481de9c ZY |
242 | |
243 | return 0; | |
188cf6c7 SO |
244 | err: |
245 | for (i = 0; i < slots_num; i++) { | |
246 | kfree(txq->cmd[i]); | |
247 | txq->cmd[i] = NULL; | |
248 | } | |
249 | ||
250 | if (txq_id == IWL_CMD_QUEUE_NUM) { | |
251 | kfree(txq->cmd[slots_num]); | |
252 | txq->cmd[slots_num] = NULL; | |
253 | } | |
254 | return -ENOMEM; | |
b481de9c ZY |
255 | } |
256 | ||
257 | /** | |
bb8c093b | 258 | * iwl3945_tx_queue_free - Deallocate DMA queue. |
b481de9c ZY |
259 | * @txq: Transmit queue to deallocate. |
260 | * | |
261 | * Empty queue by removing and destroying all BD's. | |
6440adb5 BC |
262 | * Free all buffers. |
263 | * 0-fill, but do not free "txq" descriptor structure. | |
b481de9c | 264 | */ |
188cf6c7 | 265 | void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
b481de9c | 266 | { |
d20b3c65 | 267 | struct iwl_queue *q = &txq->q; |
b481de9c | 268 | struct pci_dev *dev = priv->pci_dev; |
188cf6c7 | 269 | int len, i; |
b481de9c ZY |
270 | |
271 | if (q->n_bd == 0) | |
272 | return; | |
273 | ||
274 | /* first, empty all BD's */ | |
fc4b6853 | 275 | for (; q->write_ptr != q->read_ptr; |
c54b679d | 276 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) |
bb8c093b | 277 | iwl3945_hw_txq_free_tfd(priv, txq); |
b481de9c | 278 | |
c2d79b48 | 279 | len = sizeof(struct iwl_cmd) * q->n_window; |
b481de9c ZY |
280 | if (q->id == IWL_CMD_QUEUE_NUM) |
281 | len += IWL_MAX_SCAN_SIZE; | |
282 | ||
6440adb5 | 283 | /* De-alloc array of command/tx buffers */ |
188cf6c7 SO |
284 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
285 | kfree(txq->cmd[i]); | |
b481de9c | 286 | |
6440adb5 | 287 | /* De-alloc circular buffer of TFDs */ |
b481de9c | 288 | if (txq->q.n_bd) |
dbb6654c | 289 | pci_free_consistent(dev, sizeof(struct iwl3945_tfd) * |
188cf6c7 | 290 | txq->q.n_bd, txq->tfds39, txq->q.dma_addr); |
b481de9c | 291 | |
6440adb5 | 292 | /* De-alloc array of per-TFD driver data */ |
3ac7f146 TW |
293 | kfree(txq->txb); |
294 | txq->txb = NULL; | |
b481de9c | 295 | |
6440adb5 | 296 | /* 0-fill queue descriptor structure */ |
b481de9c ZY |
297 | memset(txq, 0, sizeof(*txq)); |
298 | } | |
299 | ||
b481de9c | 300 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 301 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
302 | * the functionality provided here |
303 | */ | |
304 | ||
305 | /**************************************************************/ | |
01ebd063 | 306 | #if 0 /* temporary disable till we add real remove station */ |
6440adb5 BC |
307 | /** |
308 | * iwl3945_remove_station - Remove driver's knowledge of station. | |
309 | * | |
310 | * NOTE: This does not remove station from device's station table. | |
311 | */ | |
4a8a4322 | 312 | static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
313 | { |
314 | int index = IWL_INVALID_STATION; | |
315 | int i; | |
316 | unsigned long flags; | |
317 | ||
318 | spin_lock_irqsave(&priv->sta_lock, flags); | |
319 | ||
320 | if (is_ap) | |
321 | index = IWL_AP_ID; | |
322 | else if (is_broadcast_ether_addr(addr)) | |
3832ec9d | 323 | index = priv->hw_params.bcast_sta_id; |
b481de9c | 324 | else |
3832ec9d | 325 | for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) |
f2c7e521 AK |
326 | if (priv->stations_39[i].used && |
327 | !compare_ether_addr(priv->stations_39[i].sta.sta.addr, | |
b481de9c ZY |
328 | addr)) { |
329 | index = i; | |
330 | break; | |
331 | } | |
332 | ||
333 | if (unlikely(index == IWL_INVALID_STATION)) | |
334 | goto out; | |
335 | ||
f2c7e521 AK |
336 | if (priv->stations_39[index].used) { |
337 | priv->stations_39[index].used = 0; | |
b481de9c ZY |
338 | priv->num_stations--; |
339 | } | |
340 | ||
341 | BUG_ON(priv->num_stations < 0); | |
342 | ||
343 | out: | |
344 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
345 | return 0; | |
346 | } | |
556f8db7 | 347 | #endif |
6440adb5 BC |
348 | |
349 | /** | |
350 | * iwl3945_clear_stations_table - Clear the driver's station table | |
351 | * | |
352 | * NOTE: This does not clear or otherwise alter the device's station table. | |
353 | */ | |
4a8a4322 | 354 | static void iwl3945_clear_stations_table(struct iwl_priv *priv) |
b481de9c ZY |
355 | { |
356 | unsigned long flags; | |
357 | ||
358 | spin_lock_irqsave(&priv->sta_lock, flags); | |
359 | ||
360 | priv->num_stations = 0; | |
f2c7e521 | 361 | memset(priv->stations_39, 0, sizeof(priv->stations_39)); |
b481de9c ZY |
362 | |
363 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
364 | } | |
365 | ||
6440adb5 BC |
366 | /** |
367 | * iwl3945_add_station - Add station to station tables in driver and device | |
368 | */ | |
4a8a4322 | 369 | u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags) |
b481de9c ZY |
370 | { |
371 | int i; | |
372 | int index = IWL_INVALID_STATION; | |
bb8c093b | 373 | struct iwl3945_station_entry *station; |
b481de9c | 374 | unsigned long flags_spin; |
c14c521e | 375 | u8 rate; |
b481de9c ZY |
376 | |
377 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
378 | if (is_ap) | |
379 | index = IWL_AP_ID; | |
380 | else if (is_broadcast_ether_addr(addr)) | |
3832ec9d | 381 | index = priv->hw_params.bcast_sta_id; |
b481de9c | 382 | else |
3832ec9d | 383 | for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) { |
f2c7e521 | 384 | if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr, |
b481de9c ZY |
385 | addr)) { |
386 | index = i; | |
387 | break; | |
388 | } | |
389 | ||
f2c7e521 | 390 | if (!priv->stations_39[i].used && |
b481de9c ZY |
391 | index == IWL_INVALID_STATION) |
392 | index = i; | |
393 | } | |
394 | ||
01ebd063 | 395 | /* These two conditions has the same outcome but keep them separate |
b481de9c ZY |
396 | since they have different meaning */ |
397 | if (unlikely(index == IWL_INVALID_STATION)) { | |
398 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
399 | return index; | |
400 | } | |
401 | ||
f2c7e521 AK |
402 | if (priv->stations_39[index].used && |
403 | !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) { | |
b481de9c ZY |
404 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
405 | return index; | |
406 | } | |
407 | ||
e174961c | 408 | IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr); |
f2c7e521 | 409 | station = &priv->stations_39[index]; |
b481de9c ZY |
410 | station->used = 1; |
411 | priv->num_stations++; | |
412 | ||
6440adb5 | 413 | /* Set up the REPLY_ADD_STA command to send to device */ |
bb8c093b | 414 | memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd)); |
b481de9c ZY |
415 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); |
416 | station->sta.mode = 0; | |
417 | station->sta.sta.sta_id = index; | |
418 | station->sta.station_flags = 0; | |
419 | ||
8318d78a | 420 | if (priv->band == IEEE80211_BAND_5GHZ) |
69946333 TW |
421 | rate = IWL_RATE_6M_PLCP; |
422 | else | |
423 | rate = IWL_RATE_1M_PLCP; | |
c14c521e ZY |
424 | |
425 | /* Turn on both antennas for the station... */ | |
426 | station->sta.rate_n_flags = | |
bb8c093b | 427 | iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK); |
c14c521e | 428 | |
b481de9c | 429 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
6440adb5 BC |
430 | |
431 | /* Add station to device's station table */ | |
bb8c093b | 432 | iwl3945_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
433 | return index; |
434 | ||
435 | } | |
436 | ||
b481de9c ZY |
437 | |
438 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
439 | ||
c3056065 | 440 | #define IWL_CMD(x) case x: return #x |
b481de9c ZY |
441 | #define HOST_COMPLETE_TIMEOUT (HZ / 2) |
442 | ||
443 | /** | |
bb8c093b | 444 | * iwl3945_enqueue_hcmd - enqueue a uCode command |
b481de9c ZY |
445 | * @priv: device private data point |
446 | * @cmd: a point to the ucode command structure | |
447 | * | |
448 | * The function returns < 0 values to indicate the operation is | |
449 | * failed. On success, it turns the index (> 0) of command in the | |
450 | * command queue. | |
451 | */ | |
c2d79b48 | 452 | static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
b481de9c | 453 | { |
188cf6c7 | 454 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
d20b3c65 | 455 | struct iwl_queue *q = &txq->q; |
dbb6654c | 456 | struct iwl3945_tfd *tfd; |
c2d79b48 | 457 | struct iwl_cmd *out_cmd; |
b481de9c ZY |
458 | u32 idx; |
459 | u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
460 | dma_addr_t phys_addr; | |
461 | int pad; | |
188cf6c7 | 462 | int ret, len; |
b481de9c ZY |
463 | unsigned long flags; |
464 | ||
465 | /* If any of the command structures end up being larger than | |
466 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
467 | * we will need to increase the size of the TFD entries */ | |
c2d79b48 | 468 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && |
b481de9c ZY |
469 | !(cmd->meta.flags & CMD_SIZE_HUGE)); |
470 | ||
c342a1b9 | 471 | |
775a6e27 | 472 | if (iwl_is_rfkill(priv)) { |
c342a1b9 GG |
473 | IWL_DEBUG_INFO("Not sending command - RF KILL"); |
474 | return -EIO; | |
475 | } | |
476 | ||
d20b3c65 | 477 | if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { |
15b1687c | 478 | IWL_ERR(priv, "No space for Tx\n"); |
b481de9c ZY |
479 | return -ENOSPC; |
480 | } | |
481 | ||
482 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
483 | ||
188cf6c7 | 484 | tfd = &txq->tfds39[q->write_ptr]; |
b481de9c ZY |
485 | memset(tfd, 0, sizeof(*tfd)); |
486 | ||
fc4b6853 | 487 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
188cf6c7 | 488 | out_cmd = txq->cmd[idx]; |
b481de9c ZY |
489 | |
490 | out_cmd->hdr.cmd = cmd->id; | |
491 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
492 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
493 | ||
494 | /* At this point, the out_cmd now has all of the incoming cmd | |
495 | * information */ | |
496 | ||
497 | out_cmd->hdr.flags = 0; | |
498 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
fc4b6853 | 499 | INDEX_TO_SEQ(q->write_ptr)); |
b481de9c | 500 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
600c0e11 | 501 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
b481de9c | 502 | |
188cf6c7 SO |
503 | len = (idx == TFD_CMD_SLOTS) ? |
504 | IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd); | |
505 | ||
506 | phys_addr = pci_map_single(priv->pci_dev, out_cmd, | |
507 | len, PCI_DMA_TODEVICE); | |
508 | pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr); | |
509 | pci_unmap_len_set(&out_cmd->meta, len, len); | |
510 | phys_addr += offsetof(struct iwl_cmd, hdr); | |
511 | ||
bb8c093b | 512 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); |
b481de9c ZY |
513 | |
514 | pad = U32_PAD(cmd->len); | |
dbb6654c | 515 | tfd->control_flags |= cpu_to_le32(TFD_CTL_PAD_SET(pad)); |
b481de9c ZY |
516 | |
517 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
518 | "%d bytes at %d[%d]:%d\n", | |
519 | get_cmd_string(out_cmd->hdr.cmd), | |
520 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
fc4b6853 | 521 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); |
b481de9c ZY |
522 | |
523 | txq->need_update = 1; | |
6440adb5 BC |
524 | |
525 | /* Increment and update queue's write index */ | |
c54b679d | 526 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
4f3602c8 | 527 | ret = iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
528 | |
529 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
530 | return ret ? ret : idx; | |
531 | } | |
532 | ||
c2d79b48 WT |
533 | static int iwl3945_send_cmd_async(struct iwl_priv *priv, |
534 | struct iwl_host_cmd *cmd) | |
b481de9c ZY |
535 | { |
536 | int ret; | |
537 | ||
538 | BUG_ON(!(cmd->meta.flags & CMD_ASYNC)); | |
539 | ||
540 | /* An asynchronous command can not expect an SKB to be set. */ | |
541 | BUG_ON(cmd->meta.flags & CMD_WANT_SKB); | |
542 | ||
543 | /* An asynchronous command MUST have a callback. */ | |
544 | BUG_ON(!cmd->meta.u.callback); | |
545 | ||
546 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
547 | return -EBUSY; | |
548 | ||
bb8c093b | 549 | ret = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c | 550 | if (ret < 0) { |
15b1687c WT |
551 | IWL_ERR(priv, |
552 | "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", | |
553 | get_cmd_string(cmd->id), ret); | |
b481de9c ZY |
554 | return ret; |
555 | } | |
556 | return 0; | |
557 | } | |
558 | ||
c2d79b48 WT |
559 | static int iwl3945_send_cmd_sync(struct iwl_priv *priv, |
560 | struct iwl_host_cmd *cmd) | |
b481de9c ZY |
561 | { |
562 | int cmd_idx; | |
563 | int ret; | |
b481de9c ZY |
564 | |
565 | BUG_ON(cmd->meta.flags & CMD_ASYNC); | |
566 | ||
567 | /* A synchronous command can not have a callback set. */ | |
568 | BUG_ON(cmd->meta.u.callback != NULL); | |
569 | ||
e5472978 | 570 | if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) { |
15b1687c WT |
571 | IWL_ERR(priv, |
572 | "Error sending %s: Already sending a host command\n", | |
573 | get_cmd_string(cmd->id)); | |
e5472978 TW |
574 | ret = -EBUSY; |
575 | goto out; | |
b481de9c ZY |
576 | } |
577 | ||
578 | set_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
579 | ||
580 | if (cmd->meta.flags & CMD_WANT_SKB) | |
581 | cmd->meta.source = &cmd->meta; | |
582 | ||
bb8c093b | 583 | cmd_idx = iwl3945_enqueue_hcmd(priv, cmd); |
b481de9c ZY |
584 | if (cmd_idx < 0) { |
585 | ret = cmd_idx; | |
15b1687c WT |
586 | IWL_ERR(priv, |
587 | "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n", | |
588 | get_cmd_string(cmd->id), ret); | |
b481de9c ZY |
589 | goto out; |
590 | } | |
591 | ||
592 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
593 | !test_bit(STATUS_HCMD_ACTIVE, &priv->status), | |
594 | HOST_COMPLETE_TIMEOUT); | |
595 | if (!ret) { | |
596 | if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) { | |
15b1687c | 597 | IWL_ERR(priv, "Error sending %s: time out after %dms\n", |
b481de9c ZY |
598 | get_cmd_string(cmd->id), |
599 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
600 | ||
601 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
602 | ret = -ETIMEDOUT; | |
603 | goto cancel; | |
604 | } | |
605 | } | |
606 | ||
607 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
608 | IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n", | |
609 | get_cmd_string(cmd->id)); | |
610 | ret = -ECANCELED; | |
611 | goto fail; | |
612 | } | |
613 | if (test_bit(STATUS_FW_ERROR, &priv->status)) { | |
614 | IWL_DEBUG_INFO("Command %s failed: FW Error\n", | |
615 | get_cmd_string(cmd->id)); | |
616 | ret = -EIO; | |
617 | goto fail; | |
618 | } | |
619 | if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) { | |
15b1687c | 620 | IWL_ERR(priv, "Error: Response NULL in '%s'\n", |
b481de9c ZY |
621 | get_cmd_string(cmd->id)); |
622 | ret = -EIO; | |
73e1a65d | 623 | goto cancel; |
b481de9c ZY |
624 | } |
625 | ||
626 | ret = 0; | |
627 | goto out; | |
628 | ||
629 | cancel: | |
630 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
c2d79b48 | 631 | struct iwl_cmd *qcmd; |
b481de9c ZY |
632 | |
633 | /* Cancel the CMD_WANT_SKB flag for the cmd in the | |
634 | * TX cmd queue. Otherwise in case the cmd comes | |
635 | * in later, it will possibly set an invalid | |
636 | * address (cmd->meta.source). */ | |
188cf6c7 | 637 | qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx]; |
b481de9c ZY |
638 | qcmd->meta.flags &= ~CMD_WANT_SKB; |
639 | } | |
640 | fail: | |
641 | if (cmd->meta.u.skb) { | |
642 | dev_kfree_skb_any(cmd->meta.u.skb); | |
643 | cmd->meta.u.skb = NULL; | |
644 | } | |
645 | out: | |
e5472978 | 646 | clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status); |
b481de9c ZY |
647 | return ret; |
648 | } | |
649 | ||
c2d79b48 | 650 | int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) |
b481de9c | 651 | { |
b481de9c | 652 | if (cmd->meta.flags & CMD_ASYNC) |
bb8c093b | 653 | return iwl3945_send_cmd_async(priv, cmd); |
b481de9c | 654 | |
bb8c093b | 655 | return iwl3945_send_cmd_sync(priv, cmd); |
b481de9c ZY |
656 | } |
657 | ||
4a8a4322 | 658 | int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data) |
b481de9c | 659 | { |
c2d79b48 | 660 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
661 | .id = id, |
662 | .len = len, | |
663 | .data = data, | |
664 | }; | |
665 | ||
bb8c093b | 666 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
667 | } |
668 | ||
4a8a4322 | 669 | static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val) |
b481de9c | 670 | { |
c2d79b48 | 671 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
672 | .id = id, |
673 | .len = sizeof(val), | |
674 | .data = &val, | |
675 | }; | |
676 | ||
bb8c093b | 677 | return iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
678 | } |
679 | ||
4a8a4322 | 680 | int iwl3945_send_statistics_request(struct iwl_priv *priv) |
b481de9c | 681 | { |
bb8c093b | 682 | return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0); |
b481de9c ZY |
683 | } |
684 | ||
b481de9c | 685 | /** |
bb8c093b | 686 | * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON |
8318d78a JB |
687 | * @band: 2.4 or 5 GHz band |
688 | * @channel: Any channel valid for the requested band | |
b481de9c | 689 | |
8318d78a | 690 | * In addition to setting the staging RXON, priv->band is also set. |
b481de9c ZY |
691 | * |
692 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
8318d78a | 693 | * in the staging RXON flag structure based on the band |
b481de9c | 694 | */ |
4a8a4322 | 695 | static int iwl3945_set_rxon_channel(struct iwl_priv *priv, |
8318d78a JB |
696 | enum ieee80211_band band, |
697 | u16 channel) | |
b481de9c | 698 | { |
8318d78a | 699 | if (!iwl3945_get_channel_info(priv, band, channel)) { |
b481de9c | 700 | IWL_DEBUG_INFO("Could not set channel to %d [%d]\n", |
8318d78a | 701 | channel, band); |
b481de9c ZY |
702 | return -EINVAL; |
703 | } | |
704 | ||
f2c7e521 | 705 | if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) && |
8318d78a | 706 | (priv->band == band)) |
b481de9c ZY |
707 | return 0; |
708 | ||
f2c7e521 | 709 | priv->staging39_rxon.channel = cpu_to_le16(channel); |
8318d78a | 710 | if (band == IEEE80211_BAND_5GHZ) |
f2c7e521 | 711 | priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; |
b481de9c | 712 | else |
f2c7e521 | 713 | priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK; |
b481de9c | 714 | |
8318d78a | 715 | priv->band = band; |
b481de9c | 716 | |
8318d78a | 717 | IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band); |
b481de9c ZY |
718 | |
719 | return 0; | |
720 | } | |
721 | ||
722 | /** | |
bb8c093b | 723 | * iwl3945_check_rxon_cmd - validate RXON structure is valid |
b481de9c ZY |
724 | * |
725 | * NOTE: This is really only useful during development and can eventually | |
726 | * be #ifdef'd out once the driver is stable and folks aren't actively | |
727 | * making changes | |
728 | */ | |
4a8a4322 | 729 | static int iwl3945_check_rxon_cmd(struct iwl_priv *priv) |
b481de9c ZY |
730 | { |
731 | int error = 0; | |
732 | int counter = 1; | |
f2c7e521 | 733 | struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon; |
b481de9c ZY |
734 | |
735 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
736 | error |= le32_to_cpu(rxon->flags & | |
737 | (RXON_FLG_TGJ_NARROW_BAND_MSK | | |
738 | RXON_FLG_RADAR_DETECT_MSK)); | |
739 | if (error) | |
39aadf8c | 740 | IWL_WARN(priv, "check 24G fields %d | %d\n", |
b481de9c ZY |
741 | counter++, error); |
742 | } else { | |
743 | error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ? | |
744 | 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK); | |
745 | if (error) | |
39aadf8c | 746 | IWL_WARN(priv, "check 52 fields %d | %d\n", |
b481de9c ZY |
747 | counter++, error); |
748 | error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK); | |
749 | if (error) | |
39aadf8c | 750 | IWL_WARN(priv, "check 52 CCK %d | %d\n", |
b481de9c ZY |
751 | counter++, error); |
752 | } | |
753 | error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1; | |
754 | if (error) | |
39aadf8c | 755 | IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error); |
b481de9c ZY |
756 | |
757 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
758 | error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) && | |
759 | ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0)); | |
760 | if (error) | |
39aadf8c | 761 | IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error); |
b481de9c ZY |
762 | |
763 | error |= (le16_to_cpu(rxon->assoc_id) > 2007); | |
764 | if (error) | |
39aadf8c | 765 | IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error); |
b481de9c ZY |
766 | |
767 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) | |
768 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)); | |
769 | if (error) | |
39aadf8c | 770 | IWL_WARN(priv, "check CCK and short slot %d | %d\n", |
b481de9c ZY |
771 | counter++, error); |
772 | ||
773 | error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) | |
774 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)); | |
775 | if (error) | |
39aadf8c | 776 | IWL_WARN(priv, "check CCK & auto detect %d | %d\n", |
b481de9c ZY |
777 | counter++, error); |
778 | ||
779 | error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | | |
780 | RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK); | |
781 | if (error) | |
39aadf8c | 782 | IWL_WARN(priv, "check TGG and auto detect %d | %d\n", |
b481de9c ZY |
783 | counter++, error); |
784 | ||
785 | if ((rxon->flags & RXON_FLG_DIS_DIV_MSK)) | |
786 | error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK | | |
787 | RXON_FLG_ANT_A_MSK)) == 0); | |
788 | if (error) | |
39aadf8c | 789 | IWL_WARN(priv, "check antenna %d %d\n", counter++, error); |
b481de9c ZY |
790 | |
791 | if (error) | |
39aadf8c | 792 | IWL_WARN(priv, "Tuning to channel %d\n", |
b481de9c ZY |
793 | le16_to_cpu(rxon->channel)); |
794 | ||
795 | if (error) { | |
15b1687c | 796 | IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n"); |
b481de9c ZY |
797 | return -1; |
798 | } | |
799 | return 0; | |
800 | } | |
801 | ||
802 | /** | |
9fbab516 | 803 | * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
01ebd063 | 804 | * @priv: staging_rxon is compared to active_rxon |
b481de9c | 805 | * |
9fbab516 BC |
806 | * If the RXON structure is changing enough to require a new tune, |
807 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
808 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
b481de9c | 809 | */ |
4a8a4322 | 810 | static int iwl3945_full_rxon_required(struct iwl_priv *priv) |
b481de9c ZY |
811 | { |
812 | ||
813 | /* These items are only settable from the full RXON command */ | |
5d1e2325 | 814 | if (!(iwl3945_is_associated(priv)) || |
f2c7e521 AK |
815 | compare_ether_addr(priv->staging39_rxon.bssid_addr, |
816 | priv->active39_rxon.bssid_addr) || | |
817 | compare_ether_addr(priv->staging39_rxon.node_addr, | |
818 | priv->active39_rxon.node_addr) || | |
819 | compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr, | |
820 | priv->active39_rxon.wlap_bssid_addr) || | |
821 | (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) || | |
822 | (priv->staging39_rxon.channel != priv->active39_rxon.channel) || | |
823 | (priv->staging39_rxon.air_propagation != | |
824 | priv->active39_rxon.air_propagation) || | |
825 | (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id)) | |
b481de9c ZY |
826 | return 1; |
827 | ||
828 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
829 | * be updated with the RXON_ASSOC command -- however only some | |
830 | * flag transitions are allowed using RXON_ASSOC */ | |
831 | ||
832 | /* Check if we are not switching bands */ | |
f2c7e521 AK |
833 | if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) != |
834 | (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)) | |
b481de9c ZY |
835 | return 1; |
836 | ||
837 | /* Check if we are switching association toggle */ | |
f2c7e521 AK |
838 | if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) != |
839 | (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) | |
b481de9c ZY |
840 | return 1; |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
4a8a4322 | 845 | static int iwl3945_send_rxon_assoc(struct iwl_priv *priv) |
b481de9c ZY |
846 | { |
847 | int rc = 0; | |
3d24a9f7 | 848 | struct iwl_rx_packet *res = NULL; |
bb8c093b | 849 | struct iwl3945_rxon_assoc_cmd rxon_assoc; |
c2d79b48 | 850 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
851 | .id = REPLY_RXON_ASSOC, |
852 | .len = sizeof(rxon_assoc), | |
853 | .meta.flags = CMD_WANT_SKB, | |
854 | .data = &rxon_assoc, | |
855 | }; | |
f2c7e521 AK |
856 | const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon; |
857 | const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon; | |
b481de9c ZY |
858 | |
859 | if ((rxon1->flags == rxon2->flags) && | |
860 | (rxon1->filter_flags == rxon2->filter_flags) && | |
861 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
862 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
863 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
864 | return 0; | |
865 | } | |
866 | ||
f2c7e521 AK |
867 | rxon_assoc.flags = priv->staging39_rxon.flags; |
868 | rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags; | |
869 | rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates; | |
870 | rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates; | |
b481de9c ZY |
871 | rxon_assoc.reserved = 0; |
872 | ||
bb8c093b | 873 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
874 | if (rc) |
875 | return rc; | |
876 | ||
3d24a9f7 | 877 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c | 878 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
15b1687c | 879 | IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n"); |
b481de9c ZY |
880 | rc = -EIO; |
881 | } | |
882 | ||
883 | priv->alloc_rxb_skb--; | |
884 | dev_kfree_skb_any(cmd.meta.u.skb); | |
885 | ||
886 | return rc; | |
887 | } | |
888 | ||
889 | /** | |
bb8c093b | 890 | * iwl3945_commit_rxon - commit staging_rxon to hardware |
b481de9c | 891 | * |
01ebd063 | 892 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
893 | * the active_rxon structure is updated with the new data. This |
894 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
895 | * a HW tune is required based on the RXON structure changes. | |
896 | */ | |
4a8a4322 | 897 | static int iwl3945_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
898 | { |
899 | /* cast away the const for active_rxon in this function */ | |
f2c7e521 | 900 | struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon; |
b481de9c ZY |
901 | int rc = 0; |
902 | ||
775a6e27 | 903 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
904 | return -1; |
905 | ||
906 | /* always get timestamp with Rx frame */ | |
f2c7e521 | 907 | priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK; |
b481de9c ZY |
908 | |
909 | /* select antenna */ | |
f2c7e521 | 910 | priv->staging39_rxon.flags &= |
b481de9c | 911 | ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK); |
f2c7e521 | 912 | priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv); |
b481de9c | 913 | |
a3139c59 | 914 | rc = iwl3945_check_rxon_cmd(priv); |
b481de9c | 915 | if (rc) { |
15b1687c | 916 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
917 | return -EINVAL; |
918 | } | |
919 | ||
920 | /* If we don't need to send a full RXON, we can use | |
bb8c093b | 921 | * iwl3945_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 922 | * and other flags for the current radio configuration. */ |
bb8c093b CH |
923 | if (!iwl3945_full_rxon_required(priv)) { |
924 | rc = iwl3945_send_rxon_assoc(priv); | |
b481de9c | 925 | if (rc) { |
15b1687c | 926 | IWL_ERR(priv, "Error setting RXON_ASSOC " |
b481de9c ZY |
927 | "configuration (%d).\n", rc); |
928 | return rc; | |
929 | } | |
930 | ||
f2c7e521 | 931 | memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon)); |
b481de9c ZY |
932 | |
933 | return 0; | |
934 | } | |
935 | ||
936 | /* If we are currently associated and the new config requires | |
937 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
938 | * we must clear the associated from the active configuration | |
939 | * before we apply the new config */ | |
bb8c093b | 940 | if (iwl3945_is_associated(priv) && |
f2c7e521 | 941 | (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) { |
b481de9c ZY |
942 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); |
943 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
944 | ||
bb8c093b CH |
945 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
946 | sizeof(struct iwl3945_rxon_cmd), | |
f2c7e521 | 947 | &priv->active39_rxon); |
b481de9c ZY |
948 | |
949 | /* If the mask clearing failed then we set | |
950 | * active_rxon back to what it was previously */ | |
951 | if (rc) { | |
952 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
15b1687c | 953 | IWL_ERR(priv, "Error clearing ASSOC_MSK on current " |
b481de9c ZY |
954 | "configuration (%d).\n", rc); |
955 | return rc; | |
956 | } | |
b481de9c ZY |
957 | } |
958 | ||
959 | IWL_DEBUG_INFO("Sending RXON\n" | |
960 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
961 | "* channel = %d\n" | |
e174961c | 962 | "* bssid = %pM\n", |
f2c7e521 | 963 | ((priv->staging39_rxon.filter_flags & |
b481de9c | 964 | RXON_FILTER_ASSOC_MSK) ? "" : "out"), |
f2c7e521 | 965 | le16_to_cpu(priv->staging39_rxon.channel), |
e174961c | 966 | priv->staging_rxon.bssid_addr); |
b481de9c ZY |
967 | |
968 | /* Apply the new configuration */ | |
bb8c093b | 969 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON, |
f2c7e521 | 970 | sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon); |
b481de9c | 971 | if (rc) { |
15b1687c | 972 | IWL_ERR(priv, "Error setting new configuration (%d).\n", rc); |
b481de9c ZY |
973 | return rc; |
974 | } | |
975 | ||
f2c7e521 | 976 | memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon)); |
b481de9c | 977 | |
bb8c093b | 978 | iwl3945_clear_stations_table(priv); |
556f8db7 | 979 | |
b481de9c ZY |
980 | /* If we issue a new RXON command which required a tune then we must |
981 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
bb8c093b | 982 | rc = iwl3945_hw_reg_send_txpower(priv); |
b481de9c | 983 | if (rc) { |
15b1687c | 984 | IWL_ERR(priv, "Error setting Tx power (%d).\n", rc); |
b481de9c ZY |
985 | return rc; |
986 | } | |
987 | ||
988 | /* Add the broadcast address so we can send broadcast frames */ | |
b5323d36 | 989 | if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) == |
b481de9c | 990 | IWL_INVALID_STATION) { |
15b1687c | 991 | IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n"); |
b481de9c ZY |
992 | return -EIO; |
993 | } | |
994 | ||
995 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
996 | * add the IWL_AP_ID to the station rate table */ | |
bb8c093b | 997 | if (iwl3945_is_associated(priv) && |
05c914fe | 998 | (priv->iw_mode == NL80211_IFTYPE_STATION)) |
f2c7e521 | 999 | if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0) |
b481de9c | 1000 | == IWL_INVALID_STATION) { |
15b1687c | 1001 | IWL_ERR(priv, "Error adding AP address for transmit\n"); |
b481de9c ZY |
1002 | return -EIO; |
1003 | } | |
1004 | ||
8318d78a | 1005 | /* Init the hardware's rate fallback order based on the band */ |
b481de9c ZY |
1006 | rc = iwl3945_init_hw_rate_table(priv); |
1007 | if (rc) { | |
15b1687c | 1008 | IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc); |
b481de9c ZY |
1009 | return -EIO; |
1010 | } | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
4a8a4322 | 1015 | static int iwl3945_send_bt_config(struct iwl_priv *priv) |
b481de9c | 1016 | { |
4c897253 | 1017 | struct iwl_bt_cmd bt_cmd = { |
b481de9c ZY |
1018 | .flags = 3, |
1019 | .lead_time = 0xAA, | |
1020 | .max_kill = 1, | |
1021 | .kill_ack_mask = 0, | |
1022 | .kill_cts_mask = 0, | |
1023 | }; | |
1024 | ||
bb8c093b | 1025 | return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
4c897253 | 1026 | sizeof(bt_cmd), &bt_cmd); |
b481de9c ZY |
1027 | } |
1028 | ||
4a8a4322 | 1029 | static int iwl3945_send_scan_abort(struct iwl_priv *priv) |
b481de9c ZY |
1030 | { |
1031 | int rc = 0; | |
3d24a9f7 | 1032 | struct iwl_rx_packet *res; |
c2d79b48 | 1033 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
1034 | .id = REPLY_SCAN_ABORT_CMD, |
1035 | .meta.flags = CMD_WANT_SKB, | |
1036 | }; | |
1037 | ||
1038 | /* If there isn't a scan actively going on in the hardware | |
1039 | * then we are in between scan bands and not actually | |
1040 | * actively scanning, so don't send the abort command */ | |
1041 | if (!test_bit(STATUS_SCAN_HW, &priv->status)) { | |
1042 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1043 | return 0; | |
1044 | } | |
1045 | ||
bb8c093b | 1046 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
1047 | if (rc) { |
1048 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1049 | return rc; | |
1050 | } | |
1051 | ||
3d24a9f7 | 1052 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c ZY |
1053 | if (res->u.status != CAN_ABORT_STATUS) { |
1054 | /* The scan abort will return 1 for success or | |
1055 | * 2 for "failure". A failure condition can be | |
1056 | * due to simply not being in an active scan which | |
1057 | * can occur if we send the scan abort before we | |
1058 | * the microcode has notified us that a scan is | |
1059 | * completed. */ | |
1060 | IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status); | |
1061 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
1062 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
1063 | } | |
1064 | ||
1065 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1066 | ||
1067 | return rc; | |
1068 | } | |
1069 | ||
4a8a4322 | 1070 | static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv, |
c2d79b48 | 1071 | struct iwl_cmd *cmd, struct sk_buff *skb) |
b481de9c | 1072 | { |
3d24a9f7 | 1073 | struct iwl_rx_packet *res = NULL; |
b481de9c ZY |
1074 | |
1075 | if (!skb) { | |
15b1687c | 1076 | IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n"); |
b481de9c ZY |
1077 | return 1; |
1078 | } | |
1079 | ||
3d24a9f7 | 1080 | res = (struct iwl_rx_packet *)skb->data; |
b481de9c | 1081 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
15b1687c | 1082 | IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n", |
b481de9c ZY |
1083 | res->hdr.flags); |
1084 | return 1; | |
1085 | } | |
1086 | ||
1087 | switch (res->u.add_sta.status) { | |
1088 | case ADD_STA_SUCCESS_MSK: | |
1089 | break; | |
1090 | default: | |
1091 | break; | |
1092 | } | |
1093 | ||
1094 | /* We didn't cache the SKB; let the caller free it */ | |
1095 | return 1; | |
1096 | } | |
1097 | ||
4a8a4322 | 1098 | int iwl3945_send_add_station(struct iwl_priv *priv, |
bb8c093b | 1099 | struct iwl3945_addsta_cmd *sta, u8 flags) |
b481de9c | 1100 | { |
3d24a9f7 | 1101 | struct iwl_rx_packet *res = NULL; |
b481de9c | 1102 | int rc = 0; |
c2d79b48 | 1103 | struct iwl_host_cmd cmd = { |
b481de9c | 1104 | .id = REPLY_ADD_STA, |
bb8c093b | 1105 | .len = sizeof(struct iwl3945_addsta_cmd), |
b481de9c ZY |
1106 | .meta.flags = flags, |
1107 | .data = sta, | |
1108 | }; | |
1109 | ||
1110 | if (flags & CMD_ASYNC) | |
bb8c093b | 1111 | cmd.meta.u.callback = iwl3945_add_sta_sync_callback; |
b481de9c ZY |
1112 | else |
1113 | cmd.meta.flags |= CMD_WANT_SKB; | |
1114 | ||
bb8c093b | 1115 | rc = iwl3945_send_cmd(priv, &cmd); |
b481de9c ZY |
1116 | |
1117 | if (rc || (flags & CMD_ASYNC)) | |
1118 | return rc; | |
1119 | ||
3d24a9f7 | 1120 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c | 1121 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
15b1687c | 1122 | IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n", |
b481de9c ZY |
1123 | res->hdr.flags); |
1124 | rc = -EIO; | |
1125 | } | |
1126 | ||
1127 | if (rc == 0) { | |
1128 | switch (res->u.add_sta.status) { | |
1129 | case ADD_STA_SUCCESS_MSK: | |
1130 | IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n"); | |
1131 | break; | |
1132 | default: | |
1133 | rc = -EIO; | |
39aadf8c | 1134 | IWL_WARN(priv, "REPLY_ADD_STA failed\n"); |
b481de9c ZY |
1135 | break; |
1136 | } | |
1137 | } | |
1138 | ||
1139 | priv->alloc_rxb_skb--; | |
1140 | dev_kfree_skb_any(cmd.meta.u.skb); | |
1141 | ||
1142 | return rc; | |
1143 | } | |
1144 | ||
4a8a4322 | 1145 | static int iwl3945_update_sta_key_info(struct iwl_priv *priv, |
b481de9c ZY |
1146 | struct ieee80211_key_conf *keyconf, |
1147 | u8 sta_id) | |
1148 | { | |
1149 | unsigned long flags; | |
1150 | __le16 key_flags = 0; | |
1151 | ||
1152 | switch (keyconf->alg) { | |
1153 | case ALG_CCMP: | |
1154 | key_flags |= STA_KEY_FLG_CCMP; | |
1155 | key_flags |= cpu_to_le16( | |
1156 | keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
1157 | key_flags &= ~STA_KEY_FLG_INVALID; | |
1158 | break; | |
1159 | case ALG_TKIP: | |
1160 | case ALG_WEP: | |
b481de9c ZY |
1161 | default: |
1162 | return -EINVAL; | |
1163 | } | |
1164 | spin_lock_irqsave(&priv->sta_lock, flags); | |
f2c7e521 AK |
1165 | priv->stations_39[sta_id].keyinfo.alg = keyconf->alg; |
1166 | priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen; | |
1167 | memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key, | |
b481de9c ZY |
1168 | keyconf->keylen); |
1169 | ||
f2c7e521 | 1170 | memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key, |
b481de9c | 1171 | keyconf->keylen); |
f2c7e521 AK |
1172 | priv->stations_39[sta_id].sta.key.key_flags = key_flags; |
1173 | priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1174 | priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
1175 | |
1176 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1177 | ||
1178 | IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n"); | |
f2c7e521 | 1179 | iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0); |
b481de9c ZY |
1180 | return 0; |
1181 | } | |
1182 | ||
4a8a4322 | 1183 | static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
1184 | { |
1185 | unsigned long flags; | |
1186 | ||
1187 | spin_lock_irqsave(&priv->sta_lock, flags); | |
f2c7e521 AK |
1188 | memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key)); |
1189 | memset(&priv->stations_39[sta_id].sta.key, 0, | |
4c897253 | 1190 | sizeof(struct iwl4965_keyinfo)); |
f2c7e521 AK |
1191 | priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
1192 | priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
1193 | priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
1194 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
1195 | ||
1196 | IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n"); | |
f2c7e521 | 1197 | iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0); |
b481de9c ZY |
1198 | return 0; |
1199 | } | |
1200 | ||
4a8a4322 | 1201 | static void iwl3945_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
1202 | { |
1203 | struct list_head *element; | |
1204 | ||
1205 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
1206 | priv->frames_count); | |
1207 | ||
1208 | while (!list_empty(&priv->free_frames)) { | |
1209 | element = priv->free_frames.next; | |
1210 | list_del(element); | |
bb8c093b | 1211 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
1212 | priv->frames_count--; |
1213 | } | |
1214 | ||
1215 | if (priv->frames_count) { | |
39aadf8c | 1216 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
1217 | priv->frames_count); |
1218 | priv->frames_count = 0; | |
1219 | } | |
1220 | } | |
1221 | ||
4a8a4322 | 1222 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv) |
b481de9c | 1223 | { |
bb8c093b | 1224 | struct iwl3945_frame *frame; |
b481de9c ZY |
1225 | struct list_head *element; |
1226 | if (list_empty(&priv->free_frames)) { | |
1227 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
1228 | if (!frame) { | |
15b1687c | 1229 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
1230 | return NULL; |
1231 | } | |
1232 | ||
1233 | priv->frames_count++; | |
1234 | return frame; | |
1235 | } | |
1236 | ||
1237 | element = priv->free_frames.next; | |
1238 | list_del(element); | |
bb8c093b | 1239 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
1240 | } |
1241 | ||
4a8a4322 | 1242 | static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
1243 | { |
1244 | memset(frame, 0, sizeof(*frame)); | |
1245 | list_add(&frame->list, &priv->free_frames); | |
1246 | } | |
1247 | ||
4a8a4322 | 1248 | unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c | 1249 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 1250 | int left) |
b481de9c ZY |
1251 | { |
1252 | ||
bb8c093b | 1253 | if (!iwl3945_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
1254 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
1255 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
1256 | return 0; |
1257 | ||
1258 | if (priv->ibss_beacon->len > left) | |
1259 | return 0; | |
1260 | ||
1261 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
1262 | ||
1263 | return priv->ibss_beacon->len; | |
1264 | } | |
1265 | ||
4a8a4322 | 1266 | static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv) |
b481de9c ZY |
1267 | { |
1268 | u8 i; | |
c24f0817 KA |
1269 | int rate_mask; |
1270 | ||
1271 | /* Set rate mask*/ | |
f2c7e521 | 1272 | if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) |
dbce56a4 | 1273 | rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK; |
c24f0817 | 1274 | else |
dbce56a4 | 1275 | rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK; |
b481de9c ZY |
1276 | |
1277 | for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID; | |
bb8c093b | 1278 | i = iwl3945_rates[i].next_ieee) { |
b481de9c | 1279 | if (rate_mask & (1 << i)) |
bb8c093b | 1280 | return iwl3945_rates[i].plcp; |
b481de9c ZY |
1281 | } |
1282 | ||
c24f0817 | 1283 | /* No valid rate was found. Assign the lowest one */ |
f2c7e521 | 1284 | if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) |
c24f0817 KA |
1285 | return IWL_RATE_1M_PLCP; |
1286 | else | |
1287 | return IWL_RATE_6M_PLCP; | |
b481de9c ZY |
1288 | } |
1289 | ||
4a8a4322 | 1290 | static int iwl3945_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 1291 | { |
bb8c093b | 1292 | struct iwl3945_frame *frame; |
b481de9c ZY |
1293 | unsigned int frame_size; |
1294 | int rc; | |
1295 | u8 rate; | |
1296 | ||
bb8c093b | 1297 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
1298 | |
1299 | if (!frame) { | |
15b1687c | 1300 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
1301 | "command.\n"); |
1302 | return -ENOMEM; | |
1303 | } | |
1304 | ||
c24f0817 | 1305 | rate = iwl3945_rate_get_lowest_plcp(priv); |
b481de9c | 1306 | |
bb8c093b | 1307 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 1308 | |
bb8c093b | 1309 | rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
1310 | &frame->u.cmd[0]); |
1311 | ||
bb8c093b | 1312 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
1313 | |
1314 | return rc; | |
1315 | } | |
1316 | ||
1317 | /****************************************************************************** | |
1318 | * | |
1319 | * EEPROM related functions | |
1320 | * | |
1321 | ******************************************************************************/ | |
1322 | ||
4a8a4322 | 1323 | static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac) |
b481de9c | 1324 | { |
f2c7e521 | 1325 | memcpy(mac, priv->eeprom39.mac_address, 6); |
b481de9c ZY |
1326 | } |
1327 | ||
74a3a250 RC |
1328 | /* |
1329 | * Clear the OWNER_MSK, to establish driver (instead of uCode running on | |
1330 | * embedded controller) as EEPROM reader; each read is a series of pulses | |
1331 | * to/from the EEPROM chip, not a single event, so even reads could conflict | |
1332 | * if they weren't arbitrated by some ownership mechanism. Here, the driver | |
1333 | * simply claims ownership, which should be safe when this function is called | |
1334 | * (i.e. before loading uCode!). | |
1335 | */ | |
4a8a4322 | 1336 | static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv) |
74a3a250 | 1337 | { |
5d49f498 | 1338 | _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); |
74a3a250 RC |
1339 | return 0; |
1340 | } | |
1341 | ||
b481de9c | 1342 | /** |
bb8c093b | 1343 | * iwl3945_eeprom_init - read EEPROM contents |
b481de9c | 1344 | * |
f2c7e521 | 1345 | * Load the EEPROM contents from adapter into priv->eeprom39 |
b481de9c ZY |
1346 | * |
1347 | * NOTE: This routine uses the non-debug IO access functions. | |
1348 | */ | |
4a8a4322 | 1349 | int iwl3945_eeprom_init(struct iwl_priv *priv) |
b481de9c | 1350 | { |
f2c7e521 | 1351 | u16 *e = (u16 *)&priv->eeprom39; |
5d49f498 | 1352 | u32 gp = iwl_read32(priv, CSR_EEPROM_GP); |
f2c7e521 | 1353 | int sz = sizeof(priv->eeprom39); |
3d5717ad | 1354 | int ret; |
b481de9c ZY |
1355 | u16 addr; |
1356 | ||
1357 | /* The EEPROM structure has several padding buffers within it | |
1358 | * and when adding new EEPROM maps is subject to programmer errors | |
1359 | * which may be very difficult to identify without explicitly | |
1360 | * checking the resulting size of the eeprom map. */ | |
f2c7e521 | 1361 | BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE); |
b481de9c ZY |
1362 | |
1363 | if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { | |
15b1687c | 1364 | IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp); |
b481de9c ZY |
1365 | return -ENOENT; |
1366 | } | |
1367 | ||
6440adb5 | 1368 | /* Make sure driver (instead of uCode) is allowed to read EEPROM */ |
3d5717ad ZY |
1369 | ret = iwl3945_eeprom_acquire_semaphore(priv); |
1370 | if (ret < 0) { | |
15b1687c | 1371 | IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n"); |
b481de9c ZY |
1372 | return -ENOENT; |
1373 | } | |
1374 | ||
1375 | /* eeprom is an array of 16bit values */ | |
1376 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | |
3d5717ad | 1377 | u32 r; |
b481de9c | 1378 | |
5d49f498 | 1379 | _iwl_write32(priv, CSR_EEPROM_REG, |
3d5717ad | 1380 | CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); |
5d49f498 AK |
1381 | _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD); |
1382 | ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG, | |
3d5717ad ZY |
1383 | CSR_EEPROM_REG_READ_VALID_MSK, |
1384 | IWL_EEPROM_ACCESS_TIMEOUT); | |
1385 | if (ret < 0) { | |
15b1687c | 1386 | IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr); |
3d5717ad | 1387 | return ret; |
b481de9c | 1388 | } |
3d5717ad | 1389 | |
5d49f498 | 1390 | r = _iwl_read_direct32(priv, CSR_EEPROM_REG); |
58ff6d4d | 1391 | e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); |
b481de9c ZY |
1392 | } |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
4a8a4322 | 1397 | static void iwl3945_unset_hw_params(struct iwl_priv *priv) |
b481de9c | 1398 | { |
3832ec9d | 1399 | if (priv->shared_virt) |
b481de9c | 1400 | pci_free_consistent(priv->pci_dev, |
bb8c093b | 1401 | sizeof(struct iwl3945_shared), |
3832ec9d AK |
1402 | priv->shared_virt, |
1403 | priv->shared_phys); | |
b481de9c ZY |
1404 | } |
1405 | ||
1406 | /** | |
bb8c093b | 1407 | * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field |
b481de9c ZY |
1408 | * |
1409 | * return : set the bit for each supported rate insert in ie | |
1410 | */ | |
bb8c093b | 1411 | static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate, |
c7c46676 | 1412 | u16 basic_rate, int *left) |
b481de9c ZY |
1413 | { |
1414 | u16 ret_rates = 0, bit; | |
1415 | int i; | |
c7c46676 TW |
1416 | u8 *cnt = ie; |
1417 | u8 *rates = ie + 1; | |
b481de9c ZY |
1418 | |
1419 | for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) { | |
1420 | if (bit & supported_rate) { | |
1421 | ret_rates |= bit; | |
bb8c093b | 1422 | rates[*cnt] = iwl3945_rates[i].ieee | |
c7c46676 TW |
1423 | ((bit & basic_rate) ? 0x80 : 0x00); |
1424 | (*cnt)++; | |
1425 | (*left)--; | |
1426 | if ((*left <= 0) || | |
1427 | (*cnt >= IWL_SUPPORTED_RATES_IE_LEN)) | |
b481de9c ZY |
1428 | break; |
1429 | } | |
1430 | } | |
1431 | ||
1432 | return ret_rates; | |
1433 | } | |
1434 | ||
1435 | /** | |
bb8c093b | 1436 | * iwl3945_fill_probe_req - fill in all required fields and IE for probe request |
b481de9c | 1437 | */ |
4a8a4322 | 1438 | static u16 iwl3945_fill_probe_req(struct iwl_priv *priv, |
b481de9c | 1439 | struct ieee80211_mgmt *frame, |
430cfe95 | 1440 | int left) |
b481de9c ZY |
1441 | { |
1442 | int len = 0; | |
1443 | u8 *pos = NULL; | |
c7c46676 | 1444 | u16 active_rates, ret_rates, cck_rates; |
b481de9c ZY |
1445 | |
1446 | /* Make sure there is enough space for the probe request, | |
1447 | * two mandatory IEs and the data */ | |
1448 | left -= 24; | |
1449 | if (left < 0) | |
1450 | return 0; | |
1451 | len += 24; | |
1452 | ||
1453 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
b5323d36 | 1454 | memcpy(frame->da, iwl_bcast_addr, ETH_ALEN); |
b481de9c | 1455 | memcpy(frame->sa, priv->mac_addr, ETH_ALEN); |
b5323d36 | 1456 | memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN); |
b481de9c ZY |
1457 | frame->seq_ctrl = 0; |
1458 | ||
1459 | /* fill in our indirect SSID IE */ | |
1460 | /* ...next IE... */ | |
1461 | ||
1462 | left -= 2; | |
1463 | if (left < 0) | |
1464 | return 0; | |
1465 | len += 2; | |
1466 | pos = &(frame->u.probe_req.variable[0]); | |
1467 | *pos++ = WLAN_EID_SSID; | |
1468 | *pos++ = 0; | |
1469 | ||
b481de9c ZY |
1470 | /* fill in supported rate */ |
1471 | /* ...next IE... */ | |
1472 | left -= 2; | |
1473 | if (left < 0) | |
1474 | return 0; | |
c7c46676 | 1475 | |
b481de9c ZY |
1476 | /* ... fill it in... */ |
1477 | *pos++ = WLAN_EID_SUPP_RATES; | |
1478 | *pos = 0; | |
c7c46676 TW |
1479 | |
1480 | priv->active_rate = priv->rates_mask; | |
1481 | active_rates = priv->active_rate; | |
b481de9c ZY |
1482 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; |
1483 | ||
c7c46676 | 1484 | cck_rates = IWL_CCK_RATES_MASK & active_rates; |
bb8c093b | 1485 | ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates, |
c7c46676 TW |
1486 | priv->active_rate_basic, &left); |
1487 | active_rates &= ~ret_rates; | |
1488 | ||
bb8c093b | 1489 | ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 TW |
1490 | priv->active_rate_basic, &left); |
1491 | active_rates &= ~ret_rates; | |
1492 | ||
b481de9c ZY |
1493 | len += 2 + *pos; |
1494 | pos += (*pos) + 1; | |
c7c46676 | 1495 | if (active_rates == 0) |
b481de9c ZY |
1496 | goto fill_end; |
1497 | ||
1498 | /* fill in supported extended rate */ | |
1499 | /* ...next IE... */ | |
1500 | left -= 2; | |
1501 | if (left < 0) | |
1502 | return 0; | |
1503 | /* ... fill it in... */ | |
1504 | *pos++ = WLAN_EID_EXT_SUPP_RATES; | |
1505 | *pos = 0; | |
bb8c093b | 1506 | iwl3945_supported_rate_to_ie(pos, active_rates, |
c7c46676 | 1507 | priv->active_rate_basic, &left); |
b481de9c ZY |
1508 | if (*pos > 0) |
1509 | len += 2 + *pos; | |
1510 | ||
1511 | fill_end: | |
1512 | return (u16)len; | |
1513 | } | |
1514 | ||
1515 | /* | |
1516 | * QoS support | |
1517 | */ | |
4a8a4322 | 1518 | static int iwl3945_send_qos_params_command(struct iwl_priv *priv, |
4c897253 | 1519 | struct iwl_qosparam_cmd *qos) |
b481de9c ZY |
1520 | { |
1521 | ||
bb8c093b | 1522 | return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM, |
4c897253 | 1523 | sizeof(struct iwl_qosparam_cmd), qos); |
b481de9c ZY |
1524 | } |
1525 | ||
4a8a4322 | 1526 | static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force) |
b481de9c ZY |
1527 | { |
1528 | unsigned long flags; | |
1529 | ||
b481de9c ZY |
1530 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
1531 | return; | |
1532 | ||
b481de9c ZY |
1533 | spin_lock_irqsave(&priv->lock, flags); |
1534 | priv->qos_data.def_qos_parm.qos_flags = 0; | |
1535 | ||
1536 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
1537 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
1538 | priv->qos_data.def_qos_parm.qos_flags |= | |
1539 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
1540 | ||
1541 | if (priv->qos_data.qos_active) | |
1542 | priv->qos_data.def_qos_parm.qos_flags |= | |
1543 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
1544 | ||
1545 | spin_unlock_irqrestore(&priv->lock, flags); | |
1546 | ||
bb8c093b | 1547 | if (force || iwl3945_is_associated(priv)) { |
a96a27f9 | 1548 | IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n", |
b481de9c ZY |
1549 | priv->qos_data.qos_active); |
1550 | ||
bb8c093b | 1551 | iwl3945_send_qos_params_command(priv, |
b481de9c ZY |
1552 | &(priv->qos_data.def_qos_parm)); |
1553 | } | |
1554 | } | |
1555 | ||
b481de9c ZY |
1556 | /* |
1557 | * Power management (not Tx power!) functions | |
1558 | */ | |
1559 | #define MSEC_TO_USEC 1024 | |
1560 | ||
600c0e11 TW |
1561 | |
1562 | #define NOSLP __constant_cpu_to_le16(0), 0, 0 | |
1563 | #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0 | |
b481de9c ZY |
1564 | #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC) |
1565 | #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \ | |
1566 | __constant_cpu_to_le32(X1), \ | |
1567 | __constant_cpu_to_le32(X2), \ | |
1568 | __constant_cpu_to_le32(X3), \ | |
1569 | __constant_cpu_to_le32(X4)} | |
1570 | ||
b481de9c | 1571 | /* default power management (not Tx power) table values */ |
a96a27f9 | 1572 | /* for TIM 0-10 */ |
1125eff3 | 1573 | static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = { |
b481de9c ZY |
1574 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1575 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | |
1576 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0}, | |
1577 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0}, | |
1578 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1}, | |
1579 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1} | |
1580 | }; | |
1581 | ||
a96a27f9 | 1582 | /* for TIM > 10 */ |
1125eff3 | 1583 | static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = { |
b481de9c ZY |
1584 | {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
1585 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), | |
1586 | SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | |
1587 | {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), | |
1588 | SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | |
1589 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), | |
1590 | SLP_VEC(2, 6, 9, 9, 0xFF)}, 0}, | |
1591 | {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0}, | |
1592 | {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), | |
1593 | SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | |
1594 | }; | |
1595 | ||
4a8a4322 | 1596 | int iwl3945_power_init_handle(struct iwl_priv *priv) |
b481de9c ZY |
1597 | { |
1598 | int rc = 0, i; | |
bb8c093b | 1599 | struct iwl3945_power_mgr *pow_data; |
1125eff3 | 1600 | int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC; |
b481de9c ZY |
1601 | u16 pci_pm; |
1602 | ||
1603 | IWL_DEBUG_POWER("Initialize power \n"); | |
1604 | ||
f2c7e521 | 1605 | pow_data = &(priv->power_data_39); |
b481de9c ZY |
1606 | |
1607 | memset(pow_data, 0, sizeof(*pow_data)); | |
1608 | ||
1609 | pow_data->active_index = IWL_POWER_RANGE_0; | |
1610 | pow_data->dtim_val = 0xffff; | |
1611 | ||
1612 | memcpy(&pow_data->pwr_range_0[0], &range_0[0], size); | |
1613 | memcpy(&pow_data->pwr_range_1[0], &range_1[0], size); | |
1614 | ||
1615 | rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm); | |
1616 | if (rc != 0) | |
1617 | return 0; | |
1618 | else { | |
600c0e11 | 1619 | struct iwl_powertable_cmd *cmd; |
b481de9c ZY |
1620 | |
1621 | IWL_DEBUG_POWER("adjust power command flags\n"); | |
1622 | ||
1125eff3 | 1623 | for (i = 0; i < IWL39_POWER_AC; i++) { |
b481de9c ZY |
1624 | cmd = &pow_data->pwr_range_0[i].cmd; |
1625 | ||
1626 | if (pci_pm & 0x1) | |
1627 | cmd->flags &= ~IWL_POWER_PCI_PM_MSK; | |
1628 | else | |
1629 | cmd->flags |= IWL_POWER_PCI_PM_MSK; | |
1630 | } | |
1631 | } | |
1632 | return rc; | |
1633 | } | |
1634 | ||
4a8a4322 | 1635 | static int iwl3945_update_power_cmd(struct iwl_priv *priv, |
600c0e11 | 1636 | struct iwl_powertable_cmd *cmd, u32 mode) |
b481de9c ZY |
1637 | { |
1638 | int rc = 0, i; | |
1639 | u8 skip; | |
1640 | u32 max_sleep = 0; | |
1125eff3 | 1641 | struct iwl_power_vec_entry *range; |
b481de9c | 1642 | u8 period = 0; |
bb8c093b | 1643 | struct iwl3945_power_mgr *pow_data; |
b481de9c ZY |
1644 | |
1645 | if (mode > IWL_POWER_INDEX_5) { | |
1646 | IWL_DEBUG_POWER("Error invalid power mode \n"); | |
1647 | return -1; | |
1648 | } | |
f2c7e521 | 1649 | pow_data = &(priv->power_data_39); |
b481de9c ZY |
1650 | |
1651 | if (pow_data->active_index == IWL_POWER_RANGE_0) | |
1652 | range = &pow_data->pwr_range_0[0]; | |
1653 | else | |
1654 | range = &pow_data->pwr_range_1[1]; | |
1655 | ||
bb8c093b | 1656 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd)); |
b481de9c ZY |
1657 | |
1658 | #ifdef IWL_MAC80211_DISABLE | |
1659 | if (priv->assoc_network != NULL) { | |
1660 | unsigned long flags; | |
1661 | ||
1662 | period = priv->assoc_network->tim.tim_period; | |
1663 | } | |
1664 | #endif /*IWL_MAC80211_DISABLE */ | |
1665 | skip = range[mode].no_dtim; | |
1666 | ||
1667 | if (period == 0) { | |
1668 | period = 1; | |
1669 | skip = 0; | |
1670 | } | |
1671 | ||
1672 | if (skip == 0) { | |
1673 | max_sleep = period; | |
1674 | cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1675 | } else { | |
1676 | __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]; | |
1677 | max_sleep = (le32_to_cpu(slp_itrvl) / period) * period; | |
1678 | cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK; | |
1679 | } | |
1680 | ||
1681 | for (i = 0; i < IWL_POWER_VEC_SIZE; i++) { | |
1682 | if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep) | |
1683 | cmd->sleep_interval[i] = cpu_to_le32(max_sleep); | |
1684 | } | |
1685 | ||
1686 | IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags); | |
1687 | IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); | |
1688 | IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
1689 | IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
1690 | le32_to_cpu(cmd->sleep_interval[0]), | |
1691 | le32_to_cpu(cmd->sleep_interval[1]), | |
1692 | le32_to_cpu(cmd->sleep_interval[2]), | |
1693 | le32_to_cpu(cmd->sleep_interval[3]), | |
1694 | le32_to_cpu(cmd->sleep_interval[4])); | |
1695 | ||
1696 | return rc; | |
1697 | } | |
1698 | ||
4a8a4322 | 1699 | static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode) |
b481de9c | 1700 | { |
9a62f73b | 1701 | u32 uninitialized_var(final_mode); |
b481de9c | 1702 | int rc; |
600c0e11 | 1703 | struct iwl_powertable_cmd cmd; |
b481de9c ZY |
1704 | |
1705 | /* If on battery, set to 3, | |
01ebd063 | 1706 | * if plugged into AC power, set to CAM ("continuously aware mode"), |
b481de9c ZY |
1707 | * else user level */ |
1708 | switch (mode) { | |
1125eff3 | 1709 | case IWL39_POWER_BATTERY: |
b481de9c ZY |
1710 | final_mode = IWL_POWER_INDEX_3; |
1711 | break; | |
1125eff3 | 1712 | case IWL39_POWER_AC: |
b481de9c ZY |
1713 | final_mode = IWL_POWER_MODE_CAM; |
1714 | break; | |
1715 | default: | |
1716 | final_mode = mode; | |
1717 | break; | |
1718 | } | |
1719 | ||
bb8c093b | 1720 | iwl3945_update_power_cmd(priv, &cmd, final_mode); |
b481de9c | 1721 | |
600c0e11 TW |
1722 | /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */ |
1723 | rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, | |
1724 | sizeof(struct iwl3945_powertable_cmd), &cmd); | |
b481de9c ZY |
1725 | |
1726 | if (final_mode == IWL_POWER_MODE_CAM) | |
1727 | clear_bit(STATUS_POWER_PMI, &priv->status); | |
1728 | else | |
1729 | set_bit(STATUS_POWER_PMI, &priv->status); | |
1730 | ||
1731 | return rc; | |
1732 | } | |
1733 | ||
b481de9c ZY |
1734 | #define MAX_UCODE_BEACON_INTERVAL 1024 |
1735 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | |
1736 | ||
bb8c093b | 1737 | static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
1738 | { |
1739 | u16 new_val = 0; | |
1740 | u16 beacon_factor = 0; | |
1741 | ||
1742 | beacon_factor = | |
1743 | (beacon_val + MAX_UCODE_BEACON_INTERVAL) | |
1744 | / MAX_UCODE_BEACON_INTERVAL; | |
1745 | new_val = beacon_val / beacon_factor; | |
1746 | ||
1747 | return cpu_to_le16(new_val); | |
1748 | } | |
1749 | ||
4a8a4322 | 1750 | static void iwl3945_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c ZY |
1751 | { |
1752 | u64 interval_tm_unit; | |
1753 | u64 tsf, result; | |
1754 | unsigned long flags; | |
1755 | struct ieee80211_conf *conf = NULL; | |
1756 | u16 beacon_int = 0; | |
1757 | ||
1758 | conf = ieee80211_get_hw_conf(priv->hw); | |
1759 | ||
1760 | spin_lock_irqsave(&priv->lock, flags); | |
28afaf91 | 1761 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); |
b481de9c ZY |
1762 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; |
1763 | ||
28afaf91 | 1764 | tsf = priv->timestamp; |
b481de9c ZY |
1765 | |
1766 | beacon_int = priv->beacon_int; | |
1767 | spin_unlock_irqrestore(&priv->lock, flags); | |
1768 | ||
05c914fe | 1769 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
b481de9c ZY |
1770 | if (beacon_int == 0) { |
1771 | priv->rxon_timing.beacon_interval = cpu_to_le16(100); | |
1772 | priv->rxon_timing.beacon_init_val = cpu_to_le32(102400); | |
1773 | } else { | |
1774 | priv->rxon_timing.beacon_interval = | |
1775 | cpu_to_le16(beacon_int); | |
1776 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1777 | iwl3945_adjust_beacon_interval( |
b481de9c ZY |
1778 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
1779 | } | |
1780 | ||
1781 | priv->rxon_timing.atim_window = 0; | |
1782 | } else { | |
1783 | priv->rxon_timing.beacon_interval = | |
bb8c093b | 1784 | iwl3945_adjust_beacon_interval(conf->beacon_int); |
b481de9c ZY |
1785 | /* TODO: we need to get atim_window from upper stack |
1786 | * for now we set to 0 */ | |
1787 | priv->rxon_timing.atim_window = 0; | |
1788 | } | |
1789 | ||
1790 | interval_tm_unit = | |
1791 | (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024); | |
1792 | result = do_div(tsf, interval_tm_unit); | |
1793 | priv->rxon_timing.beacon_init_val = | |
1794 | cpu_to_le32((u32) ((u64) interval_tm_unit - result)); | |
1795 | ||
1796 | IWL_DEBUG_ASSOC | |
1797 | ("beacon interval %d beacon timer %d beacon tim %d\n", | |
1798 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
1799 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
1800 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
1801 | } | |
1802 | ||
4a8a4322 | 1803 | static int iwl3945_scan_initiate(struct iwl_priv *priv) |
b481de9c | 1804 | { |
775a6e27 | 1805 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
1806 | IWL_DEBUG_SCAN("Aborting scan due to not ready.\n"); |
1807 | return -EIO; | |
1808 | } | |
1809 | ||
1810 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1811 | IWL_DEBUG_SCAN("Scan already in progress.\n"); | |
1812 | return -EAGAIN; | |
1813 | } | |
1814 | ||
1815 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
1816 | IWL_DEBUG_SCAN("Scan request while abort pending. " | |
1817 | "Queuing.\n"); | |
1818 | return -EAGAIN; | |
1819 | } | |
1820 | ||
1821 | IWL_DEBUG_INFO("Starting scan...\n"); | |
66b5004d RR |
1822 | if (priv->cfg->sku & IWL_SKU_G) |
1823 | priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ); | |
1824 | if (priv->cfg->sku & IWL_SKU_A) | |
1825 | priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ); | |
b481de9c ZY |
1826 | set_bit(STATUS_SCANNING, &priv->status); |
1827 | priv->scan_start = jiffies; | |
1828 | priv->scan_pass_start = priv->scan_start; | |
1829 | ||
1830 | queue_work(priv->workqueue, &priv->request_scan); | |
1831 | ||
1832 | return 0; | |
1833 | } | |
1834 | ||
4a8a4322 | 1835 | static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt) |
b481de9c | 1836 | { |
f2c7e521 | 1837 | struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon; |
b481de9c ZY |
1838 | |
1839 | if (hw_decrypt) | |
1840 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
1841 | else | |
1842 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
1843 | ||
1844 | return 0; | |
1845 | } | |
1846 | ||
4a8a4322 | 1847 | static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv, |
8318d78a | 1848 | enum ieee80211_band band) |
b481de9c | 1849 | { |
8318d78a | 1850 | if (band == IEEE80211_BAND_5GHZ) { |
f2c7e521 | 1851 | priv->staging39_rxon.flags &= |
b481de9c ZY |
1852 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
1853 | | RXON_FLG_CCK_MSK); | |
f2c7e521 | 1854 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 1855 | } else { |
bb8c093b | 1856 | /* Copied from iwl3945_bg_post_associate() */ |
b481de9c | 1857 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
f2c7e521 | 1858 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 1859 | else |
f2c7e521 | 1860 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 1861 | |
05c914fe | 1862 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
f2c7e521 | 1863 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 1864 | |
f2c7e521 AK |
1865 | priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK; |
1866 | priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
1867 | priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK; | |
b481de9c ZY |
1868 | } |
1869 | } | |
1870 | ||
1871 | /* | |
01ebd063 | 1872 | * initialize rxon structure with default values from eeprom |
b481de9c | 1873 | */ |
4a8a4322 | 1874 | static void iwl3945_connection_init_rx_config(struct iwl_priv *priv, |
60294de3 | 1875 | int mode) |
b481de9c | 1876 | { |
d20b3c65 | 1877 | const struct iwl_channel_info *ch_info; |
b481de9c | 1878 | |
f2c7e521 | 1879 | memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon)); |
b481de9c | 1880 | |
60294de3 | 1881 | switch (mode) { |
05c914fe | 1882 | case NL80211_IFTYPE_AP: |
f2c7e521 | 1883 | priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP; |
b481de9c ZY |
1884 | break; |
1885 | ||
05c914fe | 1886 | case NL80211_IFTYPE_STATION: |
f2c7e521 AK |
1887 | priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS; |
1888 | priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
b481de9c ZY |
1889 | break; |
1890 | ||
05c914fe | 1891 | case NL80211_IFTYPE_ADHOC: |
f2c7e521 AK |
1892 | priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS; |
1893 | priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
1894 | priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
b481de9c ZY |
1895 | RXON_FILTER_ACCEPT_GRP_MSK; |
1896 | break; | |
1897 | ||
05c914fe | 1898 | case NL80211_IFTYPE_MONITOR: |
f2c7e521 AK |
1899 | priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER; |
1900 | priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK | | |
b481de9c ZY |
1901 | RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK; |
1902 | break; | |
69dc5d9d | 1903 | default: |
15b1687c | 1904 | IWL_ERR(priv, "Unsupported interface type %d\n", mode); |
69dc5d9d | 1905 | break; |
b481de9c ZY |
1906 | } |
1907 | ||
1908 | #if 0 | |
1909 | /* TODO: Figure out when short_preamble would be set and cache from | |
1910 | * that */ | |
1911 | if (!hw_to_local(priv->hw)->short_preamble) | |
f2c7e521 | 1912 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 1913 | else |
f2c7e521 | 1914 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c ZY |
1915 | #endif |
1916 | ||
8318d78a | 1917 | ch_info = iwl3945_get_channel_info(priv, priv->band, |
f2c7e521 | 1918 | le16_to_cpu(priv->active39_rxon.channel)); |
b481de9c ZY |
1919 | |
1920 | if (!ch_info) | |
1921 | ch_info = &priv->channel_info[0]; | |
1922 | ||
1923 | /* | |
1924 | * in some case A channels are all non IBSS | |
1925 | * in this case force B/G channel | |
1926 | */ | |
60294de3 | 1927 | if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info))) |
b481de9c ZY |
1928 | ch_info = &priv->channel_info[0]; |
1929 | ||
f2c7e521 | 1930 | priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel); |
b481de9c | 1931 | if (is_channel_a_band(ch_info)) |
8318d78a | 1932 | priv->band = IEEE80211_BAND_5GHZ; |
b481de9c | 1933 | else |
8318d78a | 1934 | priv->band = IEEE80211_BAND_2GHZ; |
b481de9c | 1935 | |
8318d78a | 1936 | iwl3945_set_flags_for_phymode(priv, priv->band); |
b481de9c | 1937 | |
f2c7e521 | 1938 | priv->staging39_rxon.ofdm_basic_rates = |
b481de9c | 1939 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
f2c7e521 | 1940 | priv->staging39_rxon.cck_basic_rates = |
b481de9c ZY |
1941 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
1942 | } | |
1943 | ||
4a8a4322 | 1944 | static int iwl3945_set_mode(struct iwl_priv *priv, int mode) |
b481de9c | 1945 | { |
05c914fe | 1946 | if (mode == NL80211_IFTYPE_ADHOC) { |
d20b3c65 | 1947 | const struct iwl_channel_info *ch_info; |
b481de9c | 1948 | |
bb8c093b | 1949 | ch_info = iwl3945_get_channel_info(priv, |
8318d78a | 1950 | priv->band, |
f2c7e521 | 1951 | le16_to_cpu(priv->staging39_rxon.channel)); |
b481de9c ZY |
1952 | |
1953 | if (!ch_info || !is_channel_ibss(ch_info)) { | |
15b1687c | 1954 | IWL_ERR(priv, "channel %d not IBSS channel\n", |
f2c7e521 | 1955 | le16_to_cpu(priv->staging39_rxon.channel)); |
b481de9c ZY |
1956 | return -EINVAL; |
1957 | } | |
1958 | } | |
1959 | ||
60294de3 | 1960 | iwl3945_connection_init_rx_config(priv, mode); |
f2c7e521 | 1961 | memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
b481de9c | 1962 | |
bb8c093b | 1963 | iwl3945_clear_stations_table(priv); |
b481de9c | 1964 | |
a96a27f9 | 1965 | /* don't commit rxon if rf-kill is on*/ |
775a6e27 | 1966 | if (!iwl_is_ready_rf(priv)) |
fde3571f MA |
1967 | return -EAGAIN; |
1968 | ||
1969 | cancel_delayed_work(&priv->scan_check); | |
af0053d6 | 1970 | if (iwl_scan_cancel_timeout(priv, 100)) { |
39aadf8c | 1971 | IWL_WARN(priv, "Aborted scan still in progress after 100ms\n"); |
fde3571f MA |
1972 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); |
1973 | return -EAGAIN; | |
1974 | } | |
1975 | ||
bb8c093b | 1976 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
1977 | |
1978 | return 0; | |
1979 | } | |
1980 | ||
4a8a4322 | 1981 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
e039fa4a | 1982 | struct ieee80211_tx_info *info, |
c2d79b48 | 1983 | struct iwl_cmd *cmd, |
b481de9c ZY |
1984 | struct sk_buff *skb_frag, |
1985 | int last_frag) | |
1986 | { | |
e52119c5 | 1987 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
1c014420 | 1988 | struct iwl3945_hw_key *keyinfo = |
f2c7e521 | 1989 | &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo; |
b481de9c ZY |
1990 | |
1991 | switch (keyinfo->alg) { | |
1992 | case ALG_CCMP: | |
e52119c5 WT |
1993 | tx->sec_ctl = TX_CMD_SEC_CCM; |
1994 | memcpy(tx->key, keyinfo->key, keyinfo->keylen); | |
a96a27f9 | 1995 | IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n"); |
b481de9c ZY |
1996 | break; |
1997 | ||
1998 | case ALG_TKIP: | |
1999 | #if 0 | |
e52119c5 | 2000 | tx->sec_ctl = TX_CMD_SEC_TKIP; |
b481de9c ZY |
2001 | |
2002 | if (last_frag) | |
e52119c5 | 2003 | memcpy(tx->tkip_mic.byte, skb_frag->tail - 8, |
b481de9c ZY |
2004 | 8); |
2005 | else | |
e52119c5 | 2006 | memset(tx->tkip_mic.byte, 0, 8); |
b481de9c ZY |
2007 | #endif |
2008 | break; | |
2009 | ||
2010 | case ALG_WEP: | |
e52119c5 | 2011 | tx->sec_ctl = TX_CMD_SEC_WEP | |
e039fa4a | 2012 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c ZY |
2013 | |
2014 | if (keyinfo->keylen == 13) | |
e52119c5 | 2015 | tx->sec_ctl |= TX_CMD_SEC_KEY128; |
b481de9c | 2016 | |
e52119c5 | 2017 | memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen); |
b481de9c ZY |
2018 | |
2019 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
e039fa4a | 2020 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
2021 | break; |
2022 | ||
b481de9c | 2023 | default: |
978785a3 | 2024 | IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg); |
b481de9c ZY |
2025 | break; |
2026 | } | |
2027 | } | |
2028 | ||
2029 | /* | |
2030 | * handle build REPLY_TX command notification. | |
2031 | */ | |
4a8a4322 | 2032 | static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv, |
c2d79b48 | 2033 | struct iwl_cmd *cmd, |
e039fa4a | 2034 | struct ieee80211_tx_info *info, |
e52119c5 | 2035 | struct ieee80211_hdr *hdr, u8 std_id) |
b481de9c | 2036 | { |
e52119c5 WT |
2037 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
2038 | __le32 tx_flags = tx->tx_flags; | |
fd7c8a40 | 2039 | __le16 fc = hdr->frame_control; |
e6a9854b | 2040 | u8 rc_flags = info->control.rates[0].flags; |
b481de9c | 2041 | |
e52119c5 | 2042 | tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
e039fa4a | 2043 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 2044 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 2045 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 2046 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 2047 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
2048 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
2049 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
2050 | } else { | |
2051 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
2052 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
2053 | } | |
2054 | ||
e52119c5 | 2055 | tx->sta_id = std_id; |
8b7b1e05 | 2056 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
2057 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
2058 | ||
fd7c8a40 HH |
2059 | if (ieee80211_is_data_qos(fc)) { |
2060 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
e52119c5 | 2061 | tx->tid_tspec = qc[0] & 0xf; |
b481de9c | 2062 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 2063 | } else { |
b481de9c | 2064 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 2065 | } |
b481de9c | 2066 | |
e6a9854b | 2067 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { |
b481de9c ZY |
2068 | tx_flags |= TX_CMD_FLG_RTS_MSK; |
2069 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
e6a9854b | 2070 | } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
b481de9c ZY |
2071 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
2072 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
2073 | } | |
2074 | ||
2075 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
2076 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
2077 | ||
2078 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
2079 | if (ieee80211_is_mgmt(fc)) { |
2080 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
e52119c5 | 2081 | tx->timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 2082 | else |
e52119c5 | 2083 | tx->timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 2084 | } else { |
e52119c5 | 2085 | tx->timeout.pm_frame_timeout = 0; |
ab53d8af MA |
2086 | #ifdef CONFIG_IWL3945_LEDS |
2087 | priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len); | |
2088 | #endif | |
2089 | } | |
b481de9c | 2090 | |
e52119c5 WT |
2091 | tx->driver_txop = 0; |
2092 | tx->tx_flags = tx_flags; | |
2093 | tx->next_frame_len = 0; | |
b481de9c ZY |
2094 | } |
2095 | ||
6440adb5 BC |
2096 | /** |
2097 | * iwl3945_get_sta_id - Find station's index within station table | |
2098 | */ | |
4a8a4322 | 2099 | static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr) |
b481de9c ZY |
2100 | { |
2101 | int sta_id; | |
2102 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2103 | ||
6440adb5 | 2104 | /* If this frame is broadcast or management, use broadcast station id */ |
b481de9c ZY |
2105 | if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) || |
2106 | is_multicast_ether_addr(hdr->addr1)) | |
3832ec9d | 2107 | return priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2108 | |
2109 | switch (priv->iw_mode) { | |
2110 | ||
6440adb5 BC |
2111 | /* If we are a client station in a BSS network, use the special |
2112 | * AP station entry (that's the only station we communicate with) */ | |
05c914fe | 2113 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2114 | return IWL_AP_ID; |
2115 | ||
2116 | /* If we are an AP, then find the station, or use BCAST */ | |
05c914fe | 2117 | case NL80211_IFTYPE_AP: |
bb8c093b | 2118 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2119 | if (sta_id != IWL_INVALID_STATION) |
2120 | return sta_id; | |
3832ec9d | 2121 | return priv->hw_params.bcast_sta_id; |
b481de9c | 2122 | |
6440adb5 BC |
2123 | /* If this frame is going out to an IBSS network, find the station, |
2124 | * or create a new station table entry */ | |
05c914fe | 2125 | case NL80211_IFTYPE_ADHOC: { |
6440adb5 | 2126 | /* Create new station table entry */ |
bb8c093b | 2127 | sta_id = iwl3945_hw_find_station(priv, hdr->addr1); |
b481de9c ZY |
2128 | if (sta_id != IWL_INVALID_STATION) |
2129 | return sta_id; | |
2130 | ||
bb8c093b | 2131 | sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC); |
b481de9c ZY |
2132 | |
2133 | if (sta_id != IWL_INVALID_STATION) | |
2134 | return sta_id; | |
2135 | ||
e174961c | 2136 | IWL_DEBUG_DROP("Station %pM not in station map. " |
b481de9c | 2137 | "Defaulting to broadcast...\n", |
e174961c | 2138 | hdr->addr1); |
40b8ec0b | 2139 | iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr)); |
3832ec9d | 2140 | return priv->hw_params.bcast_sta_id; |
0795af57 | 2141 | } |
914233d6 SG |
2142 | /* If we are in monitor mode, use BCAST. This is required for |
2143 | * packet injection. */ | |
05c914fe | 2144 | case NL80211_IFTYPE_MONITOR: |
3832ec9d | 2145 | return priv->hw_params.bcast_sta_id; |
914233d6 | 2146 | |
b481de9c | 2147 | default: |
39aadf8c WT |
2148 | IWL_WARN(priv, "Unknown mode of operation: %d\n", |
2149 | priv->iw_mode); | |
3832ec9d | 2150 | return priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2151 | } |
2152 | } | |
2153 | ||
2154 | /* | |
2155 | * start REPLY_TX command process | |
2156 | */ | |
4a8a4322 | 2157 | static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
2158 | { |
2159 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 2160 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
dbb6654c | 2161 | struct iwl3945_tfd *tfd; |
e52119c5 | 2162 | struct iwl3945_tx_cmd *tx; |
188cf6c7 | 2163 | struct iwl_tx_queue *txq = NULL; |
d20b3c65 | 2164 | struct iwl_queue *q = NULL; |
e52119c5 | 2165 | struct iwl_cmd *out_cmd = NULL; |
b481de9c ZY |
2166 | dma_addr_t phys_addr; |
2167 | dma_addr_t txcmd_phys; | |
e52119c5 | 2168 | int txq_id = skb_get_queue_mapping(skb); |
54dbb525 TW |
2169 | u16 len, idx, len_org, hdr_len; |
2170 | u8 id; | |
2171 | u8 unicast; | |
b481de9c | 2172 | u8 sta_id; |
54dbb525 | 2173 | u8 tid = 0; |
b481de9c | 2174 | u16 seq_number = 0; |
fd7c8a40 | 2175 | __le16 fc; |
b481de9c | 2176 | u8 wait_write_ptr = 0; |
54dbb525 | 2177 | u8 *qc = NULL; |
b481de9c ZY |
2178 | unsigned long flags; |
2179 | int rc; | |
2180 | ||
2181 | spin_lock_irqsave(&priv->lock, flags); | |
775a6e27 | 2182 | if (iwl_is_rfkill(priv)) { |
b481de9c ZY |
2183 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); |
2184 | goto drop_unlock; | |
2185 | } | |
2186 | ||
e039fa4a | 2187 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
15b1687c | 2188 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
b481de9c ZY |
2189 | goto drop_unlock; |
2190 | } | |
2191 | ||
2192 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
2193 | id = 0; | |
2194 | ||
fd7c8a40 | 2195 | fc = hdr->frame_control; |
b481de9c | 2196 | |
c8b0e6e1 | 2197 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
2198 | if (ieee80211_is_auth(fc)) |
2199 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
fd7c8a40 | 2200 | else if (ieee80211_is_assoc_req(fc)) |
b481de9c | 2201 | IWL_DEBUG_TX("Sending ASSOC frame\n"); |
fd7c8a40 | 2202 | else if (ieee80211_is_reassoc_req(fc)) |
b481de9c ZY |
2203 | IWL_DEBUG_TX("Sending REASSOC frame\n"); |
2204 | #endif | |
2205 | ||
7878a5a4 | 2206 | /* drop all data frame if we are not associated */ |
914233d6 | 2207 | if (ieee80211_is_data(fc) && |
05c914fe | 2208 | (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */ |
914233d6 | 2209 | (!iwl3945_is_associated(priv) || |
05c914fe | 2210 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) { |
bb8c093b | 2211 | IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n"); |
b481de9c ZY |
2212 | goto drop_unlock; |
2213 | } | |
2214 | ||
2215 | spin_unlock_irqrestore(&priv->lock, flags); | |
2216 | ||
7294ec95 | 2217 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 BC |
2218 | |
2219 | /* Find (or create) index into station table for destination station */ | |
bb8c093b | 2220 | sta_id = iwl3945_get_sta_id(priv, hdr); |
b481de9c | 2221 | if (sta_id == IWL_INVALID_STATION) { |
e174961c JB |
2222 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n", |
2223 | hdr->addr1); | |
b481de9c ZY |
2224 | goto drop; |
2225 | } | |
2226 | ||
2227 | IWL_DEBUG_RATE("station Id %d\n", sta_id); | |
2228 | ||
fd7c8a40 HH |
2229 | if (ieee80211_is_data_qos(fc)) { |
2230 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 2231 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
f2c7e521 | 2232 | seq_number = priv->stations_39[sta_id].tid[tid].seq_number & |
b481de9c ZY |
2233 | IEEE80211_SCTL_SEQ; |
2234 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
2235 | (hdr->seq_ctrl & | |
2236 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
2237 | seq_number += 0x10; | |
2238 | } | |
6440adb5 BC |
2239 | |
2240 | /* Descriptor for chosen Tx queue */ | |
188cf6c7 | 2241 | txq = &priv->txq[txq_id]; |
b481de9c ZY |
2242 | q = &txq->q; |
2243 | ||
2244 | spin_lock_irqsave(&priv->lock, flags); | |
2245 | ||
6440adb5 | 2246 | /* Set up first empty TFD within this queue's circular TFD buffer */ |
188cf6c7 | 2247 | tfd = &txq->tfds39[q->write_ptr]; |
b481de9c | 2248 | memset(tfd, 0, sizeof(*tfd)); |
fc4b6853 | 2249 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 2250 | |
6440adb5 | 2251 | /* Set up driver data for this TFD */ |
dbb6654c | 2252 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); |
fc4b6853 | 2253 | txq->txb[q->write_ptr].skb[0] = skb; |
6440adb5 BC |
2254 | |
2255 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
188cf6c7 | 2256 | out_cmd = txq->cmd[idx]; |
e52119c5 | 2257 | tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload; |
b481de9c | 2258 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
e52119c5 | 2259 | memset(tx, 0, sizeof(*tx)); |
6440adb5 BC |
2260 | |
2261 | /* | |
2262 | * Set up the Tx-command (not MAC!) header. | |
2263 | * Store the chosen Tx queue and TFD index within the sequence field; | |
2264 | * after Tx, uCode's Tx response will return this value so driver can | |
2265 | * locate the frame within the tx queue and do post-tx processing. | |
2266 | */ | |
b481de9c ZY |
2267 | out_cmd->hdr.cmd = REPLY_TX; |
2268 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 2269 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
2270 | |
2271 | /* Copy MAC header from skb into command buffer */ | |
e52119c5 | 2272 | memcpy(tx->hdr, hdr, hdr_len); |
b481de9c | 2273 | |
6440adb5 BC |
2274 | /* |
2275 | * Use the first empty entry in this queue's command buffer array | |
2276 | * to contain the Tx command and MAC header concatenated together | |
2277 | * (payload data will be in another buffer). | |
2278 | * Size of this varies, due to varying MAC header length. | |
2279 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
2280 | * of the MAC header (device reads on dword boundaries). | |
2281 | * We'll tell device about this padding later. | |
2282 | */ | |
3832ec9d | 2283 | len = sizeof(struct iwl3945_tx_cmd) + |
4c897253 | 2284 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
2285 | |
2286 | len_org = len; | |
2287 | len = (len + 3) & ~3; | |
2288 | ||
2289 | if (len_org != len) | |
2290 | len_org = 1; | |
2291 | else | |
2292 | len_org = 0; | |
2293 | ||
6440adb5 BC |
2294 | /* Physical address of this Tx command's header (not MAC header!), |
2295 | * within command buffer array. */ | |
188cf6c7 SO |
2296 | txcmd_phys = pci_map_single(priv->pci_dev, |
2297 | out_cmd, sizeof(struct iwl_cmd), | |
2298 | PCI_DMA_TODEVICE); | |
2299 | pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys); | |
2300 | pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd)); | |
2301 | /* Add buffer containing Tx command and MAC(!) header to TFD's | |
2302 | * first entry */ | |
2303 | txcmd_phys += offsetof(struct iwl_cmd, hdr); | |
b481de9c | 2304 | |
6440adb5 BC |
2305 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
2306 | * first entry */ | |
bb8c093b | 2307 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); |
b481de9c | 2308 | |
d0f09804 | 2309 | if (info->control.hw_key) |
e039fa4a | 2310 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0); |
b481de9c | 2311 | |
6440adb5 BC |
2312 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
2313 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
2314 | len = skb->len - hdr_len; |
2315 | if (len) { | |
2316 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
2317 | len, PCI_DMA_TODEVICE); | |
bb8c093b | 2318 | iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); |
b481de9c ZY |
2319 | } |
2320 | ||
b481de9c | 2321 | if (!len) |
6440adb5 | 2322 | /* If there is no payload, then we use only one Tx buffer */ |
dbb6654c | 2323 | tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(1)); |
b481de9c | 2324 | else |
6440adb5 BC |
2325 | /* Else use 2 buffers. |
2326 | * Tell 3945 about any padding after MAC header */ | |
dbb6654c WT |
2327 | tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(2) | |
2328 | TFD_CTL_PAD_SET(U32_PAD(len))); | |
b481de9c | 2329 | |
6440adb5 | 2330 | /* Total # bytes to be transmitted */ |
b481de9c | 2331 | len = (u16)skb->len; |
e52119c5 | 2332 | tx->len = cpu_to_le16(len); |
b481de9c ZY |
2333 | |
2334 | /* TODO need this for burst mode later on */ | |
e52119c5 | 2335 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id); |
b481de9c ZY |
2336 | |
2337 | /* set is_hcca to 0; it probably will never be implemented */ | |
e039fa4a | 2338 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); |
b481de9c | 2339 | |
e52119c5 WT |
2340 | tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; |
2341 | tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
b481de9c | 2342 | |
8b7b1e05 | 2343 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
b481de9c | 2344 | txq->need_update = 1; |
3ac7f146 | 2345 | if (qc) |
f2c7e521 | 2346 | priv->stations_39[sta_id].tid[tid].seq_number = seq_number; |
b481de9c ZY |
2347 | } else { |
2348 | wait_write_ptr = 1; | |
2349 | txq->need_update = 0; | |
2350 | } | |
2351 | ||
e52119c5 | 2352 | iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx)); |
b481de9c | 2353 | |
e52119c5 | 2354 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr, |
7294ec95 | 2355 | ieee80211_hdrlen(fc)); |
b481de9c | 2356 | |
6440adb5 | 2357 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 2358 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
4f3602c8 | 2359 | rc = iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
2360 | spin_unlock_irqrestore(&priv->lock, flags); |
2361 | ||
2362 | if (rc) | |
2363 | return rc; | |
2364 | ||
d20b3c65 | 2365 | if ((iwl_queue_space(q) < q->high_mark) |
b481de9c ZY |
2366 | && priv->mac80211_registered) { |
2367 | if (wait_write_ptr) { | |
2368 | spin_lock_irqsave(&priv->lock, flags); | |
2369 | txq->need_update = 1; | |
4f3602c8 | 2370 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
2371 | spin_unlock_irqrestore(&priv->lock, flags); |
2372 | } | |
2373 | ||
e2530083 | 2374 | ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb)); |
b481de9c ZY |
2375 | } |
2376 | ||
2377 | return 0; | |
2378 | ||
2379 | drop_unlock: | |
2380 | spin_unlock_irqrestore(&priv->lock, flags); | |
2381 | drop: | |
2382 | return -1; | |
2383 | } | |
2384 | ||
4a8a4322 | 2385 | static void iwl3945_set_rate(struct iwl_priv *priv) |
b481de9c | 2386 | { |
8318d78a | 2387 | const struct ieee80211_supported_band *sband = NULL; |
b481de9c ZY |
2388 | struct ieee80211_rate *rate; |
2389 | int i; | |
2390 | ||
cbba18c6 | 2391 | sband = iwl_get_hw_mode(priv, priv->band); |
8318d78a | 2392 | if (!sband) { |
15b1687c | 2393 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); |
c4ba9621 SA |
2394 | return; |
2395 | } | |
b481de9c ZY |
2396 | |
2397 | priv->active_rate = 0; | |
2398 | priv->active_rate_basic = 0; | |
2399 | ||
8318d78a JB |
2400 | IWL_DEBUG_RATE("Setting rates for %s GHz\n", |
2401 | sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5"); | |
2402 | ||
2403 | for (i = 0; i < sband->n_bitrates; i++) { | |
2404 | rate = &sband->bitrates[i]; | |
2405 | if ((rate->hw_value < IWL_RATE_COUNT) && | |
2406 | !(rate->flags & IEEE80211_CHAN_DISABLED)) { | |
2407 | IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n", | |
2408 | rate->hw_value, iwl3945_rates[rate->hw_value].plcp); | |
2409 | priv->active_rate |= (1 << rate->hw_value); | |
2410 | } | |
b481de9c ZY |
2411 | } |
2412 | ||
2413 | IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n", | |
2414 | priv->active_rate, priv->active_rate_basic); | |
2415 | ||
2416 | /* | |
2417 | * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK) | |
2418 | * otherwise set it to the default of all CCK rates and 6, 12, 24 for | |
2419 | * OFDM | |
2420 | */ | |
2421 | if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK) | |
f2c7e521 | 2422 | priv->staging39_rxon.cck_basic_rates = |
b481de9c ZY |
2423 | ((priv->active_rate_basic & |
2424 | IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF; | |
2425 | else | |
f2c7e521 | 2426 | priv->staging39_rxon.cck_basic_rates = |
b481de9c ZY |
2427 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
2428 | ||
2429 | if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK) | |
f2c7e521 | 2430 | priv->staging39_rxon.ofdm_basic_rates = |
b481de9c ZY |
2431 | ((priv->active_rate_basic & |
2432 | (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >> | |
2433 | IWL_FIRST_OFDM_RATE) & 0xFF; | |
2434 | else | |
f2c7e521 | 2435 | priv->staging39_rxon.ofdm_basic_rates = |
b481de9c ZY |
2436 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
2437 | } | |
2438 | ||
4a8a4322 | 2439 | static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio) |
b481de9c ZY |
2440 | { |
2441 | unsigned long flags; | |
2442 | ||
2443 | if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status)) | |
2444 | return; | |
2445 | ||
2446 | IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n", | |
2447 | disable_radio ? "OFF" : "ON"); | |
2448 | ||
2449 | if (disable_radio) { | |
af0053d6 | 2450 | iwl_scan_cancel(priv); |
b481de9c | 2451 | /* FIXME: This is a workaround for AP */ |
05c914fe | 2452 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
b481de9c | 2453 | spin_lock_irqsave(&priv->lock, flags); |
5d49f498 | 2454 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2455 | CSR_UCODE_SW_BIT_RFKILL); |
2456 | spin_unlock_irqrestore(&priv->lock, flags); | |
c496294e | 2457 | iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0); |
b481de9c ZY |
2458 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
2459 | } | |
2460 | return; | |
2461 | } | |
2462 | ||
2463 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 2464 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
b481de9c ZY |
2465 | |
2466 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2467 | spin_unlock_irqrestore(&priv->lock, flags); | |
2468 | ||
2469 | /* wake up ucode */ | |
2470 | msleep(10); | |
2471 | ||
2472 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 AK |
2473 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
2474 | if (!iwl_grab_nic_access(priv)) | |
2475 | iwl_release_nic_access(priv); | |
b481de9c ZY |
2476 | spin_unlock_irqrestore(&priv->lock, flags); |
2477 | ||
2478 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { | |
2479 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
2480 | "disabled by HW switch\n"); | |
2481 | return; | |
2482 | } | |
2483 | ||
808e72a0 ZY |
2484 | if (priv->is_open) |
2485 | queue_work(priv->workqueue, &priv->restart); | |
b481de9c ZY |
2486 | return; |
2487 | } | |
2488 | ||
4a8a4322 | 2489 | void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb, |
b481de9c ZY |
2490 | u32 decrypt_res, struct ieee80211_rx_status *stats) |
2491 | { | |
2492 | u16 fc = | |
2493 | le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control); | |
2494 | ||
f2c7e521 | 2495 | if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) |
b481de9c ZY |
2496 | return; |
2497 | ||
2498 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2499 | return; | |
2500 | ||
2501 | IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res); | |
2502 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2503 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
2504 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2505 | RX_RES_STATUS_BAD_ICV_MIC) | |
2506 | stats->flag |= RX_FLAG_MMIC_ERROR; | |
2507 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2508 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2509 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2510 | RX_RES_STATUS_DECRYPT_OK) { | |
2511 | IWL_DEBUG_RX("hw decrypt successfully!!!\n"); | |
2512 | stats->flag |= RX_FLAG_DECRYPTED; | |
2513 | } | |
2514 | break; | |
2515 | ||
2516 | default: | |
2517 | break; | |
2518 | } | |
2519 | } | |
2520 | ||
c8b0e6e1 | 2521 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
2522 | |
2523 | #include "iwl-spectrum.h" | |
2524 | ||
2525 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF | |
2526 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
2527 | #define TIME_UNIT 1024 | |
2528 | ||
2529 | /* | |
2530 | * extended beacon time format | |
2531 | * time in usec will be changed into a 32-bit value in 8:24 format | |
2532 | * the high 1 byte is the beacon counts | |
2533 | * the lower 3 bytes is the time in usec within one beacon interval | |
2534 | */ | |
2535 | ||
bb8c093b | 2536 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
2537 | { |
2538 | u32 quot; | |
2539 | u32 rem; | |
2540 | u32 interval = beacon_interval * 1024; | |
2541 | ||
2542 | if (!interval || !usec) | |
2543 | return 0; | |
2544 | ||
2545 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
2546 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
2547 | ||
2548 | return (quot << 24) + rem; | |
2549 | } | |
2550 | ||
2551 | /* base is usually what we get from ucode with each received frame, | |
2552 | * the same as HW timer counter counting down | |
2553 | */ | |
2554 | ||
bb8c093b | 2555 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
2556 | { |
2557 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
2558 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
2559 | u32 interval = beacon_interval * TIME_UNIT; | |
2560 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
2561 | (addon & BEACON_TIME_MASK_HIGH); | |
2562 | ||
2563 | if (base_low > addon_low) | |
2564 | res += base_low - addon_low; | |
2565 | else if (base_low < addon_low) { | |
2566 | res += interval + base_low - addon_low; | |
2567 | res += (1 << 24); | |
2568 | } else | |
2569 | res += (1 << 24); | |
2570 | ||
2571 | return cpu_to_le32(res); | |
2572 | } | |
2573 | ||
4a8a4322 | 2574 | static int iwl3945_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
2575 | struct ieee80211_measurement_params *params, |
2576 | u8 type) | |
2577 | { | |
600c0e11 | 2578 | struct iwl_spectrum_cmd spectrum; |
3d24a9f7 | 2579 | struct iwl_rx_packet *res; |
c2d79b48 | 2580 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
2581 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
2582 | .data = (void *)&spectrum, | |
2583 | .meta.flags = CMD_WANT_SKB, | |
2584 | }; | |
2585 | u32 add_time = le64_to_cpu(params->start_time); | |
2586 | int rc; | |
2587 | int spectrum_resp_status; | |
2588 | int duration = le16_to_cpu(params->duration); | |
2589 | ||
bb8c093b | 2590 | if (iwl3945_is_associated(priv)) |
b481de9c | 2591 | add_time = |
bb8c093b | 2592 | iwl3945_usecs_to_beacons( |
b481de9c ZY |
2593 | le64_to_cpu(params->start_time) - priv->last_tsf, |
2594 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2595 | ||
2596 | memset(&spectrum, 0, sizeof(spectrum)); | |
2597 | ||
2598 | spectrum.channel_count = cpu_to_le16(1); | |
2599 | spectrum.flags = | |
2600 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
2601 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
2602 | cmd.len = sizeof(spectrum); | |
2603 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
2604 | ||
bb8c093b | 2605 | if (iwl3945_is_associated(priv)) |
b481de9c | 2606 | spectrum.start_time = |
bb8c093b | 2607 | iwl3945_add_beacon_time(priv->last_beacon_time, |
b481de9c ZY |
2608 | add_time, |
2609 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
2610 | else | |
2611 | spectrum.start_time = 0; | |
2612 | ||
2613 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
2614 | spectrum.channels[0].channel = params->channel; | |
2615 | spectrum.channels[0].type = type; | |
f2c7e521 | 2616 | if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK) |
b481de9c ZY |
2617 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | |
2618 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
2619 | ||
bb8c093b | 2620 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
2621 | if (rc) |
2622 | return rc; | |
2623 | ||
3d24a9f7 | 2624 | res = (struct iwl_rx_packet *)cmd.meta.u.skb->data; |
b481de9c | 2625 | if (res->hdr.flags & IWL_CMD_FAILED_MSK) { |
15b1687c | 2626 | IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n"); |
b481de9c ZY |
2627 | rc = -EIO; |
2628 | } | |
2629 | ||
2630 | spectrum_resp_status = le16_to_cpu(res->u.spectrum.status); | |
2631 | switch (spectrum_resp_status) { | |
2632 | case 0: /* Command will be handled */ | |
2633 | if (res->u.spectrum.id != 0xff) { | |
bc434dd2 IS |
2634 | IWL_DEBUG_INFO("Replaced existing measurement: %d\n", |
2635 | res->u.spectrum.id); | |
b481de9c ZY |
2636 | priv->measurement_status &= ~MEASUREMENT_READY; |
2637 | } | |
2638 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
2639 | rc = 0; | |
2640 | break; | |
2641 | ||
2642 | case 1: /* Command will not be handled */ | |
2643 | rc = -EAGAIN; | |
2644 | break; | |
2645 | } | |
2646 | ||
2647 | dev_kfree_skb_any(cmd.meta.u.skb); | |
2648 | ||
2649 | return rc; | |
2650 | } | |
2651 | #endif | |
2652 | ||
4a8a4322 | 2653 | static void iwl3945_rx_reply_alive(struct iwl_priv *priv, |
6100b588 | 2654 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2655 | { |
3d24a9f7 TW |
2656 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
2657 | struct iwl_alive_resp *palive; | |
b481de9c ZY |
2658 | struct delayed_work *pwork; |
2659 | ||
2660 | palive = &pkt->u.alive_frame; | |
2661 | ||
2662 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
2663 | "0x%01X 0x%01X\n", | |
2664 | palive->is_valid, palive->ver_type, | |
2665 | palive->ver_subtype); | |
2666 | ||
2667 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
2668 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
3d24a9f7 TW |
2669 | memcpy(&priv->card_alive_init, &pkt->u.alive_frame, |
2670 | sizeof(struct iwl_alive_resp)); | |
b481de9c ZY |
2671 | pwork = &priv->init_alive_start; |
2672 | } else { | |
2673 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
2674 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
3d24a9f7 | 2675 | sizeof(struct iwl_alive_resp)); |
b481de9c | 2676 | pwork = &priv->alive_start; |
bb8c093b | 2677 | iwl3945_disable_events(priv); |
b481de9c ZY |
2678 | } |
2679 | ||
2680 | /* We delay the ALIVE response by 5ms to | |
2681 | * give the HW RF Kill time to activate... */ | |
2682 | if (palive->is_valid == UCODE_VALID_OK) | |
2683 | queue_delayed_work(priv->workqueue, pwork, | |
2684 | msecs_to_jiffies(5)); | |
2685 | else | |
39aadf8c | 2686 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
2687 | } |
2688 | ||
4a8a4322 | 2689 | static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv, |
6100b588 | 2690 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2691 | { |
c7e035a9 | 2692 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 2693 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
c7e035a9 | 2694 | #endif |
b481de9c ZY |
2695 | |
2696 | IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); | |
2697 | return; | |
2698 | } | |
2699 | ||
4a8a4322 | 2700 | static void iwl3945_rx_reply_error(struct iwl_priv *priv, |
6100b588 | 2701 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2702 | { |
3d24a9f7 | 2703 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c | 2704 | |
15b1687c | 2705 | IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) " |
b481de9c ZY |
2706 | "seq 0x%04X ser 0x%08X\n", |
2707 | le32_to_cpu(pkt->u.err_resp.error_type), | |
2708 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
2709 | pkt->u.err_resp.cmd_id, | |
2710 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
2711 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
2712 | } | |
2713 | ||
2714 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
2715 | ||
4a8a4322 | 2716 | static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2717 | { |
3d24a9f7 | 2718 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
f2c7e521 | 2719 | struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon; |
600c0e11 | 2720 | struct iwl_csa_notification *csa = &(pkt->u.csa_notif); |
b481de9c ZY |
2721 | IWL_DEBUG_11H("CSA notif: channel %d, status %d\n", |
2722 | le16_to_cpu(csa->channel), le32_to_cpu(csa->status)); | |
2723 | rxon->channel = csa->channel; | |
f2c7e521 | 2724 | priv->staging39_rxon.channel = csa->channel; |
b481de9c ZY |
2725 | } |
2726 | ||
4a8a4322 | 2727 | static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv, |
6100b588 | 2728 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2729 | { |
c8b0e6e1 | 2730 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
3d24a9f7 | 2731 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
600c0e11 | 2732 | struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif); |
b481de9c ZY |
2733 | |
2734 | if (!report->state) { | |
2735 | IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO, | |
2736 | "Spectrum Measure Notification: Start\n"); | |
2737 | return; | |
2738 | } | |
2739 | ||
2740 | memcpy(&priv->measure_report, report, sizeof(*report)); | |
2741 | priv->measurement_status |= MEASUREMENT_READY; | |
2742 | #endif | |
2743 | } | |
2744 | ||
4a8a4322 | 2745 | static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv, |
6100b588 | 2746 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2747 | { |
c8b0e6e1 | 2748 | #ifdef CONFIG_IWL3945_DEBUG |
3d24a9f7 | 2749 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
600c0e11 | 2750 | struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif); |
b481de9c ZY |
2751 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
2752 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
2753 | #endif | |
2754 | } | |
2755 | ||
4a8a4322 | 2756 | static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv, |
6100b588 | 2757 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2758 | { |
3d24a9f7 | 2759 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
2760 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
2761 | "notification for %s:\n", | |
2762 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
40b8ec0b SO |
2763 | iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, |
2764 | le32_to_cpu(pkt->len)); | |
b481de9c ZY |
2765 | } |
2766 | ||
bb8c093b | 2767 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 2768 | { |
4a8a4322 AK |
2769 | struct iwl_priv *priv = |
2770 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
2771 | struct sk_buff *beacon; |
2772 | ||
2773 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 2774 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
2775 | |
2776 | if (!beacon) { | |
15b1687c | 2777 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
2778 | return; |
2779 | } | |
2780 | ||
2781 | mutex_lock(&priv->mutex); | |
2782 | /* new beacon skb is allocated every time; dispose previous.*/ | |
2783 | if (priv->ibss_beacon) | |
2784 | dev_kfree_skb(priv->ibss_beacon); | |
2785 | ||
2786 | priv->ibss_beacon = beacon; | |
2787 | mutex_unlock(&priv->mutex); | |
2788 | ||
bb8c093b | 2789 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
2790 | } |
2791 | ||
4a8a4322 | 2792 | static void iwl3945_rx_beacon_notif(struct iwl_priv *priv, |
6100b588 | 2793 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2794 | { |
c8b0e6e1 | 2795 | #ifdef CONFIG_IWL3945_DEBUG |
3d24a9f7 | 2796 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
bb8c093b | 2797 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); |
b481de9c ZY |
2798 | u8 rate = beacon->beacon_notify_hdr.rate; |
2799 | ||
2800 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
2801 | "tsf %d %d rate %d\n", | |
2802 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
2803 | beacon->beacon_notify_hdr.failure_frame, | |
2804 | le32_to_cpu(beacon->ibss_mgr_status), | |
2805 | le32_to_cpu(beacon->high_tsf), | |
2806 | le32_to_cpu(beacon->low_tsf), rate); | |
2807 | #endif | |
2808 | ||
05c914fe | 2809 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
2810 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
2811 | queue_work(priv->workqueue, &priv->beacon_update); | |
2812 | } | |
2813 | ||
2814 | /* Service response to REPLY_SCAN_CMD (0x80) */ | |
4a8a4322 | 2815 | static void iwl3945_rx_reply_scan(struct iwl_priv *priv, |
6100b588 | 2816 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2817 | { |
c8b0e6e1 | 2818 | #ifdef CONFIG_IWL3945_DEBUG |
3d24a9f7 | 2819 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
4c897253 TW |
2820 | struct iwl_scanreq_notification *notif = |
2821 | (struct iwl_scanreq_notification *)pkt->u.raw; | |
b481de9c ZY |
2822 | |
2823 | IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status); | |
2824 | #endif | |
2825 | } | |
2826 | ||
2827 | /* Service SCAN_START_NOTIFICATION (0x82) */ | |
4a8a4322 | 2828 | static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv, |
6100b588 | 2829 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2830 | { |
3d24a9f7 | 2831 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
4c897253 TW |
2832 | struct iwl_scanstart_notification *notif = |
2833 | (struct iwl_scanstart_notification *)pkt->u.raw; | |
b481de9c ZY |
2834 | priv->scan_start_tsf = le32_to_cpu(notif->tsf_low); |
2835 | IWL_DEBUG_SCAN("Scan start: " | |
2836 | "%d [802.11%s] " | |
2837 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", | |
2838 | notif->channel, | |
2839 | notif->band ? "bg" : "a", | |
2840 | notif->tsf_high, | |
2841 | notif->tsf_low, notif->status, notif->beacon_timer); | |
2842 | } | |
2843 | ||
2844 | /* Service SCAN_RESULTS_NOTIFICATION (0x83) */ | |
4a8a4322 | 2845 | static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv, |
6100b588 | 2846 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2847 | { |
c7e035a9 | 2848 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 2849 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
4c897253 TW |
2850 | struct iwl_scanresults_notification *notif = |
2851 | (struct iwl_scanresults_notification *)pkt->u.raw; | |
c7e035a9 | 2852 | #endif |
b481de9c ZY |
2853 | |
2854 | IWL_DEBUG_SCAN("Scan ch.res: " | |
2855 | "%d [802.11%s] " | |
2856 | "(TSF: 0x%08X:%08X) - %d " | |
2857 | "elapsed=%lu usec (%dms since last)\n", | |
2858 | notif->channel, | |
2859 | notif->band ? "bg" : "a", | |
2860 | le32_to_cpu(notif->tsf_high), | |
2861 | le32_to_cpu(notif->tsf_low), | |
2862 | le32_to_cpu(notif->statistics[0]), | |
2863 | le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf, | |
2864 | jiffies_to_msecs(elapsed_jiffies | |
2865 | (priv->last_scan_jiffies, jiffies))); | |
2866 | ||
2867 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 2868 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
2869 | } |
2870 | ||
2871 | /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */ | |
4a8a4322 | 2872 | static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv, |
6100b588 | 2873 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2874 | { |
c7e035a9 | 2875 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d24a9f7 | 2876 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
4c897253 | 2877 | struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw; |
c7e035a9 | 2878 | #endif |
b481de9c ZY |
2879 | |
2880 | IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", | |
2881 | scan_notif->scanned_channels, | |
2882 | scan_notif->tsf_low, | |
2883 | scan_notif->tsf_high, scan_notif->status); | |
2884 | ||
2885 | /* The HW is no longer scanning */ | |
2886 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
2887 | ||
2888 | /* The scan completion notification came in, so kill that timer... */ | |
2889 | cancel_delayed_work(&priv->scan_check); | |
2890 | ||
2891 | IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n", | |
66b5004d RR |
2892 | (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ? |
2893 | "2.4" : "5.2", | |
b481de9c ZY |
2894 | jiffies_to_msecs(elapsed_jiffies |
2895 | (priv->scan_pass_start, jiffies))); | |
2896 | ||
66b5004d RR |
2897 | /* Remove this scanned band from the list of pending |
2898 | * bands to scan, band G precedes A in order of scanning | |
2899 | * as seen in iwl3945_bg_request_scan */ | |
2900 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) | |
2901 | priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ); | |
2902 | else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) | |
2903 | priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ); | |
b481de9c ZY |
2904 | |
2905 | /* If a request to abort was given, or the scan did not succeed | |
2906 | * then we reset the scan state machine and terminate, | |
2907 | * re-queuing another scan if one has been requested */ | |
2908 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
2909 | IWL_DEBUG_INFO("Aborted scan completed.\n"); | |
2910 | clear_bit(STATUS_SCAN_ABORTING, &priv->status); | |
2911 | } else { | |
2912 | /* If there are more bands on this scan pass reschedule */ | |
2913 | if (priv->scan_bands > 0) | |
2914 | goto reschedule; | |
2915 | } | |
2916 | ||
2917 | priv->last_scan_jiffies = jiffies; | |
7878a5a4 | 2918 | priv->next_scan_jiffies = 0; |
b481de9c ZY |
2919 | IWL_DEBUG_INFO("Setting scan to off\n"); |
2920 | ||
2921 | clear_bit(STATUS_SCANNING, &priv->status); | |
2922 | ||
2923 | IWL_DEBUG_INFO("Scan took %dms\n", | |
2924 | jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies))); | |
2925 | ||
2926 | queue_work(priv->workqueue, &priv->scan_completed); | |
2927 | ||
2928 | return; | |
2929 | ||
2930 | reschedule: | |
2931 | priv->scan_pass_start = jiffies; | |
2932 | queue_work(priv->workqueue, &priv->request_scan); | |
2933 | } | |
2934 | ||
2935 | /* Handle notification from uCode that card's power state is changing | |
2936 | * due to software, hardware, or critical temperature RFKILL */ | |
4a8a4322 | 2937 | static void iwl3945_rx_card_state_notif(struct iwl_priv *priv, |
6100b588 | 2938 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 2939 | { |
3d24a9f7 | 2940 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
2941 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
2942 | unsigned long status = priv->status; | |
2943 | ||
2944 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
2945 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
2946 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
2947 | ||
5d49f498 | 2948 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
2949 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2950 | ||
2951 | if (flags & HW_CARD_DISABLED) | |
2952 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2953 | else | |
2954 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2955 | ||
2956 | ||
2957 | if (flags & SW_CARD_DISABLED) | |
2958 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
2959 | else | |
2960 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
2961 | ||
af0053d6 | 2962 | iwl_scan_cancel(priv); |
b481de9c ZY |
2963 | |
2964 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
2965 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
2966 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
2967 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
2968 | queue_work(priv->workqueue, &priv->rf_kill); | |
2969 | else | |
2970 | wake_up_interruptible(&priv->wait_command_queue); | |
2971 | } | |
2972 | ||
2973 | /** | |
bb8c093b | 2974 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
2975 | * |
2976 | * Setup the RX handlers for each of the reply types sent from the uCode | |
2977 | * to the host. | |
2978 | * | |
2979 | * This function chains into the hardware specific files for them to setup | |
2980 | * any hardware specific handlers as well. | |
2981 | */ | |
4a8a4322 | 2982 | static void iwl3945_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 2983 | { |
bb8c093b CH |
2984 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
2985 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
2986 | priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error; | |
2987 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa; | |
b481de9c | 2988 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
bb8c093b CH |
2989 | iwl3945_rx_spectrum_measure_notif; |
2990 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif; | |
b481de9c | 2991 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
bb8c093b CH |
2992 | iwl3945_rx_pm_debug_statistics_notif; |
2993 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; | |
b481de9c | 2994 | |
9fbab516 BC |
2995 | /* |
2996 | * The same handler is used for both the REPLY to a discrete | |
2997 | * statistics request from the host as well as for the periodic | |
2998 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 2999 | */ |
bb8c093b CH |
3000 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics; |
3001 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; | |
b481de9c | 3002 | |
bb8c093b CH |
3003 | priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan; |
3004 | priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif; | |
b481de9c | 3005 | priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] = |
bb8c093b | 3006 | iwl3945_rx_scan_results_notif; |
b481de9c | 3007 | priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] = |
bb8c093b CH |
3008 | iwl3945_rx_scan_complete_notif; |
3009 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; | |
b481de9c | 3010 | |
9fbab516 | 3011 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 3012 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
3013 | } |
3014 | ||
91c066f2 TW |
3015 | /** |
3016 | * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries | |
3017 | * When FW advances 'R' index, all entries between old and new 'R' index | |
3018 | * need to be reclaimed. | |
3019 | */ | |
4a8a4322 | 3020 | static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv, |
91c066f2 TW |
3021 | int txq_id, int index) |
3022 | { | |
188cf6c7 | 3023 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
d20b3c65 | 3024 | struct iwl_queue *q = &txq->q; |
91c066f2 TW |
3025 | int nfreed = 0; |
3026 | ||
625a381a | 3027 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { |
15b1687c | 3028 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
91c066f2 TW |
3029 | "is out of range [0-%d] %d %d.\n", txq_id, |
3030 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
3031 | return; | |
3032 | } | |
3033 | ||
3034 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
3035 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
3036 | if (nfreed > 1) { | |
15b1687c | 3037 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index, |
91c066f2 TW |
3038 | q->write_ptr, q->read_ptr); |
3039 | queue_work(priv->workqueue, &priv->restart); | |
3040 | break; | |
3041 | } | |
3042 | nfreed++; | |
3043 | } | |
3044 | } | |
3045 | ||
3046 | ||
b481de9c | 3047 | /** |
bb8c093b | 3048 | * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them |
b481de9c ZY |
3049 | * @rxb: Rx buffer to reclaim |
3050 | * | |
3051 | * If an Rx buffer has an async callback associated with it the callback | |
3052 | * will be executed. The attached skb (if present) will only be freed | |
3053 | * if the callback returns 1 | |
3054 | */ | |
4a8a4322 | 3055 | static void iwl3945_tx_cmd_complete(struct iwl_priv *priv, |
6100b588 | 3056 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 3057 | { |
3d24a9f7 | 3058 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3059 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
3060 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3061 | int index = SEQ_TO_INDEX(sequence); | |
600c0e11 | 3062 | int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
b481de9c | 3063 | int cmd_index; |
c2d79b48 | 3064 | struct iwl_cmd *cmd; |
b481de9c | 3065 | |
638d0eb9 CR |
3066 | if (WARN(txq_id != IWL_CMD_QUEUE_NUM, |
3067 | "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n", | |
3068 | txq_id, sequence, | |
3069 | priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr, | |
3070 | priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) { | |
3071 | iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32); | |
3072 | return; | |
3073 | } | |
b481de9c | 3074 | |
188cf6c7 SO |
3075 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); |
3076 | cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
b481de9c ZY |
3077 | |
3078 | /* Input error checking is done when commands are added to queue. */ | |
3079 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
3080 | cmd->meta.source->u.skb = rxb->skb; | |
3081 | rxb->skb = NULL; | |
3082 | } else if (cmd->meta.u.callback && | |
3083 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
3084 | rxb->skb = NULL; | |
3085 | ||
91c066f2 | 3086 | iwl3945_cmd_queue_reclaim(priv, txq_id, index); |
b481de9c ZY |
3087 | |
3088 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
3089 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3090 | wake_up_interruptible(&priv->wait_command_queue); | |
3091 | } | |
3092 | } | |
3093 | ||
3094 | /************************** RX-FUNCTIONS ****************************/ | |
3095 | /* | |
3096 | * Rx theory of operation | |
3097 | * | |
3098 | * The host allocates 32 DMA target addresses and passes the host address | |
3099 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
3100 | * 0 to 31 | |
3101 | * | |
3102 | * Rx Queue Indexes | |
3103 | * The host/firmware share two index registers for managing the Rx buffers. | |
3104 | * | |
3105 | * The READ index maps to the first position that the firmware may be writing | |
3106 | * to -- the driver can read up to (but not including) this position and get | |
3107 | * good data. | |
3108 | * The READ index is managed by the firmware once the card is enabled. | |
3109 | * | |
3110 | * The WRITE index maps to the last position the driver has read from -- the | |
3111 | * position preceding WRITE is the last slot the firmware can place a packet. | |
3112 | * | |
3113 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
3114 | * WRITE = READ. | |
3115 | * | |
9fbab516 | 3116 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
3117 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
3118 | * | |
9fbab516 | 3119 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
3120 | * and fire the RX interrupt. The driver can then query the READ index and |
3121 | * process as many packets as possible, moving the WRITE index forward as it | |
3122 | * resets the Rx queue buffers with new memory. | |
3123 | * | |
3124 | * The management in the driver is as follows: | |
3125 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
3126 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 3127 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 3128 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
3129 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
3130 | * 'processed' and 'read' driver indexes as well) | |
3131 | * + A received packet is processed and handed to the kernel network stack, | |
3132 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
3133 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
3134 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
3135 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
3136 | * were enough free buffers and RX_STALLED is set it is cleared. | |
3137 | * | |
3138 | * | |
3139 | * Driver sequence: | |
3140 | * | |
9fbab516 | 3141 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls |
bb8c093b | 3142 | * iwl3945_rx_queue_restock |
9fbab516 | 3143 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
3144 | * queue, updates firmware pointers, and updates |
3145 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 3146 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
3147 | * |
3148 | * -- enable interrupts -- | |
6100b588 | 3149 | * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the |
b481de9c ZY |
3150 | * READ INDEX, detaching the SKB from the pool. |
3151 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 3152 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
3153 | * slots. |
3154 | * ... | |
3155 | * | |
3156 | */ | |
3157 | ||
b481de9c | 3158 | /** |
9fbab516 | 3159 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 3160 | */ |
4a8a4322 | 3161 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
3162 | dma_addr_t dma_addr) |
3163 | { | |
3164 | return cpu_to_le32((u32)dma_addr); | |
3165 | } | |
3166 | ||
3167 | /** | |
bb8c093b | 3168 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 3169 | * |
9fbab516 | 3170 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 3171 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 3172 | * as we can, pulling from rx_free. |
b481de9c ZY |
3173 | * |
3174 | * This moves the 'write' index forward to catch up with 'processed', and | |
3175 | * also updates the memory address in the firmware to reference the new | |
3176 | * target buffer. | |
3177 | */ | |
4a8a4322 | 3178 | static int iwl3945_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 3179 | { |
cc2f362c | 3180 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 3181 | struct list_head *element; |
6100b588 | 3182 | struct iwl_rx_mem_buffer *rxb; |
b481de9c ZY |
3183 | unsigned long flags; |
3184 | int write, rc; | |
3185 | ||
3186 | spin_lock_irqsave(&rxq->lock, flags); | |
3187 | write = rxq->write & ~0x7; | |
37d68317 | 3188 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 3189 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 3190 | element = rxq->rx_free.next; |
6100b588 | 3191 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
b481de9c | 3192 | list_del(element); |
6440adb5 BC |
3193 | |
3194 | /* Point to Rx buffer via next RBD in circular buffer */ | |
6100b588 | 3195 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr); |
b481de9c ZY |
3196 | rxq->queue[rxq->write] = rxb; |
3197 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
3198 | rxq->free_count--; | |
3199 | } | |
3200 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3201 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
3202 | * refill it */ | |
3203 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
3204 | queue_work(priv->workqueue, &priv->rx_replenish); | |
3205 | ||
3206 | ||
6440adb5 BC |
3207 | /* If we've added more space for the firmware to place data, tell it. |
3208 | * Increment device's write pointer in multiples of 8. */ | |
b481de9c ZY |
3209 | if ((write != (rxq->write & ~0x7)) |
3210 | || (abs(rxq->write - rxq->read) > 7)) { | |
3211 | spin_lock_irqsave(&rxq->lock, flags); | |
3212 | rxq->need_update = 1; | |
3213 | spin_unlock_irqrestore(&rxq->lock, flags); | |
141c43a3 | 3214 | rc = iwl_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
3215 | if (rc) |
3216 | return rc; | |
3217 | } | |
3218 | ||
3219 | return 0; | |
3220 | } | |
3221 | ||
3222 | /** | |
bb8c093b | 3223 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
3224 | * |
3225 | * When moving to rx_free an SKB is allocated for the slot. | |
3226 | * | |
bb8c093b | 3227 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 3228 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 3229 | */ |
4a8a4322 | 3230 | static void iwl3945_rx_allocate(struct iwl_priv *priv) |
b481de9c | 3231 | { |
cc2f362c | 3232 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 3233 | struct list_head *element; |
6100b588 | 3234 | struct iwl_rx_mem_buffer *rxb; |
b481de9c ZY |
3235 | unsigned long flags; |
3236 | spin_lock_irqsave(&rxq->lock, flags); | |
3237 | while (!list_empty(&rxq->rx_used)) { | |
3238 | element = rxq->rx_used.next; | |
6100b588 | 3239 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
6440adb5 BC |
3240 | |
3241 | /* Alloc a new receive buffer */ | |
b481de9c | 3242 | rxb->skb = |
1e33dc64 WT |
3243 | alloc_skb(priv->hw_params.rx_buf_size, |
3244 | __GFP_NOWARN | GFP_ATOMIC); | |
b481de9c ZY |
3245 | if (!rxb->skb) { |
3246 | if (net_ratelimit()) | |
978785a3 | 3247 | IWL_CRIT(priv, ": Can not allocate SKB buffers\n"); |
b481de9c ZY |
3248 | /* We don't reschedule replenish work here -- we will |
3249 | * call the restock method and if it still needs | |
3250 | * more buffers it will schedule replenish */ | |
3251 | break; | |
3252 | } | |
12342c47 ZY |
3253 | |
3254 | /* If radiotap head is required, reserve some headroom here. | |
3255 | * The physical head count is a variable rx_stats->phy_count. | |
3256 | * We reserve 4 bytes here. Plus these extra bytes, the | |
3257 | * headroom of the physical head should be enough for the | |
3258 | * radiotap head that iwl3945 supported. See iwl3945_rt. | |
3259 | */ | |
3260 | skb_reserve(rxb->skb, 4); | |
3261 | ||
b481de9c ZY |
3262 | priv->alloc_rxb_skb++; |
3263 | list_del(element); | |
6440adb5 BC |
3264 | |
3265 | /* Get physical address of RB/SKB */ | |
1e33dc64 WT |
3266 | rxb->real_dma_addr = pci_map_single(priv->pci_dev, |
3267 | rxb->skb->data, | |
3268 | priv->hw_params.rx_buf_size, | |
3269 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
3270 | list_add_tail(&rxb->list, &rxq->rx_free); |
3271 | rxq->free_count++; | |
3272 | } | |
3273 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5c0eef96 MA |
3274 | } |
3275 | ||
3276 | /* | |
3277 | * this should be called while priv->lock is locked | |
3278 | */ | |
4fd1f841 | 3279 | static void __iwl3945_rx_replenish(void *data) |
5c0eef96 | 3280 | { |
4a8a4322 | 3281 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3282 | |
3283 | iwl3945_rx_allocate(priv); | |
3284 | iwl3945_rx_queue_restock(priv); | |
3285 | } | |
3286 | ||
3287 | ||
3288 | void iwl3945_rx_replenish(void *data) | |
3289 | { | |
4a8a4322 | 3290 | struct iwl_priv *priv = data; |
5c0eef96 MA |
3291 | unsigned long flags; |
3292 | ||
3293 | iwl3945_rx_allocate(priv); | |
b481de9c ZY |
3294 | |
3295 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 3296 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
3297 | spin_unlock_irqrestore(&priv->lock, flags); |
3298 | } | |
3299 | ||
b481de9c ZY |
3300 | /* Convert linear signal-to-noise ratio into dB */ |
3301 | static u8 ratio2dB[100] = { | |
3302 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
3303 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
3304 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
3305 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
3306 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
3307 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
3308 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
3309 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
3310 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
3311 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
3312 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
3313 | }; | |
3314 | ||
3315 | /* Calculates a relative dB value from a ratio of linear | |
3316 | * (i.e. not dB) signal levels. | |
3317 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 3318 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 3319 | { |
221c80cf AB |
3320 | /* 1000:1 or higher just report as 60 dB */ |
3321 | if (sig_ratio >= 1000) | |
b481de9c ZY |
3322 | return 60; |
3323 | ||
221c80cf | 3324 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 3325 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 3326 | if (sig_ratio >= 100) |
3ac7f146 | 3327 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
3328 | |
3329 | /* We shouldn't see this */ | |
3330 | if (sig_ratio < 1) | |
3331 | return 0; | |
3332 | ||
3333 | /* Use table for ratios 1:1 - 99:1 */ | |
3334 | return (int)ratio2dB[sig_ratio]; | |
3335 | } | |
3336 | ||
3337 | #define PERFECT_RSSI (-20) /* dBm */ | |
3338 | #define WORST_RSSI (-95) /* dBm */ | |
3339 | #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI) | |
3340 | ||
3341 | /* Calculate an indication of rx signal quality (a percentage, not dBm!). | |
3342 | * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info | |
3343 | * about formulas used below. */ | |
bb8c093b | 3344 | int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm) |
b481de9c ZY |
3345 | { |
3346 | int sig_qual; | |
3347 | int degradation = PERFECT_RSSI - rssi_dbm; | |
3348 | ||
3349 | /* If we get a noise measurement, use signal-to-noise ratio (SNR) | |
3350 | * as indicator; formula is (signal dbm - noise dbm). | |
3351 | * SNR at or above 40 is a great signal (100%). | |
3352 | * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator. | |
3353 | * Weakest usable signal is usually 10 - 15 dB SNR. */ | |
3354 | if (noise_dbm) { | |
3355 | if (rssi_dbm - noise_dbm >= 40) | |
3356 | return 100; | |
3357 | else if (rssi_dbm < noise_dbm) | |
3358 | return 0; | |
3359 | sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2; | |
3360 | ||
3361 | /* Else use just the signal level. | |
3362 | * This formula is a least squares fit of data points collected and | |
3363 | * compared with a reference system that had a percentage (%) display | |
3364 | * for signal quality. */ | |
3365 | } else | |
3366 | sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation * | |
3367 | (15 * RSSI_RANGE + 62 * degradation)) / | |
3368 | (RSSI_RANGE * RSSI_RANGE); | |
3369 | ||
3370 | if (sig_qual > 100) | |
3371 | sig_qual = 100; | |
3372 | else if (sig_qual < 1) | |
3373 | sig_qual = 0; | |
3374 | ||
3375 | return sig_qual; | |
3376 | } | |
3377 | ||
3378 | /** | |
9fbab516 | 3379 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
3380 | * |
3381 | * Uses the priv->rx_handlers callback function array to invoke | |
3382 | * the appropriate handlers, including command responses, | |
3383 | * frame-received notifications, and other notifications. | |
3384 | */ | |
4a8a4322 | 3385 | static void iwl3945_rx_handle(struct iwl_priv *priv) |
b481de9c | 3386 | { |
6100b588 | 3387 | struct iwl_rx_mem_buffer *rxb; |
3d24a9f7 | 3388 | struct iwl_rx_packet *pkt; |
cc2f362c | 3389 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
3390 | u32 r, i; |
3391 | int reclaim; | |
3392 | unsigned long flags; | |
5c0eef96 | 3393 | u8 fill_rx = 0; |
d68ab680 | 3394 | u32 count = 8; |
b481de9c | 3395 | |
6440adb5 BC |
3396 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
3397 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8cd812bc | 3398 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
3399 | i = rxq->read; |
3400 | ||
37d68317 | 3401 | if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
5c0eef96 | 3402 | fill_rx = 1; |
b481de9c ZY |
3403 | /* Rx interrupt, but nothing sent from uCode */ |
3404 | if (i == r) | |
3405 | IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i); | |
3406 | ||
3407 | while (i != r) { | |
3408 | rxb = rxq->queue[i]; | |
3409 | ||
9fbab516 | 3410 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
3411 | * then a bug has been introduced in the queue refilling |
3412 | * routines -- catch it here */ | |
3413 | BUG_ON(rxb == NULL); | |
3414 | ||
3415 | rxq->queue[i] = NULL; | |
3416 | ||
6100b588 | 3417 | pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr, |
1e33dc64 | 3418 | priv->hw_params.rx_buf_size, |
b481de9c | 3419 | PCI_DMA_FROMDEVICE); |
3d24a9f7 | 3420 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3421 | |
3422 | /* Reclaim a command buffer only if this packet is a response | |
3423 | * to a (driver-originated) command. | |
3424 | * If the packet (e.g. Rx frame) originated from uCode, | |
3425 | * there is no command buffer to reclaim. | |
3426 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
3427 | * but apparently a few don't get set; catch them here. */ | |
3428 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
3429 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
3430 | (pkt->hdr.cmd != REPLY_TX); | |
3431 | ||
3432 | /* Based on type of command response or notification, | |
3433 | * handle those that need handling via function in | |
bb8c093b | 3434 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c | 3435 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
40b8ec0b | 3436 | IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR, |
b481de9c ZY |
3437 | "r = %d, i = %d, %s, 0x%02x\n", r, i, |
3438 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
3439 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); | |
3440 | } else { | |
3441 | /* No handling needed */ | |
40b8ec0b | 3442 | IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR, |
b481de9c ZY |
3443 | "r %d i %d No handler needed for %s, 0x%02x\n", |
3444 | r, i, get_cmd_string(pkt->hdr.cmd), | |
3445 | pkt->hdr.cmd); | |
3446 | } | |
3447 | ||
3448 | if (reclaim) { | |
9fbab516 BC |
3449 | /* Invoke any callbacks, transfer the skb to caller, and |
3450 | * fire off the (possibly) blocking iwl3945_send_cmd() | |
b481de9c ZY |
3451 | * as we reclaim the driver command queue */ |
3452 | if (rxb && rxb->skb) | |
bb8c093b | 3453 | iwl3945_tx_cmd_complete(priv, rxb); |
b481de9c | 3454 | else |
39aadf8c | 3455 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
3456 | } |
3457 | ||
3458 | /* For now we just don't re-use anything. We can tweak this | |
3459 | * later to try and re-use notification packets and SKBs that | |
3460 | * fail to Rx correctly */ | |
3461 | if (rxb->skb != NULL) { | |
3462 | priv->alloc_rxb_skb--; | |
3463 | dev_kfree_skb_any(rxb->skb); | |
3464 | rxb->skb = NULL; | |
3465 | } | |
3466 | ||
6100b588 | 3467 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
1e33dc64 WT |
3468 | priv->hw_params.rx_buf_size, |
3469 | PCI_DMA_FROMDEVICE); | |
b481de9c ZY |
3470 | spin_lock_irqsave(&rxq->lock, flags); |
3471 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
3472 | spin_unlock_irqrestore(&rxq->lock, flags); | |
3473 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
3474 | /* If there are a lot of unused frames, |
3475 | * restock the Rx queue so ucode won't assert. */ | |
3476 | if (fill_rx) { | |
3477 | count++; | |
3478 | if (count >= 8) { | |
3479 | priv->rxq.read = i; | |
3480 | __iwl3945_rx_replenish(priv); | |
3481 | count = 0; | |
3482 | } | |
3483 | } | |
b481de9c ZY |
3484 | } |
3485 | ||
3486 | /* Backtrack one entry */ | |
3487 | priv->rxq.read = i; | |
bb8c093b | 3488 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
3489 | } |
3490 | ||
c8b0e6e1 | 3491 | #ifdef CONFIG_IWL3945_DEBUG |
4a8a4322 | 3492 | static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv, |
40b8ec0b | 3493 | struct iwl3945_rxon_cmd *rxon) |
b481de9c ZY |
3494 | { |
3495 | IWL_DEBUG_RADIO("RX CONFIG:\n"); | |
40b8ec0b | 3496 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
b481de9c ZY |
3497 | IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
3498 | IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
3499 | IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n", | |
3500 | le32_to_cpu(rxon->filter_flags)); | |
3501 | IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); | |
3502 | IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n", | |
3503 | rxon->ofdm_basic_rates); | |
3504 | IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
e174961c JB |
3505 | IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr); |
3506 | IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
b481de9c ZY |
3507 | IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
3508 | } | |
3509 | #endif | |
3510 | ||
4a8a4322 | 3511 | static void iwl3945_enable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
3512 | { |
3513 | IWL_DEBUG_ISR("Enabling interrupts\n"); | |
3514 | set_bit(STATUS_INT_ENABLED, &priv->status); | |
5d49f498 | 3515 | iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK); |
b481de9c ZY |
3516 | } |
3517 | ||
0359facc MA |
3518 | |
3519 | /* call this function to flush any scheduled tasklet */ | |
4a8a4322 | 3520 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) |
0359facc | 3521 | { |
a96a27f9 | 3522 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
3523 | synchronize_irq(priv->pci_dev->irq); |
3524 | tasklet_kill(&priv->irq_tasklet); | |
3525 | } | |
3526 | ||
3527 | ||
4a8a4322 | 3528 | static inline void iwl3945_disable_interrupts(struct iwl_priv *priv) |
b481de9c ZY |
3529 | { |
3530 | clear_bit(STATUS_INT_ENABLED, &priv->status); | |
3531 | ||
3532 | /* disable interrupts from uCode/NIC to host */ | |
5d49f498 | 3533 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); |
b481de9c ZY |
3534 | |
3535 | /* acknowledge/clear/reset any interrupts still pending | |
3536 | * from uCode or flow handler (Rx/Tx DMA) */ | |
5d49f498 AK |
3537 | iwl_write32(priv, CSR_INT, 0xffffffff); |
3538 | iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff); | |
b481de9c ZY |
3539 | IWL_DEBUG_ISR("Disabled interrupts\n"); |
3540 | } | |
3541 | ||
3542 | static const char *desc_lookup(int i) | |
3543 | { | |
3544 | switch (i) { | |
3545 | case 1: | |
3546 | return "FAIL"; | |
3547 | case 2: | |
3548 | return "BAD_PARAM"; | |
3549 | case 3: | |
3550 | return "BAD_CHECKSUM"; | |
3551 | case 4: | |
3552 | return "NMI_INTERRUPT"; | |
3553 | case 5: | |
3554 | return "SYSASSERT"; | |
3555 | case 6: | |
3556 | return "FATAL_ERROR"; | |
3557 | } | |
3558 | ||
3559 | return "UNKNOWN"; | |
3560 | } | |
3561 | ||
3562 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
3563 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
3564 | ||
4a8a4322 | 3565 | static void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
3566 | { |
3567 | u32 i; | |
3568 | u32 desc, time, count, base, data1; | |
3569 | u32 blink1, blink2, ilink1, ilink2; | |
3570 | int rc; | |
3571 | ||
3572 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
3573 | ||
bb8c093b | 3574 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 3575 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); |
b481de9c ZY |
3576 | return; |
3577 | } | |
3578 | ||
5d49f498 | 3579 | rc = iwl_grab_nic_access(priv); |
b481de9c | 3580 | if (rc) { |
39aadf8c | 3581 | IWL_WARN(priv, "Can not read from adapter at this time.\n"); |
b481de9c ZY |
3582 | return; |
3583 | } | |
3584 | ||
5d49f498 | 3585 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
3586 | |
3587 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
15b1687c WT |
3588 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
3589 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
3590 | priv->status, count); | |
b481de9c ZY |
3591 | } |
3592 | ||
15b1687c | 3593 | IWL_ERR(priv, "Desc Time asrtPC blink2 " |
b481de9c ZY |
3594 | "ilink1 nmiPC Line\n"); |
3595 | for (i = ERROR_START_OFFSET; | |
3596 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
3597 | i += ERROR_ELEM_SIZE) { | |
5d49f498 | 3598 | desc = iwl_read_targ_mem(priv, base + i); |
b481de9c | 3599 | time = |
5d49f498 | 3600 | iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 3601 | blink1 = |
5d49f498 | 3602 | iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 3603 | blink2 = |
5d49f498 | 3604 | iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 3605 | ilink1 = |
5d49f498 | 3606 | iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 3607 | ilink2 = |
5d49f498 | 3608 | iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 3609 | data1 = |
5d49f498 | 3610 | iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c | 3611 | |
15b1687c WT |
3612 | IWL_ERR(priv, |
3613 | "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
3614 | desc_lookup(desc), desc, time, blink1, blink2, | |
3615 | ilink1, ilink2, data1); | |
b481de9c ZY |
3616 | } |
3617 | ||
5d49f498 | 3618 | iwl_release_nic_access(priv); |
b481de9c ZY |
3619 | |
3620 | } | |
3621 | ||
f58177b9 | 3622 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
3623 | |
3624 | /** | |
bb8c093b | 3625 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 3626 | * |
5d49f498 | 3627 | * NOTE: Must be called with iwl_grab_nic_access() already obtained! |
b481de9c | 3628 | */ |
4a8a4322 | 3629 | static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, |
b481de9c ZY |
3630 | u32 num_events, u32 mode) |
3631 | { | |
3632 | u32 i; | |
3633 | u32 base; /* SRAM byte address of event log header */ | |
3634 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
3635 | u32 ptr; /* SRAM byte address of log data */ | |
3636 | u32 ev, time, data; /* event log data */ | |
3637 | ||
3638 | if (num_events == 0) | |
3639 | return; | |
3640 | ||
3641 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
3642 | ||
3643 | if (mode == 0) | |
3644 | event_size = 2 * sizeof(u32); | |
3645 | else | |
3646 | event_size = 3 * sizeof(u32); | |
3647 | ||
3648 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
3649 | ||
3650 | /* "time" is actually "data" for mode 0 (no timestamp). | |
3651 | * place event id # at far right for easier visual parsing. */ | |
3652 | for (i = 0; i < num_events; i++) { | |
5d49f498 | 3653 | ev = iwl_read_targ_mem(priv, ptr); |
b481de9c | 3654 | ptr += sizeof(u32); |
5d49f498 | 3655 | time = iwl_read_targ_mem(priv, ptr); |
b481de9c | 3656 | ptr += sizeof(u32); |
15b1687c WT |
3657 | if (mode == 0) { |
3658 | /* data, ev */ | |
3659 | IWL_ERR(priv, "0x%08x\t%04u\n", time, ev); | |
3660 | } else { | |
5d49f498 | 3661 | data = iwl_read_targ_mem(priv, ptr); |
b481de9c | 3662 | ptr += sizeof(u32); |
15b1687c | 3663 | IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev); |
b481de9c ZY |
3664 | } |
3665 | } | |
3666 | } | |
3667 | ||
4a8a4322 | 3668 | static void iwl3945_dump_nic_event_log(struct iwl_priv *priv) |
b481de9c ZY |
3669 | { |
3670 | int rc; | |
3671 | u32 base; /* SRAM byte address of event log header */ | |
3672 | u32 capacity; /* event log capacity in # entries */ | |
3673 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
3674 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
3675 | u32 next_entry; /* index of next entry to be written by uCode */ | |
3676 | u32 size; /* # entries that we'll print */ | |
3677 | ||
3678 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 3679 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 3680 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
b481de9c ZY |
3681 | return; |
3682 | } | |
3683 | ||
5d49f498 | 3684 | rc = iwl_grab_nic_access(priv); |
b481de9c | 3685 | if (rc) { |
39aadf8c | 3686 | IWL_WARN(priv, "Can not read from adapter at this time.\n"); |
b481de9c ZY |
3687 | return; |
3688 | } | |
3689 | ||
3690 | /* event log header */ | |
5d49f498 AK |
3691 | capacity = iwl_read_targ_mem(priv, base); |
3692 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
3693 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
3694 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c ZY |
3695 | |
3696 | size = num_wraps ? capacity : next_entry; | |
3697 | ||
3698 | /* bail out if nothing in log */ | |
3699 | if (size == 0) { | |
15b1687c | 3700 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); |
5d49f498 | 3701 | iwl_release_nic_access(priv); |
b481de9c ZY |
3702 | return; |
3703 | } | |
3704 | ||
15b1687c | 3705 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", |
b481de9c ZY |
3706 | size, num_wraps); |
3707 | ||
3708 | /* if uCode has wrapped back to top of log, start at the oldest entry, | |
3709 | * i.e the next one that uCode would fill. */ | |
3710 | if (num_wraps) | |
bb8c093b | 3711 | iwl3945_print_event_log(priv, next_entry, |
b481de9c ZY |
3712 | capacity - next_entry, mode); |
3713 | ||
3714 | /* (then/else) start at top of log */ | |
bb8c093b | 3715 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
b481de9c | 3716 | |
5d49f498 | 3717 | iwl_release_nic_access(priv); |
b481de9c ZY |
3718 | } |
3719 | ||
3720 | /** | |
bb8c093b | 3721 | * iwl3945_irq_handle_error - called for HW or SW error interrupt from card |
b481de9c | 3722 | */ |
4a8a4322 | 3723 | static void iwl3945_irq_handle_error(struct iwl_priv *priv) |
b481de9c | 3724 | { |
bb8c093b | 3725 | /* Set the FW error flag -- cleared on iwl3945_down */ |
b481de9c ZY |
3726 | set_bit(STATUS_FW_ERROR, &priv->status); |
3727 | ||
3728 | /* Cancel currently queued command. */ | |
3729 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
3730 | ||
c8b0e6e1 | 3731 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 3732 | if (priv->debug_level & IWL_DL_FW_ERRORS) { |
bb8c093b CH |
3733 | iwl3945_dump_nic_error_log(priv); |
3734 | iwl3945_dump_nic_event_log(priv); | |
f2c7e521 | 3735 | iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon); |
b481de9c ZY |
3736 | } |
3737 | #endif | |
3738 | ||
3739 | wake_up_interruptible(&priv->wait_command_queue); | |
3740 | ||
3741 | /* Keep the restart process from trying to send host | |
3742 | * commands by clearing the INIT status bit */ | |
3743 | clear_bit(STATUS_READY, &priv->status); | |
3744 | ||
3745 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
3746 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS, | |
3747 | "Restarting adapter due to uCode error.\n"); | |
3748 | ||
bb8c093b | 3749 | if (iwl3945_is_associated(priv)) { |
f2c7e521 AK |
3750 | memcpy(&priv->recovery39_rxon, &priv->active39_rxon, |
3751 | sizeof(priv->recovery39_rxon)); | |
b481de9c ZY |
3752 | priv->error_recovering = 1; |
3753 | } | |
3754 | queue_work(priv->workqueue, &priv->restart); | |
3755 | } | |
3756 | } | |
3757 | ||
4a8a4322 | 3758 | static void iwl3945_error_recovery(struct iwl_priv *priv) |
b481de9c ZY |
3759 | { |
3760 | unsigned long flags; | |
3761 | ||
f2c7e521 AK |
3762 | memcpy(&priv->staging39_rxon, &priv->recovery39_rxon, |
3763 | sizeof(priv->staging39_rxon)); | |
3764 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
bb8c093b | 3765 | iwl3945_commit_rxon(priv); |
b481de9c | 3766 | |
bb8c093b | 3767 | iwl3945_add_station(priv, priv->bssid, 1, 0); |
b481de9c ZY |
3768 | |
3769 | spin_lock_irqsave(&priv->lock, flags); | |
f2c7e521 | 3770 | priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id); |
b481de9c ZY |
3771 | priv->error_recovering = 0; |
3772 | spin_unlock_irqrestore(&priv->lock, flags); | |
3773 | } | |
3774 | ||
4a8a4322 | 3775 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
3776 | { |
3777 | u32 inta, handled = 0; | |
3778 | u32 inta_fh; | |
3779 | unsigned long flags; | |
c8b0e6e1 | 3780 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
3781 | u32 inta_mask; |
3782 | #endif | |
3783 | ||
3784 | spin_lock_irqsave(&priv->lock, flags); | |
3785 | ||
3786 | /* Ack/clear/reset pending uCode interrupts. | |
3787 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
3788 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
5d49f498 AK |
3789 | inta = iwl_read32(priv, CSR_INT); |
3790 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
3791 | |
3792 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
3793 | * Any new interrupts that happen after this, either while we're | |
3794 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
5d49f498 AK |
3795 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
3796 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 3797 | |
c8b0e6e1 | 3798 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 3799 | if (priv->debug_level & IWL_DL_ISR) { |
9fbab516 | 3800 | /* just for debug */ |
5d49f498 | 3801 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
b481de9c ZY |
3802 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
3803 | inta, inta_mask, inta_fh); | |
3804 | } | |
3805 | #endif | |
3806 | ||
3807 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
3808 | * atomic, make sure that inta covers all the interrupts that | |
3809 | * we've discovered, even if FH interrupt came in just after | |
3810 | * reading CSR_INT. */ | |
6f83eaa1 | 3811 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 3812 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 3813 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
3814 | inta |= CSR_INT_BIT_FH_TX; |
3815 | ||
3816 | /* Now service all interrupt bits discovered above. */ | |
3817 | if (inta & CSR_INT_BIT_HW_ERR) { | |
15b1687c | 3818 | IWL_ERR(priv, "Microcode HW error detected. Restarting.\n"); |
b481de9c ZY |
3819 | |
3820 | /* Tell the device to stop sending interrupts */ | |
bb8c093b | 3821 | iwl3945_disable_interrupts(priv); |
b481de9c | 3822 | |
bb8c093b | 3823 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
3824 | |
3825 | handled |= CSR_INT_BIT_HW_ERR; | |
3826 | ||
3827 | spin_unlock_irqrestore(&priv->lock, flags); | |
3828 | ||
3829 | return; | |
3830 | } | |
3831 | ||
c8b0e6e1 | 3832 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 3833 | if (priv->debug_level & (IWL_DL_ISR)) { |
b481de9c | 3834 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
3835 | if (inta & CSR_INT_BIT_SCD) |
3836 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
3837 | "the frame/frames.\n"); | |
b481de9c ZY |
3838 | |
3839 | /* Alive notification via Rx interrupt will do the real work */ | |
3840 | if (inta & CSR_INT_BIT_ALIVE) | |
3841 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
3842 | } | |
3843 | #endif | |
3844 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 3845 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 3846 | |
b481de9c ZY |
3847 | /* Error detected by uCode */ |
3848 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
3849 | IWL_ERR(priv, "Microcode SW error detected. " |
3850 | "Restarting 0x%X.\n", inta); | |
bb8c093b | 3851 | iwl3945_irq_handle_error(priv); |
b481de9c ZY |
3852 | handled |= CSR_INT_BIT_SW_ERR; |
3853 | } | |
3854 | ||
3855 | /* uCode wakes up after power-down sleep */ | |
3856 | if (inta & CSR_INT_BIT_WAKEUP) { | |
3857 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
141c43a3 | 3858 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
4f3602c8 SO |
3859 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
3860 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
3861 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
3862 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
3863 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
3864 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c ZY |
3865 | |
3866 | handled |= CSR_INT_BIT_WAKEUP; | |
3867 | } | |
3868 | ||
3869 | /* All uCode command responses, including Tx command responses, | |
3870 | * Rx "responses" (frame-received notification), and other | |
3871 | * notifications from uCode come through here*/ | |
3872 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 3873 | iwl3945_rx_handle(priv); |
b481de9c ZY |
3874 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
3875 | } | |
3876 | ||
3877 | if (inta & CSR_INT_BIT_FH_TX) { | |
3878 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
3879 | ||
5d49f498 AK |
3880 | iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
3881 | if (!iwl_grab_nic_access(priv)) { | |
3882 | iwl_write_direct32(priv, FH39_TCSR_CREDIT | |
bddadf86 | 3883 | (FH39_SRVC_CHNL), 0x0); |
5d49f498 | 3884 | iwl_release_nic_access(priv); |
b481de9c ZY |
3885 | } |
3886 | handled |= CSR_INT_BIT_FH_TX; | |
3887 | } | |
3888 | ||
3889 | if (inta & ~handled) | |
15b1687c | 3890 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
b481de9c ZY |
3891 | |
3892 | if (inta & ~CSR_INI_SET_MASK) { | |
39aadf8c | 3893 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
b481de9c | 3894 | inta & ~CSR_INI_SET_MASK); |
39aadf8c | 3895 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
3896 | } |
3897 | ||
3898 | /* Re-enable all interrupts */ | |
0359facc MA |
3899 | /* only Re-enable if disabled by irq */ |
3900 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
3901 | iwl3945_enable_interrupts(priv); | |
b481de9c | 3902 | |
c8b0e6e1 | 3903 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 3904 | if (priv->debug_level & (IWL_DL_ISR)) { |
5d49f498 AK |
3905 | inta = iwl_read32(priv, CSR_INT); |
3906 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
3907 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
3908 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
3909 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
3910 | } | |
3911 | #endif | |
3912 | spin_unlock_irqrestore(&priv->lock, flags); | |
3913 | } | |
3914 | ||
bb8c093b | 3915 | static irqreturn_t iwl3945_isr(int irq, void *data) |
b481de9c | 3916 | { |
4a8a4322 | 3917 | struct iwl_priv *priv = data; |
b481de9c ZY |
3918 | u32 inta, inta_mask; |
3919 | u32 inta_fh; | |
3920 | if (!priv) | |
3921 | return IRQ_NONE; | |
3922 | ||
3923 | spin_lock(&priv->lock); | |
3924 | ||
3925 | /* Disable (but don't clear!) interrupts here to avoid | |
3926 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
3927 | * If we have something to service, the tasklet will re-enable ints. | |
3928 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
5d49f498 AK |
3929 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
3930 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
3931 | |
3932 | /* Discover which interrupts are active/pending */ | |
5d49f498 AK |
3933 | inta = iwl_read32(priv, CSR_INT); |
3934 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
3935 | |
3936 | /* Ignore interrupt if there's nothing in NIC to service. | |
3937 | * This may be due to IRQ shared with another device, | |
3938 | * or due to sporadic interrupts thrown from our NIC. */ | |
3939 | if (!inta && !inta_fh) { | |
3940 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
3941 | goto none; | |
3942 | } | |
3943 | ||
3944 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
3945 | /* Hardware disappeared */ | |
39aadf8c | 3946 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); |
cb4da1a3 | 3947 | goto unplugged; |
b481de9c ZY |
3948 | } |
3949 | ||
3950 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
3951 | inta, inta_mask, inta_fh); | |
3952 | ||
25c03d8e JP |
3953 | inta &= ~CSR_INT_BIT_SCD; |
3954 | ||
bb8c093b | 3955 | /* iwl3945_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
3956 | if (likely(inta || inta_fh)) |
3957 | tasklet_schedule(&priv->irq_tasklet); | |
cb4da1a3 | 3958 | unplugged: |
b481de9c ZY |
3959 | spin_unlock(&priv->lock); |
3960 | ||
3961 | return IRQ_HANDLED; | |
3962 | ||
3963 | none: | |
3964 | /* re-enable interrupts here since we don't have anything to service. */ | |
0359facc MA |
3965 | /* only Re-enable if disabled by irq */ |
3966 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
3967 | iwl3945_enable_interrupts(priv); | |
b481de9c ZY |
3968 | spin_unlock(&priv->lock); |
3969 | return IRQ_NONE; | |
3970 | } | |
3971 | ||
3972 | /************************** EEPROM BANDS **************************** | |
3973 | * | |
bb8c093b | 3974 | * The iwl3945_eeprom_band definitions below provide the mapping from the |
b481de9c ZY |
3975 | * EEPROM contents to the specific channel number supported for each |
3976 | * band. | |
3977 | * | |
f2c7e521 | 3978 | * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3 |
b481de9c ZY |
3979 | * definition below maps to physical channel 42 in the 5.2GHz spectrum. |
3980 | * The specific geography and calibration information for that channel | |
3981 | * is contained in the eeprom map itself. | |
3982 | * | |
3983 | * During init, we copy the eeprom information and channel map | |
3984 | * information into priv->channel_info_24/52 and priv->channel_map_24/52 | |
3985 | * | |
3986 | * channel_map_24/52 provides the index in the channel_info array for a | |
3987 | * given channel. We have to have two separate maps as there is channel | |
3988 | * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and | |
3989 | * band_2 | |
3990 | * | |
3991 | * A value of 0xff stored in the channel_map indicates that the channel | |
3992 | * is not supported by the hardware at all. | |
3993 | * | |
3994 | * A value of 0xfe in the channel_map indicates that the channel is not | |
3995 | * valid for Tx with the current hardware. This means that | |
3996 | * while the system can tune and receive on a given channel, it may not | |
3997 | * be able to associate or transmit any frames on that | |
3998 | * channel. There is no corresponding channel information for that | |
3999 | * entry. | |
4000 | * | |
4001 | *********************************************************************/ | |
4002 | ||
4003 | /* 2.4 GHz */ | |
bb8c093b | 4004 | static const u8 iwl3945_eeprom_band_1[14] = { |
b481de9c ZY |
4005 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 |
4006 | }; | |
4007 | ||
4008 | /* 5.2 GHz bands */ | |
9fbab516 | 4009 | static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */ |
b481de9c ZY |
4010 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 |
4011 | }; | |
4012 | ||
9fbab516 | 4013 | static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */ |
b481de9c ZY |
4014 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 |
4015 | }; | |
4016 | ||
bb8c093b | 4017 | static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */ |
b481de9c ZY |
4018 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 |
4019 | }; | |
4020 | ||
bb8c093b | 4021 | static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */ |
b481de9c ZY |
4022 | 145, 149, 153, 157, 161, 165 |
4023 | }; | |
4024 | ||
4a8a4322 | 4025 | static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band, |
b481de9c | 4026 | int *eeprom_ch_count, |
0f741d99 | 4027 | const struct iwl_eeprom_channel |
b481de9c ZY |
4028 | **eeprom_ch_info, |
4029 | const u8 **eeprom_ch_index) | |
4030 | { | |
4031 | switch (band) { | |
4032 | case 1: /* 2.4GHz band */ | |
bb8c093b | 4033 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1); |
f2c7e521 | 4034 | *eeprom_ch_info = priv->eeprom39.band_1_channels; |
bb8c093b | 4035 | *eeprom_ch_index = iwl3945_eeprom_band_1; |
b481de9c | 4036 | break; |
9fbab516 | 4037 | case 2: /* 4.9GHz band */ |
bb8c093b | 4038 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2); |
f2c7e521 | 4039 | *eeprom_ch_info = priv->eeprom39.band_2_channels; |
bb8c093b | 4040 | *eeprom_ch_index = iwl3945_eeprom_band_2; |
b481de9c ZY |
4041 | break; |
4042 | case 3: /* 5.2GHz band */ | |
bb8c093b | 4043 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3); |
f2c7e521 | 4044 | *eeprom_ch_info = priv->eeprom39.band_3_channels; |
bb8c093b | 4045 | *eeprom_ch_index = iwl3945_eeprom_band_3; |
b481de9c | 4046 | break; |
9fbab516 | 4047 | case 4: /* 5.5GHz band */ |
bb8c093b | 4048 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4); |
f2c7e521 | 4049 | *eeprom_ch_info = priv->eeprom39.band_4_channels; |
bb8c093b | 4050 | *eeprom_ch_index = iwl3945_eeprom_band_4; |
b481de9c | 4051 | break; |
9fbab516 | 4052 | case 5: /* 5.7GHz band */ |
bb8c093b | 4053 | *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5); |
f2c7e521 | 4054 | *eeprom_ch_info = priv->eeprom39.band_5_channels; |
bb8c093b | 4055 | *eeprom_ch_index = iwl3945_eeprom_band_5; |
b481de9c ZY |
4056 | break; |
4057 | default: | |
4058 | BUG(); | |
4059 | return; | |
4060 | } | |
4061 | } | |
4062 | ||
6440adb5 BC |
4063 | /** |
4064 | * iwl3945_get_channel_info - Find driver's private channel info | |
4065 | * | |
4066 | * Based on band and channel number. | |
4067 | */ | |
d20b3c65 | 4068 | const struct iwl_channel_info * |
4a8a4322 | 4069 | iwl3945_get_channel_info(const struct iwl_priv *priv, |
d20b3c65 | 4070 | enum ieee80211_band band, u16 channel) |
b481de9c ZY |
4071 | { |
4072 | int i; | |
4073 | ||
8318d78a JB |
4074 | switch (band) { |
4075 | case IEEE80211_BAND_5GHZ: | |
b481de9c ZY |
4076 | for (i = 14; i < priv->channel_count; i++) { |
4077 | if (priv->channel_info[i].channel == channel) | |
4078 | return &priv->channel_info[i]; | |
4079 | } | |
4080 | break; | |
4081 | ||
8318d78a | 4082 | case IEEE80211_BAND_2GHZ: |
b481de9c ZY |
4083 | if (channel >= 1 && channel <= 14) |
4084 | return &priv->channel_info[channel - 1]; | |
4085 | break; | |
8318d78a JB |
4086 | case IEEE80211_NUM_BANDS: |
4087 | WARN_ON(1); | |
b481de9c ZY |
4088 | } |
4089 | ||
4090 | return NULL; | |
4091 | } | |
4092 | ||
4093 | #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \ | |
4094 | ? # x " " : "") | |
4095 | ||
6440adb5 BC |
4096 | /** |
4097 | * iwl3945_init_channel_map - Set up driver's info for all possible channels | |
4098 | */ | |
4a8a4322 | 4099 | static int iwl3945_init_channel_map(struct iwl_priv *priv) |
b481de9c ZY |
4100 | { |
4101 | int eeprom_ch_count = 0; | |
4102 | const u8 *eeprom_ch_index = NULL; | |
0f741d99 | 4103 | const struct iwl_eeprom_channel *eeprom_ch_info = NULL; |
b481de9c | 4104 | int band, ch; |
d20b3c65 | 4105 | struct iwl_channel_info *ch_info; |
b481de9c ZY |
4106 | |
4107 | if (priv->channel_count) { | |
4108 | IWL_DEBUG_INFO("Channel map already initialized.\n"); | |
4109 | return 0; | |
4110 | } | |
4111 | ||
f2c7e521 | 4112 | if (priv->eeprom39.version < 0x2f) { |
39aadf8c | 4113 | IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n", |
f2c7e521 | 4114 | priv->eeprom39.version); |
b481de9c ZY |
4115 | return -EINVAL; |
4116 | } | |
4117 | ||
4118 | IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n"); | |
4119 | ||
4120 | priv->channel_count = | |
bb8c093b CH |
4121 | ARRAY_SIZE(iwl3945_eeprom_band_1) + |
4122 | ARRAY_SIZE(iwl3945_eeprom_band_2) + | |
4123 | ARRAY_SIZE(iwl3945_eeprom_band_3) + | |
4124 | ARRAY_SIZE(iwl3945_eeprom_band_4) + | |
4125 | ARRAY_SIZE(iwl3945_eeprom_band_5); | |
b481de9c ZY |
4126 | |
4127 | IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count); | |
4128 | ||
d20b3c65 | 4129 | priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) * |
b481de9c ZY |
4130 | priv->channel_count, GFP_KERNEL); |
4131 | if (!priv->channel_info) { | |
15b1687c | 4132 | IWL_ERR(priv, "Could not allocate channel_info\n"); |
b481de9c ZY |
4133 | priv->channel_count = 0; |
4134 | return -ENOMEM; | |
4135 | } | |
4136 | ||
4137 | ch_info = priv->channel_info; | |
4138 | ||
4139 | /* Loop through the 5 EEPROM bands adding them in order to the | |
4140 | * channel map we maintain (that contains additional information than | |
4141 | * what just in the EEPROM) */ | |
4142 | for (band = 1; band <= 5; band++) { | |
4143 | ||
bb8c093b | 4144 | iwl3945_init_band_reference(priv, band, &eeprom_ch_count, |
b481de9c ZY |
4145 | &eeprom_ch_info, &eeprom_ch_index); |
4146 | ||
4147 | /* Loop through each band adding each of the channels */ | |
4148 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
4149 | ch_info->channel = eeprom_ch_index[ch]; | |
8318d78a JB |
4150 | ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ : |
4151 | IEEE80211_BAND_5GHZ; | |
b481de9c ZY |
4152 | |
4153 | /* permanently store EEPROM's channel regulatory flags | |
4154 | * and max power in channel info database. */ | |
4155 | ch_info->eeprom = eeprom_ch_info[ch]; | |
4156 | ||
4157 | /* Copy the run-time flags so they are there even on | |
4158 | * invalid channels */ | |
4159 | ch_info->flags = eeprom_ch_info[ch].flags; | |
4160 | ||
4161 | if (!(is_channel_valid(ch_info))) { | |
4162 | IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - " | |
4163 | "No traffic\n", | |
4164 | ch_info->channel, | |
4165 | ch_info->flags, | |
4166 | is_channel_a_band(ch_info) ? | |
4167 | "5.2" : "2.4"); | |
4168 | ch_info++; | |
4169 | continue; | |
4170 | } | |
4171 | ||
4172 | /* Initialize regulatory-based run-time data */ | |
4173 | ch_info->max_power_avg = ch_info->curr_txpow = | |
4174 | eeprom_ch_info[ch].max_power_avg; | |
4175 | ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; | |
4176 | ch_info->min_power = 0; | |
4177 | ||
fe7c4040 | 4178 | IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x" |
b481de9c ZY |
4179 | " %ddBm): Ad-Hoc %ssupported\n", |
4180 | ch_info->channel, | |
4181 | is_channel_a_band(ch_info) ? | |
4182 | "5.2" : "2.4", | |
8211ef78 | 4183 | CHECK_AND_PRINT(VALID), |
b481de9c ZY |
4184 | CHECK_AND_PRINT(IBSS), |
4185 | CHECK_AND_PRINT(ACTIVE), | |
4186 | CHECK_AND_PRINT(RADAR), | |
4187 | CHECK_AND_PRINT(WIDE), | |
b481de9c ZY |
4188 | CHECK_AND_PRINT(DFS), |
4189 | eeprom_ch_info[ch].flags, | |
4190 | eeprom_ch_info[ch].max_power_avg, | |
4191 | ((eeprom_ch_info[ch]. | |
4192 | flags & EEPROM_CHANNEL_IBSS) | |
4193 | && !(eeprom_ch_info[ch]. | |
4194 | flags & EEPROM_CHANNEL_RADAR)) | |
4195 | ? "" : "not "); | |
4196 | ||
4197 | /* Set the user_txpower_limit to the highest power | |
4198 | * supported by any channel */ | |
4199 | if (eeprom_ch_info[ch].max_power_avg > | |
4200 | priv->user_txpower_limit) | |
4201 | priv->user_txpower_limit = | |
4202 | eeprom_ch_info[ch].max_power_avg; | |
4203 | ||
4204 | ch_info++; | |
4205 | } | |
4206 | } | |
4207 | ||
6440adb5 | 4208 | /* Set up txpower settings in driver for all channels */ |
b481de9c ZY |
4209 | if (iwl3945_txpower_set_from_eeprom(priv)) |
4210 | return -EIO; | |
4211 | ||
4212 | return 0; | |
4213 | } | |
4214 | ||
849e0dce RC |
4215 | /* |
4216 | * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map | |
4217 | */ | |
4a8a4322 | 4218 | static void iwl3945_free_channel_map(struct iwl_priv *priv) |
849e0dce RC |
4219 | { |
4220 | kfree(priv->channel_info); | |
4221 | priv->channel_count = 0; | |
4222 | } | |
4223 | ||
b481de9c ZY |
4224 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after |
4225 | * sending probe req. This should be set long enough to hear probe responses | |
4226 | * from more than one AP. */ | |
f9340520 AK |
4227 | #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ |
4228 | #define IWL_ACTIVE_DWELL_TIME_52 (20) | |
4229 | ||
4230 | #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3) | |
4231 | #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2) | |
b481de9c ZY |
4232 | |
4233 | /* For faster active scanning, scan will move to the next channel if fewer than | |
4234 | * PLCP_QUIET_THRESH packets are heard on this channel within | |
4235 | * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell | |
4236 | * time if it's a quiet channel (nothing responded to our probe, and there's | |
4237 | * no other traffic). | |
4238 | * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ | |
4239 | #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */ | |
f9340520 | 4240 | #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */ |
b481de9c ZY |
4241 | |
4242 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
4243 | * Must be set longer than active dwell time. | |
4244 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
4245 | #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ | |
4246 | #define IWL_PASSIVE_DWELL_TIME_52 (10) | |
4247 | #define IWL_PASSIVE_DWELL_BASE (100) | |
4248 | #define IWL_CHANNEL_TUNE_TIME 5 | |
4249 | ||
e720ce9d | 4250 | #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1))) |
f9340520 | 4251 | |
4a8a4322 | 4252 | static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv, |
f9340520 AK |
4253 | enum ieee80211_band band, |
4254 | u8 n_probes) | |
b481de9c | 4255 | { |
8318d78a | 4256 | if (band == IEEE80211_BAND_5GHZ) |
f9340520 AK |
4257 | return IWL_ACTIVE_DWELL_TIME_52 + |
4258 | IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1); | |
b481de9c | 4259 | else |
f9340520 AK |
4260 | return IWL_ACTIVE_DWELL_TIME_24 + |
4261 | IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1); | |
b481de9c ZY |
4262 | } |
4263 | ||
4a8a4322 | 4264 | static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv, |
8318d78a | 4265 | enum ieee80211_band band) |
b481de9c | 4266 | { |
8318d78a | 4267 | u16 passive = (band == IEEE80211_BAND_2GHZ) ? |
b481de9c ZY |
4268 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 : |
4269 | IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52; | |
4270 | ||
bb8c093b | 4271 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
4272 | /* If we're associated, we clamp the maximum passive |
4273 | * dwell time to be 98% of the beacon interval (minus | |
4274 | * 2 * channel tune time) */ | |
4275 | passive = priv->beacon_int; | |
4276 | if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive) | |
4277 | passive = IWL_PASSIVE_DWELL_BASE; | |
4278 | passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2; | |
4279 | } | |
4280 | ||
b481de9c ZY |
4281 | return passive; |
4282 | } | |
4283 | ||
4a8a4322 | 4284 | static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 4285 | enum ieee80211_band band, |
f9340520 | 4286 | u8 is_active, u8 n_probes, |
bb8c093b | 4287 | struct iwl3945_scan_channel *scan_ch) |
b481de9c ZY |
4288 | { |
4289 | const struct ieee80211_channel *channels = NULL; | |
8318d78a | 4290 | const struct ieee80211_supported_band *sband; |
d20b3c65 | 4291 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
4292 | u16 passive_dwell = 0; |
4293 | u16 active_dwell = 0; | |
4294 | int added, i; | |
4295 | ||
cbba18c6 | 4296 | sband = iwl_get_hw_mode(priv, band); |
8318d78a | 4297 | if (!sband) |
b481de9c ZY |
4298 | return 0; |
4299 | ||
8318d78a | 4300 | channels = sband->channels; |
b481de9c | 4301 | |
f9340520 | 4302 | active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes); |
8318d78a | 4303 | passive_dwell = iwl3945_get_passive_dwell_time(priv, band); |
b481de9c | 4304 | |
8f4807a1 AK |
4305 | if (passive_dwell <= active_dwell) |
4306 | passive_dwell = active_dwell + 1; | |
4307 | ||
8318d78a | 4308 | for (i = 0, added = 0; i < sband->n_channels; i++) { |
182e2e66 JB |
4309 | if (channels[i].flags & IEEE80211_CHAN_DISABLED) |
4310 | continue; | |
4311 | ||
8318d78a | 4312 | scan_ch->channel = channels[i].hw_value; |
b481de9c | 4313 | |
8318d78a | 4314 | ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 4315 | if (!is_channel_valid(ch_info)) { |
66b5004d | 4316 | IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n", |
b481de9c ZY |
4317 | scan_ch->channel); |
4318 | continue; | |
4319 | } | |
4320 | ||
011a0330 AK |
4321 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
4322 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
4323 | /* If passive , set up for auto-switch | |
4324 | * and use long active_dwell time. | |
4325 | */ | |
b481de9c | 4326 | if (!is_active || is_channel_passive(ch_info) || |
011a0330 | 4327 | (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
b481de9c | 4328 | scan_ch->type = 0; /* passive */ |
011a0330 AK |
4329 | if (IWL_UCODE_API(priv->ucode_ver) == 1) |
4330 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); | |
4331 | } else { | |
b481de9c | 4332 | scan_ch->type = 1; /* active */ |
011a0330 | 4333 | } |
b481de9c | 4334 | |
011a0330 AK |
4335 | /* Set direct probe bits. These may be used both for active |
4336 | * scan channels (probes gets sent right away), | |
4337 | * or for passive channels (probes get se sent only after | |
4338 | * hearing clear Rx packet).*/ | |
4339 | if (IWL_UCODE_API(priv->ucode_ver) >= 2) { | |
4340 | if (n_probes) | |
4341 | scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes); | |
4342 | } else { | |
4343 | /* uCode v1 does not allow setting direct probe bits on | |
4344 | * passive channel. */ | |
4345 | if ((scan_ch->type & 1) && n_probes) | |
4346 | scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes); | |
4347 | } | |
b481de9c | 4348 | |
9fbab516 | 4349 | /* Set txpower levels to defaults */ |
b481de9c ZY |
4350 | scan_ch->tpc.dsp_atten = 110; |
4351 | /* scan_pwr_info->tpc.dsp_atten; */ | |
4352 | ||
4353 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 4354 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4355 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
4356 | else { | |
4357 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
4358 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 4359 | * power level: |
8a1b0245 | 4360 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
4361 | */ |
4362 | } | |
4363 | ||
4364 | IWL_DEBUG_SCAN("Scanning %d [%s %d]\n", | |
4365 | scan_ch->channel, | |
4366 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
4367 | (scan_ch->type & 1) ? | |
4368 | active_dwell : passive_dwell); | |
4369 | ||
4370 | scan_ch++; | |
4371 | added++; | |
4372 | } | |
4373 | ||
4374 | IWL_DEBUG_SCAN("total channels to scan %d \n", added); | |
4375 | return added; | |
4376 | } | |
4377 | ||
4a8a4322 | 4378 | static void iwl3945_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
4379 | struct ieee80211_rate *rates) |
4380 | { | |
4381 | int i; | |
4382 | ||
4383 | for (i = 0; i < IWL_RATE_COUNT; i++) { | |
8318d78a JB |
4384 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
4385 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
4386 | rates[i].hw_value_short = i; | |
4387 | rates[i].flags = 0; | |
d9829a67 | 4388 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
b481de9c | 4389 | /* |
8318d78a | 4390 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 4391 | */ |
bb8c093b | 4392 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 4393 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 4394 | } |
b481de9c ZY |
4395 | } |
4396 | } | |
4397 | ||
4398 | /** | |
bb8c093b | 4399 | * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom |
b481de9c | 4400 | */ |
4a8a4322 | 4401 | static int iwl3945_init_geos(struct iwl_priv *priv) |
b481de9c | 4402 | { |
d20b3c65 | 4403 | struct iwl_channel_info *ch; |
8211ef78 | 4404 | struct ieee80211_supported_band *sband; |
b481de9c ZY |
4405 | struct ieee80211_channel *channels; |
4406 | struct ieee80211_channel *geo_ch; | |
4407 | struct ieee80211_rate *rates; | |
4408 | int i = 0; | |
b481de9c | 4409 | |
8318d78a JB |
4410 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
4411 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
b481de9c ZY |
4412 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
4413 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4414 | return 0; | |
4415 | } | |
4416 | ||
b481de9c ZY |
4417 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
4418 | priv->channel_count, GFP_KERNEL); | |
8318d78a | 4419 | if (!channels) |
b481de9c | 4420 | return -ENOMEM; |
b481de9c | 4421 | |
8211ef78 | 4422 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
b481de9c ZY |
4423 | GFP_KERNEL); |
4424 | if (!rates) { | |
b481de9c ZY |
4425 | kfree(channels); |
4426 | return -ENOMEM; | |
4427 | } | |
4428 | ||
b481de9c | 4429 | /* 5.2GHz channels start after the 2.4GHz channels */ |
8211ef78 TW |
4430 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
4431 | sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)]; | |
4432 | /* just OFDM */ | |
4433 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; | |
4434 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; | |
4435 | ||
4436 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; | |
4437 | sband->channels = channels; | |
4438 | /* OFDM & CCK */ | |
4439 | sband->bitrates = rates; | |
4440 | sband->n_bitrates = IWL_RATE_COUNT; | |
b481de9c ZY |
4441 | |
4442 | priv->ieee_channels = channels; | |
4443 | priv->ieee_rates = rates; | |
4444 | ||
bb8c093b | 4445 | iwl3945_init_hw_rates(priv, rates); |
b481de9c | 4446 | |
8211ef78 | 4447 | for (i = 0; i < priv->channel_count; i++) { |
b481de9c ZY |
4448 | ch = &priv->channel_info[i]; |
4449 | ||
8211ef78 TW |
4450 | /* FIXME: might be removed if scan is OK*/ |
4451 | if (!is_channel_valid(ch)) | |
b481de9c | 4452 | continue; |
b481de9c ZY |
4453 | |
4454 | if (is_channel_a_band(ch)) | |
8211ef78 | 4455 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
8318d78a | 4456 | else |
8211ef78 | 4457 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
b481de9c | 4458 | |
8211ef78 TW |
4459 | geo_ch = &sband->channels[sband->n_channels++]; |
4460 | ||
4461 | geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel); | |
8318d78a JB |
4462 | geo_ch->max_power = ch->max_power_avg; |
4463 | geo_ch->max_antenna_gain = 0xff; | |
7b72304d | 4464 | geo_ch->hw_value = ch->channel; |
b481de9c ZY |
4465 | |
4466 | if (is_channel_valid(ch)) { | |
8318d78a JB |
4467 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
4468 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
b481de9c | 4469 | |
8318d78a JB |
4470 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
4471 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
b481de9c ZY |
4472 | |
4473 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
8318d78a | 4474 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
b481de9c ZY |
4475 | |
4476 | if (ch->max_power_avg > priv->max_channel_txpower_limit) | |
4477 | priv->max_channel_txpower_limit = | |
4478 | ch->max_power_avg; | |
8211ef78 | 4479 | } else { |
8318d78a | 4480 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
8211ef78 TW |
4481 | } |
4482 | ||
4483 | /* Save flags for reg domain usage */ | |
4484 | geo_ch->orig_flags = geo_ch->flags; | |
4485 | ||
4486 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", | |
4487 | ch->channel, geo_ch->center_freq, | |
4488 | is_channel_a_band(ch) ? "5.2" : "2.4", | |
4489 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? | |
4490 | "restricted" : "valid", | |
4491 | geo_ch->flags); | |
b481de9c ZY |
4492 | } |
4493 | ||
82b9a121 TW |
4494 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
4495 | priv->cfg->sku & IWL_SKU_A) { | |
978785a3 TW |
4496 | IWL_INFO(priv, "Incorrectly detected BG card as ABG. " |
4497 | "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n", | |
4498 | priv->pci_dev->device, priv->pci_dev->subsystem_device); | |
82b9a121 | 4499 | priv->cfg->sku &= ~IWL_SKU_A; |
b481de9c ZY |
4500 | } |
4501 | ||
978785a3 | 4502 | IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
8318d78a JB |
4503 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
4504 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); | |
b481de9c | 4505 | |
e0e0a67e JL |
4506 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
4507 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
4508 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
4509 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
4510 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
4511 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
b481de9c | 4512 | |
b481de9c ZY |
4513 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
4514 | ||
4515 | return 0; | |
4516 | } | |
4517 | ||
849e0dce RC |
4518 | /* |
4519 | * iwl3945_free_geos - undo allocations in iwl3945_init_geos | |
4520 | */ | |
4a8a4322 | 4521 | static void iwl3945_free_geos(struct iwl_priv *priv) |
849e0dce | 4522 | { |
849e0dce RC |
4523 | kfree(priv->ieee_channels); |
4524 | kfree(priv->ieee_rates); | |
4525 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); | |
4526 | } | |
4527 | ||
b481de9c ZY |
4528 | /****************************************************************************** |
4529 | * | |
4530 | * uCode download functions | |
4531 | * | |
4532 | ******************************************************************************/ | |
4533 | ||
4a8a4322 | 4534 | static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 4535 | { |
98c92211 TW |
4536 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
4537 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
4538 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
4539 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
4540 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
4541 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
4542 | } |
4543 | ||
4544 | /** | |
bb8c093b | 4545 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
4546 | * looking at all data. |
4547 | */ | |
4a8a4322 | 4548 | static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
4549 | { |
4550 | u32 val; | |
4551 | u32 save_len = len; | |
4552 | int rc = 0; | |
4553 | u32 errcnt; | |
4554 | ||
4555 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
4556 | ||
5d49f498 | 4557 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4558 | if (rc) |
4559 | return rc; | |
4560 | ||
5d49f498 | 4561 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 4562 | IWL39_RTC_INST_LOWER_BOUND); |
b481de9c ZY |
4563 | |
4564 | errcnt = 0; | |
4565 | for (; len > 0; len -= sizeof(u32), image++) { | |
4566 | /* read data comes through single port, auto-incr addr */ | |
4567 | /* NOTE: Use the debugless read so we don't flood kernel log | |
4568 | * if IWL_DL_IO is set */ | |
5d49f498 | 4569 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c | 4570 | if (val != le32_to_cpu(*image)) { |
15b1687c | 4571 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
4572 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
4573 | save_len - len, val, le32_to_cpu(*image)); | |
4574 | rc = -EIO; | |
4575 | errcnt++; | |
4576 | if (errcnt >= 20) | |
4577 | break; | |
4578 | } | |
4579 | } | |
4580 | ||
5d49f498 | 4581 | iwl_release_nic_access(priv); |
b481de9c ZY |
4582 | |
4583 | if (!errcnt) | |
bc434dd2 | 4584 | IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n"); |
b481de9c ZY |
4585 | |
4586 | return rc; | |
4587 | } | |
4588 | ||
4589 | ||
4590 | /** | |
bb8c093b | 4591 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
4592 | * using sample data 100 bytes apart. If these sample points are good, |
4593 | * it's a pretty good bet that everything between them is good, too. | |
4594 | */ | |
4a8a4322 | 4595 | static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
4596 | { |
4597 | u32 val; | |
4598 | int rc = 0; | |
4599 | u32 errcnt = 0; | |
4600 | u32 i; | |
4601 | ||
4602 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); | |
4603 | ||
5d49f498 | 4604 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4605 | if (rc) |
4606 | return rc; | |
4607 | ||
4608 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
4609 | /* read data comes through single port, auto-incr addr */ | |
4610 | /* NOTE: Use the debugless read so we don't flood kernel log | |
4611 | * if IWL_DL_IO is set */ | |
5d49f498 | 4612 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 4613 | i + IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 4614 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
4615 | if (val != le32_to_cpu(*image)) { |
4616 | #if 0 /* Enable this if you want to see details */ | |
15b1687c | 4617 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
4618 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
4619 | i, val, *image); | |
4620 | #endif | |
4621 | rc = -EIO; | |
4622 | errcnt++; | |
4623 | if (errcnt >= 3) | |
4624 | break; | |
4625 | } | |
4626 | } | |
4627 | ||
5d49f498 | 4628 | iwl_release_nic_access(priv); |
b481de9c ZY |
4629 | |
4630 | return rc; | |
4631 | } | |
4632 | ||
4633 | ||
4634 | /** | |
bb8c093b | 4635 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
4636 | * and verify its contents |
4637 | */ | |
4a8a4322 | 4638 | static int iwl3945_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
4639 | { |
4640 | __le32 *image; | |
4641 | u32 len; | |
4642 | int rc = 0; | |
4643 | ||
4644 | /* Try bootstrap */ | |
4645 | image = (__le32 *)priv->ucode_boot.v_addr; | |
4646 | len = priv->ucode_boot.len; | |
bb8c093b | 4647 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
4648 | if (rc == 0) { |
4649 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
4650 | return 0; | |
4651 | } | |
4652 | ||
4653 | /* Try initialize */ | |
4654 | image = (__le32 *)priv->ucode_init.v_addr; | |
4655 | len = priv->ucode_init.len; | |
bb8c093b | 4656 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
4657 | if (rc == 0) { |
4658 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); | |
4659 | return 0; | |
4660 | } | |
4661 | ||
4662 | /* Try runtime/protocol */ | |
4663 | image = (__le32 *)priv->ucode_code.v_addr; | |
4664 | len = priv->ucode_code.len; | |
bb8c093b | 4665 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c ZY |
4666 | if (rc == 0) { |
4667 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); | |
4668 | return 0; | |
4669 | } | |
4670 | ||
15b1687c | 4671 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b481de9c | 4672 | |
9fbab516 BC |
4673 | /* Since nothing seems to match, show first several data entries in |
4674 | * instruction SRAM, so maybe visual inspection will give a clue. | |
4675 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
4676 | image = (__le32 *)priv->ucode_boot.v_addr; |
4677 | len = priv->ucode_boot.len; | |
bb8c093b | 4678 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
4679 | |
4680 | return rc; | |
4681 | } | |
4682 | ||
4a8a4322 | 4683 | static void iwl3945_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
4684 | { |
4685 | /* Remove all resets to allow NIC to operate */ | |
5d49f498 | 4686 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
4687 | } |
4688 | ||
4689 | /** | |
bb8c093b | 4690 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
4691 | * |
4692 | * Copy into buffers for card to fetch via bus-mastering | |
4693 | */ | |
4a8a4322 | 4694 | static int iwl3945_read_ucode(struct iwl_priv *priv) |
b481de9c | 4695 | { |
a78fe754 | 4696 | struct iwl_ucode *ucode; |
a0987a8d | 4697 | int ret = -EINVAL, index; |
b481de9c ZY |
4698 | const struct firmware *ucode_raw; |
4699 | /* firmware file name contains uCode/driver compatibility version */ | |
a0987a8d RC |
4700 | const char *name_pre = priv->cfg->fw_name_pre; |
4701 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
4702 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
4703 | char buf[25]; | |
b481de9c ZY |
4704 | u8 *src; |
4705 | size_t len; | |
a0987a8d | 4706 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
4707 | |
4708 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
4709 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
4710 | for (index = api_max; index >= api_min; index--) { |
4711 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
4712 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
4713 | if (ret < 0) { | |
15b1687c | 4714 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
4715 | buf, ret); |
4716 | if (ret == -ENOENT) | |
4717 | continue; | |
4718 | else | |
4719 | goto error; | |
4720 | } else { | |
4721 | if (index < api_max) | |
15b1687c WT |
4722 | IWL_ERR(priv, "Loaded firmware %s, " |
4723 | "which is deprecated. " | |
4724 | " Please use API v%u instead.\n", | |
a0987a8d RC |
4725 | buf, api_max); |
4726 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", | |
4727 | buf, ucode_raw->size); | |
4728 | break; | |
4729 | } | |
b481de9c ZY |
4730 | } |
4731 | ||
a0987a8d RC |
4732 | if (ret < 0) |
4733 | goto error; | |
b481de9c ZY |
4734 | |
4735 | /* Make sure that we got at least our header! */ | |
4736 | if (ucode_raw->size < sizeof(*ucode)) { | |
15b1687c | 4737 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 4738 | ret = -EINVAL; |
b481de9c ZY |
4739 | goto err_release; |
4740 | } | |
4741 | ||
4742 | /* Data from ucode file: header followed by uCode images */ | |
4743 | ucode = (void *)ucode_raw->data; | |
4744 | ||
c02b3acd | 4745 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 4746 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
b481de9c ZY |
4747 | inst_size = le32_to_cpu(ucode->inst_size); |
4748 | data_size = le32_to_cpu(ucode->data_size); | |
4749 | init_size = le32_to_cpu(ucode->init_size); | |
4750 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
4751 | boot_size = le32_to_cpu(ucode->boot_size); | |
4752 | ||
a0987a8d RC |
4753 | /* api_ver should match the api version forming part of the |
4754 | * firmware filename ... but we don't check for that and only rely | |
4755 | * on the API version read from firware header from here on forward */ | |
4756 | ||
4757 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 4758 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
4759 | "Driver supports v%u, firmware is v%u.\n", |
4760 | api_max, api_ver); | |
4761 | priv->ucode_ver = 0; | |
4762 | ret = -EINVAL; | |
4763 | goto err_release; | |
4764 | } | |
4765 | if (api_ver != api_max) | |
15b1687c | 4766 | IWL_ERR(priv, "Firmware has old API version. Expected %u, " |
a0987a8d RC |
4767 | "got %u. New firmware can be obtained " |
4768 | "from http://www.intellinuxwireless.org.\n", | |
4769 | api_max, api_ver); | |
4770 | ||
978785a3 TW |
4771 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
4772 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
4773 | IWL_UCODE_MINOR(priv->ucode_ver), | |
4774 | IWL_UCODE_API(priv->ucode_ver), | |
4775 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
4776 | ||
a0987a8d RC |
4777 | IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n", |
4778 | priv->ucode_ver); | |
bc434dd2 IS |
4779 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size); |
4780 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size); | |
4781 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size); | |
4782 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size); | |
4783 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size); | |
b481de9c | 4784 | |
a0987a8d | 4785 | |
b481de9c ZY |
4786 | /* Verify size of file vs. image size info in file's header */ |
4787 | if (ucode_raw->size < sizeof(*ucode) + | |
4788 | inst_size + data_size + init_size + | |
4789 | init_data_size + boot_size) { | |
4790 | ||
4791 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
4792 | (int)ucode_raw->size); | |
90e759d1 | 4793 | ret = -EINVAL; |
b481de9c ZY |
4794 | goto err_release; |
4795 | } | |
4796 | ||
4797 | /* Verify that uCode images will fit in card's SRAM */ | |
250bdd21 | 4798 | if (inst_size > IWL39_MAX_INST_SIZE) { |
90e759d1 TW |
4799 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
4800 | inst_size); | |
4801 | ret = -EINVAL; | |
b481de9c ZY |
4802 | goto err_release; |
4803 | } | |
4804 | ||
250bdd21 | 4805 | if (data_size > IWL39_MAX_DATA_SIZE) { |
90e759d1 TW |
4806 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
4807 | data_size); | |
4808 | ret = -EINVAL; | |
b481de9c ZY |
4809 | goto err_release; |
4810 | } | |
250bdd21 | 4811 | if (init_size > IWL39_MAX_INST_SIZE) { |
90e759d1 TW |
4812 | IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n", |
4813 | init_size); | |
4814 | ret = -EINVAL; | |
b481de9c ZY |
4815 | goto err_release; |
4816 | } | |
250bdd21 | 4817 | if (init_data_size > IWL39_MAX_DATA_SIZE) { |
90e759d1 TW |
4818 | IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n", |
4819 | init_data_size); | |
4820 | ret = -EINVAL; | |
b481de9c ZY |
4821 | goto err_release; |
4822 | } | |
250bdd21 | 4823 | if (boot_size > IWL39_MAX_BSM_SIZE) { |
90e759d1 TW |
4824 | IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n", |
4825 | boot_size); | |
4826 | ret = -EINVAL; | |
b481de9c ZY |
4827 | goto err_release; |
4828 | } | |
4829 | ||
4830 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
4831 | ||
4832 | /* Runtime instructions and 2 copies of data: | |
4833 | * 1) unmodified from disk | |
4834 | * 2) backup cache for save/restore during power-downs */ | |
4835 | priv->ucode_code.len = inst_size; | |
98c92211 | 4836 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
4837 | |
4838 | priv->ucode_data.len = data_size; | |
98c92211 | 4839 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
4840 | |
4841 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 4842 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 4843 | |
90e759d1 TW |
4844 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
4845 | !priv->ucode_data_backup.v_addr) | |
4846 | goto err_pci_alloc; | |
b481de9c ZY |
4847 | |
4848 | /* Initialization instructions and data */ | |
90e759d1 TW |
4849 | if (init_size && init_data_size) { |
4850 | priv->ucode_init.len = init_size; | |
98c92211 | 4851 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
4852 | |
4853 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 4854 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
4855 | |
4856 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
4857 | goto err_pci_alloc; | |
4858 | } | |
b481de9c ZY |
4859 | |
4860 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
4861 | if (boot_size) { |
4862 | priv->ucode_boot.len = boot_size; | |
98c92211 | 4863 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 4864 | |
90e759d1 TW |
4865 | if (!priv->ucode_boot.v_addr) |
4866 | goto err_pci_alloc; | |
4867 | } | |
b481de9c ZY |
4868 | |
4869 | /* Copy images into buffers for card's bus-master reads ... */ | |
4870 | ||
4871 | /* Runtime instructions (first block of data in file) */ | |
4872 | src = &ucode->data[0]; | |
4873 | len = priv->ucode_code.len; | |
90e759d1 | 4874 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
4875 | memcpy(priv->ucode_code.v_addr, src, len); |
4876 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
4877 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
4878 | ||
4879 | /* Runtime data (2nd block) | |
bb8c093b | 4880 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
b481de9c ZY |
4881 | src = &ucode->data[inst_size]; |
4882 | len = priv->ucode_data.len; | |
90e759d1 | 4883 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
4884 | memcpy(priv->ucode_data.v_addr, src, len); |
4885 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
4886 | ||
4887 | /* Initialization instructions (3rd block) */ | |
4888 | if (init_size) { | |
4889 | src = &ucode->data[inst_size + data_size]; | |
4890 | len = priv->ucode_init.len; | |
90e759d1 TW |
4891 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
4892 | len); | |
b481de9c ZY |
4893 | memcpy(priv->ucode_init.v_addr, src, len); |
4894 | } | |
4895 | ||
4896 | /* Initialization data (4th block) */ | |
4897 | if (init_data_size) { | |
4898 | src = &ucode->data[inst_size + data_size + init_size]; | |
4899 | len = priv->ucode_init_data.len; | |
4900 | IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n", | |
4901 | (int)len); | |
4902 | memcpy(priv->ucode_init_data.v_addr, src, len); | |
4903 | } | |
4904 | ||
4905 | /* Bootstrap instructions (5th block) */ | |
4906 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
4907 | len = priv->ucode_boot.len; | |
4908 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n", | |
4909 | (int)len); | |
4910 | memcpy(priv->ucode_boot.v_addr, src, len); | |
4911 | ||
4912 | /* We have our copies now, allow OS release its copies */ | |
4913 | release_firmware(ucode_raw); | |
4914 | return 0; | |
4915 | ||
4916 | err_pci_alloc: | |
15b1687c | 4917 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 4918 | ret = -ENOMEM; |
bb8c093b | 4919 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
4920 | |
4921 | err_release: | |
4922 | release_firmware(ucode_raw); | |
4923 | ||
4924 | error: | |
90e759d1 | 4925 | return ret; |
b481de9c ZY |
4926 | } |
4927 | ||
4928 | ||
4929 | /** | |
bb8c093b | 4930 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
4931 | * |
4932 | * Tell initialization uCode where to find runtime uCode. | |
4933 | * | |
4934 | * BSM registers initially contain pointers to initialization uCode. | |
4935 | * We need to replace them to load runtime uCode inst and data, | |
4936 | * and to save runtime data when powering down. | |
4937 | */ | |
4a8a4322 | 4938 | static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
4939 | { |
4940 | dma_addr_t pinst; | |
4941 | dma_addr_t pdata; | |
4942 | int rc = 0; | |
4943 | unsigned long flags; | |
4944 | ||
4945 | /* bits 31:0 for 3945 */ | |
4946 | pinst = priv->ucode_code.p_addr; | |
4947 | pdata = priv->ucode_data_backup.p_addr; | |
4948 | ||
4949 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 4950 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
4951 | if (rc) { |
4952 | spin_unlock_irqrestore(&priv->lock, flags); | |
4953 | return rc; | |
4954 | } | |
4955 | ||
4956 | /* Tell bootstrap uCode where to find image to load */ | |
5d49f498 AK |
4957 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
4958 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
4959 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
4960 | priv->ucode_data.len); |
4961 | ||
a96a27f9 | 4962 | /* Inst byte count must be last to set up, bit 31 signals uCode |
b481de9c | 4963 | * that all new ptr/size info is in place */ |
5d49f498 | 4964 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
4965 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
4966 | ||
5d49f498 | 4967 | iwl_release_nic_access(priv); |
b481de9c ZY |
4968 | |
4969 | spin_unlock_irqrestore(&priv->lock, flags); | |
4970 | ||
4971 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
4972 | ||
4973 | return rc; | |
4974 | } | |
4975 | ||
4976 | /** | |
bb8c093b | 4977 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
4978 | * |
4979 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
4980 | * | |
b481de9c | 4981 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 4982 | */ |
4a8a4322 | 4983 | static void iwl3945_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
4984 | { |
4985 | /* Check alive response for "valid" sign from uCode */ | |
4986 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
4987 | /* We had an error bringing up the hardware, so take it | |
4988 | * all the way back down so we can try again */ | |
4989 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
4990 | goto restart; | |
4991 | } | |
4992 | ||
4993 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
4994 | * This is a paranoid check, because we would not have gotten the | |
4995 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 4996 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
4997 | /* Runtime instruction load was bad; |
4998 | * take it all the way back down so we can try again */ | |
4999 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
5000 | goto restart; | |
5001 | } | |
5002 | ||
5003 | /* Send pointers to protocol/runtime uCode image ... init code will | |
5004 | * load and launch runtime uCode, which will send us another "Alive" | |
5005 | * notification. */ | |
5006 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
bb8c093b | 5007 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
5008 | /* Runtime instruction load won't happen; |
5009 | * take it all the way back down so we can try again */ | |
5010 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
5011 | goto restart; | |
5012 | } | |
5013 | return; | |
5014 | ||
5015 | restart: | |
5016 | queue_work(priv->workqueue, &priv->restart); | |
5017 | } | |
5018 | ||
5019 | ||
9bdf5eca MA |
5020 | /* temporary */ |
5021 | static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, | |
5022 | struct sk_buff *skb); | |
5023 | ||
b481de9c | 5024 | /** |
bb8c093b | 5025 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 5026 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 5027 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 5028 | */ |
4a8a4322 | 5029 | static void iwl3945_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
5030 | { |
5031 | int rc = 0; | |
5032 | int thermal_spin = 0; | |
5033 | u32 rfkill; | |
5034 | ||
5035 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
5036 | ||
5037 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
5038 | /* We had an error bringing up the hardware, so take it | |
5039 | * all the way back down so we can try again */ | |
5040 | IWL_DEBUG_INFO("Alive failed.\n"); | |
5041 | goto restart; | |
5042 | } | |
5043 | ||
5044 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5045 | * This is a paranoid check, because we would not have gotten the | |
5046 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 5047 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
5048 | /* Runtime instruction load was bad; |
5049 | * take it all the way back down so we can try again */ | |
5050 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
5051 | goto restart; | |
5052 | } | |
5053 | ||
bb8c093b | 5054 | iwl3945_clear_stations_table(priv); |
b481de9c | 5055 | |
5d49f498 | 5056 | rc = iwl_grab_nic_access(priv); |
b481de9c | 5057 | if (rc) { |
39aadf8c | 5058 | IWL_WARN(priv, "Can not read RFKILL status from adapter\n"); |
b481de9c ZY |
5059 | return; |
5060 | } | |
5061 | ||
5d49f498 | 5062 | rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); |
b481de9c | 5063 | IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill); |
5d49f498 | 5064 | iwl_release_nic_access(priv); |
b481de9c ZY |
5065 | |
5066 | if (rfkill & 0x1) { | |
5067 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a96a27f9 | 5068 | /* if RFKILL is not on, then wait for thermal |
b481de9c | 5069 | * sensor in adapter to kick in */ |
bb8c093b | 5070 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
5071 | thermal_spin++; |
5072 | udelay(10); | |
5073 | } | |
5074 | ||
5075 | if (thermal_spin) | |
5076 | IWL_DEBUG_INFO("Thermal calibration took %dus\n", | |
5077 | thermal_spin * 10); | |
5078 | } else | |
5079 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5080 | ||
9fbab516 | 5081 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
5082 | set_bit(STATUS_ALIVE, &priv->status); |
5083 | ||
5084 | /* Clear out the uCode error bit if it is set */ | |
5085 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
5086 | ||
775a6e27 | 5087 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
5088 | return; |
5089 | ||
36d6825b | 5090 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
5091 | |
5092 | priv->active_rate = priv->rates_mask; | |
5093 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
5094 | ||
bb8c093b | 5095 | iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode)); |
b481de9c | 5096 | |
bb8c093b CH |
5097 | if (iwl3945_is_associated(priv)) { |
5098 | struct iwl3945_rxon_cmd *active_rxon = | |
f2c7e521 | 5099 | (struct iwl3945_rxon_cmd *)(&priv->active39_rxon); |
b481de9c | 5100 | |
f2c7e521 AK |
5101 | memcpy(&priv->staging39_rxon, &priv->active39_rxon, |
5102 | sizeof(priv->staging39_rxon)); | |
b481de9c ZY |
5103 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
5104 | } else { | |
5105 | /* Initialize our rx_config data */ | |
60294de3 | 5106 | iwl3945_connection_init_rx_config(priv, priv->iw_mode); |
f2c7e521 | 5107 | memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
b481de9c ZY |
5108 | } |
5109 | ||
9fbab516 | 5110 | /* Configure Bluetooth device coexistence support */ |
bb8c093b | 5111 | iwl3945_send_bt_config(priv); |
b481de9c ZY |
5112 | |
5113 | /* Configure the adapter for unassociated operation */ | |
bb8c093b | 5114 | iwl3945_commit_rxon(priv); |
b481de9c | 5115 | |
b481de9c ZY |
5116 | iwl3945_reg_txpower_periodic(priv); |
5117 | ||
fe00b5a5 RC |
5118 | iwl3945_led_register(priv); |
5119 | ||
b481de9c | 5120 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); |
a9f46786 | 5121 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 5122 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
5123 | |
5124 | if (priv->error_recovering) | |
bb8c093b | 5125 | iwl3945_error_recovery(priv); |
b481de9c | 5126 | |
9bdf5eca MA |
5127 | /* reassociate for ADHOC mode */ |
5128 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
5129 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
5130 | priv->vif); | |
5131 | if (beacon) | |
5132 | iwl3945_mac_beacon_update(priv->hw, beacon); | |
5133 | } | |
5134 | ||
b481de9c ZY |
5135 | return; |
5136 | ||
5137 | restart: | |
5138 | queue_work(priv->workqueue, &priv->restart); | |
5139 | } | |
5140 | ||
4a8a4322 | 5141 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 5142 | |
4a8a4322 | 5143 | static void __iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
5144 | { |
5145 | unsigned long flags; | |
5146 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
5147 | struct ieee80211_conf *conf = NULL; | |
5148 | ||
5149 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
5150 | ||
5151 | conf = ieee80211_get_hw_conf(priv->hw); | |
5152 | ||
5153 | if (!exit_pending) | |
5154 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5155 | ||
ab53d8af | 5156 | iwl3945_led_unregister(priv); |
bb8c093b | 5157 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
5158 | |
5159 | /* Unblock any waiting calls */ | |
5160 | wake_up_interruptible_all(&priv->wait_command_queue); | |
5161 | ||
b481de9c ZY |
5162 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
5163 | * exiting the module */ | |
5164 | if (!exit_pending) | |
5165 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
5166 | ||
5167 | /* stop and reset the on-board processor */ | |
5d49f498 | 5168 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
5169 | |
5170 | /* tell the device to stop sending interrupts */ | |
0359facc | 5171 | spin_lock_irqsave(&priv->lock, flags); |
bb8c093b | 5172 | iwl3945_disable_interrupts(priv); |
0359facc MA |
5173 | spin_unlock_irqrestore(&priv->lock, flags); |
5174 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
5175 | |
5176 | if (priv->mac80211_registered) | |
5177 | ieee80211_stop_queues(priv->hw); | |
5178 | ||
bb8c093b | 5179 | /* If we have not previously called iwl3945_init() then |
b481de9c | 5180 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
775a6e27 | 5181 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
5182 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
5183 | STATUS_RF_KILL_HW | | |
5184 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5185 | STATUS_RF_KILL_SW | | |
9788864e RC |
5186 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5187 | STATUS_GEO_CONFIGURED | | |
b481de9c | 5188 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
ebef2008 AK |
5189 | STATUS_IN_SUSPEND | |
5190 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
5191 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
5192 | goto exit; |
5193 | } | |
5194 | ||
5195 | /* ...otherwise clear out all the status bits but the RF Kill and | |
5196 | * SUSPEND bits and continue taking the NIC down. */ | |
5197 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
5198 | STATUS_RF_KILL_HW | | |
5199 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
5200 | STATUS_RF_KILL_SW | | |
9788864e RC |
5201 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
5202 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
5203 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
5204 | STATUS_IN_SUSPEND | | |
5205 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
ebef2008 AK |
5206 | STATUS_FW_ERROR | |
5207 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
5208 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
5209 | |
5210 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 5211 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
5212 | spin_unlock_irqrestore(&priv->lock, flags); |
5213 | ||
bb8c093b CH |
5214 | iwl3945_hw_txq_ctx_stop(priv); |
5215 | iwl3945_hw_rxq_stop(priv); | |
b481de9c ZY |
5216 | |
5217 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 AK |
5218 | if (!iwl_grab_nic_access(priv)) { |
5219 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 5220 | APMG_CLK_VAL_DMA_CLK_RQT); |
5d49f498 | 5221 | iwl_release_nic_access(priv); |
b481de9c ZY |
5222 | } |
5223 | spin_unlock_irqrestore(&priv->lock, flags); | |
5224 | ||
5225 | udelay(5); | |
5226 | ||
01ec616d | 5227 | priv->cfg->ops->lib->apm_ops.reset(priv); |
b481de9c | 5228 | exit: |
3d24a9f7 | 5229 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
5230 | |
5231 | if (priv->ibss_beacon) | |
5232 | dev_kfree_skb(priv->ibss_beacon); | |
5233 | priv->ibss_beacon = NULL; | |
5234 | ||
5235 | /* clear out any free frames */ | |
bb8c093b | 5236 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
5237 | } |
5238 | ||
4a8a4322 | 5239 | static void iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
5240 | { |
5241 | mutex_lock(&priv->mutex); | |
bb8c093b | 5242 | __iwl3945_down(priv); |
b481de9c | 5243 | mutex_unlock(&priv->mutex); |
b24d22b1 | 5244 | |
bb8c093b | 5245 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
5246 | } |
5247 | ||
5248 | #define MAX_HW_RESTARTS 5 | |
5249 | ||
4a8a4322 | 5250 | static int __iwl3945_up(struct iwl_priv *priv) |
b481de9c ZY |
5251 | { |
5252 | int rc, i; | |
5253 | ||
5254 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 5255 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
5256 | return -EIO; |
5257 | } | |
5258 | ||
5259 | if (test_bit(STATUS_RF_KILL_SW, &priv->status)) { | |
39aadf8c | 5260 | IWL_WARN(priv, "Radio disabled by SW RF kill (module " |
b481de9c | 5261 | "parameter)\n"); |
e655b9f0 ZY |
5262 | return -ENODEV; |
5263 | } | |
5264 | ||
e903fbd4 | 5265 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 5266 | IWL_ERR(priv, "ucode not available for device bring up\n"); |
e903fbd4 RC |
5267 | return -EIO; |
5268 | } | |
5269 | ||
e655b9f0 | 5270 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5d49f498 | 5271 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
5272 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
5273 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5274 | else { | |
5275 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5276 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) { | |
39aadf8c | 5277 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
e655b9f0 ZY |
5278 | return -ENODEV; |
5279 | } | |
b481de9c | 5280 | } |
80fcc9e2 | 5281 | |
5d49f498 | 5282 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 5283 | |
bb8c093b | 5284 | rc = iwl3945_hw_nic_init(priv); |
b481de9c | 5285 | if (rc) { |
15b1687c | 5286 | IWL_ERR(priv, "Unable to int nic\n"); |
b481de9c ZY |
5287 | return rc; |
5288 | } | |
5289 | ||
5290 | /* make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
5291 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5292 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
5293 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
5294 | ||
5295 | /* clear (again), then enable host interrupts */ | |
5d49f498 | 5296 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
bb8c093b | 5297 | iwl3945_enable_interrupts(priv); |
b481de9c ZY |
5298 | |
5299 | /* really make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
5300 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5301 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
5302 | |
5303 | /* Copy original ucode data image from disk into backup cache. | |
5304 | * This will be used to initialize the on-board processor's | |
5305 | * data SRAM for a clean start when the runtime program first loads. */ | |
5306 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 5307 | priv->ucode_data.len); |
b481de9c | 5308 | |
e655b9f0 ZY |
5309 | /* We return success when we resume from suspend and rf_kill is on. */ |
5310 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5311 | return 0; | |
5312 | ||
b481de9c ZY |
5313 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
5314 | ||
bb8c093b | 5315 | iwl3945_clear_stations_table(priv); |
b481de9c ZY |
5316 | |
5317 | /* load bootstrap state machine, | |
5318 | * load bootstrap program into processor's memory, | |
5319 | * prepare to load the "initialize" uCode */ | |
0164b9b4 | 5320 | priv->cfg->ops->lib->load_ucode(priv); |
b481de9c ZY |
5321 | |
5322 | if (rc) { | |
15b1687c WT |
5323 | IWL_ERR(priv, |
5324 | "Unable to set up bootstrap uCode: %d\n", rc); | |
b481de9c ZY |
5325 | continue; |
5326 | } | |
5327 | ||
5328 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 5329 | iwl3945_nic_start(priv); |
b481de9c | 5330 | |
b481de9c ZY |
5331 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
5332 | ||
5333 | return 0; | |
5334 | } | |
5335 | ||
5336 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 5337 | __iwl3945_down(priv); |
ebef2008 | 5338 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
5339 | |
5340 | /* tried to restart and config the device for as long as our | |
5341 | * patience could withstand */ | |
15b1687c | 5342 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
5343 | return -EIO; |
5344 | } | |
5345 | ||
5346 | ||
5347 | /***************************************************************************** | |
5348 | * | |
5349 | * Workqueue callbacks | |
5350 | * | |
5351 | *****************************************************************************/ | |
5352 | ||
bb8c093b | 5353 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 5354 | { |
4a8a4322 AK |
5355 | struct iwl_priv *priv = |
5356 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
5357 | |
5358 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5359 | return; | |
5360 | ||
5361 | mutex_lock(&priv->mutex); | |
bb8c093b | 5362 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
5363 | mutex_unlock(&priv->mutex); |
5364 | } | |
5365 | ||
bb8c093b | 5366 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 5367 | { |
4a8a4322 AK |
5368 | struct iwl_priv *priv = |
5369 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
5370 | |
5371 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5372 | return; | |
5373 | ||
5374 | mutex_lock(&priv->mutex); | |
bb8c093b | 5375 | iwl3945_alive_start(priv); |
b481de9c ZY |
5376 | mutex_unlock(&priv->mutex); |
5377 | } | |
5378 | ||
bb8c093b | 5379 | static void iwl3945_bg_rf_kill(struct work_struct *work) |
b481de9c | 5380 | { |
4a8a4322 | 5381 | struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill); |
b481de9c ZY |
5382 | |
5383 | wake_up_interruptible(&priv->wait_command_queue); | |
5384 | ||
5385 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5386 | return; | |
5387 | ||
5388 | mutex_lock(&priv->mutex); | |
5389 | ||
775a6e27 | 5390 | if (!iwl_is_rfkill(priv)) { |
b481de9c ZY |
5391 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL, |
5392 | "HW and/or SW RF Kill no longer active, restarting " | |
5393 | "device\n"); | |
2663516d HS |
5394 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status) && |
5395 | test_bit(STATUS_ALIVE, &priv->status)) | |
b481de9c ZY |
5396 | queue_work(priv->workqueue, &priv->restart); |
5397 | } else { | |
5398 | ||
5399 | if (!test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5400 | IWL_DEBUG_RF_KILL("Can not turn radio back on - " | |
5401 | "disabled by SW switch\n"); | |
5402 | else | |
39aadf8c | 5403 | IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n" |
b481de9c ZY |
5404 | "Kill switch must be turned off for " |
5405 | "wireless networking to work.\n"); | |
5406 | } | |
ebef2008 | 5407 | |
b481de9c | 5408 | mutex_unlock(&priv->mutex); |
80fcc9e2 | 5409 | iwl3945_rfkill_set_hw_state(priv); |
b481de9c ZY |
5410 | } |
5411 | ||
2663516d HS |
5412 | static void iwl3945_rfkill_poll(struct work_struct *data) |
5413 | { | |
5414 | struct iwl_priv *priv = | |
5415 | container_of(data, struct iwl_priv, rfkill_poll.work); | |
5416 | unsigned long status = priv->status; | |
5417 | ||
5418 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
5419 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
5420 | else | |
5421 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
5422 | ||
5423 | if (test_bit(STATUS_RF_KILL_HW, &status) != test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
5424 | queue_work(priv->workqueue, &priv->rf_kill); | |
5425 | ||
5426 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
5427 | round_jiffies_relative(2 * HZ)); | |
5428 | ||
5429 | } | |
5430 | ||
b481de9c ZY |
5431 | #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) |
5432 | ||
bb8c093b | 5433 | static void iwl3945_bg_scan_check(struct work_struct *data) |
b481de9c | 5434 | { |
4a8a4322 AK |
5435 | struct iwl_priv *priv = |
5436 | container_of(data, struct iwl_priv, scan_check.work); | |
b481de9c ZY |
5437 | |
5438 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5439 | return; | |
5440 | ||
5441 | mutex_lock(&priv->mutex); | |
5442 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
5443 | test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
5444 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, | |
5445 | "Scan completion watchdog resetting adapter (%dms)\n", | |
5446 | jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG)); | |
15e869d8 | 5447 | |
b481de9c | 5448 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
bb8c093b | 5449 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
5450 | } |
5451 | mutex_unlock(&priv->mutex); | |
5452 | } | |
5453 | ||
bb8c093b | 5454 | static void iwl3945_bg_request_scan(struct work_struct *data) |
b481de9c | 5455 | { |
4a8a4322 AK |
5456 | struct iwl_priv *priv = |
5457 | container_of(data, struct iwl_priv, request_scan); | |
c2d79b48 | 5458 | struct iwl_host_cmd cmd = { |
b481de9c | 5459 | .id = REPLY_SCAN_CMD, |
bb8c093b | 5460 | .len = sizeof(struct iwl3945_scan_cmd), |
b481de9c ZY |
5461 | .meta.flags = CMD_SIZE_HUGE, |
5462 | }; | |
5463 | int rc = 0; | |
bb8c093b | 5464 | struct iwl3945_scan_cmd *scan; |
b481de9c | 5465 | struct ieee80211_conf *conf = NULL; |
f9340520 | 5466 | u8 n_probes = 2; |
8318d78a | 5467 | enum ieee80211_band band; |
9387b7ca | 5468 | DECLARE_SSID_BUF(ssid); |
b481de9c ZY |
5469 | |
5470 | conf = ieee80211_get_hw_conf(priv->hw); | |
5471 | ||
5472 | mutex_lock(&priv->mutex); | |
5473 | ||
775a6e27 | 5474 | if (!iwl_is_ready(priv)) { |
39aadf8c | 5475 | IWL_WARN(priv, "request scan called when driver not ready.\n"); |
b481de9c ZY |
5476 | goto done; |
5477 | } | |
5478 | ||
a96a27f9 | 5479 | /* Make sure the scan wasn't canceled before this queued work |
b481de9c ZY |
5480 | * was given the chance to run... */ |
5481 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
5482 | goto done; | |
5483 | ||
5484 | /* This should never be called or scheduled if there is currently | |
5485 | * a scan active in the hardware. */ | |
5486 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
5487 | IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. " | |
5488 | "Ignoring second request.\n"); | |
5489 | rc = -EIO; | |
5490 | goto done; | |
5491 | } | |
5492 | ||
5493 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
5494 | IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n"); | |
5495 | goto done; | |
5496 | } | |
5497 | ||
5498 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
5499 | IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n"); | |
5500 | goto done; | |
5501 | } | |
5502 | ||
775a6e27 | 5503 | if (iwl_is_rfkill(priv)) { |
b481de9c ZY |
5504 | IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n"); |
5505 | goto done; | |
5506 | } | |
5507 | ||
5508 | if (!test_bit(STATUS_READY, &priv->status)) { | |
5509 | IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n"); | |
5510 | goto done; | |
5511 | } | |
5512 | ||
5513 | if (!priv->scan_bands) { | |
5514 | IWL_DEBUG_HC("Aborting scan due to no requested bands\n"); | |
5515 | goto done; | |
5516 | } | |
5517 | ||
f2c7e521 AK |
5518 | if (!priv->scan39) { |
5519 | priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) + | |
b481de9c | 5520 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); |
f2c7e521 | 5521 | if (!priv->scan39) { |
b481de9c ZY |
5522 | rc = -ENOMEM; |
5523 | goto done; | |
5524 | } | |
5525 | } | |
f2c7e521 | 5526 | scan = priv->scan39; |
bb8c093b | 5527 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
5528 | |
5529 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
5530 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
5531 | ||
bb8c093b | 5532 | if (iwl3945_is_associated(priv)) { |
b481de9c ZY |
5533 | u16 interval = 0; |
5534 | u32 extra; | |
5535 | u32 suspend_time = 100; | |
5536 | u32 scan_suspend_time = 100; | |
5537 | unsigned long flags; | |
5538 | ||
5539 | IWL_DEBUG_INFO("Scanning while associated...\n"); | |
5540 | ||
5541 | spin_lock_irqsave(&priv->lock, flags); | |
5542 | interval = priv->beacon_int; | |
5543 | spin_unlock_irqrestore(&priv->lock, flags); | |
5544 | ||
5545 | scan->suspend_time = 0; | |
15e869d8 | 5546 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
5547 | if (!interval) |
5548 | interval = suspend_time; | |
5549 | /* | |
5550 | * suspend time format: | |
5551 | * 0-19: beacon interval in usec (time before exec.) | |
5552 | * 20-23: 0 | |
5553 | * 24-31: number of beacons (suspend between channels) | |
5554 | */ | |
5555 | ||
5556 | extra = (suspend_time / interval) << 24; | |
5557 | scan_suspend_time = 0xFF0FFFFF & | |
5558 | (extra | ((suspend_time % interval) * 1024)); | |
5559 | ||
5560 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
5561 | IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n", | |
5562 | scan_suspend_time, interval); | |
5563 | } | |
5564 | ||
5565 | /* We should add the ability for user to lock to PASSIVE ONLY */ | |
5566 | if (priv->one_direct_scan) { | |
5567 | IWL_DEBUG_SCAN | |
5568 | ("Kicking off one direct scan for '%s'\n", | |
9387b7ca JL |
5569 | print_ssid(ssid, priv->direct_ssid, |
5570 | priv->direct_ssid_len)); | |
b481de9c ZY |
5571 | scan->direct_scan[0].id = WLAN_EID_SSID; |
5572 | scan->direct_scan[0].len = priv->direct_ssid_len; | |
5573 | memcpy(scan->direct_scan[0].ssid, | |
5574 | priv->direct_ssid, priv->direct_ssid_len); | |
f9340520 | 5575 | n_probes++; |
f9340520 | 5576 | } else |
786b4557 | 5577 | IWL_DEBUG_SCAN("Kicking off one indirect scan.\n"); |
b481de9c ZY |
5578 | |
5579 | /* We don't build a direct scan probe request; the uCode will do | |
5580 | * that based on the direct_mask added to each channel entry */ | |
5581 | scan->tx_cmd.len = cpu_to_le16( | |
bb8c093b | 5582 | iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data, |
430cfe95 | 5583 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); |
b481de9c | 5584 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
3832ec9d | 5585 | scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id; |
b481de9c ZY |
5586 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
5587 | ||
5588 | /* flags + rate selection */ | |
5589 | ||
66b5004d | 5590 | if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) { |
b481de9c ZY |
5591 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
5592 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
5593 | scan->good_CRC_th = 0; | |
8318d78a | 5594 | band = IEEE80211_BAND_2GHZ; |
66b5004d | 5595 | } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) { |
b481de9c ZY |
5596 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
5597 | scan->good_CRC_th = IWL_GOOD_CRC_TH; | |
8318d78a | 5598 | band = IEEE80211_BAND_5GHZ; |
66b5004d | 5599 | } else { |
39aadf8c | 5600 | IWL_WARN(priv, "Invalid scan band count\n"); |
b481de9c ZY |
5601 | goto done; |
5602 | } | |
5603 | ||
5604 | /* select Rx antennas */ | |
5605 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
5606 | ||
05c914fe | 5607 | if (priv->iw_mode == NL80211_IFTYPE_MONITOR) |
b481de9c ZY |
5608 | scan->filter_flags = RXON_FILTER_PROMISC_MSK; |
5609 | ||
f9340520 AK |
5610 | scan->channel_count = |
5611 | iwl3945_get_channels_for_scan(priv, band, 1, /* active */ | |
5612 | n_probes, | |
5613 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]); | |
b481de9c | 5614 | |
14b54336 RC |
5615 | if (scan->channel_count == 0) { |
5616 | IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count); | |
5617 | goto done; | |
5618 | } | |
5619 | ||
b481de9c | 5620 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 5621 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
5622 | cmd.data = scan; |
5623 | scan->len = cpu_to_le16(cmd.len); | |
5624 | ||
5625 | set_bit(STATUS_SCAN_HW, &priv->status); | |
bb8c093b | 5626 | rc = iwl3945_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
5627 | if (rc) |
5628 | goto done; | |
5629 | ||
5630 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
5631 | IWL_SCAN_CHECK_WATCHDOG); | |
5632 | ||
5633 | mutex_unlock(&priv->mutex); | |
5634 | return; | |
5635 | ||
5636 | done: | |
2420ebc1 MA |
5637 | /* can not perform scan make sure we clear scanning |
5638 | * bits from status so next scan request can be performed. | |
5639 | * if we dont clear scanning status bit here all next scan | |
5640 | * will fail | |
5641 | */ | |
5642 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
5643 | clear_bit(STATUS_SCANNING, &priv->status); | |
5644 | ||
01ebd063 | 5645 | /* inform mac80211 scan aborted */ |
b481de9c ZY |
5646 | queue_work(priv->workqueue, &priv->scan_completed); |
5647 | mutex_unlock(&priv->mutex); | |
5648 | } | |
5649 | ||
bb8c093b | 5650 | static void iwl3945_bg_up(struct work_struct *data) |
b481de9c | 5651 | { |
4a8a4322 | 5652 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
5653 | |
5654 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5655 | return; | |
5656 | ||
5657 | mutex_lock(&priv->mutex); | |
bb8c093b | 5658 | __iwl3945_up(priv); |
b481de9c | 5659 | mutex_unlock(&priv->mutex); |
80fcc9e2 | 5660 | iwl3945_rfkill_set_hw_state(priv); |
b481de9c ZY |
5661 | } |
5662 | ||
bb8c093b | 5663 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 5664 | { |
4a8a4322 | 5665 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
5666 | |
5667 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5668 | return; | |
5669 | ||
bb8c093b | 5670 | iwl3945_down(priv); |
b481de9c ZY |
5671 | queue_work(priv->workqueue, &priv->up); |
5672 | } | |
5673 | ||
bb8c093b | 5674 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 5675 | { |
4a8a4322 AK |
5676 | struct iwl_priv *priv = |
5677 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
5678 | |
5679 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5680 | return; | |
5681 | ||
5682 | mutex_lock(&priv->mutex); | |
bb8c093b | 5683 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
5684 | mutex_unlock(&priv->mutex); |
5685 | } | |
5686 | ||
7878a5a4 MA |
5687 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
5688 | ||
4a8a4322 | 5689 | static void iwl3945_post_associate(struct iwl_priv *priv) |
b481de9c | 5690 | { |
b481de9c ZY |
5691 | int rc = 0; |
5692 | struct ieee80211_conf *conf = NULL; | |
5693 | ||
05c914fe | 5694 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 5695 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
5696 | return; |
5697 | } | |
5698 | ||
5699 | ||
e174961c | 5700 | IWL_DEBUG_ASSOC("Associated as %d to: %pM\n", |
f2c7e521 | 5701 | priv->assoc_id, priv->active39_rxon.bssid_addr); |
b481de9c ZY |
5702 | |
5703 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5704 | return; | |
5705 | ||
322a9811 | 5706 | if (!priv->vif || !priv->is_open) |
6ef89d0a | 5707 | return; |
322a9811 | 5708 | |
af0053d6 | 5709 | iwl_scan_cancel_timeout(priv, 200); |
15e869d8 | 5710 | |
b481de9c ZY |
5711 | conf = ieee80211_get_hw_conf(priv->hw); |
5712 | ||
f2c7e521 | 5713 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 5714 | iwl3945_commit_rxon(priv); |
b481de9c | 5715 | |
28afaf91 | 5716 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
bb8c093b CH |
5717 | iwl3945_setup_rxon_timing(priv); |
5718 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
5719 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
5720 | if (rc) | |
39aadf8c | 5721 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
5722 | "Attempting to continue.\n"); |
5723 | ||
f2c7e521 | 5724 | priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 5725 | |
f2c7e521 | 5726 | priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c ZY |
5727 | |
5728 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
5729 | priv->assoc_id, priv->beacon_int); | |
5730 | ||
5731 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
f2c7e521 | 5732 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 5733 | else |
f2c7e521 | 5734 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 5735 | |
f2c7e521 | 5736 | if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c | 5737 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
f2c7e521 | 5738 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 5739 | else |
f2c7e521 | 5740 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 5741 | |
05c914fe | 5742 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
f2c7e521 | 5743 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
5744 | |
5745 | } | |
5746 | ||
bb8c093b | 5747 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
5748 | |
5749 | switch (priv->iw_mode) { | |
05c914fe | 5750 | case NL80211_IFTYPE_STATION: |
bb8c093b | 5751 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c ZY |
5752 | break; |
5753 | ||
05c914fe | 5754 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 5755 | |
ce546fd2 | 5756 | priv->assoc_id = 1; |
bb8c093b | 5757 | iwl3945_add_station(priv, priv->bssid, 0, 0); |
b481de9c | 5758 | iwl3945_sync_sta(priv, IWL_STA_ID, |
8318d78a | 5759 | (priv->band == IEEE80211_BAND_5GHZ) ? |
b481de9c ZY |
5760 | IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP, |
5761 | CMD_ASYNC); | |
bb8c093b CH |
5762 | iwl3945_rate_scale_init(priv->hw, IWL_STA_ID); |
5763 | iwl3945_send_beacon_cmd(priv); | |
b481de9c ZY |
5764 | |
5765 | break; | |
5766 | ||
5767 | default: | |
15b1687c | 5768 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 5769 | __func__, priv->iw_mode); |
b481de9c ZY |
5770 | break; |
5771 | } | |
5772 | ||
bb8c093b | 5773 | iwl3945_activate_qos(priv, 0); |
292ae174 | 5774 | |
7878a5a4 MA |
5775 | /* we have just associated, don't start scan too early */ |
5776 | priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN; | |
cd56d331 AK |
5777 | } |
5778 | ||
bb8c093b | 5779 | static void iwl3945_bg_abort_scan(struct work_struct *work) |
b481de9c | 5780 | { |
4a8a4322 | 5781 | struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan); |
b481de9c | 5782 | |
775a6e27 | 5783 | if (!iwl_is_ready(priv)) |
b481de9c ZY |
5784 | return; |
5785 | ||
5786 | mutex_lock(&priv->mutex); | |
5787 | ||
5788 | set_bit(STATUS_SCAN_ABORTING, &priv->status); | |
bb8c093b | 5789 | iwl3945_send_scan_abort(priv); |
b481de9c ZY |
5790 | |
5791 | mutex_unlock(&priv->mutex); | |
5792 | } | |
5793 | ||
e8975581 | 5794 | static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed); |
76bb77e0 | 5795 | |
bb8c093b | 5796 | static void iwl3945_bg_scan_completed(struct work_struct *work) |
b481de9c | 5797 | { |
4a8a4322 AK |
5798 | struct iwl_priv *priv = |
5799 | container_of(work, struct iwl_priv, scan_completed); | |
b481de9c ZY |
5800 | |
5801 | IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n"); | |
5802 | ||
5803 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
5804 | return; | |
5805 | ||
a0646470 | 5806 | if (test_bit(STATUS_CONF_PENDING, &priv->status)) |
e8975581 | 5807 | iwl3945_mac_config(priv->hw, 0); |
76bb77e0 | 5808 | |
b481de9c ZY |
5809 | ieee80211_scan_completed(priv->hw); |
5810 | ||
5811 | /* Since setting the TXPOWER may have been deferred while | |
5812 | * performing the scan, fire one off */ | |
5813 | mutex_lock(&priv->mutex); | |
bb8c093b | 5814 | iwl3945_hw_reg_send_txpower(priv); |
b481de9c ZY |
5815 | mutex_unlock(&priv->mutex); |
5816 | } | |
5817 | ||
5818 | /***************************************************************************** | |
5819 | * | |
5820 | * mac80211 entry point functions | |
5821 | * | |
5822 | *****************************************************************************/ | |
5823 | ||
5a66926a ZY |
5824 | #define UCODE_READY_TIMEOUT (2 * HZ) |
5825 | ||
bb8c093b | 5826 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 5827 | { |
4a8a4322 | 5828 | struct iwl_priv *priv = hw->priv; |
5a66926a | 5829 | int ret; |
b481de9c ZY |
5830 | |
5831 | IWL_DEBUG_MAC80211("enter\n"); | |
5832 | ||
5833 | /* we should be verifying the device is ready to be opened */ | |
5834 | mutex_lock(&priv->mutex); | |
5835 | ||
f2c7e521 | 5836 | memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd)); |
5a66926a ZY |
5837 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
5838 | * ucode filename and max sizes are card-specific. */ | |
5839 | ||
5840 | if (!priv->ucode_code.len) { | |
5841 | ret = iwl3945_read_ucode(priv); | |
5842 | if (ret) { | |
15b1687c | 5843 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a ZY |
5844 | mutex_unlock(&priv->mutex); |
5845 | goto out_release_irq; | |
5846 | } | |
5847 | } | |
b481de9c | 5848 | |
e655b9f0 | 5849 | ret = __iwl3945_up(priv); |
b481de9c ZY |
5850 | |
5851 | mutex_unlock(&priv->mutex); | |
5a66926a | 5852 | |
80fcc9e2 AG |
5853 | iwl3945_rfkill_set_hw_state(priv); |
5854 | ||
e655b9f0 ZY |
5855 | if (ret) |
5856 | goto out_release_irq; | |
5857 | ||
5858 | IWL_DEBUG_INFO("Start UP work.\n"); | |
5859 | ||
5860 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
5861 | return 0; | |
5862 | ||
5a66926a ZY |
5863 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
5864 | * mac80211 will not be run successfully. */ | |
5865 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
5866 | test_bit(STATUS_READY, &priv->status), | |
5867 | UCODE_READY_TIMEOUT); | |
5868 | if (!ret) { | |
5869 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c WT |
5870 | IWL_ERR(priv, |
5871 | "Wait for START_ALIVE timeout after %dms.\n", | |
5872 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
5a66926a ZY |
5873 | ret = -ETIMEDOUT; |
5874 | goto out_release_irq; | |
5875 | } | |
5876 | } | |
5877 | ||
2663516d HS |
5878 | /* ucode is running and will send rfkill notifications, |
5879 | * no need to poll the killswitch state anymore */ | |
5880 | cancel_delayed_work(&priv->rfkill_poll); | |
5881 | ||
e655b9f0 | 5882 | priv->is_open = 1; |
b481de9c ZY |
5883 | IWL_DEBUG_MAC80211("leave\n"); |
5884 | return 0; | |
5a66926a ZY |
5885 | |
5886 | out_release_irq: | |
e655b9f0 ZY |
5887 | priv->is_open = 0; |
5888 | IWL_DEBUG_MAC80211("leave - failed\n"); | |
5a66926a | 5889 | return ret; |
b481de9c ZY |
5890 | } |
5891 | ||
bb8c093b | 5892 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 5893 | { |
4a8a4322 | 5894 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
5895 | |
5896 | IWL_DEBUG_MAC80211("enter\n"); | |
6ef89d0a | 5897 | |
e655b9f0 ZY |
5898 | if (!priv->is_open) { |
5899 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
5900 | return; | |
5901 | } | |
5902 | ||
b481de9c | 5903 | priv->is_open = 0; |
5a66926a | 5904 | |
775a6e27 | 5905 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
5906 | /* stop mac, cancel any scan request and clear |
5907 | * RXON_FILTER_ASSOC_MSK BIT | |
5908 | */ | |
5a66926a | 5909 | mutex_lock(&priv->mutex); |
af0053d6 | 5910 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 5911 | mutex_unlock(&priv->mutex); |
fde3571f MA |
5912 | } |
5913 | ||
5a66926a ZY |
5914 | iwl3945_down(priv); |
5915 | ||
5916 | flush_workqueue(priv->workqueue); | |
2663516d HS |
5917 | |
5918 | /* start polling the killswitch state again */ | |
5919 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
5920 | round_jiffies_relative(2 * HZ)); | |
6ef89d0a | 5921 | |
b481de9c | 5922 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
5923 | } |
5924 | ||
e039fa4a | 5925 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 5926 | { |
4a8a4322 | 5927 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
5928 | |
5929 | IWL_DEBUG_MAC80211("enter\n"); | |
5930 | ||
b481de9c | 5931 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 5932 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 5933 | |
e039fa4a | 5934 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
5935 | dev_kfree_skb_any(skb); |
5936 | ||
5937 | IWL_DEBUG_MAC80211("leave\n"); | |
637f8837 | 5938 | return NETDEV_TX_OK; |
b481de9c ZY |
5939 | } |
5940 | ||
bb8c093b | 5941 | static int iwl3945_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
5942 | struct ieee80211_if_init_conf *conf) |
5943 | { | |
4a8a4322 | 5944 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
5945 | unsigned long flags; |
5946 | ||
32bfd35d | 5947 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 5948 | |
32bfd35d JB |
5949 | if (priv->vif) { |
5950 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
864792e3 | 5951 | return -EOPNOTSUPP; |
b481de9c ZY |
5952 | } |
5953 | ||
5954 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 5955 | priv->vif = conf->vif; |
60294de3 | 5956 | priv->iw_mode = conf->type; |
b481de9c ZY |
5957 | |
5958 | spin_unlock_irqrestore(&priv->lock, flags); | |
5959 | ||
5960 | mutex_lock(&priv->mutex); | |
864792e3 TW |
5961 | |
5962 | if (conf->mac_addr) { | |
e174961c | 5963 | IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr); |
864792e3 TW |
5964 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); |
5965 | } | |
5966 | ||
775a6e27 | 5967 | if (iwl_is_ready(priv)) |
5a66926a | 5968 | iwl3945_set_mode(priv, conf->type); |
b481de9c | 5969 | |
b481de9c ZY |
5970 | mutex_unlock(&priv->mutex); |
5971 | ||
5a66926a | 5972 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
5973 | return 0; |
5974 | } | |
5975 | ||
5976 | /** | |
bb8c093b | 5977 | * iwl3945_mac_config - mac80211 config callback |
b481de9c ZY |
5978 | * |
5979 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
5980 | * be set inappropriately and the driver currently sets the hardware up to | |
5981 | * use it whenever needed. | |
5982 | */ | |
e8975581 | 5983 | static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed) |
b481de9c | 5984 | { |
4a8a4322 | 5985 | struct iwl_priv *priv = hw->priv; |
d20b3c65 | 5986 | const struct iwl_channel_info *ch_info; |
e8975581 | 5987 | struct ieee80211_conf *conf = &hw->conf; |
b481de9c | 5988 | unsigned long flags; |
76bb77e0 | 5989 | int ret = 0; |
b481de9c ZY |
5990 | |
5991 | mutex_lock(&priv->mutex); | |
8318d78a | 5992 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 5993 | |
775a6e27 | 5994 | if (!iwl_is_ready(priv)) { |
b481de9c | 5995 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
5996 | ret = -EIO; |
5997 | goto out; | |
b481de9c ZY |
5998 | } |
5999 | ||
df878d8f | 6000 | if (unlikely(!iwl3945_mod_params.disable_hw_scan && |
b481de9c | 6001 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 ZY |
6002 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
6003 | set_bit(STATUS_CONF_PENDING, &priv->status); | |
b481de9c | 6004 | mutex_unlock(&priv->mutex); |
a0646470 | 6005 | return 0; |
b481de9c ZY |
6006 | } |
6007 | ||
6008 | spin_lock_irqsave(&priv->lock, flags); | |
6009 | ||
8318d78a JB |
6010 | ch_info = iwl3945_get_channel_info(priv, conf->channel->band, |
6011 | conf->channel->hw_value); | |
b481de9c | 6012 | if (!is_channel_valid(ch_info)) { |
66b5004d | 6013 | IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n", |
8318d78a | 6014 | conf->channel->hw_value, conf->channel->band); |
b481de9c ZY |
6015 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
6016 | spin_unlock_irqrestore(&priv->lock, flags); | |
76bb77e0 ZY |
6017 | ret = -EINVAL; |
6018 | goto out; | |
b481de9c ZY |
6019 | } |
6020 | ||
8318d78a | 6021 | iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value); |
b481de9c | 6022 | |
8318d78a | 6023 | iwl3945_set_flags_for_phymode(priv, conf->channel->band); |
b481de9c ZY |
6024 | |
6025 | /* The list of supported rates and rate mask can be different | |
6026 | * for each phymode; since the phymode may have changed, reset | |
6027 | * the rate mask to what mac80211 lists */ | |
bb8c093b | 6028 | iwl3945_set_rate(priv); |
b481de9c ZY |
6029 | |
6030 | spin_unlock_irqrestore(&priv->lock, flags); | |
6031 | ||
6032 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
6033 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
bb8c093b | 6034 | iwl3945_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 6035 | goto out; |
b481de9c ZY |
6036 | } |
6037 | #endif | |
6038 | ||
bb8c093b | 6039 | iwl3945_radio_kill_sw(priv, !conf->radio_enabled); |
b481de9c ZY |
6040 | |
6041 | if (!conf->radio_enabled) { | |
6042 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 6043 | goto out; |
b481de9c ZY |
6044 | } |
6045 | ||
775a6e27 | 6046 | if (iwl_is_rfkill(priv)) { |
b481de9c | 6047 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
6048 | ret = -EIO; |
6049 | goto out; | |
b481de9c ZY |
6050 | } |
6051 | ||
bb8c093b | 6052 | iwl3945_set_rate(priv); |
b481de9c | 6053 | |
f2c7e521 AK |
6054 | if (memcmp(&priv->active39_rxon, |
6055 | &priv->staging39_rxon, sizeof(priv->staging39_rxon))) | |
bb8c093b | 6056 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6057 | else |
6058 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
6059 | ||
6060 | IWL_DEBUG_MAC80211("leave\n"); | |
6061 | ||
76bb77e0 | 6062 | out: |
a0646470 | 6063 | clear_bit(STATUS_CONF_PENDING, &priv->status); |
b481de9c | 6064 | mutex_unlock(&priv->mutex); |
76bb77e0 | 6065 | return ret; |
b481de9c ZY |
6066 | } |
6067 | ||
4a8a4322 | 6068 | static void iwl3945_config_ap(struct iwl_priv *priv) |
b481de9c ZY |
6069 | { |
6070 | int rc = 0; | |
6071 | ||
d986bcd1 | 6072 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
6073 | return; |
6074 | ||
6075 | /* The following should be done only at AP bring up */ | |
5d1e2325 | 6076 | if (!(iwl3945_is_associated(priv))) { |
b481de9c ZY |
6077 | |
6078 | /* RXON - unassoc (to set timing command) */ | |
f2c7e521 | 6079 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6080 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6081 | |
6082 | /* RXON Timing */ | |
28afaf91 | 6083 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
bb8c093b CH |
6084 | iwl3945_setup_rxon_timing(priv); |
6085 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING, | |
b481de9c ZY |
6086 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
6087 | if (rc) | |
39aadf8c | 6088 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
6089 | "Attempting to continue.\n"); |
6090 | ||
6091 | /* FIXME: what should be the assoc_id for AP? */ | |
f2c7e521 | 6092 | priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
b481de9c | 6093 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) |
f2c7e521 | 6094 | priv->staging39_rxon.flags |= |
b481de9c ZY |
6095 | RXON_FLG_SHORT_PREAMBLE_MSK; |
6096 | else | |
f2c7e521 | 6097 | priv->staging39_rxon.flags &= |
b481de9c ZY |
6098 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
6099 | ||
f2c7e521 | 6100 | if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
b481de9c ZY |
6101 | if (priv->assoc_capability & |
6102 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
f2c7e521 | 6103 | priv->staging39_rxon.flags |= |
b481de9c ZY |
6104 | RXON_FLG_SHORT_SLOT_MSK; |
6105 | else | |
f2c7e521 | 6106 | priv->staging39_rxon.flags &= |
b481de9c ZY |
6107 | ~RXON_FLG_SHORT_SLOT_MSK; |
6108 | ||
05c914fe | 6109 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
f2c7e521 | 6110 | priv->staging39_rxon.flags &= |
b481de9c ZY |
6111 | ~RXON_FLG_SHORT_SLOT_MSK; |
6112 | } | |
6113 | /* restore RXON assoc */ | |
f2c7e521 | 6114 | priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6115 | iwl3945_commit_rxon(priv); |
b5323d36 | 6116 | iwl3945_add_station(priv, iwl_bcast_addr, 0, 0); |
556f8db7 | 6117 | } |
bb8c093b | 6118 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
6119 | |
6120 | /* FIXME - we need to add code here to detect a totally new | |
6121 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
6122 | * clear sta table, add BCAST sta... */ | |
6123 | } | |
6124 | ||
32bfd35d JB |
6125 | static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, |
6126 | struct ieee80211_vif *vif, | |
4a8a4322 | 6127 | struct ieee80211_if_conf *conf) |
b481de9c | 6128 | { |
4a8a4322 | 6129 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6130 | int rc; |
6131 | ||
6132 | if (conf == NULL) | |
6133 | return -EIO; | |
6134 | ||
b716bb91 EG |
6135 | if (priv->vif != vif) { |
6136 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
b716bb91 EG |
6137 | return 0; |
6138 | } | |
6139 | ||
9d139c81 | 6140 | /* handle this temporarily here */ |
05c914fe | 6141 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && |
9d139c81 JB |
6142 | conf->changed & IEEE80211_IFCC_BEACON) { |
6143 | struct sk_buff *beacon = ieee80211_beacon_get(hw, vif); | |
6144 | if (!beacon) | |
6145 | return -ENOMEM; | |
9bdf5eca | 6146 | mutex_lock(&priv->mutex); |
9d139c81 | 6147 | rc = iwl3945_mac_beacon_update(hw, beacon); |
9bdf5eca | 6148 | mutex_unlock(&priv->mutex); |
9d139c81 JB |
6149 | if (rc) |
6150 | return rc; | |
6151 | } | |
6152 | ||
775a6e27 | 6153 | if (!iwl_is_alive(priv)) |
5a66926a ZY |
6154 | return -EAGAIN; |
6155 | ||
b481de9c ZY |
6156 | mutex_lock(&priv->mutex); |
6157 | ||
b481de9c | 6158 | if (conf->bssid) |
e174961c | 6159 | IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid); |
b481de9c | 6160 | |
4150c572 JB |
6161 | /* |
6162 | * very dubious code was here; the probe filtering flag is never set: | |
6163 | * | |
b481de9c ZY |
6164 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
6165 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 | 6166 | */ |
b481de9c | 6167 | |
05c914fe | 6168 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
b481de9c ZY |
6169 | if (!conf->bssid) { |
6170 | conf->bssid = priv->mac_addr; | |
6171 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
e174961c JB |
6172 | IWL_DEBUG_MAC80211("bssid was set to: %pM\n", |
6173 | conf->bssid); | |
b481de9c ZY |
6174 | } |
6175 | if (priv->ibss_beacon) | |
6176 | dev_kfree_skb(priv->ibss_beacon); | |
6177 | ||
9d139c81 | 6178 | priv->ibss_beacon = ieee80211_beacon_get(hw, vif); |
b481de9c ZY |
6179 | } |
6180 | ||
775a6e27 | 6181 | if (iwl_is_rfkill(priv)) |
fde3571f MA |
6182 | goto done; |
6183 | ||
b481de9c ZY |
6184 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
6185 | !is_multicast_ether_addr(conf->bssid)) { | |
6186 | /* If there is currently a HW scan going on in the background | |
6187 | * then we need to cancel it else the RXON below will fail. */ | |
af0053d6 | 6188 | if (iwl_scan_cancel_timeout(priv, 100)) { |
39aadf8c | 6189 | IWL_WARN(priv, "Aborted scan still in progress " |
b481de9c ZY |
6190 | "after 100ms\n"); |
6191 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
6192 | mutex_unlock(&priv->mutex); | |
6193 | return -EAGAIN; | |
6194 | } | |
f2c7e521 | 6195 | memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN); |
b481de9c ZY |
6196 | |
6197 | /* TODO: Audit driver for usage of these members and see | |
6198 | * if mac80211 deprecates them (priv->bssid looks like it | |
6199 | * shouldn't be there, but I haven't scanned the IBSS code | |
6200 | * to verify) - jpk */ | |
6201 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
6202 | ||
05c914fe | 6203 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
bb8c093b | 6204 | iwl3945_config_ap(priv); |
b481de9c | 6205 | else { |
bb8c093b | 6206 | rc = iwl3945_commit_rxon(priv); |
05c914fe | 6207 | if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc) |
bb8c093b | 6208 | iwl3945_add_station(priv, |
f2c7e521 | 6209 | priv->active39_rxon.bssid_addr, 1, 0); |
b481de9c ZY |
6210 | } |
6211 | ||
6212 | } else { | |
af0053d6 | 6213 | iwl_scan_cancel_timeout(priv, 100); |
f2c7e521 | 6214 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6215 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6216 | } |
6217 | ||
fde3571f | 6218 | done: |
b481de9c ZY |
6219 | IWL_DEBUG_MAC80211("leave\n"); |
6220 | mutex_unlock(&priv->mutex); | |
6221 | ||
6222 | return 0; | |
6223 | } | |
6224 | ||
bb8c093b | 6225 | static void iwl3945_configure_filter(struct ieee80211_hw *hw, |
4150c572 JB |
6226 | unsigned int changed_flags, |
6227 | unsigned int *total_flags, | |
6228 | int mc_count, struct dev_addr_list *mc_list) | |
6229 | { | |
4a8a4322 | 6230 | struct iwl_priv *priv = hw->priv; |
f2c7e521 | 6231 | __le32 *filter_flags = &priv->staging39_rxon.filter_flags; |
25b3f57c | 6232 | |
352bc8de ZY |
6233 | IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", |
6234 | changed_flags, *total_flags); | |
6235 | ||
6236 | if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) { | |
6237 | if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) | |
6238 | *filter_flags |= RXON_FILTER_PROMISC_MSK; | |
6239 | else | |
6240 | *filter_flags &= ~RXON_FILTER_PROMISC_MSK; | |
6241 | } | |
6242 | if (changed_flags & FIF_ALLMULTI) { | |
6243 | if (*total_flags & FIF_ALLMULTI) | |
6244 | *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK; | |
6245 | else | |
6246 | *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK; | |
6247 | } | |
6248 | if (changed_flags & FIF_CONTROL) { | |
6249 | if (*total_flags & FIF_CONTROL) | |
6250 | *filter_flags |= RXON_FILTER_CTL2HOST_MSK; | |
6251 | else | |
6252 | *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK; | |
5ec03976 | 6253 | } |
352bc8de ZY |
6254 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
6255 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
6256 | *filter_flags |= RXON_FILTER_BCON_AWARE_MSK; | |
6257 | else | |
6258 | *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK; | |
6259 | } | |
6260 | ||
6261 | /* We avoid iwl_commit_rxon here to commit the new filter flags | |
6262 | * since mac80211 will call ieee80211_hw_config immediately. | |
6263 | * (mc_list is not supported at this time). Otherwise, we need to | |
6264 | * queue a background iwl_commit_rxon work. | |
6265 | */ | |
6266 | ||
6267 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
25b3f57c | 6268 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; |
4150c572 JB |
6269 | } |
6270 | ||
bb8c093b | 6271 | static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
6272 | struct ieee80211_if_init_conf *conf) |
6273 | { | |
4a8a4322 | 6274 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6275 | |
6276 | IWL_DEBUG_MAC80211("enter\n"); | |
6277 | ||
6278 | mutex_lock(&priv->mutex); | |
6ef89d0a | 6279 | |
775a6e27 | 6280 | if (iwl_is_ready_rf(priv)) { |
af0053d6 | 6281 | iwl_scan_cancel_timeout(priv, 100); |
f2c7e521 | 6282 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
fde3571f MA |
6283 | iwl3945_commit_rxon(priv); |
6284 | } | |
32bfd35d JB |
6285 | if (priv->vif == conf->vif) { |
6286 | priv->vif = NULL; | |
b481de9c | 6287 | memset(priv->bssid, 0, ETH_ALEN); |
b481de9c ZY |
6288 | } |
6289 | mutex_unlock(&priv->mutex); | |
6290 | ||
6291 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
6292 | } |
6293 | ||
cd56d331 AK |
6294 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
6295 | ||
6296 | static void iwl3945_bss_info_changed(struct ieee80211_hw *hw, | |
6297 | struct ieee80211_vif *vif, | |
6298 | struct ieee80211_bss_conf *bss_conf, | |
6299 | u32 changes) | |
6300 | { | |
4a8a4322 | 6301 | struct iwl_priv *priv = hw->priv; |
cd56d331 AK |
6302 | |
6303 | IWL_DEBUG_MAC80211("changes = 0x%X\n", changes); | |
6304 | ||
6305 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { | |
6306 | IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n", | |
6307 | bss_conf->use_short_preamble); | |
6308 | if (bss_conf->use_short_preamble) | |
f2c7e521 | 6309 | priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
cd56d331 | 6310 | else |
f2c7e521 | 6311 | priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
cd56d331 AK |
6312 | } |
6313 | ||
6314 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { | |
6315 | IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); | |
6316 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) | |
f2c7e521 | 6317 | priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; |
cd56d331 | 6318 | else |
f2c7e521 | 6319 | priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; |
cd56d331 AK |
6320 | } |
6321 | ||
6322 | if (changes & BSS_CHANGED_ASSOC) { | |
6323 | IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc); | |
6324 | /* This should never happen as this function should | |
6325 | * never be called from interrupt context. */ | |
6326 | if (WARN_ON_ONCE(in_interrupt())) | |
6327 | return; | |
6328 | if (bss_conf->assoc) { | |
6329 | priv->assoc_id = bss_conf->aid; | |
6330 | priv->beacon_int = bss_conf->beacon_int; | |
28afaf91 | 6331 | priv->timestamp = bss_conf->timestamp; |
cd56d331 AK |
6332 | priv->assoc_capability = bss_conf->assoc_capability; |
6333 | priv->next_scan_jiffies = jiffies + | |
6334 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
6335 | mutex_lock(&priv->mutex); | |
6336 | iwl3945_post_associate(priv); | |
6337 | mutex_unlock(&priv->mutex); | |
6338 | } else { | |
6339 | priv->assoc_id = 0; | |
6340 | IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc); | |
6341 | } | |
6342 | } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) { | |
6343 | IWL_DEBUG_MAC80211("Associated Changes %d\n", changes); | |
6344 | iwl3945_send_rxon_assoc(priv); | |
6345 | } | |
6346 | ||
6347 | } | |
6348 | ||
bb8c093b | 6349 | static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len) |
b481de9c ZY |
6350 | { |
6351 | int rc = 0; | |
6352 | unsigned long flags; | |
4a8a4322 | 6353 | struct iwl_priv *priv = hw->priv; |
9387b7ca | 6354 | DECLARE_SSID_BUF(ssid_buf); |
b481de9c ZY |
6355 | |
6356 | IWL_DEBUG_MAC80211("enter\n"); | |
6357 | ||
15e869d8 | 6358 | mutex_lock(&priv->mutex); |
b481de9c ZY |
6359 | spin_lock_irqsave(&priv->lock, flags); |
6360 | ||
775a6e27 | 6361 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
6362 | rc = -EIO; |
6363 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); | |
6364 | goto out_unlock; | |
6365 | } | |
6366 | ||
7878a5a4 MA |
6367 | /* we don't schedule scan within next_scan_jiffies period */ |
6368 | if (priv->next_scan_jiffies && | |
6369 | time_after(priv->next_scan_jiffies, jiffies)) { | |
6370 | rc = -EAGAIN; | |
6371 | goto out_unlock; | |
6372 | } | |
15dbf1b7 BM |
6373 | /* if we just finished scan ask for delay for a broadcast scan */ |
6374 | if ((len == 0) && priv->last_scan_jiffies && | |
6375 | time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN, | |
6376 | jiffies)) { | |
b481de9c ZY |
6377 | rc = -EAGAIN; |
6378 | goto out_unlock; | |
6379 | } | |
6380 | if (len) { | |
7878a5a4 | 6381 | IWL_DEBUG_SCAN("direct scan for %s [%d]\n ", |
9387b7ca | 6382 | print_ssid(ssid_buf, ssid, len), (int)len); |
b481de9c ZY |
6383 | |
6384 | priv->one_direct_scan = 1; | |
6385 | priv->direct_ssid_len = (u8) | |
6386 | min((u8) len, (u8) IW_ESSID_MAX_SIZE); | |
6387 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); | |
6ef89d0a MA |
6388 | } else |
6389 | priv->one_direct_scan = 0; | |
b481de9c | 6390 | |
bb8c093b | 6391 | rc = iwl3945_scan_initiate(priv); |
b481de9c ZY |
6392 | |
6393 | IWL_DEBUG_MAC80211("leave\n"); | |
6394 | ||
6395 | out_unlock: | |
6396 | spin_unlock_irqrestore(&priv->lock, flags); | |
15e869d8 | 6397 | mutex_unlock(&priv->mutex); |
b481de9c ZY |
6398 | |
6399 | return rc; | |
6400 | } | |
6401 | ||
bb8c093b | 6402 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
6403 | struct ieee80211_vif *vif, |
6404 | struct ieee80211_sta *sta, | |
6405 | struct ieee80211_key_conf *key) | |
b481de9c | 6406 | { |
4a8a4322 | 6407 | struct iwl_priv *priv = hw->priv; |
dc822b5d | 6408 | const u8 *addr; |
42986796 | 6409 | int ret; |
b481de9c ZY |
6410 | u8 sta_id; |
6411 | ||
6412 | IWL_DEBUG_MAC80211("enter\n"); | |
6413 | ||
df878d8f | 6414 | if (iwl3945_mod_params.sw_crypto) { |
b481de9c ZY |
6415 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
6416 | return -EOPNOTSUPP; | |
6417 | } | |
6418 | ||
42986796 | 6419 | addr = sta ? sta->addr : iwl_bcast_addr; |
bb8c093b | 6420 | sta_id = iwl3945_hw_find_station(priv, addr); |
b481de9c | 6421 | if (sta_id == IWL_INVALID_STATION) { |
e174961c JB |
6422 | IWL_DEBUG_MAC80211("leave - %pM not in station map.\n", |
6423 | addr); | |
b481de9c ZY |
6424 | return -EINVAL; |
6425 | } | |
6426 | ||
6427 | mutex_lock(&priv->mutex); | |
6428 | ||
af0053d6 | 6429 | iwl_scan_cancel_timeout(priv, 100); |
15e869d8 | 6430 | |
b481de9c ZY |
6431 | switch (cmd) { |
6432 | case SET_KEY: | |
42986796 WT |
6433 | ret = iwl3945_update_sta_key_info(priv, key, sta_id); |
6434 | if (!ret) { | |
bb8c093b CH |
6435 | iwl3945_set_rxon_hwcrypto(priv, 1); |
6436 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
6437 | key->hw_key_idx = sta_id; |
6438 | IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n"); | |
6439 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
6440 | } | |
6441 | break; | |
6442 | case DISABLE_KEY: | |
42986796 WT |
6443 | ret = iwl3945_clear_sta_key_info(priv, sta_id); |
6444 | if (!ret) { | |
bb8c093b CH |
6445 | iwl3945_set_rxon_hwcrypto(priv, 0); |
6446 | iwl3945_commit_rxon(priv); | |
b481de9c ZY |
6447 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); |
6448 | } | |
6449 | break; | |
6450 | default: | |
42986796 | 6451 | ret = -EINVAL; |
b481de9c ZY |
6452 | } |
6453 | ||
6454 | IWL_DEBUG_MAC80211("leave\n"); | |
6455 | mutex_unlock(&priv->mutex); | |
6456 | ||
42986796 | 6457 | return ret; |
b481de9c ZY |
6458 | } |
6459 | ||
e100bb64 | 6460 | static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
b481de9c ZY |
6461 | const struct ieee80211_tx_queue_params *params) |
6462 | { | |
4a8a4322 | 6463 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6464 | unsigned long flags; |
6465 | int q; | |
b481de9c ZY |
6466 | |
6467 | IWL_DEBUG_MAC80211("enter\n"); | |
6468 | ||
775a6e27 | 6469 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
6470 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
6471 | return -EIO; | |
6472 | } | |
6473 | ||
6474 | if (queue >= AC_NUM) { | |
6475 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
6476 | return 0; | |
6477 | } | |
6478 | ||
b481de9c ZY |
6479 | q = AC_NUM - 1 - queue; |
6480 | ||
6481 | spin_lock_irqsave(&priv->lock, flags); | |
6482 | ||
6483 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
6484 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
6485 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
6486 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 6487 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
6488 | |
6489 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
6490 | priv->qos_data.qos_active = 1; | |
6491 | ||
6492 | spin_unlock_irqrestore(&priv->lock, flags); | |
6493 | ||
6494 | mutex_lock(&priv->mutex); | |
05c914fe | 6495 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
bb8c093b CH |
6496 | iwl3945_activate_qos(priv, 1); |
6497 | else if (priv->assoc_id && iwl3945_is_associated(priv)) | |
6498 | iwl3945_activate_qos(priv, 0); | |
b481de9c ZY |
6499 | |
6500 | mutex_unlock(&priv->mutex); | |
6501 | ||
b481de9c ZY |
6502 | IWL_DEBUG_MAC80211("leave\n"); |
6503 | return 0; | |
6504 | } | |
6505 | ||
bb8c093b | 6506 | static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
6507 | struct ieee80211_tx_queue_stats *stats) |
6508 | { | |
4a8a4322 | 6509 | struct iwl_priv *priv = hw->priv; |
b481de9c | 6510 | int i, avail; |
188cf6c7 | 6511 | struct iwl_tx_queue *txq; |
d20b3c65 | 6512 | struct iwl_queue *q; |
b481de9c ZY |
6513 | unsigned long flags; |
6514 | ||
6515 | IWL_DEBUG_MAC80211("enter\n"); | |
6516 | ||
775a6e27 | 6517 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
6518 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
6519 | return -EIO; | |
6520 | } | |
6521 | ||
6522 | spin_lock_irqsave(&priv->lock, flags); | |
6523 | ||
6524 | for (i = 0; i < AC_NUM; i++) { | |
188cf6c7 | 6525 | txq = &priv->txq[i]; |
b481de9c | 6526 | q = &txq->q; |
d20b3c65 | 6527 | avail = iwl_queue_space(q); |
b481de9c | 6528 | |
57ffc589 JB |
6529 | stats[i].len = q->n_window - avail; |
6530 | stats[i].limit = q->n_window - q->high_mark; | |
6531 | stats[i].count = q->n_window; | |
b481de9c ZY |
6532 | |
6533 | } | |
6534 | spin_unlock_irqrestore(&priv->lock, flags); | |
6535 | ||
6536 | IWL_DEBUG_MAC80211("leave\n"); | |
6537 | ||
6538 | return 0; | |
6539 | } | |
6540 | ||
bb8c093b | 6541 | static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 6542 | { |
4a8a4322 | 6543 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6544 | unsigned long flags; |
6545 | ||
6546 | mutex_lock(&priv->mutex); | |
6547 | IWL_DEBUG_MAC80211("enter\n"); | |
6548 | ||
775a6e27 | 6549 | iwl_reset_qos(priv); |
292ae174 | 6550 | |
b481de9c ZY |
6551 | spin_lock_irqsave(&priv->lock, flags); |
6552 | priv->assoc_id = 0; | |
6553 | priv->assoc_capability = 0; | |
6554 | priv->call_post_assoc_from_beacon = 0; | |
6555 | ||
6556 | /* new association get rid of ibss beacon skb */ | |
6557 | if (priv->ibss_beacon) | |
6558 | dev_kfree_skb(priv->ibss_beacon); | |
6559 | ||
6560 | priv->ibss_beacon = NULL; | |
6561 | ||
6562 | priv->beacon_int = priv->hw->conf.beacon_int; | |
28afaf91 | 6563 | priv->timestamp = 0; |
05c914fe | 6564 | if ((priv->iw_mode == NL80211_IFTYPE_STATION)) |
b481de9c ZY |
6565 | priv->beacon_int = 0; |
6566 | ||
6567 | spin_unlock_irqrestore(&priv->lock, flags); | |
6568 | ||
775a6e27 | 6569 | if (!iwl_is_ready_rf(priv)) { |
fde3571f MA |
6570 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
6571 | mutex_unlock(&priv->mutex); | |
6572 | return; | |
6573 | } | |
6574 | ||
15e869d8 MA |
6575 | /* we are restarting association process |
6576 | * clear RXON_FILTER_ASSOC_MSK bit | |
6577 | */ | |
05c914fe | 6578 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
af0053d6 | 6579 | iwl_scan_cancel_timeout(priv, 100); |
f2c7e521 | 6580 | priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
bb8c093b | 6581 | iwl3945_commit_rxon(priv); |
15e869d8 MA |
6582 | } |
6583 | ||
b481de9c | 6584 | /* Per mac80211.h: This is only used in IBSS mode... */ |
05c914fe | 6585 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
15e869d8 | 6586 | |
b481de9c ZY |
6587 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
6588 | mutex_unlock(&priv->mutex); | |
6589 | return; | |
b481de9c ZY |
6590 | } |
6591 | ||
bb8c093b | 6592 | iwl3945_set_rate(priv); |
b481de9c ZY |
6593 | |
6594 | mutex_unlock(&priv->mutex); | |
6595 | ||
6596 | IWL_DEBUG_MAC80211("leave\n"); | |
6597 | ||
6598 | } | |
6599 | ||
e039fa4a | 6600 | static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 6601 | { |
4a8a4322 | 6602 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
6603 | unsigned long flags; |
6604 | ||
b481de9c ZY |
6605 | IWL_DEBUG_MAC80211("enter\n"); |
6606 | ||
775a6e27 | 6607 | if (!iwl_is_ready_rf(priv)) { |
b481de9c | 6608 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
b481de9c ZY |
6609 | return -EIO; |
6610 | } | |
6611 | ||
05c914fe | 6612 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
b481de9c | 6613 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); |
b481de9c ZY |
6614 | return -EIO; |
6615 | } | |
6616 | ||
6617 | spin_lock_irqsave(&priv->lock, flags); | |
6618 | ||
6619 | if (priv->ibss_beacon) | |
6620 | dev_kfree_skb(priv->ibss_beacon); | |
6621 | ||
6622 | priv->ibss_beacon = skb; | |
6623 | ||
6624 | priv->assoc_id = 0; | |
6625 | ||
6626 | IWL_DEBUG_MAC80211("leave\n"); | |
6627 | spin_unlock_irqrestore(&priv->lock, flags); | |
6628 | ||
775a6e27 | 6629 | iwl_reset_qos(priv); |
b481de9c | 6630 | |
dc4b1e7d | 6631 | iwl3945_post_associate(priv); |
b481de9c | 6632 | |
b481de9c ZY |
6633 | |
6634 | return 0; | |
6635 | } | |
6636 | ||
6637 | /***************************************************************************** | |
6638 | * | |
6639 | * sysfs attributes | |
6640 | * | |
6641 | *****************************************************************************/ | |
6642 | ||
c8b0e6e1 | 6643 | #ifdef CONFIG_IWL3945_DEBUG |
b481de9c ZY |
6644 | |
6645 | /* | |
6646 | * The following adds a new attribute to the sysfs representation | |
6647 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
6648 | * used for controlling the debug level. | |
6649 | * | |
6650 | * See the level definitions in iwl for details. | |
6651 | */ | |
40b8ec0b SO |
6652 | static ssize_t show_debug_level(struct device *d, |
6653 | struct device_attribute *attr, char *buf) | |
b481de9c | 6654 | { |
4a8a4322 | 6655 | struct iwl_priv *priv = d->driver_data; |
40b8ec0b SO |
6656 | |
6657 | return sprintf(buf, "0x%08X\n", priv->debug_level); | |
b481de9c | 6658 | } |
40b8ec0b SO |
6659 | static ssize_t store_debug_level(struct device *d, |
6660 | struct device_attribute *attr, | |
b481de9c ZY |
6661 | const char *buf, size_t count) |
6662 | { | |
4a8a4322 | 6663 | struct iwl_priv *priv = d->driver_data; |
40b8ec0b SO |
6664 | unsigned long val; |
6665 | int ret; | |
b481de9c | 6666 | |
40b8ec0b SO |
6667 | ret = strict_strtoul(buf, 0, &val); |
6668 | if (ret) | |
978785a3 | 6669 | IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf); |
b481de9c | 6670 | else |
40b8ec0b | 6671 | priv->debug_level = val; |
b481de9c ZY |
6672 | |
6673 | return strnlen(buf, count); | |
6674 | } | |
6675 | ||
40b8ec0b SO |
6676 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
6677 | show_debug_level, store_debug_level); | |
b481de9c | 6678 | |
c8b0e6e1 | 6679 | #endif /* CONFIG_IWL3945_DEBUG */ |
b481de9c | 6680 | |
b481de9c ZY |
6681 | static ssize_t show_temperature(struct device *d, |
6682 | struct device_attribute *attr, char *buf) | |
6683 | { | |
4a8a4322 | 6684 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 6685 | |
775a6e27 | 6686 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
6687 | return -EAGAIN; |
6688 | ||
bb8c093b | 6689 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
6690 | } |
6691 | ||
6692 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
6693 | ||
b481de9c ZY |
6694 | static ssize_t show_tx_power(struct device *d, |
6695 | struct device_attribute *attr, char *buf) | |
6696 | { | |
4a8a4322 | 6697 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
6698 | return sprintf(buf, "%d\n", priv->user_txpower_limit); |
6699 | } | |
6700 | ||
6701 | static ssize_t store_tx_power(struct device *d, | |
6702 | struct device_attribute *attr, | |
6703 | const char *buf, size_t count) | |
6704 | { | |
4a8a4322 | 6705 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
6706 | char *p = (char *)buf; |
6707 | u32 val; | |
6708 | ||
6709 | val = simple_strtoul(p, &p, 10); | |
6710 | if (p == buf) | |
978785a3 | 6711 | IWL_INFO(priv, ": %s is not in decimal form.\n", buf); |
b481de9c | 6712 | else |
bb8c093b | 6713 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
6714 | |
6715 | return count; | |
6716 | } | |
6717 | ||
6718 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
6719 | ||
6720 | static ssize_t show_flags(struct device *d, | |
6721 | struct device_attribute *attr, char *buf) | |
6722 | { | |
4a8a4322 | 6723 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 6724 | |
f2c7e521 | 6725 | return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags); |
b481de9c ZY |
6726 | } |
6727 | ||
6728 | static ssize_t store_flags(struct device *d, | |
6729 | struct device_attribute *attr, | |
6730 | const char *buf, size_t count) | |
6731 | { | |
4a8a4322 | 6732 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
6733 | u32 flags = simple_strtoul(buf, NULL, 0); |
6734 | ||
6735 | mutex_lock(&priv->mutex); | |
f2c7e521 | 6736 | if (le32_to_cpu(priv->staging39_rxon.flags) != flags) { |
b481de9c | 6737 | /* Cancel any currently running scans... */ |
af0053d6 | 6738 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 6739 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c ZY |
6740 | else { |
6741 | IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n", | |
6742 | flags); | |
f2c7e521 | 6743 | priv->staging39_rxon.flags = cpu_to_le32(flags); |
bb8c093b | 6744 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6745 | } |
6746 | } | |
6747 | mutex_unlock(&priv->mutex); | |
6748 | ||
6749 | return count; | |
6750 | } | |
6751 | ||
6752 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
6753 | ||
6754 | static ssize_t show_filter_flags(struct device *d, | |
6755 | struct device_attribute *attr, char *buf) | |
6756 | { | |
4a8a4322 | 6757 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
6758 | |
6759 | return sprintf(buf, "0x%04X\n", | |
f2c7e521 | 6760 | le32_to_cpu(priv->active39_rxon.filter_flags)); |
b481de9c ZY |
6761 | } |
6762 | ||
6763 | static ssize_t store_filter_flags(struct device *d, | |
6764 | struct device_attribute *attr, | |
6765 | const char *buf, size_t count) | |
6766 | { | |
4a8a4322 | 6767 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
6768 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
6769 | ||
6770 | mutex_lock(&priv->mutex); | |
f2c7e521 | 6771 | if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) { |
b481de9c | 6772 | /* Cancel any currently running scans... */ |
af0053d6 | 6773 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 6774 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c ZY |
6775 | else { |
6776 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
6777 | "0x%04X\n", filter_flags); | |
f2c7e521 | 6778 | priv->staging39_rxon.filter_flags = |
b481de9c | 6779 | cpu_to_le32(filter_flags); |
bb8c093b | 6780 | iwl3945_commit_rxon(priv); |
b481de9c ZY |
6781 | } |
6782 | } | |
6783 | mutex_unlock(&priv->mutex); | |
6784 | ||
6785 | return count; | |
6786 | } | |
6787 | ||
6788 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
6789 | store_filter_flags); | |
6790 | ||
c8b0e6e1 | 6791 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
6792 | |
6793 | static ssize_t show_measurement(struct device *d, | |
6794 | struct device_attribute *attr, char *buf) | |
6795 | { | |
4a8a4322 | 6796 | struct iwl_priv *priv = dev_get_drvdata(d); |
600c0e11 | 6797 | struct iwl_spectrum_notification measure_report; |
b481de9c | 6798 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 6799 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
6800 | unsigned long flags; |
6801 | ||
6802 | spin_lock_irqsave(&priv->lock, flags); | |
6803 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
6804 | spin_unlock_irqrestore(&priv->lock, flags); | |
6805 | return 0; | |
6806 | } | |
6807 | memcpy(&measure_report, &priv->measure_report, size); | |
6808 | priv->measurement_status = 0; | |
6809 | spin_unlock_irqrestore(&priv->lock, flags); | |
6810 | ||
6811 | while (size && (PAGE_SIZE - len)) { | |
6812 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
6813 | PAGE_SIZE - len, 1); | |
6814 | len = strlen(buf); | |
6815 | if (PAGE_SIZE - len) | |
6816 | buf[len++] = '\n'; | |
6817 | ||
6818 | ofs += 16; | |
6819 | size -= min(size, 16U); | |
6820 | } | |
6821 | ||
6822 | return len; | |
6823 | } | |
6824 | ||
6825 | static ssize_t store_measurement(struct device *d, | |
6826 | struct device_attribute *attr, | |
6827 | const char *buf, size_t count) | |
6828 | { | |
4a8a4322 | 6829 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 6830 | struct ieee80211_measurement_params params = { |
f2c7e521 | 6831 | .channel = le16_to_cpu(priv->active39_rxon.channel), |
b481de9c ZY |
6832 | .start_time = cpu_to_le64(priv->last_tsf), |
6833 | .duration = cpu_to_le16(1), | |
6834 | }; | |
6835 | u8 type = IWL_MEASURE_BASIC; | |
6836 | u8 buffer[32]; | |
6837 | u8 channel; | |
6838 | ||
6839 | if (count) { | |
6840 | char *p = buffer; | |
6841 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
6842 | channel = simple_strtoul(p, NULL, 0); | |
6843 | if (channel) | |
6844 | params.channel = channel; | |
6845 | ||
6846 | p = buffer; | |
6847 | while (*p && *p != ' ') | |
6848 | p++; | |
6849 | if (*p) | |
6850 | type = simple_strtoul(p + 1, NULL, 0); | |
6851 | } | |
6852 | ||
6853 | IWL_DEBUG_INFO("Invoking measurement of type %d on " | |
6854 | "channel %d (for '%s')\n", type, params.channel, buf); | |
bb8c093b | 6855 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
6856 | |
6857 | return count; | |
6858 | } | |
6859 | ||
6860 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
6861 | show_measurement, store_measurement); | |
c8b0e6e1 | 6862 | #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */ |
b481de9c | 6863 | |
b481de9c ZY |
6864 | static ssize_t store_retry_rate(struct device *d, |
6865 | struct device_attribute *attr, | |
6866 | const char *buf, size_t count) | |
6867 | { | |
4a8a4322 | 6868 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
6869 | |
6870 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
6871 | if (priv->retry_rate <= 0) | |
6872 | priv->retry_rate = 1; | |
6873 | ||
6874 | return count; | |
6875 | } | |
6876 | ||
6877 | static ssize_t show_retry_rate(struct device *d, | |
6878 | struct device_attribute *attr, char *buf) | |
6879 | { | |
4a8a4322 | 6880 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
6881 | return sprintf(buf, "%d", priv->retry_rate); |
6882 | } | |
6883 | ||
6884 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
6885 | store_retry_rate); | |
6886 | ||
6887 | static ssize_t store_power_level(struct device *d, | |
6888 | struct device_attribute *attr, | |
6889 | const char *buf, size_t count) | |
6890 | { | |
4a8a4322 | 6891 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
6892 | int rc; |
6893 | int mode; | |
6894 | ||
6895 | mode = simple_strtoul(buf, NULL, 0); | |
6896 | mutex_lock(&priv->mutex); | |
6897 | ||
775a6e27 | 6898 | if (!iwl_is_ready(priv)) { |
b481de9c ZY |
6899 | rc = -EAGAIN; |
6900 | goto out; | |
6901 | } | |
6902 | ||
1125eff3 SO |
6903 | if ((mode < 1) || (mode > IWL39_POWER_LIMIT) || |
6904 | (mode == IWL39_POWER_AC)) | |
6905 | mode = IWL39_POWER_AC; | |
b481de9c ZY |
6906 | else |
6907 | mode |= IWL_POWER_ENABLED; | |
6908 | ||
6909 | if (mode != priv->power_mode) { | |
bb8c093b | 6910 | rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode)); |
b481de9c ZY |
6911 | if (rc) { |
6912 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | |
6913 | goto out; | |
6914 | } | |
6915 | priv->power_mode = mode; | |
6916 | } | |
6917 | ||
6918 | rc = count; | |
6919 | ||
6920 | out: | |
6921 | mutex_unlock(&priv->mutex); | |
6922 | return rc; | |
6923 | } | |
6924 | ||
6925 | #define MAX_WX_STRING 80 | |
6926 | ||
6927 | /* Values are in microsecond */ | |
6928 | static const s32 timeout_duration[] = { | |
6929 | 350000, | |
6930 | 250000, | |
6931 | 75000, | |
6932 | 37000, | |
6933 | 25000, | |
6934 | }; | |
6935 | static const s32 period_duration[] = { | |
6936 | 400000, | |
6937 | 700000, | |
6938 | 1000000, | |
6939 | 1000000, | |
6940 | 1000000 | |
6941 | }; | |
6942 | ||
6943 | static ssize_t show_power_level(struct device *d, | |
6944 | struct device_attribute *attr, char *buf) | |
6945 | { | |
4a8a4322 | 6946 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
6947 | int level = IWL_POWER_LEVEL(priv->power_mode); |
6948 | char *p = buf; | |
6949 | ||
6950 | p += sprintf(p, "%d ", level); | |
6951 | switch (level) { | |
6952 | case IWL_POWER_MODE_CAM: | |
1125eff3 | 6953 | case IWL39_POWER_AC: |
b481de9c ZY |
6954 | p += sprintf(p, "(AC)"); |
6955 | break; | |
1125eff3 | 6956 | case IWL39_POWER_BATTERY: |
b481de9c ZY |
6957 | p += sprintf(p, "(BATTERY)"); |
6958 | break; | |
6959 | default: | |
6960 | p += sprintf(p, | |
6961 | "(Timeout %dms, Period %dms)", | |
6962 | timeout_duration[level - 1] / 1000, | |
6963 | period_duration[level - 1] / 1000); | |
6964 | } | |
6965 | ||
6966 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | |
6967 | p += sprintf(p, " OFF\n"); | |
6968 | else | |
6969 | p += sprintf(p, " \n"); | |
6970 | ||
3ac7f146 | 6971 | return p - buf + 1; |
b481de9c ZY |
6972 | |
6973 | } | |
6974 | ||
6975 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
6976 | store_power_level); | |
6977 | ||
6978 | static ssize_t show_channels(struct device *d, | |
6979 | struct device_attribute *attr, char *buf) | |
6980 | { | |
8318d78a JB |
6981 | /* all this shit doesn't belong into sysfs anyway */ |
6982 | return 0; | |
b481de9c ZY |
6983 | } |
6984 | ||
6985 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
6986 | ||
6987 | static ssize_t show_statistics(struct device *d, | |
6988 | struct device_attribute *attr, char *buf) | |
6989 | { | |
4a8a4322 | 6990 | struct iwl_priv *priv = dev_get_drvdata(d); |
bb8c093b | 6991 | u32 size = sizeof(struct iwl3945_notif_statistics); |
b481de9c | 6992 | u32 len = 0, ofs = 0; |
f2c7e521 | 6993 | u8 *data = (u8 *)&priv->statistics_39; |
b481de9c ZY |
6994 | int rc = 0; |
6995 | ||
775a6e27 | 6996 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
6997 | return -EAGAIN; |
6998 | ||
6999 | mutex_lock(&priv->mutex); | |
bb8c093b | 7000 | rc = iwl3945_send_statistics_request(priv); |
b481de9c ZY |
7001 | mutex_unlock(&priv->mutex); |
7002 | ||
7003 | if (rc) { | |
7004 | len = sprintf(buf, | |
7005 | "Error sending statistics request: 0x%08X\n", rc); | |
7006 | return len; | |
7007 | } | |
7008 | ||
7009 | while (size && (PAGE_SIZE - len)) { | |
7010 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
7011 | PAGE_SIZE - len, 1); | |
7012 | len = strlen(buf); | |
7013 | if (PAGE_SIZE - len) | |
7014 | buf[len++] = '\n'; | |
7015 | ||
7016 | ofs += 16; | |
7017 | size -= min(size, 16U); | |
7018 | } | |
7019 | ||
7020 | return len; | |
7021 | } | |
7022 | ||
7023 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
7024 | ||
7025 | static ssize_t show_antenna(struct device *d, | |
7026 | struct device_attribute *attr, char *buf) | |
7027 | { | |
4a8a4322 | 7028 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 7029 | |
775a6e27 | 7030 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7031 | return -EAGAIN; |
7032 | ||
7033 | return sprintf(buf, "%d\n", priv->antenna); | |
7034 | } | |
7035 | ||
7036 | static ssize_t store_antenna(struct device *d, | |
7037 | struct device_attribute *attr, | |
7038 | const char *buf, size_t count) | |
7039 | { | |
7040 | int ant; | |
4a8a4322 | 7041 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
7042 | |
7043 | if (count == 0) | |
7044 | return 0; | |
7045 | ||
7046 | if (sscanf(buf, "%1i", &ant) != 1) { | |
7047 | IWL_DEBUG_INFO("not in hex or decimal form.\n"); | |
7048 | return count; | |
7049 | } | |
7050 | ||
7051 | if ((ant >= 0) && (ant <= 2)) { | |
7052 | IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant); | |
bb8c093b | 7053 | priv->antenna = (enum iwl3945_antenna)ant; |
b481de9c ZY |
7054 | } else |
7055 | IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant); | |
7056 | ||
7057 | ||
7058 | return count; | |
7059 | } | |
7060 | ||
7061 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
7062 | ||
7063 | static ssize_t show_status(struct device *d, | |
7064 | struct device_attribute *attr, char *buf) | |
7065 | { | |
4a8a4322 | 7066 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
775a6e27 | 7067 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
7068 | return -EAGAIN; |
7069 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
7070 | } | |
7071 | ||
7072 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
7073 | ||
7074 | static ssize_t dump_error_log(struct device *d, | |
7075 | struct device_attribute *attr, | |
7076 | const char *buf, size_t count) | |
7077 | { | |
7078 | char *p = (char *)buf; | |
7079 | ||
7080 | if (p[0] == '1') | |
4a8a4322 | 7081 | iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7082 | |
7083 | return strnlen(buf, count); | |
7084 | } | |
7085 | ||
7086 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
7087 | ||
7088 | static ssize_t dump_event_log(struct device *d, | |
7089 | struct device_attribute *attr, | |
7090 | const char *buf, size_t count) | |
7091 | { | |
7092 | char *p = (char *)buf; | |
7093 | ||
7094 | if (p[0] == '1') | |
4a8a4322 | 7095 | iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data); |
b481de9c ZY |
7096 | |
7097 | return strnlen(buf, count); | |
7098 | } | |
7099 | ||
7100 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | |
7101 | ||
7102 | /***************************************************************************** | |
7103 | * | |
a96a27f9 | 7104 | * driver setup and tear down |
b481de9c ZY |
7105 | * |
7106 | *****************************************************************************/ | |
7107 | ||
4a8a4322 | 7108 | static void iwl3945_setup_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
7109 | { |
7110 | priv->workqueue = create_workqueue(DRV_NAME); | |
7111 | ||
7112 | init_waitqueue_head(&priv->wait_command_queue); | |
7113 | ||
bb8c093b CH |
7114 | INIT_WORK(&priv->up, iwl3945_bg_up); |
7115 | INIT_WORK(&priv->restart, iwl3945_bg_restart); | |
7116 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
7117 | INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed); | |
7118 | INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan); | |
7119 | INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan); | |
7120 | INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill); | |
7121 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); | |
bb8c093b CH |
7122 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
7123 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
7124 | INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check); | |
2663516d | 7125 | INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll); |
bb8c093b CH |
7126 | |
7127 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c ZY |
7128 | |
7129 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
bb8c093b | 7130 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
7131 | } |
7132 | ||
4a8a4322 | 7133 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 7134 | { |
bb8c093b | 7135 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 7136 | |
e47eb6ad | 7137 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
7138 | cancel_delayed_work(&priv->scan_check); |
7139 | cancel_delayed_work(&priv->alive_start); | |
b481de9c ZY |
7140 | cancel_work_sync(&priv->beacon_update); |
7141 | } | |
7142 | ||
bb8c093b | 7143 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
7144 | &dev_attr_antenna.attr, |
7145 | &dev_attr_channels.attr, | |
7146 | &dev_attr_dump_errors.attr, | |
7147 | &dev_attr_dump_events.attr, | |
7148 | &dev_attr_flags.attr, | |
7149 | &dev_attr_filter_flags.attr, | |
c8b0e6e1 | 7150 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
b481de9c ZY |
7151 | &dev_attr_measurement.attr, |
7152 | #endif | |
7153 | &dev_attr_power_level.attr, | |
b481de9c | 7154 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
7155 | &dev_attr_statistics.attr, |
7156 | &dev_attr_status.attr, | |
7157 | &dev_attr_temperature.attr, | |
b481de9c | 7158 | &dev_attr_tx_power.attr, |
40b8ec0b SO |
7159 | #ifdef CONFIG_IWL3945_DEBUG |
7160 | &dev_attr_debug_level.attr, | |
7161 | #endif | |
b481de9c ZY |
7162 | NULL |
7163 | }; | |
7164 | ||
bb8c093b | 7165 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 7166 | .name = NULL, /* put in device directory */ |
bb8c093b | 7167 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
7168 | }; |
7169 | ||
bb8c093b CH |
7170 | static struct ieee80211_ops iwl3945_hw_ops = { |
7171 | .tx = iwl3945_mac_tx, | |
7172 | .start = iwl3945_mac_start, | |
7173 | .stop = iwl3945_mac_stop, | |
7174 | .add_interface = iwl3945_mac_add_interface, | |
7175 | .remove_interface = iwl3945_mac_remove_interface, | |
7176 | .config = iwl3945_mac_config, | |
7177 | .config_interface = iwl3945_mac_config_interface, | |
7178 | .configure_filter = iwl3945_configure_filter, | |
7179 | .set_key = iwl3945_mac_set_key, | |
bb8c093b CH |
7180 | .get_tx_stats = iwl3945_mac_get_tx_stats, |
7181 | .conf_tx = iwl3945_mac_conf_tx, | |
bb8c093b | 7182 | .reset_tsf = iwl3945_mac_reset_tsf, |
cd56d331 | 7183 | .bss_info_changed = iwl3945_bss_info_changed, |
bb8c093b | 7184 | .hw_scan = iwl3945_mac_hw_scan |
b481de9c ZY |
7185 | }; |
7186 | ||
e52119c5 | 7187 | static int iwl3945_init_drv(struct iwl_priv *priv) |
90a30a02 KA |
7188 | { |
7189 | int ret; | |
7190 | ||
7191 | priv->retry_rate = 1; | |
7192 | priv->ibss_beacon = NULL; | |
7193 | ||
7194 | spin_lock_init(&priv->lock); | |
c7a7c8ec | 7195 | spin_lock_init(&priv->power_data_39.lock); |
90a30a02 KA |
7196 | spin_lock_init(&priv->sta_lock); |
7197 | spin_lock_init(&priv->hcmd_lock); | |
7198 | ||
7199 | INIT_LIST_HEAD(&priv->free_frames); | |
7200 | ||
7201 | mutex_init(&priv->mutex); | |
7202 | ||
7203 | /* Clear the driver's (not device's) station table */ | |
7204 | iwl3945_clear_stations_table(priv); | |
7205 | ||
7206 | priv->data_retry_limit = -1; | |
7207 | priv->ieee_channels = NULL; | |
7208 | priv->ieee_rates = NULL; | |
7209 | priv->band = IEEE80211_BAND_2GHZ; | |
7210 | ||
7211 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
7212 | ||
7213 | iwl_reset_qos(priv); | |
7214 | ||
7215 | priv->qos_data.qos_active = 0; | |
7216 | priv->qos_data.qos_cap.val = 0; | |
7217 | ||
7218 | priv->rates_mask = IWL_RATES_MASK; | |
7219 | /* If power management is turned on, default to AC mode */ | |
c7a7c8ec | 7220 | priv->power_mode = IWL39_POWER_AC; |
90a30a02 KA |
7221 | priv->user_txpower_limit = IWL_DEFAULT_TX_POWER; |
7222 | ||
7223 | ret = iwl3945_init_channel_map(priv); | |
7224 | if (ret) { | |
7225 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
7226 | goto err; | |
7227 | } | |
7228 | ||
7229 | ret = iwl3945_init_geos(priv); | |
7230 | if (ret) { | |
7231 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
7232 | goto err_free_channel_map; | |
7233 | } | |
7234 | ||
7235 | return 0; | |
7236 | ||
7237 | err_free_channel_map: | |
7238 | iwl3945_free_channel_map(priv); | |
7239 | err: | |
7240 | return ret; | |
7241 | } | |
7242 | ||
bb8c093b | 7243 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
7244 | { |
7245 | int err = 0; | |
4a8a4322 | 7246 | struct iwl_priv *priv; |
b481de9c | 7247 | struct ieee80211_hw *hw; |
c0f20d91 | 7248 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 7249 | unsigned long flags; |
b481de9c | 7250 | |
cee53ddb KA |
7251 | /*********************** |
7252 | * 1. Allocating HW data | |
7253 | * ********************/ | |
7254 | ||
b481de9c ZY |
7255 | /* mac80211 allocates memory for this device instance, including |
7256 | * space for this driver's private structure */ | |
90a30a02 | 7257 | hw = iwl_alloc_all(cfg, &iwl3945_hw_ops); |
b481de9c | 7258 | if (hw == NULL) { |
a3139c59 | 7259 | printk(KERN_ERR DRV_NAME "Can not allocate network device\n"); |
b481de9c ZY |
7260 | err = -ENOMEM; |
7261 | goto out; | |
7262 | } | |
b481de9c | 7263 | priv = hw->priv; |
90a30a02 | 7264 | SET_IEEE80211_DEV(hw, &pdev->dev); |
6440adb5 | 7265 | |
df878d8f KA |
7266 | if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) || |
7267 | (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) { | |
15b1687c WT |
7268 | IWL_ERR(priv, |
7269 | "invalid queues_num, should be between %d and %d\n", | |
7270 | IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES); | |
a3139c59 SO |
7271 | err = -EINVAL; |
7272 | goto out; | |
7273 | } | |
7274 | ||
90a30a02 KA |
7275 | /* |
7276 | * Disabling hardware scan means that mac80211 will perform scans | |
7277 | * "the hard way", rather than using device's scan. | |
7278 | */ | |
df878d8f | 7279 | if (iwl3945_mod_params.disable_hw_scan) { |
40b8ec0b SO |
7280 | IWL_DEBUG_INFO("Disabling hw_scan\n"); |
7281 | iwl3945_hw_ops.hw_scan = NULL; | |
7282 | } | |
7283 | ||
90a30a02 | 7284 | |
cee53ddb | 7285 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); |
90a30a02 KA |
7286 | priv->cfg = cfg; |
7287 | priv->pci_dev = pdev; | |
cee53ddb | 7288 | |
c8b0e6e1 | 7289 | #ifdef CONFIG_IWL3945_DEBUG |
df878d8f | 7290 | priv->debug_level = iwl3945_mod_params.debug; |
b481de9c ZY |
7291 | atomic_set(&priv->restrict_refcnt, 0); |
7292 | #endif | |
90a30a02 KA |
7293 | hw->rate_control_algorithm = "iwl-3945-rs"; |
7294 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); | |
7295 | ||
7296 | /* Select antenna (may be helpful if only one antenna is connected) */ | |
7297 | priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna; | |
b481de9c | 7298 | |
566bfe5a | 7299 | /* Tell mac80211 our characteristics */ |
605a0bd6 | 7300 | hw->flags = IEEE80211_HW_SIGNAL_DBM | |
566bfe5a | 7301 | IEEE80211_HW_NOISE_DBM; |
b481de9c | 7302 | |
f59ac048 | 7303 | hw->wiphy->interface_modes = |
f59ac048 LR |
7304 | BIT(NL80211_IFTYPE_STATION) | |
7305 | BIT(NL80211_IFTYPE_ADHOC); | |
7306 | ||
ea4a82dc LR |
7307 | hw->wiphy->fw_handles_regulatory = true; |
7308 | ||
6440adb5 | 7309 | /* 4 EDCA QOS priorities */ |
b481de9c ZY |
7310 | hw->queues = 4; |
7311 | ||
cee53ddb KA |
7312 | /*************************** |
7313 | * 2. Initializing PCI bus | |
7314 | * *************************/ | |
b481de9c ZY |
7315 | if (pci_enable_device(pdev)) { |
7316 | err = -ENODEV; | |
7317 | goto out_ieee80211_free_hw; | |
7318 | } | |
7319 | ||
7320 | pci_set_master(pdev); | |
7321 | ||
b481de9c ZY |
7322 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
7323 | if (!err) | |
7324 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
7325 | if (err) { | |
978785a3 | 7326 | IWL_WARN(priv, "No suitable DMA available.\n"); |
b481de9c ZY |
7327 | goto out_pci_disable_device; |
7328 | } | |
7329 | ||
7330 | pci_set_drvdata(pdev, priv); | |
7331 | err = pci_request_regions(pdev, DRV_NAME); | |
7332 | if (err) | |
7333 | goto out_pci_disable_device; | |
6440adb5 | 7334 | |
cee53ddb KA |
7335 | /*********************** |
7336 | * 3. Read REV Register | |
7337 | * ********************/ | |
b481de9c ZY |
7338 | priv->hw_base = pci_iomap(pdev, 0, 0); |
7339 | if (!priv->hw_base) { | |
7340 | err = -ENODEV; | |
7341 | goto out_pci_release_regions; | |
7342 | } | |
7343 | ||
7344 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
7345 | (unsigned long long) pci_resource_len(pdev, 0)); | |
7346 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
7347 | ||
cee53ddb KA |
7348 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
7349 | * PCI Tx retries from interfering with C3 CPU state */ | |
7350 | pci_write_config_byte(pdev, 0x41, 0x00); | |
b481de9c | 7351 | |
90a30a02 KA |
7352 | /* amp init */ |
7353 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
cee53ddb | 7354 | if (err < 0) { |
90a30a02 KA |
7355 | IWL_DEBUG_INFO("Failed to init APMG\n"); |
7356 | goto out_iounmap; | |
cee53ddb | 7357 | } |
b481de9c | 7358 | |
cee53ddb KA |
7359 | /*********************** |
7360 | * 4. Read EEPROM | |
7361 | * ********************/ | |
90a30a02 | 7362 | |
cee53ddb KA |
7363 | /* Read the EEPROM */ |
7364 | err = iwl3945_eeprom_init(priv); | |
7365 | if (err) { | |
15b1687c | 7366 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
cee53ddb KA |
7367 | goto out_remove_sysfs; |
7368 | } | |
7369 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
7370 | get_eeprom_mac(priv, priv->mac_addr); | |
7371 | IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr); | |
7372 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); | |
b481de9c | 7373 | |
cee53ddb KA |
7374 | /*********************** |
7375 | * 5. Setup HW Constants | |
7376 | * ********************/ | |
b481de9c | 7377 | /* Device-specific setup */ |
3832ec9d | 7378 | if (iwl3945_hw_set_hw_params(priv)) { |
15b1687c | 7379 | IWL_ERR(priv, "failed to set hw settings\n"); |
b481de9c ZY |
7380 | goto out_iounmap; |
7381 | } | |
7382 | ||
cee53ddb KA |
7383 | /*********************** |
7384 | * 6. Setup priv | |
7385 | * ********************/ | |
cee53ddb | 7386 | |
90a30a02 | 7387 | err = iwl3945_init_drv(priv); |
b481de9c | 7388 | if (err) { |
90a30a02 KA |
7389 | IWL_ERR(priv, "initializing driver failed\n"); |
7390 | goto out_free_geos; | |
b481de9c ZY |
7391 | } |
7392 | ||
978785a3 TW |
7393 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n", |
7394 | priv->cfg->name); | |
cee53ddb KA |
7395 | |
7396 | /*********************************** | |
7397 | * 7. Initialize Module Parameters | |
7398 | * **********************************/ | |
7399 | ||
7400 | /* Initialize module parameter values here */ | |
7401 | /* Disable radio (SW RF KILL) via parameter when loading driver */ | |
df878d8f | 7402 | if (iwl3945_mod_params.disable) { |
cee53ddb KA |
7403 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
7404 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
849e0dce RC |
7405 | } |
7406 | ||
cee53ddb KA |
7407 | |
7408 | /*********************** | |
7409 | * 8. Setup Services | |
7410 | * ********************/ | |
7411 | ||
7412 | spin_lock_irqsave(&priv->lock, flags); | |
7413 | iwl3945_disable_interrupts(priv); | |
7414 | spin_unlock_irqrestore(&priv->lock, flags); | |
7415 | ||
2663516d HS |
7416 | pci_enable_msi(priv->pci_dev); |
7417 | ||
7418 | err = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED, | |
7419 | DRV_NAME, priv); | |
7420 | if (err) { | |
7421 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
7422 | goto out_disable_msi; | |
7423 | } | |
7424 | ||
cee53ddb | 7425 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
849e0dce | 7426 | if (err) { |
15b1687c | 7427 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
90a30a02 | 7428 | goto out_release_irq; |
849e0dce | 7429 | } |
849e0dce | 7430 | |
cee53ddb KA |
7431 | iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6); |
7432 | iwl3945_setup_deferred_work(priv); | |
7433 | iwl3945_setup_rx_handlers(priv); | |
7434 | ||
cee53ddb | 7435 | /********************************* |
2663516d | 7436 | * 9. Setup and Register mac80211 |
cee53ddb KA |
7437 | * *******************************/ |
7438 | ||
5a66926a ZY |
7439 | err = ieee80211_register_hw(priv->hw); |
7440 | if (err) { | |
15b1687c | 7441 | IWL_ERR(priv, "Failed to register network device: %d\n", err); |
cee53ddb | 7442 | goto out_remove_sysfs; |
5a66926a | 7443 | } |
b481de9c | 7444 | |
5a66926a ZY |
7445 | priv->hw->conf.beacon_int = 100; |
7446 | priv->mac80211_registered = 1; | |
cee53ddb | 7447 | |
ebef2008 AK |
7448 | err = iwl3945_rfkill_init(priv); |
7449 | if (err) | |
15b1687c | 7450 | IWL_ERR(priv, "Unable to initialize RFKILL system. " |
ebef2008 AK |
7451 | "Ignoring error: %d\n", err); |
7452 | ||
2663516d HS |
7453 | /* Start monitoring the killswitch */ |
7454 | queue_delayed_work(priv->workqueue, &priv->rfkill_poll, | |
7455 | 2 * HZ); | |
7456 | ||
b481de9c ZY |
7457 | return 0; |
7458 | ||
cee53ddb KA |
7459 | out_remove_sysfs: |
7460 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); | |
849e0dce RC |
7461 | out_free_geos: |
7462 | iwl3945_free_geos(priv); | |
b481de9c ZY |
7463 | |
7464 | out_release_irq: | |
2663516d | 7465 | free_irq(priv->pci_dev->irq, priv); |
b481de9c ZY |
7466 | destroy_workqueue(priv->workqueue); |
7467 | priv->workqueue = NULL; | |
3832ec9d | 7468 | iwl3945_unset_hw_params(priv); |
2663516d HS |
7469 | out_disable_msi: |
7470 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
7471 | out_iounmap: |
7472 | pci_iounmap(pdev, priv->hw_base); | |
7473 | out_pci_release_regions: | |
7474 | pci_release_regions(pdev); | |
7475 | out_pci_disable_device: | |
7476 | pci_disable_device(pdev); | |
7477 | pci_set_drvdata(pdev, NULL); | |
7478 | out_ieee80211_free_hw: | |
7479 | ieee80211_free_hw(priv->hw); | |
7480 | out: | |
7481 | return err; | |
7482 | } | |
7483 | ||
c83dbf68 | 7484 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 7485 | { |
4a8a4322 | 7486 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 7487 | unsigned long flags; |
b481de9c ZY |
7488 | |
7489 | if (!priv) | |
7490 | return; | |
7491 | ||
7492 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
7493 | ||
b481de9c | 7494 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 7495 | |
d552bfb6 KA |
7496 | if (priv->mac80211_registered) { |
7497 | ieee80211_unregister_hw(priv->hw); | |
7498 | priv->mac80211_registered = 0; | |
7499 | } else { | |
7500 | iwl3945_down(priv); | |
7501 | } | |
b481de9c | 7502 | |
0359facc MA |
7503 | /* make sure we flush any pending irq or |
7504 | * tasklet for the driver | |
7505 | */ | |
7506 | spin_lock_irqsave(&priv->lock, flags); | |
7507 | iwl3945_disable_interrupts(priv); | |
7508 | spin_unlock_irqrestore(&priv->lock, flags); | |
7509 | ||
7510 | iwl_synchronize_irq(priv); | |
7511 | ||
bb8c093b | 7512 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 7513 | |
ebef2008 | 7514 | iwl3945_rfkill_unregister(priv); |
2663516d HS |
7515 | cancel_delayed_work(&priv->rfkill_poll); |
7516 | ||
bb8c093b | 7517 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
7518 | |
7519 | if (priv->rxq.bd) | |
51af3d3f | 7520 | iwl_rx_queue_free(priv, &priv->rxq); |
bb8c093b | 7521 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c | 7522 | |
3832ec9d | 7523 | iwl3945_unset_hw_params(priv); |
bb8c093b | 7524 | iwl3945_clear_stations_table(priv); |
b481de9c | 7525 | |
6ef89d0a MA |
7526 | /*netif_stop_queue(dev); */ |
7527 | flush_workqueue(priv->workqueue); | |
7528 | ||
bb8c093b | 7529 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
7530 | * priv->workqueue... so we can't take down the workqueue |
7531 | * until now... */ | |
7532 | destroy_workqueue(priv->workqueue); | |
7533 | priv->workqueue = NULL; | |
7534 | ||
2663516d HS |
7535 | free_irq(pdev->irq, priv); |
7536 | pci_disable_msi(pdev); | |
7537 | ||
b481de9c ZY |
7538 | pci_iounmap(pdev, priv->hw_base); |
7539 | pci_release_regions(pdev); | |
7540 | pci_disable_device(pdev); | |
7541 | pci_set_drvdata(pdev, NULL); | |
7542 | ||
849e0dce RC |
7543 | iwl3945_free_channel_map(priv); |
7544 | iwl3945_free_geos(priv); | |
f2c7e521 | 7545 | kfree(priv->scan39); |
b481de9c ZY |
7546 | if (priv->ibss_beacon) |
7547 | dev_kfree_skb(priv->ibss_beacon); | |
7548 | ||
7549 | ieee80211_free_hw(priv->hw); | |
7550 | } | |
7551 | ||
7552 | #ifdef CONFIG_PM | |
7553 | ||
bb8c093b | 7554 | static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 7555 | { |
4a8a4322 | 7556 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 7557 | |
e655b9f0 ZY |
7558 | if (priv->is_open) { |
7559 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
7560 | iwl3945_mac_stop(priv->hw); | |
7561 | priv->is_open = 1; | |
7562 | } | |
2663516d HS |
7563 | pci_save_state(pdev); |
7564 | pci_disable_device(pdev); | |
b481de9c ZY |
7565 | pci_set_power_state(pdev, PCI_D3hot); |
7566 | ||
b481de9c ZY |
7567 | return 0; |
7568 | } | |
7569 | ||
bb8c093b | 7570 | static int iwl3945_pci_resume(struct pci_dev *pdev) |
b481de9c | 7571 | { |
4a8a4322 | 7572 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 7573 | |
b481de9c | 7574 | pci_set_power_state(pdev, PCI_D0); |
2663516d HS |
7575 | pci_enable_device(pdev); |
7576 | pci_restore_state(pdev); | |
b481de9c | 7577 | |
e655b9f0 ZY |
7578 | if (priv->is_open) |
7579 | iwl3945_mac_start(priv->hw); | |
b481de9c | 7580 | |
e655b9f0 | 7581 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
7582 | return 0; |
7583 | } | |
7584 | ||
7585 | #endif /* CONFIG_PM */ | |
7586 | ||
ebef2008 | 7587 | /*************** RFKILL FUNCTIONS **********/ |
80fcc9e2 | 7588 | #ifdef CONFIG_IWL3945_RFKILL |
ebef2008 AK |
7589 | /* software rf-kill from user */ |
7590 | static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state) | |
7591 | { | |
4a8a4322 | 7592 | struct iwl_priv *priv = data; |
ebef2008 AK |
7593 | int err = 0; |
7594 | ||
80fcc9e2 | 7595 | if (!priv->rfkill) |
ebef2008 AK |
7596 | return 0; |
7597 | ||
7598 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
7599 | return 0; | |
7600 | ||
a96a27f9 | 7601 | IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state); |
ebef2008 AK |
7602 | mutex_lock(&priv->mutex); |
7603 | ||
7604 | switch (state) { | |
acdfe9b4 | 7605 | case RFKILL_STATE_UNBLOCKED: |
775a6e27 | 7606 | if (iwl_is_rfkill_hw(priv)) { |
ebef2008 | 7607 | err = -EBUSY; |
80fcc9e2 AG |
7608 | goto out_unlock; |
7609 | } | |
7610 | iwl3945_radio_kill_sw(priv, 0); | |
ebef2008 | 7611 | break; |
acdfe9b4 | 7612 | case RFKILL_STATE_SOFT_BLOCKED: |
ebef2008 | 7613 | iwl3945_radio_kill_sw(priv, 1); |
ebef2008 | 7614 | break; |
acdfe9b4 | 7615 | default: |
39aadf8c | 7616 | IWL_WARN(priv, "received unexpected RFKILL state %d\n", state); |
acdfe9b4 | 7617 | break; |
ebef2008 | 7618 | } |
80fcc9e2 | 7619 | out_unlock: |
ebef2008 AK |
7620 | mutex_unlock(&priv->mutex); |
7621 | ||
7622 | return err; | |
7623 | } | |
7624 | ||
4a8a4322 | 7625 | int iwl3945_rfkill_init(struct iwl_priv *priv) |
ebef2008 AK |
7626 | { |
7627 | struct device *device = wiphy_dev(priv->hw->wiphy); | |
7628 | int ret = 0; | |
7629 | ||
7630 | BUG_ON(device == NULL); | |
7631 | ||
7632 | IWL_DEBUG_RF_KILL("Initializing RFKILL.\n"); | |
80fcc9e2 AG |
7633 | priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN); |
7634 | if (!priv->rfkill) { | |
15b1687c | 7635 | IWL_ERR(priv, "Unable to allocate rfkill device.\n"); |
ebef2008 AK |
7636 | ret = -ENOMEM; |
7637 | goto error; | |
7638 | } | |
7639 | ||
80fcc9e2 AG |
7640 | priv->rfkill->name = priv->cfg->name; |
7641 | priv->rfkill->data = priv; | |
7642 | priv->rfkill->state = RFKILL_STATE_UNBLOCKED; | |
7643 | priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill; | |
7644 | priv->rfkill->user_claim_unsupported = 1; | |
ebef2008 | 7645 | |
80fcc9e2 AG |
7646 | priv->rfkill->dev.class->suspend = NULL; |
7647 | priv->rfkill->dev.class->resume = NULL; | |
ebef2008 | 7648 | |
80fcc9e2 | 7649 | ret = rfkill_register(priv->rfkill); |
ebef2008 | 7650 | if (ret) { |
15b1687c | 7651 | IWL_ERR(priv, "Unable to register rfkill: %d\n", ret); |
80fcc9e2 | 7652 | goto freed_rfkill; |
ebef2008 AK |
7653 | } |
7654 | ||
7655 | IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n"); | |
7656 | return ret; | |
7657 | ||
ebef2008 | 7658 | freed_rfkill: |
80fcc9e2 AG |
7659 | if (priv->rfkill != NULL) |
7660 | rfkill_free(priv->rfkill); | |
7661 | priv->rfkill = NULL; | |
ebef2008 AK |
7662 | |
7663 | error: | |
7664 | IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n"); | |
7665 | return ret; | |
7666 | } | |
7667 | ||
4a8a4322 | 7668 | void iwl3945_rfkill_unregister(struct iwl_priv *priv) |
ebef2008 | 7669 | { |
80fcc9e2 AG |
7670 | if (priv->rfkill) |
7671 | rfkill_unregister(priv->rfkill); | |
ebef2008 | 7672 | |
80fcc9e2 | 7673 | priv->rfkill = NULL; |
ebef2008 AK |
7674 | } |
7675 | ||
7676 | /* set rf-kill to the right state. */ | |
4a8a4322 | 7677 | void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv) |
ebef2008 AK |
7678 | { |
7679 | ||
80fcc9e2 AG |
7680 | if (!priv->rfkill) |
7681 | return; | |
7682 | ||
775a6e27 | 7683 | if (iwl_is_rfkill_hw(priv)) { |
80fcc9e2 | 7684 | rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED); |
ebef2008 | 7685 | return; |
80fcc9e2 | 7686 | } |
ebef2008 | 7687 | |
775a6e27 | 7688 | if (!iwl_is_rfkill_sw(priv)) |
80fcc9e2 | 7689 | rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED); |
ebef2008 | 7690 | else |
80fcc9e2 | 7691 | rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED); |
ebef2008 AK |
7692 | } |
7693 | #endif | |
7694 | ||
b481de9c ZY |
7695 | /***************************************************************************** |
7696 | * | |
7697 | * driver and module entry point | |
7698 | * | |
7699 | *****************************************************************************/ | |
7700 | ||
bb8c093b | 7701 | static struct pci_driver iwl3945_driver = { |
b481de9c | 7702 | .name = DRV_NAME, |
bb8c093b CH |
7703 | .id_table = iwl3945_hw_card_ids, |
7704 | .probe = iwl3945_pci_probe, | |
7705 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 7706 | #ifdef CONFIG_PM |
bb8c093b CH |
7707 | .suspend = iwl3945_pci_suspend, |
7708 | .resume = iwl3945_pci_resume, | |
b481de9c ZY |
7709 | #endif |
7710 | }; | |
7711 | ||
bb8c093b | 7712 | static int __init iwl3945_init(void) |
b481de9c ZY |
7713 | { |
7714 | ||
7715 | int ret; | |
7716 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
7717 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
7718 | |
7719 | ret = iwl3945_rate_control_register(); | |
7720 | if (ret) { | |
a3139c59 SO |
7721 | printk(KERN_ERR DRV_NAME |
7722 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
7723 | return ret; |
7724 | } | |
7725 | ||
bb8c093b | 7726 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c | 7727 | if (ret) { |
a3139c59 | 7728 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 7729 | goto error_register; |
b481de9c | 7730 | } |
b481de9c ZY |
7731 | |
7732 | return ret; | |
897e1cf2 | 7733 | |
897e1cf2 RC |
7734 | error_register: |
7735 | iwl3945_rate_control_unregister(); | |
7736 | return ret; | |
b481de9c ZY |
7737 | } |
7738 | ||
bb8c093b | 7739 | static void __exit iwl3945_exit(void) |
b481de9c | 7740 | { |
bb8c093b | 7741 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 7742 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
7743 | } |
7744 | ||
a0987a8d | 7745 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); |
25cb6cad | 7746 | |
df878d8f | 7747 | module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444); |
b481de9c | 7748 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
df878d8f | 7749 | module_param_named(disable, iwl3945_mod_params.disable, int, 0444); |
b481de9c | 7750 | MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])"); |
9c74d9fb SO |
7751 | module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444); |
7752 | MODULE_PARM_DESC(swcrypto, | |
7753 | "using software crypto (default 1 [software])\n"); | |
df878d8f | 7754 | module_param_named(debug, iwl3945_mod_params.debug, uint, 0444); |
b481de9c | 7755 | MODULE_PARM_DESC(debug, "debug output mask"); |
df878d8f | 7756 | module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444); |
b481de9c ZY |
7757 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
7758 | ||
df878d8f | 7759 | module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444); |
b481de9c ZY |
7760 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
7761 | ||
bb8c093b CH |
7762 | module_exit(iwl3945_exit); |
7763 | module_init(iwl3945_init); |