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pktgen: multiqueue etc.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
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1053d35f
RR		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
fd4abac5 30#include <linux/etherdevice.h>
1053d35f
RR		 31#include <net/mac80211.h>
32#include "iwl-eeprom.h"
33#include "iwl-dev.h"
34#include "iwl-core.h"
35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38
30e553e3
TW		 39static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57};
58
30e553e3 59
1053d35f
RR		 60/**
61 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
62 *
63 * Does NOT advance any TFD circular buffer read/write indexes
64 * Does NOT free the TFD itself (which is within circular buffer)
65 */
16466903 66int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
1053d35f
RR		 67{
68 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
69 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
70 struct pci_dev *dev = priv->pci_dev;
71 int i;
72 int counter = 0;
73 int index, is_odd;
74
75 /* Host command buffers stay mapped in memory, nothing to clean */
76 if (txq->q.id == IWL_CMD_QUEUE_NUM)
77 return 0;
78
79 /* Sanity check on number of chunks */
80 counter = IWL_GET_BITS(*bd, num_tbs);
81 if (counter > MAX_NUM_OF_TBS) {
82 IWL_ERROR("Too many chunks: %i\n", counter);
83 /* @todo issue fatal error, it is quite serious situation */
84 return 0;
85 }
86
87 /* Unmap chunks, if any.
88 * TFD info for odd chunks is different format than for even chunks. */
89 for (i = 0; i < counter; i++) {
90 index = i / 2;
91 is_odd = i & 0x1;
92
93 if (is_odd)
94 pci_unmap_single(
95 dev,
96 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
97 (IWL_GET_BITS(bd->pa[index],
98 tb2_addr_hi20) << 16),
99 IWL_GET_BITS(bd->pa[index], tb2_len),
100 PCI_DMA_TODEVICE);
101
102 else if (i > 0)
103 pci_unmap_single(dev,
104 le32_to_cpu(bd->pa[index].tb1_addr),
105 IWL_GET_BITS(bd->pa[index], tb1_len),
106 PCI_DMA_TODEVICE);
107
108 /* Free SKB, if any, for this chunk */
109 if (txq->txb[txq->q.read_ptr].skb[i]) {
110 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
111
112 dev_kfree_skb(skb);
113 txq->txb[txq->q.read_ptr].skb[i] = NULL;
114 }
115 }
116 return 0;
117}
118EXPORT_SYMBOL(iwl_hw_txq_free_tfd);
119
fd4abac5
TW		 120
121int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
122 dma_addr_t addr, u16 len)
123{
124 int index, is_odd;
125 struct iwl_tfd_frame *tfd = ptr;
126 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
127
128 /* Each TFD can point to a maximum 20 Tx buffers */
129 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
130 IWL_ERROR("Error can not send more than %d chunks\n",
131 MAX_NUM_OF_TBS);
132 return -EINVAL;
133 }
134
135 index = num_tbs / 2;
136 is_odd = num_tbs & 0x1;
137
138 if (!is_odd) {
139 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
140 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
141 iwl_get_dma_hi_address(addr));
142 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
143 } else {
144 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
145 (u32) (addr & 0xffff));
146 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
147 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
148 }
149
150 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
151
152 return 0;
153}
154EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd);
155
156/**
157 * iwl_txq_update_write_ptr - Send new write index to hardware
158 */
159int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
160{
161 u32 reg = 0;
162 int ret = 0;
163 int txq_id = txq->q.id;
164
165 if (txq->need_update == 0)
166 return ret;
167
168 /* if we're trying to save power */
169 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
170 /* wake up nic if it's powered down ...
171 * uCode will wake up, and interrupt us again, so next
172 * time we'll skip this part. */
173 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
174
175 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
176 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
177 iwl_set_bit(priv, CSR_GP_CNTRL,
178 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
179 return ret;
180 }
181
182 /* restore this queue's parameters in nic hardware. */
183 ret = iwl_grab_nic_access(priv);
184 if (ret)
185 return ret;
186 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
187 txq->q.write_ptr | (txq_id << 8));
188 iwl_release_nic_access(priv);
189
190 /* else not in power-save mode, uCode will never sleep when we're
191 * trying to tx (during RFKILL, we're not trying to tx). */
192 } else
193 iwl_write32(priv, HBUS_TARG_WRPTR,
194 txq->q.write_ptr | (txq_id << 8));
195
196 txq->need_update = 0;
197
198 return ret;
199}
200EXPORT_SYMBOL(iwl_txq_update_write_ptr);
201
202
1053d35f
RR		 203/**
204 * iwl_tx_queue_free - Deallocate DMA queue.
205 * @txq: Transmit queue to deallocate.
206 *
207 * Empty queue by removing and destroying all BD's.
208 * Free all buffers.
209 * 0-fill, but do not free "txq" descriptor structure.
210 */
da99c4b6 211static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
1053d35f 212{
da99c4b6 213 struct iwl_tx_queue *txq = &priv->txq[txq_id];
443cfd45 214 struct iwl_queue *q = &txq->q;
1053d35f 215 struct pci_dev *dev = priv->pci_dev;
da99c4b6 216 int i, slots_num, len;
1053d35f
RR		 217
218 if (q->n_bd == 0)
219 return;
220
221 /* first, empty all BD's */
222 for (; q->write_ptr != q->read_ptr;
223 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
224 iwl_hw_txq_free_tfd(priv, txq);
225
226 len = sizeof(struct iwl_cmd) * q->n_window;
227 if (q->id == IWL_CMD_QUEUE_NUM)
228 len += IWL_MAX_SCAN_SIZE;
229
230 /* De-alloc array of command/tx buffers */
da99c4b6
GG		 231 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
232 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
233 for (i = 0; i < slots_num; i++)
234 kfree(txq->cmd[i]);
235 if (txq_id == IWL_CMD_QUEUE_NUM)
236 kfree(txq->cmd[slots_num]);
1053d35f
RR		 237
238 /* De-alloc circular buffer of TFDs */
239 if (txq->q.n_bd)
240 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
241 txq->q.n_bd, txq->bd, txq->q.dma_addr);
242
243 /* De-alloc array of per-TFD driver data */
244 kfree(txq->txb);
245 txq->txb = NULL;
246
247 /* 0-fill queue descriptor structure */
248 memset(txq, 0, sizeof(*txq));
249}
250
fd4abac5
TW		 251/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
252 * DMA services
253 *
254 * Theory of operation
255 *
256 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
257 * of buffer descriptors, each of which points to one or more data buffers for
258 * the device to read from or fill. Driver and device exchange status of each
259 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
260 * entries in each circular buffer, to protect against confusing empty and full
261 * queue states.
262 *
263 * The device reads or writes the data in the queues via the device's several
264 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
265 *
266 * For Tx queue, there are low mark and high mark limits. If, after queuing
267 * the packet for Tx, free space become < low mark, Tx queue stopped. When
268 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
269 * Tx queue resumed.
270 *
271 * See more detailed info in iwl-4965-hw.h.
272 ***************************************************/
273
274int iwl_queue_space(const struct iwl_queue *q)
275{
276 int s = q->read_ptr - q->write_ptr;
277
278 if (q->read_ptr > q->write_ptr)
279 s -= q->n_bd;
280
281 if (s <= 0)
282 s += q->n_window;
283 /* keep some reserve to not confuse empty and full situations */
284 s -= 2;
285 if (s < 0)
286 s = 0;
287 return s;
288}
289EXPORT_SYMBOL(iwl_queue_space);
290
291
1053d35f
RR		 292/**
293 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
294 */
443cfd45 295static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR		 296 int count, int slots_num, u32 id)
297{
298 q->n_bd = count;
299 q->n_window = slots_num;
300 q->id = id;
301
302 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
303 * and iwl_queue_dec_wrap are broken. */
304 BUG_ON(!is_power_of_2(count));
305
306 /* slots_num must be power-of-two size, otherwise
307 * get_cmd_index is broken. */
308 BUG_ON(!is_power_of_2(slots_num));
309
310 q->low_mark = q->n_window / 4;
311 if (q->low_mark < 4)
312 q->low_mark = 4;
313
314 q->high_mark = q->n_window / 8;
315 if (q->high_mark < 2)
316 q->high_mark = 2;
317
318 q->write_ptr = q->read_ptr = 0;
319
320 return 0;
321}
322
323/**
324 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
325 */
326static int iwl_tx_queue_alloc(struct iwl_priv *priv,
16466903 327 struct iwl_tx_queue *txq, u32 id)
1053d35f
RR		 328{
329 struct pci_dev *dev = priv->pci_dev;
330
331 /* Driver private data, only for Tx (not command) queues,
332 * not shared with device. */
333 if (id != IWL_CMD_QUEUE_NUM) {
334 txq->txb = kmalloc(sizeof(txq->txb[0]) *
335 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
336 if (!txq->txb) {
337 IWL_ERROR("kmalloc for auxiliary BD "
338 "structures failed\n");
339 goto error;
340 }
341 } else
342 txq->txb = NULL;
343
344 /* Circular buffer of transmit frame descriptors (TFDs),
345 * shared with device */
346 txq->bd = pci_alloc_consistent(dev,
347 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
348 &txq->q.dma_addr);
349
350 if (!txq->bd) {
351 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
352 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
353 goto error;
354 }
355 txq->q.id = id;
356
357 return 0;
358
359 error:
360 kfree(txq->txb);
361 txq->txb = NULL;
362
363 return -ENOMEM;
364}
365
366/*
367 * Tell nic where to find circular buffer of Tx Frame Descriptors for
368 * given Tx queue, and enable the DMA channel used for that queue.
369 *
370 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
371 * channels supported in hardware.
372 */
373static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
16466903 374 struct iwl_tx_queue *txq)
1053d35f
RR		 375{
376 int rc;
377 unsigned long flags;
378 int txq_id = txq->q.id;
379
380 spin_lock_irqsave(&priv->lock, flags);
381 rc = iwl_grab_nic_access(priv);
382 if (rc) {
383 spin_unlock_irqrestore(&priv->lock, flags);
384 return rc;
385 }
386
387 /* Circular buffer (TFD queue in DRAM) physical base address */
388 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
389 txq->q.dma_addr >> 8);
390
391 /* Enable DMA channel, using same id as for TFD queue */
392 iwl_write_direct32(
393 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
394 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
395 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
396 iwl_release_nic_access(priv);
397 spin_unlock_irqrestore(&priv->lock, flags);
398
399 return 0;
400}
401
402/**
403 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
404 */
405static int iwl_tx_queue_init(struct iwl_priv *priv,
16466903 406 struct iwl_tx_queue *txq,
1053d35f
RR		 407 int slots_num, u32 txq_id)
408{
da99c4b6 409 int i, len;
1053d35f
RR		 410 int rc = 0;
411
412 /*
413 * Alloc buffer array for commands (Tx or other types of commands).
414 * For the command queue (#4), allocate command space + one big
415 * command for scan, since scan command is very huge; the system will
416 * not have two scans at the same time, so only one is needed.
417 * For normal Tx queues (all other queues), no super-size command
418 * space is needed.
419 */
da99c4b6
GG		 420 len = sizeof(struct iwl_cmd);
421 for (i = 0; i <= slots_num; i++) {
422 if (i == slots_num) {
423 if (txq_id == IWL_CMD_QUEUE_NUM)
424 len += IWL_MAX_SCAN_SIZE;
425 else
426 continue;
427 }
428
429 txq->cmd[i] = kmalloc(len, GFP_KERNEL | GFP_DMA);
430 if (!txq->cmd[i])
431 return -ENOMEM;
432 }
1053d35f
RR		 433
434 /* Alloc driver data array and TFD circular buffer */
435 rc = iwl_tx_queue_alloc(priv, txq, txq_id);
436 if (rc) {
da99c4b6
GG		 437 for (i = 0; i < slots_num; i++)
438 kfree(txq->cmd[i]);
1053d35f
RR		 439
440 return -ENOMEM;
441 }
442 txq->need_update = 0;
443
444 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
445 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
446 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
447
448 /* Initialize queue's high/low-water marks, and head/tail indexes */
449 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
450
451 /* Tell device where to find queue */
452 iwl_hw_tx_queue_init(priv, txq);
453
454 return 0;
455}
da1bc453
TW		 456/**
457 * iwl_hw_txq_ctx_free - Free TXQ Context
458 *
459 * Destroy all TX DMA queues and structures
460 */
461void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
462{
463 int txq_id;
464
465 /* Tx queues */
466 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
da99c4b6 467 iwl_tx_queue_free(priv, txq_id);
da1bc453
TW		 468
469 /* Keep-warm buffer */
470 iwl_kw_free(priv);
471}
472EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
473
1053d35f
RR		 474
475/**
476 * iwl_txq_ctx_reset - Reset TX queue context
477 * Destroys all DMA structures and initialise them again
478 *
479 * @param priv
480 * @return error code
481 */
482int iwl_txq_ctx_reset(struct iwl_priv *priv)
483{
484 int ret = 0;
485 int txq_id, slots_num;
da1bc453 486 unsigned long flags;
1053d35f
RR		 487
488 iwl_kw_free(priv);
489
490 /* Free all tx/cmd queues and keep-warm buffer */
491 iwl_hw_txq_ctx_free(priv);
492
493 /* Alloc keep-warm buffer */
494 ret = iwl_kw_alloc(priv);
495 if (ret) {
496 IWL_ERROR("Keep Warm allocation failed");
497 goto error_kw;
498 }
da1bc453
TW		 499 spin_lock_irqsave(&priv->lock, flags);
500 ret = iwl_grab_nic_access(priv);
501 if (unlikely(ret)) {
502 spin_unlock_irqrestore(&priv->lock, flags);
503 goto error_reset;
504 }
1053d35f
RR		 505
506 /* Turn off all Tx DMA fifos */
da1bc453
TW		 507 priv->cfg->ops->lib->txq_set_sched(priv, 0);
508
509 iwl_release_nic_access(priv);
510 spin_unlock_irqrestore(&priv->lock, flags);
511
1053d35f
RR		 512
513 /* Tell nic where to find the keep-warm buffer */
514 ret = iwl_kw_init(priv);
515 if (ret) {
516 IWL_ERROR("kw_init failed\n");
517 goto error_reset;
518 }
519
da1bc453 520 /* Alloc and init all Tx queues, including the command queue (#4) */
1053d35f
RR		 521 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
522 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
523 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
524 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
525 txq_id);
526 if (ret) {
527 IWL_ERROR("Tx %d queue init failed\n", txq_id);
528 goto error;
529 }
530 }
531
532 return ret;
533
534 error:
535 iwl_hw_txq_ctx_free(priv);
536 error_reset:
537 iwl_kw_free(priv);
538 error_kw:
539 return ret;
540}
da1bc453
TW		 541/**
542 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
543 */
544void iwl_txq_ctx_stop(struct iwl_priv *priv)
545{
546
547 int txq_id;
548 unsigned long flags;
549
550
551 /* Turn off all Tx DMA fifos */
552 spin_lock_irqsave(&priv->lock, flags);
553 if (iwl_grab_nic_access(priv)) {
554 spin_unlock_irqrestore(&priv->lock, flags);
555 return;
556 }
557
558 priv->cfg->ops->lib->txq_set_sched(priv, 0);
559
560 /* Stop each Tx DMA channel, and wait for it to be idle */
561 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
562 iwl_write_direct32(priv,
563 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
564 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
565 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
566 (txq_id), 200);
567 }
568 iwl_release_nic_access(priv);
569 spin_unlock_irqrestore(&priv->lock, flags);
570
571 /* Deallocate memory for all Tx queues */
572 iwl_hw_txq_ctx_free(priv);
573}
574EXPORT_SYMBOL(iwl_txq_ctx_stop);
fd4abac5
TW		 575
576/*
577 * handle build REPLY_TX command notification.
578 */
579static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
580 struct iwl_tx_cmd *tx_cmd,
e039fa4a 581 struct ieee80211_tx_info *info,
fd4abac5
TW		 582 struct ieee80211_hdr *hdr,
583 int is_unicast, u8 std_id)
584{
fd7c8a40 585 __le16 fc = hdr->frame_control;
fd4abac5
TW		 586 __le32 tx_flags = tx_cmd->tx_flags;
587
588 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 589 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
fd4abac5 590 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 591 if (ieee80211_is_mgmt(fc))
fd4abac5 592 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 593 if (ieee80211_is_probe_resp(fc) &&
fd4abac5
TW		 594 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
595 tx_flags |= TX_CMD_FLG_TSF_MSK;
596 } else {
597 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
598 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
599 }
600
fd7c8a40 601 if (ieee80211_is_back_req(fc))
fd4abac5
TW		 602 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
603
604
605 tx_cmd->sta_id = std_id;
8b7b1e05 606 if (ieee80211_has_morefrags(fc))
fd4abac5
TW		 607 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
608
fd7c8a40
HH		 609 if (ieee80211_is_data_qos(fc)) {
610 u8 *qc = ieee80211_get_qos_ctl(hdr);
fd4abac5
TW		 611 tx_cmd->tid_tspec = qc[0] & 0xf;
612 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
613 } else {
614 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
615 }
616
a326a5d0 617 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
fd4abac5
TW		 618
619 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
620 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
621
622 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 623 if (ieee80211_is_mgmt(fc)) {
624 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 625 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
626 else
627 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
628 } else {
629 tx_cmd->timeout.pm_frame_timeout = 0;
630 }
631
632 tx_cmd->driver_txop = 0;
633 tx_cmd->tx_flags = tx_flags;
634 tx_cmd->next_frame_len = 0;
635}
636
637#define RTS_HCCA_RETRY_LIMIT 3
638#define RTS_DFAULT_RETRY_LIMIT 60
639
640static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
641 struct iwl_tx_cmd *tx_cmd,
e039fa4a 642 struct ieee80211_tx_info *info,
fd7c8a40 643 __le16 fc, int sta_id,
fd4abac5
TW		 644 int is_hcca)
645{
646 u8 rts_retry_limit = 0;
647 u8 data_retry_limit = 0;
648 u8 rate_plcp;
649 u16 rate_flags = 0;
2e92e6f2
JB		 650 int rate_idx;
651
e039fa4a 652 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
2e92e6f2 653 IWL_RATE_COUNT - 1);
fd4abac5
TW		 654
655 rate_plcp = iwl_rates[rate_idx].plcp;
656
657 rts_retry_limit = (is_hcca) ?
658 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
659
660 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
661 rate_flags |= RATE_MCS_CCK_MSK;
662
663
fd7c8a40 664 if (ieee80211_is_probe_resp(fc)) {
fd4abac5
TW		 665 data_retry_limit = 3;
666 if (data_retry_limit < rts_retry_limit)
667 rts_retry_limit = data_retry_limit;
668 } else
669 data_retry_limit = IWL_DEFAULT_TX_RETRY;
670
671 if (priv->data_retry_limit != -1)
672 data_retry_limit = priv->data_retry_limit;
673
674
675 if (ieee80211_is_data(fc)) {
676 tx_cmd->initial_rate_index = 0;
677 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
678 } else {
fd7c8a40
HH		 679 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
680 case cpu_to_le16(IEEE80211_STYPE_AUTH):
681 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
682 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
683 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
fd4abac5
TW		 684 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
685 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
686 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
687 }
688 break;
689 default:
690 break;
691 }
692
693 /* Alternate between antenna A and B for successive frames */
694 if (priv->use_ant_b_for_management_frame) {
695 priv->use_ant_b_for_management_frame = 0;
696 rate_flags |= RATE_MCS_ANT_B_MSK;
697 } else {
698 priv->use_ant_b_for_management_frame = 1;
699 rate_flags |= RATE_MCS_ANT_A_MSK;
700 }
701 }
702
703 tx_cmd->rts_retry_limit = rts_retry_limit;
704 tx_cmd->data_retry_limit = data_retry_limit;
e7d326ac 705 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
fd4abac5
TW		 706}
707
708static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
e039fa4a 709 struct ieee80211_tx_info *info,
fd4abac5
TW		 710 struct iwl_tx_cmd *tx_cmd,
711 struct sk_buff *skb_frag,
712 int sta_id)
713{
e039fa4a 714 struct ieee80211_key_conf *keyconf = info->control.hw_key;
fd4abac5 715
ccc038ab 716 switch (keyconf->alg) {
fd4abac5
TW		 717 case ALG_CCMP:
718 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
ccc038ab 719 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
e039fa4a 720 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 721 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
722 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
723 break;
724
725 case ALG_TKIP:
726 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
ccc038ab 727 ieee80211_get_tkip_key(keyconf, skb_frag,
fd4abac5
TW		 728 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
729 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
730 break;
731
732 case ALG_WEP:
fd4abac5 733 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
ccc038ab
EG		 734 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
735
736 if (keyconf->keylen == WEP_KEY_LEN_128)
737 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
738
739 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
fd4abac5
TW		 740
741 IWL_DEBUG_TX("Configuring packet for WEP encryption "
ccc038ab 742 "with key %d\n", keyconf->keyidx);
fd4abac5
TW		 743 break;
744
745 default:
ccc038ab 746 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
fd4abac5
TW		 747 break;
748 }
749}
750
751static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
752{
753 /* 0 - mgmt, 1 - cnt, 2 - data */
754 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
755 priv->tx_stats[idx].cnt++;
756 priv->tx_stats[idx].bytes += len;
757}
758
759/*
760 * start REPLY_TX command process
761 */
e039fa4a 762int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
fd4abac5
TW		 763{
764 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 765 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fd4abac5
TW		 766 struct iwl_tfd_frame *tfd;
767 u32 *control_flags;
e2530083 768 int txq_id = skb_get_queue_mapping(skb);
fd4abac5
TW		 769 struct iwl_tx_queue *txq = NULL;
770 struct iwl_queue *q = NULL;
771 dma_addr_t phys_addr;
772 dma_addr_t txcmd_phys;
773 dma_addr_t scratch_phys;
774 struct iwl_cmd *out_cmd = NULL;
775 struct iwl_tx_cmd *tx_cmd;
776 u16 len, idx, len_org;
777 u16 seq_number = 0;
778 u8 id, hdr_len, unicast;
779 u8 sta_id;
fd7c8a40 780 __le16 fc;
fd4abac5
TW		 781 u8 wait_write_ptr = 0;
782 u8 tid = 0;
783 u8 *qc = NULL;
784 unsigned long flags;
785 int ret;
786
787 spin_lock_irqsave(&priv->lock, flags);
788 if (iwl_is_rfkill(priv)) {
789 IWL_DEBUG_DROP("Dropping - RF KILL\n");
790 goto drop_unlock;
791 }
792
793 if (!priv->vif) {
794 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
795 goto drop_unlock;
796 }
797
e039fa4a 798 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
2e92e6f2 799 IWL_INVALID_RATE) {
fd4abac5
TW		 800 IWL_ERROR("ERROR: No TX rate available.\n");
801 goto drop_unlock;
802 }
803
804 unicast = !is_multicast_ether_addr(hdr->addr1);
805 id = 0;
806
fd7c8a40 807 fc = hdr->frame_control;
fd4abac5
TW		 808
809#ifdef CONFIG_IWLWIFI_DEBUG
810 if (ieee80211_is_auth(fc))
811 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 812 else if (ieee80211_is_assoc_req(fc))
fd4abac5 813 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 814 else if (ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 815 IWL_DEBUG_TX("Sending REASSOC frame\n");
816#endif
817
818 /* drop all data frame if we are not associated */
fd7c8a40 819 if (ieee80211_is_data(fc) &&
fd4abac5
TW		 820 (!iwl_is_associated(priv) ||
821 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) ||
822 !priv->assoc_station_added)) {
823 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
824 goto drop_unlock;
825 }
826
827 spin_unlock_irqrestore(&priv->lock, flags);
828
fd7c8a40 829 hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc));
fd4abac5
TW		 830
831 /* Find (or create) index into station table for destination station */
832 sta_id = iwl_get_sta_id(priv, hdr);
833 if (sta_id == IWL_INVALID_STATION) {
834 DECLARE_MAC_BUF(mac);
835
836 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
837 print_mac(mac, hdr->addr1));
838 goto drop;
839 }
840
841 IWL_DEBUG_TX("station Id %d\n", sta_id);
842
fd7c8a40
HH		 843 if (ieee80211_is_data_qos(fc)) {
844 qc = ieee80211_get_qos_ctl(hdr);
fd4abac5
TW		 845 tid = qc[0] & 0xf;
846 seq_number = priv->stations[sta_id].tid[tid].seq_number &
847 IEEE80211_SCTL_SEQ;
848 hdr->seq_ctrl = cpu_to_le16(seq_number) |
849 (hdr->seq_ctrl &
850 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
851 seq_number += 0x10;
fd4abac5 852 /* aggregation is on for this <sta,tid> */
e039fa4a 853 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 854 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
855 priv->stations[sta_id].tid[tid].tfds_in_queue++;
fd4abac5
TW		 856 }
857
858 /* Descriptor for chosen Tx queue */
859 txq = &priv->txq[txq_id];
860 q = &txq->q;
861
862 spin_lock_irqsave(&priv->lock, flags);
863
864 /* Set up first empty TFD within this queue's circular TFD buffer */
865 tfd = &txq->bd[q->write_ptr];
866 memset(tfd, 0, sizeof(*tfd));
867 control_flags = (u32 *) tfd;
868 idx = get_cmd_index(q, q->write_ptr, 0);
869
870 /* Set up driver data for this TFD */
871 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
872 txq->txb[q->write_ptr].skb[0] = skb;
fd4abac5
TW		 873
874 /* Set up first empty entry in queue's array of Tx/cmd buffers */
da99c4b6 875 out_cmd = txq->cmd[idx];
fd4abac5
TW		 876 tx_cmd = &out_cmd->cmd.tx;
877 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
878 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
879
880 /*
881 * Set up the Tx-command (not MAC!) header.
882 * Store the chosen Tx queue and TFD index within the sequence field;
883 * after Tx, uCode's Tx response will return this value so driver can
884 * locate the frame within the tx queue and do post-tx processing.
885 */
886 out_cmd->hdr.cmd = REPLY_TX;
887 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
888 INDEX_TO_SEQ(q->write_ptr)));
889
890 /* Copy MAC header from skb into command buffer */
891 memcpy(tx_cmd->hdr, hdr, hdr_len);
892
893 /*
894 * Use the first empty entry in this queue's command buffer array
895 * to contain the Tx command and MAC header concatenated together
896 * (payload data will be in another buffer).
897 * Size of this varies, due to varying MAC header length.
898 * If end is not dword aligned, we'll have 2 extra bytes at the end
899 * of the MAC header (device reads on dword boundaries).
900 * We'll tell device about this padding later.
901 */
902 len = sizeof(struct iwl_tx_cmd) +
903 sizeof(struct iwl_cmd_header) + hdr_len;
904
905 len_org = len;
906 len = (len + 3) & ~3;
907
908 if (len_org != len)
909 len_org = 1;
910 else
911 len_org = 0;
912
913 /* Physical address of this Tx command's header (not MAC header!),
914 * within command buffer array. */
da99c4b6
GG		 915 txcmd_phys = pci_map_single(priv->pci_dev, out_cmd,
916 sizeof(struct iwl_cmd), PCI_DMA_TODEVICE);
917 txcmd_phys += offsetof(struct iwl_cmd, hdr);
fd4abac5
TW		 918
919 /* Add buffer containing Tx command and MAC(!) header to TFD's
920 * first entry */
921 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
922
d0f09804 923 if (info->control.hw_key)
e039fa4a 924 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
fd4abac5
TW		 925
926 /* Set up TFD's 2nd entry to point directly to remainder of skb,
927 * if any (802.11 null frames have no payload). */
928 len = skb->len - hdr_len;
929 if (len) {
930 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
931 len, PCI_DMA_TODEVICE);
932 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
933 }
934
935 /* Tell NIC about any 2-byte padding after MAC header */
936 if (len_org)
937 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
938
939 /* Total # bytes to be transmitted */
940 len = (u16)skb->len;
941 tx_cmd->len = cpu_to_le16(len);
942 /* TODO need this for burst mode later on */
e039fa4a 943 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
fd4abac5
TW		 944
945 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 946 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
fd4abac5 947
fd7c8a40 948 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
fd4abac5
TW		 949
950 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
951 offsetof(struct iwl_tx_cmd, scratch);
952 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
953 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
954
8b7b1e05 955 if (!ieee80211_has_morefrags(hdr->frame_control)) {
fd4abac5
TW		 956 txq->need_update = 1;
957 if (qc)
958 priv->stations[sta_id].tid[tid].seq_number = seq_number;
959 } else {
960 wait_write_ptr = 1;
961 txq->need_update = 0;
962 }
963
964 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
965
966 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
967
968 /* Set up entry for this TFD in Tx byte-count array */
969 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
970
971 /* Tell device the write index *just past* this latest filled TFD */
972 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
973 ret = iwl_txq_update_write_ptr(priv, txq);
974 spin_unlock_irqrestore(&priv->lock, flags);
975
976 if (ret)
977 return ret;
978
143b09ef 979 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
fd4abac5
TW		 980 if (wait_write_ptr) {
981 spin_lock_irqsave(&priv->lock, flags);
982 txq->need_update = 1;
983 iwl_txq_update_write_ptr(priv, txq);
984 spin_unlock_irqrestore(&priv->lock, flags);
143b09ef
TW		 985 } else {
986 ieee80211_stop_queue(priv->hw,
987 skb_get_queue_mapping(skb));
fd4abac5 988 }
fd4abac5
TW		 989 }
990
991 return 0;
992
993drop_unlock:
994 spin_unlock_irqrestore(&priv->lock, flags);
995drop:
996 return -1;
997}
998EXPORT_SYMBOL(iwl_tx_skb);
999
1000/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1001
1002/**
1003 * iwl_enqueue_hcmd - enqueue a uCode command
1004 * @priv: device private data point
1005 * @cmd: a point to the ucode command structure
1006 *
1007 * The function returns < 0 values to indicate the operation is
1008 * failed. On success, it turns the index (> 0) of command in the
1009 * command queue.
1010 */
1011int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1012{
1013 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1014 struct iwl_queue *q = &txq->q;
1015 struct iwl_tfd_frame *tfd;
1016 u32 *control_flags;
1017 struct iwl_cmd *out_cmd;
1018 u32 idx;
1019 u16 fix_size;
1020 dma_addr_t phys_addr;
da99c4b6 1021 int len, ret;
fd4abac5
TW		 1022 unsigned long flags;
1023
1024 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1025 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1026
1027 /* If any of the command structures end up being larger than
1028 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1029 * we will need to increase the size of the TFD entries */
1030 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1031 !(cmd->meta.flags & CMD_SIZE_HUGE));
1032
1033 if (iwl_is_rfkill(priv)) {
1034 IWL_DEBUG_INFO("Not sending command - RF KILL");
1035 return -EIO;
1036 }
1037
1038 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1039 IWL_ERROR("No space for Tx\n");
1040 return -ENOSPC;
1041 }
1042
1043 spin_lock_irqsave(&priv->hcmd_lock, flags);
1044
1045 tfd = &txq->bd[q->write_ptr];
1046 memset(tfd, 0, sizeof(*tfd));
1047
1048 control_flags = (u32 *) tfd;
1049
1050 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
da99c4b6 1051 out_cmd = txq->cmd[idx];
fd4abac5
TW		 1052
1053 out_cmd->hdr.cmd = cmd->id;
1054 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1055 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1056
1057 /* At this point, the out_cmd now has all of the incoming cmd
1058 * information */
1059
1060 out_cmd->hdr.flags = 0;
1061 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1062 INDEX_TO_SEQ(q->write_ptr));
1063 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
1064 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
da99c4b6
GG		 1065 len = (idx == TFD_CMD_SLOTS) ?
1066 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
1067 phys_addr = pci_map_single(priv->pci_dev, out_cmd, len,
1068 PCI_DMA_TODEVICE);
1069 phys_addr += offsetof(struct iwl_cmd, hdr);
fd4abac5
TW		 1070 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1071
1072 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1073 "%d bytes at %d[%d]:%d\n",
1074 get_cmd_string(out_cmd->hdr.cmd),
1075 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1076 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1077
1078 txq->need_update = 1;
1079
1080 /* Set up entry in queue's byte count circular buffer */
1081 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1082
1083 /* Increment and update queue's write index */
1084 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1085 ret = iwl_txq_update_write_ptr(priv, txq);
1086
1087 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1088 return ret ? ret : idx;
1089}
1090
17b88929
TW		 1091int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1092{
1093 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1094 struct iwl_queue *q = &txq->q;
1095 struct iwl_tx_info *tx_info;
1096 int nfreed = 0;
1097
1098 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1099 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1100 "is out of range [0-%d] %d %d.\n", txq_id,
1101 index, q->n_bd, q->write_ptr, q->read_ptr);
1102 return 0;
1103 }
1104
1105 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1106 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1107
1108 tx_info = &txq->txb[txq->q.read_ptr];
1109 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1110 tx_info->skb[0] = NULL;
17b88929 1111
972cf447
TW		 1112 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1113 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1114
1115 iwl_hw_txq_free_tfd(priv, txq);
17b88929
TW		 1116 nfreed++;
1117 }
1118 return nfreed;
1119}
1120EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1121
1122
1123/**
1124 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1125 *
1126 * When FW advances 'R' index, all entries between old and new 'R' index
1127 * need to be reclaimed. As result, some free space forms. If there is
1128 * enough free space (> low mark), wake the stack that feeds us.
1129 */
1130static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1131{
1132 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1133 struct iwl_queue *q = &txq->q;
da99c4b6
GG		 1134 struct iwl_tfd_frame *bd = &txq->bd[index];
1135 dma_addr_t dma_addr;
1136 int is_odd, buf_len;
17b88929
TW		 1137 int nfreed = 0;
1138
1139 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1140 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1141 "is out of range [0-%d] %d %d.\n", txq_id,
1142 index, q->n_bd, q->write_ptr, q->read_ptr);
1143 return;
1144 }
1145
1146 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1147 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1148
1149 if (nfreed > 1) {
1150 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
1151 q->write_ptr, q->read_ptr);
1152 queue_work(priv->workqueue, &priv->restart);
1153 }
da99c4b6
GG		 1154 is_odd = (index/2) & 0x1;
1155 if (is_odd) {
1156 dma_addr = IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1157 (IWL_GET_BITS(bd->pa[index],
1158 tb2_addr_hi20) << 16);
1159 buf_len = IWL_GET_BITS(bd->pa[index], tb2_len);
1160 } else {
1161 dma_addr = le32_to_cpu(bd->pa[index].tb1_addr);
1162 buf_len = IWL_GET_BITS(bd->pa[index], tb1_len);
1163 }
1164
1165 pci_unmap_single(priv->pci_dev, dma_addr, buf_len,
1166 PCI_DMA_TODEVICE);
17b88929
TW		 1167 nfreed++;
1168 }
1169}
1170
1171/**
1172 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1173 * @rxb: Rx buffer to reclaim
1174 *
1175 * If an Rx buffer has an async callback associated with it the callback
1176 * will be executed. The attached skb (if present) will only be freed
1177 * if the callback returns 1
1178 */
1179void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1180{
1181 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1182 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1183 int txq_id = SEQ_TO_QUEUE(sequence);
1184 int index = SEQ_TO_INDEX(sequence);
1185 int huge = sequence & SEQ_HUGE_FRAME;
1186 int cmd_index;
1187 struct iwl_cmd *cmd;
1188
1189 /* If a Tx command is being handled and it isn't in the actual
1190 * command queue then there a command routing bug has been introduced
1191 * in the queue management code. */
1192 if (txq_id != IWL_CMD_QUEUE_NUM)
1193 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
1194 txq_id, pkt->hdr.cmd);
1195 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
1196
1197 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
da99c4b6 1198 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
17b88929
TW		 1199
1200 /* Input error checking is done when commands are added to queue. */
1201 if (cmd->meta.flags & CMD_WANT_SKB) {
1202 cmd->meta.source->u.skb = rxb->skb;
1203 rxb->skb = NULL;
1204 } else if (cmd->meta.u.callback &&
1205 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1206 rxb->skb = NULL;
1207
1208 iwl_hcmd_queue_reclaim(priv, txq_id, index);
1209
1210 if (!(cmd->meta.flags & CMD_ASYNC)) {
1211 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1212 wake_up_interruptible(&priv->wait_command_queue);
1213 }
1214}
1215EXPORT_SYMBOL(iwl_tx_cmd_complete);
1216
30e553e3
TW		 1217/*
1218 * Find first available (lowest unused) Tx Queue, mark it "active".
1219 * Called only when finding queue for aggregation.
1220 * Should never return anything < 7, because they should already
1221 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1222 */
1223static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1224{
1225 int txq_id;
1226
1227 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1228 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1229 return txq_id;
1230 return -1;
1231}
1232
1233int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1234{
1235 int sta_id;
1236 int tx_fifo;
1237 int txq_id;
1238 int ret;
1239 unsigned long flags;
1240 struct iwl_tid_data *tid_data;
1241 DECLARE_MAC_BUF(mac);
1242
1243 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1244 tx_fifo = default_tid_to_tx_fifo[tid];
1245 else
1246 return -EINVAL;
1247
1248 IWL_WARNING("%s on ra = %s tid = %d\n",
1249 __func__, print_mac(mac, ra), tid);
1250
1251 sta_id = iwl_find_station(priv, ra);
1252 if (sta_id == IWL_INVALID_STATION)
1253 return -ENXIO;
1254
1255 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1256 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1257 return -ENXIO;
1258 }
1259
1260 txq_id = iwl_txq_ctx_activate_free(priv);
1261 if (txq_id == -1)
1262 return -ENXIO;
1263
1264 spin_lock_irqsave(&priv->sta_lock, flags);
1265 tid_data = &priv->stations[sta_id].tid[tid];
1266 *ssn = SEQ_TO_SN(tid_data->seq_number);
1267 tid_data->agg.txq_id = txq_id;
1268 spin_unlock_irqrestore(&priv->sta_lock, flags);
1269
1270 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1271 sta_id, tid, *ssn);
1272 if (ret)
1273 return ret;
1274
1275 if (tid_data->tfds_in_queue == 0) {
1276 printk(KERN_ERR "HW queue is empty\n");
1277 tid_data->agg.state = IWL_AGG_ON;
1278 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1279 } else {
1280 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1281 tid_data->tfds_in_queue);
1282 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1283 }
1284 return ret;
1285}
1286EXPORT_SYMBOL(iwl_tx_agg_start);
1287
1288int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1289{
1290 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1291 struct iwl_tid_data *tid_data;
1292 int ret, write_ptr, read_ptr;
1293 unsigned long flags;
1294 DECLARE_MAC_BUF(mac);
1295
1296 if (!ra) {
1297 IWL_ERROR("ra = NULL\n");
1298 return -EINVAL;
1299 }
1300
1301 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1302 tx_fifo_id = default_tid_to_tx_fifo[tid];
1303 else
1304 return -EINVAL;
1305
1306 sta_id = iwl_find_station(priv, ra);
1307
1308 if (sta_id == IWL_INVALID_STATION)
1309 return -ENXIO;
1310
1311 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1312 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1313
1314 tid_data = &priv->stations[sta_id].tid[tid];
1315 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1316 txq_id = tid_data->agg.txq_id;
1317 write_ptr = priv->txq[txq_id].q.write_ptr;
1318 read_ptr = priv->txq[txq_id].q.read_ptr;
1319
1320 /* The queue is not empty */
1321 if (write_ptr != read_ptr) {
1322 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1323 priv->stations[sta_id].tid[tid].agg.state =
1324 IWL_EMPTYING_HW_QUEUE_DELBA;
1325 return 0;
1326 }
1327
1328 IWL_DEBUG_HT("HW queue is empty\n");
1329 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1330
1331 spin_lock_irqsave(&priv->lock, flags);
1332 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1333 tx_fifo_id);
1334 spin_unlock_irqrestore(&priv->lock, flags);
1335
1336 if (ret)
1337 return ret;
1338
1339 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1340
1341 return 0;
1342}
1343EXPORT_SYMBOL(iwl_tx_agg_stop);
1344
1345int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1346{
1347 struct iwl_queue *q = &priv->txq[txq_id].q;
1348 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1349 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1350
1351 switch (priv->stations[sta_id].tid[tid].agg.state) {
1352 case IWL_EMPTYING_HW_QUEUE_DELBA:
1353 /* We are reclaiming the last packet of the */
1354 /* aggregated HW queue */
1355 if (txq_id == tid_data->agg.txq_id &&
1356 q->read_ptr == q->write_ptr) {
1357 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1358 int tx_fifo = default_tid_to_tx_fifo[tid];
1359 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1360 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1361 ssn, tx_fifo);
1362 tid_data->agg.state = IWL_AGG_OFF;
1363 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1364 }
1365 break;
1366 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1367 /* We are reclaiming the last packet of the queue */
1368 if (tid_data->tfds_in_queue == 0) {
1369 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1370 tid_data->agg.state = IWL_AGG_ON;
1371 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1372 }
1373 break;
1374 }
1375 return 0;
1376}
1377EXPORT_SYMBOL(iwl_txq_check_empty);
30e553e3 1378
653fa4a0
EG		 1379/**
1380 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1381 *
1382 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1383 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1384 */
1385static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1386 struct iwl_ht_agg *agg,
1387 struct iwl_compressed_ba_resp *ba_resp)
1388
1389{
1390 int i, sh, ack;
1391 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1392 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1393 u64 bitmap;
1394 int successes = 0;
1395 struct ieee80211_tx_info *info;
1396
1397 if (unlikely(!agg->wait_for_ba)) {
1398 IWL_ERROR("Received BA when not expected\n");
1399 return -EINVAL;
1400 }
1401
1402 /* Mark that the expected block-ack response arrived */
1403 agg->wait_for_ba = 0;
1404 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1405
1406 /* Calculate shift to align block-ack bits with our Tx window bits */
1407 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
1408 if (sh < 0) /* tbw something is wrong with indices */
1409 sh += 0x100;
1410
1411 /* don't use 64-bit values for now */
1412 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1413
1414 if (agg->frame_count > (64 - sh)) {
1415 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1416 return -1;
1417 }
1418
1419 /* check for success or failure according to the
1420 * transmitted bitmap and block-ack bitmap */
1421 bitmap &= agg->bitmap;
1422
1423 /* For each frame attempted in aggregation,
1424 * update driver's record of tx frame's status. */
1425 for (i = 0; i < agg->frame_count ; i++) {
4aa41f12 1426 ack = bitmap & (1ULL << i);
653fa4a0
EG		 1427 successes += !!ack;
1428 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1429 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
1430 agg->start_idx + i);
1431 }
1432
1433 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1434 memset(&info->status, 0, sizeof(info->status));
1435 info->flags = IEEE80211_TX_STAT_ACK;
1436 info->flags |= IEEE80211_TX_STAT_AMPDU;
1437 info->status.ampdu_ack_map = successes;
1438 info->status.ampdu_ack_len = agg->frame_count;
1439 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1440
1441 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1442
1443 return 0;
1444}
1445
1446/**
1447 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1448 *
1449 * Handles block-acknowledge notification from device, which reports success
1450 * of frames sent via aggregation.
1451 */
1452void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1453 struct iwl_rx_mem_buffer *rxb)
1454{
1455 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1456 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1457 int index;
1458 struct iwl_tx_queue *txq = NULL;
1459 struct iwl_ht_agg *agg;
1460 DECLARE_MAC_BUF(mac);
1461
1462 /* "flow" corresponds to Tx queue */
1463 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1464
1465 /* "ssn" is start of block-ack Tx window, corresponds to index
1466 * (in Tx queue's circular buffer) of first TFD/frame in window */
1467 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1468
1469 if (scd_flow >= priv->hw_params.max_txq_num) {
1470 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
1471 return;
1472 }
1473
1474 txq = &priv->txq[scd_flow];
1475 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
1476
1477 /* Find index just before block-ack window */
1478 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1479
1480 /* TODO: Need to get this copy more safely - now good for debug */
1481
1482 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
1483 "sta_id = %d\n",
1484 agg->wait_for_ba,
1485 print_mac(mac, (u8 *) &ba_resp->sta_addr_lo32),
1486 ba_resp->sta_id);
1487 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1488 "%d, scd_ssn = %d\n",
1489 ba_resp->tid,
1490 ba_resp->seq_ctl,
1491 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1492 ba_resp->scd_flow,
1493 ba_resp->scd_ssn);
1494 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1495 agg->start_idx,
1496 (unsigned long long)agg->bitmap);
1497
1498 /* Update driver's record of ACK vs. not for each frame in window */
1499 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1500
1501 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1502 * block-ack window (we assume that they've been successfully
1503 * transmitted ... if not, it's too late anyway). */
1504 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1505 /* calculate mac80211 ampdu sw queue to wake */
1506 int ampdu_q =
1507 scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
1508 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1509 priv->stations[ba_resp->sta_id].
1510 tid[ba_resp->tid].tfds_in_queue -= freed;
1511 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1512 priv->mac80211_registered &&
1513 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
1514 ieee80211_wake_queue(priv->hw, ampdu_q);
1515
1516 iwl_txq_check_empty(priv, ba_resp->sta_id,
1517 ba_resp->tid, scd_flow);
1518 }
1519}
1520EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1521
994d31f7 1522#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW		 1523#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1524
1525const char *iwl_get_tx_fail_reason(u32 status)
1526{
1527 switch (status & TX_STATUS_MSK) {
1528 case TX_STATUS_SUCCESS:
1529 return "SUCCESS";
1530 TX_STATUS_ENTRY(SHORT_LIMIT);
1531 TX_STATUS_ENTRY(LONG_LIMIT);
1532 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1533 TX_STATUS_ENTRY(MGMNT_ABORT);
1534 TX_STATUS_ENTRY(NEXT_FRAG);
1535 TX_STATUS_ENTRY(LIFE_EXPIRE);
1536 TX_STATUS_ENTRY(DEST_PS);
1537 TX_STATUS_ENTRY(ABORTED);
1538 TX_STATUS_ENTRY(BT_RETRY);
1539 TX_STATUS_ENTRY(STA_INVALID);
1540 TX_STATUS_ENTRY(FRAG_DROPPED);
1541 TX_STATUS_ENTRY(TID_DISABLE);
1542 TX_STATUS_ENTRY(FRAME_FLUSHED);
1543 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1544 TX_STATUS_ENTRY(TX_LOCKED);
1545 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1546 }
1547
1548 return "UNKNOWN";
1549}
1550EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1551#endif /* CONFIG_IWLWIFI_DEBUG */
kernel source for telekom puls (alcatel/mediatek)