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iwlwifi: unify tx antenna toggling
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
CommitLineData
1053d35f
RR		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
fd4abac5 30#include <linux/etherdevice.h>
1053d35f
RR		 31#include <net/mac80211.h>
32#include "iwl-eeprom.h"
33#include "iwl-dev.h"
34#include "iwl-core.h"
35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38
30e553e3
TW		 39static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57};
58
30e553e3 59
1053d35f
RR		 60/**
61 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
62 *
63 * Does NOT advance any TFD circular buffer read/write indexes
64 * Does NOT free the TFD itself (which is within circular buffer)
65 */
a33c2f47 66static int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
1053d35f
RR		 67{
68 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
69 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
70 struct pci_dev *dev = priv->pci_dev;
71 int i;
72 int counter = 0;
73 int index, is_odd;
74
1053d35f
RR		 75 /* Sanity check on number of chunks */
76 counter = IWL_GET_BITS(*bd, num_tbs);
77 if (counter > MAX_NUM_OF_TBS) {
78 IWL_ERROR("Too many chunks: %i\n", counter);
79 /* @todo issue fatal error, it is quite serious situation */
80 return 0;
81 }
82
83 /* Unmap chunks, if any.
84 * TFD info for odd chunks is different format than for even chunks. */
85 for (i = 0; i < counter; i++) {
86 index = i / 2;
87 is_odd = i & 0x1;
88
89 if (is_odd)
90 pci_unmap_single(
91 dev,
92 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
93 (IWL_GET_BITS(bd->pa[index],
94 tb2_addr_hi20) << 16),
95 IWL_GET_BITS(bd->pa[index], tb2_len),
96 PCI_DMA_TODEVICE);
97
98 else if (i > 0)
99 pci_unmap_single(dev,
100 le32_to_cpu(bd->pa[index].tb1_addr),
101 IWL_GET_BITS(bd->pa[index], tb1_len),
102 PCI_DMA_TODEVICE);
103
104 /* Free SKB, if any, for this chunk */
105 if (txq->txb[txq->q.read_ptr].skb[i]) {
106 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
107
108 dev_kfree_skb(skb);
109 txq->txb[txq->q.read_ptr].skb[i] = NULL;
110 }
111 }
112 return 0;
113}
1053d35f 114
a33c2f47 115static int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
fd4abac5
TW		 116 dma_addr_t addr, u16 len)
117{
118 int index, is_odd;
119 struct iwl_tfd_frame *tfd = ptr;
120 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
121
122 /* Each TFD can point to a maximum 20 Tx buffers */
73ae98a1 123 if (num_tbs >= MAX_NUM_OF_TBS) {
fd4abac5
TW		 124 IWL_ERROR("Error can not send more than %d chunks\n",
125 MAX_NUM_OF_TBS);
126 return -EINVAL;
127 }
128
129 index = num_tbs / 2;
130 is_odd = num_tbs & 0x1;
131
132 if (!is_odd) {
133 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
134 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
135 iwl_get_dma_hi_address(addr));
136 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
137 } else {
138 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
139 (u32) (addr & 0xffff));
140 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
141 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
142 }
143
144 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
145
146 return 0;
147}
fd4abac5
TW		 148
149/**
150 * iwl_txq_update_write_ptr - Send new write index to hardware
151 */
152int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
153{
154 u32 reg = 0;
155 int ret = 0;
156 int txq_id = txq->q.id;
157
158 if (txq->need_update == 0)
159 return ret;
160
161 /* if we're trying to save power */
162 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
163 /* wake up nic if it's powered down ...
164 * uCode will wake up, and interrupt us again, so next
165 * time we'll skip this part. */
166 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
167
168 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
169 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
170 iwl_set_bit(priv, CSR_GP_CNTRL,
171 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
172 return ret;
173 }
174
175 /* restore this queue's parameters in nic hardware. */
176 ret = iwl_grab_nic_access(priv);
177 if (ret)
178 return ret;
179 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
180 txq->q.write_ptr | (txq_id << 8));
181 iwl_release_nic_access(priv);
182
183 /* else not in power-save mode, uCode will never sleep when we're
184 * trying to tx (during RFKILL, we're not trying to tx). */
185 } else
186 iwl_write32(priv, HBUS_TARG_WRPTR,
187 txq->q.write_ptr | (txq_id << 8));
188
189 txq->need_update = 0;
190
191 return ret;
192}
193EXPORT_SYMBOL(iwl_txq_update_write_ptr);
194
195
1053d35f
RR		 196/**
197 * iwl_tx_queue_free - Deallocate DMA queue.
198 * @txq: Transmit queue to deallocate.
199 *
200 * Empty queue by removing and destroying all BD's.
201 * Free all buffers.
202 * 0-fill, but do not free "txq" descriptor structure.
203 */
da99c4b6 204static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
1053d35f 205{
da99c4b6 206 struct iwl_tx_queue *txq = &priv->txq[txq_id];
443cfd45 207 struct iwl_queue *q = &txq->q;
1053d35f 208 struct pci_dev *dev = priv->pci_dev;
961ba60a 209 int i, len;
1053d35f
RR		 210
211 if (q->n_bd == 0)
212 return;
213
214 /* first, empty all BD's */
215 for (; q->write_ptr != q->read_ptr;
216 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
217 iwl_hw_txq_free_tfd(priv, txq);
218
219 len = sizeof(struct iwl_cmd) * q->n_window;
1053d35f
RR		 220
221 /* De-alloc array of command/tx buffers */
961ba60a 222 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
da99c4b6 223 kfree(txq->cmd[i]);
1053d35f
RR		 224
225 /* De-alloc circular buffer of TFDs */
226 if (txq->q.n_bd)
227 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
228 txq->q.n_bd, txq->bd, txq->q.dma_addr);
229
230 /* De-alloc array of per-TFD driver data */
231 kfree(txq->txb);
232 txq->txb = NULL;
233
234 /* 0-fill queue descriptor structure */
235 memset(txq, 0, sizeof(*txq));
236}
237
961ba60a
TW		 238
239/**
240 * iwl_cmd_queue_free - Deallocate DMA queue.
241 * @txq: Transmit queue to deallocate.
242 *
243 * Empty queue by removing and destroying all BD's.
244 * Free all buffers.
245 * 0-fill, but do not free "txq" descriptor structure.
246 */
247static void iwl_cmd_queue_free(struct iwl_priv *priv)
248{
249 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
250 struct iwl_queue *q = &txq->q;
251 struct pci_dev *dev = priv->pci_dev;
252 int i, len;
253
254 if (q->n_bd == 0)
255 return;
256
257 len = sizeof(struct iwl_cmd) * q->n_window;
258 len += IWL_MAX_SCAN_SIZE;
259
260 /* De-alloc array of command/tx buffers */
261 for (i = 0; i <= TFD_CMD_SLOTS; i++)
262 kfree(txq->cmd[i]);
263
264 /* De-alloc circular buffer of TFDs */
265 if (txq->q.n_bd)
266 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
267 txq->q.n_bd, txq->bd, txq->q.dma_addr);
268
269 /* 0-fill queue descriptor structure */
270 memset(txq, 0, sizeof(*txq));
271}
fd4abac5
TW		 272/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
273 * DMA services
274 *
275 * Theory of operation
276 *
277 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
278 * of buffer descriptors, each of which points to one or more data buffers for
279 * the device to read from or fill. Driver and device exchange status of each
280 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
281 * entries in each circular buffer, to protect against confusing empty and full
282 * queue states.
283 *
284 * The device reads or writes the data in the queues via the device's several
285 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
286 *
287 * For Tx queue, there are low mark and high mark limits. If, after queuing
288 * the packet for Tx, free space become < low mark, Tx queue stopped. When
289 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
290 * Tx queue resumed.
291 *
292 * See more detailed info in iwl-4965-hw.h.
293 ***************************************************/
294
295int iwl_queue_space(const struct iwl_queue *q)
296{
297 int s = q->read_ptr - q->write_ptr;
298
299 if (q->read_ptr > q->write_ptr)
300 s -= q->n_bd;
301
302 if (s <= 0)
303 s += q->n_window;
304 /* keep some reserve to not confuse empty and full situations */
305 s -= 2;
306 if (s < 0)
307 s = 0;
308 return s;
309}
310EXPORT_SYMBOL(iwl_queue_space);
311
312
1053d35f
RR		 313/**
314 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
315 */
443cfd45 316static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR		 317 int count, int slots_num, u32 id)
318{
319 q->n_bd = count;
320 q->n_window = slots_num;
321 q->id = id;
322
323 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
324 * and iwl_queue_dec_wrap are broken. */
325 BUG_ON(!is_power_of_2(count));
326
327 /* slots_num must be power-of-two size, otherwise
328 * get_cmd_index is broken. */
329 BUG_ON(!is_power_of_2(slots_num));
330
331 q->low_mark = q->n_window / 4;
332 if (q->low_mark < 4)
333 q->low_mark = 4;
334
335 q->high_mark = q->n_window / 8;
336 if (q->high_mark < 2)
337 q->high_mark = 2;
338
339 q->write_ptr = q->read_ptr = 0;
340
341 return 0;
342}
343
344/**
345 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
346 */
347static int iwl_tx_queue_alloc(struct iwl_priv *priv,
16466903 348 struct iwl_tx_queue *txq, u32 id)
1053d35f
RR		 349{
350 struct pci_dev *dev = priv->pci_dev;
351
352 /* Driver private data, only for Tx (not command) queues,
353 * not shared with device. */
354 if (id != IWL_CMD_QUEUE_NUM) {
355 txq->txb = kmalloc(sizeof(txq->txb[0]) *
356 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
357 if (!txq->txb) {
358 IWL_ERROR("kmalloc for auxiliary BD "
359 "structures failed\n");
360 goto error;
361 }
362 } else
363 txq->txb = NULL;
364
365 /* Circular buffer of transmit frame descriptors (TFDs),
366 * shared with device */
367 txq->bd = pci_alloc_consistent(dev,
368 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
369 &txq->q.dma_addr);
370
371 if (!txq->bd) {
372 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
373 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
374 goto error;
375 }
376 txq->q.id = id;
377
378 return 0;
379
380 error:
381 kfree(txq->txb);
382 txq->txb = NULL;
383
384 return -ENOMEM;
385}
386
387/*
388 * Tell nic where to find circular buffer of Tx Frame Descriptors for
389 * given Tx queue, and enable the DMA channel used for that queue.
390 *
391 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
392 * channels supported in hardware.
393 */
394static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
16466903 395 struct iwl_tx_queue *txq)
1053d35f
RR		 396{
397 int rc;
398 unsigned long flags;
399 int txq_id = txq->q.id;
400
401 spin_lock_irqsave(&priv->lock, flags);
402 rc = iwl_grab_nic_access(priv);
403 if (rc) {
404 spin_unlock_irqrestore(&priv->lock, flags);
405 return rc;
406 }
407
408 /* Circular buffer (TFD queue in DRAM) physical base address */
409 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
410 txq->q.dma_addr >> 8);
411
412 /* Enable DMA channel, using same id as for TFD queue */
413 iwl_write_direct32(
414 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
415 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
416 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
417 iwl_release_nic_access(priv);
418 spin_unlock_irqrestore(&priv->lock, flags);
419
420 return 0;
421}
422
423/**
424 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
425 */
73b7d742 426static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
1053d35f
RR		 427 int slots_num, u32 txq_id)
428{
da99c4b6 429 int i, len;
73b7d742 430 int ret;
1053d35f
RR		 431
432 /*
433 * Alloc buffer array for commands (Tx or other types of commands).
434 * For the command queue (#4), allocate command space + one big
435 * command for scan, since scan command is very huge; the system will
436 * not have two scans at the same time, so only one is needed.
437 * For normal Tx queues (all other queues), no super-size command
438 * space is needed.
439 */
da99c4b6
GG		 440 len = sizeof(struct iwl_cmd);
441 for (i = 0; i <= slots_num; i++) {
442 if (i == slots_num) {
443 if (txq_id == IWL_CMD_QUEUE_NUM)
444 len += IWL_MAX_SCAN_SIZE;
445 else
446 continue;
447 }
448
49898852 449 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
da99c4b6 450 if (!txq->cmd[i])
73b7d742 451 goto err;
da99c4b6 452 }
1053d35f
RR		 453
454 /* Alloc driver data array and TFD circular buffer */
73b7d742
TW		 455 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
456 if (ret)
457 goto err;
1053d35f 458
1053d35f
RR		 459 txq->need_update = 0;
460
461 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
462 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
463 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
464
465 /* Initialize queue's high/low-water marks, and head/tail indexes */
466 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
467
468 /* Tell device where to find queue */
469 iwl_hw_tx_queue_init(priv, txq);
470
471 return 0;
73b7d742
TW		 472err:
473 for (i = 0; i < slots_num; i++) {
474 kfree(txq->cmd[i]);
475 txq->cmd[i] = NULL;
476 }
477
478 if (txq_id == IWL_CMD_QUEUE_NUM) {
479 kfree(txq->cmd[slots_num]);
480 txq->cmd[slots_num] = NULL;
481 }
482 return -ENOMEM;
1053d35f 483}
da1bc453
TW		 484/**
485 * iwl_hw_txq_ctx_free - Free TXQ Context
486 *
487 * Destroy all TX DMA queues and structures
488 */
489void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
490{
491 int txq_id;
492
493 /* Tx queues */
494 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
961ba60a
TW		 495 if (txq_id == IWL_CMD_QUEUE_NUM)
496 iwl_cmd_queue_free(priv);
497 else
498 iwl_tx_queue_free(priv, txq_id);
da1bc453
TW		 499
500 /* Keep-warm buffer */
501 iwl_kw_free(priv);
502}
503EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
504
1053d35f
RR		 505/**
506 * iwl_txq_ctx_reset - Reset TX queue context
507 * Destroys all DMA structures and initialise them again
508 *
509 * @param priv
510 * @return error code
511 */
512int iwl_txq_ctx_reset(struct iwl_priv *priv)
513{
514 int ret = 0;
515 int txq_id, slots_num;
da1bc453 516 unsigned long flags;
1053d35f
RR		 517
518 iwl_kw_free(priv);
519
520 /* Free all tx/cmd queues and keep-warm buffer */
521 iwl_hw_txq_ctx_free(priv);
522
523 /* Alloc keep-warm buffer */
524 ret = iwl_kw_alloc(priv);
525 if (ret) {
6f147926 526 IWL_ERROR("Keep Warm allocation failed\n");
1053d35f
RR		 527 goto error_kw;
528 }
da1bc453
TW		 529 spin_lock_irqsave(&priv->lock, flags);
530 ret = iwl_grab_nic_access(priv);
531 if (unlikely(ret)) {
532 spin_unlock_irqrestore(&priv->lock, flags);
533 goto error_reset;
534 }
1053d35f
RR		 535
536 /* Turn off all Tx DMA fifos */
da1bc453
TW		 537 priv->cfg->ops->lib->txq_set_sched(priv, 0);
538
539 iwl_release_nic_access(priv);
540 spin_unlock_irqrestore(&priv->lock, flags);
541
1053d35f
RR		 542
543 /* Tell nic where to find the keep-warm buffer */
544 ret = iwl_kw_init(priv);
545 if (ret) {
546 IWL_ERROR("kw_init failed\n");
547 goto error_reset;
548 }
549
da1bc453 550 /* Alloc and init all Tx queues, including the command queue (#4) */
1053d35f
RR		 551 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
552 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
553 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
554 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
555 txq_id);
556 if (ret) {
557 IWL_ERROR("Tx %d queue init failed\n", txq_id);
558 goto error;
559 }
560 }
561
562 return ret;
563
564 error:
565 iwl_hw_txq_ctx_free(priv);
566 error_reset:
567 iwl_kw_free(priv);
568 error_kw:
569 return ret;
570}
a33c2f47 571
da1bc453
TW		 572/**
573 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
574 */
575void iwl_txq_ctx_stop(struct iwl_priv *priv)
576{
577
578 int txq_id;
579 unsigned long flags;
580
581
582 /* Turn off all Tx DMA fifos */
583 spin_lock_irqsave(&priv->lock, flags);
584 if (iwl_grab_nic_access(priv)) {
585 spin_unlock_irqrestore(&priv->lock, flags);
586 return;
587 }
588
589 priv->cfg->ops->lib->txq_set_sched(priv, 0);
590
591 /* Stop each Tx DMA channel, and wait for it to be idle */
592 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
593 iwl_write_direct32(priv,
594 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
595 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
596 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
597 (txq_id), 200);
598 }
599 iwl_release_nic_access(priv);
600 spin_unlock_irqrestore(&priv->lock, flags);
601
602 /* Deallocate memory for all Tx queues */
603 iwl_hw_txq_ctx_free(priv);
604}
605EXPORT_SYMBOL(iwl_txq_ctx_stop);
fd4abac5
TW		 606
607/*
608 * handle build REPLY_TX command notification.
609 */
610static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
611 struct iwl_tx_cmd *tx_cmd,
e039fa4a 612 struct ieee80211_tx_info *info,
fd4abac5
TW		 613 struct ieee80211_hdr *hdr,
614 int is_unicast, u8 std_id)
615{
fd7c8a40 616 __le16 fc = hdr->frame_control;
fd4abac5
TW		 617 __le32 tx_flags = tx_cmd->tx_flags;
618
619 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 620 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
fd4abac5 621 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 622 if (ieee80211_is_mgmt(fc))
fd4abac5 623 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 624 if (ieee80211_is_probe_resp(fc) &&
fd4abac5
TW		 625 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
626 tx_flags |= TX_CMD_FLG_TSF_MSK;
627 } else {
628 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
629 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
630 }
631
fd7c8a40 632 if (ieee80211_is_back_req(fc))
fd4abac5
TW		 633 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
634
635
636 tx_cmd->sta_id = std_id;
8b7b1e05 637 if (ieee80211_has_morefrags(fc))
fd4abac5
TW		 638 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
639
fd7c8a40
HH		 640 if (ieee80211_is_data_qos(fc)) {
641 u8 *qc = ieee80211_get_qos_ctl(hdr);
fd4abac5
TW		 642 tx_cmd->tid_tspec = qc[0] & 0xf;
643 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
644 } else {
645 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
646 }
647
a326a5d0 648 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
fd4abac5
TW		 649
650 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
651 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
652
653 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 654 if (ieee80211_is_mgmt(fc)) {
655 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 656 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
657 else
658 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
659 } else {
660 tx_cmd->timeout.pm_frame_timeout = 0;
661 }
662
663 tx_cmd->driver_txop = 0;
664 tx_cmd->tx_flags = tx_flags;
665 tx_cmd->next_frame_len = 0;
666}
667
668#define RTS_HCCA_RETRY_LIMIT 3
669#define RTS_DFAULT_RETRY_LIMIT 60
670
671static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
672 struct iwl_tx_cmd *tx_cmd,
e039fa4a 673 struct ieee80211_tx_info *info,
fd7c8a40 674 __le16 fc, int sta_id,
fd4abac5
TW		 675 int is_hcca)
676{
76eff18b
TW		 677 u32 rate_flags = 0;
678 int rate_idx;
fd4abac5
TW		 679 u8 rts_retry_limit = 0;
680 u8 data_retry_limit = 0;
681 u8 rate_plcp;
2e92e6f2 682
e039fa4a 683 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
2e92e6f2 684 IWL_RATE_COUNT - 1);
fd4abac5
TW		 685
686 rate_plcp = iwl_rates[rate_idx].plcp;
687
688 rts_retry_limit = (is_hcca) ?
689 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
690
691 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
692 rate_flags |= RATE_MCS_CCK_MSK;
693
694
fd7c8a40 695 if (ieee80211_is_probe_resp(fc)) {
fd4abac5
TW		 696 data_retry_limit = 3;
697 if (data_retry_limit < rts_retry_limit)
698 rts_retry_limit = data_retry_limit;
699 } else
700 data_retry_limit = IWL_DEFAULT_TX_RETRY;
701
702 if (priv->data_retry_limit != -1)
703 data_retry_limit = priv->data_retry_limit;
704
705
706 if (ieee80211_is_data(fc)) {
707 tx_cmd->initial_rate_index = 0;
708 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
709 } else {
fd7c8a40
HH		 710 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
711 case cpu_to_le16(IEEE80211_STYPE_AUTH):
712 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
713 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
714 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
fd4abac5
TW		 715 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
716 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
717 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
718 }
719 break;
720 default:
721 break;
722 }
723
76eff18b
TW		 724 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
725 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
fd4abac5
TW		 726 }
727
728 tx_cmd->rts_retry_limit = rts_retry_limit;
729 tx_cmd->data_retry_limit = data_retry_limit;
e7d326ac 730 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
fd4abac5
TW		 731}
732
733static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
e039fa4a 734 struct ieee80211_tx_info *info,
fd4abac5
TW		 735 struct iwl_tx_cmd *tx_cmd,
736 struct sk_buff *skb_frag,
737 int sta_id)
738{
e039fa4a 739 struct ieee80211_key_conf *keyconf = info->control.hw_key;
fd4abac5 740
ccc038ab 741 switch (keyconf->alg) {
fd4abac5
TW		 742 case ALG_CCMP:
743 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
ccc038ab 744 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
e039fa4a 745 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 746 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
747 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
748 break;
749
750 case ALG_TKIP:
751 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
ccc038ab 752 ieee80211_get_tkip_key(keyconf, skb_frag,
fd4abac5
TW		 753 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
754 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
755 break;
756
757 case ALG_WEP:
fd4abac5 758 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
ccc038ab
EG		 759 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
760
761 if (keyconf->keylen == WEP_KEY_LEN_128)
762 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
763
764 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
fd4abac5
TW		 765
766 IWL_DEBUG_TX("Configuring packet for WEP encryption "
ccc038ab 767 "with key %d\n", keyconf->keyidx);
fd4abac5
TW		 768 break;
769
770 default:
ccc038ab 771 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
fd4abac5
TW		 772 break;
773 }
774}
775
776static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
777{
778 /* 0 - mgmt, 1 - cnt, 2 - data */
779 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
780 priv->tx_stats[idx].cnt++;
781 priv->tx_stats[idx].bytes += len;
782}
783
784/*
785 * start REPLY_TX command process
786 */
e039fa4a 787int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
fd4abac5
TW		 788{
789 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 790 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fd4abac5 791 struct iwl_tfd_frame *tfd;
f3674227
TW		 792 struct iwl_tx_queue *txq;
793 struct iwl_queue *q;
794 struct iwl_cmd *out_cmd;
795 struct iwl_tx_cmd *tx_cmd;
796 int swq_id, txq_id;
fd4abac5
TW		 797 dma_addr_t phys_addr;
798 dma_addr_t txcmd_phys;
799 dma_addr_t scratch_phys;
fd4abac5
TW		 800 u16 len, idx, len_org;
801 u16 seq_number = 0;
fd7c8a40 802 __le16 fc;
f3674227
TW		 803 u8 hdr_len, unicast;
804 u8 sta_id;
fd4abac5
TW		 805 u8 wait_write_ptr = 0;
806 u8 tid = 0;
807 u8 *qc = NULL;
808 unsigned long flags;
809 int ret;
810
811 spin_lock_irqsave(&priv->lock, flags);
812 if (iwl_is_rfkill(priv)) {
813 IWL_DEBUG_DROP("Dropping - RF KILL\n");
814 goto drop_unlock;
815 }
816
e039fa4a 817 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
2e92e6f2 818 IWL_INVALID_RATE) {
fd4abac5
TW		 819 IWL_ERROR("ERROR: No TX rate available.\n");
820 goto drop_unlock;
821 }
822
823 unicast = !is_multicast_ether_addr(hdr->addr1);
fd4abac5 824
fd7c8a40 825 fc = hdr->frame_control;
fd4abac5
TW		 826
827#ifdef CONFIG_IWLWIFI_DEBUG
828 if (ieee80211_is_auth(fc))
829 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 830 else if (ieee80211_is_assoc_req(fc))
fd4abac5 831 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 832 else if (ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 833 IWL_DEBUG_TX("Sending REASSOC frame\n");
834#endif
835
836 /* drop all data frame if we are not associated */
fd7c8a40 837 if (ieee80211_is_data(fc) &&
05c914fe 838 (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
d10c4ec8
SG		 839 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
840 (!iwl_is_associated(priv) ||
05c914fe 841 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
d10c4ec8 842 !priv->assoc_station_added)) {
fd4abac5
TW		 843 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
844 goto drop_unlock;
845 }
846
847 spin_unlock_irqrestore(&priv->lock, flags);
848
7294ec95 849 hdr_len = ieee80211_hdrlen(fc);
fd4abac5
TW		 850
851 /* Find (or create) index into station table for destination station */
852 sta_id = iwl_get_sta_id(priv, hdr);
853 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 854 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
855 hdr->addr1);
fd4abac5
TW		 856 goto drop;
857 }
858
859 IWL_DEBUG_TX("station Id %d\n", sta_id);
860
f3674227
TW		 861 swq_id = skb_get_queue_mapping(skb);
862 txq_id = swq_id;
fd7c8a40
HH		 863 if (ieee80211_is_data_qos(fc)) {
864 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 865 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
f3674227
TW		 866 seq_number = priv->stations[sta_id].tid[tid].seq_number;
867 seq_number &= IEEE80211_SCTL_SEQ;
868 hdr->seq_ctrl = hdr->seq_ctrl &
869 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG);
870 hdr->seq_ctrl |= cpu_to_le16(seq_number);
fd4abac5 871 seq_number += 0x10;
fd4abac5 872 /* aggregation is on for this <sta,tid> */
e039fa4a 873 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 874 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
875 priv->stations[sta_id].tid[tid].tfds_in_queue++;
fd4abac5
TW		 876 }
877
878 /* Descriptor for chosen Tx queue */
879 txq = &priv->txq[txq_id];
880 q = &txq->q;
881
882 spin_lock_irqsave(&priv->lock, flags);
883
884 /* Set up first empty TFD within this queue's circular TFD buffer */
885 tfd = &txq->bd[q->write_ptr];
886 memset(tfd, 0, sizeof(*tfd));
fd4abac5
TW		 887 idx = get_cmd_index(q, q->write_ptr, 0);
888
889 /* Set up driver data for this TFD */
890 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
891 txq->txb[q->write_ptr].skb[0] = skb;
fd4abac5
TW		 892
893 /* Set up first empty entry in queue's array of Tx/cmd buffers */
da99c4b6 894 out_cmd = txq->cmd[idx];
fd4abac5
TW		 895 tx_cmd = &out_cmd->cmd.tx;
896 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
897 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
898
899 /*
900 * Set up the Tx-command (not MAC!) header.
901 * Store the chosen Tx queue and TFD index within the sequence field;
902 * after Tx, uCode's Tx response will return this value so driver can
903 * locate the frame within the tx queue and do post-tx processing.
904 */
905 out_cmd->hdr.cmd = REPLY_TX;
906 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
907 INDEX_TO_SEQ(q->write_ptr)));
908
909 /* Copy MAC header from skb into command buffer */
910 memcpy(tx_cmd->hdr, hdr, hdr_len);
911
912 /*
913 * Use the first empty entry in this queue's command buffer array
914 * to contain the Tx command and MAC header concatenated together
915 * (payload data will be in another buffer).
916 * Size of this varies, due to varying MAC header length.
917 * If end is not dword aligned, we'll have 2 extra bytes at the end
918 * of the MAC header (device reads on dword boundaries).
919 * We'll tell device about this padding later.
920 */
921 len = sizeof(struct iwl_tx_cmd) +
922 sizeof(struct iwl_cmd_header) + hdr_len;
923
924 len_org = len;
925 len = (len + 3) & ~3;
926
927 if (len_org != len)
928 len_org = 1;
929 else
930 len_org = 0;
931
932 /* Physical address of this Tx command's header (not MAC header!),
933 * within command buffer array. */
da99c4b6
GG		 934 txcmd_phys = pci_map_single(priv->pci_dev, out_cmd,
935 sizeof(struct iwl_cmd), PCI_DMA_TODEVICE);
936 txcmd_phys += offsetof(struct iwl_cmd, hdr);
fd4abac5
TW		 937
938 /* Add buffer containing Tx command and MAC(!) header to TFD's
939 * first entry */
940 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
941
d0f09804 942 if (info->control.hw_key)
e039fa4a 943 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
fd4abac5
TW		 944
945 /* Set up TFD's 2nd entry to point directly to remainder of skb,
946 * if any (802.11 null frames have no payload). */
947 len = skb->len - hdr_len;
948 if (len) {
949 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
950 len, PCI_DMA_TODEVICE);
951 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
952 }
953
954 /* Tell NIC about any 2-byte padding after MAC header */
955 if (len_org)
956 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
957
958 /* Total # bytes to be transmitted */
959 len = (u16)skb->len;
960 tx_cmd->len = cpu_to_le16(len);
961 /* TODO need this for burst mode later on */
e039fa4a 962 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
fd4abac5
TW		 963
964 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 965 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
fd4abac5 966
fd7c8a40 967 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
fd4abac5
TW		 968
969 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
970 offsetof(struct iwl_tx_cmd, scratch);
971 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
972 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
973
8b7b1e05 974 if (!ieee80211_has_morefrags(hdr->frame_control)) {
fd4abac5
TW		 975 txq->need_update = 1;
976 if (qc)
977 priv->stations[sta_id].tid[tid].seq_number = seq_number;
978 } else {
979 wait_write_ptr = 1;
980 txq->need_update = 0;
981 }
982
983 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
984
985 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
986
987 /* Set up entry for this TFD in Tx byte-count array */
988 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
989
990 /* Tell device the write index *just past* this latest filled TFD */
991 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
992 ret = iwl_txq_update_write_ptr(priv, txq);
993 spin_unlock_irqrestore(&priv->lock, flags);
994
995 if (ret)
996 return ret;
997
143b09ef 998 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
fd4abac5
TW		 999 if (wait_write_ptr) {
1000 spin_lock_irqsave(&priv->lock, flags);
1001 txq->need_update = 1;
1002 iwl_txq_update_write_ptr(priv, txq);
1003 spin_unlock_irqrestore(&priv->lock, flags);
143b09ef 1004 } else {
f3674227 1005 ieee80211_stop_queue(priv->hw, swq_id);
fd4abac5 1006 }
fd4abac5
TW		 1007 }
1008
1009 return 0;
1010
1011drop_unlock:
1012 spin_unlock_irqrestore(&priv->lock, flags);
1013drop:
1014 return -1;
1015}
1016EXPORT_SYMBOL(iwl_tx_skb);
1017
1018/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1019
1020/**
1021 * iwl_enqueue_hcmd - enqueue a uCode command
1022 * @priv: device private data point
1023 * @cmd: a point to the ucode command structure
1024 *
1025 * The function returns < 0 values to indicate the operation is
1026 * failed. On success, it turns the index (> 0) of command in the
1027 * command queue.
1028 */
1029int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1030{
1031 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1032 struct iwl_queue *q = &txq->q;
1033 struct iwl_tfd_frame *tfd;
fd4abac5 1034 struct iwl_cmd *out_cmd;
fd4abac5 1035 dma_addr_t phys_addr;
fd4abac5 1036 unsigned long flags;
f3674227
TW		 1037 int len, ret;
1038 u32 idx;
1039 u16 fix_size;
fd4abac5
TW		 1040
1041 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1042 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1043
1044 /* If any of the command structures end up being larger than
1045 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1046 * we will need to increase the size of the TFD entries */
1047 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1048 !(cmd->meta.flags & CMD_SIZE_HUGE));
1049
1050 if (iwl_is_rfkill(priv)) {
1051 IWL_DEBUG_INFO("Not sending command - RF KILL");
1052 return -EIO;
1053 }
1054
1055 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1056 IWL_ERROR("No space for Tx\n");
1057 return -ENOSPC;
1058 }
1059
1060 spin_lock_irqsave(&priv->hcmd_lock, flags);
1061
1062 tfd = &txq->bd[q->write_ptr];
1063 memset(tfd, 0, sizeof(*tfd));
1064
fd4abac5
TW		 1065
1066 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
da99c4b6 1067 out_cmd = txq->cmd[idx];
fd4abac5
TW		 1068
1069 out_cmd->hdr.cmd = cmd->id;
1070 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1071 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1072
1073 /* At this point, the out_cmd now has all of the incoming cmd
1074 * information */
1075
1076 out_cmd->hdr.flags = 0;
1077 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1078 INDEX_TO_SEQ(q->write_ptr));
1079 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
9734cb23 1080 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
da99c4b6
GG		 1081 len = (idx == TFD_CMD_SLOTS) ?
1082 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
1083 phys_addr = pci_map_single(priv->pci_dev, out_cmd, len,
1084 PCI_DMA_TODEVICE);
1085 phys_addr += offsetof(struct iwl_cmd, hdr);
fd4abac5
TW		 1086 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1087
ded2ae7c
EK		 1088#ifdef CONFIG_IWLWIFI_DEBUG
1089 switch (out_cmd->hdr.cmd) {
1090 case REPLY_TX_LINK_QUALITY_CMD:
1091 case SENSITIVITY_CMD:
1092 IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
1093 "%d bytes at %d[%d]:%d\n",
1094 get_cmd_string(out_cmd->hdr.cmd),
1095 out_cmd->hdr.cmd,
1096 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1097 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1098 break;
1099 default:
1100 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1101 "%d bytes at %d[%d]:%d\n",
1102 get_cmd_string(out_cmd->hdr.cmd),
1103 out_cmd->hdr.cmd,
1104 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1105 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1106 }
1107#endif
fd4abac5
TW		 1108 txq->need_update = 1;
1109
1110 /* Set up entry in queue's byte count circular buffer */
1111 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1112
1113 /* Increment and update queue's write index */
1114 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1115 ret = iwl_txq_update_write_ptr(priv, txq);
1116
1117 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1118 return ret ? ret : idx;
1119}
1120
17b88929
TW		 1121int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1122{
1123 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1124 struct iwl_queue *q = &txq->q;
1125 struct iwl_tx_info *tx_info;
1126 int nfreed = 0;
1127
1128 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1129 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1130 "is out of range [0-%d] %d %d.\n", txq_id,
1131 index, q->n_bd, q->write_ptr, q->read_ptr);
1132 return 0;
1133 }
1134
1135 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1136 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1137
1138 tx_info = &txq->txb[txq->q.read_ptr];
1139 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1140 tx_info->skb[0] = NULL;
17b88929 1141
972cf447
TW		 1142 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1143 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1144
1145 iwl_hw_txq_free_tfd(priv, txq);
17b88929
TW		 1146 nfreed++;
1147 }
1148 return nfreed;
1149}
1150EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1151
1152
1153/**
1154 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1155 *
1156 * When FW advances 'R' index, all entries between old and new 'R' index
1157 * need to be reclaimed. As result, some free space forms. If there is
1158 * enough free space (> low mark), wake the stack that feeds us.
1159 */
1160static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1161{
1162 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1163 struct iwl_queue *q = &txq->q;
da99c4b6
GG		 1164 struct iwl_tfd_frame *bd = &txq->bd[index];
1165 dma_addr_t dma_addr;
1166 int is_odd, buf_len;
17b88929
TW		 1167 int nfreed = 0;
1168
1169 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1170 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1171 "is out of range [0-%d] %d %d.\n", txq_id,
1172 index, q->n_bd, q->write_ptr, q->read_ptr);
1173 return;
1174 }
1175
1176 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1177 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1178
1179 if (nfreed > 1) {
1180 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
1181 q->write_ptr, q->read_ptr);
1182 queue_work(priv->workqueue, &priv->restart);
1183 }
da99c4b6
GG		 1184 is_odd = (index/2) & 0x1;
1185 if (is_odd) {
1186 dma_addr = IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1187 (IWL_GET_BITS(bd->pa[index],
1188 tb2_addr_hi20) << 16);
1189 buf_len = IWL_GET_BITS(bd->pa[index], tb2_len);
1190 } else {
1191 dma_addr = le32_to_cpu(bd->pa[index].tb1_addr);
1192 buf_len = IWL_GET_BITS(bd->pa[index], tb1_len);
1193 }
1194
1195 pci_unmap_single(priv->pci_dev, dma_addr, buf_len,
1196 PCI_DMA_TODEVICE);
17b88929
TW		 1197 nfreed++;
1198 }
1199}
1200
1201/**
1202 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1203 * @rxb: Rx buffer to reclaim
1204 *
1205 * If an Rx buffer has an async callback associated with it the callback
1206 * will be executed. The attached skb (if present) will only be freed
1207 * if the callback returns 1
1208 */
1209void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1210{
1211 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1212 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1213 int txq_id = SEQ_TO_QUEUE(sequence);
1214 int index = SEQ_TO_INDEX(sequence);
17b88929 1215 int cmd_index;
9734cb23 1216 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
17b88929
TW		 1217 struct iwl_cmd *cmd;
1218
1219 /* If a Tx command is being handled and it isn't in the actual
1220 * command queue then there a command routing bug has been introduced
1221 * in the queue management code. */
55d6a3cd
JB		 1222 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1223 "wrong command queue %d, command id 0x%X\n", txq_id, pkt->hdr.cmd))
1224 return;
17b88929
TW		 1225
1226 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
da99c4b6 1227 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
17b88929
TW		 1228
1229 /* Input error checking is done when commands are added to queue. */
1230 if (cmd->meta.flags & CMD_WANT_SKB) {
1231 cmd->meta.source->u.skb = rxb->skb;
1232 rxb->skb = NULL;
1233 } else if (cmd->meta.u.callback &&
1234 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1235 rxb->skb = NULL;
1236
1237 iwl_hcmd_queue_reclaim(priv, txq_id, index);
1238
1239 if (!(cmd->meta.flags & CMD_ASYNC)) {
1240 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1241 wake_up_interruptible(&priv->wait_command_queue);
1242 }
1243}
1244EXPORT_SYMBOL(iwl_tx_cmd_complete);
1245
30e553e3
TW		 1246/*
1247 * Find first available (lowest unused) Tx Queue, mark it "active".
1248 * Called only when finding queue for aggregation.
1249 * Should never return anything < 7, because they should already
1250 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1251 */
1252static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1253{
1254 int txq_id;
1255
1256 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1257 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1258 return txq_id;
1259 return -1;
1260}
1261
1262int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1263{
1264 int sta_id;
1265 int tx_fifo;
1266 int txq_id;
1267 int ret;
1268 unsigned long flags;
1269 struct iwl_tid_data *tid_data;
30e553e3
TW		 1270
1271 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1272 tx_fifo = default_tid_to_tx_fifo[tid];
1273 else
1274 return -EINVAL;
1275
e174961c
JB		 1276 IWL_WARNING("%s on ra = %pM tid = %d\n",
1277 __func__, ra, tid);
30e553e3
TW		 1278
1279 sta_id = iwl_find_station(priv, ra);
1280 if (sta_id == IWL_INVALID_STATION)
1281 return -ENXIO;
1282
1283 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1284 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1285 return -ENXIO;
1286 }
1287
1288 txq_id = iwl_txq_ctx_activate_free(priv);
1289 if (txq_id == -1)
1290 return -ENXIO;
1291
1292 spin_lock_irqsave(&priv->sta_lock, flags);
1293 tid_data = &priv->stations[sta_id].tid[tid];
1294 *ssn = SEQ_TO_SN(tid_data->seq_number);
1295 tid_data->agg.txq_id = txq_id;
1296 spin_unlock_irqrestore(&priv->sta_lock, flags);
1297
1298 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1299 sta_id, tid, *ssn);
1300 if (ret)
1301 return ret;
1302
1303 if (tid_data->tfds_in_queue == 0) {
1304 printk(KERN_ERR "HW queue is empty\n");
1305 tid_data->agg.state = IWL_AGG_ON;
1306 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1307 } else {
1308 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1309 tid_data->tfds_in_queue);
1310 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1311 }
1312 return ret;
1313}
1314EXPORT_SYMBOL(iwl_tx_agg_start);
1315
1316int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1317{
1318 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1319 struct iwl_tid_data *tid_data;
1320 int ret, write_ptr, read_ptr;
1321 unsigned long flags;
30e553e3
TW		 1322
1323 if (!ra) {
1324 IWL_ERROR("ra = NULL\n");
1325 return -EINVAL;
1326 }
1327
1328 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1329 tx_fifo_id = default_tid_to_tx_fifo[tid];
1330 else
1331 return -EINVAL;
1332
1333 sta_id = iwl_find_station(priv, ra);
1334
1335 if (sta_id == IWL_INVALID_STATION)
1336 return -ENXIO;
1337
1338 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1339 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1340
1341 tid_data = &priv->stations[sta_id].tid[tid];
1342 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1343 txq_id = tid_data->agg.txq_id;
1344 write_ptr = priv->txq[txq_id].q.write_ptr;
1345 read_ptr = priv->txq[txq_id].q.read_ptr;
1346
1347 /* The queue is not empty */
1348 if (write_ptr != read_ptr) {
1349 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1350 priv->stations[sta_id].tid[tid].agg.state =
1351 IWL_EMPTYING_HW_QUEUE_DELBA;
1352 return 0;
1353 }
1354
1355 IWL_DEBUG_HT("HW queue is empty\n");
1356 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1357
1358 spin_lock_irqsave(&priv->lock, flags);
1359 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1360 tx_fifo_id);
1361 spin_unlock_irqrestore(&priv->lock, flags);
1362
1363 if (ret)
1364 return ret;
1365
1366 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1367
1368 return 0;
1369}
1370EXPORT_SYMBOL(iwl_tx_agg_stop);
1371
1372int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1373{
1374 struct iwl_queue *q = &priv->txq[txq_id].q;
1375 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1376 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1377
1378 switch (priv->stations[sta_id].tid[tid].agg.state) {
1379 case IWL_EMPTYING_HW_QUEUE_DELBA:
1380 /* We are reclaiming the last packet of the */
1381 /* aggregated HW queue */
1382 if (txq_id == tid_data->agg.txq_id &&
1383 q->read_ptr == q->write_ptr) {
1384 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1385 int tx_fifo = default_tid_to_tx_fifo[tid];
1386 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1387 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1388 ssn, tx_fifo);
1389 tid_data->agg.state = IWL_AGG_OFF;
1390 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1391 }
1392 break;
1393 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1394 /* We are reclaiming the last packet of the queue */
1395 if (tid_data->tfds_in_queue == 0) {
1396 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1397 tid_data->agg.state = IWL_AGG_ON;
1398 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1399 }
1400 break;
1401 }
1402 return 0;
1403}
1404EXPORT_SYMBOL(iwl_txq_check_empty);
30e553e3 1405
653fa4a0
EG		 1406/**
1407 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1408 *
1409 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1410 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1411 */
1412static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1413 struct iwl_ht_agg *agg,
1414 struct iwl_compressed_ba_resp *ba_resp)
1415
1416{
1417 int i, sh, ack;
1418 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1419 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1420 u64 bitmap;
1421 int successes = 0;
1422 struct ieee80211_tx_info *info;
1423
1424 if (unlikely(!agg->wait_for_ba)) {
1425 IWL_ERROR("Received BA when not expected\n");
1426 return -EINVAL;
1427 }
1428
1429 /* Mark that the expected block-ack response arrived */
1430 agg->wait_for_ba = 0;
1431 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1432
1433 /* Calculate shift to align block-ack bits with our Tx window bits */
1434 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
1435 if (sh < 0) /* tbw something is wrong with indices */
1436 sh += 0x100;
1437
1438 /* don't use 64-bit values for now */
1439 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1440
1441 if (agg->frame_count > (64 - sh)) {
1442 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1443 return -1;
1444 }
1445
1446 /* check for success or failure according to the
1447 * transmitted bitmap and block-ack bitmap */
1448 bitmap &= agg->bitmap;
1449
1450 /* For each frame attempted in aggregation,
1451 * update driver's record of tx frame's status. */
1452 for (i = 0; i < agg->frame_count ; i++) {
4aa41f12 1453 ack = bitmap & (1ULL << i);
653fa4a0
EG		 1454 successes += !!ack;
1455 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1456 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
1457 agg->start_idx + i);
1458 }
1459
1460 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1461 memset(&info->status, 0, sizeof(info->status));
1462 info->flags = IEEE80211_TX_STAT_ACK;
1463 info->flags |= IEEE80211_TX_STAT_AMPDU;
1464 info->status.ampdu_ack_map = successes;
1465 info->status.ampdu_ack_len = agg->frame_count;
1466 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1467
1468 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1469
1470 return 0;
1471}
1472
1473/**
1474 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1475 *
1476 * Handles block-acknowledge notification from device, which reports success
1477 * of frames sent via aggregation.
1478 */
1479void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1480 struct iwl_rx_mem_buffer *rxb)
1481{
1482 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1483 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1484 int index;
1485 struct iwl_tx_queue *txq = NULL;
1486 struct iwl_ht_agg *agg;
653fa4a0
EG		 1487
1488 /* "flow" corresponds to Tx queue */
1489 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1490
1491 /* "ssn" is start of block-ack Tx window, corresponds to index
1492 * (in Tx queue's circular buffer) of first TFD/frame in window */
1493 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1494
1495 if (scd_flow >= priv->hw_params.max_txq_num) {
6f147926 1496 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n");
653fa4a0
EG		 1497 return;
1498 }
1499
1500 txq = &priv->txq[scd_flow];
1501 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
1502
1503 /* Find index just before block-ack window */
1504 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1505
1506 /* TODO: Need to get this copy more safely - now good for debug */
1507
e174961c 1508 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %pM, "
653fa4a0
EG		 1509 "sta_id = %d\n",
1510 agg->wait_for_ba,
e174961c 1511 (u8 *) &ba_resp->sta_addr_lo32,
653fa4a0
EG		 1512 ba_resp->sta_id);
1513 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1514 "%d, scd_ssn = %d\n",
1515 ba_resp->tid,
1516 ba_resp->seq_ctl,
1517 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1518 ba_resp->scd_flow,
1519 ba_resp->scd_ssn);
1520 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1521 agg->start_idx,
1522 (unsigned long long)agg->bitmap);
1523
1524 /* Update driver's record of ACK vs. not for each frame in window */
1525 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1526
1527 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1528 * block-ack window (we assume that they've been successfully
1529 * transmitted ... if not, it's too late anyway). */
1530 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1531 /* calculate mac80211 ampdu sw queue to wake */
1532 int ampdu_q =
1533 scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
1534 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1535 priv->stations[ba_resp->sta_id].
1536 tid[ba_resp->tid].tfds_in_queue -= freed;
1537 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1538 priv->mac80211_registered &&
1539 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
1540 ieee80211_wake_queue(priv->hw, ampdu_q);
1541
1542 iwl_txq_check_empty(priv, ba_resp->sta_id,
1543 ba_resp->tid, scd_flow);
1544 }
1545}
1546EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1547
994d31f7 1548#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW		 1549#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1550
1551const char *iwl_get_tx_fail_reason(u32 status)
1552{
1553 switch (status & TX_STATUS_MSK) {
1554 case TX_STATUS_SUCCESS:
1555 return "SUCCESS";
1556 TX_STATUS_ENTRY(SHORT_LIMIT);
1557 TX_STATUS_ENTRY(LONG_LIMIT);
1558 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1559 TX_STATUS_ENTRY(MGMNT_ABORT);
1560 TX_STATUS_ENTRY(NEXT_FRAG);
1561 TX_STATUS_ENTRY(LIFE_EXPIRE);
1562 TX_STATUS_ENTRY(DEST_PS);
1563 TX_STATUS_ENTRY(ABORTED);
1564 TX_STATUS_ENTRY(BT_RETRY);
1565 TX_STATUS_ENTRY(STA_INVALID);
1566 TX_STATUS_ENTRY(FRAG_DROPPED);
1567 TX_STATUS_ENTRY(TID_DISABLE);
1568 TX_STATUS_ENTRY(FRAME_FLUSHED);
1569 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1570 TX_STATUS_ENTRY(TX_LOCKED);
1571 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1572 }
1573
1574 return "UNKNOWN";
1575}
1576EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1577#endif /* CONFIG_IWLWIFI_DEBUG */
kernel source for telekom puls (alcatel/mediatek)