Commit | Line | Data |
---|---|---|
1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
1053d35f RR |
31 | #include <net/mac80211.h> |
32 | #include "iwl-eeprom.h" | |
33 | #include "iwl-dev.h" | |
34 | #include "iwl-core.h" | |
35 | #include "iwl-sta.h" | |
36 | #include "iwl-io.h" | |
37 | #include "iwl-helpers.h" | |
38 | ||
30e553e3 TW |
39 | static const u16 default_tid_to_tx_fifo[] = { |
40 | IWL_TX_FIFO_AC1, | |
41 | IWL_TX_FIFO_AC0, | |
42 | IWL_TX_FIFO_AC0, | |
43 | IWL_TX_FIFO_AC1, | |
44 | IWL_TX_FIFO_AC2, | |
45 | IWL_TX_FIFO_AC2, | |
46 | IWL_TX_FIFO_AC3, | |
47 | IWL_TX_FIFO_AC3, | |
48 | IWL_TX_FIFO_NONE, | |
49 | IWL_TX_FIFO_NONE, | |
50 | IWL_TX_FIFO_NONE, | |
51 | IWL_TX_FIFO_NONE, | |
52 | IWL_TX_FIFO_NONE, | |
53 | IWL_TX_FIFO_NONE, | |
54 | IWL_TX_FIFO_NONE, | |
55 | IWL_TX_FIFO_NONE, | |
56 | IWL_TX_FIFO_AC3 | |
57 | }; | |
58 | ||
4ddbb7d0 TW |
59 | static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv, |
60 | struct iwl_dma_ptr *ptr, size_t size) | |
61 | { | |
62 | ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma); | |
63 | if (!ptr->addr) | |
64 | return -ENOMEM; | |
65 | ptr->size = size; | |
66 | return 0; | |
67 | } | |
68 | ||
69 | static inline void iwl_free_dma_ptr(struct iwl_priv *priv, | |
70 | struct iwl_dma_ptr *ptr) | |
71 | { | |
72 | if (unlikely(!ptr->addr)) | |
73 | return; | |
74 | ||
75 | pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma); | |
76 | memset(ptr, 0, sizeof(*ptr)); | |
77 | } | |
78 | ||
fd4abac5 TW |
79 | /** |
80 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
81 | */ | |
82 | int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
83 | { | |
84 | u32 reg = 0; | |
85 | int ret = 0; | |
86 | int txq_id = txq->q.id; | |
87 | ||
88 | if (txq->need_update == 0) | |
89 | return ret; | |
90 | ||
91 | /* if we're trying to save power */ | |
92 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
93 | /* wake up nic if it's powered down ... | |
94 | * uCode will wake up, and interrupt us again, so next | |
95 | * time we'll skip this part. */ | |
96 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
97 | ||
98 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
e1623446 | 99 | IWL_DEBUG_INFO(priv, "Requesting wakeup, GP1 = 0x%x\n", reg); |
fd4abac5 TW |
100 | iwl_set_bit(priv, CSR_GP_CNTRL, |
101 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
102 | return ret; | |
103 | } | |
104 | ||
fd4abac5 TW |
105 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
106 | txq->q.write_ptr | (txq_id << 8)); | |
fd4abac5 TW |
107 | |
108 | /* else not in power-save mode, uCode will never sleep when we're | |
109 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
110 | } else | |
111 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
112 | txq->q.write_ptr | (txq_id << 8)); | |
113 | ||
114 | txq->need_update = 0; | |
115 | ||
116 | return ret; | |
117 | } | |
118 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
119 | ||
120 | ||
1053d35f RR |
121 | /** |
122 | * iwl_tx_queue_free - Deallocate DMA queue. | |
123 | * @txq: Transmit queue to deallocate. | |
124 | * | |
125 | * Empty queue by removing and destroying all BD's. | |
126 | * Free all buffers. | |
127 | * 0-fill, but do not free "txq" descriptor structure. | |
128 | */ | |
a8e74e27 | 129 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 130 | { |
da99c4b6 | 131 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
443cfd45 | 132 | struct iwl_queue *q = &txq->q; |
1053d35f | 133 | struct pci_dev *dev = priv->pci_dev; |
961ba60a | 134 | int i, len; |
1053d35f RR |
135 | |
136 | if (q->n_bd == 0) | |
137 | return; | |
138 | ||
139 | /* first, empty all BD's */ | |
140 | for (; q->write_ptr != q->read_ptr; | |
141 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
7aaa1d79 | 142 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
1053d35f | 143 | |
c2acea8e | 144 | len = sizeof(struct iwl_device_cmd) * q->n_window; |
1053d35f RR |
145 | |
146 | /* De-alloc array of command/tx buffers */ | |
961ba60a | 147 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 148 | kfree(txq->cmd[i]); |
1053d35f RR |
149 | |
150 | /* De-alloc circular buffer of TFDs */ | |
151 | if (txq->q.n_bd) | |
a8e74e27 | 152 | pci_free_consistent(dev, priv->hw_params.tfd_size * |
499b1883 | 153 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
1053d35f RR |
154 | |
155 | /* De-alloc array of per-TFD driver data */ | |
156 | kfree(txq->txb); | |
157 | txq->txb = NULL; | |
158 | ||
c2acea8e JB |
159 | /* deallocate arrays */ |
160 | kfree(txq->cmd); | |
161 | kfree(txq->meta); | |
162 | txq->cmd = NULL; | |
163 | txq->meta = NULL; | |
164 | ||
1053d35f RR |
165 | /* 0-fill queue descriptor structure */ |
166 | memset(txq, 0, sizeof(*txq)); | |
167 | } | |
a8e74e27 | 168 | EXPORT_SYMBOL(iwl_tx_queue_free); |
961ba60a TW |
169 | |
170 | /** | |
171 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
172 | * @txq: Transmit queue to deallocate. | |
173 | * | |
174 | * Empty queue by removing and destroying all BD's. | |
175 | * Free all buffers. | |
176 | * 0-fill, but do not free "txq" descriptor structure. | |
177 | */ | |
3e5d238f | 178 | void iwl_cmd_queue_free(struct iwl_priv *priv) |
961ba60a TW |
179 | { |
180 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
181 | struct iwl_queue *q = &txq->q; | |
182 | struct pci_dev *dev = priv->pci_dev; | |
183 | int i, len; | |
184 | ||
185 | if (q->n_bd == 0) | |
186 | return; | |
187 | ||
c2acea8e | 188 | len = sizeof(struct iwl_device_cmd) * q->n_window; |
961ba60a TW |
189 | len += IWL_MAX_SCAN_SIZE; |
190 | ||
191 | /* De-alloc array of command/tx buffers */ | |
192 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
193 | kfree(txq->cmd[i]); | |
194 | ||
195 | /* De-alloc circular buffer of TFDs */ | |
196 | if (txq->q.n_bd) | |
3e5d238f | 197 | pci_free_consistent(dev, priv->hw_params.tfd_size * |
499b1883 | 198 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
961ba60a | 199 | |
28142986 RC |
200 | /* deallocate arrays */ |
201 | kfree(txq->cmd); | |
202 | kfree(txq->meta); | |
203 | txq->cmd = NULL; | |
204 | txq->meta = NULL; | |
205 | ||
961ba60a TW |
206 | /* 0-fill queue descriptor structure */ |
207 | memset(txq, 0, sizeof(*txq)); | |
208 | } | |
3e5d238f AK |
209 | EXPORT_SYMBOL(iwl_cmd_queue_free); |
210 | ||
fd4abac5 TW |
211 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
212 | * DMA services | |
213 | * | |
214 | * Theory of operation | |
215 | * | |
216 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
217 | * of buffer descriptors, each of which points to one or more data buffers for | |
218 | * the device to read from or fill. Driver and device exchange status of each | |
219 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
220 | * entries in each circular buffer, to protect against confusing empty and full | |
221 | * queue states. | |
222 | * | |
223 | * The device reads or writes the data in the queues via the device's several | |
224 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
225 | * | |
226 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
227 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
228 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
229 | * Tx queue resumed. | |
230 | * | |
231 | * See more detailed info in iwl-4965-hw.h. | |
232 | ***************************************************/ | |
233 | ||
234 | int iwl_queue_space(const struct iwl_queue *q) | |
235 | { | |
236 | int s = q->read_ptr - q->write_ptr; | |
237 | ||
238 | if (q->read_ptr > q->write_ptr) | |
239 | s -= q->n_bd; | |
240 | ||
241 | if (s <= 0) | |
242 | s += q->n_window; | |
243 | /* keep some reserve to not confuse empty and full situations */ | |
244 | s -= 2; | |
245 | if (s < 0) | |
246 | s = 0; | |
247 | return s; | |
248 | } | |
249 | EXPORT_SYMBOL(iwl_queue_space); | |
250 | ||
251 | ||
1053d35f RR |
252 | /** |
253 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
254 | */ | |
443cfd45 | 255 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
256 | int count, int slots_num, u32 id) |
257 | { | |
258 | q->n_bd = count; | |
259 | q->n_window = slots_num; | |
260 | q->id = id; | |
261 | ||
262 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
263 | * and iwl_queue_dec_wrap are broken. */ | |
264 | BUG_ON(!is_power_of_2(count)); | |
265 | ||
266 | /* slots_num must be power-of-two size, otherwise | |
267 | * get_cmd_index is broken. */ | |
268 | BUG_ON(!is_power_of_2(slots_num)); | |
269 | ||
270 | q->low_mark = q->n_window / 4; | |
271 | if (q->low_mark < 4) | |
272 | q->low_mark = 4; | |
273 | ||
274 | q->high_mark = q->n_window / 8; | |
275 | if (q->high_mark < 2) | |
276 | q->high_mark = 2; | |
277 | ||
278 | q->write_ptr = q->read_ptr = 0; | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
283 | /** | |
284 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
285 | */ | |
286 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 287 | struct iwl_tx_queue *txq, u32 id) |
1053d35f RR |
288 | { |
289 | struct pci_dev *dev = priv->pci_dev; | |
3978e5bc | 290 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
291 | |
292 | /* Driver private data, only for Tx (not command) queues, | |
293 | * not shared with device. */ | |
294 | if (id != IWL_CMD_QUEUE_NUM) { | |
295 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
296 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
297 | if (!txq->txb) { | |
15b1687c | 298 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
299 | "structures failed\n"); |
300 | goto error; | |
301 | } | |
3978e5bc | 302 | } else { |
1053d35f | 303 | txq->txb = NULL; |
3978e5bc | 304 | } |
1053d35f RR |
305 | |
306 | /* Circular buffer of transmit frame descriptors (TFDs), | |
307 | * shared with device */ | |
3978e5bc | 308 | txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr); |
1053d35f | 309 | |
499b1883 | 310 | if (!txq->tfds) { |
3978e5bc | 311 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
312 | goto error; |
313 | } | |
314 | txq->q.id = id; | |
315 | ||
316 | return 0; | |
317 | ||
318 | error: | |
319 | kfree(txq->txb); | |
320 | txq->txb = NULL; | |
321 | ||
322 | return -ENOMEM; | |
323 | } | |
324 | ||
1053d35f RR |
325 | /** |
326 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
327 | */ | |
a8e74e27 SO |
328 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
329 | int slots_num, u32 txq_id) | |
1053d35f | 330 | { |
da99c4b6 | 331 | int i, len; |
73b7d742 | 332 | int ret; |
c2acea8e | 333 | int actual_slots = slots_num; |
1053d35f RR |
334 | |
335 | /* | |
336 | * Alloc buffer array for commands (Tx or other types of commands). | |
337 | * For the command queue (#4), allocate command space + one big | |
338 | * command for scan, since scan command is very huge; the system will | |
339 | * not have two scans at the same time, so only one is needed. | |
340 | * For normal Tx queues (all other queues), no super-size command | |
341 | * space is needed. | |
342 | */ | |
c2acea8e JB |
343 | if (txq_id == IWL_CMD_QUEUE_NUM) |
344 | actual_slots++; | |
345 | ||
346 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, | |
347 | GFP_KERNEL); | |
348 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, | |
349 | GFP_KERNEL); | |
350 | ||
351 | if (!txq->meta || !txq->cmd) | |
352 | goto out_free_arrays; | |
353 | ||
354 | len = sizeof(struct iwl_device_cmd); | |
355 | for (i = 0; i < actual_slots; i++) { | |
356 | /* only happens for cmd queue */ | |
357 | if (i == slots_num) | |
358 | len += IWL_MAX_SCAN_SIZE; | |
da99c4b6 | 359 | |
49898852 | 360 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 361 | if (!txq->cmd[i]) |
73b7d742 | 362 | goto err; |
da99c4b6 | 363 | } |
1053d35f RR |
364 | |
365 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
366 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
367 | if (ret) | |
368 | goto err; | |
1053d35f | 369 | |
1053d35f RR |
370 | txq->need_update = 0; |
371 | ||
45af8195 JB |
372 | /* aggregation TX queues will get their ID when aggregation begins */ |
373 | if (txq_id <= IWL_TX_FIFO_AC3) | |
374 | txq->swq_id = txq_id; | |
375 | ||
1053d35f RR |
376 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
377 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
378 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
379 | ||
380 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
381 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
382 | ||
383 | /* Tell device where to find queue */ | |
a8e74e27 | 384 | priv->cfg->ops->lib->txq_init(priv, txq); |
1053d35f RR |
385 | |
386 | return 0; | |
73b7d742 | 387 | err: |
c2acea8e | 388 | for (i = 0; i < actual_slots; i++) |
73b7d742 | 389 | kfree(txq->cmd[i]); |
c2acea8e JB |
390 | out_free_arrays: |
391 | kfree(txq->meta); | |
392 | kfree(txq->cmd); | |
73b7d742 | 393 | |
73b7d742 | 394 | return -ENOMEM; |
1053d35f | 395 | } |
a8e74e27 SO |
396 | EXPORT_SYMBOL(iwl_tx_queue_init); |
397 | ||
da1bc453 TW |
398 | /** |
399 | * iwl_hw_txq_ctx_free - Free TXQ Context | |
400 | * | |
401 | * Destroy all TX DMA queues and structures | |
402 | */ | |
403 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |
404 | { | |
405 | int txq_id; | |
406 | ||
407 | /* Tx queues */ | |
88804e2b WYG |
408 | if (priv->txq) |
409 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; | |
410 | txq_id++) | |
411 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
412 | iwl_cmd_queue_free(priv); | |
413 | else | |
414 | iwl_tx_queue_free(priv, txq_id); | |
4ddbb7d0 TW |
415 | iwl_free_dma_ptr(priv, &priv->kw); |
416 | ||
417 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
88804e2b WYG |
418 | |
419 | /* free tx queue structure */ | |
420 | iwl_free_txq_mem(priv); | |
da1bc453 TW |
421 | } |
422 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); | |
423 | ||
1053d35f RR |
424 | /** |
425 | * iwl_txq_ctx_reset - Reset TX queue context | |
a96a27f9 | 426 | * Destroys all DMA structures and initialize them again |
1053d35f RR |
427 | * |
428 | * @param priv | |
429 | * @return error code | |
430 | */ | |
431 | int iwl_txq_ctx_reset(struct iwl_priv *priv) | |
432 | { | |
433 | int ret = 0; | |
434 | int txq_id, slots_num; | |
da1bc453 | 435 | unsigned long flags; |
1053d35f | 436 | |
1053d35f RR |
437 | /* Free all tx/cmd queues and keep-warm buffer */ |
438 | iwl_hw_txq_ctx_free(priv); | |
439 | ||
4ddbb7d0 TW |
440 | ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls, |
441 | priv->hw_params.scd_bc_tbls_size); | |
442 | if (ret) { | |
15b1687c | 443 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); |
4ddbb7d0 TW |
444 | goto error_bc_tbls; |
445 | } | |
1053d35f | 446 | /* Alloc keep-warm buffer */ |
4ddbb7d0 | 447 | ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); |
1053d35f | 448 | if (ret) { |
15b1687c | 449 | IWL_ERR(priv, "Keep Warm allocation failed\n"); |
1053d35f RR |
450 | goto error_kw; |
451 | } | |
88804e2b WYG |
452 | |
453 | /* allocate tx queue structure */ | |
454 | ret = iwl_alloc_txq_mem(priv); | |
455 | if (ret) | |
456 | goto error; | |
457 | ||
da1bc453 | 458 | spin_lock_irqsave(&priv->lock, flags); |
1053d35f RR |
459 | |
460 | /* Turn off all Tx DMA fifos */ | |
da1bc453 TW |
461 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
462 | ||
4ddbb7d0 TW |
463 | /* Tell NIC where to find the "keep warm" buffer */ |
464 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
465 | ||
da1bc453 TW |
466 | spin_unlock_irqrestore(&priv->lock, flags); |
467 | ||
da1bc453 | 468 | /* Alloc and init all Tx queues, including the command queue (#4) */ |
1053d35f RR |
469 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
470 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
471 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
472 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
473 | txq_id); | |
474 | if (ret) { | |
15b1687c | 475 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); |
1053d35f RR |
476 | goto error; |
477 | } | |
478 | } | |
479 | ||
480 | return ret; | |
481 | ||
482 | error: | |
483 | iwl_hw_txq_ctx_free(priv); | |
4ddbb7d0 | 484 | iwl_free_dma_ptr(priv, &priv->kw); |
1053d35f | 485 | error_kw: |
4ddbb7d0 TW |
486 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); |
487 | error_bc_tbls: | |
1053d35f RR |
488 | return ret; |
489 | } | |
a33c2f47 | 490 | |
da1bc453 TW |
491 | /** |
492 | * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory | |
493 | */ | |
494 | void iwl_txq_ctx_stop(struct iwl_priv *priv) | |
495 | { | |
f3f911d1 | 496 | int ch; |
da1bc453 TW |
497 | unsigned long flags; |
498 | ||
da1bc453 TW |
499 | /* Turn off all Tx DMA fifos */ |
500 | spin_lock_irqsave(&priv->lock, flags); | |
da1bc453 TW |
501 | |
502 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
503 | ||
504 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
f3f911d1 ZY |
505 | for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) { |
506 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
da1bc453 | 507 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, |
f3f911d1 | 508 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
f056658b | 509 | 1000); |
da1bc453 | 510 | } |
da1bc453 TW |
511 | spin_unlock_irqrestore(&priv->lock, flags); |
512 | ||
513 | /* Deallocate memory for all Tx queues */ | |
514 | iwl_hw_txq_ctx_free(priv); | |
515 | } | |
516 | EXPORT_SYMBOL(iwl_txq_ctx_stop); | |
fd4abac5 TW |
517 | |
518 | /* | |
519 | * handle build REPLY_TX command notification. | |
520 | */ | |
521 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, | |
522 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 523 | struct ieee80211_tx_info *info, |
fd4abac5 | 524 | struct ieee80211_hdr *hdr, |
0e7690f1 | 525 | u8 std_id) |
fd4abac5 | 526 | { |
fd7c8a40 | 527 | __le16 fc = hdr->frame_control; |
fd4abac5 TW |
528 | __le32 tx_flags = tx_cmd->tx_flags; |
529 | ||
530 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 531 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
fd4abac5 | 532 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 533 | if (ieee80211_is_mgmt(fc)) |
fd4abac5 | 534 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 535 | if (ieee80211_is_probe_resp(fc) && |
fd4abac5 TW |
536 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
537 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
538 | } else { | |
539 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
540 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
541 | } | |
542 | ||
fd7c8a40 | 543 | if (ieee80211_is_back_req(fc)) |
fd4abac5 TW |
544 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; |
545 | ||
546 | ||
547 | tx_cmd->sta_id = std_id; | |
8b7b1e05 | 548 | if (ieee80211_has_morefrags(fc)) |
fd4abac5 TW |
549 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
550 | ||
fd7c8a40 HH |
551 | if (ieee80211_is_data_qos(fc)) { |
552 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
fd4abac5 TW |
553 | tx_cmd->tid_tspec = qc[0] & 0xf; |
554 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
555 | } else { | |
556 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
557 | } | |
558 | ||
a326a5d0 | 559 | priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags); |
fd4abac5 TW |
560 | |
561 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
562 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
563 | ||
564 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
565 | if (ieee80211_is_mgmt(fc)) { |
566 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
fd4abac5 TW |
567 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
568 | else | |
569 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
570 | } else { | |
571 | tx_cmd->timeout.pm_frame_timeout = 0; | |
572 | } | |
573 | ||
574 | tx_cmd->driver_txop = 0; | |
575 | tx_cmd->tx_flags = tx_flags; | |
576 | tx_cmd->next_frame_len = 0; | |
577 | } | |
578 | ||
579 | #define RTS_HCCA_RETRY_LIMIT 3 | |
580 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
581 | ||
582 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, | |
583 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 584 | struct ieee80211_tx_info *info, |
b58ef214 | 585 | __le16 fc, int is_hcca) |
fd4abac5 | 586 | { |
b58ef214 | 587 | u32 rate_flags; |
76eff18b | 588 | int rate_idx; |
b58ef214 DH |
589 | u8 rts_retry_limit; |
590 | u8 data_retry_limit; | |
fd4abac5 | 591 | u8 rate_plcp; |
2e92e6f2 | 592 | |
b58ef214 | 593 | /* Set retry limit on DATA packets and Probe Responses*/ |
1f0436f4 | 594 | if (ieee80211_is_probe_resp(fc)) |
b58ef214 DH |
595 | data_retry_limit = 3; |
596 | else | |
597 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
598 | tx_cmd->data_retry_limit = data_retry_limit; | |
fd4abac5 | 599 | |
b58ef214 DH |
600 | /* Set retry limit on RTS packets */ |
601 | rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT : | |
602 | RTS_DFAULT_RETRY_LIMIT; | |
603 | if (data_retry_limit < rts_retry_limit) | |
604 | rts_retry_limit = data_retry_limit; | |
605 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
fd4abac5 | 606 | |
b58ef214 DH |
607 | /* DATA packets will use the uCode station table for rate/antenna |
608 | * selection */ | |
fd4abac5 TW |
609 | if (ieee80211_is_data(fc)) { |
610 | tx_cmd->initial_rate_index = 0; | |
611 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
b58ef214 DH |
612 | return; |
613 | } | |
614 | ||
615 | /** | |
616 | * If the current TX rate stored in mac80211 has the MCS bit set, it's | |
617 | * not really a TX rate. Thus, we use the lowest supported rate for | |
618 | * this band. Also use the lowest supported rate if the stored rate | |
619 | * index is invalid. | |
620 | */ | |
621 | rate_idx = info->control.rates[0].idx; | |
622 | if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS || | |
623 | (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY)) | |
624 | rate_idx = rate_lowest_index(&priv->bands[info->band], | |
625 | info->control.sta); | |
626 | /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ | |
627 | if (info->band == IEEE80211_BAND_5GHZ) | |
628 | rate_idx += IWL_FIRST_OFDM_RATE; | |
629 | /* Get PLCP rate for tx_cmd->rate_n_flags */ | |
630 | rate_plcp = iwl_rates[rate_idx].plcp; | |
631 | /* Zero out flags for this packet */ | |
632 | rate_flags = 0; | |
fd4abac5 | 633 | |
b58ef214 DH |
634 | /* Set CCK flag as needed */ |
635 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
636 | rate_flags |= RATE_MCS_CCK_MSK; | |
637 | ||
638 | /* Set up RTS and CTS flags for certain packets */ | |
639 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
640 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
641 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
642 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
643 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
644 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { | |
645 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
646 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
647 | } | |
648 | break; | |
649 | default: | |
650 | break; | |
fd4abac5 TW |
651 | } |
652 | ||
b58ef214 DH |
653 | /* Set up antennas */ |
654 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant); | |
655 | rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant); | |
656 | ||
657 | /* Set the rate in the TX cmd */ | |
e7d326ac | 658 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); |
fd4abac5 TW |
659 | } |
660 | ||
661 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
e039fa4a | 662 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
663 | struct iwl_tx_cmd *tx_cmd, |
664 | struct sk_buff *skb_frag, | |
665 | int sta_id) | |
666 | { | |
e039fa4a | 667 | struct ieee80211_key_conf *keyconf = info->control.hw_key; |
fd4abac5 | 668 | |
ccc038ab | 669 | switch (keyconf->alg) { |
fd4abac5 TW |
670 | case ALG_CCMP: |
671 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
ccc038ab | 672 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
e039fa4a | 673 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 | 674 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; |
e1623446 | 675 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
fd4abac5 TW |
676 | break; |
677 | ||
678 | case ALG_TKIP: | |
679 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
ccc038ab | 680 | ieee80211_get_tkip_key(keyconf, skb_frag, |
fd4abac5 | 681 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
e1623446 | 682 | IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); |
fd4abac5 TW |
683 | break; |
684 | ||
685 | case ALG_WEP: | |
fd4abac5 | 686 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
ccc038ab EG |
687 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
688 | ||
689 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
690 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
691 | ||
692 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
fd4abac5 | 693 | |
e1623446 | 694 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
ccc038ab | 695 | "with key %d\n", keyconf->keyidx); |
fd4abac5 TW |
696 | break; |
697 | ||
698 | default: | |
978785a3 | 699 | IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg); |
fd4abac5 TW |
700 | break; |
701 | } | |
702 | } | |
703 | ||
fd4abac5 TW |
704 | /* |
705 | * start REPLY_TX command process | |
706 | */ | |
e039fa4a | 707 | int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
fd4abac5 TW |
708 | { |
709 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 710 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
f3674227 TW |
711 | struct iwl_tx_queue *txq; |
712 | struct iwl_queue *q; | |
c2acea8e JB |
713 | struct iwl_device_cmd *out_cmd; |
714 | struct iwl_cmd_meta *out_meta; | |
f3674227 TW |
715 | struct iwl_tx_cmd *tx_cmd; |
716 | int swq_id, txq_id; | |
fd4abac5 TW |
717 | dma_addr_t phys_addr; |
718 | dma_addr_t txcmd_phys; | |
719 | dma_addr_t scratch_phys; | |
be1a71a1 | 720 | u16 len, len_org, firstlen, secondlen; |
fd4abac5 | 721 | u16 seq_number = 0; |
fd7c8a40 | 722 | __le16 fc; |
0e7690f1 | 723 | u8 hdr_len; |
f3674227 | 724 | u8 sta_id; |
fd4abac5 TW |
725 | u8 wait_write_ptr = 0; |
726 | u8 tid = 0; | |
727 | u8 *qc = NULL; | |
728 | unsigned long flags; | |
729 | int ret; | |
730 | ||
731 | spin_lock_irqsave(&priv->lock, flags); | |
732 | if (iwl_is_rfkill(priv)) { | |
e1623446 | 733 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
fd4abac5 TW |
734 | goto drop_unlock; |
735 | } | |
736 | ||
fd7c8a40 | 737 | fc = hdr->frame_control; |
fd4abac5 TW |
738 | |
739 | #ifdef CONFIG_IWLWIFI_DEBUG | |
740 | if (ieee80211_is_auth(fc)) | |
e1623446 | 741 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 742 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 743 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 744 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 745 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
fd4abac5 TW |
746 | #endif |
747 | ||
aa065263 | 748 | /* drop all non-injected data frame if we are not associated */ |
fd7c8a40 | 749 | if (ieee80211_is_data(fc) && |
aa065263 | 750 | !(info->flags & IEEE80211_TX_CTL_INJECTED) && |
d10c4ec8 | 751 | (!iwl_is_associated(priv) || |
05c914fe | 752 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) || |
d10c4ec8 | 753 | !priv->assoc_station_added)) { |
e1623446 | 754 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
fd4abac5 TW |
755 | goto drop_unlock; |
756 | } | |
757 | ||
7294ec95 | 758 | hdr_len = ieee80211_hdrlen(fc); |
fd4abac5 TW |
759 | |
760 | /* Find (or create) index into station table for destination station */ | |
aa065263 GS |
761 | if (info->flags & IEEE80211_TX_CTL_INJECTED) |
762 | sta_id = priv->hw_params.bcast_sta_id; | |
763 | else | |
764 | sta_id = iwl_get_sta_id(priv, hdr); | |
fd4abac5 | 765 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 766 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 767 | hdr->addr1); |
3995bd93 | 768 | goto drop_unlock; |
fd4abac5 TW |
769 | } |
770 | ||
e1623446 | 771 | IWL_DEBUG_TX(priv, "station Id %d\n", sta_id); |
fd4abac5 | 772 | |
45af8195 | 773 | txq_id = skb_get_queue_mapping(skb); |
fd7c8a40 HH |
774 | if (ieee80211_is_data_qos(fc)) { |
775 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 776 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
e6a6cf4c RC |
777 | if (unlikely(tid >= MAX_TID_COUNT)) |
778 | goto drop_unlock; | |
f3674227 TW |
779 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
780 | seq_number &= IEEE80211_SCTL_SEQ; | |
781 | hdr->seq_ctrl = hdr->seq_ctrl & | |
c1b4aa3f | 782 | cpu_to_le16(IEEE80211_SCTL_FRAG); |
f3674227 | 783 | hdr->seq_ctrl |= cpu_to_le16(seq_number); |
fd4abac5 | 784 | seq_number += 0x10; |
fd4abac5 | 785 | /* aggregation is on for this <sta,tid> */ |
45af8195 | 786 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 | 787 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
fd4abac5 TW |
788 | } |
789 | ||
fd4abac5 | 790 | txq = &priv->txq[txq_id]; |
45af8195 | 791 | swq_id = txq->swq_id; |
fd4abac5 TW |
792 | q = &txq->q; |
793 | ||
3995bd93 JB |
794 | if (unlikely(iwl_queue_space(q) < q->high_mark)) |
795 | goto drop_unlock; | |
796 | ||
797 | if (ieee80211_is_data_qos(fc)) | |
798 | priv->stations[sta_id].tid[tid].tfds_in_queue++; | |
fd4abac5 | 799 | |
fd4abac5 TW |
800 | /* Set up driver data for this TFD */ |
801 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
802 | txq->txb[q->write_ptr].skb[0] = skb; | |
fd4abac5 TW |
803 | |
804 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
b88b15df | 805 | out_cmd = txq->cmd[q->write_ptr]; |
c2acea8e | 806 | out_meta = &txq->meta[q->write_ptr]; |
fd4abac5 TW |
807 | tx_cmd = &out_cmd->cmd.tx; |
808 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
809 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
810 | ||
811 | /* | |
812 | * Set up the Tx-command (not MAC!) header. | |
813 | * Store the chosen Tx queue and TFD index within the sequence field; | |
814 | * after Tx, uCode's Tx response will return this value so driver can | |
815 | * locate the frame within the tx queue and do post-tx processing. | |
816 | */ | |
817 | out_cmd->hdr.cmd = REPLY_TX; | |
818 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
819 | INDEX_TO_SEQ(q->write_ptr))); | |
820 | ||
821 | /* Copy MAC header from skb into command buffer */ | |
822 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
823 | ||
df833b1d RC |
824 | |
825 | /* Total # bytes to be transmitted */ | |
826 | len = (u16)skb->len; | |
827 | tx_cmd->len = cpu_to_le16(len); | |
828 | ||
829 | if (info->control.hw_key) | |
830 | iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); | |
831 | ||
832 | /* TODO need this for burst mode later on */ | |
833 | iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id); | |
20594eb0 | 834 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
df833b1d RC |
835 | |
836 | /* set is_hcca to 0; it probably will never be implemented */ | |
b58ef214 | 837 | iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0); |
df833b1d | 838 | |
22fdf3c9 | 839 | iwl_update_stats(priv, true, fc, len); |
fd4abac5 TW |
840 | /* |
841 | * Use the first empty entry in this queue's command buffer array | |
842 | * to contain the Tx command and MAC header concatenated together | |
843 | * (payload data will be in another buffer). | |
844 | * Size of this varies, due to varying MAC header length. | |
845 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
846 | * of the MAC header (device reads on dword boundaries). | |
847 | * We'll tell device about this padding later. | |
848 | */ | |
849 | len = sizeof(struct iwl_tx_cmd) + | |
850 | sizeof(struct iwl_cmd_header) + hdr_len; | |
851 | ||
852 | len_org = len; | |
be1a71a1 | 853 | firstlen = len = (len + 3) & ~3; |
fd4abac5 TW |
854 | |
855 | if (len_org != len) | |
856 | len_org = 1; | |
857 | else | |
858 | len_org = 0; | |
859 | ||
df833b1d RC |
860 | /* Tell NIC about any 2-byte padding after MAC header */ |
861 | if (len_org) | |
862 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
863 | ||
fd4abac5 TW |
864 | /* Physical address of this Tx command's header (not MAC header!), |
865 | * within command buffer array. */ | |
499b1883 | 866 | txcmd_phys = pci_map_single(priv->pci_dev, |
df833b1d | 867 | &out_cmd->hdr, len, |
96891cee | 868 | PCI_DMA_BIDIRECTIONAL); |
c2acea8e JB |
869 | pci_unmap_addr_set(out_meta, mapping, txcmd_phys); |
870 | pci_unmap_len_set(out_meta, len, len); | |
fd4abac5 TW |
871 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
872 | * first entry */ | |
7aaa1d79 SO |
873 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
874 | txcmd_phys, len, 1, 0); | |
fd4abac5 | 875 | |
df833b1d RC |
876 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
877 | txq->need_update = 1; | |
878 | if (qc) | |
879 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
880 | } else { | |
881 | wait_write_ptr = 1; | |
882 | txq->need_update = 0; | |
883 | } | |
fd4abac5 TW |
884 | |
885 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
886 | * if any (802.11 null frames have no payload). */ | |
be1a71a1 | 887 | secondlen = len = skb->len - hdr_len; |
fd4abac5 TW |
888 | if (len) { |
889 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
890 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
891 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
892 | phys_addr, len, | |
893 | 0, 0); | |
fd4abac5 TW |
894 | } |
895 | ||
fd4abac5 | 896 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
df833b1d RC |
897 | offsetof(struct iwl_tx_cmd, scratch); |
898 | ||
899 | len = sizeof(struct iwl_tx_cmd) + | |
900 | sizeof(struct iwl_cmd_header) + hdr_len; | |
901 | /* take back ownership of DMA buffer to enable update */ | |
902 | pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys, | |
903 | len, PCI_DMA_BIDIRECTIONAL); | |
fd4abac5 | 904 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
499b1883 | 905 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); |
fd4abac5 | 906 | |
d2ee9cd2 RC |
907 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n", |
908 | le16_to_cpu(out_cmd->hdr.sequence)); | |
909 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags)); | |
3d816c77 RC |
910 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); |
911 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
fd4abac5 TW |
912 | |
913 | /* Set up entry for this TFD in Tx byte-count array */ | |
7b80ece4 RC |
914 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
915 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, | |
df833b1d RC |
916 | le16_to_cpu(tx_cmd->len)); |
917 | ||
918 | pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys, | |
919 | len, PCI_DMA_BIDIRECTIONAL); | |
fd4abac5 | 920 | |
be1a71a1 JB |
921 | trace_iwlwifi_dev_tx(priv, |
922 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], | |
923 | sizeof(struct iwl_tfd), | |
924 | &out_cmd->hdr, firstlen, | |
925 | skb->data + hdr_len, secondlen); | |
926 | ||
fd4abac5 TW |
927 | /* Tell device the write index *just past* this latest filled TFD */ |
928 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
929 | ret = iwl_txq_update_write_ptr(priv, txq); | |
930 | spin_unlock_irqrestore(&priv->lock, flags); | |
931 | ||
932 | if (ret) | |
933 | return ret; | |
934 | ||
143b09ef | 935 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { |
fd4abac5 TW |
936 | if (wait_write_ptr) { |
937 | spin_lock_irqsave(&priv->lock, flags); | |
938 | txq->need_update = 1; | |
939 | iwl_txq_update_write_ptr(priv, txq); | |
940 | spin_unlock_irqrestore(&priv->lock, flags); | |
143b09ef | 941 | } else { |
e4e72fb4 | 942 | iwl_stop_queue(priv, txq->swq_id); |
fd4abac5 | 943 | } |
fd4abac5 TW |
944 | } |
945 | ||
946 | return 0; | |
947 | ||
948 | drop_unlock: | |
949 | spin_unlock_irqrestore(&priv->lock, flags); | |
fd4abac5 TW |
950 | return -1; |
951 | } | |
952 | EXPORT_SYMBOL(iwl_tx_skb); | |
953 | ||
954 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
955 | ||
956 | /** | |
957 | * iwl_enqueue_hcmd - enqueue a uCode command | |
958 | * @priv: device private data point | |
959 | * @cmd: a point to the ucode command structure | |
960 | * | |
961 | * The function returns < 0 values to indicate the operation is | |
962 | * failed. On success, it turns the index (> 0) of command in the | |
963 | * command queue. | |
964 | */ | |
965 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
966 | { | |
967 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
968 | struct iwl_queue *q = &txq->q; | |
c2acea8e JB |
969 | struct iwl_device_cmd *out_cmd; |
970 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 971 | dma_addr_t phys_addr; |
fd4abac5 | 972 | unsigned long flags; |
f3674227 TW |
973 | int len, ret; |
974 | u32 idx; | |
975 | u16 fix_size; | |
fd4abac5 TW |
976 | |
977 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
978 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
979 | ||
980 | /* If any of the command structures end up being larger than | |
981 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
982 | * we will need to increase the size of the TFD entries */ | |
983 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
c2acea8e | 984 | !(cmd->flags & CMD_SIZE_HUGE)); |
fd4abac5 | 985 | |
7812b167 WYG |
986 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
987 | IWL_DEBUG_INFO(priv, "Not sending command - RF/CT KILL\n"); | |
fd4abac5 TW |
988 | return -EIO; |
989 | } | |
990 | ||
c2acea8e | 991 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
15b1687c | 992 | IWL_ERR(priv, "No space for Tx\n"); |
7812b167 WYG |
993 | if (iwl_within_ct_kill_margin(priv)) |
994 | iwl_tt_enter_ct_kill(priv); | |
995 | else { | |
996 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); | |
997 | queue_work(priv->workqueue, &priv->restart); | |
998 | } | |
fd4abac5 TW |
999 | return -ENOSPC; |
1000 | } | |
1001 | ||
1002 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
1003 | ||
c2acea8e | 1004 | idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); |
da99c4b6 | 1005 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
1006 | out_meta = &txq->meta[idx]; |
1007 | ||
8ce73f3a | 1008 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1009 | out_meta->flags = cmd->flags; |
1010 | if (cmd->flags & CMD_WANT_SKB) | |
1011 | out_meta->source = cmd; | |
1012 | if (cmd->flags & CMD_ASYNC) | |
1013 | out_meta->callback = cmd->callback; | |
fd4abac5 TW |
1014 | |
1015 | out_cmd->hdr.cmd = cmd->id; | |
fd4abac5 TW |
1016 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); |
1017 | ||
1018 | /* At this point, the out_cmd now has all of the incoming cmd | |
1019 | * information */ | |
1020 | ||
1021 | out_cmd->hdr.flags = 0; | |
1022 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
1023 | INDEX_TO_SEQ(q->write_ptr)); | |
c2acea8e | 1024 | if (cmd->flags & CMD_SIZE_HUGE) |
9734cb23 | 1025 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
c2acea8e | 1026 | len = sizeof(struct iwl_device_cmd); |
df833b1d | 1027 | len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0; |
499b1883 | 1028 | |
fd4abac5 | 1029 | |
ded2ae7c EK |
1030 | #ifdef CONFIG_IWLWIFI_DEBUG |
1031 | switch (out_cmd->hdr.cmd) { | |
1032 | case REPLY_TX_LINK_QUALITY_CMD: | |
1033 | case SENSITIVITY_CMD: | |
e1623446 | 1034 | IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
1035 | "%d bytes at %d[%d]:%d\n", |
1036 | get_cmd_string(out_cmd->hdr.cmd), | |
1037 | out_cmd->hdr.cmd, | |
1038 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1039 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1040 | break; | |
1041 | default: | |
e1623446 | 1042 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
1043 | "%d bytes at %d[%d]:%d\n", |
1044 | get_cmd_string(out_cmd->hdr.cmd), | |
1045 | out_cmd->hdr.cmd, | |
1046 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1047 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1048 | } | |
1049 | #endif | |
fd4abac5 TW |
1050 | txq->need_update = 1; |
1051 | ||
518099a8 SO |
1052 | if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl) |
1053 | /* Set up entry in queue's byte count circular buffer */ | |
1054 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
fd4abac5 | 1055 | |
df833b1d RC |
1056 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
1057 | fix_size, PCI_DMA_BIDIRECTIONAL); | |
c2acea8e JB |
1058 | pci_unmap_addr_set(out_meta, mapping, phys_addr); |
1059 | pci_unmap_len_set(out_meta, len, fix_size); | |
df833b1d | 1060 | |
be1a71a1 JB |
1061 | trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags); |
1062 | ||
df833b1d RC |
1063 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
1064 | phys_addr, fix_size, 1, | |
1065 | U32_PAD(cmd->len)); | |
1066 | ||
fd4abac5 TW |
1067 | /* Increment and update queue's write index */ |
1068 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1069 | ret = iwl_txq_update_write_ptr(priv, txq); | |
1070 | ||
1071 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
1072 | return ret ? ret : idx; | |
1073 | } | |
1074 | ||
17b88929 TW |
1075 | int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
1076 | { | |
1077 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1078 | struct iwl_queue *q = &txq->q; | |
1079 | struct iwl_tx_info *tx_info; | |
1080 | int nfreed = 0; | |
1081 | ||
1082 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
15b1687c | 1083 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 TW |
1084 | "is out of range [0-%d] %d %d.\n", txq_id, |
1085 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1086 | return 0; | |
1087 | } | |
1088 | ||
499b1883 TW |
1089 | for (index = iwl_queue_inc_wrap(index, q->n_bd); |
1090 | q->read_ptr != index; | |
1091 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 TW |
1092 | |
1093 | tx_info = &txq->txb[txq->q.read_ptr]; | |
1094 | ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]); | |
1095 | tx_info->skb[0] = NULL; | |
17b88929 | 1096 | |
972cf447 TW |
1097 | if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl) |
1098 | priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq); | |
1099 | ||
7aaa1d79 | 1100 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
17b88929 TW |
1101 | nfreed++; |
1102 | } | |
1103 | return nfreed; | |
1104 | } | |
1105 | EXPORT_SYMBOL(iwl_tx_queue_reclaim); | |
1106 | ||
1107 | ||
1108 | /** | |
1109 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
1110 | * | |
1111 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1112 | * need to be reclaimed. As result, some free space forms. If there is | |
1113 | * enough free space (> low mark), wake the stack that feeds us. | |
1114 | */ | |
499b1883 TW |
1115 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, |
1116 | int idx, int cmd_idx) | |
17b88929 TW |
1117 | { |
1118 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1119 | struct iwl_queue *q = &txq->q; | |
1120 | int nfreed = 0; | |
1121 | ||
499b1883 | 1122 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 1123 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 1124 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 1125 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
1126 | return; |
1127 | } | |
1128 | ||
499b1883 | 1129 | pci_unmap_single(priv->pci_dev, |
c2acea8e JB |
1130 | pci_unmap_addr(&txq->meta[cmd_idx], mapping), |
1131 | pci_unmap_len(&txq->meta[cmd_idx], len), | |
96891cee | 1132 | PCI_DMA_BIDIRECTIONAL); |
499b1883 TW |
1133 | |
1134 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; | |
1135 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 1136 | |
499b1883 | 1137 | if (nfreed++ > 0) { |
15b1687c | 1138 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 TW |
1139 | q->write_ptr, q->read_ptr); |
1140 | queue_work(priv->workqueue, &priv->restart); | |
1141 | } | |
da99c4b6 | 1142 | |
17b88929 TW |
1143 | } |
1144 | } | |
1145 | ||
1146 | /** | |
1147 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
1148 | * @rxb: Rx buffer to reclaim | |
1149 | * | |
1150 | * If an Rx buffer has an async callback associated with it the callback | |
1151 | * will be executed. The attached skb (if present) will only be freed | |
1152 | * if the callback returns 1 | |
1153 | */ | |
1154 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1155 | { | |
2f301227 | 1156 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1157 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1158 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1159 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1160 | int cmd_index; |
9734cb23 | 1161 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
c2acea8e JB |
1162 | struct iwl_device_cmd *cmd; |
1163 | struct iwl_cmd_meta *meta; | |
17b88929 TW |
1164 | |
1165 | /* If a Tx command is being handled and it isn't in the actual | |
1166 | * command queue then there a command routing bug has been introduced | |
1167 | * in the queue management code. */ | |
55d6a3cd | 1168 | if (WARN(txq_id != IWL_CMD_QUEUE_NUM, |
01ef9323 WT |
1169 | "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n", |
1170 | txq_id, sequence, | |
1171 | priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr, | |
1172 | priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) { | |
ec741164 | 1173 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 1174 | return; |
01ef9323 | 1175 | } |
17b88929 TW |
1176 | |
1177 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
da99c4b6 | 1178 | cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; |
c2acea8e | 1179 | meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index]; |
17b88929 TW |
1180 | |
1181 | /* Input error checking is done when commands are added to queue. */ | |
c2acea8e | 1182 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
1183 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
1184 | rxb->page = NULL; | |
5696aea6 | 1185 | } else if (meta->callback) |
2f301227 | 1186 | meta->callback(priv, cmd, pkt); |
17b88929 | 1187 | |
499b1883 | 1188 | iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
17b88929 | 1189 | |
c2acea8e | 1190 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 TW |
1191 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
1192 | wake_up_interruptible(&priv->wait_command_queue); | |
1193 | } | |
1194 | } | |
1195 | EXPORT_SYMBOL(iwl_tx_cmd_complete); | |
1196 | ||
30e553e3 TW |
1197 | /* |
1198 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
1199 | * Called only when finding queue for aggregation. | |
1200 | * Should never return anything < 7, because they should already | |
1201 | * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6). | |
1202 | */ | |
1203 | static int iwl_txq_ctx_activate_free(struct iwl_priv *priv) | |
1204 | { | |
1205 | int txq_id; | |
1206 | ||
1207 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
1208 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
1209 | return txq_id; | |
1210 | return -1; | |
1211 | } | |
1212 | ||
1213 | int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn) | |
1214 | { | |
1215 | int sta_id; | |
1216 | int tx_fifo; | |
1217 | int txq_id; | |
1218 | int ret; | |
1219 | unsigned long flags; | |
1220 | struct iwl_tid_data *tid_data; | |
30e553e3 TW |
1221 | |
1222 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1223 | tx_fifo = default_tid_to_tx_fifo[tid]; | |
1224 | else | |
1225 | return -EINVAL; | |
1226 | ||
39aadf8c | 1227 | IWL_WARN(priv, "%s on ra = %pM tid = %d\n", |
e174961c | 1228 | __func__, ra, tid); |
30e553e3 TW |
1229 | |
1230 | sta_id = iwl_find_station(priv, ra); | |
3eb92969 WYG |
1231 | if (sta_id == IWL_INVALID_STATION) { |
1232 | IWL_ERR(priv, "Start AGG on invalid station\n"); | |
30e553e3 | 1233 | return -ENXIO; |
3eb92969 | 1234 | } |
082e708a RK |
1235 | if (unlikely(tid >= MAX_TID_COUNT)) |
1236 | return -EINVAL; | |
30e553e3 TW |
1237 | |
1238 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
15b1687c | 1239 | IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n"); |
30e553e3 TW |
1240 | return -ENXIO; |
1241 | } | |
1242 | ||
1243 | txq_id = iwl_txq_ctx_activate_free(priv); | |
3eb92969 WYG |
1244 | if (txq_id == -1) { |
1245 | IWL_ERR(priv, "No free aggregation queue available\n"); | |
30e553e3 | 1246 | return -ENXIO; |
3eb92969 | 1247 | } |
30e553e3 TW |
1248 | |
1249 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1250 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1251 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1252 | tid_data->agg.txq_id = txq_id; | |
45af8195 | 1253 | priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id); |
30e553e3 TW |
1254 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
1255 | ||
1256 | ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo, | |
1257 | sta_id, tid, *ssn); | |
1258 | if (ret) | |
1259 | return ret; | |
1260 | ||
1261 | if (tid_data->tfds_in_queue == 0) { | |
3eb92969 | 1262 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 TW |
1263 | tid_data->agg.state = IWL_AGG_ON; |
1264 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1265 | } else { | |
e1623446 | 1266 | IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n", |
30e553e3 TW |
1267 | tid_data->tfds_in_queue); |
1268 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1269 | } | |
1270 | return ret; | |
1271 | } | |
1272 | EXPORT_SYMBOL(iwl_tx_agg_start); | |
1273 | ||
1274 | int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid) | |
1275 | { | |
1276 | int tx_fifo_id, txq_id, sta_id, ssn = -1; | |
1277 | struct iwl_tid_data *tid_data; | |
1278 | int ret, write_ptr, read_ptr; | |
1279 | unsigned long flags; | |
30e553e3 TW |
1280 | |
1281 | if (!ra) { | |
15b1687c | 1282 | IWL_ERR(priv, "ra = NULL\n"); |
30e553e3 TW |
1283 | return -EINVAL; |
1284 | } | |
1285 | ||
e6a6cf4c RC |
1286 | if (unlikely(tid >= MAX_TID_COUNT)) |
1287 | return -EINVAL; | |
1288 | ||
30e553e3 TW |
1289 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) |
1290 | tx_fifo_id = default_tid_to_tx_fifo[tid]; | |
1291 | else | |
1292 | return -EINVAL; | |
1293 | ||
1294 | sta_id = iwl_find_station(priv, ra); | |
1295 | ||
a2f1cbeb WYG |
1296 | if (sta_id == IWL_INVALID_STATION) { |
1297 | IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid); | |
30e553e3 | 1298 | return -ENXIO; |
a2f1cbeb | 1299 | } |
30e553e3 TW |
1300 | |
1301 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON) | |
39aadf8c | 1302 | IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n"); |
30e553e3 TW |
1303 | |
1304 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1305 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1306 | txq_id = tid_data->agg.txq_id; | |
1307 | write_ptr = priv->txq[txq_id].q.write_ptr; | |
1308 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1309 | ||
1310 | /* The queue is not empty */ | |
1311 | if (write_ptr != read_ptr) { | |
e1623446 | 1312 | IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n"); |
30e553e3 TW |
1313 | priv->stations[sta_id].tid[tid].agg.state = |
1314 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
1315 | return 0; | |
1316 | } | |
1317 | ||
e1623446 | 1318 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 TW |
1319 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1320 | ||
1321 | spin_lock_irqsave(&priv->lock, flags); | |
1322 | ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn, | |
1323 | tx_fifo_id); | |
1324 | spin_unlock_irqrestore(&priv->lock, flags); | |
1325 | ||
1326 | if (ret) | |
1327 | return ret; | |
1328 | ||
1329 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1330 | ||
1331 | return 0; | |
1332 | } | |
1333 | EXPORT_SYMBOL(iwl_tx_agg_stop); | |
1334 | ||
1335 | int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id) | |
1336 | { | |
1337 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1338 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1339 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
1340 | ||
1341 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1342 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1343 | /* We are reclaiming the last packet of the */ | |
1344 | /* aggregated HW queue */ | |
3fd07a1e TW |
1345 | if ((txq_id == tid_data->agg.txq_id) && |
1346 | (q->read_ptr == q->write_ptr)) { | |
30e553e3 TW |
1347 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); |
1348 | int tx_fifo = default_tid_to_tx_fifo[tid]; | |
e1623446 | 1349 | IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n"); |
30e553e3 TW |
1350 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, |
1351 | ssn, tx_fifo); | |
1352 | tid_data->agg.state = IWL_AGG_OFF; | |
1353 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1354 | } | |
1355 | break; | |
1356 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1357 | /* We are reclaiming the last packet of the queue */ | |
1358 | if (tid_data->tfds_in_queue == 0) { | |
e1623446 | 1359 | IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n"); |
30e553e3 TW |
1360 | tid_data->agg.state = IWL_AGG_ON; |
1361 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1362 | } | |
1363 | break; | |
1364 | } | |
1365 | return 0; | |
1366 | } | |
1367 | EXPORT_SYMBOL(iwl_txq_check_empty); | |
30e553e3 | 1368 | |
653fa4a0 EG |
1369 | /** |
1370 | * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack | |
1371 | * | |
1372 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
1373 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
1374 | */ | |
1375 | static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |
1376 | struct iwl_ht_agg *agg, | |
1377 | struct iwl_compressed_ba_resp *ba_resp) | |
1378 | ||
1379 | { | |
1380 | int i, sh, ack; | |
1381 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); | |
1382 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1383 | u64 bitmap; | |
1384 | int successes = 0; | |
1385 | struct ieee80211_tx_info *info; | |
1386 | ||
1387 | if (unlikely(!agg->wait_for_ba)) { | |
15b1687c | 1388 | IWL_ERR(priv, "Received BA when not expected\n"); |
653fa4a0 EG |
1389 | return -EINVAL; |
1390 | } | |
1391 | ||
1392 | /* Mark that the expected block-ack response arrived */ | |
1393 | agg->wait_for_ba = 0; | |
e1623446 | 1394 | IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); |
653fa4a0 EG |
1395 | |
1396 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
3fd07a1e | 1397 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4); |
653fa4a0 EG |
1398 | if (sh < 0) /* tbw something is wrong with indices */ |
1399 | sh += 0x100; | |
1400 | ||
1401 | /* don't use 64-bit values for now */ | |
1402 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
1403 | ||
1404 | if (agg->frame_count > (64 - sh)) { | |
e1623446 | 1405 | IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size"); |
653fa4a0 EG |
1406 | return -1; |
1407 | } | |
1408 | ||
1409 | /* check for success or failure according to the | |
1410 | * transmitted bitmap and block-ack bitmap */ | |
1411 | bitmap &= agg->bitmap; | |
1412 | ||
1413 | /* For each frame attempted in aggregation, | |
1414 | * update driver's record of tx frame's status. */ | |
1415 | for (i = 0; i < agg->frame_count ; i++) { | |
4aa41f12 | 1416 | ack = bitmap & (1ULL << i); |
653fa4a0 | 1417 | successes += !!ack; |
e1623446 | 1418 | IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n", |
c3056065 | 1419 | ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff, |
653fa4a0 EG |
1420 | agg->start_idx + i); |
1421 | } | |
1422 | ||
1423 | info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]); | |
1424 | memset(&info->status, 0, sizeof(info->status)); | |
91a55ae6 | 1425 | info->flags |= IEEE80211_TX_STAT_ACK; |
653fa4a0 EG |
1426 | info->flags |= IEEE80211_TX_STAT_AMPDU; |
1427 | info->status.ampdu_ack_map = successes; | |
1428 | info->status.ampdu_ack_len = agg->frame_count; | |
1429 | iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info); | |
1430 | ||
e1623446 | 1431 | IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap); |
653fa4a0 EG |
1432 | |
1433 | return 0; | |
1434 | } | |
1435 | ||
1436 | /** | |
1437 | * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
1438 | * | |
1439 | * Handles block-acknowledge notification from device, which reports success | |
1440 | * of frames sent via aggregation. | |
1441 | */ | |
1442 | void iwl_rx_reply_compressed_ba(struct iwl_priv *priv, | |
1443 | struct iwl_rx_mem_buffer *rxb) | |
1444 | { | |
2f301227 | 1445 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
653fa4a0 | 1446 | struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; |
653fa4a0 EG |
1447 | struct iwl_tx_queue *txq = NULL; |
1448 | struct iwl_ht_agg *agg; | |
3fd07a1e TW |
1449 | int index; |
1450 | int sta_id; | |
1451 | int tid; | |
653fa4a0 EG |
1452 | |
1453 | /* "flow" corresponds to Tx queue */ | |
1454 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1455 | ||
1456 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
1457 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
1458 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
1459 | ||
1460 | if (scd_flow >= priv->hw_params.max_txq_num) { | |
15b1687c WT |
1461 | IWL_ERR(priv, |
1462 | "BUG_ON scd_flow is bigger than number of queues\n"); | |
653fa4a0 EG |
1463 | return; |
1464 | } | |
1465 | ||
1466 | txq = &priv->txq[scd_flow]; | |
3fd07a1e TW |
1467 | sta_id = ba_resp->sta_id; |
1468 | tid = ba_resp->tid; | |
1469 | agg = &priv->stations[sta_id].tid[tid].agg; | |
653fa4a0 EG |
1470 | |
1471 | /* Find index just before block-ack window */ | |
1472 | index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
1473 | ||
1474 | /* TODO: Need to get this copy more safely - now good for debug */ | |
1475 | ||
e1623446 | 1476 | IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, " |
653fa4a0 EG |
1477 | "sta_id = %d\n", |
1478 | agg->wait_for_ba, | |
e174961c | 1479 | (u8 *) &ba_resp->sta_addr_lo32, |
653fa4a0 | 1480 | ba_resp->sta_id); |
e1623446 | 1481 | IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " |
653fa4a0 EG |
1482 | "%d, scd_ssn = %d\n", |
1483 | ba_resp->tid, | |
1484 | ba_resp->seq_ctl, | |
1485 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
1486 | ba_resp->scd_flow, | |
1487 | ba_resp->scd_ssn); | |
e1623446 | 1488 | IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n", |
653fa4a0 EG |
1489 | agg->start_idx, |
1490 | (unsigned long long)agg->bitmap); | |
1491 | ||
1492 | /* Update driver's record of ACK vs. not for each frame in window */ | |
1493 | iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp); | |
1494 | ||
1495 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
1496 | * block-ack window (we assume that they've been successfully | |
1497 | * transmitted ... if not, it's too late anyway). */ | |
1498 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
1499 | /* calculate mac80211 ampdu sw queue to wake */ | |
653fa4a0 | 1500 | int freed = iwl_tx_queue_reclaim(priv, scd_flow, index); |
3fd07a1e TW |
1501 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1502 | ||
1503 | if ((iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1504 | priv->mac80211_registered && | |
1505 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) | |
e4e72fb4 | 1506 | iwl_wake_queue(priv, txq->swq_id); |
3fd07a1e TW |
1507 | |
1508 | iwl_txq_check_empty(priv, sta_id, tid, scd_flow); | |
653fa4a0 EG |
1509 | } |
1510 | } | |
1511 | EXPORT_SYMBOL(iwl_rx_reply_compressed_ba); | |
1512 | ||
994d31f7 | 1513 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1514 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x |
1515 | ||
1516 | const char *iwl_get_tx_fail_reason(u32 status) | |
1517 | { | |
1518 | switch (status & TX_STATUS_MSK) { | |
1519 | case TX_STATUS_SUCCESS: | |
1520 | return "SUCCESS"; | |
1521 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1522 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1523 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1524 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1525 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1526 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1527 | TX_STATUS_ENTRY(DEST_PS); | |
1528 | TX_STATUS_ENTRY(ABORTED); | |
1529 | TX_STATUS_ENTRY(BT_RETRY); | |
1530 | TX_STATUS_ENTRY(STA_INVALID); | |
1531 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1532 | TX_STATUS_ENTRY(TID_DISABLE); | |
1533 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1534 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1535 | TX_STATUS_ENTRY(TX_LOCKED); | |
1536 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1537 | } | |
1538 | ||
1539 | return "UNKNOWN"; | |
1540 | } | |
1541 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); | |
1542 | #endif /* CONFIG_IWLWIFI_DEBUG */ |