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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
1053d35f RR |
31 | #include <net/mac80211.h> |
32 | #include "iwl-eeprom.h" | |
33 | #include "iwl-dev.h" | |
34 | #include "iwl-core.h" | |
35 | #include "iwl-sta.h" | |
36 | #include "iwl-io.h" | |
37 | #include "iwl-helpers.h" | |
38 | ||
30e553e3 TW |
39 | static const u16 default_tid_to_tx_fifo[] = { |
40 | IWL_TX_FIFO_AC1, | |
41 | IWL_TX_FIFO_AC0, | |
42 | IWL_TX_FIFO_AC0, | |
43 | IWL_TX_FIFO_AC1, | |
44 | IWL_TX_FIFO_AC2, | |
45 | IWL_TX_FIFO_AC2, | |
46 | IWL_TX_FIFO_AC3, | |
47 | IWL_TX_FIFO_AC3, | |
48 | IWL_TX_FIFO_NONE, | |
49 | IWL_TX_FIFO_NONE, | |
50 | IWL_TX_FIFO_NONE, | |
51 | IWL_TX_FIFO_NONE, | |
52 | IWL_TX_FIFO_NONE, | |
53 | IWL_TX_FIFO_NONE, | |
54 | IWL_TX_FIFO_NONE, | |
55 | IWL_TX_FIFO_NONE, | |
56 | IWL_TX_FIFO_AC3 | |
57 | }; | |
58 | ||
30e553e3 | 59 | |
1053d35f RR |
60 | /** |
61 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
62 | * | |
63 | * Does NOT advance any TFD circular buffer read/write indexes | |
64 | * Does NOT free the TFD itself (which is within circular buffer) | |
65 | */ | |
16466903 | 66 | int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
1053d35f RR |
67 | { |
68 | struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0]; | |
69 | struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; | |
70 | struct pci_dev *dev = priv->pci_dev; | |
71 | int i; | |
72 | int counter = 0; | |
73 | int index, is_odd; | |
74 | ||
75 | /* Host command buffers stay mapped in memory, nothing to clean */ | |
76 | if (txq->q.id == IWL_CMD_QUEUE_NUM) | |
77 | return 0; | |
78 | ||
79 | /* Sanity check on number of chunks */ | |
80 | counter = IWL_GET_BITS(*bd, num_tbs); | |
81 | if (counter > MAX_NUM_OF_TBS) { | |
82 | IWL_ERROR("Too many chunks: %i\n", counter); | |
83 | /* @todo issue fatal error, it is quite serious situation */ | |
84 | return 0; | |
85 | } | |
86 | ||
87 | /* Unmap chunks, if any. | |
88 | * TFD info for odd chunks is different format than for even chunks. */ | |
89 | for (i = 0; i < counter; i++) { | |
90 | index = i / 2; | |
91 | is_odd = i & 0x1; | |
92 | ||
93 | if (is_odd) | |
94 | pci_unmap_single( | |
95 | dev, | |
96 | IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) | | |
97 | (IWL_GET_BITS(bd->pa[index], | |
98 | tb2_addr_hi20) << 16), | |
99 | IWL_GET_BITS(bd->pa[index], tb2_len), | |
100 | PCI_DMA_TODEVICE); | |
101 | ||
102 | else if (i > 0) | |
103 | pci_unmap_single(dev, | |
104 | le32_to_cpu(bd->pa[index].tb1_addr), | |
105 | IWL_GET_BITS(bd->pa[index], tb1_len), | |
106 | PCI_DMA_TODEVICE); | |
107 | ||
108 | /* Free SKB, if any, for this chunk */ | |
109 | if (txq->txb[txq->q.read_ptr].skb[i]) { | |
110 | struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i]; | |
111 | ||
112 | dev_kfree_skb(skb); | |
113 | txq->txb[txq->q.read_ptr].skb[i] = NULL; | |
114 | } | |
115 | } | |
116 | return 0; | |
117 | } | |
118 | EXPORT_SYMBOL(iwl_hw_txq_free_tfd); | |
119 | ||
fd4abac5 TW |
120 | |
121 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr, | |
122 | dma_addr_t addr, u16 len) | |
123 | { | |
124 | int index, is_odd; | |
125 | struct iwl_tfd_frame *tfd = ptr; | |
126 | u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs); | |
127 | ||
128 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
129 | if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) { | |
130 | IWL_ERROR("Error can not send more than %d chunks\n", | |
131 | MAX_NUM_OF_TBS); | |
132 | return -EINVAL; | |
133 | } | |
134 | ||
135 | index = num_tbs / 2; | |
136 | is_odd = num_tbs & 0x1; | |
137 | ||
138 | if (!is_odd) { | |
139 | tfd->pa[index].tb1_addr = cpu_to_le32(addr); | |
140 | IWL_SET_BITS(tfd->pa[index], tb1_addr_hi, | |
141 | iwl_get_dma_hi_address(addr)); | |
142 | IWL_SET_BITS(tfd->pa[index], tb1_len, len); | |
143 | } else { | |
144 | IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16, | |
145 | (u32) (addr & 0xffff)); | |
146 | IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16); | |
147 | IWL_SET_BITS(tfd->pa[index], tb2_len, len); | |
148 | } | |
149 | ||
150 | IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1); | |
151 | ||
152 | return 0; | |
153 | } | |
154 | EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd); | |
155 | ||
156 | /** | |
157 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
158 | */ | |
159 | int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
160 | { | |
161 | u32 reg = 0; | |
162 | int ret = 0; | |
163 | int txq_id = txq->q.id; | |
164 | ||
165 | if (txq->need_update == 0) | |
166 | return ret; | |
167 | ||
168 | /* if we're trying to save power */ | |
169 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
170 | /* wake up nic if it's powered down ... | |
171 | * uCode will wake up, and interrupt us again, so next | |
172 | * time we'll skip this part. */ | |
173 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
174 | ||
175 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
176 | IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg); | |
177 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
178 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
179 | return ret; | |
180 | } | |
181 | ||
182 | /* restore this queue's parameters in nic hardware. */ | |
183 | ret = iwl_grab_nic_access(priv); | |
184 | if (ret) | |
185 | return ret; | |
186 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
187 | txq->q.write_ptr | (txq_id << 8)); | |
188 | iwl_release_nic_access(priv); | |
189 | ||
190 | /* else not in power-save mode, uCode will never sleep when we're | |
191 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
192 | } else | |
193 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
194 | txq->q.write_ptr | (txq_id << 8)); | |
195 | ||
196 | txq->need_update = 0; | |
197 | ||
198 | return ret; | |
199 | } | |
200 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
201 | ||
202 | ||
1053d35f RR |
203 | /** |
204 | * iwl_tx_queue_free - Deallocate DMA queue. | |
205 | * @txq: Transmit queue to deallocate. | |
206 | * | |
207 | * Empty queue by removing and destroying all BD's. | |
208 | * Free all buffers. | |
209 | * 0-fill, but do not free "txq" descriptor structure. | |
210 | */ | |
16466903 | 211 | static void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
1053d35f | 212 | { |
443cfd45 | 213 | struct iwl_queue *q = &txq->q; |
1053d35f RR |
214 | struct pci_dev *dev = priv->pci_dev; |
215 | int len; | |
216 | ||
217 | if (q->n_bd == 0) | |
218 | return; | |
219 | ||
220 | /* first, empty all BD's */ | |
221 | for (; q->write_ptr != q->read_ptr; | |
222 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
223 | iwl_hw_txq_free_tfd(priv, txq); | |
224 | ||
225 | len = sizeof(struct iwl_cmd) * q->n_window; | |
226 | if (q->id == IWL_CMD_QUEUE_NUM) | |
227 | len += IWL_MAX_SCAN_SIZE; | |
228 | ||
229 | /* De-alloc array of command/tx buffers */ | |
230 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
231 | ||
232 | /* De-alloc circular buffer of TFDs */ | |
233 | if (txq->q.n_bd) | |
234 | pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) * | |
235 | txq->q.n_bd, txq->bd, txq->q.dma_addr); | |
236 | ||
237 | /* De-alloc array of per-TFD driver data */ | |
238 | kfree(txq->txb); | |
239 | txq->txb = NULL; | |
240 | ||
241 | /* 0-fill queue descriptor structure */ | |
242 | memset(txq, 0, sizeof(*txq)); | |
243 | } | |
244 | ||
fd4abac5 TW |
245 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
246 | * DMA services | |
247 | * | |
248 | * Theory of operation | |
249 | * | |
250 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
251 | * of buffer descriptors, each of which points to one or more data buffers for | |
252 | * the device to read from or fill. Driver and device exchange status of each | |
253 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
254 | * entries in each circular buffer, to protect against confusing empty and full | |
255 | * queue states. | |
256 | * | |
257 | * The device reads or writes the data in the queues via the device's several | |
258 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
259 | * | |
260 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
261 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
262 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
263 | * Tx queue resumed. | |
264 | * | |
265 | * See more detailed info in iwl-4965-hw.h. | |
266 | ***************************************************/ | |
267 | ||
268 | int iwl_queue_space(const struct iwl_queue *q) | |
269 | { | |
270 | int s = q->read_ptr - q->write_ptr; | |
271 | ||
272 | if (q->read_ptr > q->write_ptr) | |
273 | s -= q->n_bd; | |
274 | ||
275 | if (s <= 0) | |
276 | s += q->n_window; | |
277 | /* keep some reserve to not confuse empty and full situations */ | |
278 | s -= 2; | |
279 | if (s < 0) | |
280 | s = 0; | |
281 | return s; | |
282 | } | |
283 | EXPORT_SYMBOL(iwl_queue_space); | |
284 | ||
285 | ||
1053d35f RR |
286 | /** |
287 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
288 | */ | |
443cfd45 | 289 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
290 | int count, int slots_num, u32 id) |
291 | { | |
292 | q->n_bd = count; | |
293 | q->n_window = slots_num; | |
294 | q->id = id; | |
295 | ||
296 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
297 | * and iwl_queue_dec_wrap are broken. */ | |
298 | BUG_ON(!is_power_of_2(count)); | |
299 | ||
300 | /* slots_num must be power-of-two size, otherwise | |
301 | * get_cmd_index is broken. */ | |
302 | BUG_ON(!is_power_of_2(slots_num)); | |
303 | ||
304 | q->low_mark = q->n_window / 4; | |
305 | if (q->low_mark < 4) | |
306 | q->low_mark = 4; | |
307 | ||
308 | q->high_mark = q->n_window / 8; | |
309 | if (q->high_mark < 2) | |
310 | q->high_mark = 2; | |
311 | ||
312 | q->write_ptr = q->read_ptr = 0; | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | /** | |
318 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
319 | */ | |
320 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 321 | struct iwl_tx_queue *txq, u32 id) |
1053d35f RR |
322 | { |
323 | struct pci_dev *dev = priv->pci_dev; | |
324 | ||
325 | /* Driver private data, only for Tx (not command) queues, | |
326 | * not shared with device. */ | |
327 | if (id != IWL_CMD_QUEUE_NUM) { | |
328 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
329 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
330 | if (!txq->txb) { | |
331 | IWL_ERROR("kmalloc for auxiliary BD " | |
332 | "structures failed\n"); | |
333 | goto error; | |
334 | } | |
335 | } else | |
336 | txq->txb = NULL; | |
337 | ||
338 | /* Circular buffer of transmit frame descriptors (TFDs), | |
339 | * shared with device */ | |
340 | txq->bd = pci_alloc_consistent(dev, | |
341 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX, | |
342 | &txq->q.dma_addr); | |
343 | ||
344 | if (!txq->bd) { | |
345 | IWL_ERROR("pci_alloc_consistent(%zd) failed\n", | |
346 | sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX); | |
347 | goto error; | |
348 | } | |
349 | txq->q.id = id; | |
350 | ||
351 | return 0; | |
352 | ||
353 | error: | |
354 | kfree(txq->txb); | |
355 | txq->txb = NULL; | |
356 | ||
357 | return -ENOMEM; | |
358 | } | |
359 | ||
360 | /* | |
361 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
362 | * given Tx queue, and enable the DMA channel used for that queue. | |
363 | * | |
364 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
365 | * channels supported in hardware. | |
366 | */ | |
367 | static int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
16466903 | 368 | struct iwl_tx_queue *txq) |
1053d35f RR |
369 | { |
370 | int rc; | |
371 | unsigned long flags; | |
372 | int txq_id = txq->q.id; | |
373 | ||
374 | spin_lock_irqsave(&priv->lock, flags); | |
375 | rc = iwl_grab_nic_access(priv); | |
376 | if (rc) { | |
377 | spin_unlock_irqrestore(&priv->lock, flags); | |
378 | return rc; | |
379 | } | |
380 | ||
381 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
382 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
383 | txq->q.dma_addr >> 8); | |
384 | ||
385 | /* Enable DMA channel, using same id as for TFD queue */ | |
386 | iwl_write_direct32( | |
387 | priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), | |
388 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
389 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); | |
390 | iwl_release_nic_access(priv); | |
391 | spin_unlock_irqrestore(&priv->lock, flags); | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | /** | |
397 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
398 | */ | |
399 | static int iwl_tx_queue_init(struct iwl_priv *priv, | |
16466903 | 400 | struct iwl_tx_queue *txq, |
1053d35f RR |
401 | int slots_num, u32 txq_id) |
402 | { | |
403 | struct pci_dev *dev = priv->pci_dev; | |
404 | int len; | |
405 | int rc = 0; | |
406 | ||
407 | /* | |
408 | * Alloc buffer array for commands (Tx or other types of commands). | |
409 | * For the command queue (#4), allocate command space + one big | |
410 | * command for scan, since scan command is very huge; the system will | |
411 | * not have two scans at the same time, so only one is needed. | |
412 | * For normal Tx queues (all other queues), no super-size command | |
413 | * space is needed. | |
414 | */ | |
415 | len = sizeof(struct iwl_cmd) * slots_num; | |
416 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
417 | len += IWL_MAX_SCAN_SIZE; | |
418 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | |
419 | if (!txq->cmd) | |
420 | return -ENOMEM; | |
421 | ||
422 | /* Alloc driver data array and TFD circular buffer */ | |
423 | rc = iwl_tx_queue_alloc(priv, txq, txq_id); | |
424 | if (rc) { | |
425 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | |
426 | ||
427 | return -ENOMEM; | |
428 | } | |
429 | txq->need_update = 0; | |
430 | ||
431 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
432 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
433 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
434 | ||
435 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
436 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
437 | ||
438 | /* Tell device where to find queue */ | |
439 | iwl_hw_tx_queue_init(priv, txq); | |
440 | ||
441 | return 0; | |
442 | } | |
da1bc453 TW |
443 | /** |
444 | * iwl_hw_txq_ctx_free - Free TXQ Context | |
445 | * | |
446 | * Destroy all TX DMA queues and structures | |
447 | */ | |
448 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |
449 | { | |
450 | int txq_id; | |
451 | ||
452 | /* Tx queues */ | |
453 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
454 | iwl_tx_queue_free(priv, &priv->txq[txq_id]); | |
455 | ||
456 | /* Keep-warm buffer */ | |
457 | iwl_kw_free(priv); | |
458 | } | |
459 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); | |
460 | ||
1053d35f RR |
461 | |
462 | /** | |
463 | * iwl_txq_ctx_reset - Reset TX queue context | |
464 | * Destroys all DMA structures and initialise them again | |
465 | * | |
466 | * @param priv | |
467 | * @return error code | |
468 | */ | |
469 | int iwl_txq_ctx_reset(struct iwl_priv *priv) | |
470 | { | |
471 | int ret = 0; | |
472 | int txq_id, slots_num; | |
da1bc453 | 473 | unsigned long flags; |
1053d35f RR |
474 | |
475 | iwl_kw_free(priv); | |
476 | ||
477 | /* Free all tx/cmd queues and keep-warm buffer */ | |
478 | iwl_hw_txq_ctx_free(priv); | |
479 | ||
480 | /* Alloc keep-warm buffer */ | |
481 | ret = iwl_kw_alloc(priv); | |
482 | if (ret) { | |
483 | IWL_ERROR("Keep Warm allocation failed"); | |
484 | goto error_kw; | |
485 | } | |
da1bc453 TW |
486 | spin_lock_irqsave(&priv->lock, flags); |
487 | ret = iwl_grab_nic_access(priv); | |
488 | if (unlikely(ret)) { | |
489 | spin_unlock_irqrestore(&priv->lock, flags); | |
490 | goto error_reset; | |
491 | } | |
1053d35f RR |
492 | |
493 | /* Turn off all Tx DMA fifos */ | |
da1bc453 TW |
494 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
495 | ||
496 | iwl_release_nic_access(priv); | |
497 | spin_unlock_irqrestore(&priv->lock, flags); | |
498 | ||
1053d35f RR |
499 | |
500 | /* Tell nic where to find the keep-warm buffer */ | |
501 | ret = iwl_kw_init(priv); | |
502 | if (ret) { | |
503 | IWL_ERROR("kw_init failed\n"); | |
504 | goto error_reset; | |
505 | } | |
506 | ||
da1bc453 | 507 | /* Alloc and init all Tx queues, including the command queue (#4) */ |
1053d35f RR |
508 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
509 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
510 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
511 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
512 | txq_id); | |
513 | if (ret) { | |
514 | IWL_ERROR("Tx %d queue init failed\n", txq_id); | |
515 | goto error; | |
516 | } | |
517 | } | |
518 | ||
519 | return ret; | |
520 | ||
521 | error: | |
522 | iwl_hw_txq_ctx_free(priv); | |
523 | error_reset: | |
524 | iwl_kw_free(priv); | |
525 | error_kw: | |
526 | return ret; | |
527 | } | |
da1bc453 TW |
528 | /** |
529 | * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory | |
530 | */ | |
531 | void iwl_txq_ctx_stop(struct iwl_priv *priv) | |
532 | { | |
533 | ||
534 | int txq_id; | |
535 | unsigned long flags; | |
536 | ||
537 | ||
538 | /* Turn off all Tx DMA fifos */ | |
539 | spin_lock_irqsave(&priv->lock, flags); | |
540 | if (iwl_grab_nic_access(priv)) { | |
541 | spin_unlock_irqrestore(&priv->lock, flags); | |
542 | return; | |
543 | } | |
544 | ||
545 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
546 | ||
547 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
548 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { | |
549 | iwl_write_direct32(priv, | |
550 | FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0); | |
551 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, | |
552 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE | |
553 | (txq_id), 200); | |
554 | } | |
555 | iwl_release_nic_access(priv); | |
556 | spin_unlock_irqrestore(&priv->lock, flags); | |
557 | ||
558 | /* Deallocate memory for all Tx queues */ | |
559 | iwl_hw_txq_ctx_free(priv); | |
560 | } | |
561 | EXPORT_SYMBOL(iwl_txq_ctx_stop); | |
fd4abac5 TW |
562 | |
563 | /* | |
564 | * handle build REPLY_TX command notification. | |
565 | */ | |
566 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, | |
567 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 568 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
569 | struct ieee80211_hdr *hdr, |
570 | int is_unicast, u8 std_id) | |
571 | { | |
fd7c8a40 | 572 | __le16 fc = hdr->frame_control; |
fd4abac5 TW |
573 | __le32 tx_flags = tx_cmd->tx_flags; |
574 | ||
575 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 576 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
fd4abac5 | 577 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 578 | if (ieee80211_is_mgmt(fc)) |
fd4abac5 | 579 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 580 | if (ieee80211_is_probe_resp(fc) && |
fd4abac5 TW |
581 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
582 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
583 | } else { | |
584 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
585 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
586 | } | |
587 | ||
fd7c8a40 | 588 | if (ieee80211_is_back_req(fc)) |
fd4abac5 TW |
589 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; |
590 | ||
591 | ||
592 | tx_cmd->sta_id = std_id; | |
8b7b1e05 | 593 | if (ieee80211_has_morefrags(fc)) |
fd4abac5 TW |
594 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
595 | ||
fd7c8a40 HH |
596 | if (ieee80211_is_data_qos(fc)) { |
597 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
fd4abac5 TW |
598 | tx_cmd->tid_tspec = qc[0] & 0xf; |
599 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
600 | } else { | |
601 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
602 | } | |
603 | ||
e039fa4a | 604 | if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) { |
fd4abac5 TW |
605 | tx_flags |= TX_CMD_FLG_RTS_MSK; |
606 | tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
e039fa4a | 607 | } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) { |
fd4abac5 TW |
608 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
609 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
610 | } | |
611 | ||
612 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
613 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
614 | ||
615 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
616 | if (ieee80211_is_mgmt(fc)) { |
617 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
fd4abac5 TW |
618 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
619 | else | |
620 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
621 | } else { | |
622 | tx_cmd->timeout.pm_frame_timeout = 0; | |
623 | } | |
624 | ||
625 | tx_cmd->driver_txop = 0; | |
626 | tx_cmd->tx_flags = tx_flags; | |
627 | tx_cmd->next_frame_len = 0; | |
628 | } | |
629 | ||
630 | #define RTS_HCCA_RETRY_LIMIT 3 | |
631 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
632 | ||
633 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, | |
634 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 635 | struct ieee80211_tx_info *info, |
fd7c8a40 | 636 | __le16 fc, int sta_id, |
fd4abac5 TW |
637 | int is_hcca) |
638 | { | |
639 | u8 rts_retry_limit = 0; | |
640 | u8 data_retry_limit = 0; | |
641 | u8 rate_plcp; | |
642 | u16 rate_flags = 0; | |
2e92e6f2 JB |
643 | int rate_idx; |
644 | ||
e039fa4a | 645 | rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff, |
2e92e6f2 | 646 | IWL_RATE_COUNT - 1); |
fd4abac5 TW |
647 | |
648 | rate_plcp = iwl_rates[rate_idx].plcp; | |
649 | ||
650 | rts_retry_limit = (is_hcca) ? | |
651 | RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT; | |
652 | ||
653 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
654 | rate_flags |= RATE_MCS_CCK_MSK; | |
655 | ||
656 | ||
fd7c8a40 | 657 | if (ieee80211_is_probe_resp(fc)) { |
fd4abac5 TW |
658 | data_retry_limit = 3; |
659 | if (data_retry_limit < rts_retry_limit) | |
660 | rts_retry_limit = data_retry_limit; | |
661 | } else | |
662 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
663 | ||
664 | if (priv->data_retry_limit != -1) | |
665 | data_retry_limit = priv->data_retry_limit; | |
666 | ||
667 | ||
668 | if (ieee80211_is_data(fc)) { | |
669 | tx_cmd->initial_rate_index = 0; | |
670 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
671 | } else { | |
fd7c8a40 HH |
672 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { |
673 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
674 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
675 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
676 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
fd4abac5 TW |
677 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { |
678 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
679 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
680 | } | |
681 | break; | |
682 | default: | |
683 | break; | |
684 | } | |
685 | ||
686 | /* Alternate between antenna A and B for successive frames */ | |
687 | if (priv->use_ant_b_for_management_frame) { | |
688 | priv->use_ant_b_for_management_frame = 0; | |
689 | rate_flags |= RATE_MCS_ANT_B_MSK; | |
690 | } else { | |
691 | priv->use_ant_b_for_management_frame = 1; | |
692 | rate_flags |= RATE_MCS_ANT_A_MSK; | |
693 | } | |
694 | } | |
695 | ||
696 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
697 | tx_cmd->data_retry_limit = data_retry_limit; | |
e7d326ac | 698 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); |
fd4abac5 TW |
699 | } |
700 | ||
701 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
e039fa4a | 702 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
703 | struct iwl_tx_cmd *tx_cmd, |
704 | struct sk_buff *skb_frag, | |
705 | int sta_id) | |
706 | { | |
e039fa4a | 707 | struct ieee80211_key_conf *keyconf = info->control.hw_key; |
fd4abac5 | 708 | |
ccc038ab | 709 | switch (keyconf->alg) { |
fd4abac5 TW |
710 | case ALG_CCMP: |
711 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
ccc038ab | 712 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
e039fa4a | 713 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 TW |
714 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; |
715 | IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n"); | |
716 | break; | |
717 | ||
718 | case ALG_TKIP: | |
719 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
ccc038ab | 720 | ieee80211_get_tkip_key(keyconf, skb_frag, |
fd4abac5 TW |
721 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
722 | IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n"); | |
723 | break; | |
724 | ||
725 | case ALG_WEP: | |
fd4abac5 | 726 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
ccc038ab EG |
727 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
728 | ||
729 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
730 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
731 | ||
732 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
fd4abac5 TW |
733 | |
734 | IWL_DEBUG_TX("Configuring packet for WEP encryption " | |
ccc038ab | 735 | "with key %d\n", keyconf->keyidx); |
fd4abac5 TW |
736 | break; |
737 | ||
738 | default: | |
ccc038ab | 739 | printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg); |
fd4abac5 TW |
740 | break; |
741 | } | |
742 | } | |
743 | ||
744 | static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len) | |
745 | { | |
746 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
747 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
748 | priv->tx_stats[idx].cnt++; | |
749 | priv->tx_stats[idx].bytes += len; | |
750 | } | |
751 | ||
752 | /* | |
753 | * start REPLY_TX command process | |
754 | */ | |
e039fa4a | 755 | int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
fd4abac5 TW |
756 | { |
757 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 758 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
fd4abac5 TW |
759 | struct iwl_tfd_frame *tfd; |
760 | u32 *control_flags; | |
e2530083 | 761 | int txq_id = skb_get_queue_mapping(skb); |
fd4abac5 TW |
762 | struct iwl_tx_queue *txq = NULL; |
763 | struct iwl_queue *q = NULL; | |
764 | dma_addr_t phys_addr; | |
765 | dma_addr_t txcmd_phys; | |
766 | dma_addr_t scratch_phys; | |
767 | struct iwl_cmd *out_cmd = NULL; | |
768 | struct iwl_tx_cmd *tx_cmd; | |
769 | u16 len, idx, len_org; | |
770 | u16 seq_number = 0; | |
771 | u8 id, hdr_len, unicast; | |
772 | u8 sta_id; | |
fd7c8a40 | 773 | __le16 fc; |
fd4abac5 TW |
774 | u8 wait_write_ptr = 0; |
775 | u8 tid = 0; | |
776 | u8 *qc = NULL; | |
777 | unsigned long flags; | |
778 | int ret; | |
779 | ||
780 | spin_lock_irqsave(&priv->lock, flags); | |
781 | if (iwl_is_rfkill(priv)) { | |
782 | IWL_DEBUG_DROP("Dropping - RF KILL\n"); | |
783 | goto drop_unlock; | |
784 | } | |
785 | ||
786 | if (!priv->vif) { | |
787 | IWL_DEBUG_DROP("Dropping - !priv->vif\n"); | |
788 | goto drop_unlock; | |
789 | } | |
790 | ||
e039fa4a | 791 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == |
2e92e6f2 | 792 | IWL_INVALID_RATE) { |
fd4abac5 TW |
793 | IWL_ERROR("ERROR: No TX rate available.\n"); |
794 | goto drop_unlock; | |
795 | } | |
796 | ||
797 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
798 | id = 0; | |
799 | ||
fd7c8a40 | 800 | fc = hdr->frame_control; |
fd4abac5 TW |
801 | |
802 | #ifdef CONFIG_IWLWIFI_DEBUG | |
803 | if (ieee80211_is_auth(fc)) | |
804 | IWL_DEBUG_TX("Sending AUTH frame\n"); | |
fd7c8a40 | 805 | else if (ieee80211_is_assoc_req(fc)) |
fd4abac5 | 806 | IWL_DEBUG_TX("Sending ASSOC frame\n"); |
fd7c8a40 | 807 | else if (ieee80211_is_reassoc_req(fc)) |
fd4abac5 TW |
808 | IWL_DEBUG_TX("Sending REASSOC frame\n"); |
809 | #endif | |
810 | ||
811 | /* drop all data frame if we are not associated */ | |
fd7c8a40 | 812 | if (ieee80211_is_data(fc) && |
fd4abac5 TW |
813 | (!iwl_is_associated(priv) || |
814 | ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) || | |
815 | !priv->assoc_station_added)) { | |
816 | IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n"); | |
817 | goto drop_unlock; | |
818 | } | |
819 | ||
820 | spin_unlock_irqrestore(&priv->lock, flags); | |
821 | ||
fd7c8a40 | 822 | hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc)); |
fd4abac5 TW |
823 | |
824 | /* Find (or create) index into station table for destination station */ | |
825 | sta_id = iwl_get_sta_id(priv, hdr); | |
826 | if (sta_id == IWL_INVALID_STATION) { | |
827 | DECLARE_MAC_BUF(mac); | |
828 | ||
829 | IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n", | |
830 | print_mac(mac, hdr->addr1)); | |
831 | goto drop; | |
832 | } | |
833 | ||
834 | IWL_DEBUG_TX("station Id %d\n", sta_id); | |
835 | ||
fd7c8a40 HH |
836 | if (ieee80211_is_data_qos(fc)) { |
837 | qc = ieee80211_get_qos_ctl(hdr); | |
fd4abac5 TW |
838 | tid = qc[0] & 0xf; |
839 | seq_number = priv->stations[sta_id].tid[tid].seq_number & | |
840 | IEEE80211_SCTL_SEQ; | |
841 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
842 | (hdr->seq_ctrl & | |
843 | __constant_cpu_to_le16(IEEE80211_SCTL_FRAG)); | |
844 | seq_number += 0x10; | |
fd4abac5 | 845 | /* aggregation is on for this <sta,tid> */ |
e039fa4a | 846 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 TW |
847 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
848 | priv->stations[sta_id].tid[tid].tfds_in_queue++; | |
fd4abac5 TW |
849 | } |
850 | ||
851 | /* Descriptor for chosen Tx queue */ | |
852 | txq = &priv->txq[txq_id]; | |
853 | q = &txq->q; | |
854 | ||
855 | spin_lock_irqsave(&priv->lock, flags); | |
856 | ||
857 | /* Set up first empty TFD within this queue's circular TFD buffer */ | |
858 | tfd = &txq->bd[q->write_ptr]; | |
859 | memset(tfd, 0, sizeof(*tfd)); | |
860 | control_flags = (u32 *) tfd; | |
861 | idx = get_cmd_index(q, q->write_ptr, 0); | |
862 | ||
863 | /* Set up driver data for this TFD */ | |
864 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
865 | txq->txb[q->write_ptr].skb[0] = skb; | |
fd4abac5 TW |
866 | |
867 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
868 | out_cmd = &txq->cmd[idx]; | |
869 | tx_cmd = &out_cmd->cmd.tx; | |
870 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
871 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
872 | ||
873 | /* | |
874 | * Set up the Tx-command (not MAC!) header. | |
875 | * Store the chosen Tx queue and TFD index within the sequence field; | |
876 | * after Tx, uCode's Tx response will return this value so driver can | |
877 | * locate the frame within the tx queue and do post-tx processing. | |
878 | */ | |
879 | out_cmd->hdr.cmd = REPLY_TX; | |
880 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
881 | INDEX_TO_SEQ(q->write_ptr))); | |
882 | ||
883 | /* Copy MAC header from skb into command buffer */ | |
884 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
885 | ||
886 | /* | |
887 | * Use the first empty entry in this queue's command buffer array | |
888 | * to contain the Tx command and MAC header concatenated together | |
889 | * (payload data will be in another buffer). | |
890 | * Size of this varies, due to varying MAC header length. | |
891 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
892 | * of the MAC header (device reads on dword boundaries). | |
893 | * We'll tell device about this padding later. | |
894 | */ | |
895 | len = sizeof(struct iwl_tx_cmd) + | |
896 | sizeof(struct iwl_cmd_header) + hdr_len; | |
897 | ||
898 | len_org = len; | |
899 | len = (len + 3) & ~3; | |
900 | ||
901 | if (len_org != len) | |
902 | len_org = 1; | |
903 | else | |
904 | len_org = 0; | |
905 | ||
906 | /* Physical address of this Tx command's header (not MAC header!), | |
907 | * within command buffer array. */ | |
908 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx + | |
909 | offsetof(struct iwl_cmd, hdr); | |
910 | ||
911 | /* Add buffer containing Tx command and MAC(!) header to TFD's | |
912 | * first entry */ | |
913 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len); | |
914 | ||
e039fa4a JB |
915 | if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) |
916 | iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); | |
fd4abac5 TW |
917 | |
918 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
919 | * if any (802.11 null frames have no payload). */ | |
920 | len = skb->len - hdr_len; | |
921 | if (len) { | |
922 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
923 | len, PCI_DMA_TODEVICE); | |
924 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len); | |
925 | } | |
926 | ||
927 | /* Tell NIC about any 2-byte padding after MAC header */ | |
928 | if (len_org) | |
929 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
930 | ||
931 | /* Total # bytes to be transmitted */ | |
932 | len = (u16)skb->len; | |
933 | tx_cmd->len = cpu_to_le16(len); | |
934 | /* TODO need this for burst mode later on */ | |
e039fa4a | 935 | iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id); |
fd4abac5 TW |
936 | |
937 | /* set is_hcca to 0; it probably will never be implemented */ | |
e039fa4a | 938 | iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0); |
fd4abac5 | 939 | |
fd7c8a40 | 940 | iwl_update_tx_stats(priv, le16_to_cpu(fc), len); |
fd4abac5 TW |
941 | |
942 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
943 | offsetof(struct iwl_tx_cmd, scratch); | |
944 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
945 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys); | |
946 | ||
8b7b1e05 | 947 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
fd4abac5 TW |
948 | txq->need_update = 1; |
949 | if (qc) | |
950 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
951 | } else { | |
952 | wait_write_ptr = 1; | |
953 | txq->need_update = 0; | |
954 | } | |
955 | ||
956 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
957 | ||
958 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
959 | ||
960 | /* Set up entry for this TFD in Tx byte-count array */ | |
961 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len); | |
962 | ||
963 | /* Tell device the write index *just past* this latest filled TFD */ | |
964 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
965 | ret = iwl_txq_update_write_ptr(priv, txq); | |
966 | spin_unlock_irqrestore(&priv->lock, flags); | |
967 | ||
968 | if (ret) | |
969 | return ret; | |
970 | ||
971 | if ((iwl_queue_space(q) < q->high_mark) | |
972 | && priv->mac80211_registered) { | |
973 | if (wait_write_ptr) { | |
974 | spin_lock_irqsave(&priv->lock, flags); | |
975 | txq->need_update = 1; | |
976 | iwl_txq_update_write_ptr(priv, txq); | |
977 | spin_unlock_irqrestore(&priv->lock, flags); | |
978 | } | |
979 | ||
e2530083 | 980 | ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb)); |
fd4abac5 TW |
981 | } |
982 | ||
983 | return 0; | |
984 | ||
985 | drop_unlock: | |
986 | spin_unlock_irqrestore(&priv->lock, flags); | |
987 | drop: | |
988 | return -1; | |
989 | } | |
990 | EXPORT_SYMBOL(iwl_tx_skb); | |
991 | ||
992 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
993 | ||
994 | /** | |
995 | * iwl_enqueue_hcmd - enqueue a uCode command | |
996 | * @priv: device private data point | |
997 | * @cmd: a point to the ucode command structure | |
998 | * | |
999 | * The function returns < 0 values to indicate the operation is | |
1000 | * failed. On success, it turns the index (> 0) of command in the | |
1001 | * command queue. | |
1002 | */ | |
1003 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
1004 | { | |
1005 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
1006 | struct iwl_queue *q = &txq->q; | |
1007 | struct iwl_tfd_frame *tfd; | |
1008 | u32 *control_flags; | |
1009 | struct iwl_cmd *out_cmd; | |
1010 | u32 idx; | |
1011 | u16 fix_size; | |
1012 | dma_addr_t phys_addr; | |
1013 | int ret; | |
1014 | unsigned long flags; | |
1015 | ||
1016 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
1017 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
1018 | ||
1019 | /* If any of the command structures end up being larger than | |
1020 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
1021 | * we will need to increase the size of the TFD entries */ | |
1022 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
1023 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
1024 | ||
1025 | if (iwl_is_rfkill(priv)) { | |
1026 | IWL_DEBUG_INFO("Not sending command - RF KILL"); | |
1027 | return -EIO; | |
1028 | } | |
1029 | ||
1030 | if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { | |
1031 | IWL_ERROR("No space for Tx\n"); | |
1032 | return -ENOSPC; | |
1033 | } | |
1034 | ||
1035 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
1036 | ||
1037 | tfd = &txq->bd[q->write_ptr]; | |
1038 | memset(tfd, 0, sizeof(*tfd)); | |
1039 | ||
1040 | control_flags = (u32 *) tfd; | |
1041 | ||
1042 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); | |
1043 | out_cmd = &txq->cmd[idx]; | |
1044 | ||
1045 | out_cmd->hdr.cmd = cmd->id; | |
1046 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
1047 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
1048 | ||
1049 | /* At this point, the out_cmd now has all of the incoming cmd | |
1050 | * information */ | |
1051 | ||
1052 | out_cmd->hdr.flags = 0; | |
1053 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
1054 | INDEX_TO_SEQ(q->write_ptr)); | |
1055 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) | |
1056 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | |
1057 | ||
1058 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | |
1059 | offsetof(struct iwl_cmd, hdr); | |
1060 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); | |
1061 | ||
1062 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | |
1063 | "%d bytes at %d[%d]:%d\n", | |
1064 | get_cmd_string(out_cmd->hdr.cmd), | |
1065 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), | |
1066 | fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1067 | ||
1068 | txq->need_update = 1; | |
1069 | ||
1070 | /* Set up entry in queue's byte count circular buffer */ | |
1071 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
1072 | ||
1073 | /* Increment and update queue's write index */ | |
1074 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1075 | ret = iwl_txq_update_write_ptr(priv, txq); | |
1076 | ||
1077 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
1078 | return ret ? ret : idx; | |
1079 | } | |
1080 | ||
17b88929 TW |
1081 | int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
1082 | { | |
1083 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1084 | struct iwl_queue *q = &txq->q; | |
1085 | struct iwl_tx_info *tx_info; | |
1086 | int nfreed = 0; | |
1087 | ||
1088 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
1089 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
1090 | "is out of range [0-%d] %d %d.\n", txq_id, | |
1091 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
1096 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1097 | ||
1098 | tx_info = &txq->txb[txq->q.read_ptr]; | |
1099 | ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]); | |
1100 | tx_info->skb[0] = NULL; | |
17b88929 | 1101 | |
972cf447 TW |
1102 | if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl) |
1103 | priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq); | |
1104 | ||
1105 | iwl_hw_txq_free_tfd(priv, txq); | |
17b88929 TW |
1106 | nfreed++; |
1107 | } | |
1108 | return nfreed; | |
1109 | } | |
1110 | EXPORT_SYMBOL(iwl_tx_queue_reclaim); | |
1111 | ||
1112 | ||
1113 | /** | |
1114 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
1115 | * | |
1116 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1117 | * need to be reclaimed. As result, some free space forms. If there is | |
1118 | * enough free space (> low mark), wake the stack that feeds us. | |
1119 | */ | |
1120 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) | |
1121 | { | |
1122 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1123 | struct iwl_queue *q = &txq->q; | |
1124 | int nfreed = 0; | |
1125 | ||
1126 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
1127 | IWL_ERROR("Read index for DMA queue txq id (%d), index %d, " | |
1128 | "is out of range [0-%d] %d %d.\n", txq_id, | |
1129 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1130 | return; | |
1131 | } | |
1132 | ||
1133 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
1134 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
1135 | ||
1136 | if (nfreed > 1) { | |
1137 | IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index, | |
1138 | q->write_ptr, q->read_ptr); | |
1139 | queue_work(priv->workqueue, &priv->restart); | |
1140 | } | |
1141 | nfreed++; | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | /** | |
1146 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
1147 | * @rxb: Rx buffer to reclaim | |
1148 | * | |
1149 | * If an Rx buffer has an async callback associated with it the callback | |
1150 | * will be executed. The attached skb (if present) will only be freed | |
1151 | * if the callback returns 1 | |
1152 | */ | |
1153 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1154 | { | |
1155 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1156 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1157 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1158 | int index = SEQ_TO_INDEX(sequence); | |
1159 | int huge = sequence & SEQ_HUGE_FRAME; | |
1160 | int cmd_index; | |
1161 | struct iwl_cmd *cmd; | |
1162 | ||
1163 | /* If a Tx command is being handled and it isn't in the actual | |
1164 | * command queue then there a command routing bug has been introduced | |
1165 | * in the queue management code. */ | |
1166 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
1167 | IWL_ERROR("Error wrong command queue %d command id 0x%X\n", | |
1168 | txq_id, pkt->hdr.cmd); | |
1169 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); | |
1170 | ||
1171 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
1172 | cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | |
1173 | ||
1174 | /* Input error checking is done when commands are added to queue. */ | |
1175 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
1176 | cmd->meta.source->u.skb = rxb->skb; | |
1177 | rxb->skb = NULL; | |
1178 | } else if (cmd->meta.u.callback && | |
1179 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
1180 | rxb->skb = NULL; | |
1181 | ||
1182 | iwl_hcmd_queue_reclaim(priv, txq_id, index); | |
1183 | ||
1184 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
1185 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
1186 | wake_up_interruptible(&priv->wait_command_queue); | |
1187 | } | |
1188 | } | |
1189 | EXPORT_SYMBOL(iwl_tx_cmd_complete); | |
1190 | ||
30e553e3 TW |
1191 | /* |
1192 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
1193 | * Called only when finding queue for aggregation. | |
1194 | * Should never return anything < 7, because they should already | |
1195 | * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6). | |
1196 | */ | |
1197 | static int iwl_txq_ctx_activate_free(struct iwl_priv *priv) | |
1198 | { | |
1199 | int txq_id; | |
1200 | ||
1201 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
1202 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
1203 | return txq_id; | |
1204 | return -1; | |
1205 | } | |
1206 | ||
1207 | int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn) | |
1208 | { | |
1209 | int sta_id; | |
1210 | int tx_fifo; | |
1211 | int txq_id; | |
1212 | int ret; | |
1213 | unsigned long flags; | |
1214 | struct iwl_tid_data *tid_data; | |
1215 | DECLARE_MAC_BUF(mac); | |
1216 | ||
1217 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1218 | tx_fifo = default_tid_to_tx_fifo[tid]; | |
1219 | else | |
1220 | return -EINVAL; | |
1221 | ||
1222 | IWL_WARNING("%s on ra = %s tid = %d\n", | |
1223 | __func__, print_mac(mac, ra), tid); | |
1224 | ||
1225 | sta_id = iwl_find_station(priv, ra); | |
1226 | if (sta_id == IWL_INVALID_STATION) | |
1227 | return -ENXIO; | |
1228 | ||
1229 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
1230 | IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n"); | |
1231 | return -ENXIO; | |
1232 | } | |
1233 | ||
1234 | txq_id = iwl_txq_ctx_activate_free(priv); | |
1235 | if (txq_id == -1) | |
1236 | return -ENXIO; | |
1237 | ||
1238 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1239 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1240 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1241 | tid_data->agg.txq_id = txq_id; | |
1242 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1243 | ||
1244 | ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo, | |
1245 | sta_id, tid, *ssn); | |
1246 | if (ret) | |
1247 | return ret; | |
1248 | ||
1249 | if (tid_data->tfds_in_queue == 0) { | |
1250 | printk(KERN_ERR "HW queue is empty\n"); | |
1251 | tid_data->agg.state = IWL_AGG_ON; | |
1252 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1253 | } else { | |
1254 | IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n", | |
1255 | tid_data->tfds_in_queue); | |
1256 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1257 | } | |
1258 | return ret; | |
1259 | } | |
1260 | EXPORT_SYMBOL(iwl_tx_agg_start); | |
1261 | ||
1262 | int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid) | |
1263 | { | |
1264 | int tx_fifo_id, txq_id, sta_id, ssn = -1; | |
1265 | struct iwl_tid_data *tid_data; | |
1266 | int ret, write_ptr, read_ptr; | |
1267 | unsigned long flags; | |
1268 | DECLARE_MAC_BUF(mac); | |
1269 | ||
1270 | if (!ra) { | |
1271 | IWL_ERROR("ra = NULL\n"); | |
1272 | return -EINVAL; | |
1273 | } | |
1274 | ||
1275 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1276 | tx_fifo_id = default_tid_to_tx_fifo[tid]; | |
1277 | else | |
1278 | return -EINVAL; | |
1279 | ||
1280 | sta_id = iwl_find_station(priv, ra); | |
1281 | ||
1282 | if (sta_id == IWL_INVALID_STATION) | |
1283 | return -ENXIO; | |
1284 | ||
1285 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON) | |
1286 | IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n"); | |
1287 | ||
1288 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1289 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1290 | txq_id = tid_data->agg.txq_id; | |
1291 | write_ptr = priv->txq[txq_id].q.write_ptr; | |
1292 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1293 | ||
1294 | /* The queue is not empty */ | |
1295 | if (write_ptr != read_ptr) { | |
1296 | IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n"); | |
1297 | priv->stations[sta_id].tid[tid].agg.state = | |
1298 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | IWL_DEBUG_HT("HW queue is empty\n"); | |
1303 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; | |
1304 | ||
1305 | spin_lock_irqsave(&priv->lock, flags); | |
1306 | ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn, | |
1307 | tx_fifo_id); | |
1308 | spin_unlock_irqrestore(&priv->lock, flags); | |
1309 | ||
1310 | if (ret) | |
1311 | return ret; | |
1312 | ||
1313 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | EXPORT_SYMBOL(iwl_tx_agg_stop); | |
1318 | ||
1319 | int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id) | |
1320 | { | |
1321 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1322 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1323 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
1324 | ||
1325 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1326 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1327 | /* We are reclaiming the last packet of the */ | |
1328 | /* aggregated HW queue */ | |
1329 | if (txq_id == tid_data->agg.txq_id && | |
1330 | q->read_ptr == q->write_ptr) { | |
1331 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); | |
1332 | int tx_fifo = default_tid_to_tx_fifo[tid]; | |
1333 | IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n"); | |
1334 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, | |
1335 | ssn, tx_fifo); | |
1336 | tid_data->agg.state = IWL_AGG_OFF; | |
1337 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1338 | } | |
1339 | break; | |
1340 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1341 | /* We are reclaiming the last packet of the queue */ | |
1342 | if (tid_data->tfds_in_queue == 0) { | |
1343 | IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n"); | |
1344 | tid_data->agg.state = IWL_AGG_ON; | |
1345 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1346 | } | |
1347 | break; | |
1348 | } | |
1349 | return 0; | |
1350 | } | |
1351 | EXPORT_SYMBOL(iwl_txq_check_empty); | |
30e553e3 | 1352 | |
a332f8d6 TW |
1353 | #ifdef CONFIG_IWLWIF_DEBUG |
1354 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
1355 | ||
1356 | const char *iwl_get_tx_fail_reason(u32 status) | |
1357 | { | |
1358 | switch (status & TX_STATUS_MSK) { | |
1359 | case TX_STATUS_SUCCESS: | |
1360 | return "SUCCESS"; | |
1361 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1362 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1363 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1364 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1365 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1366 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1367 | TX_STATUS_ENTRY(DEST_PS); | |
1368 | TX_STATUS_ENTRY(ABORTED); | |
1369 | TX_STATUS_ENTRY(BT_RETRY); | |
1370 | TX_STATUS_ENTRY(STA_INVALID); | |
1371 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1372 | TX_STATUS_ENTRY(TID_DISABLE); | |
1373 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1374 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1375 | TX_STATUS_ENTRY(TX_LOCKED); | |
1376 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1377 | } | |
1378 | ||
1379 | return "UNKNOWN"; | |
1380 | } | |
1381 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); | |
1382 | #endif /* CONFIG_IWLWIFI_DEBUG */ |