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1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | #include <linux/sched.h> | |
30 | #include <linux/wait.h> | |
31 | ||
32 | #include "iwl-dev.h" | |
33 | #include "iwl-agn.h" | |
34 | #include "iwl-core.h" | |
35 | #include "iwl-io.h" | |
36 | #include "iwl-helpers.h" | |
37 | #include "iwl-trans-int-pcie.h" | |
38 | ||
39 | /****************************************************************************** | |
40 | * | |
41 | * RX path functions | |
42 | * | |
43 | ******************************************************************************/ | |
44 | ||
45 | /* | |
46 | * Rx theory of operation | |
47 | * | |
48 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
49 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
50 | * used not only for Rx frames, but for any command response or notification | |
51 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
52 | * of indexes into the circular buffer. | |
53 | * | |
54 | * Rx Queue Indexes | |
55 | * The host/firmware share two index registers for managing the Rx buffers. | |
56 | * | |
57 | * The READ index maps to the first position that the firmware may be writing | |
58 | * to -- the driver can read up to (but not including) this position and get | |
59 | * good data. | |
60 | * The READ index is managed by the firmware once the card is enabled. | |
61 | * | |
62 | * The WRITE index maps to the last position the driver has read from -- the | |
63 | * position preceding WRITE is the last slot the firmware can place a packet. | |
64 | * | |
65 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
66 | * WRITE = READ. | |
67 | * | |
68 | * During initialization, the host sets up the READ queue position to the first | |
69 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
70 | * | |
71 | * When the firmware places a packet in a buffer, it will advance the READ index | |
72 | * and fire the RX interrupt. The driver can then query the READ index and | |
73 | * process as many packets as possible, moving the WRITE index forward as it | |
74 | * resets the Rx queue buffers with new memory. | |
75 | * | |
76 | * The management in the driver is as follows: | |
77 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
78 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
79 | * to replenish the iwl->rxq->rx_free. | |
80 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
81 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
82 | * 'processed' and 'read' driver indexes as well) | |
83 | * + A received packet is processed and handed to the kernel network stack, | |
84 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
85 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
86 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
87 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
88 | * were enough free buffers and RX_STALLED is set it is cleared. | |
89 | * | |
90 | * | |
91 | * Driver sequence: | |
92 | * | |
93 | * iwl_rx_queue_alloc() Allocates rx_free | |
94 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
95 | * iwl_rx_queue_restock | |
96 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
97 | * queue, updates firmware pointers, and updates | |
98 | * the WRITE index. If insufficient rx_free buffers | |
99 | * are available, schedules iwl_rx_replenish | |
100 | * | |
101 | * -- enable interrupts -- | |
102 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
103 | * READ INDEX, detaching the SKB from the pool. | |
104 | * Moves the packet buffer from queue to rx_used. | |
105 | * Calls iwl_rx_queue_restock to refill any empty | |
106 | * slots. | |
107 | * ... | |
108 | * | |
109 | */ | |
110 | ||
111 | /** | |
112 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
113 | */ | |
114 | static int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
115 | { | |
116 | int s = q->read - q->write; | |
117 | if (s <= 0) | |
118 | s += RX_QUEUE_SIZE; | |
119 | /* keep some buffer to not confuse full and empty queue */ | |
120 | s -= 2; | |
121 | if (s < 0) | |
122 | s = 0; | |
123 | return s; | |
124 | } | |
125 | ||
126 | /** | |
127 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
128 | */ | |
129 | void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, | |
130 | struct iwl_rx_queue *q) | |
131 | { | |
132 | unsigned long flags; | |
133 | u32 reg; | |
134 | ||
135 | spin_lock_irqsave(&q->lock, flags); | |
136 | ||
137 | if (q->need_update == 0) | |
138 | goto exit_unlock; | |
139 | ||
140 | if (priv->cfg->base_params->shadow_reg_enable) { | |
141 | /* shadow register enabled */ | |
142 | /* Device expects a multiple of 8 */ | |
143 | q->write_actual = (q->write & ~0x7); | |
144 | iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write_actual); | |
145 | } else { | |
146 | /* If power-saving is in use, make sure device is awake */ | |
147 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
148 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
149 | ||
150 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
151 | IWL_DEBUG_INFO(priv, | |
152 | "Rx queue requesting wakeup," | |
153 | " GP1 = 0x%x\n", reg); | |
154 | iwl_set_bit(priv, CSR_GP_CNTRL, | |
155 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
156 | goto exit_unlock; | |
157 | } | |
158 | ||
159 | q->write_actual = (q->write & ~0x7); | |
160 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, | |
161 | q->write_actual); | |
162 | ||
163 | /* Else device is assumed to be awake */ | |
164 | } else { | |
165 | /* Device expects a multiple of 8 */ | |
166 | q->write_actual = (q->write & ~0x7); | |
167 | iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, | |
168 | q->write_actual); | |
169 | } | |
170 | } | |
171 | q->need_update = 0; | |
172 | ||
173 | exit_unlock: | |
174 | spin_unlock_irqrestore(&q->lock, flags); | |
175 | } | |
176 | ||
177 | /** | |
178 | * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
179 | */ | |
180 | static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv, | |
181 | dma_addr_t dma_addr) | |
182 | { | |
183 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
184 | } | |
185 | ||
186 | /** | |
187 | * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool | |
188 | * | |
189 | * If there are slots in the RX queue that need to be restocked, | |
190 | * and we have free pre-allocated buffers, fill the ranks as much | |
191 | * as we can, pulling from rx_free. | |
192 | * | |
193 | * This moves the 'write' index forward to catch up with 'processed', and | |
194 | * also updates the memory address in the firmware to reference the new | |
195 | * target buffer. | |
196 | */ | |
197 | static void iwlagn_rx_queue_restock(struct iwl_priv *priv) | |
198 | { | |
199 | struct iwl_rx_queue *rxq = &priv->rxq; | |
200 | struct list_head *element; | |
201 | struct iwl_rx_mem_buffer *rxb; | |
202 | unsigned long flags; | |
203 | ||
204 | spin_lock_irqsave(&rxq->lock, flags); | |
205 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
206 | /* The overwritten rxb must be a used one */ | |
207 | rxb = rxq->queue[rxq->write]; | |
208 | BUG_ON(rxb && rxb->page); | |
209 | ||
210 | /* Get next free Rx buffer, remove from free list */ | |
211 | element = rxq->rx_free.next; | |
212 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
213 | list_del(element); | |
214 | ||
215 | /* Point to Rx buffer via next RBD in circular buffer */ | |
216 | rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv, | |
217 | rxb->page_dma); | |
218 | rxq->queue[rxq->write] = rxb; | |
219 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
220 | rxq->free_count--; | |
221 | } | |
222 | spin_unlock_irqrestore(&rxq->lock, flags); | |
223 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
224 | * refill it */ | |
225 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
226 | queue_work(priv->workqueue, &priv->rx_replenish); | |
227 | ||
228 | ||
229 | /* If we've added more space for the firmware to place data, tell it. | |
230 | * Increment device's write pointer in multiples of 8. */ | |
231 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
232 | spin_lock_irqsave(&rxq->lock, flags); | |
233 | rxq->need_update = 1; | |
234 | spin_unlock_irqrestore(&rxq->lock, flags); | |
235 | iwl_rx_queue_update_write_ptr(priv, rxq); | |
236 | } | |
237 | } | |
238 | ||
239 | /** | |
240 | * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free | |
241 | * | |
242 | * When moving to rx_free an SKB is allocated for the slot. | |
243 | * | |
244 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
245 | * This is called as a scheduled work item (except for during initialization) | |
246 | */ | |
247 | static void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority) | |
248 | { | |
249 | struct iwl_rx_queue *rxq = &priv->rxq; | |
250 | struct list_head *element; | |
251 | struct iwl_rx_mem_buffer *rxb; | |
252 | struct page *page; | |
253 | unsigned long flags; | |
254 | gfp_t gfp_mask = priority; | |
255 | ||
256 | while (1) { | |
257 | spin_lock_irqsave(&rxq->lock, flags); | |
258 | if (list_empty(&rxq->rx_used)) { | |
259 | spin_unlock_irqrestore(&rxq->lock, flags); | |
260 | return; | |
261 | } | |
262 | spin_unlock_irqrestore(&rxq->lock, flags); | |
263 | ||
264 | if (rxq->free_count > RX_LOW_WATERMARK) | |
265 | gfp_mask |= __GFP_NOWARN; | |
266 | ||
267 | if (priv->hw_params.rx_page_order > 0) | |
268 | gfp_mask |= __GFP_COMP; | |
269 | ||
270 | /* Alloc a new receive buffer */ | |
271 | page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order); | |
272 | if (!page) { | |
273 | if (net_ratelimit()) | |
274 | IWL_DEBUG_INFO(priv, "alloc_pages failed, " | |
275 | "order: %d\n", | |
276 | priv->hw_params.rx_page_order); | |
277 | ||
278 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
279 | net_ratelimit()) | |
280 | IWL_CRIT(priv, "Failed to alloc_pages with %s." | |
281 | "Only %u free buffers remaining.\n", | |
282 | priority == GFP_ATOMIC ? | |
283 | "GFP_ATOMIC" : "GFP_KERNEL", | |
284 | rxq->free_count); | |
285 | /* We don't reschedule replenish work here -- we will | |
286 | * call the restock method and if it still needs | |
287 | * more buffers it will schedule replenish */ | |
288 | return; | |
289 | } | |
290 | ||
291 | spin_lock_irqsave(&rxq->lock, flags); | |
292 | ||
293 | if (list_empty(&rxq->rx_used)) { | |
294 | spin_unlock_irqrestore(&rxq->lock, flags); | |
295 | __free_pages(page, priv->hw_params.rx_page_order); | |
296 | return; | |
297 | } | |
298 | element = rxq->rx_used.next; | |
299 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
300 | list_del(element); | |
301 | ||
302 | spin_unlock_irqrestore(&rxq->lock, flags); | |
303 | ||
304 | BUG_ON(rxb->page); | |
305 | rxb->page = page; | |
306 | /* Get physical address of the RB */ | |
307 | rxb->page_dma = dma_map_page(priv->bus.dev, page, 0, | |
308 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
309 | DMA_FROM_DEVICE); | |
310 | /* dma address must be no more than 36 bits */ | |
311 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); | |
312 | /* and also 256 byte aligned! */ | |
313 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); | |
314 | ||
315 | spin_lock_irqsave(&rxq->lock, flags); | |
316 | ||
317 | list_add_tail(&rxb->list, &rxq->rx_free); | |
318 | rxq->free_count++; | |
319 | ||
320 | spin_unlock_irqrestore(&rxq->lock, flags); | |
321 | } | |
322 | } | |
323 | ||
324 | void iwlagn_rx_replenish(struct iwl_priv *priv) | |
325 | { | |
326 | unsigned long flags; | |
327 | ||
328 | iwlagn_rx_allocate(priv, GFP_KERNEL); | |
329 | ||
330 | spin_lock_irqsave(&priv->lock, flags); | |
331 | iwlagn_rx_queue_restock(priv); | |
332 | spin_unlock_irqrestore(&priv->lock, flags); | |
333 | } | |
334 | ||
335 | static void iwlagn_rx_replenish_now(struct iwl_priv *priv) | |
336 | { | |
337 | iwlagn_rx_allocate(priv, GFP_ATOMIC); | |
338 | ||
339 | iwlagn_rx_queue_restock(priv); | |
340 | } | |
341 | ||
342 | void iwl_bg_rx_replenish(struct work_struct *data) | |
343 | { | |
344 | struct iwl_priv *priv = | |
345 | container_of(data, struct iwl_priv, rx_replenish); | |
346 | ||
347 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
348 | return; | |
349 | ||
350 | mutex_lock(&priv->mutex); | |
351 | iwlagn_rx_replenish(priv); | |
352 | mutex_unlock(&priv->mutex); | |
353 | } | |
354 | ||
355 | /** | |
356 | * iwl_rx_handle - Main entry function for receiving responses from uCode | |
357 | * | |
358 | * Uses the priv->rx_handlers callback function array to invoke | |
359 | * the appropriate handlers, including command responses, | |
360 | * frame-received notifications, and other notifications. | |
361 | */ | |
362 | static void iwl_rx_handle(struct iwl_priv *priv) | |
363 | { | |
364 | struct iwl_rx_mem_buffer *rxb; | |
365 | struct iwl_rx_packet *pkt; | |
366 | struct iwl_rx_queue *rxq = &priv->rxq; | |
367 | u32 r, i; | |
368 | int reclaim; | |
369 | unsigned long flags; | |
370 | u8 fill_rx = 0; | |
371 | u32 count = 8; | |
372 | int total_empty; | |
373 | ||
374 | /* uCode's read index (stored in shared DRAM) indicates the last Rx | |
375 | * buffer that the driver may process (last buffer filled by ucode). */ | |
376 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; | |
377 | i = rxq->read; | |
378 | ||
379 | /* Rx interrupt, but nothing sent from uCode */ | |
380 | if (i == r) | |
381 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); | |
382 | ||
383 | /* calculate total frames need to be restock after handling RX */ | |
384 | total_empty = r - rxq->write_actual; | |
385 | if (total_empty < 0) | |
386 | total_empty += RX_QUEUE_SIZE; | |
387 | ||
388 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
389 | fill_rx = 1; | |
390 | ||
391 | while (i != r) { | |
392 | int len; | |
393 | ||
394 | rxb = rxq->queue[i]; | |
395 | ||
396 | /* If an RXB doesn't have a Rx queue slot associated with it, | |
397 | * then a bug has been introduced in the queue refilling | |
398 | * routines -- catch it here */ | |
399 | if (WARN_ON(rxb == NULL)) { | |
400 | i = (i + 1) & RX_QUEUE_MASK; | |
401 | continue; | |
402 | } | |
403 | ||
404 | rxq->queue[i] = NULL; | |
405 | ||
406 | dma_unmap_page(priv->bus.dev, rxb->page_dma, | |
407 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
408 | DMA_FROM_DEVICE); | |
409 | pkt = rxb_addr(rxb); | |
410 | ||
411 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, | |
412 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
413 | ||
414 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
415 | len += sizeof(u32); /* account for status word */ | |
416 | trace_iwlwifi_dev_rx(priv, pkt, len); | |
417 | ||
418 | /* Reclaim a command buffer only if this packet is a response | |
419 | * to a (driver-originated) command. | |
420 | * If the packet (e.g. Rx frame) originated from uCode, | |
421 | * there is no command buffer to reclaim. | |
422 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
423 | * but apparently a few don't get set; catch them here. */ | |
424 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
425 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
426 | (pkt->hdr.cmd != REPLY_RX) && | |
427 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && | |
428 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && | |
429 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
430 | (pkt->hdr.cmd != REPLY_TX); | |
431 | ||
432 | iwl_rx_dispatch(priv, rxb); | |
433 | ||
434 | /* | |
435 | * XXX: After here, we should always check rxb->page | |
436 | * against NULL before touching it or its virtual | |
437 | * memory (pkt). Because some rx_handler might have | |
438 | * already taken or freed the pages. | |
439 | */ | |
440 | ||
441 | if (reclaim) { | |
442 | /* Invoke any callbacks, transfer the buffer to caller, | |
443 | * and fire off the (possibly) blocking | |
444 | * trans_send_cmd() | |
445 | * as we reclaim the driver command queue */ | |
446 | if (rxb->page) | |
447 | iwl_tx_cmd_complete(priv, rxb); | |
448 | else | |
449 | IWL_WARN(priv, "Claim null rxb?\n"); | |
450 | } | |
451 | ||
452 | /* Reuse the page if possible. For notification packets and | |
453 | * SKBs that fail to Rx correctly, add them back into the | |
454 | * rx_free list for reuse later. */ | |
455 | spin_lock_irqsave(&rxq->lock, flags); | |
456 | if (rxb->page != NULL) { | |
457 | rxb->page_dma = dma_map_page(priv->bus.dev, rxb->page, | |
458 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
459 | DMA_FROM_DEVICE); | |
460 | list_add_tail(&rxb->list, &rxq->rx_free); | |
461 | rxq->free_count++; | |
462 | } else | |
463 | list_add_tail(&rxb->list, &rxq->rx_used); | |
464 | ||
465 | spin_unlock_irqrestore(&rxq->lock, flags); | |
466 | ||
467 | i = (i + 1) & RX_QUEUE_MASK; | |
468 | /* If there are a lot of unused frames, | |
469 | * restock the Rx queue so ucode wont assert. */ | |
470 | if (fill_rx) { | |
471 | count++; | |
472 | if (count >= 8) { | |
473 | rxq->read = i; | |
474 | iwlagn_rx_replenish_now(priv); | |
475 | count = 0; | |
476 | } | |
477 | } | |
478 | } | |
479 | ||
480 | /* Backtrack one entry */ | |
481 | rxq->read = i; | |
482 | if (fill_rx) | |
483 | iwlagn_rx_replenish_now(priv); | |
484 | else | |
485 | iwlagn_rx_queue_restock(priv); | |
486 | } | |
487 | ||
488 | /* tasklet for iwlagn interrupt */ | |
489 | void iwl_irq_tasklet(struct iwl_priv *priv) | |
490 | { | |
491 | u32 inta = 0; | |
492 | u32 handled = 0; | |
493 | unsigned long flags; | |
494 | u32 i; | |
495 | #ifdef CONFIG_IWLWIFI_DEBUG | |
496 | u32 inta_mask; | |
497 | #endif | |
498 | ||
499 | spin_lock_irqsave(&priv->lock, flags); | |
500 | ||
501 | /* Ack/clear/reset pending uCode interrupts. | |
502 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
503 | */ | |
504 | /* There is a hardware bug in the interrupt mask function that some | |
505 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
506 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
507 | * ICT interrupt handling mechanism has another bug that might cause | |
508 | * these unmasked interrupts fail to be detected. We workaround the | |
509 | * hardware bugs here by ACKing all the possible interrupts so that | |
510 | * interrupt coalescing can still be achieved. | |
511 | */ | |
512 | iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask); | |
513 | ||
514 | inta = priv->_agn.inta; | |
515 | ||
516 | #ifdef CONFIG_IWLWIFI_DEBUG | |
517 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { | |
518 | /* just for debug */ | |
519 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
520 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
521 | inta, inta_mask); | |
522 | } | |
523 | #endif | |
524 | ||
525 | spin_unlock_irqrestore(&priv->lock, flags); | |
526 | ||
527 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ | |
528 | priv->_agn.inta = 0; | |
529 | ||
530 | /* Now service all interrupt bits discovered above. */ | |
531 | if (inta & CSR_INT_BIT_HW_ERR) { | |
532 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); | |
533 | ||
534 | /* Tell the device to stop sending interrupts */ | |
535 | iwl_disable_interrupts(priv); | |
536 | ||
537 | priv->isr_stats.hw++; | |
538 | iwl_irq_handle_error(priv); | |
539 | ||
540 | handled |= CSR_INT_BIT_HW_ERR; | |
541 | ||
542 | return; | |
543 | } | |
544 | ||
545 | #ifdef CONFIG_IWLWIFI_DEBUG | |
546 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { | |
547 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ | |
548 | if (inta & CSR_INT_BIT_SCD) { | |
549 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
550 | "the frame/frames.\n"); | |
551 | priv->isr_stats.sch++; | |
552 | } | |
553 | ||
554 | /* Alive notification via Rx interrupt will do the real work */ | |
555 | if (inta & CSR_INT_BIT_ALIVE) { | |
556 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
557 | priv->isr_stats.alive++; | |
558 | } | |
559 | } | |
560 | #endif | |
561 | /* Safely ignore these bits for debug checks below */ | |
562 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
563 | ||
564 | /* HW RF KILL switch toggled */ | |
565 | if (inta & CSR_INT_BIT_RF_KILL) { | |
566 | int hw_rf_kill = 0; | |
567 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
568 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
569 | hw_rf_kill = 1; | |
570 | ||
571 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", | |
572 | hw_rf_kill ? "disable radio" : "enable radio"); | |
573 | ||
574 | priv->isr_stats.rfkill++; | |
575 | ||
576 | /* driver only loads ucode once setting the interface up. | |
577 | * the driver allows loading the ucode even if the radio | |
578 | * is killed. Hence update the killswitch state here. The | |
579 | * rfkill handler will care about restarting if needed. | |
580 | */ | |
581 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
582 | if (hw_rf_kill) | |
583 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
584 | else | |
585 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
586 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); | |
587 | } | |
588 | ||
589 | handled |= CSR_INT_BIT_RF_KILL; | |
590 | } | |
591 | ||
592 | /* Chip got too hot and stopped itself */ | |
593 | if (inta & CSR_INT_BIT_CT_KILL) { | |
594 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
595 | priv->isr_stats.ctkill++; | |
596 | handled |= CSR_INT_BIT_CT_KILL; | |
597 | } | |
598 | ||
599 | /* Error detected by uCode */ | |
600 | if (inta & CSR_INT_BIT_SW_ERR) { | |
601 | IWL_ERR(priv, "Microcode SW error detected. " | |
602 | " Restarting 0x%X.\n", inta); | |
603 | priv->isr_stats.sw++; | |
604 | iwl_irq_handle_error(priv); | |
605 | handled |= CSR_INT_BIT_SW_ERR; | |
606 | } | |
607 | ||
608 | /* uCode wakes up after power-down sleep */ | |
609 | if (inta & CSR_INT_BIT_WAKEUP) { | |
610 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
611 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
612 | for (i = 0; i < priv->hw_params.max_txq_num; i++) | |
613 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
614 | ||
615 | priv->isr_stats.wakeup++; | |
616 | ||
617 | handled |= CSR_INT_BIT_WAKEUP; | |
618 | } | |
619 | ||
620 | /* All uCode command responses, including Tx command responses, | |
621 | * Rx "responses" (frame-received notification), and other | |
622 | * notifications from uCode come through here*/ | |
623 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | | |
624 | CSR_INT_BIT_RX_PERIODIC)) { | |
625 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); | |
626 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
627 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
628 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
629 | CSR_FH_INT_RX_MASK); | |
630 | } | |
631 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
632 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
633 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
634 | } | |
635 | /* Sending RX interrupt require many steps to be done in the | |
636 | * the device: | |
637 | * 1- write interrupt to current index in ICT table. | |
638 | * 2- dma RX frame. | |
639 | * 3- update RX shared data to indicate last write index. | |
640 | * 4- send interrupt. | |
641 | * This could lead to RX race, driver could receive RX interrupt | |
642 | * but the shared data changes does not reflect this; | |
643 | * periodic interrupt will detect any dangling Rx activity. | |
644 | */ | |
645 | ||
646 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
647 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
648 | CSR_INT_PERIODIC_DIS); | |
649 | iwl_rx_handle(priv); | |
650 | ||
651 | /* | |
652 | * Enable periodic interrupt in 8 msec only if we received | |
653 | * real RX interrupt (instead of just periodic int), to catch | |
654 | * any dangling Rx interrupt. If it was just the periodic | |
655 | * interrupt, there was no dangling Rx activity, and no need | |
656 | * to extend the periodic interrupt; one-shot is enough. | |
657 | */ | |
658 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
659 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
660 | CSR_INT_PERIODIC_ENA); | |
661 | ||
662 | priv->isr_stats.rx++; | |
663 | } | |
664 | ||
665 | /* This "Tx" DMA channel is used only for loading uCode */ | |
666 | if (inta & CSR_INT_BIT_FH_TX) { | |
667 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); | |
668 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); | |
669 | priv->isr_stats.tx++; | |
670 | handled |= CSR_INT_BIT_FH_TX; | |
671 | /* Wake up uCode load routine, now that load is complete */ | |
672 | priv->ucode_write_complete = 1; | |
673 | wake_up_interruptible(&priv->wait_command_queue); | |
674 | } | |
675 | ||
676 | if (inta & ~handled) { | |
677 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
678 | priv->isr_stats.unhandled++; | |
679 | } | |
680 | ||
681 | if (inta & ~(priv->inta_mask)) { | |
682 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", | |
683 | inta & ~priv->inta_mask); | |
684 | } | |
685 | ||
686 | /* Re-enable all interrupts */ | |
687 | /* only Re-enable if disabled by irq */ | |
688 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
689 | iwl_enable_interrupts(priv); | |
690 | /* Re-enable RF_KILL if it occurred */ | |
691 | else if (handled & CSR_INT_BIT_RF_KILL) | |
692 | iwl_enable_rfkill_int(priv); | |
693 | } | |
694 |