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ab697a9f EG |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
ab697a9f EG |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | #include <linux/sched.h> | |
30 | #include <linux/wait.h> | |
1a361cd8 | 31 | #include <linux/gfp.h> |
ab697a9f | 32 | |
522376d2 | 33 | /*TODO: Remove include to iwl-core.h*/ |
ab697a9f EG |
34 | #include "iwl-core.h" |
35 | #include "iwl-io.h" | |
c17d0681 | 36 | #include "iwl-trans-pcie-int.h" |
db70f290 | 37 | #include "iwl-op-mode.h" |
ab697a9f | 38 | |
a5916977 GG |
39 | #ifdef CONFIG_IWLWIFI_IDI |
40 | #include "iwl-amfh.h" | |
41 | #endif | |
42 | ||
ab697a9f EG |
43 | /****************************************************************************** |
44 | * | |
45 | * RX path functions | |
46 | * | |
47 | ******************************************************************************/ | |
48 | ||
49 | /* | |
50 | * Rx theory of operation | |
51 | * | |
52 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
53 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
54 | * used not only for Rx frames, but for any command response or notification | |
55 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
56 | * of indexes into the circular buffer. | |
57 | * | |
58 | * Rx Queue Indexes | |
59 | * The host/firmware share two index registers for managing the Rx buffers. | |
60 | * | |
61 | * The READ index maps to the first position that the firmware may be writing | |
62 | * to -- the driver can read up to (but not including) this position and get | |
63 | * good data. | |
64 | * The READ index is managed by the firmware once the card is enabled. | |
65 | * | |
66 | * The WRITE index maps to the last position the driver has read from -- the | |
67 | * position preceding WRITE is the last slot the firmware can place a packet. | |
68 | * | |
69 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
70 | * WRITE = READ. | |
71 | * | |
72 | * During initialization, the host sets up the READ queue position to the first | |
73 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
74 | * | |
75 | * When the firmware places a packet in a buffer, it will advance the READ index | |
76 | * and fire the RX interrupt. The driver can then query the READ index and | |
77 | * process as many packets as possible, moving the WRITE index forward as it | |
78 | * resets the Rx queue buffers with new memory. | |
79 | * | |
80 | * The management in the driver is as follows: | |
81 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
82 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
83 | * to replenish the iwl->rxq->rx_free. | |
84 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
85 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
86 | * 'processed' and 'read' driver indexes as well) | |
87 | * + A received packet is processed and handed to the kernel network stack, | |
88 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
89 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
90 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
91 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
92 | * were enough free buffers and RX_STALLED is set it is cleared. | |
93 | * | |
94 | * | |
95 | * Driver sequence: | |
96 | * | |
97 | * iwl_rx_queue_alloc() Allocates rx_free | |
98 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
99 | * iwl_rx_queue_restock | |
100 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
101 | * queue, updates firmware pointers, and updates | |
102 | * the WRITE index. If insufficient rx_free buffers | |
103 | * are available, schedules iwl_rx_replenish | |
104 | * | |
105 | * -- enable interrupts -- | |
106 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
107 | * READ INDEX, detaching the SKB from the pool. | |
108 | * Moves the packet buffer from queue to rx_used. | |
109 | * Calls iwl_rx_queue_restock to refill any empty | |
110 | * slots. | |
111 | * ... | |
112 | * | |
113 | */ | |
114 | ||
115 | /** | |
116 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
117 | */ | |
118 | static int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
119 | { | |
120 | int s = q->read - q->write; | |
121 | if (s <= 0) | |
122 | s += RX_QUEUE_SIZE; | |
123 | /* keep some buffer to not confuse full and empty queue */ | |
124 | s -= 2; | |
125 | if (s < 0) | |
126 | s = 0; | |
127 | return s; | |
128 | } | |
129 | ||
130 | /** | |
131 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
132 | */ | |
5a878bf6 | 133 | void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, |
ab697a9f EG |
134 | struct iwl_rx_queue *q) |
135 | { | |
136 | unsigned long flags; | |
137 | u32 reg; | |
138 | ||
139 | spin_lock_irqsave(&q->lock, flags); | |
140 | ||
141 | if (q->need_update == 0) | |
142 | goto exit_unlock; | |
143 | ||
fd656935 | 144 | if (hw_params(trans).shadow_reg_enable) { |
ab697a9f EG |
145 | /* shadow register enabled */ |
146 | /* Device expects a multiple of 8 */ | |
147 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 148 | iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual); |
ab697a9f EG |
149 | } else { |
150 | /* If power-saving is in use, make sure device is awake */ | |
5a878bf6 | 151 | if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { |
1042db2a | 152 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
ab697a9f EG |
153 | |
154 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
5a878bf6 | 155 | IWL_DEBUG_INFO(trans, |
ab697a9f EG |
156 | "Rx queue requesting wakeup," |
157 | " GP1 = 0x%x\n", reg); | |
1042db2a | 158 | iwl_set_bit(trans, CSR_GP_CNTRL, |
ab697a9f EG |
159 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
160 | goto exit_unlock; | |
161 | } | |
162 | ||
163 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 164 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR, |
ab697a9f EG |
165 | q->write_actual); |
166 | ||
167 | /* Else device is assumed to be awake */ | |
168 | } else { | |
169 | /* Device expects a multiple of 8 */ | |
170 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 171 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR, |
ab697a9f EG |
172 | q->write_actual); |
173 | } | |
174 | } | |
175 | q->need_update = 0; | |
176 | ||
177 | exit_unlock: | |
178 | spin_unlock_irqrestore(&q->lock, flags); | |
179 | } | |
180 | ||
181 | /** | |
182 | * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
183 | */ | |
5a878bf6 | 184 | static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr) |
ab697a9f EG |
185 | { |
186 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
187 | } | |
188 | ||
189 | /** | |
190 | * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool | |
191 | * | |
192 | * If there are slots in the RX queue that need to be restocked, | |
193 | * and we have free pre-allocated buffers, fill the ranks as much | |
194 | * as we can, pulling from rx_free. | |
195 | * | |
196 | * This moves the 'write' index forward to catch up with 'processed', and | |
197 | * also updates the memory address in the firmware to reference the new | |
198 | * target buffer. | |
199 | */ | |
5a878bf6 | 200 | static void iwlagn_rx_queue_restock(struct iwl_trans *trans) |
ab697a9f | 201 | { |
5a878bf6 EG |
202 | struct iwl_trans_pcie *trans_pcie = |
203 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
204 | ||
205 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
ab697a9f EG |
206 | struct list_head *element; |
207 | struct iwl_rx_mem_buffer *rxb; | |
208 | unsigned long flags; | |
209 | ||
210 | spin_lock_irqsave(&rxq->lock, flags); | |
211 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
212 | /* The overwritten rxb must be a used one */ | |
213 | rxb = rxq->queue[rxq->write]; | |
214 | BUG_ON(rxb && rxb->page); | |
215 | ||
216 | /* Get next free Rx buffer, remove from free list */ | |
217 | element = rxq->rx_free.next; | |
218 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
219 | list_del(element); | |
220 | ||
221 | /* Point to Rx buffer via next RBD in circular buffer */ | |
5a878bf6 | 222 | rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma); |
ab697a9f EG |
223 | rxq->queue[rxq->write] = rxb; |
224 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
225 | rxq->free_count--; | |
226 | } | |
227 | spin_unlock_irqrestore(&rxq->lock, flags); | |
228 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
229 | * refill it */ | |
230 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1ee158d8 | 231 | schedule_work(&trans_pcie->rx_replenish); |
ab697a9f EG |
232 | |
233 | ||
234 | /* If we've added more space for the firmware to place data, tell it. | |
235 | * Increment device's write pointer in multiples of 8. */ | |
236 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
237 | spin_lock_irqsave(&rxq->lock, flags); | |
238 | rxq->need_update = 1; | |
239 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5a878bf6 | 240 | iwl_rx_queue_update_write_ptr(trans, rxq); |
ab697a9f EG |
241 | } |
242 | } | |
243 | ||
244 | /** | |
245 | * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free | |
246 | * | |
247 | * When moving to rx_free an SKB is allocated for the slot. | |
248 | * | |
249 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
250 | * This is called as a scheduled work item (except for during initialization) | |
251 | */ | |
5a878bf6 | 252 | static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority) |
ab697a9f | 253 | { |
5a878bf6 EG |
254 | struct iwl_trans_pcie *trans_pcie = |
255 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
256 | ||
257 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
ab697a9f EG |
258 | struct list_head *element; |
259 | struct iwl_rx_mem_buffer *rxb; | |
260 | struct page *page; | |
261 | unsigned long flags; | |
262 | gfp_t gfp_mask = priority; | |
263 | ||
264 | while (1) { | |
265 | spin_lock_irqsave(&rxq->lock, flags); | |
266 | if (list_empty(&rxq->rx_used)) { | |
267 | spin_unlock_irqrestore(&rxq->lock, flags); | |
268 | return; | |
269 | } | |
270 | spin_unlock_irqrestore(&rxq->lock, flags); | |
271 | ||
272 | if (rxq->free_count > RX_LOW_WATERMARK) | |
273 | gfp_mask |= __GFP_NOWARN; | |
274 | ||
5a878bf6 | 275 | if (hw_params(trans).rx_page_order > 0) |
ab697a9f EG |
276 | gfp_mask |= __GFP_COMP; |
277 | ||
278 | /* Alloc a new receive buffer */ | |
d6189124 | 279 | page = alloc_pages(gfp_mask, |
5a878bf6 | 280 | hw_params(trans).rx_page_order); |
ab697a9f EG |
281 | if (!page) { |
282 | if (net_ratelimit()) | |
5a878bf6 | 283 | IWL_DEBUG_INFO(trans, "alloc_pages failed, " |
d6189124 | 284 | "order: %d\n", |
5a878bf6 | 285 | hw_params(trans).rx_page_order); |
ab697a9f EG |
286 | |
287 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
288 | net_ratelimit()) | |
5a878bf6 | 289 | IWL_CRIT(trans, "Failed to alloc_pages with %s." |
ab697a9f EG |
290 | "Only %u free buffers remaining.\n", |
291 | priority == GFP_ATOMIC ? | |
292 | "GFP_ATOMIC" : "GFP_KERNEL", | |
293 | rxq->free_count); | |
294 | /* We don't reschedule replenish work here -- we will | |
295 | * call the restock method and if it still needs | |
296 | * more buffers it will schedule replenish */ | |
297 | return; | |
298 | } | |
299 | ||
300 | spin_lock_irqsave(&rxq->lock, flags); | |
301 | ||
302 | if (list_empty(&rxq->rx_used)) { | |
303 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5a878bf6 | 304 | __free_pages(page, hw_params(trans).rx_page_order); |
ab697a9f EG |
305 | return; |
306 | } | |
307 | element = rxq->rx_used.next; | |
308 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
309 | list_del(element); | |
310 | ||
311 | spin_unlock_irqrestore(&rxq->lock, flags); | |
312 | ||
313 | BUG_ON(rxb->page); | |
314 | rxb->page = page; | |
315 | /* Get physical address of the RB */ | |
1042db2a | 316 | rxb->page_dma = dma_map_page(trans->dev, page, 0, |
5a878bf6 | 317 | PAGE_SIZE << hw_params(trans).rx_page_order, |
ab697a9f EG |
318 | DMA_FROM_DEVICE); |
319 | /* dma address must be no more than 36 bits */ | |
320 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); | |
321 | /* and also 256 byte aligned! */ | |
322 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); | |
323 | ||
324 | spin_lock_irqsave(&rxq->lock, flags); | |
325 | ||
326 | list_add_tail(&rxb->list, &rxq->rx_free); | |
327 | rxq->free_count++; | |
328 | ||
329 | spin_unlock_irqrestore(&rxq->lock, flags); | |
330 | } | |
331 | } | |
332 | ||
5a878bf6 | 333 | void iwlagn_rx_replenish(struct iwl_trans *trans) |
ab697a9f | 334 | { |
7b11488f | 335 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ab697a9f EG |
336 | unsigned long flags; |
337 | ||
5a878bf6 | 338 | iwlagn_rx_allocate(trans, GFP_KERNEL); |
ab697a9f | 339 | |
7b11488f | 340 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
5a878bf6 | 341 | iwlagn_rx_queue_restock(trans); |
7b11488f | 342 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
ab697a9f EG |
343 | } |
344 | ||
5a878bf6 | 345 | static void iwlagn_rx_replenish_now(struct iwl_trans *trans) |
ab697a9f | 346 | { |
5a878bf6 | 347 | iwlagn_rx_allocate(trans, GFP_ATOMIC); |
ab697a9f | 348 | |
5a878bf6 | 349 | iwlagn_rx_queue_restock(trans); |
ab697a9f EG |
350 | } |
351 | ||
352 | void iwl_bg_rx_replenish(struct work_struct *data) | |
353 | { | |
5a878bf6 EG |
354 | struct iwl_trans_pcie *trans_pcie = |
355 | container_of(data, struct iwl_trans_pcie, rx_replenish); | |
ab697a9f | 356 | |
1ee158d8 | 357 | iwlagn_rx_replenish(trans_pcie->trans); |
ab697a9f EG |
358 | } |
359 | ||
df2f3216 JB |
360 | static void iwl_rx_handle_rxbuf(struct iwl_trans *trans, |
361 | struct iwl_rx_mem_buffer *rxb) | |
362 | { | |
363 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
364 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
365 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; | |
366 | struct iwl_device_cmd *cmd; | |
367 | unsigned long flags; | |
368 | int len, err; | |
369 | u16 sequence; | |
370 | struct iwl_rx_cmd_buffer rxcb; | |
371 | struct iwl_rx_packet *pkt; | |
372 | bool reclaim; | |
373 | int index, cmd_index; | |
374 | ||
375 | if (WARN_ON(!rxb)) | |
376 | return; | |
377 | ||
378 | dma_unmap_page(trans->dev, rxb->page_dma, | |
379 | PAGE_SIZE << hw_params(trans).rx_page_order, | |
380 | DMA_FROM_DEVICE); | |
381 | ||
382 | rxcb._page = rxb->page; | |
383 | pkt = rxb_addr(&rxcb); | |
384 | ||
385 | IWL_DEBUG_RX(trans, "%s, 0x%02x\n", | |
386 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
387 | ||
388 | ||
389 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
390 | len += sizeof(u32); /* account for status word */ | |
391 | trace_iwlwifi_dev_rx(priv(trans), pkt, len); | |
392 | ||
393 | /* Reclaim a command buffer only if this packet is a response | |
394 | * to a (driver-originated) command. | |
395 | * If the packet (e.g. Rx frame) originated from uCode, | |
396 | * there is no command buffer to reclaim. | |
397 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
398 | * but apparently a few don't get set; catch them here. */ | |
399 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
400 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
401 | (pkt->hdr.cmd != REPLY_RX) && | |
402 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && | |
403 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && | |
404 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
405 | (pkt->hdr.cmd != REPLY_TX); | |
406 | ||
407 | sequence = le16_to_cpu(pkt->hdr.sequence); | |
408 | index = SEQ_TO_INDEX(sequence); | |
409 | cmd_index = get_cmd_index(&txq->q, index); | |
410 | ||
411 | if (reclaim) | |
412 | cmd = txq->cmd[cmd_index]; | |
413 | else | |
414 | cmd = NULL; | |
415 | ||
416 | /* warn if this is cmd response / notification and the uCode | |
417 | * didn't set the SEQ_RX_FRAME for a frame that is | |
418 | * uCode-originated | |
419 | * If you saw this code after the second half of 2012, then | |
420 | * please remove it | |
421 | */ | |
422 | WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false && | |
423 | (!(pkt->hdr.sequence & SEQ_RX_FRAME)), | |
424 | "reclaim is false, SEQ_RX_FRAME unset: %s\n", | |
425 | get_cmd_string(pkt->hdr.cmd)); | |
426 | ||
427 | err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd); | |
428 | ||
429 | /* | |
430 | * XXX: After here, we should always check rxcb._page | |
431 | * against NULL before touching it or its virtual | |
432 | * memory (pkt). Because some rx_handler might have | |
433 | * already taken or freed the pages. | |
434 | */ | |
435 | ||
436 | if (reclaim) { | |
437 | /* Invoke any callbacks, transfer the buffer to caller, | |
438 | * and fire off the (possibly) blocking | |
439 | * iwl_trans_send_cmd() | |
440 | * as we reclaim the driver command queue */ | |
441 | if (rxcb._page) | |
442 | iwl_tx_cmd_complete(trans, &rxcb, err); | |
443 | else | |
444 | IWL_WARN(trans, "Claim null rxb?\n"); | |
445 | } | |
446 | ||
447 | /* page was stolen from us */ | |
448 | if (rxcb._page == NULL) | |
449 | rxb->page = NULL; | |
450 | ||
451 | /* Reuse the page if possible. For notification packets and | |
452 | * SKBs that fail to Rx correctly, add them back into the | |
453 | * rx_free list for reuse later. */ | |
454 | spin_lock_irqsave(&rxq->lock, flags); | |
455 | if (rxb->page != NULL) { | |
456 | rxb->page_dma = | |
457 | dma_map_page(trans->dev, rxb->page, 0, | |
458 | PAGE_SIZE << hw_params(trans).rx_page_order, | |
459 | DMA_FROM_DEVICE); | |
460 | list_add_tail(&rxb->list, &rxq->rx_free); | |
461 | rxq->free_count++; | |
462 | } else | |
463 | list_add_tail(&rxb->list, &rxq->rx_used); | |
464 | spin_unlock_irqrestore(&rxq->lock, flags); | |
465 | } | |
466 | ||
ab697a9f EG |
467 | /** |
468 | * iwl_rx_handle - Main entry function for receiving responses from uCode | |
469 | * | |
470 | * Uses the priv->rx_handlers callback function array to invoke | |
471 | * the appropriate handlers, including command responses, | |
472 | * frame-received notifications, and other notifications. | |
473 | */ | |
5a878bf6 | 474 | static void iwl_rx_handle(struct iwl_trans *trans) |
ab697a9f | 475 | { |
df2f3216 | 476 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5a878bf6 | 477 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
ab697a9f | 478 | u32 r, i; |
ab697a9f EG |
479 | u8 fill_rx = 0; |
480 | u32 count = 8; | |
481 | int total_empty; | |
482 | ||
483 | /* uCode's read index (stored in shared DRAM) indicates the last Rx | |
484 | * buffer that the driver may process (last buffer filled by ucode). */ | |
485 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; | |
486 | i = rxq->read; | |
487 | ||
488 | /* Rx interrupt, but nothing sent from uCode */ | |
489 | if (i == r) | |
5a878bf6 | 490 | IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i); |
ab697a9f EG |
491 | |
492 | /* calculate total frames need to be restock after handling RX */ | |
493 | total_empty = r - rxq->write_actual; | |
494 | if (total_empty < 0) | |
495 | total_empty += RX_QUEUE_SIZE; | |
496 | ||
497 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
498 | fill_rx = 1; | |
499 | ||
500 | while (i != r) { | |
48a2d66f | 501 | struct iwl_rx_mem_buffer *rxb; |
ab697a9f EG |
502 | |
503 | rxb = rxq->queue[i]; | |
ab697a9f EG |
504 | rxq->queue[i] = NULL; |
505 | ||
df2f3216 | 506 | IWL_DEBUG_RX(trans, "rxbuf: r = %d, i = %d (%p)\n", rxb); |
ab697a9f | 507 | |
df2f3216 | 508 | iwl_rx_handle_rxbuf(trans, rxb); |
ab697a9f EG |
509 | |
510 | i = (i + 1) & RX_QUEUE_MASK; | |
511 | /* If there are a lot of unused frames, | |
512 | * restock the Rx queue so ucode wont assert. */ | |
513 | if (fill_rx) { | |
514 | count++; | |
515 | if (count >= 8) { | |
516 | rxq->read = i; | |
5a878bf6 | 517 | iwlagn_rx_replenish_now(trans); |
ab697a9f EG |
518 | count = 0; |
519 | } | |
520 | } | |
521 | } | |
522 | ||
523 | /* Backtrack one entry */ | |
524 | rxq->read = i; | |
525 | if (fill_rx) | |
5a878bf6 | 526 | iwlagn_rx_replenish_now(trans); |
ab697a9f | 527 | else |
5a878bf6 | 528 | iwlagn_rx_queue_restock(trans); |
ab697a9f EG |
529 | } |
530 | ||
7ff94706 EG |
531 | static const char * const desc_lookup_text[] = { |
532 | "OK", | |
533 | "FAIL", | |
534 | "BAD_PARAM", | |
535 | "BAD_CHECKSUM", | |
536 | "NMI_INTERRUPT_WDG", | |
537 | "SYSASSERT", | |
538 | "FATAL_ERROR", | |
539 | "BAD_COMMAND", | |
540 | "HW_ERROR_TUNE_LOCK", | |
541 | "HW_ERROR_TEMPERATURE", | |
542 | "ILLEGAL_CHAN_FREQ", | |
543 | "VCC_NOT_STABLE", | |
544 | "FH_ERROR", | |
545 | "NMI_INTERRUPT_HOST", | |
546 | "NMI_INTERRUPT_ACTION_PT", | |
547 | "NMI_INTERRUPT_UNKNOWN", | |
548 | "UCODE_VERSION_MISMATCH", | |
549 | "HW_ERROR_ABS_LOCK", | |
550 | "HW_ERROR_CAL_LOCK_FAIL", | |
551 | "NMI_INTERRUPT_INST_ACTION_PT", | |
552 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
553 | "NMI_TRM_HW_ER", | |
554 | "NMI_INTERRUPT_TRM", | |
555 | "NMI_INTERRUPT_BREAK_POINT", | |
556 | "DEBUG_0", | |
557 | "DEBUG_1", | |
558 | "DEBUG_2", | |
559 | "DEBUG_3", | |
560 | }; | |
561 | ||
562 | static struct { char *name; u8 num; } advanced_lookup[] = { | |
563 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
564 | { "SYSASSERT", 0x35 }, | |
565 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
566 | { "BAD_COMMAND", 0x38 }, | |
567 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
568 | { "FATAL_ERROR", 0x3D }, | |
569 | { "NMI_TRM_HW_ERR", 0x46 }, | |
570 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
571 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
572 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
573 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
574 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
575 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
576 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
577 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
578 | { "ADVANCED_SYSASSERT", 0 }, | |
579 | }; | |
580 | ||
581 | static const char *desc_lookup(u32 num) | |
582 | { | |
583 | int i; | |
584 | int max = ARRAY_SIZE(desc_lookup_text); | |
585 | ||
586 | if (num < max) | |
587 | return desc_lookup_text[num]; | |
588 | ||
589 | max = ARRAY_SIZE(advanced_lookup) - 1; | |
590 | for (i = 0; i < max; i++) { | |
591 | if (advanced_lookup[i].num == num) | |
592 | break; | |
593 | } | |
594 | return advanced_lookup[i].name; | |
595 | } | |
596 | ||
597 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
598 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
599 | ||
6bb78847 | 600 | static void iwl_dump_nic_error_log(struct iwl_trans *trans) |
7ff94706 EG |
601 | { |
602 | u32 base; | |
603 | struct iwl_error_event_table table; | |
1f7b6172 EG |
604 | struct iwl_trans_pcie *trans_pcie = |
605 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
7ff94706 | 606 | |
ae6130fc | 607 | base = trans->shrd->device_pointers.error_event_table; |
3d6acefc | 608 | if (trans->shrd->ucode_type == IWL_UCODE_INIT) { |
7ff94706 | 609 | if (!base) |
0692fe41 | 610 | base = trans->shrd->fw->init_errlog_ptr; |
7ff94706 EG |
611 | } else { |
612 | if (!base) | |
0692fe41 | 613 | base = trans->shrd->fw->inst_errlog_ptr; |
7ff94706 EG |
614 | } |
615 | ||
616 | if (!iwlagn_hw_valid_rtc_data_addr(base)) { | |
6bb78847 | 617 | IWL_ERR(trans, |
7ff94706 EG |
618 | "Not valid error log pointer 0x%08X for %s uCode\n", |
619 | base, | |
3d6acefc | 620 | (trans->shrd->ucode_type == IWL_UCODE_INIT) |
7ff94706 EG |
621 | ? "Init" : "RT"); |
622 | return; | |
623 | } | |
624 | ||
8655112d | 625 | iwl_read_targ_mem_words(trans, base, &table, sizeof(table)); |
7ff94706 EG |
626 | |
627 | if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { | |
6bb78847 EG |
628 | IWL_ERR(trans, "Start IWL Error Log Dump:\n"); |
629 | IWL_ERR(trans, "Status: 0x%08lX, count: %d\n", | |
630 | trans->shrd->status, table.valid); | |
7ff94706 EG |
631 | } |
632 | ||
1f7b6172 | 633 | trans_pcie->isr_stats.err_code = table.error_id; |
7ff94706 | 634 | |
0692fe41 | 635 | trace_iwlwifi_dev_ucode_error(priv(trans), table.error_id, table.tsf_low, |
7ff94706 EG |
636 | table.data1, table.data2, table.line, |
637 | table.blink1, table.blink2, table.ilink1, | |
638 | table.ilink2, table.bcon_time, table.gp1, | |
639 | table.gp2, table.gp3, table.ucode_ver, | |
640 | table.hw_ver, table.brd_ver); | |
6bb78847 | 641 | IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id, |
7ff94706 | 642 | desc_lookup(table.error_id)); |
6bb78847 EG |
643 | IWL_ERR(trans, "0x%08X | uPc\n", table.pc); |
644 | IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1); | |
645 | IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2); | |
646 | IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1); | |
647 | IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2); | |
648 | IWL_ERR(trans, "0x%08X | data1\n", table.data1); | |
649 | IWL_ERR(trans, "0x%08X | data2\n", table.data2); | |
650 | IWL_ERR(trans, "0x%08X | line\n", table.line); | |
651 | IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time); | |
652 | IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low); | |
653 | IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi); | |
654 | IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1); | |
655 | IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2); | |
656 | IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3); | |
657 | IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver); | |
658 | IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver); | |
659 | IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver); | |
660 | IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd); | |
d332f591 WYG |
661 | |
662 | IWL_ERR(trans, "0x%08X | isr0\n", table.isr0); | |
663 | IWL_ERR(trans, "0x%08X | isr1\n", table.isr1); | |
664 | IWL_ERR(trans, "0x%08X | isr2\n", table.isr2); | |
665 | IWL_ERR(trans, "0x%08X | isr3\n", table.isr3); | |
666 | IWL_ERR(trans, "0x%08X | isr4\n", table.isr4); | |
667 | IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref); | |
668 | IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event); | |
669 | IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control); | |
670 | IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration); | |
671 | IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid); | |
672 | IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match); | |
673 | IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel); | |
674 | IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp); | |
675 | IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler); | |
7ff94706 EG |
676 | } |
677 | ||
678 | /** | |
679 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | |
680 | */ | |
6bb78847 | 681 | static void iwl_irq_handle_error(struct iwl_trans *trans) |
7ff94706 EG |
682 | { |
683 | /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ | |
ff6e75cb | 684 | if (cfg(trans)->internal_wimax_coex && |
1042db2a | 685 | (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & |
7ff94706 | 686 | APMS_CLK_VAL_MRB_FUNC_MODE) || |
1042db2a | 687 | (iwl_read_prph(trans, APMG_PS_CTRL_REG) & |
7ff94706 EG |
688 | APMG_PS_CTRL_VAL_RESET_REQ))) { |
689 | /* | |
690 | * Keep the restart process from trying to send host | |
691 | * commands by clearing the ready bit. | |
692 | */ | |
6bb78847 EG |
693 | clear_bit(STATUS_READY, &trans->shrd->status); |
694 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); | |
ff6e75cb | 695 | wake_up(&trans->shrd->wait_command_queue); |
6bb78847 | 696 | IWL_ERR(trans, "RF is used by WiMAX\n"); |
7ff94706 EG |
697 | return; |
698 | } | |
699 | ||
6bb78847 | 700 | IWL_ERR(trans, "Loaded firmware version: %s\n", |
0692fe41 | 701 | trans->shrd->fw->fw_version); |
7ff94706 | 702 | |
6bb78847 EG |
703 | iwl_dump_nic_error_log(trans); |
704 | iwl_dump_csr(trans); | |
705 | iwl_dump_fh(trans, NULL, false); | |
706 | iwl_dump_nic_event_log(trans, false, NULL, false); | |
7ff94706 | 707 | |
bcb9321c | 708 | iwl_op_mode_nic_error(trans->op_mode); |
7ff94706 EG |
709 | } |
710 | ||
711 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
712 | ||
713 | /** | |
714 | * iwl_print_event_log - Dump error event log to syslog | |
715 | * | |
716 | */ | |
6bb78847 | 717 | static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx, |
7ff94706 EG |
718 | u32 num_events, u32 mode, |
719 | int pos, char **buf, size_t bufsz) | |
720 | { | |
721 | u32 i; | |
722 | u32 base; /* SRAM byte address of event log header */ | |
723 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
724 | u32 ptr; /* SRAM byte address of log data */ | |
725 | u32 ev, time, data; /* event log data */ | |
726 | unsigned long reg_flags; | |
727 | ||
728 | if (num_events == 0) | |
729 | return pos; | |
730 | ||
ae6130fc | 731 | base = trans->shrd->device_pointers.log_event_table; |
3d6acefc | 732 | if (trans->shrd->ucode_type == IWL_UCODE_INIT) { |
7ff94706 | 733 | if (!base) |
0692fe41 | 734 | base = trans->shrd->fw->init_evtlog_ptr; |
7ff94706 EG |
735 | } else { |
736 | if (!base) | |
0692fe41 | 737 | base = trans->shrd->fw->inst_evtlog_ptr; |
7ff94706 EG |
738 | } |
739 | ||
740 | if (mode == 0) | |
741 | event_size = 2 * sizeof(u32); | |
742 | else | |
743 | event_size = 3 * sizeof(u32); | |
744 | ||
745 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
746 | ||
747 | /* Make sure device is powered up for SRAM reads */ | |
1042db2a EG |
748 | spin_lock_irqsave(&trans->reg_lock, reg_flags); |
749 | iwl_grab_nic_access(trans); | |
7ff94706 EG |
750 | |
751 | /* Set starting address; reads will auto-increment */ | |
1042db2a | 752 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr); |
7ff94706 EG |
753 | rmb(); |
754 | ||
755 | /* "time" is actually "data" for mode 0 (no timestamp). | |
756 | * place event id # at far right for easier visual parsing. */ | |
757 | for (i = 0; i < num_events; i++) { | |
1042db2a EG |
758 | ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT); |
759 | time = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
7ff94706 EG |
760 | if (mode == 0) { |
761 | /* data, ev */ | |
762 | if (bufsz) { | |
763 | pos += scnprintf(*buf + pos, bufsz - pos, | |
764 | "EVT_LOG:0x%08x:%04u\n", | |
765 | time, ev); | |
766 | } else { | |
8655112d | 767 | trace_iwlwifi_dev_ucode_event(priv(trans), 0, |
7ff94706 | 768 | time, ev); |
6bb78847 | 769 | IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n", |
7ff94706 EG |
770 | time, ev); |
771 | } | |
772 | } else { | |
1042db2a | 773 | data = iwl_read32(trans, HBUS_TARG_MEM_RDAT); |
7ff94706 EG |
774 | if (bufsz) { |
775 | pos += scnprintf(*buf + pos, bufsz - pos, | |
776 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
777 | time, data, ev); | |
778 | } else { | |
6bb78847 | 779 | IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n", |
7ff94706 | 780 | time, data, ev); |
8655112d | 781 | trace_iwlwifi_dev_ucode_event(priv(trans), time, |
7ff94706 EG |
782 | data, ev); |
783 | } | |
784 | } | |
785 | } | |
786 | ||
787 | /* Allow device to power down */ | |
1042db2a EG |
788 | iwl_release_nic_access(trans); |
789 | spin_unlock_irqrestore(&trans->reg_lock, reg_flags); | |
7ff94706 EG |
790 | return pos; |
791 | } | |
792 | ||
793 | /** | |
794 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
795 | */ | |
6bb78847 | 796 | static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity, |
7ff94706 EG |
797 | u32 num_wraps, u32 next_entry, |
798 | u32 size, u32 mode, | |
799 | int pos, char **buf, size_t bufsz) | |
800 | { | |
801 | /* | |
802 | * display the newest DEFAULT_LOG_ENTRIES entries | |
803 | * i.e the entries just before the next ont that uCode would fill. | |
804 | */ | |
805 | if (num_wraps) { | |
806 | if (next_entry < size) { | |
6bb78847 | 807 | pos = iwl_print_event_log(trans, |
7ff94706 EG |
808 | capacity - (size - next_entry), |
809 | size - next_entry, mode, | |
810 | pos, buf, bufsz); | |
6bb78847 | 811 | pos = iwl_print_event_log(trans, 0, |
7ff94706 EG |
812 | next_entry, mode, |
813 | pos, buf, bufsz); | |
814 | } else | |
6bb78847 | 815 | pos = iwl_print_event_log(trans, next_entry - size, |
7ff94706 EG |
816 | size, mode, pos, buf, bufsz); |
817 | } else { | |
818 | if (next_entry < size) { | |
6bb78847 | 819 | pos = iwl_print_event_log(trans, 0, next_entry, |
7ff94706 EG |
820 | mode, pos, buf, bufsz); |
821 | } else { | |
6bb78847 | 822 | pos = iwl_print_event_log(trans, next_entry - size, |
7ff94706 EG |
823 | size, mode, pos, buf, bufsz); |
824 | } | |
825 | } | |
826 | return pos; | |
827 | } | |
828 | ||
829 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) | |
830 | ||
6bb78847 | 831 | int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log, |
7ff94706 EG |
832 | char **buf, bool display) |
833 | { | |
834 | u32 base; /* SRAM byte address of event log header */ | |
835 | u32 capacity; /* event log capacity in # entries */ | |
836 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
837 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
838 | u32 next_entry; /* index of next entry to be written by uCode */ | |
839 | u32 size; /* # entries that we'll print */ | |
840 | u32 logsize; | |
841 | int pos = 0; | |
842 | size_t bufsz = 0; | |
843 | ||
ae6130fc | 844 | base = trans->shrd->device_pointers.log_event_table; |
3d6acefc | 845 | if (trans->shrd->ucode_type == IWL_UCODE_INIT) { |
0692fe41 | 846 | logsize = trans->shrd->fw->init_evtlog_size; |
7ff94706 | 847 | if (!base) |
0692fe41 | 848 | base = trans->shrd->fw->init_evtlog_ptr; |
7ff94706 | 849 | } else { |
0692fe41 | 850 | logsize = trans->shrd->fw->inst_evtlog_size; |
7ff94706 | 851 | if (!base) |
0692fe41 | 852 | base = trans->shrd->fw->inst_evtlog_ptr; |
7ff94706 EG |
853 | } |
854 | ||
855 | if (!iwlagn_hw_valid_rtc_data_addr(base)) { | |
6bb78847 | 856 | IWL_ERR(trans, |
7ff94706 EG |
857 | "Invalid event log pointer 0x%08X for %s uCode\n", |
858 | base, | |
3d6acefc | 859 | (trans->shrd->ucode_type == IWL_UCODE_INIT) |
7ff94706 EG |
860 | ? "Init" : "RT"); |
861 | return -EINVAL; | |
862 | } | |
863 | ||
864 | /* event log header */ | |
1042db2a EG |
865 | capacity = iwl_read_targ_mem(trans, base); |
866 | mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32))); | |
867 | num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32))); | |
868 | next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32))); | |
7ff94706 EG |
869 | |
870 | if (capacity > logsize) { | |
6bb78847 EG |
871 | IWL_ERR(trans, "Log capacity %d is bogus, limit to %d " |
872 | "entries\n", capacity, logsize); | |
7ff94706 EG |
873 | capacity = logsize; |
874 | } | |
875 | ||
876 | if (next_entry > logsize) { | |
6bb78847 | 877 | IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n", |
7ff94706 EG |
878 | next_entry, logsize); |
879 | next_entry = logsize; | |
880 | } | |
881 | ||
882 | size = num_wraps ? capacity : next_entry; | |
883 | ||
884 | /* bail out if nothing in log */ | |
885 | if (size == 0) { | |
6bb78847 | 886 | IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n"); |
7ff94706 EG |
887 | return pos; |
888 | } | |
889 | ||
7ff94706 | 890 | #ifdef CONFIG_IWLWIFI_DEBUG |
a8bceb39 | 891 | if (!(iwl_have_debug_level(IWL_DL_FW_ERRORS)) && !full_log) |
7ff94706 EG |
892 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
893 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
894 | #else | |
895 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
896 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
897 | #endif | |
6bb78847 | 898 | IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n", |
7ff94706 EG |
899 | size); |
900 | ||
901 | #ifdef CONFIG_IWLWIFI_DEBUG | |
902 | if (display) { | |
903 | if (full_log) | |
904 | bufsz = capacity * 48; | |
905 | else | |
906 | bufsz = size * 48; | |
907 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
908 | if (!*buf) | |
909 | return -ENOMEM; | |
910 | } | |
a8bceb39 | 911 | if (iwl_have_debug_level(IWL_DL_FW_ERRORS) || full_log) { |
7ff94706 EG |
912 | /* |
913 | * if uCode has wrapped back to top of log, | |
914 | * start at the oldest entry, | |
915 | * i.e the next one that uCode would fill. | |
916 | */ | |
917 | if (num_wraps) | |
6bb78847 | 918 | pos = iwl_print_event_log(trans, next_entry, |
7ff94706 EG |
919 | capacity - next_entry, mode, |
920 | pos, buf, bufsz); | |
921 | /* (then/else) start at top of log */ | |
6bb78847 | 922 | pos = iwl_print_event_log(trans, 0, |
7ff94706 EG |
923 | next_entry, mode, pos, buf, bufsz); |
924 | } else | |
6bb78847 | 925 | pos = iwl_print_last_event_logs(trans, capacity, num_wraps, |
7ff94706 EG |
926 | next_entry, size, mode, |
927 | pos, buf, bufsz); | |
928 | #else | |
6bb78847 | 929 | pos = iwl_print_last_event_logs(trans, capacity, num_wraps, |
7ff94706 EG |
930 | next_entry, size, mode, |
931 | pos, buf, bufsz); | |
932 | #endif | |
933 | return pos; | |
934 | } | |
935 | ||
ab697a9f | 936 | /* tasklet for iwlagn interrupt */ |
0c325769 | 937 | void iwl_irq_tasklet(struct iwl_trans *trans) |
ab697a9f EG |
938 | { |
939 | u32 inta = 0; | |
940 | u32 handled = 0; | |
941 | unsigned long flags; | |
942 | u32 i; | |
943 | #ifdef CONFIG_IWLWIFI_DEBUG | |
944 | u32 inta_mask; | |
945 | #endif | |
946 | ||
3e10caeb | 947 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
948 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
949 | ||
0c325769 | 950 | |
7b11488f | 951 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
ab697a9f EG |
952 | |
953 | /* Ack/clear/reset pending uCode interrupts. | |
954 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
955 | */ | |
956 | /* There is a hardware bug in the interrupt mask function that some | |
957 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
958 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
959 | * ICT interrupt handling mechanism has another bug that might cause | |
960 | * these unmasked interrupts fail to be detected. We workaround the | |
961 | * hardware bugs here by ACKing all the possible interrupts so that | |
962 | * interrupt coalescing can still be achieved. | |
963 | */ | |
1042db2a | 964 | iwl_write32(trans, CSR_INT, |
0c325769 | 965 | trans_pcie->inta | ~trans_pcie->inta_mask); |
ab697a9f | 966 | |
0c325769 | 967 | inta = trans_pcie->inta; |
ab697a9f EG |
968 | |
969 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 970 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
ab697a9f | 971 | /* just for debug */ |
1042db2a | 972 | inta_mask = iwl_read32(trans, CSR_INT_MASK); |
0c325769 | 973 | IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ", |
ab697a9f EG |
974 | inta, inta_mask); |
975 | } | |
976 | #endif | |
977 | ||
0c325769 EG |
978 | /* saved interrupt in inta variable now we can reset trans_pcie->inta */ |
979 | trans_pcie->inta = 0; | |
ab697a9f | 980 | |
7b11488f | 981 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
b49ba04a | 982 | |
ab697a9f EG |
983 | /* Now service all interrupt bits discovered above. */ |
984 | if (inta & CSR_INT_BIT_HW_ERR) { | |
0c325769 | 985 | IWL_ERR(trans, "Hardware error detected. Restarting.\n"); |
ab697a9f EG |
986 | |
987 | /* Tell the device to stop sending interrupts */ | |
0c325769 | 988 | iwl_disable_interrupts(trans); |
ab697a9f | 989 | |
1f7b6172 | 990 | isr_stats->hw++; |
6bb78847 | 991 | iwl_irq_handle_error(trans); |
ab697a9f EG |
992 | |
993 | handled |= CSR_INT_BIT_HW_ERR; | |
994 | ||
995 | return; | |
996 | } | |
997 | ||
998 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 999 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
ab697a9f EG |
1000 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1001 | if (inta & CSR_INT_BIT_SCD) { | |
0c325769 | 1002 | IWL_DEBUG_ISR(trans, "Scheduler finished to transmit " |
ab697a9f | 1003 | "the frame/frames.\n"); |
1f7b6172 | 1004 | isr_stats->sch++; |
ab697a9f EG |
1005 | } |
1006 | ||
1007 | /* Alive notification via Rx interrupt will do the real work */ | |
1008 | if (inta & CSR_INT_BIT_ALIVE) { | |
0c325769 | 1009 | IWL_DEBUG_ISR(trans, "Alive interrupt\n"); |
1f7b6172 | 1010 | isr_stats->alive++; |
ab697a9f EG |
1011 | } |
1012 | } | |
1013 | #endif | |
1014 | /* Safely ignore these bits for debug checks below */ | |
1015 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1016 | ||
1017 | /* HW RF KILL switch toggled */ | |
1018 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1019 | int hw_rf_kill = 0; | |
1042db2a | 1020 | if (!(iwl_read32(trans, CSR_GP_CNTRL) & |
ab697a9f EG |
1021 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1022 | hw_rf_kill = 1; | |
1023 | ||
0c325769 | 1024 | IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", |
ab697a9f EG |
1025 | hw_rf_kill ? "disable radio" : "enable radio"); |
1026 | ||
1f7b6172 | 1027 | isr_stats->rfkill++; |
ab697a9f EG |
1028 | |
1029 | /* driver only loads ucode once setting the interface up. | |
1030 | * the driver allows loading the ucode even if the radio | |
1031 | * is killed. Hence update the killswitch state here. The | |
1032 | * rfkill handler will care about restarting if needed. | |
1033 | */ | |
0c325769 | 1034 | if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) { |
ab697a9f | 1035 | if (hw_rf_kill) |
0c325769 EG |
1036 | set_bit(STATUS_RF_KILL_HW, |
1037 | &trans->shrd->status); | |
ab697a9f | 1038 | else |
63013ae3 | 1039 | clear_bit(STATUS_RF_KILL_HW, |
0c325769 | 1040 | &trans->shrd->status); |
7120d989 | 1041 | iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rf_kill); |
ab697a9f EG |
1042 | } |
1043 | ||
1044 | handled |= CSR_INT_BIT_RF_KILL; | |
1045 | } | |
1046 | ||
1047 | /* Chip got too hot and stopped itself */ | |
1048 | if (inta & CSR_INT_BIT_CT_KILL) { | |
0c325769 | 1049 | IWL_ERR(trans, "Microcode CT kill error detected.\n"); |
1f7b6172 | 1050 | isr_stats->ctkill++; |
ab697a9f EG |
1051 | handled |= CSR_INT_BIT_CT_KILL; |
1052 | } | |
1053 | ||
1054 | /* Error detected by uCode */ | |
1055 | if (inta & CSR_INT_BIT_SW_ERR) { | |
0c325769 | 1056 | IWL_ERR(trans, "Microcode SW error detected. " |
ab697a9f | 1057 | " Restarting 0x%X.\n", inta); |
1f7b6172 | 1058 | isr_stats->sw++; |
6bb78847 | 1059 | iwl_irq_handle_error(trans); |
ab697a9f EG |
1060 | handled |= CSR_INT_BIT_SW_ERR; |
1061 | } | |
1062 | ||
1063 | /* uCode wakes up after power-down sleep */ | |
1064 | if (inta & CSR_INT_BIT_WAKEUP) { | |
0c325769 EG |
1065 | IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); |
1066 | iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq); | |
1067 | for (i = 0; i < hw_params(trans).max_txq_num; i++) | |
fd656935 | 1068 | iwl_txq_update_write_ptr(trans, |
8ad71bef | 1069 | &trans_pcie->txq[i]); |
ab697a9f | 1070 | |
1f7b6172 | 1071 | isr_stats->wakeup++; |
ab697a9f EG |
1072 | |
1073 | handled |= CSR_INT_BIT_WAKEUP; | |
1074 | } | |
1075 | ||
1076 | /* All uCode command responses, including Tx command responses, | |
1077 | * Rx "responses" (frame-received notification), and other | |
1078 | * notifications from uCode come through here*/ | |
1079 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | | |
1080 | CSR_INT_BIT_RX_PERIODIC)) { | |
0c325769 | 1081 | IWL_DEBUG_ISR(trans, "Rx interrupt\n"); |
ab697a9f EG |
1082 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1083 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1042db2a | 1084 | iwl_write32(trans, CSR_FH_INT_STATUS, |
ab697a9f EG |
1085 | CSR_FH_INT_RX_MASK); |
1086 | } | |
1087 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1088 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1042db2a | 1089 | iwl_write32(trans, |
0c325769 | 1090 | CSR_INT, CSR_INT_BIT_RX_PERIODIC); |
ab697a9f EG |
1091 | } |
1092 | /* Sending RX interrupt require many steps to be done in the | |
1093 | * the device: | |
1094 | * 1- write interrupt to current index in ICT table. | |
1095 | * 2- dma RX frame. | |
1096 | * 3- update RX shared data to indicate last write index. | |
1097 | * 4- send interrupt. | |
1098 | * This could lead to RX race, driver could receive RX interrupt | |
1099 | * but the shared data changes does not reflect this; | |
1100 | * periodic interrupt will detect any dangling Rx activity. | |
1101 | */ | |
1102 | ||
1103 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1042db2a | 1104 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
ab697a9f | 1105 | CSR_INT_PERIODIC_DIS); |
a5916977 GG |
1106 | #ifdef CONFIG_IWLWIFI_IDI |
1107 | iwl_amfh_rx_handler(); | |
1108 | #else | |
0c325769 | 1109 | iwl_rx_handle(trans); |
a5916977 | 1110 | #endif |
ab697a9f EG |
1111 | /* |
1112 | * Enable periodic interrupt in 8 msec only if we received | |
1113 | * real RX interrupt (instead of just periodic int), to catch | |
1114 | * any dangling Rx interrupt. If it was just the periodic | |
1115 | * interrupt, there was no dangling Rx activity, and no need | |
1116 | * to extend the periodic interrupt; one-shot is enough. | |
1117 | */ | |
1118 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1042db2a | 1119 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
ab697a9f EG |
1120 | CSR_INT_PERIODIC_ENA); |
1121 | ||
1f7b6172 | 1122 | isr_stats->rx++; |
ab697a9f EG |
1123 | } |
1124 | ||
1125 | /* This "Tx" DMA channel is used only for loading uCode */ | |
1126 | if (inta & CSR_INT_BIT_FH_TX) { | |
1042db2a | 1127 | iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
0c325769 | 1128 | IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); |
1f7b6172 | 1129 | isr_stats->tx++; |
ab697a9f EG |
1130 | handled |= CSR_INT_BIT_FH_TX; |
1131 | /* Wake up uCode load routine, now that load is complete */ | |
5703ddb0 | 1132 | trans->ucode_write_complete = 1; |
effd4d9a | 1133 | wake_up(&trans->shrd->wait_command_queue); |
ab697a9f EG |
1134 | } |
1135 | ||
1136 | if (inta & ~handled) { | |
0c325769 | 1137 | IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
1f7b6172 | 1138 | isr_stats->unhandled++; |
ab697a9f EG |
1139 | } |
1140 | ||
0c325769 EG |
1141 | if (inta & ~(trans_pcie->inta_mask)) { |
1142 | IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", | |
1143 | inta & ~trans_pcie->inta_mask); | |
ab697a9f EG |
1144 | } |
1145 | ||
1146 | /* Re-enable all interrupts */ | |
1147 | /* only Re-enable if disabled by irq */ | |
0c325769 EG |
1148 | if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status)) |
1149 | iwl_enable_interrupts(trans); | |
ab697a9f | 1150 | /* Re-enable RF_KILL if it occurred */ |
1df06bdc EG |
1151 | else if (handled & CSR_INT_BIT_RF_KILL) { |
1152 | IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); | |
1153 | iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); | |
1154 | } | |
ab697a9f EG |
1155 | } |
1156 | ||
1a361cd8 EG |
1157 | /****************************************************************************** |
1158 | * | |
1159 | * ICT functions | |
1160 | * | |
1161 | ******************************************************************************/ | |
10667136 JB |
1162 | |
1163 | /* a device (PCI-E) page is 4096 bytes long */ | |
1164 | #define ICT_SHIFT 12 | |
1165 | #define ICT_SIZE (1 << ICT_SHIFT) | |
1166 | #define ICT_COUNT (ICT_SIZE / sizeof(u32)) | |
1a361cd8 EG |
1167 | |
1168 | /* Free dram table */ | |
0c325769 | 1169 | void iwl_free_isr_ict(struct iwl_trans *trans) |
1a361cd8 | 1170 | { |
0c325769 EG |
1171 | struct iwl_trans_pcie *trans_pcie = |
1172 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1173 | ||
10667136 | 1174 | if (trans_pcie->ict_tbl) { |
1042db2a | 1175 | dma_free_coherent(trans->dev, ICT_SIZE, |
10667136 | 1176 | trans_pcie->ict_tbl, |
0c325769 | 1177 | trans_pcie->ict_tbl_dma); |
10667136 JB |
1178 | trans_pcie->ict_tbl = NULL; |
1179 | trans_pcie->ict_tbl_dma = 0; | |
1a361cd8 EG |
1180 | } |
1181 | } | |
1182 | ||
1183 | ||
10667136 JB |
1184 | /* |
1185 | * allocate dram shared table, it is an aligned memory | |
1186 | * block of ICT_SIZE. | |
1a361cd8 EG |
1187 | * also reset all data related to ICT table interrupt. |
1188 | */ | |
0c325769 | 1189 | int iwl_alloc_isr_ict(struct iwl_trans *trans) |
1a361cd8 | 1190 | { |
0c325769 EG |
1191 | struct iwl_trans_pcie *trans_pcie = |
1192 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1a361cd8 | 1193 | |
10667136 | 1194 | trans_pcie->ict_tbl = |
1042db2a | 1195 | dma_alloc_coherent(trans->dev, ICT_SIZE, |
10667136 JB |
1196 | &trans_pcie->ict_tbl_dma, |
1197 | GFP_KERNEL); | |
1198 | if (!trans_pcie->ict_tbl) | |
1a361cd8 EG |
1199 | return -ENOMEM; |
1200 | ||
10667136 JB |
1201 | /* just an API sanity check ... it is guaranteed to be aligned */ |
1202 | if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { | |
1203 | iwl_free_isr_ict(trans); | |
1204 | return -EINVAL; | |
1205 | } | |
1a361cd8 | 1206 | |
10667136 JB |
1207 | IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n", |
1208 | (unsigned long long)trans_pcie->ict_tbl_dma); | |
1a361cd8 | 1209 | |
10667136 | 1210 | IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl); |
1a361cd8 EG |
1211 | |
1212 | /* reset table and index to all 0 */ | |
10667136 | 1213 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
0c325769 | 1214 | trans_pcie->ict_index = 0; |
1a361cd8 EG |
1215 | |
1216 | /* add periodic RX interrupt */ | |
0c325769 | 1217 | trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC; |
1a361cd8 EG |
1218 | return 0; |
1219 | } | |
1220 | ||
1221 | /* Device is going up inform it about using ICT interrupt table, | |
1222 | * also we need to tell the driver to start using ICT interrupt. | |
1223 | */ | |
ed6a3803 | 1224 | void iwl_reset_ict(struct iwl_trans *trans) |
1a361cd8 EG |
1225 | { |
1226 | u32 val; | |
1227 | unsigned long flags; | |
0c325769 EG |
1228 | struct iwl_trans_pcie *trans_pcie = |
1229 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1a361cd8 | 1230 | |
10667136 | 1231 | if (!trans_pcie->ict_tbl) |
ed6a3803 | 1232 | return; |
1a361cd8 | 1233 | |
7b11488f | 1234 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
0c325769 | 1235 | iwl_disable_interrupts(trans); |
1a361cd8 | 1236 | |
10667136 | 1237 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
1a361cd8 | 1238 | |
10667136 | 1239 | val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; |
1a361cd8 EG |
1240 | |
1241 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
1242 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
1243 | ||
10667136 | 1244 | IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); |
1a361cd8 | 1245 | |
1042db2a | 1246 | iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); |
0c325769 EG |
1247 | trans_pcie->use_ict = true; |
1248 | trans_pcie->ict_index = 0; | |
1042db2a | 1249 | iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); |
0c325769 | 1250 | iwl_enable_interrupts(trans); |
7b11488f | 1251 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1252 | } |
1253 | ||
1254 | /* Device is going down disable ict interrupt usage */ | |
0c325769 | 1255 | void iwl_disable_ict(struct iwl_trans *trans) |
1a361cd8 | 1256 | { |
0c325769 EG |
1257 | struct iwl_trans_pcie *trans_pcie = |
1258 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1259 | ||
1a361cd8 EG |
1260 | unsigned long flags; |
1261 | ||
7b11488f | 1262 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
0c325769 | 1263 | trans_pcie->use_ict = false; |
7b11488f | 1264 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1265 | } |
1266 | ||
1267 | static irqreturn_t iwl_isr(int irq, void *data) | |
1268 | { | |
0c325769 EG |
1269 | struct iwl_trans *trans = data; |
1270 | struct iwl_trans_pcie *trans_pcie; | |
1a361cd8 EG |
1271 | u32 inta, inta_mask; |
1272 | unsigned long flags; | |
1273 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1274 | u32 inta_fh; | |
1275 | #endif | |
0c325769 | 1276 | if (!trans) |
1a361cd8 EG |
1277 | return IRQ_NONE; |
1278 | ||
b80667ee JB |
1279 | trace_iwlwifi_dev_irq(priv(trans)); |
1280 | ||
0c325769 EG |
1281 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1282 | ||
7b11488f | 1283 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1284 | |
1285 | /* Disable (but don't clear!) interrupts here to avoid | |
1286 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1287 | * If we have something to service, the tasklet will re-enable ints. | |
1288 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
1042db2a EG |
1289 | inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */ |
1290 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1a361cd8 EG |
1291 | |
1292 | /* Discover which interrupts are active/pending */ | |
1042db2a | 1293 | inta = iwl_read32(trans, CSR_INT); |
1a361cd8 EG |
1294 | |
1295 | /* Ignore interrupt if there's nothing in NIC to service. | |
1296 | * This may be due to IRQ shared with another device, | |
1297 | * or due to sporadic interrupts thrown from our NIC. */ | |
1298 | if (!inta) { | |
0c325769 | 1299 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1a361cd8 EG |
1300 | goto none; |
1301 | } | |
1302 | ||
1303 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
1304 | /* Hardware disappeared. It might have already raised | |
1305 | * an interrupt */ | |
0c325769 | 1306 | IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); |
1a361cd8 EG |
1307 | goto unplugged; |
1308 | } | |
1309 | ||
1310 | #ifdef CONFIG_IWLWIFI_DEBUG | |
a8bceb39 | 1311 | if (iwl_have_debug_level(IWL_DL_ISR)) { |
1042db2a | 1312 | inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS); |
0c325769 | 1313 | IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, " |
1a361cd8 EG |
1314 | "fh 0x%08x\n", inta, inta_mask, inta_fh); |
1315 | } | |
1316 | #endif | |
1317 | ||
0c325769 | 1318 | trans_pcie->inta |= inta; |
1a361cd8 EG |
1319 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
1320 | if (likely(inta)) | |
0c325769 EG |
1321 | tasklet_schedule(&trans_pcie->irq_tasklet); |
1322 | else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) && | |
1323 | !trans_pcie->inta) | |
1324 | iwl_enable_interrupts(trans); | |
1a361cd8 EG |
1325 | |
1326 | unplugged: | |
7b11488f | 1327 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1328 | return IRQ_HANDLED; |
1329 | ||
1330 | none: | |
1331 | /* re-enable interrupts here since we don't have anything to service. */ | |
1332 | /* only Re-enable if disabled by irq and no schedules tasklet. */ | |
0c325769 EG |
1333 | if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) && |
1334 | !trans_pcie->inta) | |
1335 | iwl_enable_interrupts(trans); | |
1a361cd8 | 1336 | |
7b11488f | 1337 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1338 | return IRQ_NONE; |
1339 | } | |
1340 | ||
1341 | /* interrupt handler using ict table, with this interrupt driver will | |
1342 | * stop using INTA register to get device's interrupt, reading this register | |
1343 | * is expensive, device will write interrupts in ICT dram table, increment | |
1344 | * index then will fire interrupt to driver, driver will OR all ICT table | |
1345 | * entries from current index up to table entry with 0 value. the result is | |
1346 | * the interrupt we need to service, driver will set the entries back to 0 and | |
1347 | * set index. | |
1348 | */ | |
1349 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
1350 | { | |
0c325769 EG |
1351 | struct iwl_trans *trans = data; |
1352 | struct iwl_trans_pcie *trans_pcie; | |
1a361cd8 EG |
1353 | u32 inta, inta_mask; |
1354 | u32 val = 0; | |
b80667ee | 1355 | u32 read; |
1a361cd8 EG |
1356 | unsigned long flags; |
1357 | ||
0c325769 | 1358 | if (!trans) |
1a361cd8 EG |
1359 | return IRQ_NONE; |
1360 | ||
0c325769 EG |
1361 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1362 | ||
1a361cd8 EG |
1363 | /* dram interrupt table not set yet, |
1364 | * use legacy interrupt. | |
1365 | */ | |
0c325769 | 1366 | if (!trans_pcie->use_ict) |
1a361cd8 EG |
1367 | return iwl_isr(irq, data); |
1368 | ||
b80667ee JB |
1369 | trace_iwlwifi_dev_irq(priv(trans)); |
1370 | ||
7b11488f | 1371 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1372 | |
1373 | /* Disable (but don't clear!) interrupts here to avoid | |
1374 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1375 | * If we have something to service, the tasklet will re-enable ints. | |
1376 | * If we *don't* have something, we'll re-enable before leaving here. | |
1377 | */ | |
1042db2a EG |
1378 | inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */ |
1379 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1a361cd8 EG |
1380 | |
1381 | ||
1382 | /* Ignore interrupt if there's nothing in NIC to service. | |
1383 | * This may be due to IRQ shared with another device, | |
1384 | * or due to sporadic interrupts thrown from our NIC. */ | |
b80667ee JB |
1385 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); |
1386 | trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index, read); | |
1387 | if (!read) { | |
0c325769 | 1388 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1a361cd8 EG |
1389 | goto none; |
1390 | } | |
1391 | ||
b80667ee JB |
1392 | /* |
1393 | * Collect all entries up to the first 0, starting from ict_index; | |
1394 | * note we already read at ict_index. | |
1395 | */ | |
1396 | do { | |
1397 | val |= read; | |
0c325769 | 1398 | IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", |
b80667ee | 1399 | trans_pcie->ict_index, read); |
0c325769 EG |
1400 | trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; |
1401 | trans_pcie->ict_index = | |
1402 | iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT); | |
1a361cd8 | 1403 | |
b80667ee JB |
1404 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); |
1405 | trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index, | |
1406 | read); | |
1407 | } while (read); | |
1a361cd8 EG |
1408 | |
1409 | /* We should not get this value, just ignore it. */ | |
1410 | if (val == 0xffffffff) | |
1411 | val = 0; | |
1412 | ||
1413 | /* | |
1414 | * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit | |
1415 | * (bit 15 before shifting it to 31) to clear when using interrupt | |
1416 | * coalescing. fortunately, bits 18 and 19 stay set when this happens | |
1417 | * so we use them to decide on the real state of the Rx bit. | |
1418 | * In order words, bit 15 is set if bit 18 or bit 19 are set. | |
1419 | */ | |
1420 | if (val & 0xC0000) | |
1421 | val |= 0x8000; | |
1422 | ||
1423 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
0c325769 | 1424 | IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", |
1a361cd8 EG |
1425 | inta, inta_mask, val); |
1426 | ||
0c325769 EG |
1427 | inta &= trans_pcie->inta_mask; |
1428 | trans_pcie->inta |= inta; | |
1a361cd8 EG |
1429 | |
1430 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1431 | if (likely(inta)) | |
0c325769 EG |
1432 | tasklet_schedule(&trans_pcie->irq_tasklet); |
1433 | else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) && | |
b80667ee | 1434 | !trans_pcie->inta) { |
1a361cd8 EG |
1435 | /* Allow interrupt if was disabled by this handler and |
1436 | * no tasklet was schedules, We should not enable interrupt, | |
1437 | * tasklet will enable it. | |
1438 | */ | |
0c325769 | 1439 | iwl_enable_interrupts(trans); |
1a361cd8 EG |
1440 | } |
1441 | ||
7b11488f | 1442 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1443 | return IRQ_HANDLED; |
1444 | ||
1445 | none: | |
1446 | /* re-enable interrupts here since we don't have anything to service. | |
1447 | * only Re-enable if disabled by irq. | |
1448 | */ | |
0c325769 | 1449 | if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) && |
b80667ee | 1450 | !trans_pcie->inta) |
0c325769 | 1451 | iwl_enable_interrupts(trans); |
1a361cd8 | 1452 | |
7b11488f | 1453 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); |
1a361cd8 EG |
1454 | return IRQ_NONE; |
1455 | } |