Commit | Line | Data |
---|---|---|
ab697a9f EG |
1 | /****************************************************************************** |
2 | * | |
fb4961db | 3 | * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. |
ab697a9f EG |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | #include <linux/sched.h> | |
30 | #include <linux/wait.h> | |
1a361cd8 | 31 | #include <linux/gfp.h> |
ab697a9f | 32 | |
522376d2 | 33 | /*TODO: Remove include to iwl-core.h*/ |
ab697a9f EG |
34 | #include "iwl-core.h" |
35 | #include "iwl-io.h" | |
c17d0681 | 36 | #include "iwl-trans-pcie-int.h" |
ab697a9f | 37 | |
a5916977 GG |
38 | #ifdef CONFIG_IWLWIFI_IDI |
39 | #include "iwl-amfh.h" | |
40 | #endif | |
41 | ||
ab697a9f EG |
42 | /****************************************************************************** |
43 | * | |
44 | * RX path functions | |
45 | * | |
46 | ******************************************************************************/ | |
47 | ||
48 | /* | |
49 | * Rx theory of operation | |
50 | * | |
51 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
52 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
53 | * used not only for Rx frames, but for any command response or notification | |
54 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
55 | * of indexes into the circular buffer. | |
56 | * | |
57 | * Rx Queue Indexes | |
58 | * The host/firmware share two index registers for managing the Rx buffers. | |
59 | * | |
60 | * The READ index maps to the first position that the firmware may be writing | |
61 | * to -- the driver can read up to (but not including) this position and get | |
62 | * good data. | |
63 | * The READ index is managed by the firmware once the card is enabled. | |
64 | * | |
65 | * The WRITE index maps to the last position the driver has read from -- the | |
66 | * position preceding WRITE is the last slot the firmware can place a packet. | |
67 | * | |
68 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
69 | * WRITE = READ. | |
70 | * | |
71 | * During initialization, the host sets up the READ queue position to the first | |
72 | * INDEX position, and WRITE to the last (READ - 1 wrapped) | |
73 | * | |
74 | * When the firmware places a packet in a buffer, it will advance the READ index | |
75 | * and fire the RX interrupt. The driver can then query the READ index and | |
76 | * process as many packets as possible, moving the WRITE index forward as it | |
77 | * resets the Rx queue buffers with new memory. | |
78 | * | |
79 | * The management in the driver is as follows: | |
80 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
81 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
82 | * to replenish the iwl->rxq->rx_free. | |
83 | * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the | |
84 | * iwl->rxq is replenished and the READ INDEX is updated (updating the | |
85 | * 'processed' and 'read' driver indexes as well) | |
86 | * + A received packet is processed and handed to the kernel network stack, | |
87 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
88 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
89 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
90 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
91 | * were enough free buffers and RX_STALLED is set it is cleared. | |
92 | * | |
93 | * | |
94 | * Driver sequence: | |
95 | * | |
96 | * iwl_rx_queue_alloc() Allocates rx_free | |
97 | * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
98 | * iwl_rx_queue_restock | |
99 | * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx | |
100 | * queue, updates firmware pointers, and updates | |
101 | * the WRITE index. If insufficient rx_free buffers | |
102 | * are available, schedules iwl_rx_replenish | |
103 | * | |
104 | * -- enable interrupts -- | |
105 | * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the | |
106 | * READ INDEX, detaching the SKB from the pool. | |
107 | * Moves the packet buffer from queue to rx_used. | |
108 | * Calls iwl_rx_queue_restock to refill any empty | |
109 | * slots. | |
110 | * ... | |
111 | * | |
112 | */ | |
113 | ||
114 | /** | |
115 | * iwl_rx_queue_space - Return number of free slots available in queue. | |
116 | */ | |
117 | static int iwl_rx_queue_space(const struct iwl_rx_queue *q) | |
118 | { | |
119 | int s = q->read - q->write; | |
120 | if (s <= 0) | |
121 | s += RX_QUEUE_SIZE; | |
122 | /* keep some buffer to not confuse full and empty queue */ | |
123 | s -= 2; | |
124 | if (s < 0) | |
125 | s = 0; | |
126 | return s; | |
127 | } | |
128 | ||
129 | /** | |
130 | * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
131 | */ | |
5a878bf6 | 132 | void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, |
ab697a9f EG |
133 | struct iwl_rx_queue *q) |
134 | { | |
135 | unsigned long flags; | |
136 | u32 reg; | |
137 | ||
138 | spin_lock_irqsave(&q->lock, flags); | |
139 | ||
140 | if (q->need_update == 0) | |
141 | goto exit_unlock; | |
142 | ||
fd656935 | 143 | if (hw_params(trans).shadow_reg_enable) { |
ab697a9f EG |
144 | /* shadow register enabled */ |
145 | /* Device expects a multiple of 8 */ | |
146 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 147 | iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual); |
ab697a9f EG |
148 | } else { |
149 | /* If power-saving is in use, make sure device is awake */ | |
5a878bf6 | 150 | if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { |
1042db2a | 151 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
ab697a9f EG |
152 | |
153 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
5a878bf6 | 154 | IWL_DEBUG_INFO(trans, |
ab697a9f EG |
155 | "Rx queue requesting wakeup," |
156 | " GP1 = 0x%x\n", reg); | |
1042db2a | 157 | iwl_set_bit(trans, CSR_GP_CNTRL, |
ab697a9f EG |
158 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
159 | goto exit_unlock; | |
160 | } | |
161 | ||
162 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 163 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR, |
ab697a9f EG |
164 | q->write_actual); |
165 | ||
166 | /* Else device is assumed to be awake */ | |
167 | } else { | |
168 | /* Device expects a multiple of 8 */ | |
169 | q->write_actual = (q->write & ~0x7); | |
1042db2a | 170 | iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR, |
ab697a9f EG |
171 | q->write_actual); |
172 | } | |
173 | } | |
174 | q->need_update = 0; | |
175 | ||
176 | exit_unlock: | |
177 | spin_unlock_irqrestore(&q->lock, flags); | |
178 | } | |
179 | ||
180 | /** | |
181 | * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
182 | */ | |
5a878bf6 | 183 | static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr) |
ab697a9f EG |
184 | { |
185 | return cpu_to_le32((u32)(dma_addr >> 8)); | |
186 | } | |
187 | ||
188 | /** | |
189 | * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool | |
190 | * | |
191 | * If there are slots in the RX queue that need to be restocked, | |
192 | * and we have free pre-allocated buffers, fill the ranks as much | |
193 | * as we can, pulling from rx_free. | |
194 | * | |
195 | * This moves the 'write' index forward to catch up with 'processed', and | |
196 | * also updates the memory address in the firmware to reference the new | |
197 | * target buffer. | |
198 | */ | |
5a878bf6 | 199 | static void iwlagn_rx_queue_restock(struct iwl_trans *trans) |
ab697a9f | 200 | { |
5a878bf6 EG |
201 | struct iwl_trans_pcie *trans_pcie = |
202 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
203 | ||
204 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
ab697a9f EG |
205 | struct list_head *element; |
206 | struct iwl_rx_mem_buffer *rxb; | |
207 | unsigned long flags; | |
208 | ||
209 | spin_lock_irqsave(&rxq->lock, flags); | |
210 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { | |
211 | /* The overwritten rxb must be a used one */ | |
212 | rxb = rxq->queue[rxq->write]; | |
213 | BUG_ON(rxb && rxb->page); | |
214 | ||
215 | /* Get next free Rx buffer, remove from free list */ | |
216 | element = rxq->rx_free.next; | |
217 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
218 | list_del(element); | |
219 | ||
220 | /* Point to Rx buffer via next RBD in circular buffer */ | |
5a878bf6 | 221 | rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma); |
ab697a9f EG |
222 | rxq->queue[rxq->write] = rxb; |
223 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
224 | rxq->free_count--; | |
225 | } | |
226 | spin_unlock_irqrestore(&rxq->lock, flags); | |
227 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
228 | * refill it */ | |
229 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
5a878bf6 | 230 | queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish); |
ab697a9f EG |
231 | |
232 | ||
233 | /* If we've added more space for the firmware to place data, tell it. | |
234 | * Increment device's write pointer in multiples of 8. */ | |
235 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
236 | spin_lock_irqsave(&rxq->lock, flags); | |
237 | rxq->need_update = 1; | |
238 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5a878bf6 | 239 | iwl_rx_queue_update_write_ptr(trans, rxq); |
ab697a9f EG |
240 | } |
241 | } | |
242 | ||
243 | /** | |
244 | * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free | |
245 | * | |
246 | * When moving to rx_free an SKB is allocated for the slot. | |
247 | * | |
248 | * Also restock the Rx queue via iwl_rx_queue_restock. | |
249 | * This is called as a scheduled work item (except for during initialization) | |
250 | */ | |
5a878bf6 | 251 | static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority) |
ab697a9f | 252 | { |
5a878bf6 EG |
253 | struct iwl_trans_pcie *trans_pcie = |
254 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
255 | ||
256 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
ab697a9f EG |
257 | struct list_head *element; |
258 | struct iwl_rx_mem_buffer *rxb; | |
259 | struct page *page; | |
260 | unsigned long flags; | |
261 | gfp_t gfp_mask = priority; | |
262 | ||
263 | while (1) { | |
264 | spin_lock_irqsave(&rxq->lock, flags); | |
265 | if (list_empty(&rxq->rx_used)) { | |
266 | spin_unlock_irqrestore(&rxq->lock, flags); | |
267 | return; | |
268 | } | |
269 | spin_unlock_irqrestore(&rxq->lock, flags); | |
270 | ||
271 | if (rxq->free_count > RX_LOW_WATERMARK) | |
272 | gfp_mask |= __GFP_NOWARN; | |
273 | ||
5a878bf6 | 274 | if (hw_params(trans).rx_page_order > 0) |
ab697a9f EG |
275 | gfp_mask |= __GFP_COMP; |
276 | ||
277 | /* Alloc a new receive buffer */ | |
d6189124 | 278 | page = alloc_pages(gfp_mask, |
5a878bf6 | 279 | hw_params(trans).rx_page_order); |
ab697a9f EG |
280 | if (!page) { |
281 | if (net_ratelimit()) | |
5a878bf6 | 282 | IWL_DEBUG_INFO(trans, "alloc_pages failed, " |
d6189124 | 283 | "order: %d\n", |
5a878bf6 | 284 | hw_params(trans).rx_page_order); |
ab697a9f EG |
285 | |
286 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
287 | net_ratelimit()) | |
5a878bf6 | 288 | IWL_CRIT(trans, "Failed to alloc_pages with %s." |
ab697a9f EG |
289 | "Only %u free buffers remaining.\n", |
290 | priority == GFP_ATOMIC ? | |
291 | "GFP_ATOMIC" : "GFP_KERNEL", | |
292 | rxq->free_count); | |
293 | /* We don't reschedule replenish work here -- we will | |
294 | * call the restock method and if it still needs | |
295 | * more buffers it will schedule replenish */ | |
296 | return; | |
297 | } | |
298 | ||
299 | spin_lock_irqsave(&rxq->lock, flags); | |
300 | ||
301 | if (list_empty(&rxq->rx_used)) { | |
302 | spin_unlock_irqrestore(&rxq->lock, flags); | |
5a878bf6 | 303 | __free_pages(page, hw_params(trans).rx_page_order); |
ab697a9f EG |
304 | return; |
305 | } | |
306 | element = rxq->rx_used.next; | |
307 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
308 | list_del(element); | |
309 | ||
310 | spin_unlock_irqrestore(&rxq->lock, flags); | |
311 | ||
312 | BUG_ON(rxb->page); | |
313 | rxb->page = page; | |
314 | /* Get physical address of the RB */ | |
1042db2a | 315 | rxb->page_dma = dma_map_page(trans->dev, page, 0, |
5a878bf6 | 316 | PAGE_SIZE << hw_params(trans).rx_page_order, |
ab697a9f EG |
317 | DMA_FROM_DEVICE); |
318 | /* dma address must be no more than 36 bits */ | |
319 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); | |
320 | /* and also 256 byte aligned! */ | |
321 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); | |
322 | ||
323 | spin_lock_irqsave(&rxq->lock, flags); | |
324 | ||
325 | list_add_tail(&rxb->list, &rxq->rx_free); | |
326 | rxq->free_count++; | |
327 | ||
328 | spin_unlock_irqrestore(&rxq->lock, flags); | |
329 | } | |
330 | } | |
331 | ||
5a878bf6 | 332 | void iwlagn_rx_replenish(struct iwl_trans *trans) |
ab697a9f EG |
333 | { |
334 | unsigned long flags; | |
335 | ||
5a878bf6 | 336 | iwlagn_rx_allocate(trans, GFP_KERNEL); |
ab697a9f | 337 | |
5a878bf6 EG |
338 | spin_lock_irqsave(&trans->shrd->lock, flags); |
339 | iwlagn_rx_queue_restock(trans); | |
340 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
ab697a9f EG |
341 | } |
342 | ||
5a878bf6 | 343 | static void iwlagn_rx_replenish_now(struct iwl_trans *trans) |
ab697a9f | 344 | { |
5a878bf6 | 345 | iwlagn_rx_allocate(trans, GFP_ATOMIC); |
ab697a9f | 346 | |
5a878bf6 | 347 | iwlagn_rx_queue_restock(trans); |
ab697a9f EG |
348 | } |
349 | ||
350 | void iwl_bg_rx_replenish(struct work_struct *data) | |
351 | { | |
5a878bf6 EG |
352 | struct iwl_trans_pcie *trans_pcie = |
353 | container_of(data, struct iwl_trans_pcie, rx_replenish); | |
354 | struct iwl_trans *trans = trans_pcie->trans; | |
ab697a9f | 355 | |
5a878bf6 | 356 | if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status)) |
ab697a9f EG |
357 | return; |
358 | ||
5a878bf6 EG |
359 | mutex_lock(&trans->shrd->mutex); |
360 | iwlagn_rx_replenish(trans); | |
361 | mutex_unlock(&trans->shrd->mutex); | |
ab697a9f EG |
362 | } |
363 | ||
364 | /** | |
365 | * iwl_rx_handle - Main entry function for receiving responses from uCode | |
366 | * | |
367 | * Uses the priv->rx_handlers callback function array to invoke | |
368 | * the appropriate handlers, including command responses, | |
369 | * frame-received notifications, and other notifications. | |
370 | */ | |
5a878bf6 | 371 | static void iwl_rx_handle(struct iwl_trans *trans) |
ab697a9f EG |
372 | { |
373 | struct iwl_rx_mem_buffer *rxb; | |
374 | struct iwl_rx_packet *pkt; | |
5a878bf6 EG |
375 | struct iwl_trans_pcie *trans_pcie = |
376 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
377 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
247c61d6 EG |
378 | struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue]; |
379 | struct iwl_device_cmd *cmd; | |
ab697a9f EG |
380 | u32 r, i; |
381 | int reclaim; | |
382 | unsigned long flags; | |
383 | u8 fill_rx = 0; | |
384 | u32 count = 8; | |
385 | int total_empty; | |
247c61d6 | 386 | int index, cmd_index; |
ab697a9f EG |
387 | |
388 | /* uCode's read index (stored in shared DRAM) indicates the last Rx | |
389 | * buffer that the driver may process (last buffer filled by ucode). */ | |
390 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; | |
391 | i = rxq->read; | |
392 | ||
393 | /* Rx interrupt, but nothing sent from uCode */ | |
394 | if (i == r) | |
5a878bf6 | 395 | IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i); |
ab697a9f EG |
396 | |
397 | /* calculate total frames need to be restock after handling RX */ | |
398 | total_empty = r - rxq->write_actual; | |
399 | if (total_empty < 0) | |
400 | total_empty += RX_QUEUE_SIZE; | |
401 | ||
402 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
403 | fill_rx = 1; | |
404 | ||
405 | while (i != r) { | |
247c61d6 | 406 | int len, err; |
d56da920 | 407 | u16 sequence; |
ab697a9f EG |
408 | |
409 | rxb = rxq->queue[i]; | |
410 | ||
411 | /* If an RXB doesn't have a Rx queue slot associated with it, | |
412 | * then a bug has been introduced in the queue refilling | |
413 | * routines -- catch it here */ | |
414 | if (WARN_ON(rxb == NULL)) { | |
415 | i = (i + 1) & RX_QUEUE_MASK; | |
416 | continue; | |
417 | } | |
418 | ||
419 | rxq->queue[i] = NULL; | |
420 | ||
1042db2a | 421 | dma_unmap_page(trans->dev, rxb->page_dma, |
5a878bf6 | 422 | PAGE_SIZE << hw_params(trans).rx_page_order, |
ab697a9f EG |
423 | DMA_FROM_DEVICE); |
424 | pkt = rxb_addr(rxb); | |
425 | ||
5a878bf6 | 426 | IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r, |
ab697a9f EG |
427 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
428 | ||
429 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
430 | len += sizeof(u32); /* account for status word */ | |
5a878bf6 | 431 | trace_iwlwifi_dev_rx(priv(trans), pkt, len); |
ab697a9f EG |
432 | |
433 | /* Reclaim a command buffer only if this packet is a response | |
434 | * to a (driver-originated) command. | |
435 | * If the packet (e.g. Rx frame) originated from uCode, | |
436 | * there is no command buffer to reclaim. | |
437 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
438 | * but apparently a few don't get set; catch them here. */ | |
439 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
440 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
441 | (pkt->hdr.cmd != REPLY_RX) && | |
442 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && | |
443 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && | |
444 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
445 | (pkt->hdr.cmd != REPLY_TX); | |
446 | ||
17a68dd7 | 447 | sequence = le16_to_cpu(pkt->hdr.sequence); |
247c61d6 EG |
448 | index = SEQ_TO_INDEX(sequence); |
449 | cmd_index = get_cmd_index(&txq->q, index); | |
450 | ||
451 | if (reclaim) | |
452 | cmd = txq->cmd[cmd_index]; | |
453 | else | |
454 | cmd = NULL; | |
17a68dd7 EG |
455 | |
456 | /* warn if this is cmd response / notification and the uCode | |
457 | * didn't set the SEQ_RX_FRAME for a frame that is | |
d56da920 EG |
458 | * uCode-originated |
459 | * If you saw this code after the second half of 2012, then | |
460 | * please remove it | |
461 | */ | |
462 | WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false && | |
17a68dd7 EG |
463 | (!(pkt->hdr.sequence & SEQ_RX_FRAME)), |
464 | "reclaim is false, SEQ_RX_FRAME unset: %s\n", | |
465 | get_cmd_string(pkt->hdr.cmd)); | |
466 | ||
247c61d6 | 467 | err = iwl_rx_dispatch(priv(trans), rxb, cmd); |
ab697a9f EG |
468 | |
469 | /* | |
470 | * XXX: After here, we should always check rxb->page | |
471 | * against NULL before touching it or its virtual | |
472 | * memory (pkt). Because some rx_handler might have | |
473 | * already taken or freed the pages. | |
474 | */ | |
475 | ||
476 | if (reclaim) { | |
477 | /* Invoke any callbacks, transfer the buffer to caller, | |
478 | * and fire off the (possibly) blocking | |
e6bb4c9c | 479 | * iwl_trans_send_cmd() |
ab697a9f EG |
480 | * as we reclaim the driver command queue */ |
481 | if (rxb->page) | |
247c61d6 | 482 | iwl_tx_cmd_complete(trans, rxb, err); |
ab697a9f | 483 | else |
5a878bf6 | 484 | IWL_WARN(trans, "Claim null rxb?\n"); |
ab697a9f EG |
485 | } |
486 | ||
487 | /* Reuse the page if possible. For notification packets and | |
488 | * SKBs that fail to Rx correctly, add them back into the | |
489 | * rx_free list for reuse later. */ | |
490 | spin_lock_irqsave(&rxq->lock, flags); | |
491 | if (rxb->page != NULL) { | |
1042db2a | 492 | rxb->page_dma = dma_map_page(trans->dev, rxb->page, |
d6189124 | 493 | 0, PAGE_SIZE << |
5a878bf6 | 494 | hw_params(trans).rx_page_order, |
ab697a9f EG |
495 | DMA_FROM_DEVICE); |
496 | list_add_tail(&rxb->list, &rxq->rx_free); | |
497 | rxq->free_count++; | |
498 | } else | |
499 | list_add_tail(&rxb->list, &rxq->rx_used); | |
500 | ||
501 | spin_unlock_irqrestore(&rxq->lock, flags); | |
502 | ||
503 | i = (i + 1) & RX_QUEUE_MASK; | |
504 | /* If there are a lot of unused frames, | |
505 | * restock the Rx queue so ucode wont assert. */ | |
506 | if (fill_rx) { | |
507 | count++; | |
508 | if (count >= 8) { | |
509 | rxq->read = i; | |
5a878bf6 | 510 | iwlagn_rx_replenish_now(trans); |
ab697a9f EG |
511 | count = 0; |
512 | } | |
513 | } | |
514 | } | |
515 | ||
516 | /* Backtrack one entry */ | |
517 | rxq->read = i; | |
518 | if (fill_rx) | |
5a878bf6 | 519 | iwlagn_rx_replenish_now(trans); |
ab697a9f | 520 | else |
5a878bf6 | 521 | iwlagn_rx_queue_restock(trans); |
ab697a9f EG |
522 | } |
523 | ||
7ff94706 EG |
524 | static const char * const desc_lookup_text[] = { |
525 | "OK", | |
526 | "FAIL", | |
527 | "BAD_PARAM", | |
528 | "BAD_CHECKSUM", | |
529 | "NMI_INTERRUPT_WDG", | |
530 | "SYSASSERT", | |
531 | "FATAL_ERROR", | |
532 | "BAD_COMMAND", | |
533 | "HW_ERROR_TUNE_LOCK", | |
534 | "HW_ERROR_TEMPERATURE", | |
535 | "ILLEGAL_CHAN_FREQ", | |
536 | "VCC_NOT_STABLE", | |
537 | "FH_ERROR", | |
538 | "NMI_INTERRUPT_HOST", | |
539 | "NMI_INTERRUPT_ACTION_PT", | |
540 | "NMI_INTERRUPT_UNKNOWN", | |
541 | "UCODE_VERSION_MISMATCH", | |
542 | "HW_ERROR_ABS_LOCK", | |
543 | "HW_ERROR_CAL_LOCK_FAIL", | |
544 | "NMI_INTERRUPT_INST_ACTION_PT", | |
545 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
546 | "NMI_TRM_HW_ER", | |
547 | "NMI_INTERRUPT_TRM", | |
548 | "NMI_INTERRUPT_BREAK_POINT", | |
549 | "DEBUG_0", | |
550 | "DEBUG_1", | |
551 | "DEBUG_2", | |
552 | "DEBUG_3", | |
553 | }; | |
554 | ||
555 | static struct { char *name; u8 num; } advanced_lookup[] = { | |
556 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
557 | { "SYSASSERT", 0x35 }, | |
558 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
559 | { "BAD_COMMAND", 0x38 }, | |
560 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
561 | { "FATAL_ERROR", 0x3D }, | |
562 | { "NMI_TRM_HW_ERR", 0x46 }, | |
563 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
564 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
565 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
566 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
567 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
568 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
569 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
570 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
571 | { "ADVANCED_SYSASSERT", 0 }, | |
572 | }; | |
573 | ||
574 | static const char *desc_lookup(u32 num) | |
575 | { | |
576 | int i; | |
577 | int max = ARRAY_SIZE(desc_lookup_text); | |
578 | ||
579 | if (num < max) | |
580 | return desc_lookup_text[num]; | |
581 | ||
582 | max = ARRAY_SIZE(advanced_lookup) - 1; | |
583 | for (i = 0; i < max; i++) { | |
584 | if (advanced_lookup[i].num == num) | |
585 | break; | |
586 | } | |
587 | return advanced_lookup[i].name; | |
588 | } | |
589 | ||
590 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
591 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
592 | ||
6bb78847 | 593 | static void iwl_dump_nic_error_log(struct iwl_trans *trans) |
7ff94706 EG |
594 | { |
595 | u32 base; | |
596 | struct iwl_error_event_table table; | |
6bb78847 | 597 | struct iwl_priv *priv = priv(trans); |
1f7b6172 EG |
598 | struct iwl_trans_pcie *trans_pcie = |
599 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
7ff94706 | 600 | |
ae6130fc | 601 | base = trans->shrd->device_pointers.error_event_table; |
3d6acefc | 602 | if (trans->shrd->ucode_type == IWL_UCODE_INIT) { |
7ff94706 EG |
603 | if (!base) |
604 | base = priv->init_errlog_ptr; | |
605 | } else { | |
606 | if (!base) | |
607 | base = priv->inst_errlog_ptr; | |
608 | } | |
609 | ||
610 | if (!iwlagn_hw_valid_rtc_data_addr(base)) { | |
6bb78847 | 611 | IWL_ERR(trans, |
7ff94706 EG |
612 | "Not valid error log pointer 0x%08X for %s uCode\n", |
613 | base, | |
3d6acefc | 614 | (trans->shrd->ucode_type == IWL_UCODE_INIT) |
7ff94706 EG |
615 | ? "Init" : "RT"); |
616 | return; | |
617 | } | |
618 | ||
1042db2a | 619 | iwl_read_targ_mem_words(trans(priv), base, &table, sizeof(table)); |
7ff94706 EG |
620 | |
621 | if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { | |
6bb78847 EG |
622 | IWL_ERR(trans, "Start IWL Error Log Dump:\n"); |
623 | IWL_ERR(trans, "Status: 0x%08lX, count: %d\n", | |
624 | trans->shrd->status, table.valid); | |
7ff94706 EG |
625 | } |
626 | ||
1f7b6172 | 627 | trans_pcie->isr_stats.err_code = table.error_id; |
7ff94706 EG |
628 | |
629 | trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low, | |
630 | table.data1, table.data2, table.line, | |
631 | table.blink1, table.blink2, table.ilink1, | |
632 | table.ilink2, table.bcon_time, table.gp1, | |
633 | table.gp2, table.gp3, table.ucode_ver, | |
634 | table.hw_ver, table.brd_ver); | |
6bb78847 | 635 | IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id, |
7ff94706 | 636 | desc_lookup(table.error_id)); |
6bb78847 EG |
637 | IWL_ERR(trans, "0x%08X | uPc\n", table.pc); |
638 | IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1); | |
639 | IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2); | |
640 | IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1); | |
641 | IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2); | |
642 | IWL_ERR(trans, "0x%08X | data1\n", table.data1); | |
643 | IWL_ERR(trans, "0x%08X | data2\n", table.data2); | |
644 | IWL_ERR(trans, "0x%08X | line\n", table.line); | |
645 | IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time); | |
646 | IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low); | |
647 | IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi); | |
648 | IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1); | |
649 | IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2); | |
650 | IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3); | |
651 | IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver); | |
652 | IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver); | |
653 | IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver); | |
654 | IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd); | |
d332f591 WYG |
655 | |
656 | IWL_ERR(trans, "0x%08X | isr0\n", table.isr0); | |
657 | IWL_ERR(trans, "0x%08X | isr1\n", table.isr1); | |
658 | IWL_ERR(trans, "0x%08X | isr2\n", table.isr2); | |
659 | IWL_ERR(trans, "0x%08X | isr3\n", table.isr3); | |
660 | IWL_ERR(trans, "0x%08X | isr4\n", table.isr4); | |
661 | IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref); | |
662 | IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event); | |
663 | IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control); | |
664 | IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration); | |
665 | IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid); | |
666 | IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match); | |
667 | IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel); | |
668 | IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp); | |
669 | IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler); | |
7ff94706 EG |
670 | } |
671 | ||
672 | /** | |
673 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | |
674 | */ | |
6bb78847 | 675 | static void iwl_irq_handle_error(struct iwl_trans *trans) |
7ff94706 | 676 | { |
6bb78847 | 677 | struct iwl_priv *priv = priv(trans); |
7ff94706 | 678 | /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ |
38622419 | 679 | if (cfg(priv)->internal_wimax_coex && |
1042db2a | 680 | (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) & |
7ff94706 | 681 | APMS_CLK_VAL_MRB_FUNC_MODE) || |
1042db2a | 682 | (iwl_read_prph(trans, APMG_PS_CTRL_REG) & |
7ff94706 EG |
683 | APMG_PS_CTRL_VAL_RESET_REQ))) { |
684 | /* | |
685 | * Keep the restart process from trying to send host | |
686 | * commands by clearing the ready bit. | |
687 | */ | |
6bb78847 EG |
688 | clear_bit(STATUS_READY, &trans->shrd->status); |
689 | clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status); | |
effd4d9a | 690 | wake_up(&priv->shrd->wait_command_queue); |
6bb78847 | 691 | IWL_ERR(trans, "RF is used by WiMAX\n"); |
7ff94706 EG |
692 | return; |
693 | } | |
694 | ||
6bb78847 | 695 | IWL_ERR(trans, "Loaded firmware version: %s\n", |
7ff94706 EG |
696 | priv->hw->wiphy->fw_version); |
697 | ||
6bb78847 EG |
698 | iwl_dump_nic_error_log(trans); |
699 | iwl_dump_csr(trans); | |
700 | iwl_dump_fh(trans, NULL, false); | |
701 | iwl_dump_nic_event_log(trans, false, NULL, false); | |
7ff94706 | 702 | #ifdef CONFIG_IWLWIFI_DEBUG |
6bb78847 | 703 | if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) |
522376d2 | 704 | iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS); |
7ff94706 EG |
705 | #endif |
706 | ||
707 | iwlagn_fw_error(priv, false); | |
708 | } | |
709 | ||
710 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
711 | ||
712 | /** | |
713 | * iwl_print_event_log - Dump error event log to syslog | |
714 | * | |
715 | */ | |
6bb78847 | 716 | static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx, |
7ff94706 EG |
717 | u32 num_events, u32 mode, |
718 | int pos, char **buf, size_t bufsz) | |
719 | { | |
720 | u32 i; | |
721 | u32 base; /* SRAM byte address of event log header */ | |
722 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
723 | u32 ptr; /* SRAM byte address of log data */ | |
724 | u32 ev, time, data; /* event log data */ | |
725 | unsigned long reg_flags; | |
6bb78847 | 726 | struct iwl_priv *priv = priv(trans); |
7ff94706 EG |
727 | |
728 | if (num_events == 0) | |
729 | return pos; | |
730 | ||
ae6130fc | 731 | base = trans->shrd->device_pointers.log_event_table; |
3d6acefc | 732 | if (trans->shrd->ucode_type == IWL_UCODE_INIT) { |
7ff94706 EG |
733 | if (!base) |
734 | base = priv->init_evtlog_ptr; | |
735 | } else { | |
736 | if (!base) | |
737 | base = priv->inst_evtlog_ptr; | |
738 | } | |
739 | ||
740 | if (mode == 0) | |
741 | event_size = 2 * sizeof(u32); | |
742 | else | |
743 | event_size = 3 * sizeof(u32); | |
744 | ||
745 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
746 | ||
747 | /* Make sure device is powered up for SRAM reads */ | |
1042db2a EG |
748 | spin_lock_irqsave(&trans->reg_lock, reg_flags); |
749 | iwl_grab_nic_access(trans); | |
7ff94706 EG |
750 | |
751 | /* Set starting address; reads will auto-increment */ | |
1042db2a | 752 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr); |
7ff94706 EG |
753 | rmb(); |
754 | ||
755 | /* "time" is actually "data" for mode 0 (no timestamp). | |
756 | * place event id # at far right for easier visual parsing. */ | |
757 | for (i = 0; i < num_events; i++) { | |
1042db2a EG |
758 | ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT); |
759 | time = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
7ff94706 EG |
760 | if (mode == 0) { |
761 | /* data, ev */ | |
762 | if (bufsz) { | |
763 | pos += scnprintf(*buf + pos, bufsz - pos, | |
764 | "EVT_LOG:0x%08x:%04u\n", | |
765 | time, ev); | |
766 | } else { | |
767 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
768 | time, ev); | |
6bb78847 | 769 | IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n", |
7ff94706 EG |
770 | time, ev); |
771 | } | |
772 | } else { | |
1042db2a | 773 | data = iwl_read32(trans, HBUS_TARG_MEM_RDAT); |
7ff94706 EG |
774 | if (bufsz) { |
775 | pos += scnprintf(*buf + pos, bufsz - pos, | |
776 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
777 | time, data, ev); | |
778 | } else { | |
6bb78847 | 779 | IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n", |
7ff94706 EG |
780 | time, data, ev); |
781 | trace_iwlwifi_dev_ucode_event(priv, time, | |
782 | data, ev); | |
783 | } | |
784 | } | |
785 | } | |
786 | ||
787 | /* Allow device to power down */ | |
1042db2a EG |
788 | iwl_release_nic_access(trans); |
789 | spin_unlock_irqrestore(&trans->reg_lock, reg_flags); | |
7ff94706 EG |
790 | return pos; |
791 | } | |
792 | ||
793 | /** | |
794 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
795 | */ | |
6bb78847 | 796 | static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity, |
7ff94706 EG |
797 | u32 num_wraps, u32 next_entry, |
798 | u32 size, u32 mode, | |
799 | int pos, char **buf, size_t bufsz) | |
800 | { | |
801 | /* | |
802 | * display the newest DEFAULT_LOG_ENTRIES entries | |
803 | * i.e the entries just before the next ont that uCode would fill. | |
804 | */ | |
805 | if (num_wraps) { | |
806 | if (next_entry < size) { | |
6bb78847 | 807 | pos = iwl_print_event_log(trans, |
7ff94706 EG |
808 | capacity - (size - next_entry), |
809 | size - next_entry, mode, | |
810 | pos, buf, bufsz); | |
6bb78847 | 811 | pos = iwl_print_event_log(trans, 0, |
7ff94706 EG |
812 | next_entry, mode, |
813 | pos, buf, bufsz); | |
814 | } else | |
6bb78847 | 815 | pos = iwl_print_event_log(trans, next_entry - size, |
7ff94706 EG |
816 | size, mode, pos, buf, bufsz); |
817 | } else { | |
818 | if (next_entry < size) { | |
6bb78847 | 819 | pos = iwl_print_event_log(trans, 0, next_entry, |
7ff94706 EG |
820 | mode, pos, buf, bufsz); |
821 | } else { | |
6bb78847 | 822 | pos = iwl_print_event_log(trans, next_entry - size, |
7ff94706 EG |
823 | size, mode, pos, buf, bufsz); |
824 | } | |
825 | } | |
826 | return pos; | |
827 | } | |
828 | ||
829 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) | |
830 | ||
6bb78847 | 831 | int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log, |
7ff94706 EG |
832 | char **buf, bool display) |
833 | { | |
834 | u32 base; /* SRAM byte address of event log header */ | |
835 | u32 capacity; /* event log capacity in # entries */ | |
836 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
837 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
838 | u32 next_entry; /* index of next entry to be written by uCode */ | |
839 | u32 size; /* # entries that we'll print */ | |
840 | u32 logsize; | |
841 | int pos = 0; | |
842 | size_t bufsz = 0; | |
6bb78847 | 843 | struct iwl_priv *priv = priv(trans); |
7ff94706 | 844 | |
ae6130fc | 845 | base = trans->shrd->device_pointers.log_event_table; |
3d6acefc | 846 | if (trans->shrd->ucode_type == IWL_UCODE_INIT) { |
7ff94706 EG |
847 | logsize = priv->init_evtlog_size; |
848 | if (!base) | |
849 | base = priv->init_evtlog_ptr; | |
850 | } else { | |
851 | logsize = priv->inst_evtlog_size; | |
852 | if (!base) | |
853 | base = priv->inst_evtlog_ptr; | |
854 | } | |
855 | ||
856 | if (!iwlagn_hw_valid_rtc_data_addr(base)) { | |
6bb78847 | 857 | IWL_ERR(trans, |
7ff94706 EG |
858 | "Invalid event log pointer 0x%08X for %s uCode\n", |
859 | base, | |
3d6acefc | 860 | (trans->shrd->ucode_type == IWL_UCODE_INIT) |
7ff94706 EG |
861 | ? "Init" : "RT"); |
862 | return -EINVAL; | |
863 | } | |
864 | ||
865 | /* event log header */ | |
1042db2a EG |
866 | capacity = iwl_read_targ_mem(trans, base); |
867 | mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32))); | |
868 | num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32))); | |
869 | next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32))); | |
7ff94706 EG |
870 | |
871 | if (capacity > logsize) { | |
6bb78847 EG |
872 | IWL_ERR(trans, "Log capacity %d is bogus, limit to %d " |
873 | "entries\n", capacity, logsize); | |
7ff94706 EG |
874 | capacity = logsize; |
875 | } | |
876 | ||
877 | if (next_entry > logsize) { | |
6bb78847 | 878 | IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n", |
7ff94706 EG |
879 | next_entry, logsize); |
880 | next_entry = logsize; | |
881 | } | |
882 | ||
883 | size = num_wraps ? capacity : next_entry; | |
884 | ||
885 | /* bail out if nothing in log */ | |
886 | if (size == 0) { | |
6bb78847 | 887 | IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n"); |
7ff94706 EG |
888 | return pos; |
889 | } | |
890 | ||
7ff94706 | 891 | #ifdef CONFIG_IWLWIFI_DEBUG |
6bb78847 | 892 | if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log) |
7ff94706 EG |
893 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
894 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
895 | #else | |
896 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
897 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
898 | #endif | |
6bb78847 | 899 | IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n", |
7ff94706 EG |
900 | size); |
901 | ||
902 | #ifdef CONFIG_IWLWIFI_DEBUG | |
903 | if (display) { | |
904 | if (full_log) | |
905 | bufsz = capacity * 48; | |
906 | else | |
907 | bufsz = size * 48; | |
908 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
909 | if (!*buf) | |
910 | return -ENOMEM; | |
911 | } | |
6bb78847 | 912 | if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) { |
7ff94706 EG |
913 | /* |
914 | * if uCode has wrapped back to top of log, | |
915 | * start at the oldest entry, | |
916 | * i.e the next one that uCode would fill. | |
917 | */ | |
918 | if (num_wraps) | |
6bb78847 | 919 | pos = iwl_print_event_log(trans, next_entry, |
7ff94706 EG |
920 | capacity - next_entry, mode, |
921 | pos, buf, bufsz); | |
922 | /* (then/else) start at top of log */ | |
6bb78847 | 923 | pos = iwl_print_event_log(trans, 0, |
7ff94706 EG |
924 | next_entry, mode, pos, buf, bufsz); |
925 | } else | |
6bb78847 | 926 | pos = iwl_print_last_event_logs(trans, capacity, num_wraps, |
7ff94706 EG |
927 | next_entry, size, mode, |
928 | pos, buf, bufsz); | |
929 | #else | |
6bb78847 | 930 | pos = iwl_print_last_event_logs(trans, capacity, num_wraps, |
7ff94706 EG |
931 | next_entry, size, mode, |
932 | pos, buf, bufsz); | |
933 | #endif | |
934 | return pos; | |
935 | } | |
936 | ||
ab697a9f | 937 | /* tasklet for iwlagn interrupt */ |
0c325769 | 938 | void iwl_irq_tasklet(struct iwl_trans *trans) |
ab697a9f EG |
939 | { |
940 | u32 inta = 0; | |
941 | u32 handled = 0; | |
942 | unsigned long flags; | |
943 | u32 i; | |
944 | #ifdef CONFIG_IWLWIFI_DEBUG | |
945 | u32 inta_mask; | |
946 | #endif | |
947 | ||
3e10caeb | 948 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
949 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
950 | ||
0c325769 EG |
951 | |
952 | spin_lock_irqsave(&trans->shrd->lock, flags); | |
ab697a9f EG |
953 | |
954 | /* Ack/clear/reset pending uCode interrupts. | |
955 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
956 | */ | |
957 | /* There is a hardware bug in the interrupt mask function that some | |
958 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
959 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
960 | * ICT interrupt handling mechanism has another bug that might cause | |
961 | * these unmasked interrupts fail to be detected. We workaround the | |
962 | * hardware bugs here by ACKing all the possible interrupts so that | |
963 | * interrupt coalescing can still be achieved. | |
964 | */ | |
1042db2a | 965 | iwl_write32(trans, CSR_INT, |
0c325769 | 966 | trans_pcie->inta | ~trans_pcie->inta_mask); |
ab697a9f | 967 | |
0c325769 | 968 | inta = trans_pcie->inta; |
ab697a9f EG |
969 | |
970 | #ifdef CONFIG_IWLWIFI_DEBUG | |
0c325769 | 971 | if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) { |
ab697a9f | 972 | /* just for debug */ |
1042db2a | 973 | inta_mask = iwl_read32(trans, CSR_INT_MASK); |
0c325769 | 974 | IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ", |
ab697a9f EG |
975 | inta, inta_mask); |
976 | } | |
977 | #endif | |
978 | ||
0c325769 EG |
979 | /* saved interrupt in inta variable now we can reset trans_pcie->inta */ |
980 | trans_pcie->inta = 0; | |
ab697a9f | 981 | |
b49ba04a JB |
982 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
983 | ||
ab697a9f EG |
984 | /* Now service all interrupt bits discovered above. */ |
985 | if (inta & CSR_INT_BIT_HW_ERR) { | |
0c325769 | 986 | IWL_ERR(trans, "Hardware error detected. Restarting.\n"); |
ab697a9f EG |
987 | |
988 | /* Tell the device to stop sending interrupts */ | |
0c325769 | 989 | iwl_disable_interrupts(trans); |
ab697a9f | 990 | |
1f7b6172 | 991 | isr_stats->hw++; |
6bb78847 | 992 | iwl_irq_handle_error(trans); |
ab697a9f EG |
993 | |
994 | handled |= CSR_INT_BIT_HW_ERR; | |
995 | ||
996 | return; | |
997 | } | |
998 | ||
999 | #ifdef CONFIG_IWLWIFI_DEBUG | |
0c325769 | 1000 | if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) { |
ab697a9f EG |
1001 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1002 | if (inta & CSR_INT_BIT_SCD) { | |
0c325769 | 1003 | IWL_DEBUG_ISR(trans, "Scheduler finished to transmit " |
ab697a9f | 1004 | "the frame/frames.\n"); |
1f7b6172 | 1005 | isr_stats->sch++; |
ab697a9f EG |
1006 | } |
1007 | ||
1008 | /* Alive notification via Rx interrupt will do the real work */ | |
1009 | if (inta & CSR_INT_BIT_ALIVE) { | |
0c325769 | 1010 | IWL_DEBUG_ISR(trans, "Alive interrupt\n"); |
1f7b6172 | 1011 | isr_stats->alive++; |
ab697a9f EG |
1012 | } |
1013 | } | |
1014 | #endif | |
1015 | /* Safely ignore these bits for debug checks below */ | |
1016 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1017 | ||
1018 | /* HW RF KILL switch toggled */ | |
1019 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1020 | int hw_rf_kill = 0; | |
1042db2a | 1021 | if (!(iwl_read32(trans, CSR_GP_CNTRL) & |
ab697a9f EG |
1022 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1023 | hw_rf_kill = 1; | |
1024 | ||
0c325769 | 1025 | IWL_WARN(trans, "RF_KILL bit toggled to %s.\n", |
ab697a9f EG |
1026 | hw_rf_kill ? "disable radio" : "enable radio"); |
1027 | ||
1f7b6172 | 1028 | isr_stats->rfkill++; |
ab697a9f EG |
1029 | |
1030 | /* driver only loads ucode once setting the interface up. | |
1031 | * the driver allows loading the ucode even if the radio | |
1032 | * is killed. Hence update the killswitch state here. The | |
1033 | * rfkill handler will care about restarting if needed. | |
1034 | */ | |
0c325769 | 1035 | if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) { |
ab697a9f | 1036 | if (hw_rf_kill) |
0c325769 EG |
1037 | set_bit(STATUS_RF_KILL_HW, |
1038 | &trans->shrd->status); | |
ab697a9f | 1039 | else |
63013ae3 | 1040 | clear_bit(STATUS_RF_KILL_HW, |
0c325769 | 1041 | &trans->shrd->status); |
3e10caeb | 1042 | iwl_set_hw_rfkill_state(priv(trans), hw_rf_kill); |
ab697a9f EG |
1043 | } |
1044 | ||
1045 | handled |= CSR_INT_BIT_RF_KILL; | |
1046 | } | |
1047 | ||
1048 | /* Chip got too hot and stopped itself */ | |
1049 | if (inta & CSR_INT_BIT_CT_KILL) { | |
0c325769 | 1050 | IWL_ERR(trans, "Microcode CT kill error detected.\n"); |
1f7b6172 | 1051 | isr_stats->ctkill++; |
ab697a9f EG |
1052 | handled |= CSR_INT_BIT_CT_KILL; |
1053 | } | |
1054 | ||
1055 | /* Error detected by uCode */ | |
1056 | if (inta & CSR_INT_BIT_SW_ERR) { | |
0c325769 | 1057 | IWL_ERR(trans, "Microcode SW error detected. " |
ab697a9f | 1058 | " Restarting 0x%X.\n", inta); |
1f7b6172 | 1059 | isr_stats->sw++; |
6bb78847 | 1060 | iwl_irq_handle_error(trans); |
ab697a9f EG |
1061 | handled |= CSR_INT_BIT_SW_ERR; |
1062 | } | |
1063 | ||
1064 | /* uCode wakes up after power-down sleep */ | |
1065 | if (inta & CSR_INT_BIT_WAKEUP) { | |
0c325769 EG |
1066 | IWL_DEBUG_ISR(trans, "Wakeup interrupt\n"); |
1067 | iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq); | |
1068 | for (i = 0; i < hw_params(trans).max_txq_num; i++) | |
fd656935 | 1069 | iwl_txq_update_write_ptr(trans, |
8ad71bef | 1070 | &trans_pcie->txq[i]); |
ab697a9f | 1071 | |
1f7b6172 | 1072 | isr_stats->wakeup++; |
ab697a9f EG |
1073 | |
1074 | handled |= CSR_INT_BIT_WAKEUP; | |
1075 | } | |
1076 | ||
1077 | /* All uCode command responses, including Tx command responses, | |
1078 | * Rx "responses" (frame-received notification), and other | |
1079 | * notifications from uCode come through here*/ | |
1080 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | | |
1081 | CSR_INT_BIT_RX_PERIODIC)) { | |
0c325769 | 1082 | IWL_DEBUG_ISR(trans, "Rx interrupt\n"); |
ab697a9f EG |
1083 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1084 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1042db2a | 1085 | iwl_write32(trans, CSR_FH_INT_STATUS, |
ab697a9f EG |
1086 | CSR_FH_INT_RX_MASK); |
1087 | } | |
1088 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1089 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1042db2a | 1090 | iwl_write32(trans, |
0c325769 | 1091 | CSR_INT, CSR_INT_BIT_RX_PERIODIC); |
ab697a9f EG |
1092 | } |
1093 | /* Sending RX interrupt require many steps to be done in the | |
1094 | * the device: | |
1095 | * 1- write interrupt to current index in ICT table. | |
1096 | * 2- dma RX frame. | |
1097 | * 3- update RX shared data to indicate last write index. | |
1098 | * 4- send interrupt. | |
1099 | * This could lead to RX race, driver could receive RX interrupt | |
1100 | * but the shared data changes does not reflect this; | |
1101 | * periodic interrupt will detect any dangling Rx activity. | |
1102 | */ | |
1103 | ||
1104 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1042db2a | 1105 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
ab697a9f | 1106 | CSR_INT_PERIODIC_DIS); |
a5916977 GG |
1107 | #ifdef CONFIG_IWLWIFI_IDI |
1108 | iwl_amfh_rx_handler(); | |
1109 | #else | |
0c325769 | 1110 | iwl_rx_handle(trans); |
a5916977 | 1111 | #endif |
ab697a9f EG |
1112 | /* |
1113 | * Enable periodic interrupt in 8 msec only if we received | |
1114 | * real RX interrupt (instead of just periodic int), to catch | |
1115 | * any dangling Rx interrupt. If it was just the periodic | |
1116 | * interrupt, there was no dangling Rx activity, and no need | |
1117 | * to extend the periodic interrupt; one-shot is enough. | |
1118 | */ | |
1119 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1042db2a | 1120 | iwl_write8(trans, CSR_INT_PERIODIC_REG, |
ab697a9f EG |
1121 | CSR_INT_PERIODIC_ENA); |
1122 | ||
1f7b6172 | 1123 | isr_stats->rx++; |
ab697a9f EG |
1124 | } |
1125 | ||
1126 | /* This "Tx" DMA channel is used only for loading uCode */ | |
1127 | if (inta & CSR_INT_BIT_FH_TX) { | |
1042db2a | 1128 | iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
0c325769 | 1129 | IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); |
1f7b6172 | 1130 | isr_stats->tx++; |
ab697a9f EG |
1131 | handled |= CSR_INT_BIT_FH_TX; |
1132 | /* Wake up uCode load routine, now that load is complete */ | |
5703ddb0 | 1133 | trans->ucode_write_complete = 1; |
effd4d9a | 1134 | wake_up(&trans->shrd->wait_command_queue); |
ab697a9f EG |
1135 | } |
1136 | ||
1137 | if (inta & ~handled) { | |
0c325769 | 1138 | IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
1f7b6172 | 1139 | isr_stats->unhandled++; |
ab697a9f EG |
1140 | } |
1141 | ||
0c325769 EG |
1142 | if (inta & ~(trans_pcie->inta_mask)) { |
1143 | IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n", | |
1144 | inta & ~trans_pcie->inta_mask); | |
ab697a9f EG |
1145 | } |
1146 | ||
1147 | /* Re-enable all interrupts */ | |
1148 | /* only Re-enable if disabled by irq */ | |
0c325769 EG |
1149 | if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status)) |
1150 | iwl_enable_interrupts(trans); | |
ab697a9f | 1151 | /* Re-enable RF_KILL if it occurred */ |
1df06bdc EG |
1152 | else if (handled & CSR_INT_BIT_RF_KILL) { |
1153 | IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); | |
1154 | iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); | |
1155 | } | |
ab697a9f EG |
1156 | } |
1157 | ||
1a361cd8 EG |
1158 | /****************************************************************************** |
1159 | * | |
1160 | * ICT functions | |
1161 | * | |
1162 | ******************************************************************************/ | |
10667136 JB |
1163 | |
1164 | /* a device (PCI-E) page is 4096 bytes long */ | |
1165 | #define ICT_SHIFT 12 | |
1166 | #define ICT_SIZE (1 << ICT_SHIFT) | |
1167 | #define ICT_COUNT (ICT_SIZE / sizeof(u32)) | |
1a361cd8 EG |
1168 | |
1169 | /* Free dram table */ | |
0c325769 | 1170 | void iwl_free_isr_ict(struct iwl_trans *trans) |
1a361cd8 | 1171 | { |
0c325769 EG |
1172 | struct iwl_trans_pcie *trans_pcie = |
1173 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1174 | ||
10667136 | 1175 | if (trans_pcie->ict_tbl) { |
1042db2a | 1176 | dma_free_coherent(trans->dev, ICT_SIZE, |
10667136 | 1177 | trans_pcie->ict_tbl, |
0c325769 | 1178 | trans_pcie->ict_tbl_dma); |
10667136 JB |
1179 | trans_pcie->ict_tbl = NULL; |
1180 | trans_pcie->ict_tbl_dma = 0; | |
1a361cd8 EG |
1181 | } |
1182 | } | |
1183 | ||
1184 | ||
10667136 JB |
1185 | /* |
1186 | * allocate dram shared table, it is an aligned memory | |
1187 | * block of ICT_SIZE. | |
1a361cd8 EG |
1188 | * also reset all data related to ICT table interrupt. |
1189 | */ | |
0c325769 | 1190 | int iwl_alloc_isr_ict(struct iwl_trans *trans) |
1a361cd8 | 1191 | { |
0c325769 EG |
1192 | struct iwl_trans_pcie *trans_pcie = |
1193 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1a361cd8 | 1194 | |
10667136 | 1195 | trans_pcie->ict_tbl = |
1042db2a | 1196 | dma_alloc_coherent(trans->dev, ICT_SIZE, |
10667136 JB |
1197 | &trans_pcie->ict_tbl_dma, |
1198 | GFP_KERNEL); | |
1199 | if (!trans_pcie->ict_tbl) | |
1a361cd8 EG |
1200 | return -ENOMEM; |
1201 | ||
10667136 JB |
1202 | /* just an API sanity check ... it is guaranteed to be aligned */ |
1203 | if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) { | |
1204 | iwl_free_isr_ict(trans); | |
1205 | return -EINVAL; | |
1206 | } | |
1a361cd8 | 1207 | |
10667136 JB |
1208 | IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n", |
1209 | (unsigned long long)trans_pcie->ict_tbl_dma); | |
1a361cd8 | 1210 | |
10667136 | 1211 | IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl); |
1a361cd8 EG |
1212 | |
1213 | /* reset table and index to all 0 */ | |
10667136 | 1214 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
0c325769 | 1215 | trans_pcie->ict_index = 0; |
1a361cd8 EG |
1216 | |
1217 | /* add periodic RX interrupt */ | |
0c325769 | 1218 | trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC; |
1a361cd8 EG |
1219 | return 0; |
1220 | } | |
1221 | ||
1222 | /* Device is going up inform it about using ICT interrupt table, | |
1223 | * also we need to tell the driver to start using ICT interrupt. | |
1224 | */ | |
ed6a3803 | 1225 | void iwl_reset_ict(struct iwl_trans *trans) |
1a361cd8 EG |
1226 | { |
1227 | u32 val; | |
1228 | unsigned long flags; | |
0c325769 EG |
1229 | struct iwl_trans_pcie *trans_pcie = |
1230 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1a361cd8 | 1231 | |
10667136 | 1232 | if (!trans_pcie->ict_tbl) |
ed6a3803 | 1233 | return; |
1a361cd8 | 1234 | |
0c325769 EG |
1235 | spin_lock_irqsave(&trans->shrd->lock, flags); |
1236 | iwl_disable_interrupts(trans); | |
1a361cd8 | 1237 | |
10667136 | 1238 | memset(trans_pcie->ict_tbl, 0, ICT_SIZE); |
1a361cd8 | 1239 | |
10667136 | 1240 | val = trans_pcie->ict_tbl_dma >> ICT_SHIFT; |
1a361cd8 EG |
1241 | |
1242 | val |= CSR_DRAM_INT_TBL_ENABLE; | |
1243 | val |= CSR_DRAM_INIT_TBL_WRAP_CHECK; | |
1244 | ||
10667136 | 1245 | IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val); |
1a361cd8 | 1246 | |
1042db2a | 1247 | iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val); |
0c325769 EG |
1248 | trans_pcie->use_ict = true; |
1249 | trans_pcie->ict_index = 0; | |
1042db2a | 1250 | iwl_write32(trans, CSR_INT, trans_pcie->inta_mask); |
0c325769 EG |
1251 | iwl_enable_interrupts(trans); |
1252 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
1a361cd8 EG |
1253 | } |
1254 | ||
1255 | /* Device is going down disable ict interrupt usage */ | |
0c325769 | 1256 | void iwl_disable_ict(struct iwl_trans *trans) |
1a361cd8 | 1257 | { |
0c325769 EG |
1258 | struct iwl_trans_pcie *trans_pcie = |
1259 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1260 | ||
1a361cd8 EG |
1261 | unsigned long flags; |
1262 | ||
0c325769 EG |
1263 | spin_lock_irqsave(&trans->shrd->lock, flags); |
1264 | trans_pcie->use_ict = false; | |
1265 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
1a361cd8 EG |
1266 | } |
1267 | ||
1268 | static irqreturn_t iwl_isr(int irq, void *data) | |
1269 | { | |
0c325769 EG |
1270 | struct iwl_trans *trans = data; |
1271 | struct iwl_trans_pcie *trans_pcie; | |
1a361cd8 EG |
1272 | u32 inta, inta_mask; |
1273 | unsigned long flags; | |
1274 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1275 | u32 inta_fh; | |
1276 | #endif | |
0c325769 | 1277 | if (!trans) |
1a361cd8 EG |
1278 | return IRQ_NONE; |
1279 | ||
b80667ee JB |
1280 | trace_iwlwifi_dev_irq(priv(trans)); |
1281 | ||
0c325769 EG |
1282 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1283 | ||
1284 | spin_lock_irqsave(&trans->shrd->lock, flags); | |
1a361cd8 EG |
1285 | |
1286 | /* Disable (but don't clear!) interrupts here to avoid | |
1287 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1288 | * If we have something to service, the tasklet will re-enable ints. | |
1289 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
1042db2a EG |
1290 | inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */ |
1291 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1a361cd8 EG |
1292 | |
1293 | /* Discover which interrupts are active/pending */ | |
1042db2a | 1294 | inta = iwl_read32(trans, CSR_INT); |
1a361cd8 EG |
1295 | |
1296 | /* Ignore interrupt if there's nothing in NIC to service. | |
1297 | * This may be due to IRQ shared with another device, | |
1298 | * or due to sporadic interrupts thrown from our NIC. */ | |
1299 | if (!inta) { | |
0c325769 | 1300 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1a361cd8 EG |
1301 | goto none; |
1302 | } | |
1303 | ||
1304 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
1305 | /* Hardware disappeared. It might have already raised | |
1306 | * an interrupt */ | |
0c325769 | 1307 | IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta); |
1a361cd8 EG |
1308 | goto unplugged; |
1309 | } | |
1310 | ||
1311 | #ifdef CONFIG_IWLWIFI_DEBUG | |
0c325769 | 1312 | if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) { |
1042db2a | 1313 | inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS); |
0c325769 | 1314 | IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, " |
1a361cd8 EG |
1315 | "fh 0x%08x\n", inta, inta_mask, inta_fh); |
1316 | } | |
1317 | #endif | |
1318 | ||
0c325769 | 1319 | trans_pcie->inta |= inta; |
1a361cd8 EG |
1320 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
1321 | if (likely(inta)) | |
0c325769 EG |
1322 | tasklet_schedule(&trans_pcie->irq_tasklet); |
1323 | else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) && | |
1324 | !trans_pcie->inta) | |
1325 | iwl_enable_interrupts(trans); | |
1a361cd8 EG |
1326 | |
1327 | unplugged: | |
0c325769 | 1328 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
1a361cd8 EG |
1329 | return IRQ_HANDLED; |
1330 | ||
1331 | none: | |
1332 | /* re-enable interrupts here since we don't have anything to service. */ | |
1333 | /* only Re-enable if disabled by irq and no schedules tasklet. */ | |
0c325769 EG |
1334 | if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) && |
1335 | !trans_pcie->inta) | |
1336 | iwl_enable_interrupts(trans); | |
1a361cd8 | 1337 | |
0c325769 | 1338 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
1a361cd8 EG |
1339 | return IRQ_NONE; |
1340 | } | |
1341 | ||
1342 | /* interrupt handler using ict table, with this interrupt driver will | |
1343 | * stop using INTA register to get device's interrupt, reading this register | |
1344 | * is expensive, device will write interrupts in ICT dram table, increment | |
1345 | * index then will fire interrupt to driver, driver will OR all ICT table | |
1346 | * entries from current index up to table entry with 0 value. the result is | |
1347 | * the interrupt we need to service, driver will set the entries back to 0 and | |
1348 | * set index. | |
1349 | */ | |
1350 | irqreturn_t iwl_isr_ict(int irq, void *data) | |
1351 | { | |
0c325769 EG |
1352 | struct iwl_trans *trans = data; |
1353 | struct iwl_trans_pcie *trans_pcie; | |
1a361cd8 EG |
1354 | u32 inta, inta_mask; |
1355 | u32 val = 0; | |
b80667ee | 1356 | u32 read; |
1a361cd8 EG |
1357 | unsigned long flags; |
1358 | ||
0c325769 | 1359 | if (!trans) |
1a361cd8 EG |
1360 | return IRQ_NONE; |
1361 | ||
0c325769 EG |
1362 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1363 | ||
1a361cd8 EG |
1364 | /* dram interrupt table not set yet, |
1365 | * use legacy interrupt. | |
1366 | */ | |
0c325769 | 1367 | if (!trans_pcie->use_ict) |
1a361cd8 EG |
1368 | return iwl_isr(irq, data); |
1369 | ||
b80667ee JB |
1370 | trace_iwlwifi_dev_irq(priv(trans)); |
1371 | ||
0c325769 | 1372 | spin_lock_irqsave(&trans->shrd->lock, flags); |
1a361cd8 EG |
1373 | |
1374 | /* Disable (but don't clear!) interrupts here to avoid | |
1375 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1376 | * If we have something to service, the tasklet will re-enable ints. | |
1377 | * If we *don't* have something, we'll re-enable before leaving here. | |
1378 | */ | |
1042db2a EG |
1379 | inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */ |
1380 | iwl_write32(trans, CSR_INT_MASK, 0x00000000); | |
1a361cd8 EG |
1381 | |
1382 | ||
1383 | /* Ignore interrupt if there's nothing in NIC to service. | |
1384 | * This may be due to IRQ shared with another device, | |
1385 | * or due to sporadic interrupts thrown from our NIC. */ | |
b80667ee JB |
1386 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); |
1387 | trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index, read); | |
1388 | if (!read) { | |
0c325769 | 1389 | IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n"); |
1a361cd8 EG |
1390 | goto none; |
1391 | } | |
1392 | ||
b80667ee JB |
1393 | /* |
1394 | * Collect all entries up to the first 0, starting from ict_index; | |
1395 | * note we already read at ict_index. | |
1396 | */ | |
1397 | do { | |
1398 | val |= read; | |
0c325769 | 1399 | IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n", |
b80667ee | 1400 | trans_pcie->ict_index, read); |
0c325769 EG |
1401 | trans_pcie->ict_tbl[trans_pcie->ict_index] = 0; |
1402 | trans_pcie->ict_index = | |
1403 | iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT); | |
1a361cd8 | 1404 | |
b80667ee JB |
1405 | read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]); |
1406 | trace_iwlwifi_dev_ict_read(priv(trans), trans_pcie->ict_index, | |
1407 | read); | |
1408 | } while (read); | |
1a361cd8 EG |
1409 | |
1410 | /* We should not get this value, just ignore it. */ | |
1411 | if (val == 0xffffffff) | |
1412 | val = 0; | |
1413 | ||
1414 | /* | |
1415 | * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit | |
1416 | * (bit 15 before shifting it to 31) to clear when using interrupt | |
1417 | * coalescing. fortunately, bits 18 and 19 stay set when this happens | |
1418 | * so we use them to decide on the real state of the Rx bit. | |
1419 | * In order words, bit 15 is set if bit 18 or bit 19 are set. | |
1420 | */ | |
1421 | if (val & 0xC0000) | |
1422 | val |= 0x8000; | |
1423 | ||
1424 | inta = (0xff & val) | ((0xff00 & val) << 16); | |
0c325769 | 1425 | IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n", |
1a361cd8 EG |
1426 | inta, inta_mask, val); |
1427 | ||
0c325769 EG |
1428 | inta &= trans_pcie->inta_mask; |
1429 | trans_pcie->inta |= inta; | |
1a361cd8 EG |
1430 | |
1431 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ | |
1432 | if (likely(inta)) | |
0c325769 EG |
1433 | tasklet_schedule(&trans_pcie->irq_tasklet); |
1434 | else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) && | |
b80667ee | 1435 | !trans_pcie->inta) { |
1a361cd8 EG |
1436 | /* Allow interrupt if was disabled by this handler and |
1437 | * no tasklet was schedules, We should not enable interrupt, | |
1438 | * tasklet will enable it. | |
1439 | */ | |
0c325769 | 1440 | iwl_enable_interrupts(trans); |
1a361cd8 EG |
1441 | } |
1442 | ||
0c325769 | 1443 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
1a361cd8 EG |
1444 | return IRQ_HANDLED; |
1445 | ||
1446 | none: | |
1447 | /* re-enable interrupts here since we don't have anything to service. | |
1448 | * only Re-enable if disabled by irq. | |
1449 | */ | |
0c325769 | 1450 | if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) && |
b80667ee | 1451 | !trans_pcie->inta) |
0c325769 | 1452 | iwl_enable_interrupts(trans); |
1a361cd8 | 1453 | |
0c325769 | 1454 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
1a361cd8 EG |
1455 | return IRQ_NONE; |
1456 | } |