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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
128e63ef | 8 | * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. |
b481de9c ZY |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
01ebd063 | 11 | * it under the terms of version 2 of the GNU General Public License as |
b481de9c ZY |
12 | * published by the Free Software Foundation. |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 25 | * in the file called COPYING. |
b481de9c ZY |
26 | * |
27 | * Contact Information: | |
759ef89f | 28 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
128e63ef | 33 | * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. |
b481de9c ZY |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | *****************************************************************************/ | |
62 | ||
63 | #ifndef __iwl_prph_h__ | |
64 | #define __iwl_prph_h__ | |
65 | ||
e3851447 BC |
66 | /* |
67 | * Registers in this file are internal, not PCI bus memory mapped. | |
68 | * Driver accesses these via HBUS_TARG_PRPH_* registers. | |
69 | */ | |
b481de9c ZY |
70 | #define PRPH_BASE (0x00000) |
71 | #define PRPH_END (0xFFFFF) | |
72 | ||
73 | /* APMG (power management) constants */ | |
74 | #define APMG_BASE (PRPH_BASE + 0x3000) | |
75 | #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) | |
76 | #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) | |
77 | #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) | |
78 | #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) | |
79 | #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) | |
80 | #define APMG_RFKILL_REG (APMG_BASE + 0x0014) | |
81 | #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) | |
82 | #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) | |
02c06e4a WYG |
83 | #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058) |
84 | #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C) | |
b481de9c | 85 | |
50619ac9 | 86 | #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) |
b481de9c ZY |
87 | #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) |
88 | #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) | |
89 | ||
4c43e0d0 TW |
90 | #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) |
91 | #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) | |
92 | #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) | |
93 | #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) | |
4c43e0d0 | 94 | #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) |
02c06e4a WYG |
95 | #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ |
96 | #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) | |
b481de9c | 97 | |
4c43e0d0 | 98 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) |
b481de9c | 99 | |
99cd4714 JB |
100 | /* Device system time */ |
101 | #define DEVICE_SYSTEM_TIME_REG 0xA0206C | |
102 | ||
038669e4 EG |
103 | /** |
104 | * Tx Scheduler | |
105 | * | |
a96a27f9 | 106 | * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs |
038669e4 EG |
107 | * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in |
108 | * host DRAM. It steers each frame's Tx command (which contains the frame | |
109 | * data) into one of up to 7 prioritized Tx DMA FIFO channels within the | |
110 | * device. A queue maps to only one (selectable by driver) Tx DMA channel, | |
111 | * but one DMA channel may take input from several queues. | |
112 | * | |
8ff84a2c | 113 | * Tx DMA FIFOs have dedicated purposes. |
038669e4 | 114 | * |
edc1a3a0 | 115 | * For 5000 series and up, they are used differently |
68198865 JB |
116 | * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): |
117 | * | |
118 | * 0 -- EDCA BK (background) frames, lowest priority | |
119 | * 1 -- EDCA BE (best effort) frames, normal priority | |
120 | * 2 -- EDCA VI (video) frames, higher priority | |
121 | * 3 -- EDCA VO (voice) and management frames, highest priority | |
edc1a3a0 JB |
122 | * 4 -- unused |
123 | * 5 -- unused | |
124 | * 6 -- unused | |
68198865 JB |
125 | * 7 -- Commands |
126 | * | |
038669e4 | 127 | * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. |
68198865 JB |
128 | * In addition, driver can map the remaining queues to Tx DMA/FIFO |
129 | * channels 0-3 to support 11n aggregation via EDCA DMA channels. | |
038669e4 EG |
130 | * |
131 | * The driver sets up each queue to work in one of two modes: | |
132 | * | |
133 | * 1) Scheduler-Ack, in which the scheduler automatically supports a | |
134 | * block-ack (BA) window of up to 64 TFDs. In this mode, each queue | |
135 | * contains TFDs for a unique combination of Recipient Address (RA) | |
136 | * and Traffic Identifier (TID), that is, traffic of a given | |
137 | * Quality-Of-Service (QOS) priority, destined for a single station. | |
138 | * | |
139 | * In scheduler-ack mode, the scheduler keeps track of the Tx status of | |
140 | * each frame within the BA window, including whether it's been transmitted, | |
141 | * and whether it's been acknowledged by the receiving station. The device | |
142 | * automatically processes block-acks received from the receiving STA, | |
143 | * and reschedules un-acked frames to be retransmitted (successful | |
144 | * Tx completion may end up being out-of-order). | |
145 | * | |
146 | * The driver must maintain the queue's Byte Count table in host DRAM | |
8ff84a2c | 147 | * for this mode. |
038669e4 EG |
148 | * This mode does not support fragmentation. |
149 | * | |
150 | * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. | |
151 | * The device may automatically retry Tx, but will retry only one frame | |
152 | * at a time, until receiving ACK from receiving station, or reaching | |
153 | * retry limit and giving up. | |
154 | * | |
13bb9483 | 155 | * The command queue (#4/#9) must use this mode! |
038669e4 EG |
156 | * This mode does not require use of the Byte Count table in host DRAM. |
157 | * | |
158 | * Driver controls scheduler operation via 3 means: | |
159 | * 1) Scheduler registers | |
8ff84a2c | 160 | * 2) Shared scheduler data base in internal SRAM |
038669e4 EG |
161 | * 3) Shared data in host DRAM |
162 | * | |
163 | * Initialization: | |
164 | * | |
165 | * When loading, driver should allocate memory for: | |
166 | * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. | |
167 | * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory | |
168 | * (1024 bytes for each queue). | |
169 | * | |
170 | * After receiving "Alive" response from uCode, driver must initialize | |
13bb9483 | 171 | * the scheduler (especially for queue #4/#9, the command queue, otherwise |
038669e4 EG |
172 | * the driver can't issue commands!): |
173 | */ | |
f86af7ba | 174 | #define SCD_MEM_LOWER_BOUND (0x0000) |
038669e4 EG |
175 | |
176 | /** | |
177 | * Max Tx window size is the max number of contiguous TFDs that the scheduler | |
178 | * can keep track of at one time when creating block-ack chains of frames. | |
179 | * Note that "64" matches the number of ack bits in a block-ack packet. | |
038669e4 EG |
180 | */ |
181 | #define SCD_WIN_SIZE 64 | |
182 | #define SCD_FRAME_LIMIT 64 | |
183 | ||
b3c2ce13 EG |
184 | #define SCD_TXFIFO_POS_TID (0) |
185 | #define SCD_TXFIFO_POS_RA (4) | |
186 | #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) | |
038669e4 | 187 | |
f4388adc | 188 | /* agn SCD */ |
b3c2ce13 EG |
189 | #define SCD_QUEUE_STTS_REG_POS_TXF (0) |
190 | #define SCD_QUEUE_STTS_REG_POS_ACTIVE (3) | |
191 | #define SCD_QUEUE_STTS_REG_POS_WSL (4) | |
192 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) | |
cde5b487 | 193 | #define SCD_QUEUE_STTS_REG_MSK (0x017F0000) |
b3c2ce13 EG |
194 | |
195 | #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8) | |
196 | #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) | |
197 | #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) | |
198 | #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) | |
199 | #define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) | |
200 | #define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) | |
201 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) | |
202 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) | |
f4388adc | 203 | |
f86af7ba | 204 | /* Context Data */ |
b3c2ce13 EG |
205 | #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600) |
206 | #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) | |
f86af7ba WYG |
207 | |
208 | /* Tx status */ | |
b3c2ce13 EG |
209 | #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) |
210 | #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) | |
f86af7ba WYG |
211 | |
212 | /* Translation Data */ | |
b3c2ce13 EG |
213 | #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) |
214 | #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808) | |
f4388adc | 215 | |
b3c2ce13 EG |
216 | #define SCD_CONTEXT_QUEUE_OFFSET(x)\ |
217 | (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) | |
f4388adc | 218 | |
986ea6c9 EG |
219 | #define SCD_TX_STTS_QUEUE_OFFSET(x)\ |
220 | (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) | |
221 | ||
b3c2ce13 EG |
222 | #define SCD_TRANS_TBL_OFFSET_QUEUE(x) \ |
223 | ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) | |
f4388adc | 224 | |
b3c2ce13 EG |
225 | #define SCD_BASE (PRPH_BASE + 0xa02c00) |
226 | ||
227 | #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0) | |
228 | #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8) | |
229 | #define SCD_AIT (SCD_BASE + 0x0c) | |
230 | #define SCD_TXFACT (SCD_BASE + 0x10) | |
231 | #define SCD_ACTIVE (SCD_BASE + 0x14) | |
b3c2ce13 | 232 | #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8) |
d012d04e | 233 | #define SCD_CHAINEXT_EN (SCD_BASE + 0x244) |
b3c2ce13 EG |
234 | #define SCD_AGGR_SEL (SCD_BASE + 0x248) |
235 | #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108) | |
5ef4acd5 JB |
236 | |
237 | static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl) | |
238 | { | |
239 | if (chnl < 20) | |
240 | return SCD_BASE + 0x18 + chnl * 4; | |
241 | WARN_ON_ONCE(chnl >= 32); | |
242 | return SCD_BASE + 0x284 + (chnl - 20) * 4; | |
243 | } | |
244 | ||
245 | static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl) | |
246 | { | |
247 | if (chnl < 20) | |
248 | return SCD_BASE + 0x68 + chnl * 4; | |
249 | WARN_ON_ONCE(chnl >= 32); | |
250 | return SCD_BASE + 0x2B4 + (chnl - 20) * 4; | |
251 | } | |
252 | ||
253 | static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl) | |
254 | { | |
255 | if (chnl < 20) | |
256 | return SCD_BASE + 0x10c + chnl * 4; | |
257 | WARN_ON_ONCE(chnl >= 32); | |
258 | return SCD_BASE + 0x384 + (chnl - 20) * 4; | |
259 | } | |
b559e66c | 260 | |
038669e4 EG |
261 | /*********************** END TX SCHEDULER *************************************/ |
262 | ||
50920a1d EG |
263 | /* Oscillator clock */ |
264 | #define OSC_CLK (0xa04068) | |
265 | #define OSC_CLK_FORCE_CONTROL (0x8) | |
266 | ||
b481de9c | 267 | #endif /* __iwl_prph_h__ */ |