iwlagn: clean up TX aggregation code
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
7194207c 37#include <linux/wait.h>
5ed540ae 38#include <linux/leds.h>
5d08cd1d
CH
39#include <net/ieee80211_radiotap.h>
40
6bc913bd 41#include "iwl-eeprom.h"
6f83eaa1 42#include "iwl-csr.h"
5d08cd1d 43#include "iwl-prph.h"
dbb6654c 44#include "iwl-fh.h"
0a6857e7 45#include "iwl-debug.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
0975cc8f 50#include "iwl-agn-tt.h"
5d08cd1d 51
be663ab6
WYG
52#define U32_PAD(n) ((4-(n))&0x3)
53
672639de
WYG
54struct iwl_tx_queue;
55
099b40b7 56/* CT-KILL constants */
672639de
WYG
57#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
58#define CT_KILL_THRESHOLD 114 /* in Celsius */
59#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 60
5d08cd1d
CH
61/* Default noise level to report when noise measurement is not available.
62 * This may be because we're:
63 * 1) Not associated (4965, no beacon statistics being sent to driver)
64 * 2) Scanning (noise measurement does not apply to associated channel)
65 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
66 * Use default noise value of -127 ... this is below the range of measurable
67 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
68 * Also, -127 works better than 0 when averaging frames with/without
69 * noise info (e.g. averaging might be done in app); measured dBm values are
70 * always negative ... using a negative value as the default keeps all
71 * averages within an s8's (used in some apps) range of negative values. */
72#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
73
5d08cd1d
CH
74/*
75 * RTS threshold here is total size [2347] minus 4 FCS bytes
76 * Per spec:
77 * a value of 0 means RTS on all data/management packets
78 * a value > max MSDU size means no RTS
79 * else RTS for data/management frames where MPDU is larger
80 * than RTS value.
81 */
82#define DEFAULT_RTS_THRESHOLD 2347U
83#define MIN_RTS_THRESHOLD 0U
84#define MAX_RTS_THRESHOLD 2347U
85#define MAX_MSDU_SIZE 2304U
86#define MAX_MPDU_SIZE 2346U
87#define DEFAULT_BEACON_INTERVAL 100U
88#define DEFAULT_SHORT_RETRY_LIMIT 7U
89#define DEFAULT_LONG_RETRY_LIMIT 4U
90
a55360e4 91struct iwl_rx_mem_buffer {
2f301227
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92 dma_addr_t page_dma;
93 struct page *page;
5d08cd1d
CH
94 struct list_head list;
95};
96
2f301227
ZY
97#define rxb_addr(r) page_address(r->page)
98
c2acea8e
JB
99/* defined below */
100struct iwl_device_cmd;
101
102struct iwl_cmd_meta {
103 /* only for SYNC commands, iff the reply skb is wanted */
104 struct iwl_host_cmd *source;
105 /*
106 * only for ASYNC commands
107 * (which is somewhat stupid -- look at iwl-sta.c for instance
108 * which duplicates a bunch of code because the callback isn't
109 * invoked for SYNC commands, if it were and its result passed
110 * through it would be simpler...)
111 */
5696aea6
JB
112 void (*callback)(struct iwl_priv *priv,
113 struct iwl_device_cmd *cmd,
2f301227 114 struct iwl_rx_packet *pkt);
c2acea8e
JB
115
116 /* The CMD_SIZE_HUGE flag bit indicates that the command
117 * structure is stored at the end of the shared queue memory. */
118 u32 flags;
119
2e724443
FT
120 DEFINE_DMA_UNMAP_ADDR(mapping);
121 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
122};
123
5d08cd1d
CH
124/*
125 * Generic queue structure
126 *
127 * Contains common data for Rx and Tx queues
128 */
443cfd45 129struct iwl_queue {
5d08cd1d
CH
130 int n_bd; /* number of BDs in this queue */
131 int write_ptr; /* 1-st empty entry (index) host_w*/
132 int read_ptr; /* last used entry (index) host_r*/
b74e31a9 133 /* use for monitoring and recovering the stuck queue */
5d08cd1d
CH
134 dma_addr_t dma_addr; /* physical addr for BD's */
135 int n_window; /* safe queue window */
136 u32 id;
137 int low_mark; /* low watermark, resume queue if free
138 * space more than this */
139 int high_mark; /* high watermark, stop queue if free
140 * space less than this */
a839cf69 141};
5d08cd1d 142
bc47279f 143/* One for each TFD */
8567c63e 144struct iwl_tx_info {
ff0d91c3 145 struct sk_buff *skb;
c90cbbbd 146 struct iwl_rxon_context *ctx;
5d08cd1d
CH
147};
148
149/**
16466903 150 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
151 * @q: generic Rx/Tx queue descriptor
152 * @bd: base of circular buffer of TFDs
c2acea8e
JB
153 * @cmd: array of command/TX buffer pointers
154 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
155 * @dma_addr_cmd: physical address of cmd/tx buffer array
156 * @txb: array of per-TFD driver data
22de94de 157 * @time_stamp: time (in jiffies) of last read_ptr change
bc47279f
BC
158 * @need_update: indicates need to update read/write index
159 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 160 *
bc47279f
BC
161 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
162 * descriptors) and required locking structures.
5d08cd1d 163 */
188cf6c7
SO
164#define TFD_TX_CMD_SLOTS 256
165#define TFD_CMD_SLOTS 32
166
16466903 167struct iwl_tx_queue {
443cfd45 168 struct iwl_queue q;
59606ffa 169 void *tfds;
c2acea8e
JB
170 struct iwl_device_cmd **cmd;
171 struct iwl_cmd_meta *meta;
8567c63e 172 struct iwl_tx_info *txb;
22de94de 173 unsigned long time_stamp;
3fd07a1e
TW
174 u8 need_update;
175 u8 sched_retry;
176 u8 active;
177 u8 swq_id;
5d08cd1d
CH
178};
179
180#define IWL_NUM_SCAN_RATES (2)
181
bb8c093b 182struct iwl4965_channel_tgd_info {
5d08cd1d
CH
183 u8 type;
184 s8 max_power;
185};
186
bb8c093b 187struct iwl4965_channel_tgh_info {
5d08cd1d
CH
188 s64 last_radar_time;
189};
190
d20b3c65
SO
191#define IWL4965_MAX_RATE (33)
192
85d41495
KA
193struct iwl3945_clip_group {
194 /* maximum power level to prevent clipping for each rate, derived by
195 * us from this band's saturation power in EEPROM */
196 const s8 clip_powers[IWL_MAX_RATES];
197};
198
d20b3c65
SO
199/* current Tx power values to use, one for each rate for each channel.
200 * requested power is limited by:
201 * -- regulatory EEPROM limits for this channel
202 * -- hardware capabilities (clip-powers)
203 * -- spectrum management
204 * -- user preference (e.g. iwconfig)
205 * when requested power is set, base power index must also be set. */
206struct iwl3945_channel_power_info {
207 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
208 s8 power_table_index; /* actual (compenst'd) index into gain table */
209 s8 base_power_index; /* gain index for power at factory temp. */
210 s8 requested_power; /* power (dBm) requested for this chnl/rate */
211};
212
213/* current scan Tx power values to use, one for each scan rate for each
214 * channel. */
215struct iwl3945_scan_power_info {
216 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
217 s8 power_table_index; /* actual (compenst'd) index into gain table */
218 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
219};
220
5d08cd1d
CH
221/*
222 * One for each channel, holds all channel setup data
223 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
224 * with one another!
225 */
bf85ea4f 226struct iwl_channel_info {
bb8c093b
CH
227 struct iwl4965_channel_tgd_info tgd;
228 struct iwl4965_channel_tgh_info tgh;
073d3f5f 229 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
230 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
231 * HT40 channel */
5d08cd1d
CH
232
233 u8 channel; /* channel number */
234 u8 flags; /* flags copied from EEPROM */
235 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 236 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
237 s8 min_power; /* always 0 */
238 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
239
240 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
241 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 242 enum ieee80211_band band;
5d08cd1d 243
7aafef1c
WYG
244 /* HT40 channel info */
245 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
246 u8 ht40_flags; /* flags copied from EEPROM */
247 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
248
249 /* Radio/DSP gain settings for each "normal" data Tx rate.
250 * These include, in addition to RF and DSP gain, a few fields for
251 * remembering/modifying gain settings (indexes). */
252 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
253
254 /* Radio/DSP gain settings for each scan rate, for directed scans. */
255 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
256};
257
751ca305 258#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 259#define IWL_TX_FIFO_BE 1
751ca305 260#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 261#define IWL_TX_FIFO_VO 3
751ca305
JB
262#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
263#define IWL_TX_FIFO_BE_IPAN 4
264#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
265#define IWL_TX_FIFO_VO_IPAN 5
edc1a3a0 266#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 267
01a7e084
RC
268/* Minimum number of queues. MAX_NUM is defined in hw specific files.
269 * Set the minimum to accommodate the 4 standard TX queues, 1 command
270 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
271#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 272
bd35f150 273/*
13bb9483 274 * Command queue depends on iPAN support.
bd35f150 275 */
13bb9483
JB
276#define IWL_DEFAULT_CMD_QUEUE_NUM 4
277#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 278
751ca305
JB
279/*
280 * This queue number is required for proper operation
281 * because the ucode will stop/start the scheduler as
282 * required.
283 */
284#define IWL_IPAN_MCAST_QUEUE 8
285
5d08cd1d
CH
286#define IEEE80211_DATA_LEN 2304
287#define IEEE80211_4ADDR_LEN 30
288#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
289#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
290
fcab423d 291struct iwl_frame {
5d08cd1d
CH
292 union {
293 struct ieee80211_hdr frame;
4bf64efd 294 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
295 u8 raw[IEEE80211_FRAME_LEN];
296 u8 cmd[360];
297 } u;
298 struct list_head list;
299};
300
5d08cd1d
CH
301#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
302#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
303#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
304
305enum {
c587de0b
TW
306 CMD_SYNC = 0,
307 CMD_SIZE_NORMAL = 0,
308 CMD_NO_SKB = 0,
5d08cd1d 309 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 310 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
311 CMD_WANT_SKB = (1 << 2),
312};
313
c8c24872 314#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 315
bc47279f 316/**
c2acea8e 317 * struct iwl_device_cmd
bc47279f
BC
318 *
319 * For allocation of the command and tx queues, this establishes the overall
320 * size of the largest command we send to uCode, except for a scan command
321 * (which is relatively huge; space is allocated separately).
322 */
c2acea8e 323struct iwl_device_cmd {
857485c0 324 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 325 union {
5d08cd1d
CH
326 u32 flags;
327 u8 val8;
328 u16 val16;
329 u32 val32;
83d527d9 330 struct iwl_tx_cmd tx;
c8c24872
WYG
331 struct iwl6000_channel_switch_cmd chswitch;
332 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
333 } __packed cmd;
334} __packed;
5d08cd1d 335
c2acea8e
JB
336#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
337
3257e5d4 338
857485c0 339struct iwl_host_cmd {
5d08cd1d 340 const void *data;
2f301227 341 unsigned long reply_page;
5696aea6
JB
342 void (*callback)(struct iwl_priv *priv,
343 struct iwl_device_cmd *cmd,
2f301227 344 struct iwl_rx_packet *pkt);
c2acea8e
JB
345 u32 flags;
346 u16 len;
347 u8 id;
5d08cd1d
CH
348};
349
5d08cd1d
CH
350#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
351#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
352#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
353
354/**
a55360e4 355 * struct iwl_rx_queue - Rx queue
df833b1d 356 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 357 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
358 * @read: Shared index to newest available Rx buffer
359 * @write: Shared index to oldest written Rx packet
360 * @free_count: Number of pre-allocated buffers in rx_free
361 * @rx_free: list of free SKBs for use
362 * @rx_used: List of Rx buffers with no SKB
363 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
364 * @rb_stts: driver's pointer to receive buffer status
365 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 366 *
a55360e4 367 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 368 */
a55360e4 369struct iwl_rx_queue {
5d08cd1d 370 __le32 *bd;
d5b25c90 371 dma_addr_t bd_dma;
a55360e4
TW
372 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
373 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
374 u32 read;
375 u32 write;
376 u32 free_count;
4752c93c 377 u32 write_actual;
5d08cd1d
CH
378 struct list_head rx_free;
379 struct list_head rx_used;
380 int need_update;
8d86422a
WT
381 struct iwl_rb_status *rb_stts;
382 dma_addr_t rb_stts_dma;
5d08cd1d
CH
383 spinlock_t lock;
384};
385
386#define IWL_SUPPORTED_RATES_IE_LEN 8
387
5d08cd1d
CH
388#define MAX_TID_COUNT 9
389
390#define IWL_INVALID_RATE 0xFF
391#define IWL_INVALID_VALUE -1
392
bc47279f 393/**
6def9761 394 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
395 * @txq_id: Tx queue used for Tx attempt
396 * @frame_count: # frames attempted by Tx command
397 * @wait_for_ba: Expect block-ack before next Tx reply
398 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
399 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
400 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
401 * @rate_n_flags: Rate at which Tx was attempted
402 *
403 * If REPLY_TX indicates that aggregation was attempted, driver must wait
404 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
405 * until block ack arrives.
406 */
6def9761 407struct iwl_ht_agg {
5d08cd1d
CH
408 u16 txq_id;
409 u16 frame_count;
410 u16 wait_for_ba;
411 u16 start_idx;
fe01b477 412 u64 bitmap;
5d08cd1d 413 u32 rate_n_flags;
fe01b477
RR
414#define IWL_AGG_OFF 0
415#define IWL_AGG_ON 1
416#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
417#define IWL_EMPTYING_HW_QUEUE_DELBA 3
418 u8 state;
5d08cd1d 419};
fe01b477 420
5d08cd1d 421
6def9761 422struct iwl_tid_data {
f862a236 423 u16 seq_number; /* agn only */
fe01b477 424 u16 tfds_in_queue;
6def9761 425 struct iwl_ht_agg agg;
5d08cd1d
CH
426};
427
6def9761 428struct iwl_hw_key {
97359d12 429 u32 cipher;
5d08cd1d 430 int keylen;
0211ddda 431 u8 keyidx;
5d08cd1d
CH
432 u8 key[32];
433};
434
a78fe754 435union iwl_ht_rate_supp {
5d08cd1d
CH
436 u16 rates;
437 struct {
438 u8 siso_rate;
439 u8 mimo_rate;
440 };
441};
442
172c1d11
WYG
443#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
444#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
445#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
446#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
447#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
448#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
449#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
450
451/*
452 * Maximal MPDU density for TX aggregation
453 * 4 - 2us density
454 * 5 - 4us density
455 * 6 - 8us density
456 * 7 - 16us density
457 */
172c1d11 458#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 459#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
460#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
461#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 462#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
463#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
464#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 465
fad95bf5 466struct iwl_ht_config {
02bb1bea 467 bool single_chain_sufficient;
ba37a3d0 468 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 469};
5d08cd1d 470
5d08cd1d 471/* QoS structures */
1ff50bda 472struct iwl_qos_info {
5d08cd1d 473 int qos_active;
1ff50bda 474 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 475};
5d08cd1d 476
fe6b23dd
RC
477/*
478 * Structure should be accessed with sta_lock held. When station addition
479 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
480 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
481 * held.
482 */
6def9761 483struct iwl_station_entry {
133636de 484 struct iwl_addsta_cmd sta;
6def9761 485 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 486 u8 used, ctxid;
6def9761 487 struct iwl_hw_key keyinfo;
fe6b23dd 488 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
489};
490
fd1af15d 491struct iwl_station_priv_common {
238d781d 492 struct iwl_rxon_context *ctx;
fd1af15d
JB
493 u8 sta_id;
494};
495
8d9698b3
RC
496/*
497 * iwl_station_priv: Driver's private station information
498 *
499 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
500 * in the structure for use by driver. This structure is places in that
501 * space.
fd1af15d
JB
502 *
503 * The common struct MUST be first because it is shared between
504 * 3945 and agn!
8d9698b3
RC
505 */
506struct iwl_station_priv {
fd1af15d 507 struct iwl_station_priv_common common;
8d9698b3 508 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
509 atomic_t pending_frames;
510 bool client;
511 bool asleep;
7b090687 512 u8 max_agg_bufsize;
8d9698b3
RC
513};
514
fd1af15d
JB
515/**
516 * struct iwl_vif_priv - driver's private per-interface information
517 *
518 * When mac80211 allocates a virtual interface, it can allocate
519 * space for us to put data into.
520 */
521struct iwl_vif_priv {
246ed355 522 struct iwl_rxon_context *ctx;
fd1af15d
JB
523 u8 ibss_bssid_sta_id;
524};
525
5d08cd1d
CH
526/* one for each uCode image (inst/data, boot/init/runtime) */
527struct fw_desc {
528 void *v_addr; /* access by driver */
529 dma_addr_t p_addr; /* access by card's busmaster DMA */
530 u32 len; /* bytes */
531};
532
dd7a2509 533/* v1/v2 uCode file layout */
cc0f555d
JS
534struct iwl_ucode_header {
535 __le32 ver; /* major/minor/API/serial */
536 union {
537 struct {
538 __le32 inst_size; /* bytes of runtime code */
539 __le32 data_size; /* bytes of runtime data */
540 __le32 init_size; /* bytes of init code */
541 __le32 init_data_size; /* bytes of init data */
542 __le32 boot_size; /* bytes of bootstrap code */
543 u8 data[0]; /* in same order as sizes */
544 } v1;
545 struct {
546 __le32 build; /* build number */
547 __le32 inst_size; /* bytes of runtime code */
548 __le32 data_size; /* bytes of runtime data */
549 __le32 init_size; /* bytes of init code */
550 __le32 init_data_size; /* bytes of init data */
551 __le32 boot_size; /* bytes of bootstrap code */
552 u8 data[0]; /* in same order as sizes */
553 } v2;
554 } u;
5d08cd1d
CH
555};
556
dd7a2509
JB
557/*
558 * new TLV uCode file layout
559 *
560 * The new TLV file format contains TLVs, that each specify
561 * some piece of data. To facilitate "groups", for example
562 * different instruction image with different capabilities,
563 * bundled with the same init image, an alternative mechanism
564 * is provided:
565 * When the alternative field is 0, that means that the item
566 * is always valid. When it is non-zero, then it is only
567 * valid in conjunction with items of the same alternative,
568 * in which case the driver (user) selects one alternative
569 * to use.
570 */
571
572enum iwl_ucode_tlv_type {
573 IWL_UCODE_TLV_INVALID = 0, /* unused */
574 IWL_UCODE_TLV_INST = 1,
575 IWL_UCODE_TLV_DATA = 2,
576 IWL_UCODE_TLV_INIT = 3,
577 IWL_UCODE_TLV_INIT_DATA = 4,
578 IWL_UCODE_TLV_BOOT = 5,
579 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 580 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
581 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
582 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
583 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
584 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
585 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
586 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 587 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 588 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
dd7a2509
JB
589};
590
591struct iwl_ucode_tlv {
592 __le16 type; /* see above */
593 __le16 alternative; /* see comment */
594 __le32 length; /* not including type/length fields */
595 u8 data[0];
ba2d3587 596} __packed;
dd7a2509
JB
597
598#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
599
600struct iwl_tlv_ucode_header {
601 /*
602 * The TLV style ucode header is distinguished from
603 * the v1/v2 style header by first four bytes being
604 * zero, as such is an invalid combination of
605 * major/minor/API/serial versions.
606 */
607 __le32 zero;
608 __le32 magic;
609 u8 human_readable[64];
610 __le32 ver; /* major/minor/API/serial */
611 __le32 build;
612 __le64 alternatives; /* bitmask of valid alternatives */
613 /*
614 * The data contained herein has a TLV layout,
615 * see above for the TLV header and types.
616 * Note that each TLV is padded to a length
617 * that is a multiple of 4 for alignment.
618 */
619 u8 data[0];
620};
621
bb8c093b 622struct iwl4965_ibss_seq {
5d08cd1d
CH
623 u8 mac[ETH_ALEN];
624 u16 seq_num;
625 u16 frag_num;
626 unsigned long packet_time;
627 struct list_head list;
628};
629
f0832f13
EG
630struct iwl_sensitivity_ranges {
631 u16 min_nrg_cck;
632 u16 max_nrg_cck;
633
634 u16 nrg_th_cck;
635 u16 nrg_th_ofdm;
636
637 u16 auto_corr_min_ofdm;
638 u16 auto_corr_min_ofdm_mrc;
639 u16 auto_corr_min_ofdm_x1;
640 u16 auto_corr_min_ofdm_mrc_x1;
641
642 u16 auto_corr_max_ofdm;
643 u16 auto_corr_max_ofdm_mrc;
644 u16 auto_corr_max_ofdm_x1;
645 u16 auto_corr_max_ofdm_mrc_x1;
646
647 u16 auto_corr_max_cck;
648 u16 auto_corr_max_cck_mrc;
649 u16 auto_corr_min_cck;
650 u16 auto_corr_min_cck_mrc;
55036d66
WYG
651
652 u16 barker_corr_th_min;
653 u16 barker_corr_th_min_mrc;
654 u16 nrg_th_cca;
f0832f13
EG
655};
656
099b40b7 657
b5047f78
TW
658#define KELVIN_TO_CELSIUS(x) ((x)-273)
659#define CELSIUS_TO_KELVIN(x) ((x)+273)
660
661
bc47279f 662/**
5425e490 663 * struct iwl_hw_params
bc47279f 664 * @max_txq_num: Max # Tx queues supported
f3f911d1 665 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 666 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 667 * @tfd_size: TFD size
099b40b7
RR
668 * @tx/rx_chains_num: Number of TX/RX chains
669 * @valid_tx/rx_ant: usable antennas
bc47279f 670 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 671 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 672 * @rx_page_order: Rx buffer page order
141c43a3 673 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 674 * @max_stations:
7aafef1c 675 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
676 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
677 * @sw_crypto: 0 for hw, 1 for sw
678 * @max_xxx_size: for ucode uses
679 * @ct_kill_threshold: temperature threshold
a0ee74cf 680 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 681 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 682 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 683 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 684 */
5425e490 685struct iwl_hw_params {
f3f911d1
ZY
686 u8 max_txq_num;
687 u8 dma_chnl_num;
4ddbb7d0 688 u16 scd_bc_tbls_size;
a8e74e27 689 u32 tfd_size;
ec35cf2a
TW
690 u8 tx_chains_num;
691 u8 rx_chains_num;
692 u8 valid_tx_ant;
693 u8 valid_rx_ant;
5d08cd1d 694 u16 max_rxq_size;
ec35cf2a 695 u16 max_rxq_log;
2f301227 696 u32 rx_page_order;
141c43a3 697 u32 rx_wrt_ptr_reg;
5d08cd1d 698 u8 max_stations;
7aafef1c 699 u8 ht40_channel;
2c2f3b33 700 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
701 u32 max_inst_size;
702 u32 max_data_size;
703 u32 max_bsm_size;
704 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
705 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
706 /* for 1000, 6000 series and up */
a0ee74cf 707 u16 beacon_time_tsf_bits;
be5d56ed 708 u32 calib_init_cfg;
6d6a1afd 709 u32 calib_rt_cfg;
f0832f13 710 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
711};
712
5d08cd1d 713
5d08cd1d
CH
714/******************************************************************************
715 *
a33c2f47
EG
716 * Functions implemented in core module which are forward declared here
717 * for use by iwl-[4-5].c
5d08cd1d 718 *
a33c2f47
EG
719 * NOTE: The implementation of these functions are not hardware specific
720 * which is why they are in the core module files.
5d08cd1d
CH
721 *
722 * Naming convention --
a33c2f47 723 * iwl_ <-- Is part of iwlwifi
5d08cd1d 724 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
725 * iwl4965_bg_ <-- Called from work queue context
726 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
727 *
728 ****************************************************************************/
5b9f8cd3 729extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 730extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 731extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 732extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 733extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
734static inline int iwl_queue_used(const struct iwl_queue *q, int i)
735{
c8106d76 736 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
737 (i >= q->read_ptr && i < q->write_ptr) :
738 !(i < q->read_ptr && i >= q->write_ptr);
739}
740
741
742static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
743{
c8c24872
WYG
744 /*
745 * This is for init calibration result and scan command which
746 * required buffer > TFD_MAX_PAYLOAD_SIZE,
747 * the big buffer at end of command array
748 */
fd4abac5
TW
749 if (is_huge)
750 return q->n_window; /* must be power of 2 */
751
752 /* Otherwise, use normal size buffers */
753 return index & (q->n_window - 1);
754}
755
756
4ddbb7d0
TW
757struct iwl_dma_ptr {
758 dma_addr_t dma;
759 void *addr;
b481de9c
ZY
760 size_t size;
761};
762
b481de9c
ZY
763#define IWL_OPERATION_MODE_AUTO 0
764#define IWL_OPERATION_MODE_HT_ONLY 1
765#define IWL_OPERATION_MODE_MIXED 2
766#define IWL_OPERATION_MODE_20MHZ 3
767
3195cdb7
TW
768#define IWL_TX_CRC_SIZE 4
769#define IWL_TX_DELIMITER_SIZE 4
b481de9c 770
b481de9c 771#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 772
b481de9c 773/* Sensitivity and chain noise calibration */
b481de9c 774#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
775#define IWL4965_CAL_NUM_BEACONS 20
776#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
777#define MAXIMUM_ALLOWED_PATHLOSS 15
778
b481de9c
ZY
779#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
780
781#define MAX_FA_OFDM 50
782#define MIN_FA_OFDM 5
783#define MAX_FA_CCK 50
784#define MIN_FA_CCK 5
785
b481de9c
ZY
786#define AUTO_CORR_STEP_OFDM 1
787
b481de9c
ZY
788#define AUTO_CORR_STEP_CCK 3
789#define AUTO_CORR_MAX_TH_CCK 160
790
b481de9c
ZY
791#define NRG_DIFF 2
792#define NRG_STEP_CCK 2
793#define NRG_MARGIN 8
794#define MAX_NUMBER_CCK_NO_FA 100
795
796#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
797
798#define CHAIN_A 0
799#define CHAIN_B 1
800#define CHAIN_C 2
801#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
802#define ALL_BAND_FILTER 0xFF00
803#define IN_BAND_FILTER 0xFF
804#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
805
3195cdb7
TW
806#define NRG_NUM_PREV_STAT_L 20
807#define NUM_RX_CHAINS 3
808
bb8c093b 809enum iwl4965_false_alarm_state {
b481de9c
ZY
810 IWL_FA_TOO_MANY = 0,
811 IWL_FA_TOO_FEW = 1,
812 IWL_FA_GOOD_RANGE = 2,
813};
814
bb8c093b 815enum iwl4965_chain_noise_state {
b481de9c 816 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
817 IWL_CHAIN_NOISE_ACCUMULATE,
818 IWL_CHAIN_NOISE_CALIBRATED,
819 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
820};
821
bb8c093b 822enum iwl4965_calib_enabled_state {
b481de9c
ZY
823 IWL_CALIB_DISABLED = 0, /* must be 0 */
824 IWL_CALIB_ENABLED = 1,
825};
826
f69f42a6
TW
827
828/*
829 * enum iwl_calib
830 * defines the order in which results of initial calibrations
831 * should be sent to the runtime uCode
832 */
833enum iwl_calib {
834 IWL_CALIB_XTAL,
819500c5 835 IWL_CALIB_DC,
f69f42a6
TW
836 IWL_CALIB_LO,
837 IWL_CALIB_TX_IQ,
838 IWL_CALIB_TX_IQ_PERD,
201706ac 839 IWL_CALIB_BASE_BAND,
bf53f939 840 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
841 IWL_CALIB_MAX
842};
843
6e21f2c1
TW
844/* Opaque calibration results */
845struct iwl_calib_result {
846 void *buf;
847 size_t buf_len;
7c616cba
TW
848};
849
dbb983b7
RR
850enum ucode_type {
851 UCODE_NONE = 0,
852 UCODE_INIT,
853 UCODE_RT
854};
855
b481de9c 856/* Sensitivity calib data */
f0832f13 857struct iwl_sensitivity_data {
b481de9c
ZY
858 u32 auto_corr_ofdm;
859 u32 auto_corr_ofdm_mrc;
860 u32 auto_corr_ofdm_x1;
861 u32 auto_corr_ofdm_mrc_x1;
862 u32 auto_corr_cck;
863 u32 auto_corr_cck_mrc;
864
865 u32 last_bad_plcp_cnt_ofdm;
866 u32 last_fa_cnt_ofdm;
867 u32 last_bad_plcp_cnt_cck;
868 u32 last_fa_cnt_cck;
869
870 u32 nrg_curr_state;
871 u32 nrg_prev_state;
872 u32 nrg_value[10];
873 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
874 u32 nrg_silence_ref;
875 u32 nrg_energy_idx;
876 u32 nrg_silence_idx;
877 u32 nrg_th_cck;
878 s32 nrg_auto_corr_silence_diff;
879 u32 num_in_cck_no_fa;
880 u32 nrg_th_ofdm;
55036d66
WYG
881
882 u16 barker_corr_th_min;
883 u16 barker_corr_th_min_mrc;
884 u16 nrg_th_cca;
b481de9c
ZY
885};
886
887/* Chain noise (differential Rx gain) calib data */
f0832f13 888struct iwl_chain_noise_data {
04816448 889 u32 active_chains;
b481de9c
ZY
890 u32 chain_noise_a;
891 u32 chain_noise_b;
892 u32 chain_noise_c;
893 u32 chain_signal_a;
894 u32 chain_signal_b;
895 u32 chain_signal_c;
04816448 896 u16 beacon_count;
b481de9c
ZY
897 u8 disconn_array[NUM_RX_CHAINS];
898 u8 delta_gain_code[NUM_RX_CHAINS];
899 u8 radio_write;
04816448 900 u8 state;
b481de9c
ZY
901};
902
abceddb4
BC
903#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
904#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 905
20594eb0
WYG
906#define IWL_TRAFFIC_ENTRIES (256)
907#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 908
5d08cd1d
CH
909enum {
910 MEASUREMENT_READY = (1 << 0),
911 MEASUREMENT_ACTIVE = (1 << 1),
912};
913
0848e297
WYG
914enum iwl_nvm_type {
915 NVM_DEVICE_TYPE_EEPROM = 0,
916 NVM_DEVICE_TYPE_OTP,
917};
918
415e4993
WYG
919/*
920 * Two types of OTP memory access modes
921 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
922 * based on physical memory addressing
923 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
924 * based on logical memory addressing
925 */
926enum iwl_access_mode {
927 IWL_OTP_ACCESS_ABSOLUTE,
928 IWL_OTP_ACCESS_RELATIVE,
929};
65b7998a
WYG
930
931/**
932 * enum iwl_pa_type - Power Amplifier type
933 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
934 * @IWL_PA_INTERNAL: use Internal only
935 */
936enum iwl_pa_type {
937 IWL_PA_SYSTEM = 0,
740e7f51 938 IWL_PA_INTERNAL = 1,
65b7998a
WYG
939};
940
a83b9141
WYG
941/* interrupt statistics */
942struct isr_statistics {
943 u32 hw;
944 u32 sw;
6e6ebf4b 945 u32 err_code;
a83b9141
WYG
946 u32 sch;
947 u32 alive;
948 u32 rfkill;
949 u32 ctkill;
950 u32 wakeup;
951 u32 rx;
952 u32 rx_handlers[REPLY_MAX];
953 u32 tx;
954 u32 unhandled;
955};
5d08cd1d 956
91835ba4
WYG
957/* reply_tx_statistics (for _agn devices) */
958struct reply_tx_error_statistics {
959 u32 pp_delay;
960 u32 pp_few_bytes;
961 u32 pp_bt_prio;
962 u32 pp_quiet_period;
963 u32 pp_calc_ttak;
964 u32 int_crossed_retry;
965 u32 short_limit;
966 u32 long_limit;
967 u32 fifo_underrun;
968 u32 drain_flow;
969 u32 rfkill_flush;
970 u32 life_expire;
971 u32 dest_ps;
972 u32 host_abort;
973 u32 bt_retry;
974 u32 sta_invalid;
975 u32 frag_drop;
976 u32 tid_disable;
977 u32 fifo_flush;
978 u32 insuff_cf_poll;
979 u32 fail_hw_drop;
980 u32 sta_color_mismatch;
981 u32 unknown;
982};
983
814665fe
WYG
984/* reply_agg_tx_statistics (for _agn devices) */
985struct reply_agg_tx_error_statistics {
986 u32 underrun;
987 u32 bt_prio;
988 u32 few_bytes;
989 u32 abort;
990 u32 last_sent_ttl;
991 u32 last_sent_try;
992 u32 last_sent_bt_kill;
993 u32 scd_query;
994 u32 bad_crc32;
995 u32 response;
996 u32 dump_tx;
997 u32 delay_tx;
998 u32 unknown;
999};
1000
22fdf3c9
WYG
1001/* management statistics */
1002enum iwl_mgmt_stats {
1003 MANAGEMENT_ASSOC_REQ = 0,
1004 MANAGEMENT_ASSOC_RESP,
1005 MANAGEMENT_REASSOC_REQ,
1006 MANAGEMENT_REASSOC_RESP,
1007 MANAGEMENT_PROBE_REQ,
1008 MANAGEMENT_PROBE_RESP,
1009 MANAGEMENT_BEACON,
1010 MANAGEMENT_ATIM,
1011 MANAGEMENT_DISASSOC,
1012 MANAGEMENT_AUTH,
1013 MANAGEMENT_DEAUTH,
1014 MANAGEMENT_ACTION,
1015 MANAGEMENT_MAX,
1016};
1017/* control statistics */
1018enum iwl_ctrl_stats {
1019 CONTROL_BACK_REQ = 0,
1020 CONTROL_BACK,
1021 CONTROL_PSPOLL,
1022 CONTROL_RTS,
1023 CONTROL_CTS,
1024 CONTROL_ACK,
1025 CONTROL_CFEND,
1026 CONTROL_CFENDACK,
1027 CONTROL_MAX,
1028};
1029
1030struct traffic_stats {
5ed540ae 1031#ifdef CONFIG_IWLWIFI_DEBUGFS
22fdf3c9
WYG
1032 u32 mgmt[MANAGEMENT_MAX];
1033 u32 ctrl[CONTROL_MAX];
1034 u32 data_cnt;
1035 u64 data_bytes;
22fdf3c9 1036#endif
5ed540ae 1037};
22fdf3c9 1038
0924e519
WYG
1039/*
1040 * iwl_switch_rxon: "channel switch" structure
1041 *
1042 * @ switch_in_progress: channel switch in progress
1043 * @ channel: new channel
1044 */
1045struct iwl_switch_rxon {
1046 bool switch_in_progress;
1047 __le16 channel;
1048};
1049
a9e1cb6a
WYG
1050/*
1051 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
1052 * to perform continuous uCode event logging operation if enabled
1053 */
1054#define UCODE_TRACE_PERIOD (100)
1055
1056/*
1057 * iwl_event_log: current uCode event log position
1058 *
1059 * @ucode_trace: enable/disable ucode continuous trace timer
1060 * @num_wraps: how many times the event buffer wraps
1061 * @next_entry: the entry just before the next one that uCode would fill
1062 * @non_wraps_count: counter for no wrap detected when dump ucode events
1063 * @wraps_once_count: counter for wrap once detected when dump ucode events
1064 * @wraps_more_count: counter for wrap more than once detected
1065 * when dump ucode events
1066 */
1067struct iwl_event_log {
1068 bool ucode_trace;
1069 u32 num_wraps;
1070 u32 next_entry;
1071 int non_wraps_count;
1072 int wraps_once_count;
1073 int wraps_more_count;
1074};
1075
2be76703
WYG
1076/*
1077 * host interrupt timeout value
1078 * used with setting interrupt coalescing timer
1079 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1080 *
1081 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1082 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1083 */
1084#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1085#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1086#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1087#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1088#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1089#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1090
3e4fb5fa
TAN
1091/*
1092 * This is the threshold value of plcp error rate per 100mSecs. It is
1093 * used to set and check for the validity of plcp_delta.
1094 */
680788ac 1095#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1096#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1097#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1098#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1099#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1100#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1101
8a472da4
WYG
1102#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1103#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1104
22de94de
SG
1105/* TX queue watchdog timeouts in mSecs */
1106#define IWL_DEF_WD_TIMEOUT (2000)
1107#define IWL_LONG_WD_TIMEOUT (10000)
1108#define IWL_MAX_WD_TIMEOUT (120000)
b74e31a9 1109
bee008b7
WYG
1110/* BT Antenna Coupling Threshold (dB) */
1111#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1112
491bc292
WYG
1113/* Firmware reload counter and Timestamp */
1114#define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */
1115#define IWL_MAX_CONTINUE_RELOAD_CNT 4
1116
1117
a93e7973
WYG
1118enum iwl_reset {
1119 IWL_RF_RESET = 0,
1120 IWL_FW_RESET,
8a472da4
WYG
1121 IWL_MAX_FORCE_RESET,
1122};
1123
1124struct iwl_force_reset {
1125 int reset_request_count;
1126 int reset_success_count;
1127 int reset_reject_count;
1128 unsigned long reset_duration;
1129 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1130};
1131
a0ee74cf
WYG
1132/* extend beacon time format bit shifting */
1133/*
1134 * for _3945 devices
1135 * bits 31:24 - extended
1136 * bits 23:0 - interval
1137 */
1138#define IWL3945_EXT_BEACON_TIME_POS 24
1139/*
1140 * for _agn devices
1141 * bits 31:22 - extended
1142 * bits 21:0 - interval
1143 */
1144#define IWLAGN_EXT_BEACON_TIME_POS 22
1145
7194207c
JB
1146/**
1147 * struct iwl_notification_wait - notification wait entry
1148 * @list: list head for global list
1149 * @fn: function called with the notification
1150 * @cmd: command ID
1151 *
1152 * This structure is not used directly, to wait for a
1153 * notification declare it on the stack, and call
1154 * iwlagn_init_notification_wait() with appropriate
1155 * parameters. Then do whatever will cause the ucode
1156 * to notify the driver, and to wait for that then
1157 * call iwlagn_wait_notification().
1158 *
1159 * Each notification is one-shot. If at some point we
1160 * need to support multi-shot notifications (which
1161 * can't be allocated on the stack) we need to modify
1162 * the code for them.
1163 */
1164struct iwl_notification_wait {
1165 struct list_head list;
1166
1167 void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt);
1168
1169 u8 cmd;
1170 bool triggered;
1171};
1172
246ed355
JB
1173enum iwl_rxon_context_id {
1174 IWL_RXON_CTX_BSS,
ece9c4ee 1175 IWL_RXON_CTX_PAN,
246ed355
JB
1176
1177 NUM_IWL_RXON_CTX
1178};
1179
1180struct iwl_rxon_context {
8bd413e6 1181 struct ieee80211_vif *vif;
e72f368b
JB
1182
1183 const u8 *ac_to_fifo;
1184 const u8 *ac_to_queue;
1185 u8 mcast_queue;
1186
763cc3bf
JB
1187 /*
1188 * We could use the vif to indicate active, but we
1189 * also need it to be active during disabling when
1190 * we already removed the vif for type setting.
1191 */
1192 bool always_active, is_active;
1193
2295c66b
JB
1194 bool ht_need_multiple_chains;
1195
246ed355 1196 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1197
1198 u32 interface_modes, exclusive_interface_modes;
1199 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1200
246ed355
JB
1201 /*
1202 * We declare this const so it can only be
1203 * changed via explicit cast within the
1204 * routines that actually update the physical
1205 * hardware.
1206 */
1207 const struct iwl_rxon_cmd active;
1208 struct iwl_rxon_cmd staging;
1209
1210 struct iwl_rxon_time_cmd timing;
a194e324 1211
8dfdb9d5
JB
1212 struct iwl_qos_info qos_data;
1213
2995bafa 1214 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1215
1216 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1217 u8 qos_cmd;
c10afb6e
JB
1218 u8 wep_key_cmd;
1219
1220 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1221 u8 key_mapping_keys;
770e13bd
JB
1222
1223 __le32 station_flags;
7e6a5886
JB
1224
1225 struct {
1226 bool non_gf_sta_present;
1227 u8 protection;
1228 bool enabled, is_40mhz;
1229 u8 extension_chan_offset;
1230 } ht;
246ed355
JB
1231};
1232
266af4c7
JB
1233enum iwl_scan_type {
1234 IWL_SCAN_NORMAL,
1235 IWL_SCAN_RADIO_RESET,
1236 IWL_SCAN_OFFCH_TX,
1237};
1238
c79dd5b5 1239struct iwl_priv {
5d08cd1d
CH
1240
1241 /* ieee device used by generic ieee processing code */
1242 struct ieee80211_hw *hw;
1243 struct ieee80211_channel *ieee_channels;
1244 struct ieee80211_rate *ieee_rates;
82b9a121 1245 struct iwl_cfg *cfg;
5d08cd1d
CH
1246
1247 /* temporary frame storage list */
1248 struct list_head free_frames;
1249 int frames_count;
1250
8318d78a 1251 enum ieee80211_band band;
2f301227 1252 int alloc_rxb_page;
5d08cd1d 1253
c79dd5b5 1254 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1255 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1256
8318d78a 1257 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1258
5d08cd1d 1259 /* spectrum measurement report caching */
2aa6ab86 1260 struct iwl_spectrum_notification measure_report;
5d08cd1d 1261 u8 measurement_status;
81963d68 1262
5d08cd1d
CH
1263 /* ucode beacon time */
1264 u32 ucode_beacon_time;
a13d276f 1265 int missed_beacon_threshold;
5d08cd1d 1266
a85d7cca
JB
1267 /* track IBSS manager (last beacon) status */
1268 u32 ibss_manager;
1269
410f2bb3
SG
1270 /* jiffies when last recovery from statistics was performed */
1271 unsigned long rx_statistics_jiffies;
3e4fb5fa 1272
a93e7973 1273 /* force reset */
8a472da4 1274 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1275
491bc292
WYG
1276 /* firmware reload counter and timestamp */
1277 unsigned long reload_jiffies;
1278 int reload_count;
1279
5a2a780c 1280 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1281 * Access via channel # using indirect index array */
bf85ea4f 1282 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1283 u8 channel_count; /* # of channels */
1284
5d08cd1d
CH
1285 /* thermal calibration */
1286 s32 temperature; /* degrees Kelvin */
1287 s32 last_temperature;
1288
7c616cba 1289 /* init calibration results */
6e21f2c1 1290 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1291
5d08cd1d 1292 /* Scan related variables */
5d08cd1d 1293 unsigned long scan_start;
5d08cd1d 1294 unsigned long scan_start_tsf;
811ecc99 1295 void *scan_cmd;
00700ee0 1296 enum ieee80211_band scan_band;
1ecf9fc1 1297 struct cfg80211_scan_request *scan_request;
f84b29ec 1298 struct ieee80211_vif *scan_vif;
266af4c7 1299 enum iwl_scan_type scan_type;
76eff18b
TW
1300 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1301 u8 mgmt_tx_ant;
5d08cd1d
CH
1302
1303 /* spinlock */
1304 spinlock_t lock; /* protect general shared data */
1305 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1306 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1307 struct mutex mutex;
d2dfe6df 1308 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1309
1310 /* basic pci-network driver stuff */
1311 struct pci_dev *pci_dev;
1312
1313 /* pci hardware address support */
1314 void __iomem *hw_base;
b661c819
TW
1315 u32 hw_rev;
1316 u32 hw_wa_rev;
1317 u8 rev_id;
5d08cd1d 1318
246ed355
JB
1319 /* microcode/device supports multiple contexts */
1320 u8 valid_contexts;
1321
13bb9483
JB
1322 /* command queue number */
1323 u8 cmd_queue;
1324
c10afb6e
JB
1325 /* max number of station keys */
1326 u8 sta_key_max_num;
1327
c6fa17ed
WYG
1328 /* EEPROM MAC addresses */
1329 struct mac_address addresses[2];
1330
5d08cd1d 1331 /* uCode images, save to reload in case of failure */
b08dfd04 1332 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1333 u32 ucode_ver; /* version of ucode, copy of
1334 iwl_ucode.ver */
5d08cd1d
CH
1335 struct fw_desc ucode_code; /* runtime inst */
1336 struct fw_desc ucode_data; /* runtime data original */
1337 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1338 struct fw_desc ucode_init; /* initialization inst */
1339 struct fw_desc ucode_init_data; /* initialization data */
1340 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1341 enum ucode_type ucode_type;
1342 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1343 char firmware_name[25];
5d08cd1d 1344
246ed355 1345 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1346
0924e519
WYG
1347 struct iwl_switch_rxon switch_rxon;
1348
5d08cd1d 1349 /* 1st responses from initialize and runtime uCode images.
5a2a780c 1350 * _agn's initialize alive response contains some calibration data. */
885ba202
TW
1351 struct iwl_init_alive_resp card_alive_init;
1352 struct iwl_alive_resp card_alive;
5d08cd1d 1353
5d08cd1d 1354 u16 active_rate;
5d08cd1d 1355
5d08cd1d 1356 u8 start_calib;
f0832f13
EG
1357 struct iwl_sensitivity_data sensitivity_data;
1358 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1359 bool enhance_sensitivity_table;
5d08cd1d 1360 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1361 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1362
fad95bf5 1363 struct iwl_ht_config current_ht_config;
5d08cd1d 1364
5d08cd1d 1365 /* Rate scaling data */
5d08cd1d
CH
1366 u8 retry_rate;
1367
1368 wait_queue_head_t wait_command_queue;
1369
1370 int activity_timer_active;
1371
1372 /* Rx and Tx DMA processing queues */
a55360e4 1373 struct iwl_rx_queue rxq;
88804e2b 1374 struct iwl_tx_queue *txq;
5d08cd1d 1375 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1376 struct iwl_dma_ptr kw; /* keep warm address */
1377 struct iwl_dma_ptr scd_bc_tbls;
1378
5d08cd1d
CH
1379 u32 scd_base_addr; /* scheduler sram base address */
1380
1381 unsigned long status;
5d08cd1d 1382
19758bef 1383 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1384 struct traffic_stats tx_stats;
1385 struct traffic_stats rx_stats;
19758bef 1386
a83b9141
WYG
1387 /* counts interrupts */
1388 struct isr_statistics isr_stats;
1389
5da4b55f 1390 struct iwl_power_mgr power_data;
3ad3b92a 1391 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1392
5d08cd1d 1393 /* context information */
59c02b41 1394 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
5d08cd1d 1395
9c5ac091
RC
1396 /* station table variables */
1397
1398 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1399 spinlock_t sta_lock;
1400 int num_stations;
6def9761 1401 struct iwl_station_entry stations[IWL_STATION_COUNT];
80fb47a1 1402 unsigned long ucode_key_table;
5d08cd1d 1403
e4e72fb4
JB
1404 /* queue refcounts */
1405#define IWL_MAX_HW_QUEUES 32
1406 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1407 /* for each AC */
1408 atomic_t queue_stop_count[4];
1409
5d08cd1d 1410 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1411 u8 is_open;
5d08cd1d
CH
1412
1413 u8 mac80211_registered;
5d08cd1d 1414
af6b8ee3 1415 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1416 u8 *eeprom;
0848e297 1417 int nvm_device_type;
073d3f5f 1418 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1419
05c914fe 1420 enum nl80211_iftype iw_mode;
5d08cd1d 1421
5d08cd1d 1422 /* Last Rx'd beacon timestamp */
3109ece1 1423 u64 timestamp;
5d08cd1d 1424
ee525d13
JB
1425 union {
1426#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1427 struct {
1428 void *shared_virt;
1429 dma_addr_t shared_phys;
1430
1431 struct delayed_work thermal_periodic;
1432 struct delayed_work rfkill_poll;
1433
1434 struct iwl3945_notif_statistics statistics;
d73e4923 1435#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK
1436 struct iwl3945_notif_statistics accum_statistics;
1437 struct iwl3945_notif_statistics delta_statistics;
1438 struct iwl3945_notif_statistics max_delta;
1439#endif
ee525d13
JB
1440
1441 u32 sta_supp_rates;
e99f168c
JB
1442 int last_rx_rssi; /* From Rx packet statistics */
1443
1444 /* Rx'd packet timing information */
1445 u32 last_beacon_time;
1446 u64 last_tsf;
67d613ae
JB
1447
1448 /*
1449 * each calibration channel group in the
1450 * EEPROM has a derived clip setting for
1451 * each rate.
1452 */
1453 const struct iwl3945_clip_group clip_groups[5];
1454
ee525d13 1455 } _3945;
a4c8b2a6
JB
1456#endif
1457#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1458 struct {
1459 /* INT ICT Table */
1460 __le32 *ict_tbl;
1461 void *ict_tbl_vir;
1462 dma_addr_t ict_tbl_dma;
1463 dma_addr_t aligned_ict_tbl_dma;
1464 int ict_index;
1465 u32 inta;
1466 bool use_ict;
d5a0ffa3
WYG
1467 /*
1468 * reporting the number of tids has AGG on. 0 means
1469 * no AGGREGATION
1470 */
1471 u8 agg_tids_count;
05d57520
JB
1472
1473 struct iwl_rx_phy_res last_phy_res;
1474 bool last_phy_res_valid;
a15707d8
RC
1475
1476 struct completion firmware_loading_complete;
a2064b7a 1477
b2e640d4
JB
1478 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1479 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
f3aebeee 1480
6a822d06
WYG
1481 /*
1482 * chain noise reset and gain commands are the
1483 * two extra calibration commands follows the standard
1484 * phy calibration commands
1485 */
1486 u8 phy_calib_chain_noise_reset_cmd;
1487 u8 phy_calib_chain_noise_gain_cmd;
1488
f3aebeee 1489 struct iwl_notif_statistics statistics;
7980fba5 1490 struct iwl_bt_notif_statistics statistics_bt;
91835ba4
WYG
1491 /* counts reply_tx error */
1492 struct reply_tx_error_statistics reply_tx_stats;
814665fe 1493 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
f3aebeee
WYG
1494#ifdef CONFIG_IWLWIFI_DEBUGFS
1495 struct iwl_notif_statistics accum_statistics;
1496 struct iwl_notif_statistics delta_statistics;
1497 struct iwl_notif_statistics max_delta;
7980fba5
WYG
1498 struct iwl_bt_notif_statistics accum_statistics_bt;
1499 struct iwl_bt_notif_statistics delta_statistics_bt;
1500 struct iwl_bt_notif_statistics max_delta_bt;
f3aebeee 1501#endif
7194207c
JB
1502
1503 /* notification wait support */
1504 struct list_head notif_waits;
1505 spinlock_t notif_wait_lock;
1506 wait_queue_head_t notif_waitq;
9b9190d9
JB
1507
1508 /* remain-on-channel offload support */
1509 struct ieee80211_channel *hw_roc_channel;
1510 struct delayed_work hw_roc_work;
1511 enum nl80211_channel_type hw_roc_chantype;
1512 int hw_roc_duration;
266af4c7
JB
1513
1514 struct sk_buff *offchan_tx_skb;
1515 int offchan_tx_timeout;
1516 struct ieee80211_channel *offchan_tx_chan;
a4c8b2a6 1517 } _agn;
ee525d13
JB
1518#endif
1519 };
1520
22bf59a0 1521 /* bt coex */
f21dd005 1522 u8 bt_enable_flag;
da5dbb97 1523 u8 bt_status;
66e863a5 1524 u8 bt_traffic_load, last_bt_traffic_load;
f37837c9 1525 bool bt_ch_announce;
bee008b7
WYG
1526 bool bt_full_concurrent;
1527 bool bt_ant_couple_ok;
fbba9410
WYG
1528 __le32 kill_ack_mask;
1529 __le32 kill_cts_mask;
1530 __le16 bt_valid;
22bf59a0
WYG
1531 u16 bt_on_thresh;
1532 u16 bt_duration;
1533 u16 dynamic_frag_thresh;
bee008b7 1534 u8 bt_ci_compliance;
9e4afc21
JB
1535 struct work_struct bt_traffic_change_work;
1536
5425e490 1537 struct iwl_hw_params hw_params;
4ddbb7d0 1538
40cefda9 1539 u32 inta_mask;
5d08cd1d 1540
5d08cd1d
CH
1541 struct workqueue_struct *workqueue;
1542
5d08cd1d 1543 struct work_struct restart;
5d08cd1d
CH
1544 struct work_struct scan_completed;
1545 struct work_struct rx_replenish;
5d08cd1d 1546 struct work_struct abort_scan;
12e934dc 1547
5d08cd1d 1548 struct work_struct beacon_update;
76d04815 1549 struct iwl_rxon_context *beacon_ctx;
12e934dc 1550 struct sk_buff *beacon_skb;
76d04815 1551
a28027cd
WYG
1552 struct work_struct tt_work;
1553 struct work_struct ct_enter;
1554 struct work_struct ct_exit;
88be0264 1555 struct work_struct start_internal_scan;
65550636 1556 struct work_struct tx_flush;
bee008b7 1557 struct work_struct bt_full_concurrency;
fbba9410 1558 struct work_struct bt_runtime_config;
5d08cd1d
CH
1559
1560 struct tasklet_struct irq_tasklet;
1561
1562 struct delayed_work init_alive_start;
1563 struct delayed_work alive_start;
5d08cd1d 1564 struct delayed_work scan_check;
4a8a4322 1565
630fe9b6
TW
1566 /* TX Power */
1567 s8 tx_power_user_lmt;
dc1b0973 1568 s8 tx_power_device_lmt;
ae16fc3c 1569 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
a25a66ac 1570 s8 tx_power_next;
5d08cd1d 1571
5d08cd1d 1572
d08853a3 1573#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1574 /* debugging info */
3d816c77
RC
1575 u32 debug_level; /* per device debugging will override global
1576 iwl_debug_level if set */
d73e4923 1577#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1578#ifdef CONFIG_IWLWIFI_DEBUGFS
1579 /* debugfs */
20594eb0
WYG
1580 u16 tx_traffic_idx;
1581 u16 rx_traffic_idx;
1582 u8 *tx_traffic;
1583 u8 *rx_traffic;
4c84a8f1
JB
1584 struct dentry *debugfs_dir;
1585 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1586 bool disable_ht40;
712b6cf5 1587#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1588
1589 struct work_struct txpower_work;
445c2dff
TW
1590 u32 disable_sens_cal;
1591 u32 disable_chain_noise_cal;
203566f3 1592 u32 disable_tx_power_cal;
16e727e8 1593 struct work_struct run_time_calib_work;
5d08cd1d 1594 struct timer_list statistics_periodic;
a9e1cb6a 1595 struct timer_list ucode_trace;
22de94de 1596 struct timer_list watchdog;
086ed117 1597 bool hw_ready;
a9e1cb6a
WYG
1598
1599 struct iwl_event_log event_log;
5ed540ae
WYG
1600
1601 struct led_classdev led;
1602 unsigned long blink_on, blink_off;
1603 bool led_registered;
c79dd5b5 1604}; /*iwl_priv */
5d08cd1d 1605
36470749
RR
1606static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1607{
1608 set_bit(txq_id, &priv->txq_ctx_active_msk);
1609}
1610
1611static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1612{
1613 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1614}
1615
994d31f7 1616#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1617/*
1618 * iwl_get_debug_level: Return active debug level for device
1619 *
1620 * Using sysfs it is possible to set per device debug level. This debug
1621 * level will be used if set, otherwise the global debug level which can be
1622 * set via module parameter is used.
1623 */
1624static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1625{
1626 if (priv->debug_level)
1627 return priv->debug_level;
1628 else
1629 return iwl_debug_level;
1630}
a332f8d6 1631#else
3d816c77
RC
1632static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1633{
1634 return iwl_debug_level;
1635}
a332f8d6
TW
1636#endif
1637
1638
a332f8d6
TW
1639static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1640 int txq_id, int idx)
1641{
ff0d91c3 1642 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1643 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1644 txb[idx].skb->data;
a332f8d6
TW
1645 return NULL;
1646}
a332f8d6 1647
246ed355
JB
1648static inline struct iwl_rxon_context *
1649iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1650{
1651 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1652
1653 return vif_priv->ctx;
1654}
1655
1656#define for_each_context(priv, ctx) \
1657 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1658 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1659 if (priv->valid_contexts & BIT(ctx->ctxid))
1660
1661static inline int iwl_is_associated(struct iwl_priv *priv,
1662 enum iwl_rxon_context_id ctxid)
1663{
1664 return (priv->contexts[ctxid].active.filter_flags &
1665 RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1666}
1667
1668static inline int iwl_is_any_associated(struct iwl_priv *priv)
1669{
1670 return iwl_is_associated(priv, IWL_RXON_CTX_BSS);
1671}
a332f8d6 1672
246ed355 1673static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
5d08cd1d 1674{
246ed355 1675 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
5d08cd1d
CH
1676}
1677
bf85ea4f 1678static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1679{
1680 if (ch_info == NULL)
1681 return 0;
1682 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1683}
1684
bf85ea4f 1685static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1686{
1687 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1688}
1689
bf85ea4f 1690static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1691{
8318d78a 1692 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1693}
1694
bf85ea4f 1695static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1696{
8318d78a 1697 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1698}
1699
bf85ea4f 1700static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1701{
1702 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1703}
1704
bf85ea4f 1705static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1706{
1707 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1708}
1709
64a76b50
ZY
1710static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1711{
1712 __free_pages(page, priv->hw_params.rx_page_order);
1713 priv->alloc_rxb_page--;
1714}
1715
1716static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1717{
1718 free_pages(page, priv->hw_params.rx_page_order);
1719 priv->alloc_rxb_page--;
1720}
be1f3ab6 1721#endif /* __iwl_dev_h__ */