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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
fcd427bb | 26 | /* |
3e0d4cb1 | 27 | * Please use this file (iwl-dev.h) for driver implementation definitions. |
5a36ba0e | 28 | * Please use iwl-commands.h for uCode API definitions. |
fcd427bb BC |
29 | */ |
30 | ||
be1f3ab6 EG |
31 | #ifndef __iwl_dev_h__ |
32 | #define __iwl_dev_h__ | |
b481de9c | 33 | |
5d08cd1d CH |
34 | #include <linux/pci.h> /* for struct pci_device_id */ |
35 | #include <linux/kernel.h> | |
7194207c | 36 | #include <linux/wait.h> |
5ed540ae | 37 | #include <linux/leds.h> |
5d08cd1d CH |
38 | #include <net/ieee80211_radiotap.h> |
39 | ||
6bc913bd | 40 | #include "iwl-eeprom.h" |
6f83eaa1 | 41 | #include "iwl-csr.h" |
5d08cd1d | 42 | #include "iwl-prph.h" |
dbb6654c | 43 | #include "iwl-fh.h" |
0a6857e7 | 44 | #include "iwl-debug.h" |
b744cb79 | 45 | #include "iwl-agn-hw.h" |
ab53d8af | 46 | #include "iwl-led.h" |
5da4b55f | 47 | #include "iwl-power.h" |
e227ceac | 48 | #include "iwl-agn-rs.h" |
0975cc8f | 49 | #include "iwl-agn-tt.h" |
5d08cd1d | 50 | |
be663ab6 WYG |
51 | #define U32_PAD(n) ((4-(n))&0x3) |
52 | ||
672639de WYG |
53 | struct iwl_tx_queue; |
54 | ||
099b40b7 | 55 | /* CT-KILL constants */ |
672639de WYG |
56 | #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */ |
57 | #define CT_KILL_THRESHOLD 114 /* in Celsius */ | |
58 | #define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ | |
4bf775cd | 59 | |
5d08cd1d CH |
60 | /* Default noise level to report when noise measurement is not available. |
61 | * This may be because we're: | |
62 | * 1) Not associated (4965, no beacon statistics being sent to driver) | |
63 | * 2) Scanning (noise measurement does not apply to associated channel) | |
64 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
65 | * Use default noise value of -127 ... this is below the range of measurable | |
66 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
67 | * Also, -127 works better than 0 when averaging frames with/without | |
68 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
69 | * always negative ... using a negative value as the default keeps all | |
70 | * averages within an s8's (used in some apps) range of negative values. */ | |
71 | #define IWL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
72 | ||
5d08cd1d CH |
73 | /* |
74 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
75 | * Per spec: | |
76 | * a value of 0 means RTS on all data/management packets | |
77 | * a value > max MSDU size means no RTS | |
78 | * else RTS for data/management frames where MPDU is larger | |
79 | * than RTS value. | |
80 | */ | |
81 | #define DEFAULT_RTS_THRESHOLD 2347U | |
82 | #define MIN_RTS_THRESHOLD 0U | |
83 | #define MAX_RTS_THRESHOLD 2347U | |
84 | #define MAX_MSDU_SIZE 2304U | |
85 | #define MAX_MPDU_SIZE 2346U | |
86 | #define DEFAULT_BEACON_INTERVAL 100U | |
87 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
88 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
89 | ||
a55360e4 | 90 | struct iwl_rx_mem_buffer { |
2f301227 ZY |
91 | dma_addr_t page_dma; |
92 | struct page *page; | |
5d08cd1d CH |
93 | struct list_head list; |
94 | }; | |
95 | ||
2f301227 ZY |
96 | #define rxb_addr(r) page_address(r->page) |
97 | ||
c2acea8e JB |
98 | /* defined below */ |
99 | struct iwl_device_cmd; | |
100 | ||
101 | struct iwl_cmd_meta { | |
102 | /* only for SYNC commands, iff the reply skb is wanted */ | |
103 | struct iwl_host_cmd *source; | |
104 | /* | |
105 | * only for ASYNC commands | |
106 | * (which is somewhat stupid -- look at iwl-sta.c for instance | |
107 | * which duplicates a bunch of code because the callback isn't | |
108 | * invoked for SYNC commands, if it were and its result passed | |
109 | * through it would be simpler...) | |
110 | */ | |
5696aea6 JB |
111 | void (*callback)(struct iwl_priv *priv, |
112 | struct iwl_device_cmd *cmd, | |
2f301227 | 113 | struct iwl_rx_packet *pkt); |
c2acea8e JB |
114 | |
115 | /* The CMD_SIZE_HUGE flag bit indicates that the command | |
116 | * structure is stored at the end of the shared queue memory. */ | |
117 | u32 flags; | |
118 | ||
2e724443 FT |
119 | DEFINE_DMA_UNMAP_ADDR(mapping); |
120 | DEFINE_DMA_UNMAP_LEN(len); | |
c2acea8e JB |
121 | }; |
122 | ||
5d08cd1d CH |
123 | /* |
124 | * Generic queue structure | |
125 | * | |
126 | * Contains common data for Rx and Tx queues | |
127 | */ | |
443cfd45 | 128 | struct iwl_queue { |
5d08cd1d CH |
129 | int n_bd; /* number of BDs in this queue */ |
130 | int write_ptr; /* 1-st empty entry (index) host_w*/ | |
131 | int read_ptr; /* last used entry (index) host_r*/ | |
b74e31a9 | 132 | /* use for monitoring and recovering the stuck queue */ |
5d08cd1d CH |
133 | dma_addr_t dma_addr; /* physical addr for BD's */ |
134 | int n_window; /* safe queue window */ | |
135 | u32 id; | |
136 | int low_mark; /* low watermark, resume queue if free | |
137 | * space more than this */ | |
138 | int high_mark; /* high watermark, stop queue if free | |
139 | * space less than this */ | |
a839cf69 | 140 | }; |
5d08cd1d | 141 | |
bc47279f | 142 | /* One for each TFD */ |
8567c63e | 143 | struct iwl_tx_info { |
ff0d91c3 | 144 | struct sk_buff *skb; |
c90cbbbd | 145 | struct iwl_rxon_context *ctx; |
5d08cd1d CH |
146 | }; |
147 | ||
148 | /** | |
16466903 | 149 | * struct iwl_tx_queue - Tx Queue for DMA |
bc47279f BC |
150 | * @q: generic Rx/Tx queue descriptor |
151 | * @bd: base of circular buffer of TFDs | |
c2acea8e JB |
152 | * @cmd: array of command/TX buffer pointers |
153 | * @meta: array of meta data for each command/tx buffer | |
bc47279f BC |
154 | * @dma_addr_cmd: physical address of cmd/tx buffer array |
155 | * @txb: array of per-TFD driver data | |
22de94de | 156 | * @time_stamp: time (in jiffies) of last read_ptr change |
bc47279f BC |
157 | * @need_update: indicates need to update read/write index |
158 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
5d08cd1d | 159 | * |
bc47279f BC |
160 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame |
161 | * descriptors) and required locking structures. | |
5d08cd1d | 162 | */ |
188cf6c7 SO |
163 | #define TFD_TX_CMD_SLOTS 256 |
164 | #define TFD_CMD_SLOTS 32 | |
165 | ||
16466903 | 166 | struct iwl_tx_queue { |
443cfd45 | 167 | struct iwl_queue q; |
59606ffa | 168 | void *tfds; |
c2acea8e JB |
169 | struct iwl_device_cmd **cmd; |
170 | struct iwl_cmd_meta *meta; | |
8567c63e | 171 | struct iwl_tx_info *txb; |
22de94de | 172 | unsigned long time_stamp; |
3fd07a1e TW |
173 | u8 need_update; |
174 | u8 sched_retry; | |
175 | u8 active; | |
176 | u8 swq_id; | |
5d08cd1d CH |
177 | }; |
178 | ||
179 | #define IWL_NUM_SCAN_RATES (2) | |
180 | ||
5d08cd1d CH |
181 | /* |
182 | * One for each channel, holds all channel setup data | |
183 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
184 | * with one another! | |
185 | */ | |
bf85ea4f | 186 | struct iwl_channel_info { |
073d3f5f | 187 | struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */ |
7aafef1c WYG |
188 | struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for |
189 | * HT40 channel */ | |
5d08cd1d CH |
190 | |
191 | u8 channel; /* channel number */ | |
192 | u8 flags; /* flags copied from EEPROM */ | |
193 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
fcd427bb | 194 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ |
5d08cd1d CH |
195 | s8 min_power; /* always 0 */ |
196 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
197 | ||
198 | u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */ | |
199 | u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */ | |
8318d78a | 200 | enum ieee80211_band band; |
5d08cd1d | 201 | |
7aafef1c WYG |
202 | /* HT40 channel info */ |
203 | s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
7aafef1c WYG |
204 | u8 ht40_flags; /* flags copied from EEPROM */ |
205 | u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ | |
5d08cd1d CH |
206 | }; |
207 | ||
751ca305 | 208 | #define IWL_TX_FIFO_BK 0 /* shared */ |
edc1a3a0 | 209 | #define IWL_TX_FIFO_BE 1 |
751ca305 | 210 | #define IWL_TX_FIFO_VI 2 /* shared */ |
edc1a3a0 | 211 | #define IWL_TX_FIFO_VO 3 |
751ca305 JB |
212 | #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK |
213 | #define IWL_TX_FIFO_BE_IPAN 4 | |
214 | #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI | |
215 | #define IWL_TX_FIFO_VO_IPAN 5 | |
edc1a3a0 | 216 | #define IWL_TX_FIFO_UNUSED -1 |
5d08cd1d | 217 | |
01a7e084 RC |
218 | /* Minimum number of queues. MAX_NUM is defined in hw specific files. |
219 | * Set the minimum to accommodate the 4 standard TX queues, 1 command | |
220 | * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */ | |
221 | #define IWL_MIN_NUM_QUEUES 10 | |
5d08cd1d | 222 | |
bd35f150 | 223 | /* |
13bb9483 | 224 | * Command queue depends on iPAN support. |
bd35f150 | 225 | */ |
13bb9483 JB |
226 | #define IWL_DEFAULT_CMD_QUEUE_NUM 4 |
227 | #define IWL_IPAN_CMD_QUEUE_NUM 9 | |
bd35f150 | 228 | |
751ca305 JB |
229 | /* |
230 | * This queue number is required for proper operation | |
231 | * because the ucode will stop/start the scheduler as | |
232 | * required. | |
233 | */ | |
234 | #define IWL_IPAN_MCAST_QUEUE 8 | |
235 | ||
5d08cd1d CH |
236 | #define IEEE80211_DATA_LEN 2304 |
237 | #define IEEE80211_4ADDR_LEN 30 | |
238 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
239 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
240 | ||
fcab423d | 241 | struct iwl_frame { |
5d08cd1d CH |
242 | union { |
243 | struct ieee80211_hdr frame; | |
4bf64efd | 244 | struct iwl_tx_beacon_cmd beacon; |
5d08cd1d CH |
245 | u8 raw[IEEE80211_FRAME_LEN]; |
246 | u8 cmd[360]; | |
247 | } u; | |
248 | struct list_head list; | |
249 | }; | |
250 | ||
5d08cd1d CH |
251 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
252 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
253 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
254 | ||
255 | enum { | |
c587de0b TW |
256 | CMD_SYNC = 0, |
257 | CMD_SIZE_NORMAL = 0, | |
258 | CMD_NO_SKB = 0, | |
5d08cd1d | 259 | CMD_SIZE_HUGE = (1 << 0), |
5d08cd1d | 260 | CMD_ASYNC = (1 << 1), |
5d08cd1d | 261 | CMD_WANT_SKB = (1 << 2), |
3598e177 | 262 | CMD_MAPPED = (1 << 3), |
5d08cd1d CH |
263 | }; |
264 | ||
c8c24872 | 265 | #define DEF_CMD_PAYLOAD_SIZE 320 |
bd68fb6f | 266 | |
bc47279f | 267 | /** |
c2acea8e | 268 | * struct iwl_device_cmd |
bc47279f BC |
269 | * |
270 | * For allocation of the command and tx queues, this establishes the overall | |
271 | * size of the largest command we send to uCode, except for a scan command | |
272 | * (which is relatively huge; space is allocated separately). | |
273 | */ | |
c2acea8e | 274 | struct iwl_device_cmd { |
857485c0 | 275 | struct iwl_cmd_header hdr; /* uCode API */ |
5d08cd1d | 276 | union { |
5d08cd1d CH |
277 | u32 flags; |
278 | u8 val8; | |
279 | u16 val16; | |
280 | u32 val32; | |
83d527d9 | 281 | struct iwl_tx_cmd tx; |
c8c24872 WYG |
282 | struct iwl6000_channel_switch_cmd chswitch; |
283 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | |
ba2d3587 ED |
284 | } __packed cmd; |
285 | } __packed; | |
5d08cd1d | 286 | |
c2acea8e JB |
287 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) |
288 | ||
3257e5d4 | 289 | |
857485c0 | 290 | struct iwl_host_cmd { |
5d08cd1d | 291 | const void *data; |
2f301227 | 292 | unsigned long reply_page; |
5696aea6 JB |
293 | void (*callback)(struct iwl_priv *priv, |
294 | struct iwl_device_cmd *cmd, | |
2f301227 | 295 | struct iwl_rx_packet *pkt); |
c2acea8e JB |
296 | u32 flags; |
297 | u16 len; | |
298 | u8 id; | |
5d08cd1d CH |
299 | }; |
300 | ||
5d08cd1d CH |
301 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 |
302 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
303 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
304 | ||
305 | /** | |
a55360e4 | 306 | * struct iwl_rx_queue - Rx queue |
df833b1d | 307 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) |
d5b25c90 | 308 | * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) |
5d08cd1d CH |
309 | * @read: Shared index to newest available Rx buffer |
310 | * @write: Shared index to oldest written Rx packet | |
311 | * @free_count: Number of pre-allocated buffers in rx_free | |
312 | * @rx_free: list of free SKBs for use | |
313 | * @rx_used: List of Rx buffers with no SKB | |
314 | * @need_update: flag to indicate we need to update read/write index | |
df833b1d RC |
315 | * @rb_stts: driver's pointer to receive buffer status |
316 | * @rb_stts_dma: bus address of receive buffer status | |
5d08cd1d | 317 | * |
a55360e4 | 318 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers |
5d08cd1d | 319 | */ |
a55360e4 | 320 | struct iwl_rx_queue { |
5d08cd1d | 321 | __le32 *bd; |
d5b25c90 | 322 | dma_addr_t bd_dma; |
a55360e4 TW |
323 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; |
324 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
5d08cd1d CH |
325 | u32 read; |
326 | u32 write; | |
327 | u32 free_count; | |
4752c93c | 328 | u32 write_actual; |
5d08cd1d CH |
329 | struct list_head rx_free; |
330 | struct list_head rx_used; | |
331 | int need_update; | |
8d86422a WT |
332 | struct iwl_rb_status *rb_stts; |
333 | dma_addr_t rb_stts_dma; | |
5d08cd1d CH |
334 | spinlock_t lock; |
335 | }; | |
336 | ||
337 | #define IWL_SUPPORTED_RATES_IE_LEN 8 | |
338 | ||
5d08cd1d CH |
339 | #define MAX_TID_COUNT 9 |
340 | ||
341 | #define IWL_INVALID_RATE 0xFF | |
342 | #define IWL_INVALID_VALUE -1 | |
343 | ||
bc47279f | 344 | /** |
6def9761 | 345 | * struct iwl_ht_agg -- aggregation status while waiting for block-ack |
bc47279f BC |
346 | * @txq_id: Tx queue used for Tx attempt |
347 | * @frame_count: # frames attempted by Tx command | |
348 | * @wait_for_ba: Expect block-ack before next Tx reply | |
349 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window | |
350 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window | |
351 | * @bitmap1: High order, one bit for each frame pending ACK in Tx window | |
352 | * @rate_n_flags: Rate at which Tx was attempted | |
353 | * | |
354 | * If REPLY_TX indicates that aggregation was attempted, driver must wait | |
355 | * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info | |
356 | * until block ack arrives. | |
357 | */ | |
6def9761 | 358 | struct iwl_ht_agg { |
5d08cd1d CH |
359 | u16 txq_id; |
360 | u16 frame_count; | |
361 | u16 wait_for_ba; | |
362 | u16 start_idx; | |
fe01b477 | 363 | u64 bitmap; |
5d08cd1d | 364 | u32 rate_n_flags; |
fe01b477 RR |
365 | #define IWL_AGG_OFF 0 |
366 | #define IWL_AGG_ON 1 | |
367 | #define IWL_EMPTYING_HW_QUEUE_ADDBA 2 | |
368 | #define IWL_EMPTYING_HW_QUEUE_DELBA 3 | |
369 | u8 state; | |
c8823ec1 | 370 | u8 tx_fifo; |
5d08cd1d | 371 | }; |
fe01b477 | 372 | |
5d08cd1d | 373 | |
6def9761 | 374 | struct iwl_tid_data { |
f862a236 | 375 | u16 seq_number; /* agn only */ |
fe01b477 | 376 | u16 tfds_in_queue; |
6def9761 | 377 | struct iwl_ht_agg agg; |
5d08cd1d CH |
378 | }; |
379 | ||
6def9761 | 380 | struct iwl_hw_key { |
97359d12 | 381 | u32 cipher; |
5d08cd1d | 382 | int keylen; |
0211ddda | 383 | u8 keyidx; |
5d08cd1d CH |
384 | u8 key[32]; |
385 | }; | |
386 | ||
a78fe754 | 387 | union iwl_ht_rate_supp { |
5d08cd1d CH |
388 | u16 rates; |
389 | struct { | |
390 | u8 siso_rate; | |
391 | u8 mimo_rate; | |
392 | }; | |
393 | }; | |
394 | ||
172c1d11 WYG |
395 | #define CFG_HT_RX_AMPDU_FACTOR_8K (0x0) |
396 | #define CFG_HT_RX_AMPDU_FACTOR_16K (0x1) | |
397 | #define CFG_HT_RX_AMPDU_FACTOR_32K (0x2) | |
398 | #define CFG_HT_RX_AMPDU_FACTOR_64K (0x3) | |
399 | #define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K | |
400 | #define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K | |
401 | #define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K | |
bcc693a1 WYG |
402 | |
403 | /* | |
404 | * Maximal MPDU density for TX aggregation | |
405 | * 4 - 2us density | |
406 | * 5 - 4us density | |
407 | * 6 - 8us density | |
408 | * 7 - 16us density | |
409 | */ | |
172c1d11 | 410 | #define CFG_HT_MPDU_DENSITY_2USEC (0x4) |
bcc693a1 | 411 | #define CFG_HT_MPDU_DENSITY_4USEC (0x5) |
172c1d11 WYG |
412 | #define CFG_HT_MPDU_DENSITY_8USEC (0x6) |
413 | #define CFG_HT_MPDU_DENSITY_16USEC (0x7) | |
bcc693a1 | 414 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC |
172c1d11 WYG |
415 | #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC |
416 | #define CFG_HT_MPDU_DENSITY_MIN (0x1) | |
5d08cd1d | 417 | |
fad95bf5 | 418 | struct iwl_ht_config { |
02bb1bea | 419 | bool single_chain_sufficient; |
ba37a3d0 | 420 | enum ieee80211_smps_mode smps; /* current smps mode */ |
5d08cd1d | 421 | }; |
5d08cd1d | 422 | |
5d08cd1d | 423 | /* QoS structures */ |
1ff50bda | 424 | struct iwl_qos_info { |
5d08cd1d | 425 | int qos_active; |
1ff50bda | 426 | struct iwl_qosparam_cmd def_qos_parm; |
5d08cd1d | 427 | }; |
5d08cd1d | 428 | |
fe6b23dd RC |
429 | /* |
430 | * Structure should be accessed with sta_lock held. When station addition | |
431 | * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only | |
432 | * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock | |
433 | * held. | |
434 | */ | |
6def9761 | 435 | struct iwl_station_entry { |
133636de | 436 | struct iwl_addsta_cmd sta; |
6def9761 | 437 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
dcef732c | 438 | u8 used, ctxid; |
6def9761 | 439 | struct iwl_hw_key keyinfo; |
fe6b23dd | 440 | struct iwl_link_quality_cmd *lq; |
5d08cd1d CH |
441 | }; |
442 | ||
fd1af15d | 443 | struct iwl_station_priv_common { |
238d781d | 444 | struct iwl_rxon_context *ctx; |
fd1af15d JB |
445 | u8 sta_id; |
446 | }; | |
447 | ||
8d9698b3 RC |
448 | /* |
449 | * iwl_station_priv: Driver's private station information | |
450 | * | |
451 | * When mac80211 creates a station it reserves some space (hw->sta_data_size) | |
452 | * in the structure for use by driver. This structure is places in that | |
453 | * space. | |
8d9698b3 RC |
454 | */ |
455 | struct iwl_station_priv { | |
fd1af15d | 456 | struct iwl_station_priv_common common; |
8d9698b3 | 457 | struct iwl_lq_sta lq_sta; |
6ab10ff8 JB |
458 | atomic_t pending_frames; |
459 | bool client; | |
460 | bool asleep; | |
7b090687 | 461 | u8 max_agg_bufsize; |
8d9698b3 RC |
462 | }; |
463 | ||
fd1af15d JB |
464 | /** |
465 | * struct iwl_vif_priv - driver's private per-interface information | |
466 | * | |
467 | * When mac80211 allocates a virtual interface, it can allocate | |
468 | * space for us to put data into. | |
469 | */ | |
470 | struct iwl_vif_priv { | |
246ed355 | 471 | struct iwl_rxon_context *ctx; |
fd1af15d JB |
472 | u8 ibss_bssid_sta_id; |
473 | }; | |
474 | ||
5d08cd1d CH |
475 | /* one for each uCode image (inst/data, boot/init/runtime) */ |
476 | struct fw_desc { | |
477 | void *v_addr; /* access by driver */ | |
478 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
479 | u32 len; /* bytes */ | |
480 | }; | |
481 | ||
dd7a2509 | 482 | /* v1/v2 uCode file layout */ |
cc0f555d JS |
483 | struct iwl_ucode_header { |
484 | __le32 ver; /* major/minor/API/serial */ | |
485 | union { | |
486 | struct { | |
487 | __le32 inst_size; /* bytes of runtime code */ | |
488 | __le32 data_size; /* bytes of runtime data */ | |
489 | __le32 init_size; /* bytes of init code */ | |
490 | __le32 init_data_size; /* bytes of init data */ | |
491 | __le32 boot_size; /* bytes of bootstrap code */ | |
492 | u8 data[0]; /* in same order as sizes */ | |
493 | } v1; | |
494 | struct { | |
495 | __le32 build; /* build number */ | |
496 | __le32 inst_size; /* bytes of runtime code */ | |
497 | __le32 data_size; /* bytes of runtime data */ | |
498 | __le32 init_size; /* bytes of init code */ | |
499 | __le32 init_data_size; /* bytes of init data */ | |
500 | __le32 boot_size; /* bytes of bootstrap code */ | |
501 | u8 data[0]; /* in same order as sizes */ | |
502 | } v2; | |
503 | } u; | |
5d08cd1d CH |
504 | }; |
505 | ||
dd7a2509 JB |
506 | /* |
507 | * new TLV uCode file layout | |
508 | * | |
509 | * The new TLV file format contains TLVs, that each specify | |
510 | * some piece of data. To facilitate "groups", for example | |
511 | * different instruction image with different capabilities, | |
512 | * bundled with the same init image, an alternative mechanism | |
513 | * is provided: | |
514 | * When the alternative field is 0, that means that the item | |
515 | * is always valid. When it is non-zero, then it is only | |
516 | * valid in conjunction with items of the same alternative, | |
517 | * in which case the driver (user) selects one alternative | |
518 | * to use. | |
519 | */ | |
520 | ||
521 | enum iwl_ucode_tlv_type { | |
522 | IWL_UCODE_TLV_INVALID = 0, /* unused */ | |
523 | IWL_UCODE_TLV_INST = 1, | |
524 | IWL_UCODE_TLV_DATA = 2, | |
525 | IWL_UCODE_TLV_INIT = 3, | |
526 | IWL_UCODE_TLV_INIT_DATA = 4, | |
527 | IWL_UCODE_TLV_BOOT = 5, | |
528 | IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */ | |
ece9c4ee | 529 | IWL_UCODE_TLV_PAN = 7, |
b2e640d4 JB |
530 | IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8, |
531 | IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, | |
532 | IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10, | |
533 | IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11, | |
534 | IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12, | |
535 | IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13, | |
c8312fac | 536 | IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14, |
6a822d06 | 537 | IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, |
dd7a2509 JB |
538 | }; |
539 | ||
540 | struct iwl_ucode_tlv { | |
541 | __le16 type; /* see above */ | |
542 | __le16 alternative; /* see comment */ | |
543 | __le32 length; /* not including type/length fields */ | |
544 | u8 data[0]; | |
ba2d3587 | 545 | } __packed; |
dd7a2509 JB |
546 | |
547 | #define IWL_TLV_UCODE_MAGIC 0x0a4c5749 | |
548 | ||
549 | struct iwl_tlv_ucode_header { | |
550 | /* | |
551 | * The TLV style ucode header is distinguished from | |
552 | * the v1/v2 style header by first four bytes being | |
553 | * zero, as such is an invalid combination of | |
554 | * major/minor/API/serial versions. | |
555 | */ | |
556 | __le32 zero; | |
557 | __le32 magic; | |
558 | u8 human_readable[64]; | |
559 | __le32 ver; /* major/minor/API/serial */ | |
560 | __le32 build; | |
561 | __le64 alternatives; /* bitmask of valid alternatives */ | |
562 | /* | |
563 | * The data contained herein has a TLV layout, | |
564 | * see above for the TLV header and types. | |
565 | * Note that each TLV is padded to a length | |
566 | * that is a multiple of 4 for alignment. | |
567 | */ | |
568 | u8 data[0]; | |
569 | }; | |
570 | ||
f0832f13 EG |
571 | struct iwl_sensitivity_ranges { |
572 | u16 min_nrg_cck; | |
573 | u16 max_nrg_cck; | |
574 | ||
575 | u16 nrg_th_cck; | |
576 | u16 nrg_th_ofdm; | |
577 | ||
578 | u16 auto_corr_min_ofdm; | |
579 | u16 auto_corr_min_ofdm_mrc; | |
580 | u16 auto_corr_min_ofdm_x1; | |
581 | u16 auto_corr_min_ofdm_mrc_x1; | |
582 | ||
583 | u16 auto_corr_max_ofdm; | |
584 | u16 auto_corr_max_ofdm_mrc; | |
585 | u16 auto_corr_max_ofdm_x1; | |
586 | u16 auto_corr_max_ofdm_mrc_x1; | |
587 | ||
588 | u16 auto_corr_max_cck; | |
589 | u16 auto_corr_max_cck_mrc; | |
590 | u16 auto_corr_min_cck; | |
591 | u16 auto_corr_min_cck_mrc; | |
55036d66 WYG |
592 | |
593 | u16 barker_corr_th_min; | |
594 | u16 barker_corr_th_min_mrc; | |
595 | u16 nrg_th_cca; | |
f0832f13 EG |
596 | }; |
597 | ||
099b40b7 | 598 | |
b5047f78 TW |
599 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
600 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
601 | ||
602 | ||
bc47279f | 603 | /** |
5425e490 | 604 | * struct iwl_hw_params |
bc47279f | 605 | * @max_txq_num: Max # Tx queues supported |
f3f911d1 | 606 | * @dma_chnl_num: Number of Tx DMA/FIFO channels |
4ddbb7d0 | 607 | * @scd_bc_tbls_size: size of scheduler byte count tables |
a8e74e27 | 608 | * @tfd_size: TFD size |
099b40b7 RR |
609 | * @tx/rx_chains_num: Number of TX/RX chains |
610 | * @valid_tx/rx_ant: usable antennas | |
bc47279f | 611 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) |
bc47279f | 612 | * @max_rxq_log: Log-base-2 of max_rxq_size |
2f301227 | 613 | * @rx_page_order: Rx buffer page order |
141c43a3 | 614 | * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR |
bc47279f | 615 | * @max_stations: |
7aafef1c | 616 | * @ht40_channel: is 40MHz width possible in band 2.4 |
099b40b7 RR |
617 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) |
618 | * @sw_crypto: 0 for hw, 1 for sw | |
619 | * @max_xxx_size: for ucode uses | |
620 | * @ct_kill_threshold: temperature threshold | |
a0ee74cf | 621 | * @beacon_time_tsf_bits: number of valid tsf bits for beacon time |
a96a27f9 | 622 | * @calib_init_cfg: setup initial calibrations for the hw |
6d6a1afd | 623 | * @calib_rt_cfg: setup runtime calibrations for the hw |
f0832f13 | 624 | * @struct iwl_sensitivity_ranges: range of sensitivity values |
bc47279f | 625 | */ |
5425e490 | 626 | struct iwl_hw_params { |
f3f911d1 ZY |
627 | u8 max_txq_num; |
628 | u8 dma_chnl_num; | |
4ddbb7d0 | 629 | u16 scd_bc_tbls_size; |
a8e74e27 | 630 | u32 tfd_size; |
ec35cf2a TW |
631 | u8 tx_chains_num; |
632 | u8 rx_chains_num; | |
633 | u8 valid_tx_ant; | |
634 | u8 valid_rx_ant; | |
5d08cd1d | 635 | u16 max_rxq_size; |
ec35cf2a | 636 | u16 max_rxq_log; |
2f301227 | 637 | u32 rx_page_order; |
141c43a3 | 638 | u32 rx_wrt_ptr_reg; |
5d08cd1d | 639 | u8 max_stations; |
7aafef1c | 640 | u8 ht40_channel; |
2c2f3b33 | 641 | u8 max_beacon_itrvl; /* in 1024 ms */ |
099b40b7 RR |
642 | u32 max_inst_size; |
643 | u32 max_data_size; | |
099b40b7 | 644 | u32 ct_kill_threshold; /* value in hw-dependent units */ |
672639de WYG |
645 | u32 ct_kill_exit_threshold; /* value in hw-dependent units */ |
646 | /* for 1000, 6000 series and up */ | |
a0ee74cf | 647 | u16 beacon_time_tsf_bits; |
be5d56ed | 648 | u32 calib_init_cfg; |
6d6a1afd | 649 | u32 calib_rt_cfg; |
f0832f13 | 650 | const struct iwl_sensitivity_ranges *sens; |
5d08cd1d CH |
651 | }; |
652 | ||
5d08cd1d | 653 | |
5d08cd1d CH |
654 | /****************************************************************************** |
655 | * | |
a33c2f47 EG |
656 | * Functions implemented in core module which are forward declared here |
657 | * for use by iwl-[4-5].c | |
5d08cd1d | 658 | * |
a33c2f47 EG |
659 | * NOTE: The implementation of these functions are not hardware specific |
660 | * which is why they are in the core module files. | |
5d08cd1d CH |
661 | * |
662 | * Naming convention -- | |
a33c2f47 | 663 | * iwl_ <-- Is part of iwlwifi |
5d08cd1d | 664 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) |
5d08cd1d CH |
665 | * |
666 | ****************************************************************************/ | |
5b9f8cd3 | 667 | extern void iwl_update_chain_flags(struct iwl_priv *priv); |
a33c2f47 | 668 | extern const u8 iwl_bcast_addr[ETH_ALEN]; |
b3bbacb7 | 669 | extern int iwl_rxq_stop(struct iwl_priv *priv); |
da1bc453 | 670 | extern void iwl_txq_ctx_stop(struct iwl_priv *priv); |
443cfd45 | 671 | extern int iwl_queue_space(const struct iwl_queue *q); |
fd4abac5 TW |
672 | static inline int iwl_queue_used(const struct iwl_queue *q, int i) |
673 | { | |
c8106d76 | 674 | return q->write_ptr >= q->read_ptr ? |
fd4abac5 TW |
675 | (i >= q->read_ptr && i < q->write_ptr) : |
676 | !(i < q->read_ptr && i >= q->write_ptr); | |
677 | } | |
678 | ||
679 | ||
680 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge) | |
681 | { | |
c8c24872 WYG |
682 | /* |
683 | * This is for init calibration result and scan command which | |
684 | * required buffer > TFD_MAX_PAYLOAD_SIZE, | |
685 | * the big buffer at end of command array | |
686 | */ | |
fd4abac5 TW |
687 | if (is_huge) |
688 | return q->n_window; /* must be power of 2 */ | |
689 | ||
690 | /* Otherwise, use normal size buffers */ | |
691 | return index & (q->n_window - 1); | |
692 | } | |
693 | ||
694 | ||
4ddbb7d0 TW |
695 | struct iwl_dma_ptr { |
696 | dma_addr_t dma; | |
697 | void *addr; | |
b481de9c ZY |
698 | size_t size; |
699 | }; | |
700 | ||
b481de9c ZY |
701 | #define IWL_OPERATION_MODE_AUTO 0 |
702 | #define IWL_OPERATION_MODE_HT_ONLY 1 | |
703 | #define IWL_OPERATION_MODE_MIXED 2 | |
704 | #define IWL_OPERATION_MODE_20MHZ 3 | |
705 | ||
3195cdb7 TW |
706 | #define IWL_TX_CRC_SIZE 4 |
707 | #define IWL_TX_DELIMITER_SIZE 4 | |
b481de9c | 708 | |
b481de9c | 709 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 |
b481de9c | 710 | |
b481de9c | 711 | /* Sensitivity and chain noise calibration */ |
b481de9c | 712 | #define INITIALIZATION_VALUE 0xFFFF |
d8c07e7a | 713 | #define IWL_CAL_NUM_BEACONS 16 |
b481de9c ZY |
714 | #define MAXIMUM_ALLOWED_PATHLOSS 15 |
715 | ||
b481de9c ZY |
716 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 |
717 | ||
718 | #define MAX_FA_OFDM 50 | |
719 | #define MIN_FA_OFDM 5 | |
720 | #define MAX_FA_CCK 50 | |
721 | #define MIN_FA_CCK 5 | |
722 | ||
b481de9c ZY |
723 | #define AUTO_CORR_STEP_OFDM 1 |
724 | ||
b481de9c ZY |
725 | #define AUTO_CORR_STEP_CCK 3 |
726 | #define AUTO_CORR_MAX_TH_CCK 160 | |
727 | ||
b481de9c ZY |
728 | #define NRG_DIFF 2 |
729 | #define NRG_STEP_CCK 2 | |
730 | #define NRG_MARGIN 8 | |
731 | #define MAX_NUMBER_CCK_NO_FA 100 | |
732 | ||
733 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
734 | ||
735 | #define CHAIN_A 0 | |
736 | #define CHAIN_B 1 | |
737 | #define CHAIN_C 2 | |
738 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
739 | #define ALL_BAND_FILTER 0xFF00 | |
740 | #define IN_BAND_FILTER 0xFF | |
741 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
742 | ||
3195cdb7 TW |
743 | #define NRG_NUM_PREV_STAT_L 20 |
744 | #define NUM_RX_CHAINS 3 | |
745 | ||
3240cab3 | 746 | enum iwlagn_false_alarm_state { |
b481de9c ZY |
747 | IWL_FA_TOO_MANY = 0, |
748 | IWL_FA_TOO_FEW = 1, | |
749 | IWL_FA_GOOD_RANGE = 2, | |
750 | }; | |
751 | ||
3240cab3 | 752 | enum iwlagn_chain_noise_state { |
b481de9c | 753 | IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
04816448 GE |
754 | IWL_CHAIN_NOISE_ACCUMULATE, |
755 | IWL_CHAIN_NOISE_CALIBRATED, | |
756 | IWL_CHAIN_NOISE_DONE, | |
b481de9c ZY |
757 | }; |
758 | ||
f69f42a6 TW |
759 | |
760 | /* | |
761 | * enum iwl_calib | |
762 | * defines the order in which results of initial calibrations | |
763 | * should be sent to the runtime uCode | |
764 | */ | |
765 | enum iwl_calib { | |
766 | IWL_CALIB_XTAL, | |
819500c5 | 767 | IWL_CALIB_DC, |
f69f42a6 TW |
768 | IWL_CALIB_LO, |
769 | IWL_CALIB_TX_IQ, | |
770 | IWL_CALIB_TX_IQ_PERD, | |
201706ac | 771 | IWL_CALIB_BASE_BAND, |
bf53f939 | 772 | IWL_CALIB_TEMP_OFFSET, |
f69f42a6 TW |
773 | IWL_CALIB_MAX |
774 | }; | |
775 | ||
6e21f2c1 TW |
776 | /* Opaque calibration results */ |
777 | struct iwl_calib_result { | |
778 | void *buf; | |
779 | size_t buf_len; | |
7c616cba TW |
780 | }; |
781 | ||
dbb983b7 RR |
782 | enum ucode_type { |
783 | UCODE_NONE = 0, | |
784 | UCODE_INIT, | |
785 | UCODE_RT | |
786 | }; | |
787 | ||
b481de9c | 788 | /* Sensitivity calib data */ |
f0832f13 | 789 | struct iwl_sensitivity_data { |
b481de9c ZY |
790 | u32 auto_corr_ofdm; |
791 | u32 auto_corr_ofdm_mrc; | |
792 | u32 auto_corr_ofdm_x1; | |
793 | u32 auto_corr_ofdm_mrc_x1; | |
794 | u32 auto_corr_cck; | |
795 | u32 auto_corr_cck_mrc; | |
796 | ||
797 | u32 last_bad_plcp_cnt_ofdm; | |
798 | u32 last_fa_cnt_ofdm; | |
799 | u32 last_bad_plcp_cnt_cck; | |
800 | u32 last_fa_cnt_cck; | |
801 | ||
802 | u32 nrg_curr_state; | |
803 | u32 nrg_prev_state; | |
804 | u32 nrg_value[10]; | |
805 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; | |
806 | u32 nrg_silence_ref; | |
807 | u32 nrg_energy_idx; | |
808 | u32 nrg_silence_idx; | |
809 | u32 nrg_th_cck; | |
810 | s32 nrg_auto_corr_silence_diff; | |
811 | u32 num_in_cck_no_fa; | |
812 | u32 nrg_th_ofdm; | |
55036d66 WYG |
813 | |
814 | u16 barker_corr_th_min; | |
815 | u16 barker_corr_th_min_mrc; | |
816 | u16 nrg_th_cca; | |
b481de9c ZY |
817 | }; |
818 | ||
819 | /* Chain noise (differential Rx gain) calib data */ | |
f0832f13 | 820 | struct iwl_chain_noise_data { |
04816448 | 821 | u32 active_chains; |
b481de9c ZY |
822 | u32 chain_noise_a; |
823 | u32 chain_noise_b; | |
824 | u32 chain_noise_c; | |
825 | u32 chain_signal_a; | |
826 | u32 chain_signal_b; | |
827 | u32 chain_signal_c; | |
04816448 | 828 | u16 beacon_count; |
b481de9c ZY |
829 | u8 disconn_array[NUM_RX_CHAINS]; |
830 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
831 | u8 radio_write; | |
04816448 | 832 | u8 state; |
b481de9c ZY |
833 | }; |
834 | ||
abceddb4 BC |
835 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
836 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
b481de9c | 837 | |
20594eb0 WYG |
838 | #define IWL_TRAFFIC_ENTRIES (256) |
839 | #define IWL_TRAFFIC_ENTRY_SIZE (64) | |
5d08cd1d | 840 | |
5d08cd1d CH |
841 | enum { |
842 | MEASUREMENT_READY = (1 << 0), | |
843 | MEASUREMENT_ACTIVE = (1 << 1), | |
844 | }; | |
845 | ||
0848e297 WYG |
846 | enum iwl_nvm_type { |
847 | NVM_DEVICE_TYPE_EEPROM = 0, | |
848 | NVM_DEVICE_TYPE_OTP, | |
849 | }; | |
850 | ||
415e4993 WYG |
851 | /* |
852 | * Two types of OTP memory access modes | |
853 | * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode, | |
854 | * based on physical memory addressing | |
855 | * IWL_OTP_ACCESS_RELATIVE - relative address mode, | |
856 | * based on logical memory addressing | |
857 | */ | |
858 | enum iwl_access_mode { | |
859 | IWL_OTP_ACCESS_ABSOLUTE, | |
860 | IWL_OTP_ACCESS_RELATIVE, | |
861 | }; | |
65b7998a WYG |
862 | |
863 | /** | |
864 | * enum iwl_pa_type - Power Amplifier type | |
865 | * @IWL_PA_SYSTEM: based on uCode configuration | |
65b7998a WYG |
866 | * @IWL_PA_INTERNAL: use Internal only |
867 | */ | |
868 | enum iwl_pa_type { | |
869 | IWL_PA_SYSTEM = 0, | |
740e7f51 | 870 | IWL_PA_INTERNAL = 1, |
65b7998a WYG |
871 | }; |
872 | ||
a83b9141 WYG |
873 | /* interrupt statistics */ |
874 | struct isr_statistics { | |
875 | u32 hw; | |
876 | u32 sw; | |
6e6ebf4b | 877 | u32 err_code; |
a83b9141 WYG |
878 | u32 sch; |
879 | u32 alive; | |
880 | u32 rfkill; | |
881 | u32 ctkill; | |
882 | u32 wakeup; | |
883 | u32 rx; | |
884 | u32 rx_handlers[REPLY_MAX]; | |
885 | u32 tx; | |
886 | u32 unhandled; | |
887 | }; | |
5d08cd1d | 888 | |
91835ba4 WYG |
889 | /* reply_tx_statistics (for _agn devices) */ |
890 | struct reply_tx_error_statistics { | |
891 | u32 pp_delay; | |
892 | u32 pp_few_bytes; | |
893 | u32 pp_bt_prio; | |
894 | u32 pp_quiet_period; | |
895 | u32 pp_calc_ttak; | |
896 | u32 int_crossed_retry; | |
897 | u32 short_limit; | |
898 | u32 long_limit; | |
899 | u32 fifo_underrun; | |
900 | u32 drain_flow; | |
901 | u32 rfkill_flush; | |
902 | u32 life_expire; | |
903 | u32 dest_ps; | |
904 | u32 host_abort; | |
905 | u32 bt_retry; | |
906 | u32 sta_invalid; | |
907 | u32 frag_drop; | |
908 | u32 tid_disable; | |
909 | u32 fifo_flush; | |
910 | u32 insuff_cf_poll; | |
911 | u32 fail_hw_drop; | |
912 | u32 sta_color_mismatch; | |
913 | u32 unknown; | |
914 | }; | |
915 | ||
814665fe WYG |
916 | /* reply_agg_tx_statistics (for _agn devices) */ |
917 | struct reply_agg_tx_error_statistics { | |
918 | u32 underrun; | |
919 | u32 bt_prio; | |
920 | u32 few_bytes; | |
921 | u32 abort; | |
922 | u32 last_sent_ttl; | |
923 | u32 last_sent_try; | |
924 | u32 last_sent_bt_kill; | |
925 | u32 scd_query; | |
926 | u32 bad_crc32; | |
927 | u32 response; | |
928 | u32 dump_tx; | |
929 | u32 delay_tx; | |
930 | u32 unknown; | |
931 | }; | |
932 | ||
22fdf3c9 WYG |
933 | /* management statistics */ |
934 | enum iwl_mgmt_stats { | |
935 | MANAGEMENT_ASSOC_REQ = 0, | |
936 | MANAGEMENT_ASSOC_RESP, | |
937 | MANAGEMENT_REASSOC_REQ, | |
938 | MANAGEMENT_REASSOC_RESP, | |
939 | MANAGEMENT_PROBE_REQ, | |
940 | MANAGEMENT_PROBE_RESP, | |
941 | MANAGEMENT_BEACON, | |
942 | MANAGEMENT_ATIM, | |
943 | MANAGEMENT_DISASSOC, | |
944 | MANAGEMENT_AUTH, | |
945 | MANAGEMENT_DEAUTH, | |
946 | MANAGEMENT_ACTION, | |
947 | MANAGEMENT_MAX, | |
948 | }; | |
949 | /* control statistics */ | |
950 | enum iwl_ctrl_stats { | |
951 | CONTROL_BACK_REQ = 0, | |
952 | CONTROL_BACK, | |
953 | CONTROL_PSPOLL, | |
954 | CONTROL_RTS, | |
955 | CONTROL_CTS, | |
956 | CONTROL_ACK, | |
957 | CONTROL_CFEND, | |
958 | CONTROL_CFENDACK, | |
959 | CONTROL_MAX, | |
960 | }; | |
961 | ||
962 | struct traffic_stats { | |
5ed540ae | 963 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
22fdf3c9 WYG |
964 | u32 mgmt[MANAGEMENT_MAX]; |
965 | u32 ctrl[CONTROL_MAX]; | |
966 | u32 data_cnt; | |
967 | u64 data_bytes; | |
22fdf3c9 | 968 | #endif |
5ed540ae | 969 | }; |
22fdf3c9 | 970 | |
0924e519 WYG |
971 | /* |
972 | * iwl_switch_rxon: "channel switch" structure | |
973 | * | |
974 | * @ switch_in_progress: channel switch in progress | |
975 | * @ channel: new channel | |
976 | */ | |
977 | struct iwl_switch_rxon { | |
978 | bool switch_in_progress; | |
979 | __le16 channel; | |
980 | }; | |
981 | ||
a9e1cb6a WYG |
982 | /* |
983 | * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds | |
984 | * to perform continuous uCode event logging operation if enabled | |
985 | */ | |
986 | #define UCODE_TRACE_PERIOD (100) | |
987 | ||
988 | /* | |
989 | * iwl_event_log: current uCode event log position | |
990 | * | |
991 | * @ucode_trace: enable/disable ucode continuous trace timer | |
992 | * @num_wraps: how many times the event buffer wraps | |
993 | * @next_entry: the entry just before the next one that uCode would fill | |
994 | * @non_wraps_count: counter for no wrap detected when dump ucode events | |
995 | * @wraps_once_count: counter for wrap once detected when dump ucode events | |
996 | * @wraps_more_count: counter for wrap more than once detected | |
997 | * when dump ucode events | |
998 | */ | |
999 | struct iwl_event_log { | |
1000 | bool ucode_trace; | |
1001 | u32 num_wraps; | |
1002 | u32 next_entry; | |
1003 | int non_wraps_count; | |
1004 | int wraps_once_count; | |
1005 | int wraps_more_count; | |
1006 | }; | |
1007 | ||
2be76703 WYG |
1008 | /* |
1009 | * host interrupt timeout value | |
1010 | * used with setting interrupt coalescing timer | |
1011 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | |
1012 | * | |
1013 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | |
1014 | * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs | |
1015 | */ | |
1016 | #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) | |
1017 | #define IWL_HOST_INT_TIMEOUT_DEF (0x40) | |
1018 | #define IWL_HOST_INT_TIMEOUT_MIN (0x0) | |
1019 | #define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) | |
1020 | #define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) | |
1021 | #define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) | |
1022 | ||
3e4fb5fa TAN |
1023 | /* |
1024 | * This is the threshold value of plcp error rate per 100mSecs. It is | |
1025 | * used to set and check for the validity of plcp_delta. | |
1026 | */ | |
680788ac | 1027 | #define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1) |
3e4fb5fa TAN |
1028 | #define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50) |
1029 | #define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100) | |
6c3872e1 | 1030 | #define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200) |
3e4fb5fa | 1031 | #define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255) |
680788ac | 1032 | #define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0) |
3e4fb5fa | 1033 | |
8a472da4 WYG |
1034 | #define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3) |
1035 | #define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5) | |
1036 | ||
22de94de SG |
1037 | /* TX queue watchdog timeouts in mSecs */ |
1038 | #define IWL_DEF_WD_TIMEOUT (2000) | |
1039 | #define IWL_LONG_WD_TIMEOUT (10000) | |
1040 | #define IWL_MAX_WD_TIMEOUT (120000) | |
b74e31a9 | 1041 | |
bee008b7 WYG |
1042 | /* BT Antenna Coupling Threshold (dB) */ |
1043 | #define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35) | |
1044 | ||
491bc292 WYG |
1045 | /* Firmware reload counter and Timestamp */ |
1046 | #define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */ | |
1047 | #define IWL_MAX_CONTINUE_RELOAD_CNT 4 | |
1048 | ||
1049 | ||
a93e7973 WYG |
1050 | enum iwl_reset { |
1051 | IWL_RF_RESET = 0, | |
1052 | IWL_FW_RESET, | |
8a472da4 WYG |
1053 | IWL_MAX_FORCE_RESET, |
1054 | }; | |
1055 | ||
1056 | struct iwl_force_reset { | |
1057 | int reset_request_count; | |
1058 | int reset_success_count; | |
1059 | int reset_reject_count; | |
1060 | unsigned long reset_duration; | |
1061 | unsigned long last_force_reset_jiffies; | |
a93e7973 WYG |
1062 | }; |
1063 | ||
a0ee74cf | 1064 | /* extend beacon time format bit shifting */ |
a0ee74cf WYG |
1065 | /* |
1066 | * for _agn devices | |
1067 | * bits 31:22 - extended | |
1068 | * bits 21:0 - interval | |
1069 | */ | |
1070 | #define IWLAGN_EXT_BEACON_TIME_POS 22 | |
1071 | ||
7194207c JB |
1072 | /** |
1073 | * struct iwl_notification_wait - notification wait entry | |
1074 | * @list: list head for global list | |
1075 | * @fn: function called with the notification | |
1076 | * @cmd: command ID | |
1077 | * | |
1078 | * This structure is not used directly, to wait for a | |
1079 | * notification declare it on the stack, and call | |
1080 | * iwlagn_init_notification_wait() with appropriate | |
1081 | * parameters. Then do whatever will cause the ucode | |
1082 | * to notify the driver, and to wait for that then | |
1083 | * call iwlagn_wait_notification(). | |
1084 | * | |
1085 | * Each notification is one-shot. If at some point we | |
1086 | * need to support multi-shot notifications (which | |
1087 | * can't be allocated on the stack) we need to modify | |
1088 | * the code for them. | |
1089 | */ | |
1090 | struct iwl_notification_wait { | |
1091 | struct list_head list; | |
1092 | ||
1093 | void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt); | |
1094 | ||
1095 | u8 cmd; | |
1096 | bool triggered; | |
1097 | }; | |
1098 | ||
246ed355 JB |
1099 | enum iwl_rxon_context_id { |
1100 | IWL_RXON_CTX_BSS, | |
ece9c4ee | 1101 | IWL_RXON_CTX_PAN, |
246ed355 JB |
1102 | |
1103 | NUM_IWL_RXON_CTX | |
1104 | }; | |
1105 | ||
1106 | struct iwl_rxon_context { | |
8bd413e6 | 1107 | struct ieee80211_vif *vif; |
e72f368b JB |
1108 | |
1109 | const u8 *ac_to_fifo; | |
1110 | const u8 *ac_to_queue; | |
1111 | u8 mcast_queue; | |
1112 | ||
763cc3bf JB |
1113 | /* |
1114 | * We could use the vif to indicate active, but we | |
1115 | * also need it to be active during disabling when | |
1116 | * we already removed the vif for type setting. | |
1117 | */ | |
1118 | bool always_active, is_active; | |
1119 | ||
2295c66b JB |
1120 | bool ht_need_multiple_chains; |
1121 | ||
246ed355 | 1122 | enum iwl_rxon_context_id ctxid; |
d0fe478c JB |
1123 | |
1124 | u32 interface_modes, exclusive_interface_modes; | |
1125 | u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype; | |
1126 | ||
246ed355 JB |
1127 | /* |
1128 | * We declare this const so it can only be | |
1129 | * changed via explicit cast within the | |
1130 | * routines that actually update the physical | |
1131 | * hardware. | |
1132 | */ | |
1133 | const struct iwl_rxon_cmd active; | |
1134 | struct iwl_rxon_cmd staging; | |
1135 | ||
1136 | struct iwl_rxon_time_cmd timing; | |
a194e324 | 1137 | |
8dfdb9d5 JB |
1138 | struct iwl_qos_info qos_data; |
1139 | ||
2995bafa | 1140 | u8 bcast_sta_id, ap_sta_id; |
8f2d3d2a JB |
1141 | |
1142 | u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd; | |
8dfdb9d5 | 1143 | u8 qos_cmd; |
c10afb6e JB |
1144 | u8 wep_key_cmd; |
1145 | ||
1146 | struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; | |
1147 | u8 key_mapping_keys; | |
770e13bd JB |
1148 | |
1149 | __le32 station_flags; | |
7e6a5886 JB |
1150 | |
1151 | struct { | |
1152 | bool non_gf_sta_present; | |
1153 | u8 protection; | |
1154 | bool enabled, is_40mhz; | |
1155 | u8 extension_chan_offset; | |
1156 | } ht; | |
246ed355 JB |
1157 | }; |
1158 | ||
266af4c7 JB |
1159 | enum iwl_scan_type { |
1160 | IWL_SCAN_NORMAL, | |
1161 | IWL_SCAN_RADIO_RESET, | |
1162 | IWL_SCAN_OFFCH_TX, | |
1163 | }; | |
1164 | ||
c79dd5b5 | 1165 | struct iwl_priv { |
5d08cd1d CH |
1166 | |
1167 | /* ieee device used by generic ieee processing code */ | |
1168 | struct ieee80211_hw *hw; | |
1169 | struct ieee80211_channel *ieee_channels; | |
1170 | struct ieee80211_rate *ieee_rates; | |
82b9a121 | 1171 | struct iwl_cfg *cfg; |
5d08cd1d CH |
1172 | |
1173 | /* temporary frame storage list */ | |
1174 | struct list_head free_frames; | |
1175 | int frames_count; | |
1176 | ||
8318d78a | 1177 | enum ieee80211_band band; |
2f301227 | 1178 | int alloc_rxb_page; |
5d08cd1d | 1179 | |
c79dd5b5 | 1180 | void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv, |
a55360e4 | 1181 | struct iwl_rx_mem_buffer *rxb); |
5d08cd1d | 1182 | |
8318d78a | 1183 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; |
5d08cd1d | 1184 | |
5d08cd1d | 1185 | /* spectrum measurement report caching */ |
2aa6ab86 | 1186 | struct iwl_spectrum_notification measure_report; |
5d08cd1d | 1187 | u8 measurement_status; |
81963d68 | 1188 | |
5d08cd1d CH |
1189 | /* ucode beacon time */ |
1190 | u32 ucode_beacon_time; | |
a13d276f | 1191 | int missed_beacon_threshold; |
5d08cd1d | 1192 | |
a85d7cca JB |
1193 | /* track IBSS manager (last beacon) status */ |
1194 | u32 ibss_manager; | |
1195 | ||
410f2bb3 SG |
1196 | /* jiffies when last recovery from statistics was performed */ |
1197 | unsigned long rx_statistics_jiffies; | |
3e4fb5fa | 1198 | |
a93e7973 | 1199 | /* force reset */ |
8a472da4 | 1200 | struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET]; |
a93e7973 | 1201 | |
491bc292 WYG |
1202 | /* firmware reload counter and timestamp */ |
1203 | unsigned long reload_jiffies; | |
1204 | int reload_count; | |
1205 | ||
5a2a780c | 1206 | /* we allocate array of iwl_channel_info for NIC's valid channels. |
5d08cd1d | 1207 | * Access via channel # using indirect index array */ |
bf85ea4f | 1208 | struct iwl_channel_info *channel_info; /* channel info array */ |
5d08cd1d CH |
1209 | u8 channel_count; /* # of channels */ |
1210 | ||
5d08cd1d CH |
1211 | /* thermal calibration */ |
1212 | s32 temperature; /* degrees Kelvin */ | |
1213 | s32 last_temperature; | |
1214 | ||
7c616cba | 1215 | /* init calibration results */ |
6e21f2c1 | 1216 | struct iwl_calib_result calib_results[IWL_CALIB_MAX]; |
7c616cba | 1217 | |
5d08cd1d | 1218 | /* Scan related variables */ |
5d08cd1d | 1219 | unsigned long scan_start; |
5d08cd1d | 1220 | unsigned long scan_start_tsf; |
811ecc99 | 1221 | void *scan_cmd; |
00700ee0 | 1222 | enum ieee80211_band scan_band; |
1ecf9fc1 | 1223 | struct cfg80211_scan_request *scan_request; |
f84b29ec | 1224 | struct ieee80211_vif *scan_vif; |
266af4c7 | 1225 | enum iwl_scan_type scan_type; |
76eff18b TW |
1226 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; |
1227 | u8 mgmt_tx_ant; | |
5d08cd1d CH |
1228 | |
1229 | /* spinlock */ | |
1230 | spinlock_t lock; /* protect general shared data */ | |
1231 | spinlock_t hcmd_lock; /* protect hcmd */ | |
a8b50a0a | 1232 | spinlock_t reg_lock; /* protect hw register access */ |
5d08cd1d CH |
1233 | struct mutex mutex; |
1234 | ||
1235 | /* basic pci-network driver stuff */ | |
1236 | struct pci_dev *pci_dev; | |
1237 | ||
1238 | /* pci hardware address support */ | |
1239 | void __iomem *hw_base; | |
b661c819 TW |
1240 | u32 hw_rev; |
1241 | u32 hw_wa_rev; | |
1242 | u8 rev_id; | |
5d08cd1d | 1243 | |
246ed355 JB |
1244 | /* microcode/device supports multiple contexts */ |
1245 | u8 valid_contexts; | |
1246 | ||
13bb9483 JB |
1247 | /* command queue number */ |
1248 | u8 cmd_queue; | |
1249 | ||
c10afb6e JB |
1250 | /* max number of station keys */ |
1251 | u8 sta_key_max_num; | |
1252 | ||
c6fa17ed WYG |
1253 | /* EEPROM MAC addresses */ |
1254 | struct mac_address addresses[2]; | |
1255 | ||
5d08cd1d | 1256 | /* uCode images, save to reload in case of failure */ |
b08dfd04 | 1257 | int fw_index; /* firmware we're trying to load */ |
c02b3acd CR |
1258 | u32 ucode_ver; /* version of ucode, copy of |
1259 | iwl_ucode.ver */ | |
5d08cd1d CH |
1260 | struct fw_desc ucode_code; /* runtime inst */ |
1261 | struct fw_desc ucode_data; /* runtime data original */ | |
5d08cd1d CH |
1262 | struct fw_desc ucode_init; /* initialization inst */ |
1263 | struct fw_desc ucode_init_data; /* initialization data */ | |
dbb983b7 RR |
1264 | enum ucode_type ucode_type; |
1265 | u8 ucode_write_complete; /* the image write is complete */ | |
b08dfd04 | 1266 | char firmware_name[25]; |
5d08cd1d | 1267 | |
246ed355 | 1268 | struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX]; |
5d08cd1d | 1269 | |
0924e519 WYG |
1270 | struct iwl_switch_rxon switch_rxon; |
1271 | ||
5d08cd1d | 1272 | /* 1st responses from initialize and runtime uCode images. |
5a2a780c | 1273 | * _agn's initialize alive response contains some calibration data. */ |
885ba202 TW |
1274 | struct iwl_init_alive_resp card_alive_init; |
1275 | struct iwl_alive_resp card_alive; | |
5d08cd1d | 1276 | |
5d08cd1d | 1277 | u16 active_rate; |
5d08cd1d | 1278 | |
5d08cd1d | 1279 | u8 start_calib; |
f0832f13 EG |
1280 | struct iwl_sensitivity_data sensitivity_data; |
1281 | struct iwl_chain_noise_data chain_noise_data; | |
c8312fac | 1282 | bool enhance_sensitivity_table; |
5d08cd1d | 1283 | __le16 sensitivity_tbl[HD_TABLE_SIZE]; |
c8312fac | 1284 | __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES]; |
5d08cd1d | 1285 | |
fad95bf5 | 1286 | struct iwl_ht_config current_ht_config; |
5d08cd1d | 1287 | |
5d08cd1d | 1288 | /* Rate scaling data */ |
5d08cd1d CH |
1289 | u8 retry_rate; |
1290 | ||
1291 | wait_queue_head_t wait_command_queue; | |
1292 | ||
1293 | int activity_timer_active; | |
1294 | ||
1295 | /* Rx and Tx DMA processing queues */ | |
a55360e4 | 1296 | struct iwl_rx_queue rxq; |
88804e2b | 1297 | struct iwl_tx_queue *txq; |
5d08cd1d | 1298 | unsigned long txq_ctx_active_msk; |
4ddbb7d0 TW |
1299 | struct iwl_dma_ptr kw; /* keep warm address */ |
1300 | struct iwl_dma_ptr scd_bc_tbls; | |
1301 | ||
5d08cd1d CH |
1302 | u32 scd_base_addr; /* scheduler sram base address */ |
1303 | ||
1304 | unsigned long status; | |
5d08cd1d | 1305 | |
19758bef | 1306 | /* counts mgmt, ctl, and data packets */ |
22fdf3c9 WYG |
1307 | struct traffic_stats tx_stats; |
1308 | struct traffic_stats rx_stats; | |
19758bef | 1309 | |
a83b9141 WYG |
1310 | /* counts interrupts */ |
1311 | struct isr_statistics isr_stats; | |
1312 | ||
5da4b55f | 1313 | struct iwl_power_mgr power_data; |
3ad3b92a | 1314 | struct iwl_tt_mgmt thermal_throttle; |
5d08cd1d | 1315 | |
9c5ac091 RC |
1316 | /* station table variables */ |
1317 | ||
1318 | /* Note: if lock and sta_lock are needed, lock must be acquired first */ | |
5d08cd1d CH |
1319 | spinlock_t sta_lock; |
1320 | int num_stations; | |
3240cab3 | 1321 | struct iwl_station_entry stations[IWLAGN_STATION_COUNT]; |
80fb47a1 | 1322 | unsigned long ucode_key_table; |
5d08cd1d | 1323 | |
e4e72fb4 JB |
1324 | /* queue refcounts */ |
1325 | #define IWL_MAX_HW_QUEUES 32 | |
1326 | unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; | |
1327 | /* for each AC */ | |
1328 | atomic_t queue_stop_count[4]; | |
1329 | ||
5d08cd1d | 1330 | /* Indication if ieee80211_ops->open has been called */ |
69dc5d9d | 1331 | u8 is_open; |
5d08cd1d CH |
1332 | |
1333 | u8 mac80211_registered; | |
5d08cd1d | 1334 | |
af6b8ee3 | 1335 | /* eeprom -- this is in the card's little endian byte order */ |
073d3f5f | 1336 | u8 *eeprom; |
0848e297 | 1337 | int nvm_device_type; |
073d3f5f | 1338 | struct iwl_eeprom_calib_info *calib_info; |
5d08cd1d | 1339 | |
05c914fe | 1340 | enum nl80211_iftype iw_mode; |
5d08cd1d | 1341 | |
5d08cd1d | 1342 | /* Last Rx'd beacon timestamp */ |
3109ece1 | 1343 | u64 timestamp; |
5d08cd1d | 1344 | |
3240cab3 JB |
1345 | struct { |
1346 | /* INT ICT Table */ | |
1347 | __le32 *ict_tbl; | |
1348 | void *ict_tbl_vir; | |
1349 | dma_addr_t ict_tbl_dma; | |
1350 | dma_addr_t aligned_ict_tbl_dma; | |
1351 | int ict_index; | |
1352 | u32 inta; | |
1353 | bool use_ict; | |
1354 | /* | |
1355 | * reporting the number of tids has AGG on. 0 means | |
1356 | * no AGGREGATION | |
1357 | */ | |
1358 | u8 agg_tids_count; | |
1359 | ||
1360 | struct iwl_rx_phy_res last_phy_res; | |
1361 | bool last_phy_res_valid; | |
1362 | ||
1363 | struct completion firmware_loading_complete; | |
1364 | ||
1365 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1366 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
1367 | ||
1368 | /* | |
1369 | * chain noise reset and gain commands are the | |
1370 | * two extra calibration commands follows the standard | |
1371 | * phy calibration commands | |
1372 | */ | |
1373 | u8 phy_calib_chain_noise_reset_cmd; | |
1374 | u8 phy_calib_chain_noise_gain_cmd; | |
1375 | ||
1376 | struct iwl_notif_statistics statistics; | |
1377 | struct iwl_bt_notif_statistics statistics_bt; | |
1378 | /* counts reply_tx error */ | |
1379 | struct reply_tx_error_statistics reply_tx_stats; | |
1380 | struct reply_agg_tx_error_statistics reply_agg_tx_stats; | |
f3aebeee | 1381 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
3240cab3 JB |
1382 | struct iwl_notif_statistics accum_statistics; |
1383 | struct iwl_notif_statistics delta_statistics; | |
1384 | struct iwl_notif_statistics max_delta; | |
1385 | struct iwl_bt_notif_statistics accum_statistics_bt; | |
1386 | struct iwl_bt_notif_statistics delta_statistics_bt; | |
1387 | struct iwl_bt_notif_statistics max_delta_bt; | |
ee525d13 | 1388 | #endif |
3240cab3 JB |
1389 | /* notification wait support */ |
1390 | struct list_head notif_waits; | |
1391 | spinlock_t notif_wait_lock; | |
1392 | wait_queue_head_t notif_waitq; | |
1393 | ||
1394 | /* remain-on-channel offload support */ | |
1395 | struct ieee80211_channel *hw_roc_channel; | |
1396 | struct delayed_work hw_roc_work; | |
1397 | enum nl80211_channel_type hw_roc_chantype; | |
1398 | int hw_roc_duration; | |
1399 | bool hw_roc_setup; | |
1400 | ||
1401 | struct sk_buff *offchan_tx_skb; | |
1402 | int offchan_tx_timeout; | |
1403 | struct ieee80211_channel *offchan_tx_chan; | |
1404 | } _agn; | |
ee525d13 | 1405 | |
22bf59a0 | 1406 | /* bt coex */ |
f21dd005 | 1407 | u8 bt_enable_flag; |
da5dbb97 | 1408 | u8 bt_status; |
66e863a5 | 1409 | u8 bt_traffic_load, last_bt_traffic_load; |
f37837c9 | 1410 | bool bt_ch_announce; |
bee008b7 WYG |
1411 | bool bt_full_concurrent; |
1412 | bool bt_ant_couple_ok; | |
fbba9410 WYG |
1413 | __le32 kill_ack_mask; |
1414 | __le32 kill_cts_mask; | |
1415 | __le16 bt_valid; | |
22bf59a0 WYG |
1416 | u16 bt_on_thresh; |
1417 | u16 bt_duration; | |
1418 | u16 dynamic_frag_thresh; | |
bee008b7 | 1419 | u8 bt_ci_compliance; |
9e4afc21 JB |
1420 | struct work_struct bt_traffic_change_work; |
1421 | ||
5425e490 | 1422 | struct iwl_hw_params hw_params; |
4ddbb7d0 | 1423 | |
40cefda9 | 1424 | u32 inta_mask; |
5d08cd1d | 1425 | |
5d08cd1d CH |
1426 | struct workqueue_struct *workqueue; |
1427 | ||
5d08cd1d | 1428 | struct work_struct restart; |
5d08cd1d CH |
1429 | struct work_struct scan_completed; |
1430 | struct work_struct rx_replenish; | |
5d08cd1d | 1431 | struct work_struct abort_scan; |
12e934dc | 1432 | |
5d08cd1d | 1433 | struct work_struct beacon_update; |
76d04815 | 1434 | struct iwl_rxon_context *beacon_ctx; |
12e934dc | 1435 | struct sk_buff *beacon_skb; |
76d04815 | 1436 | |
a28027cd WYG |
1437 | struct work_struct tt_work; |
1438 | struct work_struct ct_enter; | |
1439 | struct work_struct ct_exit; | |
88be0264 | 1440 | struct work_struct start_internal_scan; |
65550636 | 1441 | struct work_struct tx_flush; |
bee008b7 | 1442 | struct work_struct bt_full_concurrency; |
fbba9410 | 1443 | struct work_struct bt_runtime_config; |
5d08cd1d CH |
1444 | |
1445 | struct tasklet_struct irq_tasklet; | |
1446 | ||
1447 | struct delayed_work init_alive_start; | |
1448 | struct delayed_work alive_start; | |
5d08cd1d | 1449 | struct delayed_work scan_check; |
4a8a4322 | 1450 | |
630fe9b6 TW |
1451 | /* TX Power */ |
1452 | s8 tx_power_user_lmt; | |
dc1b0973 | 1453 | s8 tx_power_device_lmt; |
ae16fc3c | 1454 | s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */ |
a25a66ac | 1455 | s8 tx_power_next; |
5d08cd1d | 1456 | |
5d08cd1d | 1457 | |
d08853a3 | 1458 | #ifdef CONFIG_IWLWIFI_DEBUG |
5d08cd1d | 1459 | /* debugging info */ |
3d816c77 RC |
1460 | u32 debug_level; /* per device debugging will override global |
1461 | iwl_debug_level if set */ | |
d73e4923 | 1462 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
712b6cf5 TW |
1463 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1464 | /* debugfs */ | |
20594eb0 WYG |
1465 | u16 tx_traffic_idx; |
1466 | u16 rx_traffic_idx; | |
1467 | u8 *tx_traffic; | |
1468 | u8 *rx_traffic; | |
4c84a8f1 JB |
1469 | struct dentry *debugfs_dir; |
1470 | u32 dbgfs_sram_offset, dbgfs_sram_len; | |
d73e4923 | 1471 | bool disable_ht40; |
712b6cf5 | 1472 | #endif /* CONFIG_IWLWIFI_DEBUGFS */ |
5d08cd1d CH |
1473 | |
1474 | struct work_struct txpower_work; | |
445c2dff TW |
1475 | u32 disable_sens_cal; |
1476 | u32 disable_chain_noise_cal; | |
203566f3 | 1477 | u32 disable_tx_power_cal; |
16e727e8 | 1478 | struct work_struct run_time_calib_work; |
5d08cd1d | 1479 | struct timer_list statistics_periodic; |
a9e1cb6a | 1480 | struct timer_list ucode_trace; |
22de94de | 1481 | struct timer_list watchdog; |
086ed117 | 1482 | bool hw_ready; |
a9e1cb6a WYG |
1483 | |
1484 | struct iwl_event_log event_log; | |
5ed540ae WYG |
1485 | |
1486 | struct led_classdev led; | |
1487 | unsigned long blink_on, blink_off; | |
1488 | bool led_registered; | |
c79dd5b5 | 1489 | }; /*iwl_priv */ |
5d08cd1d | 1490 | |
36470749 RR |
1491 | static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id) |
1492 | { | |
1493 | set_bit(txq_id, &priv->txq_ctx_active_msk); | |
1494 | } | |
1495 | ||
1496 | static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id) | |
1497 | { | |
1498 | clear_bit(txq_id, &priv->txq_ctx_active_msk); | |
1499 | } | |
1500 | ||
994d31f7 | 1501 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 RC |
1502 | /* |
1503 | * iwl_get_debug_level: Return active debug level for device | |
1504 | * | |
1505 | * Using sysfs it is possible to set per device debug level. This debug | |
1506 | * level will be used if set, otherwise the global debug level which can be | |
1507 | * set via module parameter is used. | |
1508 | */ | |
1509 | static inline u32 iwl_get_debug_level(struct iwl_priv *priv) | |
1510 | { | |
1511 | if (priv->debug_level) | |
1512 | return priv->debug_level; | |
1513 | else | |
1514 | return iwl_debug_level; | |
1515 | } | |
a332f8d6 | 1516 | #else |
3d816c77 RC |
1517 | static inline u32 iwl_get_debug_level(struct iwl_priv *priv) |
1518 | { | |
1519 | return iwl_debug_level; | |
1520 | } | |
a332f8d6 TW |
1521 | #endif |
1522 | ||
1523 | ||
a332f8d6 TW |
1524 | static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv, |
1525 | int txq_id, int idx) | |
1526 | { | |
ff0d91c3 | 1527 | if (priv->txq[txq_id].txb[idx].skb) |
a332f8d6 | 1528 | return (struct ieee80211_hdr *)priv->txq[txq_id]. |
ff0d91c3 | 1529 | txb[idx].skb->data; |
a332f8d6 TW |
1530 | return NULL; |
1531 | } | |
a332f8d6 | 1532 | |
246ed355 JB |
1533 | static inline struct iwl_rxon_context * |
1534 | iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif) | |
1535 | { | |
1536 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; | |
1537 | ||
1538 | return vif_priv->ctx; | |
1539 | } | |
1540 | ||
1541 | #define for_each_context(priv, ctx) \ | |
1542 | for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \ | |
1543 | ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \ | |
1544 | if (priv->valid_contexts & BIT(ctx->ctxid)) | |
1545 | ||
1546 | static inline int iwl_is_associated(struct iwl_priv *priv, | |
1547 | enum iwl_rxon_context_id ctxid) | |
1548 | { | |
1549 | return (priv->contexts[ctxid].active.filter_flags & | |
1550 | RXON_FILTER_ASSOC_MSK) ? 1 : 0; | |
1551 | } | |
1552 | ||
1553 | static inline int iwl_is_any_associated(struct iwl_priv *priv) | |
1554 | { | |
1555 | return iwl_is_associated(priv, IWL_RXON_CTX_BSS); | |
1556 | } | |
a332f8d6 | 1557 | |
246ed355 | 1558 | static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx) |
5d08cd1d | 1559 | { |
246ed355 | 1560 | return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; |
5d08cd1d CH |
1561 | } |
1562 | ||
bf85ea4f | 1563 | static inline int is_channel_valid(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1564 | { |
1565 | if (ch_info == NULL) | |
1566 | return 0; | |
1567 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1568 | } | |
1569 | ||
bf85ea4f | 1570 | static inline int is_channel_radar(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1571 | { |
1572 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1573 | } | |
1574 | ||
bf85ea4f | 1575 | static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1576 | { |
8318d78a | 1577 | return ch_info->band == IEEE80211_BAND_5GHZ; |
5d08cd1d CH |
1578 | } |
1579 | ||
bf85ea4f | 1580 | static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1581 | { |
8318d78a | 1582 | return ch_info->band == IEEE80211_BAND_2GHZ; |
5d08cd1d CH |
1583 | } |
1584 | ||
bf85ea4f | 1585 | static inline int is_channel_passive(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1586 | { |
1587 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1588 | } | |
1589 | ||
bf85ea4f | 1590 | static inline int is_channel_ibss(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1591 | { |
1592 | return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0; | |
1593 | } | |
1594 | ||
64a76b50 ZY |
1595 | static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page) |
1596 | { | |
1597 | __free_pages(page, priv->hw_params.rx_page_order); | |
1598 | priv->alloc_rxb_page--; | |
1599 | } | |
1600 | ||
1601 | static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page) | |
1602 | { | |
1603 | free_pages(page, priv->hw_params.rx_page_order); | |
1604 | priv->alloc_rxb_page--; | |
1605 | } | |
be1f3ab6 | 1606 | #endif /* __iwl_dev_h__ */ |