iwlwifi: send tx_power_cmd synchronously
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-4965-hw.h"
45#include "iwl-3945-hw.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
0975cc8f 50#include "iwl-agn-tt.h"
5d08cd1d 51
672639de
WYG
52struct iwl_tx_queue;
53
099b40b7 54/* CT-KILL constants */
672639de
WYG
55#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
56#define CT_KILL_THRESHOLD 114 /* in Celsius */
57#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 58
5d08cd1d
CH
59/* Default noise level to report when noise measurement is not available.
60 * This may be because we're:
61 * 1) Not associated (4965, no beacon statistics being sent to driver)
62 * 2) Scanning (noise measurement does not apply to associated channel)
63 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
64 * Use default noise value of -127 ... this is below the range of measurable
65 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
66 * Also, -127 works better than 0 when averaging frames with/without
67 * noise info (e.g. averaging might be done in app); measured dBm values are
68 * always negative ... using a negative value as the default keeps all
69 * averages within an s8's (used in some apps) range of negative values. */
70#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
71
5d08cd1d
CH
72/*
73 * RTS threshold here is total size [2347] minus 4 FCS bytes
74 * Per spec:
75 * a value of 0 means RTS on all data/management packets
76 * a value > max MSDU size means no RTS
77 * else RTS for data/management frames where MPDU is larger
78 * than RTS value.
79 */
80#define DEFAULT_RTS_THRESHOLD 2347U
81#define MIN_RTS_THRESHOLD 0U
82#define MAX_RTS_THRESHOLD 2347U
83#define MAX_MSDU_SIZE 2304U
84#define MAX_MPDU_SIZE 2346U
85#define DEFAULT_BEACON_INTERVAL 100U
86#define DEFAULT_SHORT_RETRY_LIMIT 7U
87#define DEFAULT_LONG_RETRY_LIMIT 4U
88
a55360e4 89struct iwl_rx_mem_buffer {
2f301227
ZY
90 dma_addr_t page_dma;
91 struct page *page;
5d08cd1d
CH
92 struct list_head list;
93};
94
2f301227
ZY
95#define rxb_addr(r) page_address(r->page)
96
c2acea8e
JB
97/* defined below */
98struct iwl_device_cmd;
99
100struct iwl_cmd_meta {
101 /* only for SYNC commands, iff the reply skb is wanted */
102 struct iwl_host_cmd *source;
103 /*
104 * only for ASYNC commands
105 * (which is somewhat stupid -- look at iwl-sta.c for instance
106 * which duplicates a bunch of code because the callback isn't
107 * invoked for SYNC commands, if it were and its result passed
108 * through it would be simpler...)
109 */
5696aea6
JB
110 void (*callback)(struct iwl_priv *priv,
111 struct iwl_device_cmd *cmd,
2f301227 112 struct iwl_rx_packet *pkt);
c2acea8e
JB
113
114 /* The CMD_SIZE_HUGE flag bit indicates that the command
115 * structure is stored at the end of the shared queue memory. */
116 u32 flags;
117
2e724443
FT
118 DEFINE_DMA_UNMAP_ADDR(mapping);
119 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
120};
121
5d08cd1d
CH
122/*
123 * Generic queue structure
124 *
125 * Contains common data for Rx and Tx queues
126 */
443cfd45 127struct iwl_queue {
5d08cd1d
CH
128 int n_bd; /* number of BDs in this queue */
129 int write_ptr; /* 1-st empty entry (index) host_w*/
130 int read_ptr; /* last used entry (index) host_r*/
b74e31a9
WYG
131 /* use for monitoring and recovering the stuck queue */
132 int last_read_ptr; /* storing the last read_ptr */
133 /* number of time read_ptr and last_read_ptr are the same */
134 u8 repeat_same_read_ptr;
5d08cd1d
CH
135 dma_addr_t dma_addr; /* physical addr for BD's */
136 int n_window; /* safe queue window */
137 u32 id;
138 int low_mark; /* low watermark, resume queue if free
139 * space more than this */
140 int high_mark; /* high watermark, stop queue if free
141 * space less than this */
ba2d3587 142} __packed;
5d08cd1d 143
bc47279f 144/* One for each TFD */
8567c63e 145struct iwl_tx_info {
ff0d91c3 146 struct sk_buff *skb;
c90cbbbd 147 struct iwl_rxon_context *ctx;
5d08cd1d
CH
148};
149
150/**
16466903 151 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
152 * @q: generic Rx/Tx queue descriptor
153 * @bd: base of circular buffer of TFDs
c2acea8e
JB
154 * @cmd: array of command/TX buffer pointers
155 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
156 * @dma_addr_cmd: physical address of cmd/tx buffer array
157 * @txb: array of per-TFD driver data
158 * @need_update: indicates need to update read/write index
159 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 160 *
bc47279f
BC
161 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
162 * descriptors) and required locking structures.
5d08cd1d 163 */
188cf6c7
SO
164#define TFD_TX_CMD_SLOTS 256
165#define TFD_CMD_SLOTS 32
166
16466903 167struct iwl_tx_queue {
443cfd45 168 struct iwl_queue q;
59606ffa 169 void *tfds;
c2acea8e
JB
170 struct iwl_device_cmd **cmd;
171 struct iwl_cmd_meta *meta;
8567c63e 172 struct iwl_tx_info *txb;
3fd07a1e
TW
173 u8 need_update;
174 u8 sched_retry;
175 u8 active;
176 u8 swq_id;
5d08cd1d
CH
177};
178
179#define IWL_NUM_SCAN_RATES (2)
180
bb8c093b 181struct iwl4965_channel_tgd_info {
5d08cd1d
CH
182 u8 type;
183 s8 max_power;
184};
185
bb8c093b 186struct iwl4965_channel_tgh_info {
5d08cd1d
CH
187 s64 last_radar_time;
188};
189
d20b3c65
SO
190#define IWL4965_MAX_RATE (33)
191
85d41495
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192struct iwl3945_clip_group {
193 /* maximum power level to prevent clipping for each rate, derived by
194 * us from this band's saturation power in EEPROM */
195 const s8 clip_powers[IWL_MAX_RATES];
196};
197
d20b3c65
SO
198/* current Tx power values to use, one for each rate for each channel.
199 * requested power is limited by:
200 * -- regulatory EEPROM limits for this channel
201 * -- hardware capabilities (clip-powers)
202 * -- spectrum management
203 * -- user preference (e.g. iwconfig)
204 * when requested power is set, base power index must also be set. */
205struct iwl3945_channel_power_info {
206 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
207 s8 power_table_index; /* actual (compenst'd) index into gain table */
208 s8 base_power_index; /* gain index for power at factory temp. */
209 s8 requested_power; /* power (dBm) requested for this chnl/rate */
210};
211
212/* current scan Tx power values to use, one for each scan rate for each
213 * channel. */
214struct iwl3945_scan_power_info {
215 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
216 s8 power_table_index; /* actual (compenst'd) index into gain table */
217 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
218};
219
5d08cd1d
CH
220/*
221 * One for each channel, holds all channel setup data
222 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
223 * with one another!
224 */
bf85ea4f 225struct iwl_channel_info {
bb8c093b
CH
226 struct iwl4965_channel_tgd_info tgd;
227 struct iwl4965_channel_tgh_info tgh;
073d3f5f 228 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
229 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
230 * HT40 channel */
5d08cd1d
CH
231
232 u8 channel; /* channel number */
233 u8 flags; /* flags copied from EEPROM */
234 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 235 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
236 s8 min_power; /* always 0 */
237 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
238
239 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
240 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 241 enum ieee80211_band band;
5d08cd1d 242
7aafef1c
WYG
243 /* HT40 channel info */
244 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
245 u8 ht40_flags; /* flags copied from EEPROM */
246 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
247
248 /* Radio/DSP gain settings for each "normal" data Tx rate.
249 * These include, in addition to RF and DSP gain, a few fields for
250 * remembering/modifying gain settings (indexes). */
251 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
252
253 /* Radio/DSP gain settings for each scan rate, for directed scans. */
254 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
255};
256
751ca305 257#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 258#define IWL_TX_FIFO_BE 1
751ca305 259#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 260#define IWL_TX_FIFO_VO 3
751ca305
JB
261#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
262#define IWL_TX_FIFO_BE_IPAN 4
263#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
264#define IWL_TX_FIFO_VO_IPAN 5
edc1a3a0 265#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 266
01a7e084
RC
267/* Minimum number of queues. MAX_NUM is defined in hw specific files.
268 * Set the minimum to accommodate the 4 standard TX queues, 1 command
269 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
270#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 271
bd35f150 272/*
13bb9483 273 * Command queue depends on iPAN support.
bd35f150 274 */
13bb9483
JB
275#define IWL_DEFAULT_CMD_QUEUE_NUM 4
276#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 277
751ca305
JB
278/*
279 * This queue number is required for proper operation
280 * because the ucode will stop/start the scheduler as
281 * required.
282 */
283#define IWL_IPAN_MCAST_QUEUE 8
284
5d08cd1d
CH
285#define IEEE80211_DATA_LEN 2304
286#define IEEE80211_4ADDR_LEN 30
287#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
288#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
289
fcab423d 290struct iwl_frame {
5d08cd1d
CH
291 union {
292 struct ieee80211_hdr frame;
4bf64efd 293 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
294 u8 raw[IEEE80211_FRAME_LEN];
295 u8 cmd[360];
296 } u;
297 struct list_head list;
298};
299
5d08cd1d
CH
300#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
301#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
302#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
303
304enum {
c587de0b
TW
305 CMD_SYNC = 0,
306 CMD_SIZE_NORMAL = 0,
307 CMD_NO_SKB = 0,
5d08cd1d 308 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 309 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
310 CMD_WANT_SKB = (1 << 2),
311};
312
c8c24872 313#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 314
bc47279f 315/**
c2acea8e 316 * struct iwl_device_cmd
bc47279f
BC
317 *
318 * For allocation of the command and tx queues, this establishes the overall
319 * size of the largest command we send to uCode, except for a scan command
320 * (which is relatively huge; space is allocated separately).
321 */
c2acea8e 322struct iwl_device_cmd {
857485c0 323 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 324 union {
5d08cd1d
CH
325 u32 flags;
326 u8 val8;
327 u16 val16;
328 u32 val32;
83d527d9 329 struct iwl_tx_cmd tx;
c8c24872
WYG
330 struct iwl6000_channel_switch_cmd chswitch;
331 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
332 } __packed cmd;
333} __packed;
5d08cd1d 334
c2acea8e
JB
335#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
336
3257e5d4 337
857485c0 338struct iwl_host_cmd {
5d08cd1d 339 const void *data;
2f301227 340 unsigned long reply_page;
5696aea6
JB
341 void (*callback)(struct iwl_priv *priv,
342 struct iwl_device_cmd *cmd,
2f301227 343 struct iwl_rx_packet *pkt);
c2acea8e
JB
344 u32 flags;
345 u16 len;
346 u8 id;
5d08cd1d
CH
347};
348
5d08cd1d
CH
349#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
350#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
351#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
352
353/**
a55360e4 354 * struct iwl_rx_queue - Rx queue
df833b1d 355 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 356 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
357 * @read: Shared index to newest available Rx buffer
358 * @write: Shared index to oldest written Rx packet
359 * @free_count: Number of pre-allocated buffers in rx_free
360 * @rx_free: list of free SKBs for use
361 * @rx_used: List of Rx buffers with no SKB
362 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
363 * @rb_stts: driver's pointer to receive buffer status
364 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 365 *
a55360e4 366 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 367 */
a55360e4 368struct iwl_rx_queue {
5d08cd1d 369 __le32 *bd;
d5b25c90 370 dma_addr_t bd_dma;
a55360e4
TW
371 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
372 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
373 u32 read;
374 u32 write;
375 u32 free_count;
4752c93c 376 u32 write_actual;
5d08cd1d
CH
377 struct list_head rx_free;
378 struct list_head rx_used;
379 int need_update;
8d86422a
WT
380 struct iwl_rb_status *rb_stts;
381 dma_addr_t rb_stts_dma;
5d08cd1d
CH
382 spinlock_t lock;
383};
384
385#define IWL_SUPPORTED_RATES_IE_LEN 8
386
5d08cd1d
CH
387#define MAX_TID_COUNT 9
388
389#define IWL_INVALID_RATE 0xFF
390#define IWL_INVALID_VALUE -1
391
bc47279f 392/**
6def9761 393 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
394 * @txq_id: Tx queue used for Tx attempt
395 * @frame_count: # frames attempted by Tx command
396 * @wait_for_ba: Expect block-ack before next Tx reply
397 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
398 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
399 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
400 * @rate_n_flags: Rate at which Tx was attempted
401 *
402 * If REPLY_TX indicates that aggregation was attempted, driver must wait
403 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
404 * until block ack arrives.
405 */
6def9761 406struct iwl_ht_agg {
5d08cd1d
CH
407 u16 txq_id;
408 u16 frame_count;
409 u16 wait_for_ba;
410 u16 start_idx;
fe01b477 411 u64 bitmap;
5d08cd1d 412 u32 rate_n_flags;
fe01b477
RR
413#define IWL_AGG_OFF 0
414#define IWL_AGG_ON 1
415#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
416#define IWL_EMPTYING_HW_QUEUE_DELBA 3
417 u8 state;
5d08cd1d 418};
fe01b477 419
5d08cd1d 420
6def9761 421struct iwl_tid_data {
f862a236 422 u16 seq_number; /* agn only */
fe01b477 423 u16 tfds_in_queue;
6def9761 424 struct iwl_ht_agg agg;
5d08cd1d
CH
425};
426
6def9761 427struct iwl_hw_key {
97359d12 428 u32 cipher;
5d08cd1d 429 int keylen;
0211ddda 430 u8 keyidx;
5d08cd1d
CH
431 u8 key[32];
432};
433
a78fe754 434union iwl_ht_rate_supp {
5d08cd1d
CH
435 u16 rates;
436 struct {
437 u8 siso_rate;
438 u8 mimo_rate;
439 };
440};
441
172c1d11
WYG
442#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
443#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
444#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
445#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
446#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
447#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
448#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
449
450/*
451 * Maximal MPDU density for TX aggregation
452 * 4 - 2us density
453 * 5 - 4us density
454 * 6 - 8us density
455 * 7 - 16us density
456 */
172c1d11 457#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 458#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
459#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
460#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 461#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
462#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
463#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 464
fad95bf5 465struct iwl_ht_config {
02bb1bea 466 bool single_chain_sufficient;
ba37a3d0 467 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 468};
5d08cd1d 469
5d08cd1d 470/* QoS structures */
1ff50bda 471struct iwl_qos_info {
5d08cd1d 472 int qos_active;
1ff50bda 473 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 474};
5d08cd1d 475
fe6b23dd
RC
476/*
477 * Structure should be accessed with sta_lock held. When station addition
478 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
479 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
480 * held.
481 */
6def9761 482struct iwl_station_entry {
133636de 483 struct iwl_addsta_cmd sta;
6def9761 484 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 485 u8 used, ctxid;
6def9761 486 struct iwl_hw_key keyinfo;
fe6b23dd 487 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
488};
489
fd1af15d 490struct iwl_station_priv_common {
238d781d 491 struct iwl_rxon_context *ctx;
fd1af15d
JB
492 u8 sta_id;
493};
494
8d9698b3
RC
495/*
496 * iwl_station_priv: Driver's private station information
497 *
498 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
499 * in the structure for use by driver. This structure is places in that
500 * space.
fd1af15d
JB
501 *
502 * The common struct MUST be first because it is shared between
503 * 3945 and agn!
8d9698b3
RC
504 */
505struct iwl_station_priv {
fd1af15d 506 struct iwl_station_priv_common common;
8d9698b3 507 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
508 atomic_t pending_frames;
509 bool client;
510 bool asleep;
8d9698b3
RC
511};
512
fd1af15d
JB
513/**
514 * struct iwl_vif_priv - driver's private per-interface information
515 *
516 * When mac80211 allocates a virtual interface, it can allocate
517 * space for us to put data into.
518 */
519struct iwl_vif_priv {
246ed355 520 struct iwl_rxon_context *ctx;
fd1af15d
JB
521 u8 ibss_bssid_sta_id;
522};
523
5d08cd1d
CH
524/* one for each uCode image (inst/data, boot/init/runtime) */
525struct fw_desc {
526 void *v_addr; /* access by driver */
527 dma_addr_t p_addr; /* access by card's busmaster DMA */
528 u32 len; /* bytes */
529};
530
dd7a2509 531/* v1/v2 uCode file layout */
cc0f555d
JS
532struct iwl_ucode_header {
533 __le32 ver; /* major/minor/API/serial */
534 union {
535 struct {
536 __le32 inst_size; /* bytes of runtime code */
537 __le32 data_size; /* bytes of runtime data */
538 __le32 init_size; /* bytes of init code */
539 __le32 init_data_size; /* bytes of init data */
540 __le32 boot_size; /* bytes of bootstrap code */
541 u8 data[0]; /* in same order as sizes */
542 } v1;
543 struct {
544 __le32 build; /* build number */
545 __le32 inst_size; /* bytes of runtime code */
546 __le32 data_size; /* bytes of runtime data */
547 __le32 init_size; /* bytes of init code */
548 __le32 init_data_size; /* bytes of init data */
549 __le32 boot_size; /* bytes of bootstrap code */
550 u8 data[0]; /* in same order as sizes */
551 } v2;
552 } u;
5d08cd1d
CH
553};
554
dd7a2509
JB
555/*
556 * new TLV uCode file layout
557 *
558 * The new TLV file format contains TLVs, that each specify
559 * some piece of data. To facilitate "groups", for example
560 * different instruction image with different capabilities,
561 * bundled with the same init image, an alternative mechanism
562 * is provided:
563 * When the alternative field is 0, that means that the item
564 * is always valid. When it is non-zero, then it is only
565 * valid in conjunction with items of the same alternative,
566 * in which case the driver (user) selects one alternative
567 * to use.
568 */
569
570enum iwl_ucode_tlv_type {
571 IWL_UCODE_TLV_INVALID = 0, /* unused */
572 IWL_UCODE_TLV_INST = 1,
573 IWL_UCODE_TLV_DATA = 2,
574 IWL_UCODE_TLV_INIT = 3,
575 IWL_UCODE_TLV_INIT_DATA = 4,
576 IWL_UCODE_TLV_BOOT = 5,
577 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 578 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
579 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
580 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
581 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
582 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
583 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
584 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 585 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 586 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
dd7a2509
JB
587};
588
589struct iwl_ucode_tlv {
590 __le16 type; /* see above */
591 __le16 alternative; /* see comment */
592 __le32 length; /* not including type/length fields */
593 u8 data[0];
ba2d3587 594} __packed;
dd7a2509
JB
595
596#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
597
598struct iwl_tlv_ucode_header {
599 /*
600 * The TLV style ucode header is distinguished from
601 * the v1/v2 style header by first four bytes being
602 * zero, as such is an invalid combination of
603 * major/minor/API/serial versions.
604 */
605 __le32 zero;
606 __le32 magic;
607 u8 human_readable[64];
608 __le32 ver; /* major/minor/API/serial */
609 __le32 build;
610 __le64 alternatives; /* bitmask of valid alternatives */
611 /*
612 * The data contained herein has a TLV layout,
613 * see above for the TLV header and types.
614 * Note that each TLV is padded to a length
615 * that is a multiple of 4 for alignment.
616 */
617 u8 data[0];
618};
619
bb8c093b 620struct iwl4965_ibss_seq {
5d08cd1d
CH
621 u8 mac[ETH_ALEN];
622 u16 seq_num;
623 u16 frag_num;
624 unsigned long packet_time;
625 struct list_head list;
626};
627
f0832f13
EG
628struct iwl_sensitivity_ranges {
629 u16 min_nrg_cck;
630 u16 max_nrg_cck;
631
632 u16 nrg_th_cck;
633 u16 nrg_th_ofdm;
634
635 u16 auto_corr_min_ofdm;
636 u16 auto_corr_min_ofdm_mrc;
637 u16 auto_corr_min_ofdm_x1;
638 u16 auto_corr_min_ofdm_mrc_x1;
639
640 u16 auto_corr_max_ofdm;
641 u16 auto_corr_max_ofdm_mrc;
642 u16 auto_corr_max_ofdm_x1;
643 u16 auto_corr_max_ofdm_mrc_x1;
644
645 u16 auto_corr_max_cck;
646 u16 auto_corr_max_cck_mrc;
647 u16 auto_corr_min_cck;
648 u16 auto_corr_min_cck_mrc;
55036d66
WYG
649
650 u16 barker_corr_th_min;
651 u16 barker_corr_th_min_mrc;
652 u16 nrg_th_cca;
f0832f13
EG
653};
654
099b40b7 655
b5047f78
TW
656#define KELVIN_TO_CELSIUS(x) ((x)-273)
657#define CELSIUS_TO_KELVIN(x) ((x)+273)
658
659
bc47279f 660/**
5425e490 661 * struct iwl_hw_params
bc47279f 662 * @max_txq_num: Max # Tx queues supported
f3f911d1 663 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 664 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 665 * @tfd_size: TFD size
099b40b7
RR
666 * @tx/rx_chains_num: Number of TX/RX chains
667 * @valid_tx/rx_ant: usable antennas
bc47279f 668 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 669 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 670 * @rx_page_order: Rx buffer page order
141c43a3 671 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 672 * @max_stations:
7aafef1c 673 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
674 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
675 * @sw_crypto: 0 for hw, 1 for sw
676 * @max_xxx_size: for ucode uses
677 * @ct_kill_threshold: temperature threshold
a0ee74cf 678 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 679 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 680 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 681 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 682 */
5425e490 683struct iwl_hw_params {
f3f911d1
ZY
684 u8 max_txq_num;
685 u8 dma_chnl_num;
4ddbb7d0 686 u16 scd_bc_tbls_size;
a8e74e27 687 u32 tfd_size;
ec35cf2a
TW
688 u8 tx_chains_num;
689 u8 rx_chains_num;
690 u8 valid_tx_ant;
691 u8 valid_rx_ant;
5d08cd1d 692 u16 max_rxq_size;
ec35cf2a 693 u16 max_rxq_log;
2f301227 694 u32 rx_page_order;
141c43a3 695 u32 rx_wrt_ptr_reg;
5d08cd1d 696 u8 max_stations;
7aafef1c 697 u8 ht40_channel;
2c2f3b33 698 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
699 u32 max_inst_size;
700 u32 max_data_size;
701 u32 max_bsm_size;
702 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
703 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
704 /* for 1000, 6000 series and up */
a0ee74cf 705 u16 beacon_time_tsf_bits;
be5d56ed 706 u32 calib_init_cfg;
6d6a1afd 707 u32 calib_rt_cfg;
f0832f13 708 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
709};
710
5d08cd1d 711
5d08cd1d
CH
712/******************************************************************************
713 *
a33c2f47
EG
714 * Functions implemented in core module which are forward declared here
715 * for use by iwl-[4-5].c
5d08cd1d 716 *
a33c2f47
EG
717 * NOTE: The implementation of these functions are not hardware specific
718 * which is why they are in the core module files.
5d08cd1d
CH
719 *
720 * Naming convention --
a33c2f47 721 * iwl_ <-- Is part of iwlwifi
5d08cd1d 722 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
723 * iwl4965_bg_ <-- Called from work queue context
724 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
725 *
726 ****************************************************************************/
5b9f8cd3 727extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 728extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 729extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 730extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 731extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
732static inline int iwl_queue_used(const struct iwl_queue *q, int i)
733{
c8106d76 734 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
735 (i >= q->read_ptr && i < q->write_ptr) :
736 !(i < q->read_ptr && i >= q->write_ptr);
737}
738
739
740static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
741{
c8c24872
WYG
742 /*
743 * This is for init calibration result and scan command which
744 * required buffer > TFD_MAX_PAYLOAD_SIZE,
745 * the big buffer at end of command array
746 */
fd4abac5
TW
747 if (is_huge)
748 return q->n_window; /* must be power of 2 */
749
750 /* Otherwise, use normal size buffers */
751 return index & (q->n_window - 1);
752}
753
754
4ddbb7d0
TW
755struct iwl_dma_ptr {
756 dma_addr_t dma;
757 void *addr;
b481de9c
ZY
758 size_t size;
759};
760
b481de9c
ZY
761#define IWL_OPERATION_MODE_AUTO 0
762#define IWL_OPERATION_MODE_HT_ONLY 1
763#define IWL_OPERATION_MODE_MIXED 2
764#define IWL_OPERATION_MODE_20MHZ 3
765
3195cdb7
TW
766#define IWL_TX_CRC_SIZE 4
767#define IWL_TX_DELIMITER_SIZE 4
b481de9c 768
b481de9c 769#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 770
b481de9c 771/* Sensitivity and chain noise calibration */
b481de9c 772#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
773#define IWL4965_CAL_NUM_BEACONS 20
774#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
775#define MAXIMUM_ALLOWED_PATHLOSS 15
776
b481de9c
ZY
777#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
778
779#define MAX_FA_OFDM 50
780#define MIN_FA_OFDM 5
781#define MAX_FA_CCK 50
782#define MIN_FA_CCK 5
783
b481de9c
ZY
784#define AUTO_CORR_STEP_OFDM 1
785
b481de9c
ZY
786#define AUTO_CORR_STEP_CCK 3
787#define AUTO_CORR_MAX_TH_CCK 160
788
b481de9c
ZY
789#define NRG_DIFF 2
790#define NRG_STEP_CCK 2
791#define NRG_MARGIN 8
792#define MAX_NUMBER_CCK_NO_FA 100
793
794#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
795
796#define CHAIN_A 0
797#define CHAIN_B 1
798#define CHAIN_C 2
799#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
800#define ALL_BAND_FILTER 0xFF00
801#define IN_BAND_FILTER 0xFF
802#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
803
3195cdb7
TW
804#define NRG_NUM_PREV_STAT_L 20
805#define NUM_RX_CHAINS 3
806
bb8c093b 807enum iwl4965_false_alarm_state {
b481de9c
ZY
808 IWL_FA_TOO_MANY = 0,
809 IWL_FA_TOO_FEW = 1,
810 IWL_FA_GOOD_RANGE = 2,
811};
812
bb8c093b 813enum iwl4965_chain_noise_state {
b481de9c 814 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
815 IWL_CHAIN_NOISE_ACCUMULATE,
816 IWL_CHAIN_NOISE_CALIBRATED,
817 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
818};
819
bb8c093b 820enum iwl4965_calib_enabled_state {
b481de9c
ZY
821 IWL_CALIB_DISABLED = 0, /* must be 0 */
822 IWL_CALIB_ENABLED = 1,
823};
824
f69f42a6
TW
825
826/*
827 * enum iwl_calib
828 * defines the order in which results of initial calibrations
829 * should be sent to the runtime uCode
830 */
831enum iwl_calib {
832 IWL_CALIB_XTAL,
819500c5 833 IWL_CALIB_DC,
f69f42a6
TW
834 IWL_CALIB_LO,
835 IWL_CALIB_TX_IQ,
836 IWL_CALIB_TX_IQ_PERD,
201706ac 837 IWL_CALIB_BASE_BAND,
bf53f939 838 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
839 IWL_CALIB_MAX
840};
841
6e21f2c1
TW
842/* Opaque calibration results */
843struct iwl_calib_result {
844 void *buf;
845 size_t buf_len;
7c616cba
TW
846};
847
dbb983b7
RR
848enum ucode_type {
849 UCODE_NONE = 0,
850 UCODE_INIT,
851 UCODE_RT
852};
853
b481de9c 854/* Sensitivity calib data */
f0832f13 855struct iwl_sensitivity_data {
b481de9c
ZY
856 u32 auto_corr_ofdm;
857 u32 auto_corr_ofdm_mrc;
858 u32 auto_corr_ofdm_x1;
859 u32 auto_corr_ofdm_mrc_x1;
860 u32 auto_corr_cck;
861 u32 auto_corr_cck_mrc;
862
863 u32 last_bad_plcp_cnt_ofdm;
864 u32 last_fa_cnt_ofdm;
865 u32 last_bad_plcp_cnt_cck;
866 u32 last_fa_cnt_cck;
867
868 u32 nrg_curr_state;
869 u32 nrg_prev_state;
870 u32 nrg_value[10];
871 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
872 u32 nrg_silence_ref;
873 u32 nrg_energy_idx;
874 u32 nrg_silence_idx;
875 u32 nrg_th_cck;
876 s32 nrg_auto_corr_silence_diff;
877 u32 num_in_cck_no_fa;
878 u32 nrg_th_ofdm;
55036d66
WYG
879
880 u16 barker_corr_th_min;
881 u16 barker_corr_th_min_mrc;
882 u16 nrg_th_cca;
b481de9c
ZY
883};
884
885/* Chain noise (differential Rx gain) calib data */
f0832f13 886struct iwl_chain_noise_data {
04816448 887 u32 active_chains;
b481de9c
ZY
888 u32 chain_noise_a;
889 u32 chain_noise_b;
890 u32 chain_noise_c;
891 u32 chain_signal_a;
892 u32 chain_signal_b;
893 u32 chain_signal_c;
04816448 894 u16 beacon_count;
b481de9c
ZY
895 u8 disconn_array[NUM_RX_CHAINS];
896 u8 delta_gain_code[NUM_RX_CHAINS];
897 u8 radio_write;
04816448 898 u8 state;
b481de9c
ZY
899};
900
abceddb4
BC
901#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
902#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 903
20594eb0
WYG
904#define IWL_TRAFFIC_ENTRIES (256)
905#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 906
5d08cd1d
CH
907enum {
908 MEASUREMENT_READY = (1 << 0),
909 MEASUREMENT_ACTIVE = (1 << 1),
910};
911
0848e297
WYG
912enum iwl_nvm_type {
913 NVM_DEVICE_TYPE_EEPROM = 0,
914 NVM_DEVICE_TYPE_OTP,
915};
916
415e4993
WYG
917/*
918 * Two types of OTP memory access modes
919 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
920 * based on physical memory addressing
921 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
922 * based on logical memory addressing
923 */
924enum iwl_access_mode {
925 IWL_OTP_ACCESS_ABSOLUTE,
926 IWL_OTP_ACCESS_RELATIVE,
927};
65b7998a
WYG
928
929/**
930 * enum iwl_pa_type - Power Amplifier type
931 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
932 * @IWL_PA_INTERNAL: use Internal only
933 */
934enum iwl_pa_type {
935 IWL_PA_SYSTEM = 0,
740e7f51 936 IWL_PA_INTERNAL = 1,
65b7998a
WYG
937};
938
a83b9141
WYG
939/* interrupt statistics */
940struct isr_statistics {
941 u32 hw;
942 u32 sw;
6e6ebf4b 943 u32 err_code;
a83b9141
WYG
944 u32 sch;
945 u32 alive;
946 u32 rfkill;
947 u32 ctkill;
948 u32 wakeup;
949 u32 rx;
950 u32 rx_handlers[REPLY_MAX];
951 u32 tx;
952 u32 unhandled;
953};
5d08cd1d 954
91835ba4
WYG
955/* reply_tx_statistics (for _agn devices) */
956struct reply_tx_error_statistics {
957 u32 pp_delay;
958 u32 pp_few_bytes;
959 u32 pp_bt_prio;
960 u32 pp_quiet_period;
961 u32 pp_calc_ttak;
962 u32 int_crossed_retry;
963 u32 short_limit;
964 u32 long_limit;
965 u32 fifo_underrun;
966 u32 drain_flow;
967 u32 rfkill_flush;
968 u32 life_expire;
969 u32 dest_ps;
970 u32 host_abort;
971 u32 bt_retry;
972 u32 sta_invalid;
973 u32 frag_drop;
974 u32 tid_disable;
975 u32 fifo_flush;
976 u32 insuff_cf_poll;
977 u32 fail_hw_drop;
978 u32 sta_color_mismatch;
979 u32 unknown;
980};
981
814665fe
WYG
982/* reply_agg_tx_statistics (for _agn devices) */
983struct reply_agg_tx_error_statistics {
984 u32 underrun;
985 u32 bt_prio;
986 u32 few_bytes;
987 u32 abort;
988 u32 last_sent_ttl;
989 u32 last_sent_try;
990 u32 last_sent_bt_kill;
991 u32 scd_query;
992 u32 bad_crc32;
993 u32 response;
994 u32 dump_tx;
995 u32 delay_tx;
996 u32 unknown;
997};
998
22fdf3c9
WYG
999#ifdef CONFIG_IWLWIFI_DEBUGFS
1000/* management statistics */
1001enum iwl_mgmt_stats {
1002 MANAGEMENT_ASSOC_REQ = 0,
1003 MANAGEMENT_ASSOC_RESP,
1004 MANAGEMENT_REASSOC_REQ,
1005 MANAGEMENT_REASSOC_RESP,
1006 MANAGEMENT_PROBE_REQ,
1007 MANAGEMENT_PROBE_RESP,
1008 MANAGEMENT_BEACON,
1009 MANAGEMENT_ATIM,
1010 MANAGEMENT_DISASSOC,
1011 MANAGEMENT_AUTH,
1012 MANAGEMENT_DEAUTH,
1013 MANAGEMENT_ACTION,
1014 MANAGEMENT_MAX,
1015};
1016/* control statistics */
1017enum iwl_ctrl_stats {
1018 CONTROL_BACK_REQ = 0,
1019 CONTROL_BACK,
1020 CONTROL_PSPOLL,
1021 CONTROL_RTS,
1022 CONTROL_CTS,
1023 CONTROL_ACK,
1024 CONTROL_CFEND,
1025 CONTROL_CFENDACK,
1026 CONTROL_MAX,
1027};
1028
1029struct traffic_stats {
1030 u32 mgmt[MANAGEMENT_MAX];
1031 u32 ctrl[CONTROL_MAX];
1032 u32 data_cnt;
1033 u64 data_bytes;
1034};
1035#else
1036struct traffic_stats {
1037 u64 data_bytes;
1038};
1039#endif
1040
0924e519
WYG
1041/*
1042 * iwl_switch_rxon: "channel switch" structure
1043 *
1044 * @ switch_in_progress: channel switch in progress
1045 * @ channel: new channel
1046 */
1047struct iwl_switch_rxon {
1048 bool switch_in_progress;
1049 __le16 channel;
1050};
1051
a9e1cb6a
WYG
1052/*
1053 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
1054 * to perform continuous uCode event logging operation if enabled
1055 */
1056#define UCODE_TRACE_PERIOD (100)
1057
1058/*
1059 * iwl_event_log: current uCode event log position
1060 *
1061 * @ucode_trace: enable/disable ucode continuous trace timer
1062 * @num_wraps: how many times the event buffer wraps
1063 * @next_entry: the entry just before the next one that uCode would fill
1064 * @non_wraps_count: counter for no wrap detected when dump ucode events
1065 * @wraps_once_count: counter for wrap once detected when dump ucode events
1066 * @wraps_more_count: counter for wrap more than once detected
1067 * when dump ucode events
1068 */
1069struct iwl_event_log {
1070 bool ucode_trace;
1071 u32 num_wraps;
1072 u32 next_entry;
1073 int non_wraps_count;
1074 int wraps_once_count;
1075 int wraps_more_count;
1076};
1077
2be76703
WYG
1078/*
1079 * host interrupt timeout value
1080 * used with setting interrupt coalescing timer
1081 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1082 *
1083 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1084 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1085 */
1086#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1087#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1088#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1089#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1090#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1091#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1092
3e4fb5fa
TAN
1093/*
1094 * This is the threshold value of plcp error rate per 100mSecs. It is
1095 * used to set and check for the validity of plcp_delta.
1096 */
680788ac 1097#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1098#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1099#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1100#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1101#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1102#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1103
8a472da4
WYG
1104#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1105#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1106
b74e31a9 1107/* timer constants use to monitor and recover stuck tx queues in mSecs */
ce60659a
WYG
1108#define IWL_DEF_MONITORING_PERIOD (1000)
1109#define IWL_LONG_MONITORING_PERIOD (5000)
b74e31a9 1110#define IWL_ONE_HUNDRED_MSECS (100)
7bdc473c 1111#define IWL_MAX_MONITORING_PERIOD (60000)
b74e31a9 1112
bee008b7
WYG
1113/* BT Antenna Coupling Threshold (dB) */
1114#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1115
a93e7973
WYG
1116enum iwl_reset {
1117 IWL_RF_RESET = 0,
1118 IWL_FW_RESET,
8a472da4
WYG
1119 IWL_MAX_FORCE_RESET,
1120};
1121
1122struct iwl_force_reset {
1123 int reset_request_count;
1124 int reset_success_count;
1125 int reset_reject_count;
1126 unsigned long reset_duration;
1127 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1128};
1129
a0ee74cf
WYG
1130/* extend beacon time format bit shifting */
1131/*
1132 * for _3945 devices
1133 * bits 31:24 - extended
1134 * bits 23:0 - interval
1135 */
1136#define IWL3945_EXT_BEACON_TIME_POS 24
1137/*
1138 * for _agn devices
1139 * bits 31:22 - extended
1140 * bits 21:0 - interval
1141 */
1142#define IWLAGN_EXT_BEACON_TIME_POS 22
1143
246ed355
JB
1144enum iwl_rxon_context_id {
1145 IWL_RXON_CTX_BSS,
ece9c4ee 1146 IWL_RXON_CTX_PAN,
246ed355
JB
1147
1148 NUM_IWL_RXON_CTX
1149};
1150
1151struct iwl_rxon_context {
8bd413e6 1152 struct ieee80211_vif *vif;
e72f368b
JB
1153
1154 const u8 *ac_to_fifo;
1155 const u8 *ac_to_queue;
1156 u8 mcast_queue;
1157
763cc3bf
JB
1158 /*
1159 * We could use the vif to indicate active, but we
1160 * also need it to be active during disabling when
1161 * we already removed the vif for type setting.
1162 */
1163 bool always_active, is_active;
1164
246ed355 1165 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1166
1167 u32 interface_modes, exclusive_interface_modes;
1168 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1169
246ed355
JB
1170 /*
1171 * We declare this const so it can only be
1172 * changed via explicit cast within the
1173 * routines that actually update the physical
1174 * hardware.
1175 */
1176 const struct iwl_rxon_cmd active;
1177 struct iwl_rxon_cmd staging;
1178
1179 struct iwl_rxon_time_cmd timing;
a194e324 1180
8dfdb9d5
JB
1181 struct iwl_qos_info qos_data;
1182
2995bafa 1183 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1184
1185 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1186 u8 qos_cmd;
c10afb6e
JB
1187 u8 wep_key_cmd;
1188
1189 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1190 u8 key_mapping_keys;
770e13bd
JB
1191
1192 __le32 station_flags;
7e6a5886
JB
1193
1194 struct {
1195 bool non_gf_sta_present;
1196 u8 protection;
1197 bool enabled, is_40mhz;
1198 u8 extension_chan_offset;
1199 } ht;
246ed355
JB
1200};
1201
c79dd5b5 1202struct iwl_priv {
5d08cd1d
CH
1203
1204 /* ieee device used by generic ieee processing code */
1205 struct ieee80211_hw *hw;
1206 struct ieee80211_channel *ieee_channels;
1207 struct ieee80211_rate *ieee_rates;
82b9a121 1208 struct iwl_cfg *cfg;
5d08cd1d
CH
1209
1210 /* temporary frame storage list */
1211 struct list_head free_frames;
1212 int frames_count;
1213
8318d78a 1214 enum ieee80211_band band;
2f301227 1215 int alloc_rxb_page;
5d08cd1d 1216
c79dd5b5 1217 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1218 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1219
8318d78a 1220 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1221
5d08cd1d 1222 /* spectrum measurement report caching */
2aa6ab86 1223 struct iwl_spectrum_notification measure_report;
5d08cd1d 1224 u8 measurement_status;
81963d68 1225
5d08cd1d
CH
1226 /* ucode beacon time */
1227 u32 ucode_beacon_time;
a13d276f 1228 int missed_beacon_threshold;
5d08cd1d 1229
a85d7cca
JB
1230 /* track IBSS manager (last beacon) status */
1231 u32 ibss_manager;
1232
3e4fb5fa
TAN
1233 /* storing the jiffies when the plcp error rate is received */
1234 unsigned long plcp_jiffies;
1235
a93e7973 1236 /* force reset */
8a472da4 1237 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1238
5a2a780c 1239 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1240 * Access via channel # using indirect index array */
bf85ea4f 1241 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1242 u8 channel_count; /* # of channels */
1243
5d08cd1d
CH
1244 /* thermal calibration */
1245 s32 temperature; /* degrees Kelvin */
1246 s32 last_temperature;
1247
7c616cba 1248 /* init calibration results */
6e21f2c1 1249 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1250
5d08cd1d 1251 /* Scan related variables */
5d08cd1d 1252 unsigned long scan_start;
5d08cd1d 1253 unsigned long scan_start_tsf;
811ecc99 1254 void *scan_cmd;
00700ee0 1255 enum ieee80211_band scan_band;
1ecf9fc1 1256 struct cfg80211_scan_request *scan_request;
f84b29ec 1257 struct ieee80211_vif *scan_vif;
afbdd69a 1258 bool is_internal_short_scan;
76eff18b
TW
1259 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1260 u8 mgmt_tx_ant;
5d08cd1d
CH
1261
1262 /* spinlock */
1263 spinlock_t lock; /* protect general shared data */
1264 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1265 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1266 struct mutex mutex;
d2dfe6df 1267 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1268
1269 /* basic pci-network driver stuff */
1270 struct pci_dev *pci_dev;
1271
1272 /* pci hardware address support */
1273 void __iomem *hw_base;
b661c819
TW
1274 u32 hw_rev;
1275 u32 hw_wa_rev;
1276 u8 rev_id;
5d08cd1d 1277
246ed355
JB
1278 /* microcode/device supports multiple contexts */
1279 u8 valid_contexts;
1280
13bb9483
JB
1281 /* command queue number */
1282 u8 cmd_queue;
1283
c10afb6e
JB
1284 /* max number of station keys */
1285 u8 sta_key_max_num;
1286
c6fa17ed
WYG
1287 /* EEPROM MAC addresses */
1288 struct mac_address addresses[2];
1289
5d08cd1d 1290 /* uCode images, save to reload in case of failure */
b08dfd04 1291 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1292 u32 ucode_ver; /* version of ucode, copy of
1293 iwl_ucode.ver */
5d08cd1d
CH
1294 struct fw_desc ucode_code; /* runtime inst */
1295 struct fw_desc ucode_data; /* runtime data original */
1296 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1297 struct fw_desc ucode_init; /* initialization inst */
1298 struct fw_desc ucode_init_data; /* initialization data */
1299 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1300 enum ucode_type ucode_type;
1301 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1302 char firmware_name[25];
5d08cd1d 1303
246ed355 1304 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1305
0924e519
WYG
1306 struct iwl_switch_rxon switch_rxon;
1307
5d08cd1d 1308 /* 1st responses from initialize and runtime uCode images.
5a2a780c 1309 * _agn's initialize alive response contains some calibration data. */
885ba202
TW
1310 struct iwl_init_alive_resp card_alive_init;
1311 struct iwl_alive_resp card_alive;
5d08cd1d 1312
ab53d8af
MA
1313 unsigned long last_blink_time;
1314 u8 last_blink_rate;
1315 u8 allow_blinking;
1316 u64 led_tpt;
e932a609 1317
5d08cd1d 1318 u16 active_rate;
5d08cd1d 1319
5d08cd1d 1320 u8 start_calib;
f0832f13
EG
1321 struct iwl_sensitivity_data sensitivity_data;
1322 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1323 bool enhance_sensitivity_table;
5d08cd1d 1324 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1325 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1326
fad95bf5 1327 struct iwl_ht_config current_ht_config;
5d08cd1d 1328
5d08cd1d 1329 /* Rate scaling data */
5d08cd1d
CH
1330 u8 retry_rate;
1331
1332 wait_queue_head_t wait_command_queue;
1333
1334 int activity_timer_active;
1335
1336 /* Rx and Tx DMA processing queues */
a55360e4 1337 struct iwl_rx_queue rxq;
88804e2b 1338 struct iwl_tx_queue *txq;
5d08cd1d 1339 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1340 struct iwl_dma_ptr kw; /* keep warm address */
1341 struct iwl_dma_ptr scd_bc_tbls;
1342
5d08cd1d
CH
1343 u32 scd_base_addr; /* scheduler sram base address */
1344
1345 unsigned long status;
5d08cd1d 1346
19758bef 1347 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1348 struct traffic_stats tx_stats;
1349 struct traffic_stats rx_stats;
19758bef 1350
a83b9141
WYG
1351 /* counts interrupts */
1352 struct isr_statistics isr_stats;
1353
5da4b55f 1354 struct iwl_power_mgr power_data;
3ad3b92a 1355 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1356
5d08cd1d 1357 /* context information */
59c02b41 1358 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
5d08cd1d 1359
9c5ac091
RC
1360 /* station table variables */
1361
1362 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1363 spinlock_t sta_lock;
1364 int num_stations;
6def9761 1365 struct iwl_station_entry stations[IWL_STATION_COUNT];
80fb47a1 1366 unsigned long ucode_key_table;
5d08cd1d 1367
e4e72fb4
JB
1368 /* queue refcounts */
1369#define IWL_MAX_HW_QUEUES 32
1370 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1371 /* for each AC */
1372 atomic_t queue_stop_count[4];
1373
5d08cd1d 1374 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1375 u8 is_open;
5d08cd1d
CH
1376
1377 u8 mac80211_registered;
5d08cd1d 1378
af6b8ee3 1379 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1380 u8 *eeprom;
0848e297 1381 int nvm_device_type;
073d3f5f 1382 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1383
05c914fe 1384 enum nl80211_iftype iw_mode;
5d08cd1d 1385
5d08cd1d 1386 /* Last Rx'd beacon timestamp */
3109ece1 1387 u64 timestamp;
5d08cd1d 1388
ee525d13
JB
1389 union {
1390#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1391 struct {
1392 void *shared_virt;
1393 dma_addr_t shared_phys;
1394
1395 struct delayed_work thermal_periodic;
1396 struct delayed_work rfkill_poll;
1397
1398 struct iwl3945_notif_statistics statistics;
d73e4923 1399#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK
1400 struct iwl3945_notif_statistics accum_statistics;
1401 struct iwl3945_notif_statistics delta_statistics;
1402 struct iwl3945_notif_statistics max_delta;
1403#endif
ee525d13
JB
1404
1405 u32 sta_supp_rates;
e99f168c
JB
1406 int last_rx_rssi; /* From Rx packet statistics */
1407
1408 /* Rx'd packet timing information */
1409 u32 last_beacon_time;
1410 u64 last_tsf;
67d613ae
JB
1411
1412 /*
1413 * each calibration channel group in the
1414 * EEPROM has a derived clip setting for
1415 * each rate.
1416 */
1417 const struct iwl3945_clip_group clip_groups[5];
1418
ee525d13 1419 } _3945;
a4c8b2a6
JB
1420#endif
1421#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1422 struct {
1423 /* INT ICT Table */
1424 __le32 *ict_tbl;
1425 void *ict_tbl_vir;
1426 dma_addr_t ict_tbl_dma;
1427 dma_addr_t aligned_ict_tbl_dma;
1428 int ict_index;
1429 u32 inta;
1430 bool use_ict;
d5a0ffa3
WYG
1431 /*
1432 * reporting the number of tids has AGG on. 0 means
1433 * no AGGREGATION
1434 */
1435 u8 agg_tids_count;
05d57520
JB
1436
1437 struct iwl_rx_phy_res last_phy_res;
1438 bool last_phy_res_valid;
a15707d8
RC
1439
1440 struct completion firmware_loading_complete;
a2064b7a 1441
b2e640d4
JB
1442 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1443 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
f3aebeee 1444
6a822d06
WYG
1445 /*
1446 * chain noise reset and gain commands are the
1447 * two extra calibration commands follows the standard
1448 * phy calibration commands
1449 */
1450 u8 phy_calib_chain_noise_reset_cmd;
1451 u8 phy_calib_chain_noise_gain_cmd;
1452
f3aebeee 1453 struct iwl_notif_statistics statistics;
7980fba5 1454 struct iwl_bt_notif_statistics statistics_bt;
91835ba4
WYG
1455 /* counts reply_tx error */
1456 struct reply_tx_error_statistics reply_tx_stats;
814665fe 1457 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
f3aebeee
WYG
1458#ifdef CONFIG_IWLWIFI_DEBUGFS
1459 struct iwl_notif_statistics accum_statistics;
1460 struct iwl_notif_statistics delta_statistics;
1461 struct iwl_notif_statistics max_delta;
7980fba5
WYG
1462 struct iwl_bt_notif_statistics accum_statistics_bt;
1463 struct iwl_bt_notif_statistics delta_statistics_bt;
1464 struct iwl_bt_notif_statistics max_delta_bt;
f3aebeee 1465#endif
a4c8b2a6 1466 } _agn;
ee525d13
JB
1467#endif
1468 };
1469
22bf59a0 1470 /* bt coex */
da5dbb97 1471 u8 bt_status;
59079949 1472 u8 bt_traffic_load, notif_bt_traffic_load;
f37837c9 1473 bool bt_ch_announce;
9e4afc21 1474 bool bt_sco_active;
bee008b7
WYG
1475 bool bt_full_concurrent;
1476 bool bt_ant_couple_ok;
fbba9410
WYG
1477 __le32 kill_ack_mask;
1478 __le32 kill_cts_mask;
1479 __le16 bt_valid;
22bf59a0
WYG
1480 u16 bt_on_thresh;
1481 u16 bt_duration;
1482 u16 dynamic_frag_thresh;
1483 u16 dynamic_agg_thresh;
bee008b7 1484 u8 bt_ci_compliance;
9e4afc21
JB
1485 struct work_struct bt_traffic_change_work;
1486
5425e490 1487 struct iwl_hw_params hw_params;
4ddbb7d0 1488
40cefda9 1489 u32 inta_mask;
5d08cd1d 1490
5d08cd1d
CH
1491 struct workqueue_struct *workqueue;
1492
5d08cd1d 1493 struct work_struct restart;
5d08cd1d
CH
1494 struct work_struct scan_completed;
1495 struct work_struct rx_replenish;
5d08cd1d 1496 struct work_struct abort_scan;
12e934dc 1497
5d08cd1d 1498 struct work_struct beacon_update;
76d04815 1499 struct iwl_rxon_context *beacon_ctx;
12e934dc 1500 struct sk_buff *beacon_skb;
76d04815 1501
a28027cd
WYG
1502 struct work_struct tt_work;
1503 struct work_struct ct_enter;
1504 struct work_struct ct_exit;
88be0264 1505 struct work_struct start_internal_scan;
65550636 1506 struct work_struct tx_flush;
bee008b7 1507 struct work_struct bt_full_concurrency;
fbba9410 1508 struct work_struct bt_runtime_config;
5d08cd1d
CH
1509
1510 struct tasklet_struct irq_tasklet;
1511
1512 struct delayed_work init_alive_start;
1513 struct delayed_work alive_start;
5d08cd1d 1514 struct delayed_work scan_check;
4a8a4322 1515
630fe9b6
TW
1516 /* TX Power */
1517 s8 tx_power_user_lmt;
dc1b0973 1518 s8 tx_power_device_lmt;
ae16fc3c 1519 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
5d08cd1d 1520
5d08cd1d 1521
d08853a3 1522#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1523 /* debugging info */
3d816c77
RC
1524 u32 debug_level; /* per device debugging will override global
1525 iwl_debug_level if set */
d73e4923 1526#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1527#ifdef CONFIG_IWLWIFI_DEBUGFS
1528 /* debugfs */
20594eb0
WYG
1529 u16 tx_traffic_idx;
1530 u16 rx_traffic_idx;
1531 u8 *tx_traffic;
1532 u8 *rx_traffic;
4c84a8f1
JB
1533 struct dentry *debugfs_dir;
1534 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1535 bool disable_ht40;
712b6cf5 1536#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1537
1538 struct work_struct txpower_work;
445c2dff
TW
1539 u32 disable_sens_cal;
1540 u32 disable_chain_noise_cal;
203566f3 1541 u32 disable_tx_power_cal;
16e727e8 1542 struct work_struct run_time_calib_work;
5d08cd1d 1543 struct timer_list statistics_periodic;
a9e1cb6a 1544 struct timer_list ucode_trace;
b74e31a9 1545 struct timer_list monitor_recover;
086ed117 1546 bool hw_ready;
a9e1cb6a
WYG
1547
1548 struct iwl_event_log event_log;
c79dd5b5 1549}; /*iwl_priv */
5d08cd1d 1550
36470749
RR
1551static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1552{
1553 set_bit(txq_id, &priv->txq_ctx_active_msk);
1554}
1555
1556static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1557{
1558 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1559}
1560
994d31f7 1561#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1562/*
1563 * iwl_get_debug_level: Return active debug level for device
1564 *
1565 * Using sysfs it is possible to set per device debug level. This debug
1566 * level will be used if set, otherwise the global debug level which can be
1567 * set via module parameter is used.
1568 */
1569static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1570{
1571 if (priv->debug_level)
1572 return priv->debug_level;
1573 else
1574 return iwl_debug_level;
1575}
a332f8d6 1576#else
3d816c77
RC
1577static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1578{
1579 return iwl_debug_level;
1580}
a332f8d6
TW
1581#endif
1582
1583
a332f8d6
TW
1584static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1585 int txq_id, int idx)
1586{
ff0d91c3 1587 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1588 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1589 txb[idx].skb->data;
a332f8d6
TW
1590 return NULL;
1591}
a332f8d6 1592
246ed355
JB
1593static inline struct iwl_rxon_context *
1594iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1595{
1596 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1597
1598 return vif_priv->ctx;
1599}
1600
1601#define for_each_context(priv, ctx) \
1602 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1603 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1604 if (priv->valid_contexts & BIT(ctx->ctxid))
1605
1606static inline int iwl_is_associated(struct iwl_priv *priv,
1607 enum iwl_rxon_context_id ctxid)
1608{
1609 return (priv->contexts[ctxid].active.filter_flags &
1610 RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1611}
1612
1613static inline int iwl_is_any_associated(struct iwl_priv *priv)
1614{
1615 return iwl_is_associated(priv, IWL_RXON_CTX_BSS);
1616}
a332f8d6 1617
246ed355 1618static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
5d08cd1d 1619{
246ed355 1620 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
5d08cd1d
CH
1621}
1622
bf85ea4f 1623static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1624{
1625 if (ch_info == NULL)
1626 return 0;
1627 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1628}
1629
bf85ea4f 1630static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1631{
1632 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1633}
1634
bf85ea4f 1635static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1636{
8318d78a 1637 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1638}
1639
bf85ea4f 1640static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1641{
8318d78a 1642 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1643}
1644
bf85ea4f 1645static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1646{
1647 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1648}
1649
bf85ea4f 1650static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1651{
1652 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1653}
1654
64a76b50
ZY
1655static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1656{
1657 __free_pages(page, priv->hw_params.rx_page_order);
1658 priv->alloc_rxb_page--;
1659}
1660
1661static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1662{
1663 free_pages(page, priv->hw_params.rx_page_order);
1664 priv->alloc_rxb_page--;
1665}
be1f3ab6 1666#endif /* __iwl_dev_h__ */