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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
fcd427bb | 26 | /* |
3e0d4cb1 | 27 | * Please use this file (iwl-dev.h) for driver implementation definitions. |
5a36ba0e | 28 | * Please use iwl-commands.h for uCode API definitions. |
fcd427bb BC |
29 | */ |
30 | ||
be1f3ab6 EG |
31 | #ifndef __iwl_dev_h__ |
32 | #define __iwl_dev_h__ | |
b481de9c | 33 | |
5d08cd1d CH |
34 | #include <linux/pci.h> /* for struct pci_device_id */ |
35 | #include <linux/kernel.h> | |
7194207c | 36 | #include <linux/wait.h> |
5ed540ae | 37 | #include <linux/leds.h> |
5d08cd1d CH |
38 | #include <net/ieee80211_radiotap.h> |
39 | ||
6bc913bd | 40 | #include "iwl-eeprom.h" |
6f83eaa1 | 41 | #include "iwl-csr.h" |
5d08cd1d | 42 | #include "iwl-prph.h" |
dbb6654c | 43 | #include "iwl-fh.h" |
0a6857e7 | 44 | #include "iwl-debug.h" |
b744cb79 | 45 | #include "iwl-agn-hw.h" |
ab53d8af | 46 | #include "iwl-led.h" |
5da4b55f | 47 | #include "iwl-power.h" |
e227ceac | 48 | #include "iwl-agn-rs.h" |
0975cc8f | 49 | #include "iwl-agn-tt.h" |
41c50542 | 50 | #include "iwl-trans.h" |
5d08cd1d | 51 | |
48d1a211 EG |
52 | #define DRV_NAME "iwlagn" |
53 | ||
672639de WYG |
54 | struct iwl_tx_queue; |
55 | ||
099b40b7 | 56 | /* CT-KILL constants */ |
672639de WYG |
57 | #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */ |
58 | #define CT_KILL_THRESHOLD 114 /* in Celsius */ | |
59 | #define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ | |
4bf775cd | 60 | |
5d08cd1d CH |
61 | /* Default noise level to report when noise measurement is not available. |
62 | * This may be because we're: | |
63 | * 1) Not associated (4965, no beacon statistics being sent to driver) | |
64 | * 2) Scanning (noise measurement does not apply to associated channel) | |
65 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
66 | * Use default noise value of -127 ... this is below the range of measurable | |
67 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
68 | * Also, -127 works better than 0 when averaging frames with/without | |
69 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
70 | * always negative ... using a negative value as the default keeps all | |
71 | * averages within an s8's (used in some apps) range of negative values. */ | |
72 | #define IWL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
73 | ||
5d08cd1d CH |
74 | /* |
75 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
76 | * Per spec: | |
77 | * a value of 0 means RTS on all data/management packets | |
78 | * a value > max MSDU size means no RTS | |
79 | * else RTS for data/management frames where MPDU is larger | |
80 | * than RTS value. | |
81 | */ | |
82 | #define DEFAULT_RTS_THRESHOLD 2347U | |
83 | #define MIN_RTS_THRESHOLD 0U | |
84 | #define MAX_RTS_THRESHOLD 2347U | |
85 | #define MAX_MSDU_SIZE 2304U | |
86 | #define MAX_MPDU_SIZE 2346U | |
51b7ef05 | 87 | #define DEFAULT_BEACON_INTERVAL 200U |
5d08cd1d CH |
88 | #define DEFAULT_SHORT_RETRY_LIMIT 7U |
89 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
90 | ||
a55360e4 | 91 | struct iwl_rx_mem_buffer { |
2f301227 ZY |
92 | dma_addr_t page_dma; |
93 | struct page *page; | |
5d08cd1d CH |
94 | struct list_head list; |
95 | }; | |
96 | ||
2f301227 ZY |
97 | #define rxb_addr(r) page_address(r->page) |
98 | ||
c2acea8e JB |
99 | /* defined below */ |
100 | struct iwl_device_cmd; | |
101 | ||
102 | struct iwl_cmd_meta { | |
103 | /* only for SYNC commands, iff the reply skb is wanted */ | |
104 | struct iwl_host_cmd *source; | |
105 | /* | |
106 | * only for ASYNC commands | |
107 | * (which is somewhat stupid -- look at iwl-sta.c for instance | |
108 | * which duplicates a bunch of code because the callback isn't | |
109 | * invoked for SYNC commands, if it were and its result passed | |
110 | * through it would be simpler...) | |
111 | */ | |
5696aea6 JB |
112 | void (*callback)(struct iwl_priv *priv, |
113 | struct iwl_device_cmd *cmd, | |
2f301227 | 114 | struct iwl_rx_packet *pkt); |
c2acea8e | 115 | |
c2acea8e JB |
116 | u32 flags; |
117 | ||
2e724443 FT |
118 | DEFINE_DMA_UNMAP_ADDR(mapping); |
119 | DEFINE_DMA_UNMAP_LEN(len); | |
c2acea8e JB |
120 | }; |
121 | ||
5d08cd1d CH |
122 | /* |
123 | * Generic queue structure | |
124 | * | |
4ce7cc2b JB |
125 | * Contains common data for Rx and Tx queues. |
126 | * | |
127 | * Note the difference between n_bd and n_window: the hardware | |
128 | * always assumes 256 descriptors, so n_bd is always 256 (unless | |
129 | * there might be HW changes in the future). For the normal TX | |
130 | * queues, n_window, which is the size of the software queue data | |
131 | * is also 256; however, for the command queue, n_window is only | |
132 | * 32 since we don't need so many commands pending. Since the HW | |
133 | * still uses 256 BDs for DMA though, n_bd stays 256. As a result, | |
134 | * the software buffers (in the variables @meta, @txb in struct | |
135 | * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds | |
136 | * in the same struct) have 256. | |
137 | * This means that we end up with the following: | |
138 | * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | | |
139 | * SW entries: | 0 | ... | 31 | | |
140 | * where N is a number between 0 and 7. This means that the SW | |
141 | * data is a window overlayed over the HW queue. | |
5d08cd1d | 142 | */ |
443cfd45 | 143 | struct iwl_queue { |
5d08cd1d CH |
144 | int n_bd; /* number of BDs in this queue */ |
145 | int write_ptr; /* 1-st empty entry (index) host_w*/ | |
146 | int read_ptr; /* last used entry (index) host_r*/ | |
b74e31a9 | 147 | /* use for monitoring and recovering the stuck queue */ |
5d08cd1d CH |
148 | dma_addr_t dma_addr; /* physical addr for BD's */ |
149 | int n_window; /* safe queue window */ | |
150 | u32 id; | |
151 | int low_mark; /* low watermark, resume queue if free | |
152 | * space more than this */ | |
153 | int high_mark; /* high watermark, stop queue if free | |
154 | * space less than this */ | |
a839cf69 | 155 | }; |
5d08cd1d | 156 | |
bc47279f | 157 | /* One for each TFD */ |
8567c63e | 158 | struct iwl_tx_info { |
ff0d91c3 | 159 | struct sk_buff *skb; |
c90cbbbd | 160 | struct iwl_rxon_context *ctx; |
5d08cd1d CH |
161 | }; |
162 | ||
163 | /** | |
16466903 | 164 | * struct iwl_tx_queue - Tx Queue for DMA |
bc47279f BC |
165 | * @q: generic Rx/Tx queue descriptor |
166 | * @bd: base of circular buffer of TFDs | |
c2acea8e JB |
167 | * @cmd: array of command/TX buffer pointers |
168 | * @meta: array of meta data for each command/tx buffer | |
bc47279f BC |
169 | * @dma_addr_cmd: physical address of cmd/tx buffer array |
170 | * @txb: array of per-TFD driver data | |
22de94de | 171 | * @time_stamp: time (in jiffies) of last read_ptr change |
bc47279f BC |
172 | * @need_update: indicates need to update read/write index |
173 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
5d08cd1d | 174 | * |
bc47279f BC |
175 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame |
176 | * descriptors) and required locking structures. | |
5d08cd1d | 177 | */ |
188cf6c7 SO |
178 | #define TFD_TX_CMD_SLOTS 256 |
179 | #define TFD_CMD_SLOTS 32 | |
180 | ||
16466903 | 181 | struct iwl_tx_queue { |
443cfd45 | 182 | struct iwl_queue q; |
4ce7cc2b | 183 | struct iwl_tfd *tfds; |
c2acea8e JB |
184 | struct iwl_device_cmd **cmd; |
185 | struct iwl_cmd_meta *meta; | |
8567c63e | 186 | struct iwl_tx_info *txb; |
22de94de | 187 | unsigned long time_stamp; |
3fd07a1e TW |
188 | u8 need_update; |
189 | u8 sched_retry; | |
190 | u8 active; | |
191 | u8 swq_id; | |
5d08cd1d CH |
192 | }; |
193 | ||
194 | #define IWL_NUM_SCAN_RATES (2) | |
195 | ||
5d08cd1d CH |
196 | /* |
197 | * One for each channel, holds all channel setup data | |
198 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
199 | * with one another! | |
200 | */ | |
bf85ea4f | 201 | struct iwl_channel_info { |
073d3f5f | 202 | struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */ |
7aafef1c WYG |
203 | struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for |
204 | * HT40 channel */ | |
5d08cd1d CH |
205 | |
206 | u8 channel; /* channel number */ | |
207 | u8 flags; /* flags copied from EEPROM */ | |
208 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
fcd427bb | 209 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ |
5d08cd1d CH |
210 | s8 min_power; /* always 0 */ |
211 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
212 | ||
213 | u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */ | |
214 | u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */ | |
8318d78a | 215 | enum ieee80211_band band; |
5d08cd1d | 216 | |
7aafef1c WYG |
217 | /* HT40 channel info */ |
218 | s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
7aafef1c WYG |
219 | u8 ht40_flags; /* flags copied from EEPROM */ |
220 | u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ | |
5d08cd1d CH |
221 | }; |
222 | ||
751ca305 | 223 | #define IWL_TX_FIFO_BK 0 /* shared */ |
edc1a3a0 | 224 | #define IWL_TX_FIFO_BE 1 |
751ca305 | 225 | #define IWL_TX_FIFO_VI 2 /* shared */ |
edc1a3a0 | 226 | #define IWL_TX_FIFO_VO 3 |
751ca305 JB |
227 | #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK |
228 | #define IWL_TX_FIFO_BE_IPAN 4 | |
229 | #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI | |
230 | #define IWL_TX_FIFO_VO_IPAN 5 | |
edc1a3a0 | 231 | #define IWL_TX_FIFO_UNUSED -1 |
5d08cd1d | 232 | |
01a7e084 RC |
233 | /* Minimum number of queues. MAX_NUM is defined in hw specific files. |
234 | * Set the minimum to accommodate the 4 standard TX queues, 1 command | |
235 | * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */ | |
236 | #define IWL_MIN_NUM_QUEUES 10 | |
5d08cd1d | 237 | |
bd35f150 | 238 | /* |
13bb9483 | 239 | * Command queue depends on iPAN support. |
bd35f150 | 240 | */ |
13bb9483 JB |
241 | #define IWL_DEFAULT_CMD_QUEUE_NUM 4 |
242 | #define IWL_IPAN_CMD_QUEUE_NUM 9 | |
bd35f150 | 243 | |
751ca305 JB |
244 | /* |
245 | * This queue number is required for proper operation | |
246 | * because the ucode will stop/start the scheduler as | |
247 | * required. | |
248 | */ | |
249 | #define IWL_IPAN_MCAST_QUEUE 8 | |
250 | ||
5d08cd1d CH |
251 | #define IEEE80211_DATA_LEN 2304 |
252 | #define IEEE80211_4ADDR_LEN 30 | |
253 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
254 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
255 | ||
5d08cd1d | 256 | |
5d08cd1d CH |
257 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
258 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
259 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
260 | ||
261 | enum { | |
c587de0b | 262 | CMD_SYNC = 0, |
e419d62d EG |
263 | CMD_ASYNC = BIT(0), |
264 | CMD_WANT_SKB = BIT(1), | |
c7c1115b | 265 | CMD_ON_DEMAND = BIT(2), |
5d08cd1d CH |
266 | }; |
267 | ||
c8c24872 | 268 | #define DEF_CMD_PAYLOAD_SIZE 320 |
bd68fb6f | 269 | |
bc47279f | 270 | /** |
c2acea8e | 271 | * struct iwl_device_cmd |
bc47279f BC |
272 | * |
273 | * For allocation of the command and tx queues, this establishes the overall | |
4ce7cc2b JB |
274 | * size of the largest command we send to uCode, except for commands that |
275 | * aren't fully copied and use other TFD space. | |
bc47279f | 276 | */ |
c2acea8e | 277 | struct iwl_device_cmd { |
857485c0 | 278 | struct iwl_cmd_header hdr; /* uCode API */ |
5d08cd1d | 279 | union { |
5d08cd1d CH |
280 | u32 flags; |
281 | u8 val8; | |
282 | u16 val16; | |
283 | u32 val32; | |
83d527d9 | 284 | struct iwl_tx_cmd tx; |
c8c24872 WYG |
285 | struct iwl6000_channel_switch_cmd chswitch; |
286 | u8 payload[DEF_CMD_PAYLOAD_SIZE]; | |
ba2d3587 ED |
287 | } __packed cmd; |
288 | } __packed; | |
5d08cd1d | 289 | |
c2acea8e JB |
290 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) |
291 | ||
4ce7cc2b JB |
292 | #define IWL_MAX_CMD_TFDS 2 |
293 | ||
294 | enum iwl_hcmd_dataflag { | |
295 | IWL_HCMD_DFL_NOCOPY = BIT(0), | |
296 | }; | |
3257e5d4 | 297 | |
e419d62d EG |
298 | /** |
299 | * struct iwl_host_cmd - Host command to the uCode | |
300 | * @data: array of chunks that composes the data of the host command | |
301 | * @reply_page: pointer to the page that holds the response to the host command | |
302 | * @callback: | |
303 | * @flags: can be CMD_* note CMD_WANT_SKB is incompatible withe CMD_ASYNC | |
304 | * @len: array of the lenths of the chunks in data | |
305 | * @dataflags: | |
306 | * @id: id of the host command | |
307 | */ | |
857485c0 | 308 | struct iwl_host_cmd { |
3fa50738 | 309 | const void *data[IWL_MAX_CMD_TFDS]; |
2f301227 | 310 | unsigned long reply_page; |
5696aea6 JB |
311 | void (*callback)(struct iwl_priv *priv, |
312 | struct iwl_device_cmd *cmd, | |
2f301227 | 313 | struct iwl_rx_packet *pkt); |
c2acea8e | 314 | u32 flags; |
3fa50738 | 315 | u16 len[IWL_MAX_CMD_TFDS]; |
4ce7cc2b | 316 | u8 dataflags[IWL_MAX_CMD_TFDS]; |
c2acea8e | 317 | u8 id; |
5d08cd1d CH |
318 | }; |
319 | ||
5d08cd1d CH |
320 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 |
321 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
322 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
323 | ||
324 | /** | |
a55360e4 | 325 | * struct iwl_rx_queue - Rx queue |
df833b1d | 326 | * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) |
d5b25c90 | 327 | * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) |
5d08cd1d CH |
328 | * @read: Shared index to newest available Rx buffer |
329 | * @write: Shared index to oldest written Rx packet | |
330 | * @free_count: Number of pre-allocated buffers in rx_free | |
331 | * @rx_free: list of free SKBs for use | |
332 | * @rx_used: List of Rx buffers with no SKB | |
333 | * @need_update: flag to indicate we need to update read/write index | |
df833b1d RC |
334 | * @rb_stts: driver's pointer to receive buffer status |
335 | * @rb_stts_dma: bus address of receive buffer status | |
5d08cd1d | 336 | * |
a55360e4 | 337 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers |
5d08cd1d | 338 | */ |
a55360e4 | 339 | struct iwl_rx_queue { |
5d08cd1d | 340 | __le32 *bd; |
d5b25c90 | 341 | dma_addr_t bd_dma; |
a55360e4 TW |
342 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; |
343 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
5d08cd1d CH |
344 | u32 read; |
345 | u32 write; | |
346 | u32 free_count; | |
4752c93c | 347 | u32 write_actual; |
5d08cd1d CH |
348 | struct list_head rx_free; |
349 | struct list_head rx_used; | |
350 | int need_update; | |
8d86422a WT |
351 | struct iwl_rb_status *rb_stts; |
352 | dma_addr_t rb_stts_dma; | |
5d08cd1d CH |
353 | spinlock_t lock; |
354 | }; | |
355 | ||
356 | #define IWL_SUPPORTED_RATES_IE_LEN 8 | |
357 | ||
5d08cd1d CH |
358 | #define MAX_TID_COUNT 9 |
359 | ||
360 | #define IWL_INVALID_RATE 0xFF | |
361 | #define IWL_INVALID_VALUE -1 | |
362 | ||
bc47279f | 363 | /** |
6def9761 | 364 | * struct iwl_ht_agg -- aggregation status while waiting for block-ack |
bc47279f BC |
365 | * @txq_id: Tx queue used for Tx attempt |
366 | * @frame_count: # frames attempted by Tx command | |
367 | * @wait_for_ba: Expect block-ack before next Tx reply | |
368 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window | |
369 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window | |
370 | * @bitmap1: High order, one bit for each frame pending ACK in Tx window | |
371 | * @rate_n_flags: Rate at which Tx was attempted | |
372 | * | |
373 | * If REPLY_TX indicates that aggregation was attempted, driver must wait | |
374 | * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info | |
375 | * until block ack arrives. | |
376 | */ | |
6def9761 | 377 | struct iwl_ht_agg { |
5d08cd1d CH |
378 | u16 txq_id; |
379 | u16 frame_count; | |
380 | u16 wait_for_ba; | |
381 | u16 start_idx; | |
fe01b477 | 382 | u64 bitmap; |
5d08cd1d | 383 | u32 rate_n_flags; |
fe01b477 RR |
384 | #define IWL_AGG_OFF 0 |
385 | #define IWL_AGG_ON 1 | |
386 | #define IWL_EMPTYING_HW_QUEUE_ADDBA 2 | |
387 | #define IWL_EMPTYING_HW_QUEUE_DELBA 3 | |
388 | u8 state; | |
c8823ec1 | 389 | u8 tx_fifo; |
5d08cd1d | 390 | }; |
fe01b477 | 391 | |
5d08cd1d | 392 | |
6def9761 | 393 | struct iwl_tid_data { |
f862a236 | 394 | u16 seq_number; /* agn only */ |
fe01b477 | 395 | u16 tfds_in_queue; |
6def9761 | 396 | struct iwl_ht_agg agg; |
5d08cd1d CH |
397 | }; |
398 | ||
6def9761 | 399 | struct iwl_hw_key { |
97359d12 | 400 | u32 cipher; |
5d08cd1d | 401 | int keylen; |
0211ddda | 402 | u8 keyidx; |
5d08cd1d CH |
403 | u8 key[32]; |
404 | }; | |
405 | ||
a78fe754 | 406 | union iwl_ht_rate_supp { |
5d08cd1d CH |
407 | u16 rates; |
408 | struct { | |
409 | u8 siso_rate; | |
410 | u8 mimo_rate; | |
411 | }; | |
412 | }; | |
413 | ||
172c1d11 WYG |
414 | #define CFG_HT_RX_AMPDU_FACTOR_8K (0x0) |
415 | #define CFG_HT_RX_AMPDU_FACTOR_16K (0x1) | |
416 | #define CFG_HT_RX_AMPDU_FACTOR_32K (0x2) | |
417 | #define CFG_HT_RX_AMPDU_FACTOR_64K (0x3) | |
418 | #define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K | |
419 | #define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K | |
420 | #define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K | |
bcc693a1 WYG |
421 | |
422 | /* | |
423 | * Maximal MPDU density for TX aggregation | |
424 | * 4 - 2us density | |
425 | * 5 - 4us density | |
426 | * 6 - 8us density | |
427 | * 7 - 16us density | |
428 | */ | |
172c1d11 | 429 | #define CFG_HT_MPDU_DENSITY_2USEC (0x4) |
bcc693a1 | 430 | #define CFG_HT_MPDU_DENSITY_4USEC (0x5) |
172c1d11 WYG |
431 | #define CFG_HT_MPDU_DENSITY_8USEC (0x6) |
432 | #define CFG_HT_MPDU_DENSITY_16USEC (0x7) | |
bcc693a1 | 433 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC |
172c1d11 WYG |
434 | #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC |
435 | #define CFG_HT_MPDU_DENSITY_MIN (0x1) | |
5d08cd1d | 436 | |
fad95bf5 | 437 | struct iwl_ht_config { |
02bb1bea | 438 | bool single_chain_sufficient; |
ba37a3d0 | 439 | enum ieee80211_smps_mode smps; /* current smps mode */ |
5d08cd1d | 440 | }; |
5d08cd1d | 441 | |
5d08cd1d | 442 | /* QoS structures */ |
1ff50bda | 443 | struct iwl_qos_info { |
5d08cd1d | 444 | int qos_active; |
1ff50bda | 445 | struct iwl_qosparam_cmd def_qos_parm; |
5d08cd1d | 446 | }; |
5d08cd1d | 447 | |
fe6b23dd RC |
448 | /* |
449 | * Structure should be accessed with sta_lock held. When station addition | |
450 | * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only | |
451 | * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock | |
452 | * held. | |
453 | */ | |
6def9761 | 454 | struct iwl_station_entry { |
133636de | 455 | struct iwl_addsta_cmd sta; |
6def9761 | 456 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
dcef732c | 457 | u8 used, ctxid; |
6def9761 | 458 | struct iwl_hw_key keyinfo; |
fe6b23dd | 459 | struct iwl_link_quality_cmd *lq; |
5d08cd1d CH |
460 | }; |
461 | ||
fd1af15d | 462 | struct iwl_station_priv_common { |
238d781d | 463 | struct iwl_rxon_context *ctx; |
fd1af15d JB |
464 | u8 sta_id; |
465 | }; | |
466 | ||
8d9698b3 RC |
467 | /* |
468 | * iwl_station_priv: Driver's private station information | |
469 | * | |
470 | * When mac80211 creates a station it reserves some space (hw->sta_data_size) | |
471 | * in the structure for use by driver. This structure is places in that | |
472 | * space. | |
8d9698b3 RC |
473 | */ |
474 | struct iwl_station_priv { | |
fd1af15d | 475 | struct iwl_station_priv_common common; |
8d9698b3 | 476 | struct iwl_lq_sta lq_sta; |
6ab10ff8 JB |
477 | atomic_t pending_frames; |
478 | bool client; | |
479 | bool asleep; | |
7b090687 | 480 | u8 max_agg_bufsize; |
8d9698b3 RC |
481 | }; |
482 | ||
fd1af15d JB |
483 | /** |
484 | * struct iwl_vif_priv - driver's private per-interface information | |
485 | * | |
486 | * When mac80211 allocates a virtual interface, it can allocate | |
487 | * space for us to put data into. | |
488 | */ | |
489 | struct iwl_vif_priv { | |
246ed355 | 490 | struct iwl_rxon_context *ctx; |
fd1af15d JB |
491 | u8 ibss_bssid_sta_id; |
492 | }; | |
493 | ||
5d08cd1d CH |
494 | /* one for each uCode image (inst/data, boot/init/runtime) */ |
495 | struct fw_desc { | |
496 | void *v_addr; /* access by driver */ | |
497 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
498 | u32 len; /* bytes */ | |
499 | }; | |
500 | ||
dbf28e21 JB |
501 | struct fw_img { |
502 | struct fw_desc code, data; | |
503 | }; | |
504 | ||
dd7a2509 | 505 | /* v1/v2 uCode file layout */ |
cc0f555d JS |
506 | struct iwl_ucode_header { |
507 | __le32 ver; /* major/minor/API/serial */ | |
508 | union { | |
509 | struct { | |
510 | __le32 inst_size; /* bytes of runtime code */ | |
511 | __le32 data_size; /* bytes of runtime data */ | |
512 | __le32 init_size; /* bytes of init code */ | |
513 | __le32 init_data_size; /* bytes of init data */ | |
514 | __le32 boot_size; /* bytes of bootstrap code */ | |
515 | u8 data[0]; /* in same order as sizes */ | |
516 | } v1; | |
517 | struct { | |
518 | __le32 build; /* build number */ | |
519 | __le32 inst_size; /* bytes of runtime code */ | |
520 | __le32 data_size; /* bytes of runtime data */ | |
521 | __le32 init_size; /* bytes of init code */ | |
522 | __le32 init_data_size; /* bytes of init data */ | |
523 | __le32 boot_size; /* bytes of bootstrap code */ | |
524 | u8 data[0]; /* in same order as sizes */ | |
525 | } v2; | |
526 | } u; | |
5d08cd1d CH |
527 | }; |
528 | ||
dd7a2509 JB |
529 | /* |
530 | * new TLV uCode file layout | |
531 | * | |
532 | * The new TLV file format contains TLVs, that each specify | |
533 | * some piece of data. To facilitate "groups", for example | |
534 | * different instruction image with different capabilities, | |
535 | * bundled with the same init image, an alternative mechanism | |
536 | * is provided: | |
537 | * When the alternative field is 0, that means that the item | |
538 | * is always valid. When it is non-zero, then it is only | |
539 | * valid in conjunction with items of the same alternative, | |
540 | * in which case the driver (user) selects one alternative | |
541 | * to use. | |
542 | */ | |
543 | ||
544 | enum iwl_ucode_tlv_type { | |
545 | IWL_UCODE_TLV_INVALID = 0, /* unused */ | |
546 | IWL_UCODE_TLV_INST = 1, | |
547 | IWL_UCODE_TLV_DATA = 2, | |
548 | IWL_UCODE_TLV_INIT = 3, | |
549 | IWL_UCODE_TLV_INIT_DATA = 4, | |
550 | IWL_UCODE_TLV_BOOT = 5, | |
551 | IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */ | |
ece9c4ee | 552 | IWL_UCODE_TLV_PAN = 7, |
b2e640d4 JB |
553 | IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8, |
554 | IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, | |
555 | IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10, | |
556 | IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11, | |
557 | IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12, | |
558 | IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13, | |
c8312fac | 559 | IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14, |
6a822d06 | 560 | IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, |
3997ff39 JB |
561 | /* 16 and 17 reserved for future use */ |
562 | IWL_UCODE_TLV_FLAGS = 18, | |
563 | }; | |
564 | ||
565 | /** | |
566 | * enum iwl_ucode_tlv_flag - ucode API flags | |
567 | * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously | |
568 | * was a separate TLV but moved here to save space. | |
d2690c0d JB |
569 | * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, |
570 | * treats good CRC threshold as a boolean | |
3997ff39 JB |
571 | * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). |
572 | */ | |
573 | enum iwl_ucode_tlv_flag { | |
574 | IWL_UCODE_TLV_FLAGS_PAN = BIT(0), | |
d2690c0d | 575 | IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1), |
3997ff39 | 576 | IWL_UCODE_TLV_FLAGS_MFP = BIT(2), |
dd7a2509 JB |
577 | }; |
578 | ||
579 | struct iwl_ucode_tlv { | |
580 | __le16 type; /* see above */ | |
581 | __le16 alternative; /* see comment */ | |
582 | __le32 length; /* not including type/length fields */ | |
583 | u8 data[0]; | |
ba2d3587 | 584 | } __packed; |
dd7a2509 JB |
585 | |
586 | #define IWL_TLV_UCODE_MAGIC 0x0a4c5749 | |
587 | ||
588 | struct iwl_tlv_ucode_header { | |
589 | /* | |
590 | * The TLV style ucode header is distinguished from | |
591 | * the v1/v2 style header by first four bytes being | |
592 | * zero, as such is an invalid combination of | |
593 | * major/minor/API/serial versions. | |
594 | */ | |
595 | __le32 zero; | |
596 | __le32 magic; | |
597 | u8 human_readable[64]; | |
598 | __le32 ver; /* major/minor/API/serial */ | |
599 | __le32 build; | |
600 | __le64 alternatives; /* bitmask of valid alternatives */ | |
601 | /* | |
602 | * The data contained herein has a TLV layout, | |
603 | * see above for the TLV header and types. | |
604 | * Note that each TLV is padded to a length | |
605 | * that is a multiple of 4 for alignment. | |
606 | */ | |
607 | u8 data[0]; | |
608 | }; | |
609 | ||
f0832f13 EG |
610 | struct iwl_sensitivity_ranges { |
611 | u16 min_nrg_cck; | |
612 | u16 max_nrg_cck; | |
613 | ||
614 | u16 nrg_th_cck; | |
615 | u16 nrg_th_ofdm; | |
616 | ||
617 | u16 auto_corr_min_ofdm; | |
618 | u16 auto_corr_min_ofdm_mrc; | |
619 | u16 auto_corr_min_ofdm_x1; | |
620 | u16 auto_corr_min_ofdm_mrc_x1; | |
621 | ||
622 | u16 auto_corr_max_ofdm; | |
623 | u16 auto_corr_max_ofdm_mrc; | |
624 | u16 auto_corr_max_ofdm_x1; | |
625 | u16 auto_corr_max_ofdm_mrc_x1; | |
626 | ||
627 | u16 auto_corr_max_cck; | |
628 | u16 auto_corr_max_cck_mrc; | |
629 | u16 auto_corr_min_cck; | |
630 | u16 auto_corr_min_cck_mrc; | |
55036d66 WYG |
631 | |
632 | u16 barker_corr_th_min; | |
633 | u16 barker_corr_th_min_mrc; | |
634 | u16 nrg_th_cca; | |
f0832f13 EG |
635 | }; |
636 | ||
099b40b7 | 637 | |
b5047f78 TW |
638 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
639 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
640 | ||
641 | ||
bc47279f | 642 | /** |
5425e490 | 643 | * struct iwl_hw_params |
bc47279f | 644 | * @max_txq_num: Max # Tx queues supported |
4ddbb7d0 | 645 | * @scd_bc_tbls_size: size of scheduler byte count tables |
a8e74e27 | 646 | * @tfd_size: TFD size |
099b40b7 RR |
647 | * @tx/rx_chains_num: Number of TX/RX chains |
648 | * @valid_tx/rx_ant: usable antennas | |
bc47279f | 649 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) |
bc47279f | 650 | * @max_rxq_log: Log-base-2 of max_rxq_size |
2f301227 | 651 | * @rx_page_order: Rx buffer page order |
141c43a3 | 652 | * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR |
bc47279f | 653 | * @max_stations: |
7aafef1c | 654 | * @ht40_channel: is 40MHz width possible in band 2.4 |
099b40b7 RR |
655 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) |
656 | * @sw_crypto: 0 for hw, 1 for sw | |
657 | * @max_xxx_size: for ucode uses | |
658 | * @ct_kill_threshold: temperature threshold | |
a0ee74cf | 659 | * @beacon_time_tsf_bits: number of valid tsf bits for beacon time |
a96a27f9 | 660 | * @calib_init_cfg: setup initial calibrations for the hw |
6d6a1afd | 661 | * @calib_rt_cfg: setup runtime calibrations for the hw |
f0832f13 | 662 | * @struct iwl_sensitivity_ranges: range of sensitivity values |
bc47279f | 663 | */ |
5425e490 | 664 | struct iwl_hw_params { |
f3f911d1 | 665 | u8 max_txq_num; |
4ddbb7d0 | 666 | u16 scd_bc_tbls_size; |
a8e74e27 | 667 | u32 tfd_size; |
ec35cf2a TW |
668 | u8 tx_chains_num; |
669 | u8 rx_chains_num; | |
670 | u8 valid_tx_ant; | |
671 | u8 valid_rx_ant; | |
5d08cd1d | 672 | u16 max_rxq_size; |
ec35cf2a | 673 | u16 max_rxq_log; |
2f301227 | 674 | u32 rx_page_order; |
5d08cd1d | 675 | u8 max_stations; |
7aafef1c | 676 | u8 ht40_channel; |
2c2f3b33 | 677 | u8 max_beacon_itrvl; /* in 1024 ms */ |
099b40b7 RR |
678 | u32 max_inst_size; |
679 | u32 max_data_size; | |
099b40b7 | 680 | u32 ct_kill_threshold; /* value in hw-dependent units */ |
672639de WYG |
681 | u32 ct_kill_exit_threshold; /* value in hw-dependent units */ |
682 | /* for 1000, 6000 series and up */ | |
a0ee74cf | 683 | u16 beacon_time_tsf_bits; |
be5d56ed | 684 | u32 calib_init_cfg; |
6d6a1afd | 685 | u32 calib_rt_cfg; |
f0832f13 | 686 | const struct iwl_sensitivity_ranges *sens; |
5d08cd1d CH |
687 | }; |
688 | ||
5d08cd1d | 689 | |
5d08cd1d CH |
690 | /****************************************************************************** |
691 | * | |
a33c2f47 EG |
692 | * Functions implemented in core module which are forward declared here |
693 | * for use by iwl-[4-5].c | |
5d08cd1d | 694 | * |
a33c2f47 EG |
695 | * NOTE: The implementation of these functions are not hardware specific |
696 | * which is why they are in the core module files. | |
5d08cd1d CH |
697 | * |
698 | * Naming convention -- | |
a33c2f47 | 699 | * iwl_ <-- Is part of iwlwifi |
5d08cd1d | 700 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) |
5d08cd1d CH |
701 | * |
702 | ****************************************************************************/ | |
5b9f8cd3 | 703 | extern void iwl_update_chain_flags(struct iwl_priv *priv); |
a33c2f47 | 704 | extern const u8 iwl_bcast_addr[ETH_ALEN]; |
443cfd45 | 705 | extern int iwl_queue_space(const struct iwl_queue *q); |
fd4abac5 TW |
706 | static inline int iwl_queue_used(const struct iwl_queue *q, int i) |
707 | { | |
c8106d76 | 708 | return q->write_ptr >= q->read_ptr ? |
fd4abac5 TW |
709 | (i >= q->read_ptr && i < q->write_ptr) : |
710 | !(i < q->read_ptr && i >= q->write_ptr); | |
711 | } | |
712 | ||
713 | ||
4ce7cc2b | 714 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index) |
fd4abac5 | 715 | { |
fd4abac5 TW |
716 | return index & (q->n_window - 1); |
717 | } | |
718 | ||
719 | ||
4ddbb7d0 TW |
720 | struct iwl_dma_ptr { |
721 | dma_addr_t dma; | |
722 | void *addr; | |
b481de9c ZY |
723 | size_t size; |
724 | }; | |
725 | ||
b481de9c ZY |
726 | #define IWL_OPERATION_MODE_AUTO 0 |
727 | #define IWL_OPERATION_MODE_HT_ONLY 1 | |
728 | #define IWL_OPERATION_MODE_MIXED 2 | |
729 | #define IWL_OPERATION_MODE_20MHZ 3 | |
730 | ||
3195cdb7 TW |
731 | #define IWL_TX_CRC_SIZE 4 |
732 | #define IWL_TX_DELIMITER_SIZE 4 | |
b481de9c | 733 | |
b481de9c | 734 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 |
b481de9c | 735 | |
b481de9c | 736 | /* Sensitivity and chain noise calibration */ |
b481de9c | 737 | #define INITIALIZATION_VALUE 0xFFFF |
d8c07e7a | 738 | #define IWL_CAL_NUM_BEACONS 16 |
b481de9c ZY |
739 | #define MAXIMUM_ALLOWED_PATHLOSS 15 |
740 | ||
b481de9c ZY |
741 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 |
742 | ||
743 | #define MAX_FA_OFDM 50 | |
744 | #define MIN_FA_OFDM 5 | |
745 | #define MAX_FA_CCK 50 | |
746 | #define MIN_FA_CCK 5 | |
747 | ||
b481de9c ZY |
748 | #define AUTO_CORR_STEP_OFDM 1 |
749 | ||
b481de9c ZY |
750 | #define AUTO_CORR_STEP_CCK 3 |
751 | #define AUTO_CORR_MAX_TH_CCK 160 | |
752 | ||
b481de9c ZY |
753 | #define NRG_DIFF 2 |
754 | #define NRG_STEP_CCK 2 | |
755 | #define NRG_MARGIN 8 | |
756 | #define MAX_NUMBER_CCK_NO_FA 100 | |
757 | ||
758 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
759 | ||
760 | #define CHAIN_A 0 | |
761 | #define CHAIN_B 1 | |
762 | #define CHAIN_C 2 | |
763 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
764 | #define ALL_BAND_FILTER 0xFF00 | |
765 | #define IN_BAND_FILTER 0xFF | |
766 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
767 | ||
3195cdb7 TW |
768 | #define NRG_NUM_PREV_STAT_L 20 |
769 | #define NUM_RX_CHAINS 3 | |
770 | ||
3240cab3 | 771 | enum iwlagn_false_alarm_state { |
b481de9c ZY |
772 | IWL_FA_TOO_MANY = 0, |
773 | IWL_FA_TOO_FEW = 1, | |
774 | IWL_FA_GOOD_RANGE = 2, | |
775 | }; | |
776 | ||
3240cab3 | 777 | enum iwlagn_chain_noise_state { |
b481de9c | 778 | IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
04816448 GE |
779 | IWL_CHAIN_NOISE_ACCUMULATE, |
780 | IWL_CHAIN_NOISE_CALIBRATED, | |
781 | IWL_CHAIN_NOISE_DONE, | |
b481de9c ZY |
782 | }; |
783 | ||
f69f42a6 TW |
784 | |
785 | /* | |
786 | * enum iwl_calib | |
787 | * defines the order in which results of initial calibrations | |
788 | * should be sent to the runtime uCode | |
789 | */ | |
790 | enum iwl_calib { | |
791 | IWL_CALIB_XTAL, | |
819500c5 | 792 | IWL_CALIB_DC, |
f69f42a6 TW |
793 | IWL_CALIB_LO, |
794 | IWL_CALIB_TX_IQ, | |
795 | IWL_CALIB_TX_IQ_PERD, | |
201706ac | 796 | IWL_CALIB_BASE_BAND, |
bf53f939 | 797 | IWL_CALIB_TEMP_OFFSET, |
f69f42a6 TW |
798 | IWL_CALIB_MAX |
799 | }; | |
800 | ||
6e21f2c1 TW |
801 | /* Opaque calibration results */ |
802 | struct iwl_calib_result { | |
803 | void *buf; | |
804 | size_t buf_len; | |
7c616cba TW |
805 | }; |
806 | ||
b481de9c | 807 | /* Sensitivity calib data */ |
f0832f13 | 808 | struct iwl_sensitivity_data { |
b481de9c ZY |
809 | u32 auto_corr_ofdm; |
810 | u32 auto_corr_ofdm_mrc; | |
811 | u32 auto_corr_ofdm_x1; | |
812 | u32 auto_corr_ofdm_mrc_x1; | |
813 | u32 auto_corr_cck; | |
814 | u32 auto_corr_cck_mrc; | |
815 | ||
816 | u32 last_bad_plcp_cnt_ofdm; | |
817 | u32 last_fa_cnt_ofdm; | |
818 | u32 last_bad_plcp_cnt_cck; | |
819 | u32 last_fa_cnt_cck; | |
820 | ||
821 | u32 nrg_curr_state; | |
822 | u32 nrg_prev_state; | |
823 | u32 nrg_value[10]; | |
824 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; | |
825 | u32 nrg_silence_ref; | |
826 | u32 nrg_energy_idx; | |
827 | u32 nrg_silence_idx; | |
828 | u32 nrg_th_cck; | |
829 | s32 nrg_auto_corr_silence_diff; | |
830 | u32 num_in_cck_no_fa; | |
831 | u32 nrg_th_ofdm; | |
55036d66 WYG |
832 | |
833 | u16 barker_corr_th_min; | |
834 | u16 barker_corr_th_min_mrc; | |
835 | u16 nrg_th_cca; | |
b481de9c ZY |
836 | }; |
837 | ||
838 | /* Chain noise (differential Rx gain) calib data */ | |
f0832f13 | 839 | struct iwl_chain_noise_data { |
04816448 | 840 | u32 active_chains; |
b481de9c ZY |
841 | u32 chain_noise_a; |
842 | u32 chain_noise_b; | |
843 | u32 chain_noise_c; | |
844 | u32 chain_signal_a; | |
845 | u32 chain_signal_b; | |
846 | u32 chain_signal_c; | |
04816448 | 847 | u16 beacon_count; |
b481de9c ZY |
848 | u8 disconn_array[NUM_RX_CHAINS]; |
849 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
850 | u8 radio_write; | |
04816448 | 851 | u8 state; |
b481de9c ZY |
852 | }; |
853 | ||
abceddb4 BC |
854 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
855 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
b481de9c | 856 | |
20594eb0 WYG |
857 | #define IWL_TRAFFIC_ENTRIES (256) |
858 | #define IWL_TRAFFIC_ENTRY_SIZE (64) | |
5d08cd1d | 859 | |
5d08cd1d CH |
860 | enum { |
861 | MEASUREMENT_READY = (1 << 0), | |
862 | MEASUREMENT_ACTIVE = (1 << 1), | |
863 | }; | |
864 | ||
0848e297 WYG |
865 | enum iwl_nvm_type { |
866 | NVM_DEVICE_TYPE_EEPROM = 0, | |
867 | NVM_DEVICE_TYPE_OTP, | |
868 | }; | |
869 | ||
415e4993 WYG |
870 | /* |
871 | * Two types of OTP memory access modes | |
872 | * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode, | |
873 | * based on physical memory addressing | |
874 | * IWL_OTP_ACCESS_RELATIVE - relative address mode, | |
875 | * based on logical memory addressing | |
876 | */ | |
877 | enum iwl_access_mode { | |
878 | IWL_OTP_ACCESS_ABSOLUTE, | |
879 | IWL_OTP_ACCESS_RELATIVE, | |
880 | }; | |
65b7998a WYG |
881 | |
882 | /** | |
883 | * enum iwl_pa_type - Power Amplifier type | |
884 | * @IWL_PA_SYSTEM: based on uCode configuration | |
65b7998a WYG |
885 | * @IWL_PA_INTERNAL: use Internal only |
886 | */ | |
887 | enum iwl_pa_type { | |
888 | IWL_PA_SYSTEM = 0, | |
740e7f51 | 889 | IWL_PA_INTERNAL = 1, |
65b7998a WYG |
890 | }; |
891 | ||
a83b9141 WYG |
892 | /* interrupt statistics */ |
893 | struct isr_statistics { | |
894 | u32 hw; | |
895 | u32 sw; | |
6e6ebf4b | 896 | u32 err_code; |
a83b9141 WYG |
897 | u32 sch; |
898 | u32 alive; | |
899 | u32 rfkill; | |
900 | u32 ctkill; | |
901 | u32 wakeup; | |
902 | u32 rx; | |
903 | u32 rx_handlers[REPLY_MAX]; | |
904 | u32 tx; | |
905 | u32 unhandled; | |
906 | }; | |
5d08cd1d | 907 | |
91835ba4 WYG |
908 | /* reply_tx_statistics (for _agn devices) */ |
909 | struct reply_tx_error_statistics { | |
910 | u32 pp_delay; | |
911 | u32 pp_few_bytes; | |
912 | u32 pp_bt_prio; | |
913 | u32 pp_quiet_period; | |
914 | u32 pp_calc_ttak; | |
915 | u32 int_crossed_retry; | |
916 | u32 short_limit; | |
917 | u32 long_limit; | |
918 | u32 fifo_underrun; | |
919 | u32 drain_flow; | |
920 | u32 rfkill_flush; | |
921 | u32 life_expire; | |
922 | u32 dest_ps; | |
923 | u32 host_abort; | |
924 | u32 bt_retry; | |
925 | u32 sta_invalid; | |
926 | u32 frag_drop; | |
927 | u32 tid_disable; | |
928 | u32 fifo_flush; | |
929 | u32 insuff_cf_poll; | |
930 | u32 fail_hw_drop; | |
931 | u32 sta_color_mismatch; | |
932 | u32 unknown; | |
933 | }; | |
934 | ||
814665fe WYG |
935 | /* reply_agg_tx_statistics (for _agn devices) */ |
936 | struct reply_agg_tx_error_statistics { | |
937 | u32 underrun; | |
938 | u32 bt_prio; | |
939 | u32 few_bytes; | |
940 | u32 abort; | |
941 | u32 last_sent_ttl; | |
942 | u32 last_sent_try; | |
943 | u32 last_sent_bt_kill; | |
944 | u32 scd_query; | |
945 | u32 bad_crc32; | |
946 | u32 response; | |
947 | u32 dump_tx; | |
948 | u32 delay_tx; | |
949 | u32 unknown; | |
950 | }; | |
951 | ||
22fdf3c9 WYG |
952 | /* management statistics */ |
953 | enum iwl_mgmt_stats { | |
954 | MANAGEMENT_ASSOC_REQ = 0, | |
955 | MANAGEMENT_ASSOC_RESP, | |
956 | MANAGEMENT_REASSOC_REQ, | |
957 | MANAGEMENT_REASSOC_RESP, | |
958 | MANAGEMENT_PROBE_REQ, | |
959 | MANAGEMENT_PROBE_RESP, | |
960 | MANAGEMENT_BEACON, | |
961 | MANAGEMENT_ATIM, | |
962 | MANAGEMENT_DISASSOC, | |
963 | MANAGEMENT_AUTH, | |
964 | MANAGEMENT_DEAUTH, | |
965 | MANAGEMENT_ACTION, | |
966 | MANAGEMENT_MAX, | |
967 | }; | |
968 | /* control statistics */ | |
969 | enum iwl_ctrl_stats { | |
970 | CONTROL_BACK_REQ = 0, | |
971 | CONTROL_BACK, | |
972 | CONTROL_PSPOLL, | |
973 | CONTROL_RTS, | |
974 | CONTROL_CTS, | |
975 | CONTROL_ACK, | |
976 | CONTROL_CFEND, | |
977 | CONTROL_CFENDACK, | |
978 | CONTROL_MAX, | |
979 | }; | |
980 | ||
981 | struct traffic_stats { | |
5ed540ae | 982 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
22fdf3c9 WYG |
983 | u32 mgmt[MANAGEMENT_MAX]; |
984 | u32 ctrl[CONTROL_MAX]; | |
985 | u32 data_cnt; | |
986 | u64 data_bytes; | |
22fdf3c9 | 987 | #endif |
5ed540ae | 988 | }; |
22fdf3c9 | 989 | |
a9e1cb6a WYG |
990 | /* |
991 | * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds | |
992 | * to perform continuous uCode event logging operation if enabled | |
993 | */ | |
994 | #define UCODE_TRACE_PERIOD (100) | |
995 | ||
996 | /* | |
997 | * iwl_event_log: current uCode event log position | |
998 | * | |
999 | * @ucode_trace: enable/disable ucode continuous trace timer | |
1000 | * @num_wraps: how many times the event buffer wraps | |
1001 | * @next_entry: the entry just before the next one that uCode would fill | |
1002 | * @non_wraps_count: counter for no wrap detected when dump ucode events | |
1003 | * @wraps_once_count: counter for wrap once detected when dump ucode events | |
1004 | * @wraps_more_count: counter for wrap more than once detected | |
1005 | * when dump ucode events | |
1006 | */ | |
1007 | struct iwl_event_log { | |
1008 | bool ucode_trace; | |
1009 | u32 num_wraps; | |
1010 | u32 next_entry; | |
1011 | int non_wraps_count; | |
1012 | int wraps_once_count; | |
1013 | int wraps_more_count; | |
1014 | }; | |
1015 | ||
2be76703 WYG |
1016 | /* |
1017 | * host interrupt timeout value | |
1018 | * used with setting interrupt coalescing timer | |
1019 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | |
1020 | * | |
1021 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | |
1022 | * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs | |
1023 | */ | |
1024 | #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) | |
1025 | #define IWL_HOST_INT_TIMEOUT_DEF (0x40) | |
1026 | #define IWL_HOST_INT_TIMEOUT_MIN (0x0) | |
1027 | #define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) | |
1028 | #define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) | |
1029 | #define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) | |
1030 | ||
3e4fb5fa TAN |
1031 | /* |
1032 | * This is the threshold value of plcp error rate per 100mSecs. It is | |
1033 | * used to set and check for the validity of plcp_delta. | |
1034 | */ | |
680788ac | 1035 | #define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1) |
3e4fb5fa TAN |
1036 | #define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50) |
1037 | #define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100) | |
6c3872e1 | 1038 | #define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200) |
3e4fb5fa | 1039 | #define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255) |
680788ac | 1040 | #define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0) |
3e4fb5fa | 1041 | |
8a472da4 WYG |
1042 | #define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3) |
1043 | #define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5) | |
1044 | ||
22de94de SG |
1045 | /* TX queue watchdog timeouts in mSecs */ |
1046 | #define IWL_DEF_WD_TIMEOUT (2000) | |
1047 | #define IWL_LONG_WD_TIMEOUT (10000) | |
1048 | #define IWL_MAX_WD_TIMEOUT (120000) | |
b74e31a9 | 1049 | |
bee008b7 WYG |
1050 | /* BT Antenna Coupling Threshold (dB) */ |
1051 | #define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35) | |
1052 | ||
491bc292 WYG |
1053 | /* Firmware reload counter and Timestamp */ |
1054 | #define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */ | |
1055 | #define IWL_MAX_CONTINUE_RELOAD_CNT 4 | |
1056 | ||
1057 | ||
a93e7973 WYG |
1058 | enum iwl_reset { |
1059 | IWL_RF_RESET = 0, | |
1060 | IWL_FW_RESET, | |
8a472da4 WYG |
1061 | IWL_MAX_FORCE_RESET, |
1062 | }; | |
1063 | ||
1064 | struct iwl_force_reset { | |
1065 | int reset_request_count; | |
1066 | int reset_success_count; | |
1067 | int reset_reject_count; | |
1068 | unsigned long reset_duration; | |
1069 | unsigned long last_force_reset_jiffies; | |
a93e7973 WYG |
1070 | }; |
1071 | ||
a0ee74cf | 1072 | /* extend beacon time format bit shifting */ |
a0ee74cf WYG |
1073 | /* |
1074 | * for _agn devices | |
1075 | * bits 31:22 - extended | |
1076 | * bits 21:0 - interval | |
1077 | */ | |
1078 | #define IWLAGN_EXT_BEACON_TIME_POS 22 | |
1079 | ||
7194207c JB |
1080 | /** |
1081 | * struct iwl_notification_wait - notification wait entry | |
1082 | * @list: list head for global list | |
1083 | * @fn: function called with the notification | |
1084 | * @cmd: command ID | |
1085 | * | |
1086 | * This structure is not used directly, to wait for a | |
1087 | * notification declare it on the stack, and call | |
1088 | * iwlagn_init_notification_wait() with appropriate | |
1089 | * parameters. Then do whatever will cause the ucode | |
1090 | * to notify the driver, and to wait for that then | |
1091 | * call iwlagn_wait_notification(). | |
1092 | * | |
1093 | * Each notification is one-shot. If at some point we | |
1094 | * need to support multi-shot notifications (which | |
1095 | * can't be allocated on the stack) we need to modify | |
1096 | * the code for them. | |
1097 | */ | |
1098 | struct iwl_notification_wait { | |
1099 | struct list_head list; | |
1100 | ||
09f18afe JB |
1101 | void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt, |
1102 | void *data); | |
1103 | void *fn_data; | |
7194207c JB |
1104 | |
1105 | u8 cmd; | |
e74fe233 | 1106 | bool triggered, aborted; |
7194207c JB |
1107 | }; |
1108 | ||
246ed355 JB |
1109 | enum iwl_rxon_context_id { |
1110 | IWL_RXON_CTX_BSS, | |
ece9c4ee | 1111 | IWL_RXON_CTX_PAN, |
246ed355 JB |
1112 | |
1113 | NUM_IWL_RXON_CTX | |
1114 | }; | |
1115 | ||
1116 | struct iwl_rxon_context { | |
8bd413e6 | 1117 | struct ieee80211_vif *vif; |
e72f368b JB |
1118 | |
1119 | const u8 *ac_to_fifo; | |
1120 | const u8 *ac_to_queue; | |
1121 | u8 mcast_queue; | |
1122 | ||
763cc3bf JB |
1123 | /* |
1124 | * We could use the vif to indicate active, but we | |
1125 | * also need it to be active during disabling when | |
1126 | * we already removed the vif for type setting. | |
1127 | */ | |
1128 | bool always_active, is_active; | |
1129 | ||
2295c66b JB |
1130 | bool ht_need_multiple_chains; |
1131 | ||
246ed355 | 1132 | enum iwl_rxon_context_id ctxid; |
d0fe478c JB |
1133 | |
1134 | u32 interface_modes, exclusive_interface_modes; | |
1135 | u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype; | |
1136 | ||
246ed355 JB |
1137 | /* |
1138 | * We declare this const so it can only be | |
1139 | * changed via explicit cast within the | |
1140 | * routines that actually update the physical | |
1141 | * hardware. | |
1142 | */ | |
1143 | const struct iwl_rxon_cmd active; | |
1144 | struct iwl_rxon_cmd staging; | |
1145 | ||
1146 | struct iwl_rxon_time_cmd timing; | |
a194e324 | 1147 | |
8dfdb9d5 JB |
1148 | struct iwl_qos_info qos_data; |
1149 | ||
2995bafa | 1150 | u8 bcast_sta_id, ap_sta_id; |
8f2d3d2a JB |
1151 | |
1152 | u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd; | |
8dfdb9d5 | 1153 | u8 qos_cmd; |
c10afb6e JB |
1154 | u8 wep_key_cmd; |
1155 | ||
1156 | struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; | |
1157 | u8 key_mapping_keys; | |
770e13bd JB |
1158 | |
1159 | __le32 station_flags; | |
7e6a5886 JB |
1160 | |
1161 | struct { | |
1162 | bool non_gf_sta_present; | |
1163 | u8 protection; | |
1164 | bool enabled, is_40mhz; | |
1165 | u8 extension_chan_offset; | |
1166 | } ht; | |
68b99311 GT |
1167 | |
1168 | bool last_tx_rejected; | |
246ed355 JB |
1169 | }; |
1170 | ||
266af4c7 JB |
1171 | enum iwl_scan_type { |
1172 | IWL_SCAN_NORMAL, | |
1173 | IWL_SCAN_RADIO_RESET, | |
1174 | IWL_SCAN_OFFCH_TX, | |
1175 | }; | |
1176 | ||
872907bb JB |
1177 | enum iwlagn_ucode_type { |
1178 | IWL_UCODE_NONE, | |
1179 | IWL_UCODE_REGULAR, | |
1180 | IWL_UCODE_INIT, | |
1181 | IWL_UCODE_WOWLAN, | |
1182 | }; | |
1183 | ||
7a4e5281 WYG |
1184 | #ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL |
1185 | struct iwl_testmode_trace { | |
49b72100 WYG |
1186 | u32 buff_size; |
1187 | u32 total_size; | |
eb64dca0 | 1188 | u32 num_chunks; |
7a4e5281 WYG |
1189 | u8 *cpu_addr; |
1190 | u8 *trace_addr; | |
1191 | dma_addr_t dma_addr; | |
1192 | bool trace_enabled; | |
1193 | }; | |
1194 | #endif | |
a48709c5 EG |
1195 | |
1196 | struct iwl_bus; | |
1197 | ||
1198 | /** | |
1199 | * struct iwl_bus_ops - bus specific operations | |
d57fa99d WYG |
1200 | |
1201 | * @get_pm_support: must returns true if the bus can go to sleep | |
1202 | * @apm_config: will be called during the config of the APM configuration | |
a48709c5 | 1203 | * @set_drv_data: set the priv pointer to the bus layer |
3599d39a | 1204 | * @get_dev: returns the device struct |
08321c06 | 1205 | * @get_irq: returns the irq number |
19707bac | 1206 | * @get_hw_id: prints the hw_id in the provided buffer |
084dd791 EG |
1207 | * @write8: write a byte to register at offset ofs |
1208 | * @write32: write a dword to register at offset ofs | |
1209 | * @wread32: read a dword at register at offset ofs | |
a48709c5 EG |
1210 | */ |
1211 | struct iwl_bus_ops { | |
d57fa99d WYG |
1212 | bool (*get_pm_support)(struct iwl_bus *bus); |
1213 | void (*apm_config)(struct iwl_bus *bus); | |
a48709c5 | 1214 | void (*set_drv_data)(struct iwl_bus *bus, void *priv); |
3599d39a | 1215 | struct device *(*get_dev)(const struct iwl_bus *bus); |
08321c06 | 1216 | unsigned int (*get_irq)(const struct iwl_bus *bus); |
19707bac | 1217 | void (*get_hw_id)(struct iwl_bus *bus, char buf[], int buf_len); |
084dd791 EG |
1218 | void (*write8)(struct iwl_bus *bus, u32 ofs, u8 val); |
1219 | void (*write32)(struct iwl_bus *bus, u32 ofs, u32 val); | |
1220 | u32 (*read32)(struct iwl_bus *bus, u32 ofs); | |
a48709c5 EG |
1221 | }; |
1222 | ||
1223 | struct iwl_bus { | |
1224 | /* pointer to bus specific struct */ | |
1225 | void *bus_specific; | |
1226 | ||
1227 | /* Common data to all buses */ | |
1228 | struct iwl_priv *priv; /* driver's context */ | |
3599d39a | 1229 | struct device *dev; |
a48709c5 | 1230 | struct iwl_bus_ops *ops; |
705cd451 | 1231 | unsigned int irq; |
a48709c5 EG |
1232 | }; |
1233 | ||
e98a1939 WYG |
1234 | /* uCode ownership */ |
1235 | #define IWL_OWNERSHIP_DRIVER 0 | |
1236 | #define IWL_OWNERSHIP_TM 1 | |
1237 | ||
c79dd5b5 | 1238 | struct iwl_priv { |
5d08cd1d CH |
1239 | |
1240 | /* ieee device used by generic ieee processing code */ | |
1241 | struct ieee80211_hw *hw; | |
1242 | struct ieee80211_channel *ieee_channels; | |
1243 | struct ieee80211_rate *ieee_rates; | |
82b9a121 | 1244 | struct iwl_cfg *cfg; |
5d08cd1d | 1245 | |
8318d78a | 1246 | enum ieee80211_band band; |
5d08cd1d | 1247 | |
4613e72d CK |
1248 | void (*pre_rx_handler)(struct iwl_priv *priv, |
1249 | struct iwl_rx_mem_buffer *rxb); | |
c79dd5b5 | 1250 | void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv, |
a55360e4 | 1251 | struct iwl_rx_mem_buffer *rxb); |
5d08cd1d | 1252 | |
8318d78a | 1253 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; |
5d08cd1d | 1254 | |
5d08cd1d | 1255 | /* spectrum measurement report caching */ |
2aa6ab86 | 1256 | struct iwl_spectrum_notification measure_report; |
5d08cd1d | 1257 | u8 measurement_status; |
81963d68 | 1258 | |
5d08cd1d CH |
1259 | /* ucode beacon time */ |
1260 | u32 ucode_beacon_time; | |
a13d276f | 1261 | int missed_beacon_threshold; |
5d08cd1d | 1262 | |
a85d7cca JB |
1263 | /* track IBSS manager (last beacon) status */ |
1264 | u32 ibss_manager; | |
1265 | ||
410f2bb3 SG |
1266 | /* jiffies when last recovery from statistics was performed */ |
1267 | unsigned long rx_statistics_jiffies; | |
3e4fb5fa | 1268 | |
a93e7973 | 1269 | /* force reset */ |
8a472da4 | 1270 | struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET]; |
a93e7973 | 1271 | |
491bc292 WYG |
1272 | /* firmware reload counter and timestamp */ |
1273 | unsigned long reload_jiffies; | |
1274 | int reload_count; | |
1275 | ||
5a2a780c | 1276 | /* we allocate array of iwl_channel_info for NIC's valid channels. |
5d08cd1d | 1277 | * Access via channel # using indirect index array */ |
bf85ea4f | 1278 | struct iwl_channel_info *channel_info; /* channel info array */ |
5d08cd1d CH |
1279 | u8 channel_count; /* # of channels */ |
1280 | ||
5d08cd1d CH |
1281 | /* thermal calibration */ |
1282 | s32 temperature; /* degrees Kelvin */ | |
1283 | s32 last_temperature; | |
1284 | ||
7c616cba | 1285 | /* init calibration results */ |
6e21f2c1 | 1286 | struct iwl_calib_result calib_results[IWL_CALIB_MAX]; |
7c616cba | 1287 | |
5d08cd1d | 1288 | /* Scan related variables */ |
5d08cd1d | 1289 | unsigned long scan_start; |
5d08cd1d | 1290 | unsigned long scan_start_tsf; |
811ecc99 | 1291 | void *scan_cmd; |
00700ee0 | 1292 | enum ieee80211_band scan_band; |
1ecf9fc1 | 1293 | struct cfg80211_scan_request *scan_request; |
f84b29ec | 1294 | struct ieee80211_vif *scan_vif; |
266af4c7 | 1295 | enum iwl_scan_type scan_type; |
76eff18b TW |
1296 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; |
1297 | u8 mgmt_tx_ant; | |
5d08cd1d CH |
1298 | |
1299 | /* spinlock */ | |
1300 | spinlock_t lock; /* protect general shared data */ | |
1301 | spinlock_t hcmd_lock; /* protect hcmd */ | |
a8b50a0a | 1302 | spinlock_t reg_lock; /* protect hw register access */ |
5d08cd1d CH |
1303 | struct mutex mutex; |
1304 | ||
a48709c5 | 1305 | struct iwl_bus bus; /* bus specific data */ |
c85eb619 | 1306 | struct iwl_trans trans; |
a48709c5 | 1307 | |
246ed355 JB |
1308 | /* microcode/device supports multiple contexts */ |
1309 | u8 valid_contexts; | |
1310 | ||
13bb9483 JB |
1311 | /* command queue number */ |
1312 | u8 cmd_queue; | |
1313 | ||
c10afb6e JB |
1314 | /* max number of station keys */ |
1315 | u8 sta_key_max_num; | |
1316 | ||
d2690c0d JB |
1317 | bool new_scan_threshold_behaviour; |
1318 | ||
c6fa17ed WYG |
1319 | /* EEPROM MAC addresses */ |
1320 | struct mac_address addresses[2]; | |
1321 | ||
5d08cd1d | 1322 | /* uCode images, save to reload in case of failure */ |
b08dfd04 | 1323 | int fw_index; /* firmware we're trying to load */ |
c02b3acd CR |
1324 | u32 ucode_ver; /* version of ucode, copy of |
1325 | iwl_ucode.ver */ | |
e98a1939 WYG |
1326 | |
1327 | /* uCode owner: default: IWL_OWNERSHIP_DRIVER */ | |
1328 | u8 ucode_owner; | |
1329 | ||
dbf28e21 JB |
1330 | struct fw_img ucode_rt; |
1331 | struct fw_img ucode_init; | |
1332 | ||
872907bb | 1333 | enum iwlagn_ucode_type ucode_type; |
dbb983b7 | 1334 | u8 ucode_write_complete; /* the image write is complete */ |
b08dfd04 | 1335 | char firmware_name[25]; |
5d08cd1d | 1336 | |
246ed355 | 1337 | struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX]; |
5d08cd1d | 1338 | |
6f213ff1 | 1339 | __le16 switch_channel; |
0924e519 | 1340 | |
d7d5783c JB |
1341 | struct { |
1342 | u32 error_event_table; | |
1343 | u32 log_event_table; | |
1344 | } device_pointers; | |
5d08cd1d | 1345 | |
5d08cd1d | 1346 | u16 active_rate; |
5d08cd1d | 1347 | |
5d08cd1d | 1348 | u8 start_calib; |
f0832f13 EG |
1349 | struct iwl_sensitivity_data sensitivity_data; |
1350 | struct iwl_chain_noise_data chain_noise_data; | |
c8312fac | 1351 | bool enhance_sensitivity_table; |
5d08cd1d | 1352 | __le16 sensitivity_tbl[HD_TABLE_SIZE]; |
c8312fac | 1353 | __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES]; |
5d08cd1d | 1354 | |
fad95bf5 | 1355 | struct iwl_ht_config current_ht_config; |
5d08cd1d | 1356 | |
5d08cd1d | 1357 | /* Rate scaling data */ |
5d08cd1d CH |
1358 | u8 retry_rate; |
1359 | ||
1360 | wait_queue_head_t wait_command_queue; | |
1361 | ||
1362 | int activity_timer_active; | |
1363 | ||
1364 | /* Rx and Tx DMA processing queues */ | |
a55360e4 | 1365 | struct iwl_rx_queue rxq; |
88804e2b | 1366 | struct iwl_tx_queue *txq; |
5d08cd1d | 1367 | unsigned long txq_ctx_active_msk; |
4ddbb7d0 TW |
1368 | struct iwl_dma_ptr kw; /* keep warm address */ |
1369 | struct iwl_dma_ptr scd_bc_tbls; | |
1370 | ||
5d08cd1d CH |
1371 | u32 scd_base_addr; /* scheduler sram base address */ |
1372 | ||
1373 | unsigned long status; | |
5d08cd1d | 1374 | |
19758bef | 1375 | /* counts mgmt, ctl, and data packets */ |
22fdf3c9 WYG |
1376 | struct traffic_stats tx_stats; |
1377 | struct traffic_stats rx_stats; | |
19758bef | 1378 | |
a83b9141 WYG |
1379 | /* counts interrupts */ |
1380 | struct isr_statistics isr_stats; | |
1381 | ||
5da4b55f | 1382 | struct iwl_power_mgr power_data; |
3ad3b92a | 1383 | struct iwl_tt_mgmt thermal_throttle; |
5d08cd1d | 1384 | |
9c5ac091 RC |
1385 | /* station table variables */ |
1386 | ||
1387 | /* Note: if lock and sta_lock are needed, lock must be acquired first */ | |
5d08cd1d CH |
1388 | spinlock_t sta_lock; |
1389 | int num_stations; | |
3240cab3 | 1390 | struct iwl_station_entry stations[IWLAGN_STATION_COUNT]; |
80fb47a1 | 1391 | unsigned long ucode_key_table; |
5d08cd1d | 1392 | |
e4e72fb4 JB |
1393 | /* queue refcounts */ |
1394 | #define IWL_MAX_HW_QUEUES 32 | |
1395 | unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; | |
1396 | /* for each AC */ | |
1397 | atomic_t queue_stop_count[4]; | |
1398 | ||
5d08cd1d | 1399 | /* Indication if ieee80211_ops->open has been called */ |
69dc5d9d | 1400 | u8 is_open; |
5d08cd1d CH |
1401 | |
1402 | u8 mac80211_registered; | |
5d08cd1d | 1403 | |
af6b8ee3 | 1404 | /* eeprom -- this is in the card's little endian byte order */ |
073d3f5f | 1405 | u8 *eeprom; |
0848e297 | 1406 | int nvm_device_type; |
073d3f5f | 1407 | struct iwl_eeprom_calib_info *calib_info; |
5d08cd1d | 1408 | |
05c914fe | 1409 | enum nl80211_iftype iw_mode; |
5d08cd1d | 1410 | |
5d08cd1d | 1411 | /* Last Rx'd beacon timestamp */ |
3109ece1 | 1412 | u64 timestamp; |
5d08cd1d | 1413 | |
0da0e5bf JB |
1414 | struct { |
1415 | __le32 flag; | |
1416 | struct statistics_general_common common; | |
1417 | struct statistics_rx_non_phy rx_non_phy; | |
1418 | struct statistics_rx_phy rx_ofdm; | |
1419 | struct statistics_rx_ht_phy rx_ofdm_ht; | |
1420 | struct statistics_rx_phy rx_cck; | |
1421 | struct statistics_tx tx; | |
1422 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
1423 | struct statistics_bt_activity bt_activity; | |
1424 | __le32 num_bt_kills, accum_num_bt_kills; | |
1425 | #endif | |
1426 | } statistics; | |
1427 | #ifdef CONFIG_IWLWIFI_DEBUGFS | |
1428 | struct { | |
1429 | struct statistics_general_common common; | |
1430 | struct statistics_rx_non_phy rx_non_phy; | |
1431 | struct statistics_rx_phy rx_ofdm; | |
1432 | struct statistics_rx_ht_phy rx_ofdm_ht; | |
1433 | struct statistics_rx_phy rx_cck; | |
1434 | struct statistics_tx tx; | |
1435 | struct statistics_bt_activity bt_activity; | |
1436 | } accum_stats, delta_stats, max_delta_stats; | |
1437 | #endif | |
1438 | ||
3240cab3 JB |
1439 | struct { |
1440 | /* INT ICT Table */ | |
1441 | __le32 *ict_tbl; | |
1442 | void *ict_tbl_vir; | |
1443 | dma_addr_t ict_tbl_dma; | |
1444 | dma_addr_t aligned_ict_tbl_dma; | |
1445 | int ict_index; | |
1446 | u32 inta; | |
1447 | bool use_ict; | |
1448 | /* | |
1449 | * reporting the number of tids has AGG on. 0 means | |
1450 | * no AGGREGATION | |
1451 | */ | |
1452 | u8 agg_tids_count; | |
1453 | ||
1454 | struct iwl_rx_phy_res last_phy_res; | |
1455 | bool last_phy_res_valid; | |
1456 | ||
1457 | struct completion firmware_loading_complete; | |
1458 | ||
1459 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1460 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
1461 | ||
1462 | /* | |
1463 | * chain noise reset and gain commands are the | |
1464 | * two extra calibration commands follows the standard | |
1465 | * phy calibration commands | |
1466 | */ | |
1467 | u8 phy_calib_chain_noise_reset_cmd; | |
1468 | u8 phy_calib_chain_noise_gain_cmd; | |
1469 | ||
3240cab3 JB |
1470 | /* counts reply_tx error */ |
1471 | struct reply_tx_error_statistics reply_tx_stats; | |
1472 | struct reply_agg_tx_error_statistics reply_agg_tx_stats; | |
3240cab3 JB |
1473 | /* notification wait support */ |
1474 | struct list_head notif_waits; | |
1475 | spinlock_t notif_wait_lock; | |
1476 | wait_queue_head_t notif_waitq; | |
1477 | ||
1478 | /* remain-on-channel offload support */ | |
1479 | struct ieee80211_channel *hw_roc_channel; | |
1480 | struct delayed_work hw_roc_work; | |
1481 | enum nl80211_channel_type hw_roc_chantype; | |
1482 | int hw_roc_duration; | |
1483 | bool hw_roc_setup; | |
1484 | ||
1485 | struct sk_buff *offchan_tx_skb; | |
1486 | int offchan_tx_timeout; | |
1487 | struct ieee80211_channel *offchan_tx_chan; | |
1488 | } _agn; | |
ee525d13 | 1489 | |
22bf59a0 | 1490 | /* bt coex */ |
f21dd005 | 1491 | u8 bt_enable_flag; |
da5dbb97 | 1492 | u8 bt_status; |
66e863a5 | 1493 | u8 bt_traffic_load, last_bt_traffic_load; |
f37837c9 | 1494 | bool bt_ch_announce; |
bee008b7 WYG |
1495 | bool bt_full_concurrent; |
1496 | bool bt_ant_couple_ok; | |
fbba9410 WYG |
1497 | __le32 kill_ack_mask; |
1498 | __le32 kill_cts_mask; | |
1499 | __le16 bt_valid; | |
22bf59a0 WYG |
1500 | u16 bt_on_thresh; |
1501 | u16 bt_duration; | |
1502 | u16 dynamic_frag_thresh; | |
bee008b7 | 1503 | u8 bt_ci_compliance; |
9e4afc21 | 1504 | struct work_struct bt_traffic_change_work; |
207ecc5e MV |
1505 | bool bt_enable_pspoll; |
1506 | struct iwl_rxon_context *cur_rssi_ctx; | |
1507 | bool bt_is_sco; | |
9e4afc21 | 1508 | |
5425e490 | 1509 | struct iwl_hw_params hw_params; |
4ddbb7d0 | 1510 | |
40cefda9 | 1511 | u32 inta_mask; |
5d08cd1d | 1512 | |
5d08cd1d CH |
1513 | struct workqueue_struct *workqueue; |
1514 | ||
5d08cd1d | 1515 | struct work_struct restart; |
5d08cd1d CH |
1516 | struct work_struct scan_completed; |
1517 | struct work_struct rx_replenish; | |
5d08cd1d | 1518 | struct work_struct abort_scan; |
12e934dc | 1519 | |
5d08cd1d | 1520 | struct work_struct beacon_update; |
76d04815 | 1521 | struct iwl_rxon_context *beacon_ctx; |
12e934dc | 1522 | struct sk_buff *beacon_skb; |
4ce7cc2b | 1523 | void *beacon_cmd; |
76d04815 | 1524 | |
a28027cd WYG |
1525 | struct work_struct tt_work; |
1526 | struct work_struct ct_enter; | |
1527 | struct work_struct ct_exit; | |
88be0264 | 1528 | struct work_struct start_internal_scan; |
65550636 | 1529 | struct work_struct tx_flush; |
bee008b7 | 1530 | struct work_struct bt_full_concurrency; |
fbba9410 | 1531 | struct work_struct bt_runtime_config; |
5d08cd1d CH |
1532 | |
1533 | struct tasklet_struct irq_tasklet; | |
1534 | ||
5d08cd1d | 1535 | struct delayed_work scan_check; |
4a8a4322 | 1536 | |
630fe9b6 TW |
1537 | /* TX Power */ |
1538 | s8 tx_power_user_lmt; | |
dc1b0973 | 1539 | s8 tx_power_device_lmt; |
ae16fc3c | 1540 | s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */ |
a25a66ac | 1541 | s8 tx_power_next; |
5d08cd1d | 1542 | |
5d08cd1d | 1543 | |
d08853a3 | 1544 | #ifdef CONFIG_IWLWIFI_DEBUG |
5d08cd1d | 1545 | /* debugging info */ |
3d816c77 RC |
1546 | u32 debug_level; /* per device debugging will override global |
1547 | iwl_debug_level if set */ | |
d73e4923 | 1548 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
712b6cf5 TW |
1549 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1550 | /* debugfs */ | |
20594eb0 WYG |
1551 | u16 tx_traffic_idx; |
1552 | u16 rx_traffic_idx; | |
1553 | u8 *tx_traffic; | |
1554 | u8 *rx_traffic; | |
4c84a8f1 JB |
1555 | struct dentry *debugfs_dir; |
1556 | u32 dbgfs_sram_offset, dbgfs_sram_len; | |
d73e4923 | 1557 | bool disable_ht40; |
712b6cf5 | 1558 | #endif /* CONFIG_IWLWIFI_DEBUGFS */ |
5d08cd1d CH |
1559 | |
1560 | struct work_struct txpower_work; | |
445c2dff TW |
1561 | u32 disable_sens_cal; |
1562 | u32 disable_chain_noise_cal; | |
16e727e8 | 1563 | struct work_struct run_time_calib_work; |
5d08cd1d | 1564 | struct timer_list statistics_periodic; |
a9e1cb6a | 1565 | struct timer_list ucode_trace; |
22de94de | 1566 | struct timer_list watchdog; |
a9e1cb6a WYG |
1567 | |
1568 | struct iwl_event_log event_log; | |
5ed540ae WYG |
1569 | |
1570 | struct led_classdev led; | |
1571 | unsigned long blink_on, blink_off; | |
1572 | bool led_registered; | |
7a4e5281 WYG |
1573 | #ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL |
1574 | struct iwl_testmode_trace testmode_trace; | |
1575 | #endif | |
4e308119 | 1576 | u32 tm_fixed_rate; |
6489854b | 1577 | |
c79dd5b5 | 1578 | }; /*iwl_priv */ |
5d08cd1d | 1579 | |
36470749 RR |
1580 | static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id) |
1581 | { | |
1582 | set_bit(txq_id, &priv->txq_ctx_active_msk); | |
1583 | } | |
1584 | ||
1585 | static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id) | |
1586 | { | |
1587 | clear_bit(txq_id, &priv->txq_ctx_active_msk); | |
1588 | } | |
1589 | ||
994d31f7 | 1590 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 RC |
1591 | /* |
1592 | * iwl_get_debug_level: Return active debug level for device | |
1593 | * | |
1594 | * Using sysfs it is possible to set per device debug level. This debug | |
1595 | * level will be used if set, otherwise the global debug level which can be | |
1596 | * set via module parameter is used. | |
1597 | */ | |
1598 | static inline u32 iwl_get_debug_level(struct iwl_priv *priv) | |
1599 | { | |
1600 | if (priv->debug_level) | |
1601 | return priv->debug_level; | |
1602 | else | |
1603 | return iwl_debug_level; | |
1604 | } | |
a332f8d6 | 1605 | #else |
3d816c77 RC |
1606 | static inline u32 iwl_get_debug_level(struct iwl_priv *priv) |
1607 | { | |
1608 | return iwl_debug_level; | |
1609 | } | |
a332f8d6 TW |
1610 | #endif |
1611 | ||
1612 | ||
a332f8d6 TW |
1613 | static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv, |
1614 | int txq_id, int idx) | |
1615 | { | |
ff0d91c3 | 1616 | if (priv->txq[txq_id].txb[idx].skb) |
a332f8d6 | 1617 | return (struct ieee80211_hdr *)priv->txq[txq_id]. |
ff0d91c3 | 1618 | txb[idx].skb->data; |
a332f8d6 TW |
1619 | return NULL; |
1620 | } | |
a332f8d6 | 1621 | |
246ed355 JB |
1622 | static inline struct iwl_rxon_context * |
1623 | iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif) | |
1624 | { | |
1625 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; | |
1626 | ||
1627 | return vif_priv->ctx; | |
1628 | } | |
1629 | ||
1630 | #define for_each_context(priv, ctx) \ | |
1631 | for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \ | |
1632 | ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \ | |
1633 | if (priv->valid_contexts & BIT(ctx->ctxid)) | |
1634 | ||
054ec924 | 1635 | static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx) |
246ed355 | 1636 | { |
054ec924 | 1637 | return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; |
246ed355 JB |
1638 | } |
1639 | ||
054ec924 JB |
1640 | static inline int iwl_is_associated(struct iwl_priv *priv, |
1641 | enum iwl_rxon_context_id ctxid) | |
246ed355 | 1642 | { |
054ec924 | 1643 | return iwl_is_associated_ctx(&priv->contexts[ctxid]); |
246ed355 | 1644 | } |
a332f8d6 | 1645 | |
054ec924 | 1646 | static inline int iwl_is_any_associated(struct iwl_priv *priv) |
5d08cd1d | 1647 | { |
054ec924 JB |
1648 | struct iwl_rxon_context *ctx; |
1649 | for_each_context(priv, ctx) | |
1650 | if (iwl_is_associated_ctx(ctx)) | |
1651 | return true; | |
1652 | return false; | |
5d08cd1d CH |
1653 | } |
1654 | ||
bf85ea4f | 1655 | static inline int is_channel_valid(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1656 | { |
1657 | if (ch_info == NULL) | |
1658 | return 0; | |
1659 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1660 | } | |
1661 | ||
bf85ea4f | 1662 | static inline int is_channel_radar(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1663 | { |
1664 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1665 | } | |
1666 | ||
bf85ea4f | 1667 | static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1668 | { |
8318d78a | 1669 | return ch_info->band == IEEE80211_BAND_5GHZ; |
5d08cd1d CH |
1670 | } |
1671 | ||
bf85ea4f | 1672 | static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1673 | { |
8318d78a | 1674 | return ch_info->band == IEEE80211_BAND_2GHZ; |
5d08cd1d CH |
1675 | } |
1676 | ||
bf85ea4f | 1677 | static inline int is_channel_passive(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1678 | { |
1679 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1680 | } | |
1681 | ||
bf85ea4f | 1682 | static inline int is_channel_ibss(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1683 | { |
1684 | return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0; | |
1685 | } | |
1686 | ||
64a76b50 ZY |
1687 | static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page) |
1688 | { | |
1689 | __free_pages(page, priv->hw_params.rx_page_order); | |
64a76b50 ZY |
1690 | } |
1691 | ||
1692 | static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page) | |
1693 | { | |
1694 | free_pages(page, priv->hw_params.rx_page_order); | |
64a76b50 | 1695 | } |
be1f3ab6 | 1696 | #endif /* __iwl_dev_h__ */ |