iwlwifi: prepare for PAN queue/fifo assignment
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-4965-hw.h"
45#include "iwl-3945-hw.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
0975cc8f 50#include "iwl-agn-tt.h"
5d08cd1d 51
672639de
WYG
52struct iwl_tx_queue;
53
099b40b7 54/* CT-KILL constants */
672639de
WYG
55#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
56#define CT_KILL_THRESHOLD 114 /* in Celsius */
57#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 58
5d08cd1d
CH
59/* Default noise level to report when noise measurement is not available.
60 * This may be because we're:
61 * 1) Not associated (4965, no beacon statistics being sent to driver)
62 * 2) Scanning (noise measurement does not apply to associated channel)
63 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
64 * Use default noise value of -127 ... this is below the range of measurable
65 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
66 * Also, -127 works better than 0 when averaging frames with/without
67 * noise info (e.g. averaging might be done in app); measured dBm values are
68 * always negative ... using a negative value as the default keeps all
69 * averages within an s8's (used in some apps) range of negative values. */
70#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
71
5d08cd1d
CH
72/*
73 * RTS threshold here is total size [2347] minus 4 FCS bytes
74 * Per spec:
75 * a value of 0 means RTS on all data/management packets
76 * a value > max MSDU size means no RTS
77 * else RTS for data/management frames where MPDU is larger
78 * than RTS value.
79 */
80#define DEFAULT_RTS_THRESHOLD 2347U
81#define MIN_RTS_THRESHOLD 0U
82#define MAX_RTS_THRESHOLD 2347U
83#define MAX_MSDU_SIZE 2304U
84#define MAX_MPDU_SIZE 2346U
85#define DEFAULT_BEACON_INTERVAL 100U
86#define DEFAULT_SHORT_RETRY_LIMIT 7U
87#define DEFAULT_LONG_RETRY_LIMIT 4U
88
a55360e4 89struct iwl_rx_mem_buffer {
2f301227
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90 dma_addr_t page_dma;
91 struct page *page;
5d08cd1d
CH
92 struct list_head list;
93};
94
2f301227
ZY
95#define rxb_addr(r) page_address(r->page)
96
c2acea8e
JB
97/* defined below */
98struct iwl_device_cmd;
99
100struct iwl_cmd_meta {
101 /* only for SYNC commands, iff the reply skb is wanted */
102 struct iwl_host_cmd *source;
103 /*
104 * only for ASYNC commands
105 * (which is somewhat stupid -- look at iwl-sta.c for instance
106 * which duplicates a bunch of code because the callback isn't
107 * invoked for SYNC commands, if it were and its result passed
108 * through it would be simpler...)
109 */
5696aea6
JB
110 void (*callback)(struct iwl_priv *priv,
111 struct iwl_device_cmd *cmd,
2f301227 112 struct iwl_rx_packet *pkt);
c2acea8e
JB
113
114 /* The CMD_SIZE_HUGE flag bit indicates that the command
115 * structure is stored at the end of the shared queue memory. */
116 u32 flags;
117
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FT
118 DEFINE_DMA_UNMAP_ADDR(mapping);
119 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
120};
121
5d08cd1d
CH
122/*
123 * Generic queue structure
124 *
125 * Contains common data for Rx and Tx queues
126 */
443cfd45 127struct iwl_queue {
5d08cd1d
CH
128 int n_bd; /* number of BDs in this queue */
129 int write_ptr; /* 1-st empty entry (index) host_w*/
130 int read_ptr; /* last used entry (index) host_r*/
b74e31a9
WYG
131 /* use for monitoring and recovering the stuck queue */
132 int last_read_ptr; /* storing the last read_ptr */
133 /* number of time read_ptr and last_read_ptr are the same */
134 u8 repeat_same_read_ptr;
5d08cd1d
CH
135 dma_addr_t dma_addr; /* physical addr for BD's */
136 int n_window; /* safe queue window */
137 u32 id;
138 int low_mark; /* low watermark, resume queue if free
139 * space more than this */
140 int high_mark; /* high watermark, stop queue if free
141 * space less than this */
ba2d3587 142} __packed;
5d08cd1d 143
bc47279f 144/* One for each TFD */
8567c63e 145struct iwl_tx_info {
ff0d91c3 146 struct sk_buff *skb;
5d08cd1d
CH
147};
148
149/**
16466903 150 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
151 * @q: generic Rx/Tx queue descriptor
152 * @bd: base of circular buffer of TFDs
c2acea8e
JB
153 * @cmd: array of command/TX buffer pointers
154 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
155 * @dma_addr_cmd: physical address of cmd/tx buffer array
156 * @txb: array of per-TFD driver data
157 * @need_update: indicates need to update read/write index
158 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 159 *
bc47279f
BC
160 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
161 * descriptors) and required locking structures.
5d08cd1d 162 */
188cf6c7
SO
163#define TFD_TX_CMD_SLOTS 256
164#define TFD_CMD_SLOTS 32
165
16466903 166struct iwl_tx_queue {
443cfd45 167 struct iwl_queue q;
59606ffa 168 void *tfds;
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JB
169 struct iwl_device_cmd **cmd;
170 struct iwl_cmd_meta *meta;
8567c63e 171 struct iwl_tx_info *txb;
3fd07a1e
TW
172 u8 need_update;
173 u8 sched_retry;
174 u8 active;
175 u8 swq_id;
5d08cd1d
CH
176};
177
178#define IWL_NUM_SCAN_RATES (2)
179
bb8c093b 180struct iwl4965_channel_tgd_info {
5d08cd1d
CH
181 u8 type;
182 s8 max_power;
183};
184
bb8c093b 185struct iwl4965_channel_tgh_info {
5d08cd1d
CH
186 s64 last_radar_time;
187};
188
d20b3c65
SO
189#define IWL4965_MAX_RATE (33)
190
85d41495
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191struct iwl3945_clip_group {
192 /* maximum power level to prevent clipping for each rate, derived by
193 * us from this band's saturation power in EEPROM */
194 const s8 clip_powers[IWL_MAX_RATES];
195};
196
d20b3c65
SO
197/* current Tx power values to use, one for each rate for each channel.
198 * requested power is limited by:
199 * -- regulatory EEPROM limits for this channel
200 * -- hardware capabilities (clip-powers)
201 * -- spectrum management
202 * -- user preference (e.g. iwconfig)
203 * when requested power is set, base power index must also be set. */
204struct iwl3945_channel_power_info {
205 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
206 s8 power_table_index; /* actual (compenst'd) index into gain table */
207 s8 base_power_index; /* gain index for power at factory temp. */
208 s8 requested_power; /* power (dBm) requested for this chnl/rate */
209};
210
211/* current scan Tx power values to use, one for each scan rate for each
212 * channel. */
213struct iwl3945_scan_power_info {
214 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
215 s8 power_table_index; /* actual (compenst'd) index into gain table */
216 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
217};
218
5d08cd1d
CH
219/*
220 * One for each channel, holds all channel setup data
221 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
222 * with one another!
223 */
bf85ea4f 224struct iwl_channel_info {
bb8c093b
CH
225 struct iwl4965_channel_tgd_info tgd;
226 struct iwl4965_channel_tgh_info tgh;
073d3f5f 227 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
228 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
229 * HT40 channel */
5d08cd1d
CH
230
231 u8 channel; /* channel number */
232 u8 flags; /* flags copied from EEPROM */
233 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 234 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
235 s8 min_power; /* always 0 */
236 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
237
238 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
239 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 240 enum ieee80211_band band;
5d08cd1d 241
7aafef1c
WYG
242 /* HT40 channel info */
243 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
244 u8 ht40_flags; /* flags copied from EEPROM */
245 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
246
247 /* Radio/DSP gain settings for each "normal" data Tx rate.
248 * These include, in addition to RF and DSP gain, a few fields for
249 * remembering/modifying gain settings (indexes). */
250 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
251
252 /* Radio/DSP gain settings for each scan rate, for directed scans. */
253 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
254};
255
edc1a3a0
JB
256#define IWL_TX_FIFO_BK 0
257#define IWL_TX_FIFO_BE 1
258#define IWL_TX_FIFO_VI 2
259#define IWL_TX_FIFO_VO 3
260#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 261
01a7e084
RC
262/* Minimum number of queues. MAX_NUM is defined in hw specific files.
263 * Set the minimum to accommodate the 4 standard TX queues, 1 command
264 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
265#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 266
bd35f150 267/*
13bb9483 268 * Command queue depends on iPAN support.
bd35f150 269 */
13bb9483
JB
270#define IWL_DEFAULT_CMD_QUEUE_NUM 4
271#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 272
5d08cd1d
CH
273/* Power management (not Tx power) structures */
274
6f4083aa
TW
275enum iwl_pwr_src {
276 IWL_PWR_SRC_VMAIN,
277 IWL_PWR_SRC_VAUX,
278};
279
5d08cd1d
CH
280#define IEEE80211_DATA_LEN 2304
281#define IEEE80211_4ADDR_LEN 30
282#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
283#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
284
fcab423d 285struct iwl_frame {
5d08cd1d
CH
286 union {
287 struct ieee80211_hdr frame;
4bf64efd 288 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
289 u8 raw[IEEE80211_FRAME_LEN];
290 u8 cmd[360];
291 } u;
292 struct list_head list;
293};
294
5d08cd1d
CH
295#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
296#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
297#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
298
299enum {
c587de0b
TW
300 CMD_SYNC = 0,
301 CMD_SIZE_NORMAL = 0,
302 CMD_NO_SKB = 0,
5d08cd1d 303 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 304 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
305 CMD_WANT_SKB = (1 << 2),
306};
307
c8c24872 308#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 309
bc47279f 310/**
c2acea8e 311 * struct iwl_device_cmd
bc47279f
BC
312 *
313 * For allocation of the command and tx queues, this establishes the overall
314 * size of the largest command we send to uCode, except for a scan command
315 * (which is relatively huge; space is allocated separately).
316 */
c2acea8e 317struct iwl_device_cmd {
857485c0 318 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 319 union {
5d08cd1d
CH
320 u32 flags;
321 u8 val8;
322 u16 val16;
323 u32 val32;
83d527d9 324 struct iwl_tx_cmd tx;
c8c24872
WYG
325 struct iwl6000_channel_switch_cmd chswitch;
326 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
327 } __packed cmd;
328} __packed;
5d08cd1d 329
c2acea8e
JB
330#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
331
3257e5d4 332
857485c0 333struct iwl_host_cmd {
5d08cd1d 334 const void *data;
2f301227 335 unsigned long reply_page;
5696aea6
JB
336 void (*callback)(struct iwl_priv *priv,
337 struct iwl_device_cmd *cmd,
2f301227 338 struct iwl_rx_packet *pkt);
c2acea8e
JB
339 u32 flags;
340 u16 len;
341 u8 id;
5d08cd1d
CH
342};
343
5d08cd1d
CH
344#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
345#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
346#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
347
348/**
a55360e4 349 * struct iwl_rx_queue - Rx queue
df833b1d 350 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 351 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
352 * @read: Shared index to newest available Rx buffer
353 * @write: Shared index to oldest written Rx packet
354 * @free_count: Number of pre-allocated buffers in rx_free
355 * @rx_free: list of free SKBs for use
356 * @rx_used: List of Rx buffers with no SKB
357 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
358 * @rb_stts: driver's pointer to receive buffer status
359 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 360 *
a55360e4 361 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 362 */
a55360e4 363struct iwl_rx_queue {
5d08cd1d 364 __le32 *bd;
d5b25c90 365 dma_addr_t bd_dma;
a55360e4
TW
366 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
367 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
368 u32 read;
369 u32 write;
370 u32 free_count;
4752c93c 371 u32 write_actual;
5d08cd1d
CH
372 struct list_head rx_free;
373 struct list_head rx_used;
374 int need_update;
8d86422a
WT
375 struct iwl_rb_status *rb_stts;
376 dma_addr_t rb_stts_dma;
5d08cd1d
CH
377 spinlock_t lock;
378};
379
380#define IWL_SUPPORTED_RATES_IE_LEN 8
381
5d08cd1d
CH
382#define MAX_TID_COUNT 9
383
384#define IWL_INVALID_RATE 0xFF
385#define IWL_INVALID_VALUE -1
386
bc47279f 387/**
6def9761 388 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
389 * @txq_id: Tx queue used for Tx attempt
390 * @frame_count: # frames attempted by Tx command
391 * @wait_for_ba: Expect block-ack before next Tx reply
392 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
393 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
394 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
395 * @rate_n_flags: Rate at which Tx was attempted
396 *
397 * If REPLY_TX indicates that aggregation was attempted, driver must wait
398 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
399 * until block ack arrives.
400 */
6def9761 401struct iwl_ht_agg {
5d08cd1d
CH
402 u16 txq_id;
403 u16 frame_count;
404 u16 wait_for_ba;
405 u16 start_idx;
fe01b477 406 u64 bitmap;
5d08cd1d 407 u32 rate_n_flags;
fe01b477
RR
408#define IWL_AGG_OFF 0
409#define IWL_AGG_ON 1
410#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
411#define IWL_EMPTYING_HW_QUEUE_DELBA 3
412 u8 state;
5d08cd1d 413};
fe01b477 414
5d08cd1d 415
6def9761 416struct iwl_tid_data {
f862a236 417 u16 seq_number; /* agn only */
fe01b477 418 u16 tfds_in_queue;
6def9761 419 struct iwl_ht_agg agg;
5d08cd1d
CH
420};
421
6def9761 422struct iwl_hw_key {
97359d12 423 u32 cipher;
5d08cd1d 424 int keylen;
0211ddda 425 u8 keyidx;
5d08cd1d
CH
426 u8 key[32];
427};
428
a78fe754 429union iwl_ht_rate_supp {
5d08cd1d
CH
430 u16 rates;
431 struct {
432 u8 siso_rate;
433 u8 mimo_rate;
434 };
435};
436
172c1d11
WYG
437#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
438#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
439#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
440#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
441#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
442#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
443#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
444
445/*
446 * Maximal MPDU density for TX aggregation
447 * 4 - 2us density
448 * 5 - 4us density
449 * 6 - 8us density
450 * 7 - 16us density
451 */
172c1d11 452#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 453#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
454#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
455#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 456#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
457#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
458#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 459
fad95bf5 460struct iwl_ht_config {
9e0cc6de 461 /* self configuration data */
c812ee24
JB
462 bool is_ht;
463 bool is_40mhz;
02bb1bea 464 bool single_chain_sufficient;
ba37a3d0 465 enum ieee80211_smps_mode smps; /* current smps mode */
9e0cc6de 466 /* BSS related data */
5d08cd1d 467 u8 extension_chan_offset;
9e0cc6de
RR
468 u8 ht_protection;
469 u8 non_GF_STA_present;
5d08cd1d 470};
5d08cd1d 471
5d08cd1d 472/* QoS structures */
1ff50bda 473struct iwl_qos_info {
5d08cd1d 474 int qos_active;
1ff50bda 475 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 476};
5d08cd1d 477
fe6b23dd
RC
478/*
479 * Structure should be accessed with sta_lock held. When station addition
480 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
481 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
482 * held.
483 */
6def9761 484struct iwl_station_entry {
133636de 485 struct iwl_addsta_cmd sta;
6def9761 486 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d 487 u8 used;
6def9761 488 struct iwl_hw_key keyinfo;
fe6b23dd 489 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
490};
491
fd1af15d
JB
492struct iwl_station_priv_common {
493 u8 sta_id;
494};
495
8d9698b3
RC
496/*
497 * iwl_station_priv: Driver's private station information
498 *
499 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
500 * in the structure for use by driver. This structure is places in that
501 * space.
fd1af15d
JB
502 *
503 * The common struct MUST be first because it is shared between
504 * 3945 and agn!
8d9698b3
RC
505 */
506struct iwl_station_priv {
fd1af15d 507 struct iwl_station_priv_common common;
8d9698b3 508 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
509 atomic_t pending_frames;
510 bool client;
511 bool asleep;
8d9698b3
RC
512};
513
fd1af15d
JB
514/**
515 * struct iwl_vif_priv - driver's private per-interface information
516 *
517 * When mac80211 allocates a virtual interface, it can allocate
518 * space for us to put data into.
519 */
520struct iwl_vif_priv {
246ed355 521 struct iwl_rxon_context *ctx;
fd1af15d
JB
522 u8 ibss_bssid_sta_id;
523};
524
5d08cd1d
CH
525/* one for each uCode image (inst/data, boot/init/runtime) */
526struct fw_desc {
527 void *v_addr; /* access by driver */
528 dma_addr_t p_addr; /* access by card's busmaster DMA */
529 u32 len; /* bytes */
530};
531
dd7a2509 532/* v1/v2 uCode file layout */
cc0f555d
JS
533struct iwl_ucode_header {
534 __le32 ver; /* major/minor/API/serial */
535 union {
536 struct {
537 __le32 inst_size; /* bytes of runtime code */
538 __le32 data_size; /* bytes of runtime data */
539 __le32 init_size; /* bytes of init code */
540 __le32 init_data_size; /* bytes of init data */
541 __le32 boot_size; /* bytes of bootstrap code */
542 u8 data[0]; /* in same order as sizes */
543 } v1;
544 struct {
545 __le32 build; /* build number */
546 __le32 inst_size; /* bytes of runtime code */
547 __le32 data_size; /* bytes of runtime data */
548 __le32 init_size; /* bytes of init code */
549 __le32 init_data_size; /* bytes of init data */
550 __le32 boot_size; /* bytes of bootstrap code */
551 u8 data[0]; /* in same order as sizes */
552 } v2;
553 } u;
5d08cd1d
CH
554};
555
dd7a2509
JB
556/*
557 * new TLV uCode file layout
558 *
559 * The new TLV file format contains TLVs, that each specify
560 * some piece of data. To facilitate "groups", for example
561 * different instruction image with different capabilities,
562 * bundled with the same init image, an alternative mechanism
563 * is provided:
564 * When the alternative field is 0, that means that the item
565 * is always valid. When it is non-zero, then it is only
566 * valid in conjunction with items of the same alternative,
567 * in which case the driver (user) selects one alternative
568 * to use.
569 */
570
571enum iwl_ucode_tlv_type {
572 IWL_UCODE_TLV_INVALID = 0, /* unused */
573 IWL_UCODE_TLV_INST = 1,
574 IWL_UCODE_TLV_DATA = 2,
575 IWL_UCODE_TLV_INIT = 3,
576 IWL_UCODE_TLV_INIT_DATA = 4,
577 IWL_UCODE_TLV_BOOT = 5,
578 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
b2e640d4
JB
579 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
580 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
581 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
582 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
583 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
584 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 585 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 586 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
dd7a2509
JB
587};
588
589struct iwl_ucode_tlv {
590 __le16 type; /* see above */
591 __le16 alternative; /* see comment */
592 __le32 length; /* not including type/length fields */
593 u8 data[0];
ba2d3587 594} __packed;
dd7a2509
JB
595
596#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
597
598struct iwl_tlv_ucode_header {
599 /*
600 * The TLV style ucode header is distinguished from
601 * the v1/v2 style header by first four bytes being
602 * zero, as such is an invalid combination of
603 * major/minor/API/serial versions.
604 */
605 __le32 zero;
606 __le32 magic;
607 u8 human_readable[64];
608 __le32 ver; /* major/minor/API/serial */
609 __le32 build;
610 __le64 alternatives; /* bitmask of valid alternatives */
611 /*
612 * The data contained herein has a TLV layout,
613 * see above for the TLV header and types.
614 * Note that each TLV is padded to a length
615 * that is a multiple of 4 for alignment.
616 */
617 u8 data[0];
618};
619
bb8c093b 620struct iwl4965_ibss_seq {
5d08cd1d
CH
621 u8 mac[ETH_ALEN];
622 u16 seq_num;
623 u16 frag_num;
624 unsigned long packet_time;
625 struct list_head list;
626};
627
f0832f13
EG
628struct iwl_sensitivity_ranges {
629 u16 min_nrg_cck;
630 u16 max_nrg_cck;
631
632 u16 nrg_th_cck;
633 u16 nrg_th_ofdm;
634
635 u16 auto_corr_min_ofdm;
636 u16 auto_corr_min_ofdm_mrc;
637 u16 auto_corr_min_ofdm_x1;
638 u16 auto_corr_min_ofdm_mrc_x1;
639
640 u16 auto_corr_max_ofdm;
641 u16 auto_corr_max_ofdm_mrc;
642 u16 auto_corr_max_ofdm_x1;
643 u16 auto_corr_max_ofdm_mrc_x1;
644
645 u16 auto_corr_max_cck;
646 u16 auto_corr_max_cck_mrc;
647 u16 auto_corr_min_cck;
648 u16 auto_corr_min_cck_mrc;
55036d66
WYG
649
650 u16 barker_corr_th_min;
651 u16 barker_corr_th_min_mrc;
652 u16 nrg_th_cca;
f0832f13
EG
653};
654
099b40b7 655
b5047f78
TW
656#define KELVIN_TO_CELSIUS(x) ((x)-273)
657#define CELSIUS_TO_KELVIN(x) ((x)+273)
658
659
bc47279f 660/**
5425e490 661 * struct iwl_hw_params
bc47279f 662 * @max_txq_num: Max # Tx queues supported
f3f911d1 663 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 664 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 665 * @tfd_size: TFD size
099b40b7
RR
666 * @tx/rx_chains_num: Number of TX/RX chains
667 * @valid_tx/rx_ant: usable antennas
bc47279f 668 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 669 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 670 * @rx_page_order: Rx buffer page order
141c43a3 671 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f
BC
672 * @max_stations:
673 * @bcast_sta_id:
7aafef1c 674 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
675 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
676 * @sw_crypto: 0 for hw, 1 for sw
677 * @max_xxx_size: for ucode uses
678 * @ct_kill_threshold: temperature threshold
a0ee74cf 679 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 680 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 681 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 682 */
5425e490 683struct iwl_hw_params {
f3f911d1
ZY
684 u8 max_txq_num;
685 u8 dma_chnl_num;
4ddbb7d0 686 u16 scd_bc_tbls_size;
a8e74e27 687 u32 tfd_size;
ec35cf2a
TW
688 u8 tx_chains_num;
689 u8 rx_chains_num;
690 u8 valid_tx_ant;
691 u8 valid_rx_ant;
5d08cd1d 692 u16 max_rxq_size;
ec35cf2a 693 u16 max_rxq_log;
2f301227 694 u32 rx_page_order;
141c43a3 695 u32 rx_wrt_ptr_reg;
5d08cd1d
CH
696 u8 max_stations;
697 u8 bcast_sta_id;
7aafef1c 698 u8 ht40_channel;
2c2f3b33 699 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
700 u32 max_inst_size;
701 u32 max_data_size;
702 u32 max_bsm_size;
703 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
704 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
705 /* for 1000, 6000 series and up */
a0ee74cf 706 u16 beacon_time_tsf_bits;
be5d56ed 707 u32 calib_init_cfg;
f0832f13 708 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
709};
710
5d08cd1d 711
5d08cd1d
CH
712/******************************************************************************
713 *
a33c2f47
EG
714 * Functions implemented in core module which are forward declared here
715 * for use by iwl-[4-5].c
5d08cd1d 716 *
a33c2f47
EG
717 * NOTE: The implementation of these functions are not hardware specific
718 * which is why they are in the core module files.
5d08cd1d
CH
719 *
720 * Naming convention --
a33c2f47 721 * iwl_ <-- Is part of iwlwifi
5d08cd1d 722 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
723 * iwl4965_bg_ <-- Called from work queue context
724 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
725 *
726 ****************************************************************************/
5b9f8cd3
EG
727extern void iwl_update_chain_flags(struct iwl_priv *priv);
728extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 729extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 730extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 731extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 732extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
733static inline int iwl_queue_used(const struct iwl_queue *q, int i)
734{
c8106d76 735 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
736 (i >= q->read_ptr && i < q->write_ptr) :
737 !(i < q->read_ptr && i >= q->write_ptr);
738}
739
740
741static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
742{
c8c24872
WYG
743 /*
744 * This is for init calibration result and scan command which
745 * required buffer > TFD_MAX_PAYLOAD_SIZE,
746 * the big buffer at end of command array
747 */
fd4abac5
TW
748 if (is_huge)
749 return q->n_window; /* must be power of 2 */
750
751 /* Otherwise, use normal size buffers */
752 return index & (q->n_window - 1);
753}
754
755
4ddbb7d0
TW
756struct iwl_dma_ptr {
757 dma_addr_t dma;
758 void *addr;
b481de9c
ZY
759 size_t size;
760};
761
b481de9c
ZY
762#define IWL_OPERATION_MODE_AUTO 0
763#define IWL_OPERATION_MODE_HT_ONLY 1
764#define IWL_OPERATION_MODE_MIXED 2
765#define IWL_OPERATION_MODE_20MHZ 3
766
3195cdb7
TW
767#define IWL_TX_CRC_SIZE 4
768#define IWL_TX_DELIMITER_SIZE 4
b481de9c 769
b481de9c 770#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 771
b481de9c 772/* Sensitivity and chain noise calibration */
b481de9c 773#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
774#define IWL4965_CAL_NUM_BEACONS 20
775#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
776#define MAXIMUM_ALLOWED_PATHLOSS 15
777
b481de9c
ZY
778#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
779
780#define MAX_FA_OFDM 50
781#define MIN_FA_OFDM 5
782#define MAX_FA_CCK 50
783#define MIN_FA_CCK 5
784
b481de9c
ZY
785#define AUTO_CORR_STEP_OFDM 1
786
b481de9c
ZY
787#define AUTO_CORR_STEP_CCK 3
788#define AUTO_CORR_MAX_TH_CCK 160
789
b481de9c
ZY
790#define NRG_DIFF 2
791#define NRG_STEP_CCK 2
792#define NRG_MARGIN 8
793#define MAX_NUMBER_CCK_NO_FA 100
794
795#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
796
797#define CHAIN_A 0
798#define CHAIN_B 1
799#define CHAIN_C 2
800#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
801#define ALL_BAND_FILTER 0xFF00
802#define IN_BAND_FILTER 0xFF
803#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
804
3195cdb7
TW
805#define NRG_NUM_PREV_STAT_L 20
806#define NUM_RX_CHAINS 3
807
bb8c093b 808enum iwl4965_false_alarm_state {
b481de9c
ZY
809 IWL_FA_TOO_MANY = 0,
810 IWL_FA_TOO_FEW = 1,
811 IWL_FA_GOOD_RANGE = 2,
812};
813
bb8c093b 814enum iwl4965_chain_noise_state {
b481de9c 815 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
816 IWL_CHAIN_NOISE_ACCUMULATE,
817 IWL_CHAIN_NOISE_CALIBRATED,
818 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
819};
820
bb8c093b 821enum iwl4965_calib_enabled_state {
b481de9c
ZY
822 IWL_CALIB_DISABLED = 0, /* must be 0 */
823 IWL_CALIB_ENABLED = 1,
824};
825
f69f42a6
TW
826
827/*
828 * enum iwl_calib
829 * defines the order in which results of initial calibrations
830 * should be sent to the runtime uCode
831 */
832enum iwl_calib {
833 IWL_CALIB_XTAL,
819500c5 834 IWL_CALIB_DC,
f69f42a6
TW
835 IWL_CALIB_LO,
836 IWL_CALIB_TX_IQ,
837 IWL_CALIB_TX_IQ_PERD,
201706ac 838 IWL_CALIB_BASE_BAND,
f69f42a6
TW
839 IWL_CALIB_MAX
840};
841
6e21f2c1
TW
842/* Opaque calibration results */
843struct iwl_calib_result {
844 void *buf;
845 size_t buf_len;
7c616cba
TW
846};
847
dbb983b7
RR
848enum ucode_type {
849 UCODE_NONE = 0,
850 UCODE_INIT,
851 UCODE_RT
852};
853
b481de9c 854/* Sensitivity calib data */
f0832f13 855struct iwl_sensitivity_data {
b481de9c
ZY
856 u32 auto_corr_ofdm;
857 u32 auto_corr_ofdm_mrc;
858 u32 auto_corr_ofdm_x1;
859 u32 auto_corr_ofdm_mrc_x1;
860 u32 auto_corr_cck;
861 u32 auto_corr_cck_mrc;
862
863 u32 last_bad_plcp_cnt_ofdm;
864 u32 last_fa_cnt_ofdm;
865 u32 last_bad_plcp_cnt_cck;
866 u32 last_fa_cnt_cck;
867
868 u32 nrg_curr_state;
869 u32 nrg_prev_state;
870 u32 nrg_value[10];
871 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
872 u32 nrg_silence_ref;
873 u32 nrg_energy_idx;
874 u32 nrg_silence_idx;
875 u32 nrg_th_cck;
876 s32 nrg_auto_corr_silence_diff;
877 u32 num_in_cck_no_fa;
878 u32 nrg_th_ofdm;
55036d66
WYG
879
880 u16 barker_corr_th_min;
881 u16 barker_corr_th_min_mrc;
882 u16 nrg_th_cca;
b481de9c
ZY
883};
884
885/* Chain noise (differential Rx gain) calib data */
f0832f13 886struct iwl_chain_noise_data {
04816448 887 u32 active_chains;
b481de9c
ZY
888 u32 chain_noise_a;
889 u32 chain_noise_b;
890 u32 chain_noise_c;
891 u32 chain_signal_a;
892 u32 chain_signal_b;
893 u32 chain_signal_c;
04816448 894 u16 beacon_count;
b481de9c
ZY
895 u8 disconn_array[NUM_RX_CHAINS];
896 u8 delta_gain_code[NUM_RX_CHAINS];
897 u8 radio_write;
04816448 898 u8 state;
b481de9c
ZY
899};
900
abceddb4
BC
901#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
902#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 903
20594eb0
WYG
904#define IWL_TRAFFIC_ENTRIES (256)
905#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 906
5d08cd1d
CH
907enum {
908 MEASUREMENT_READY = (1 << 0),
909 MEASUREMENT_ACTIVE = (1 << 1),
910};
911
0848e297
WYG
912enum iwl_nvm_type {
913 NVM_DEVICE_TYPE_EEPROM = 0,
914 NVM_DEVICE_TYPE_OTP,
915};
916
415e4993
WYG
917/*
918 * Two types of OTP memory access modes
919 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
920 * based on physical memory addressing
921 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
922 * based on logical memory addressing
923 */
924enum iwl_access_mode {
925 IWL_OTP_ACCESS_ABSOLUTE,
926 IWL_OTP_ACCESS_RELATIVE,
927};
65b7998a
WYG
928
929/**
930 * enum iwl_pa_type - Power Amplifier type
931 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
932 * @IWL_PA_INTERNAL: use Internal only
933 */
934enum iwl_pa_type {
935 IWL_PA_SYSTEM = 0,
740e7f51 936 IWL_PA_INTERNAL = 1,
65b7998a
WYG
937};
938
a83b9141
WYG
939/* interrupt statistics */
940struct isr_statistics {
941 u32 hw;
942 u32 sw;
943 u32 sw_err;
944 u32 sch;
945 u32 alive;
946 u32 rfkill;
947 u32 ctkill;
948 u32 wakeup;
949 u32 rx;
950 u32 rx_handlers[REPLY_MAX];
951 u32 tx;
952 u32 unhandled;
953};
5d08cd1d 954
22fdf3c9
WYG
955#ifdef CONFIG_IWLWIFI_DEBUGFS
956/* management statistics */
957enum iwl_mgmt_stats {
958 MANAGEMENT_ASSOC_REQ = 0,
959 MANAGEMENT_ASSOC_RESP,
960 MANAGEMENT_REASSOC_REQ,
961 MANAGEMENT_REASSOC_RESP,
962 MANAGEMENT_PROBE_REQ,
963 MANAGEMENT_PROBE_RESP,
964 MANAGEMENT_BEACON,
965 MANAGEMENT_ATIM,
966 MANAGEMENT_DISASSOC,
967 MANAGEMENT_AUTH,
968 MANAGEMENT_DEAUTH,
969 MANAGEMENT_ACTION,
970 MANAGEMENT_MAX,
971};
972/* control statistics */
973enum iwl_ctrl_stats {
974 CONTROL_BACK_REQ = 0,
975 CONTROL_BACK,
976 CONTROL_PSPOLL,
977 CONTROL_RTS,
978 CONTROL_CTS,
979 CONTROL_ACK,
980 CONTROL_CFEND,
981 CONTROL_CFENDACK,
982 CONTROL_MAX,
983};
984
985struct traffic_stats {
986 u32 mgmt[MANAGEMENT_MAX];
987 u32 ctrl[CONTROL_MAX];
988 u32 data_cnt;
989 u64 data_bytes;
990};
991#else
992struct traffic_stats {
993 u64 data_bytes;
994};
995#endif
996
0924e519
WYG
997/*
998 * iwl_switch_rxon: "channel switch" structure
999 *
1000 * @ switch_in_progress: channel switch in progress
1001 * @ channel: new channel
1002 */
1003struct iwl_switch_rxon {
1004 bool switch_in_progress;
1005 __le16 channel;
1006};
1007
a9e1cb6a
WYG
1008/*
1009 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
1010 * to perform continuous uCode event logging operation if enabled
1011 */
1012#define UCODE_TRACE_PERIOD (100)
1013
1014/*
1015 * iwl_event_log: current uCode event log position
1016 *
1017 * @ucode_trace: enable/disable ucode continuous trace timer
1018 * @num_wraps: how many times the event buffer wraps
1019 * @next_entry: the entry just before the next one that uCode would fill
1020 * @non_wraps_count: counter for no wrap detected when dump ucode events
1021 * @wraps_once_count: counter for wrap once detected when dump ucode events
1022 * @wraps_more_count: counter for wrap more than once detected
1023 * when dump ucode events
1024 */
1025struct iwl_event_log {
1026 bool ucode_trace;
1027 u32 num_wraps;
1028 u32 next_entry;
1029 int non_wraps_count;
1030 int wraps_once_count;
1031 int wraps_more_count;
1032};
1033
2be76703
WYG
1034/*
1035 * host interrupt timeout value
1036 * used with setting interrupt coalescing timer
1037 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1038 *
1039 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1040 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1041 */
1042#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1043#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1044#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1045#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1046#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1047#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1048
3e4fb5fa
TAN
1049/*
1050 * This is the threshold value of plcp error rate per 100mSecs. It is
1051 * used to set and check for the validity of plcp_delta.
1052 */
680788ac 1053#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1054#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1055#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1056#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1057#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1058#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1059
8a472da4
WYG
1060#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1061#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1062
b74e31a9 1063/* timer constants use to monitor and recover stuck tx queues in mSecs */
ce60659a
WYG
1064#define IWL_DEF_MONITORING_PERIOD (1000)
1065#define IWL_LONG_MONITORING_PERIOD (5000)
b74e31a9 1066#define IWL_ONE_HUNDRED_MSECS (100)
7bdc473c 1067#define IWL_MAX_MONITORING_PERIOD (60000)
b74e31a9 1068
bee008b7
WYG
1069/* BT Antenna Coupling Threshold (dB) */
1070#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1071
a93e7973
WYG
1072enum iwl_reset {
1073 IWL_RF_RESET = 0,
1074 IWL_FW_RESET,
8a472da4
WYG
1075 IWL_MAX_FORCE_RESET,
1076};
1077
1078struct iwl_force_reset {
1079 int reset_request_count;
1080 int reset_success_count;
1081 int reset_reject_count;
1082 unsigned long reset_duration;
1083 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1084};
1085
a0ee74cf
WYG
1086/* extend beacon time format bit shifting */
1087/*
1088 * for _3945 devices
1089 * bits 31:24 - extended
1090 * bits 23:0 - interval
1091 */
1092#define IWL3945_EXT_BEACON_TIME_POS 24
1093/*
1094 * for _agn devices
1095 * bits 31:22 - extended
1096 * bits 21:0 - interval
1097 */
1098#define IWLAGN_EXT_BEACON_TIME_POS 22
1099
246ed355
JB
1100enum iwl_rxon_context_id {
1101 IWL_RXON_CTX_BSS,
1102
1103 NUM_IWL_RXON_CTX
1104};
1105
1106struct iwl_rxon_context {
1107 enum iwl_rxon_context_id ctxid;
1108 /*
1109 * We declare this const so it can only be
1110 * changed via explicit cast within the
1111 * routines that actually update the physical
1112 * hardware.
1113 */
1114 const struct iwl_rxon_cmd active;
1115 struct iwl_rxon_cmd staging;
1116
1117 struct iwl_rxon_time_cmd timing;
1118};
1119
c79dd5b5 1120struct iwl_priv {
5d08cd1d
CH
1121
1122 /* ieee device used by generic ieee processing code */
1123 struct ieee80211_hw *hw;
1124 struct ieee80211_channel *ieee_channels;
1125 struct ieee80211_rate *ieee_rates;
82b9a121 1126 struct iwl_cfg *cfg;
5d08cd1d
CH
1127
1128 /* temporary frame storage list */
1129 struct list_head free_frames;
1130 int frames_count;
1131
8318d78a 1132 enum ieee80211_band band;
2f301227 1133 int alloc_rxb_page;
5d08cd1d 1134
c79dd5b5 1135 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1136 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1137
8318d78a 1138 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1139
5d08cd1d 1140 /* spectrum measurement report caching */
2aa6ab86 1141 struct iwl_spectrum_notification measure_report;
5d08cd1d 1142 u8 measurement_status;
81963d68 1143
5d08cd1d
CH
1144 /* ucode beacon time */
1145 u32 ucode_beacon_time;
a13d276f 1146 int missed_beacon_threshold;
5d08cd1d 1147
a85d7cca
JB
1148 /* track IBSS manager (last beacon) status */
1149 u32 ibss_manager;
1150
3e4fb5fa
TAN
1151 /* storing the jiffies when the plcp error rate is received */
1152 unsigned long plcp_jiffies;
1153
a93e7973 1154 /* force reset */
8a472da4 1155 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1156
5a2a780c 1157 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1158 * Access via channel # using indirect index array */
bf85ea4f 1159 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1160 u8 channel_count; /* # of channels */
1161
5d08cd1d
CH
1162 /* thermal calibration */
1163 s32 temperature; /* degrees Kelvin */
1164 s32 last_temperature;
1165
7c616cba 1166 /* init calibration results */
6e21f2c1 1167 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1168
5d08cd1d 1169 /* Scan related variables */
5d08cd1d 1170 unsigned long scan_start;
5d08cd1d 1171 unsigned long scan_start_tsf;
811ecc99 1172 void *scan_cmd;
00700ee0 1173 enum ieee80211_band scan_band;
1ecf9fc1 1174 struct cfg80211_scan_request *scan_request;
f84b29ec 1175 struct ieee80211_vif *scan_vif;
afbdd69a 1176 bool is_internal_short_scan;
76eff18b
TW
1177 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1178 u8 mgmt_tx_ant;
5d08cd1d
CH
1179
1180 /* spinlock */
1181 spinlock_t lock; /* protect general shared data */
1182 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1183 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1184 struct mutex mutex;
d2dfe6df 1185 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1186
1187 /* basic pci-network driver stuff */
1188 struct pci_dev *pci_dev;
1189
1190 /* pci hardware address support */
1191 void __iomem *hw_base;
b661c819
TW
1192 u32 hw_rev;
1193 u32 hw_wa_rev;
1194 u8 rev_id;
5d08cd1d 1195
246ed355
JB
1196 /* microcode/device supports multiple contexts */
1197 u8 valid_contexts;
1198
13bb9483
JB
1199 /* command queue number */
1200 u8 cmd_queue;
1201
c6fa17ed
WYG
1202 /* EEPROM MAC addresses */
1203 struct mac_address addresses[2];
1204
5d08cd1d 1205 /* uCode images, save to reload in case of failure */
b08dfd04 1206 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1207 u32 ucode_ver; /* version of ucode, copy of
1208 iwl_ucode.ver */
5d08cd1d
CH
1209 struct fw_desc ucode_code; /* runtime inst */
1210 struct fw_desc ucode_data; /* runtime data original */
1211 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1212 struct fw_desc ucode_init; /* initialization inst */
1213 struct fw_desc ucode_init_data; /* initialization data */
1214 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1215 enum ucode_type ucode_type;
1216 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1217 char firmware_name[25];
5d08cd1d 1218
246ed355 1219 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1220
0924e519
WYG
1221 struct iwl_switch_rxon switch_rxon;
1222
5d08cd1d 1223 /* 1st responses from initialize and runtime uCode images.
5a2a780c 1224 * _agn's initialize alive response contains some calibration data. */
885ba202
TW
1225 struct iwl_init_alive_resp card_alive_init;
1226 struct iwl_alive_resp card_alive;
5d08cd1d 1227
ab53d8af
MA
1228 unsigned long last_blink_time;
1229 u8 last_blink_rate;
1230 u8 allow_blinking;
1231 u64 led_tpt;
e932a609 1232
5d08cd1d 1233 u16 active_rate;
5d08cd1d 1234
5d08cd1d 1235 u8 start_calib;
f0832f13
EG
1236 struct iwl_sensitivity_data sensitivity_data;
1237 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1238 bool enhance_sensitivity_table;
5d08cd1d 1239 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1240 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1241
fad95bf5 1242 struct iwl_ht_config current_ht_config;
5d08cd1d 1243
5d08cd1d 1244 /* Rate scaling data */
5d08cd1d
CH
1245 u8 retry_rate;
1246
1247 wait_queue_head_t wait_command_queue;
1248
1249 int activity_timer_active;
1250
1251 /* Rx and Tx DMA processing queues */
a55360e4 1252 struct iwl_rx_queue rxq;
88804e2b 1253 struct iwl_tx_queue *txq;
5d08cd1d 1254 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1255 struct iwl_dma_ptr kw; /* keep warm address */
1256 struct iwl_dma_ptr scd_bc_tbls;
1257
5d08cd1d
CH
1258 u32 scd_base_addr; /* scheduler sram base address */
1259
1260 unsigned long status;
5d08cd1d 1261
19758bef 1262 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1263 struct traffic_stats tx_stats;
1264 struct traffic_stats rx_stats;
19758bef 1265
a83b9141
WYG
1266 /* counts interrupts */
1267 struct isr_statistics isr_stats;
1268
5da4b55f 1269 struct iwl_power_mgr power_data;
3ad3b92a 1270 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1271
5d08cd1d 1272 /* context information */
59c02b41 1273 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
5d08cd1d 1274
9c5ac091
RC
1275 /* station table variables */
1276
1277 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1278 spinlock_t sta_lock;
1279 int num_stations;
6def9761 1280 struct iwl_station_entry stations[IWL_STATION_COUNT];
72e15d71 1281 struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; /* protected by mutex */
6974e363 1282 u8 key_mapping_key;
80fb47a1 1283 unsigned long ucode_key_table;
5d08cd1d 1284
e4e72fb4
JB
1285 /* queue refcounts */
1286#define IWL_MAX_HW_QUEUES 32
1287 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1288 /* for each AC */
1289 atomic_t queue_stop_count[4];
1290
5d08cd1d 1291 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1292 u8 is_open;
5d08cd1d
CH
1293
1294 u8 mac80211_registered;
5d08cd1d 1295
af6b8ee3 1296 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1297 u8 *eeprom;
0848e297 1298 int nvm_device_type;
073d3f5f 1299 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1300
05c914fe 1301 enum nl80211_iftype iw_mode;
5d08cd1d
CH
1302
1303 struct sk_buff *ibss_beacon;
1304
1305 /* Last Rx'd beacon timestamp */
3109ece1 1306 u64 timestamp;
32bfd35d 1307 struct ieee80211_vif *vif;
5d08cd1d 1308
ee525d13
JB
1309 union {
1310#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1311 struct {
1312 void *shared_virt;
1313 dma_addr_t shared_phys;
1314
1315 struct delayed_work thermal_periodic;
1316 struct delayed_work rfkill_poll;
1317
1318 struct iwl3945_notif_statistics statistics;
d73e4923 1319#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK
1320 struct iwl3945_notif_statistics accum_statistics;
1321 struct iwl3945_notif_statistics delta_statistics;
1322 struct iwl3945_notif_statistics max_delta;
1323#endif
ee525d13
JB
1324
1325 u32 sta_supp_rates;
e99f168c
JB
1326 int last_rx_rssi; /* From Rx packet statistics */
1327
1328 /* Rx'd packet timing information */
1329 u32 last_beacon_time;
1330 u64 last_tsf;
67d613ae
JB
1331
1332 /*
1333 * each calibration channel group in the
1334 * EEPROM has a derived clip setting for
1335 * each rate.
1336 */
1337 const struct iwl3945_clip_group clip_groups[5];
1338
ee525d13 1339 } _3945;
a4c8b2a6
JB
1340#endif
1341#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1342 struct {
1343 /* INT ICT Table */
1344 __le32 *ict_tbl;
1345 void *ict_tbl_vir;
1346 dma_addr_t ict_tbl_dma;
1347 dma_addr_t aligned_ict_tbl_dma;
1348 int ict_index;
1349 u32 inta;
1350 bool use_ict;
d5a0ffa3
WYG
1351 /*
1352 * reporting the number of tids has AGG on. 0 means
1353 * no AGGREGATION
1354 */
1355 u8 agg_tids_count;
05d57520
JB
1356
1357 struct iwl_rx_phy_res last_phy_res;
1358 bool last_phy_res_valid;
a15707d8
RC
1359
1360 struct completion firmware_loading_complete;
a2064b7a 1361
b2e640d4
JB
1362 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1363 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
f3aebeee 1364
6a822d06
WYG
1365 /*
1366 * chain noise reset and gain commands are the
1367 * two extra calibration commands follows the standard
1368 * phy calibration commands
1369 */
1370 u8 phy_calib_chain_noise_reset_cmd;
1371 u8 phy_calib_chain_noise_gain_cmd;
1372
f3aebeee 1373 struct iwl_notif_statistics statistics;
7980fba5 1374 struct iwl_bt_notif_statistics statistics_bt;
f3aebeee
WYG
1375#ifdef CONFIG_IWLWIFI_DEBUGFS
1376 struct iwl_notif_statistics accum_statistics;
1377 struct iwl_notif_statistics delta_statistics;
1378 struct iwl_notif_statistics max_delta;
7980fba5
WYG
1379 struct iwl_bt_notif_statistics accum_statistics_bt;
1380 struct iwl_bt_notif_statistics delta_statistics_bt;
1381 struct iwl_bt_notif_statistics max_delta_bt;
f3aebeee 1382#endif
a4c8b2a6 1383 } _agn;
ee525d13
JB
1384#endif
1385 };
1386
22bf59a0 1387 /* bt coex */
da5dbb97 1388 u8 bt_status;
59079949 1389 u8 bt_traffic_load, notif_bt_traffic_load;
f37837c9 1390 bool bt_ch_announce;
9e4afc21 1391 bool bt_sco_active;
bee008b7
WYG
1392 bool bt_full_concurrent;
1393 bool bt_ant_couple_ok;
fbba9410
WYG
1394 __le32 kill_ack_mask;
1395 __le32 kill_cts_mask;
1396 __le16 bt_valid;
22bf59a0
WYG
1397 u16 bt_on_thresh;
1398 u16 bt_duration;
1399 u16 dynamic_frag_thresh;
1400 u16 dynamic_agg_thresh;
bee008b7 1401 u8 bt_ci_compliance;
9e4afc21
JB
1402 struct work_struct bt_traffic_change_work;
1403
5425e490 1404 struct iwl_hw_params hw_params;
4ddbb7d0 1405
40cefda9 1406 u32 inta_mask;
5d08cd1d 1407
1ff50bda 1408 struct iwl_qos_info qos_data;
5d08cd1d
CH
1409
1410 struct workqueue_struct *workqueue;
1411
5d08cd1d 1412 struct work_struct restart;
5d08cd1d
CH
1413 struct work_struct scan_completed;
1414 struct work_struct rx_replenish;
5d08cd1d 1415 struct work_struct abort_scan;
5d08cd1d 1416 struct work_struct beacon_update;
a28027cd
WYG
1417 struct work_struct tt_work;
1418 struct work_struct ct_enter;
1419 struct work_struct ct_exit;
88be0264 1420 struct work_struct start_internal_scan;
65550636 1421 struct work_struct tx_flush;
bee008b7 1422 struct work_struct bt_full_concurrency;
fbba9410 1423 struct work_struct bt_runtime_config;
5d08cd1d
CH
1424
1425 struct tasklet_struct irq_tasklet;
1426
1427 struct delayed_work init_alive_start;
1428 struct delayed_work alive_start;
5d08cd1d 1429 struct delayed_work scan_check;
4a8a4322 1430
630fe9b6
TW
1431 /* TX Power */
1432 s8 tx_power_user_lmt;
dc1b0973 1433 s8 tx_power_device_lmt;
ae16fc3c 1434 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
5d08cd1d 1435
5d08cd1d 1436
d08853a3 1437#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1438 /* debugging info */
3d816c77
RC
1439 u32 debug_level; /* per device debugging will override global
1440 iwl_debug_level if set */
d73e4923 1441#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1442#ifdef CONFIG_IWLWIFI_DEBUGFS
1443 /* debugfs */
20594eb0
WYG
1444 u16 tx_traffic_idx;
1445 u16 rx_traffic_idx;
1446 u8 *tx_traffic;
1447 u8 *rx_traffic;
4c84a8f1
JB
1448 struct dentry *debugfs_dir;
1449 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1450 bool disable_ht40;
712b6cf5 1451#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1452
1453 struct work_struct txpower_work;
445c2dff
TW
1454 u32 disable_sens_cal;
1455 u32 disable_chain_noise_cal;
203566f3 1456 u32 disable_tx_power_cal;
16e727e8 1457 struct work_struct run_time_calib_work;
5d08cd1d 1458 struct timer_list statistics_periodic;
a9e1cb6a 1459 struct timer_list ucode_trace;
b74e31a9 1460 struct timer_list monitor_recover;
086ed117 1461 bool hw_ready;
a9e1cb6a
WYG
1462
1463 struct iwl_event_log event_log;
c79dd5b5 1464}; /*iwl_priv */
5d08cd1d 1465
36470749
RR
1466static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1467{
1468 set_bit(txq_id, &priv->txq_ctx_active_msk);
1469}
1470
1471static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1472{
1473 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1474}
1475
994d31f7 1476#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6 1477const char *iwl_get_tx_fail_reason(u32 status);
3d816c77
RC
1478/*
1479 * iwl_get_debug_level: Return active debug level for device
1480 *
1481 * Using sysfs it is possible to set per device debug level. This debug
1482 * level will be used if set, otherwise the global debug level which can be
1483 * set via module parameter is used.
1484 */
1485static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1486{
1487 if (priv->debug_level)
1488 return priv->debug_level;
1489 else
1490 return iwl_debug_level;
1491}
a332f8d6
TW
1492#else
1493static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
3d816c77
RC
1494
1495static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1496{
1497 return iwl_debug_level;
1498}
a332f8d6
TW
1499#endif
1500
1501
a332f8d6
TW
1502static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1503 int txq_id, int idx)
1504{
ff0d91c3 1505 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1506 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1507 txb[idx].skb->data;
a332f8d6
TW
1508 return NULL;
1509}
a332f8d6 1510
246ed355
JB
1511static inline struct iwl_rxon_context *
1512iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1513{
1514 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1515
1516 return vif_priv->ctx;
1517}
1518
1519#define for_each_context(priv, ctx) \
1520 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1521 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1522 if (priv->valid_contexts & BIT(ctx->ctxid))
1523
1524static inline int iwl_is_associated(struct iwl_priv *priv,
1525 enum iwl_rxon_context_id ctxid)
1526{
1527 return (priv->contexts[ctxid].active.filter_flags &
1528 RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1529}
1530
1531static inline int iwl_is_any_associated(struct iwl_priv *priv)
1532{
1533 return iwl_is_associated(priv, IWL_RXON_CTX_BSS);
1534}
a332f8d6 1535
246ed355 1536static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
5d08cd1d 1537{
246ed355 1538 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
5d08cd1d
CH
1539}
1540
bf85ea4f 1541static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1542{
1543 if (ch_info == NULL)
1544 return 0;
1545 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1546}
1547
bf85ea4f 1548static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1549{
1550 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1551}
1552
bf85ea4f 1553static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1554{
8318d78a 1555 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1556}
1557
bf85ea4f 1558static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1559{
8318d78a 1560 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1561}
1562
bf85ea4f 1563static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1564{
1565 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1566}
1567
bf85ea4f 1568static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1569{
1570 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1571}
1572
64a76b50
ZY
1573static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1574{
1575 __free_pages(page, priv->hw_params.rx_page_order);
1576 priv->alloc_rxb_page--;
1577}
1578
1579static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1580{
1581 free_pages(page, priv->hw_params.rx_page_order);
1582 priv->alloc_rxb_page--;
1583}
be1f3ab6 1584#endif /* __iwl_dev_h__ */