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df48c323 | 1 | /****************************************************************************** |
df48c323 TW |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
4e318262 | 5 | * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved. |
df48c323 TW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
df48c323 TW |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
8ccde88a | 31 | #include <linux/etherdevice.h> |
d43c36dc | 32 | #include <linux/sched.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
1d0a082d | 34 | #include <net/mac80211.h> |
df48c323 | 35 | |
6bc913bd | 36 | #include "iwl-eeprom.h" |
19335774 | 37 | #include "iwl-debug.h" |
df48c323 | 38 | #include "iwl-core.h" |
b661c819 | 39 | #include "iwl-io.h" |
5da4b55f | 40 | #include "iwl-power.h" |
48f20d35 | 41 | #include "iwl-shared.h" |
9d143e9a | 42 | #include "iwl-agn.h" |
bdfbf092 | 43 | #include "iwl-trans.h" |
df48c323 | 44 | |
57bd1bea | 45 | const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
57bd1bea | 46 | |
7e6a5886 JB |
47 | static bool iwl_is_channel_extension(struct iwl_priv *priv, |
48 | enum ieee80211_band band, | |
49 | u16 channel, u8 extension_chan_offset) | |
47c5196e TW |
50 | { |
51 | const struct iwl_channel_info *ch_info; | |
52 | ||
53 | ch_info = iwl_get_channel_info(priv, band, channel); | |
54 | if (!is_channel_valid(ch_info)) | |
7e6a5886 | 55 | return false; |
47c5196e | 56 | |
d9fe60de | 57 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) |
7aafef1c | 58 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 59 | IEEE80211_CHAN_NO_HT40PLUS); |
d9fe60de | 60 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
7aafef1c | 61 | return !(ch_info->ht40_extension_channel & |
689da1b3 | 62 | IEEE80211_CHAN_NO_HT40MINUS); |
47c5196e | 63 | |
7e6a5886 | 64 | return false; |
47c5196e TW |
65 | } |
66 | ||
7e6a5886 JB |
67 | bool iwl_is_ht40_tx_allowed(struct iwl_priv *priv, |
68 | struct iwl_rxon_context *ctx, | |
69 | struct ieee80211_sta_ht_cap *ht_cap) | |
47c5196e | 70 | { |
7e6a5886 JB |
71 | if (!ctx->ht.enabled || !ctx->ht.is_40mhz) |
72 | return false; | |
47c5196e | 73 | |
7e6a5886 JB |
74 | /* |
75 | * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
a2b0f02e WYG |
76 | * the bit will not set if it is pure 40MHz case |
77 | */ | |
7e6a5886 JB |
78 | if (ht_cap && !ht_cap->ht_supported) |
79 | return false; | |
80 | ||
d73e4923 | 81 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1e4247d4 | 82 | if (priv->disable_ht40) |
7e6a5886 | 83 | return false; |
1e4247d4 | 84 | #endif |
7e6a5886 | 85 | |
611d3eb7 | 86 | return iwl_is_channel_extension(priv, priv->band, |
246ed355 | 87 | le16_to_cpu(ctx->staging.channel), |
7e6a5886 | 88 | ctx->ht.extension_chan_offset); |
47c5196e | 89 | } |
47c5196e | 90 | |
2c2f3b33 TW |
91 | static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) |
92 | { | |
ea196fdb JB |
93 | u16 new_val; |
94 | u16 beacon_factor; | |
95 | ||
96 | /* | |
97 | * If mac80211 hasn't given us a beacon interval, program | |
98 | * the default into the device (not checking this here | |
99 | * would cause the adjustment below to return the maximum | |
100 | * value, which may break PAN.) | |
101 | */ | |
102 | if (!beacon_val) | |
103 | return DEFAULT_BEACON_INTERVAL; | |
104 | ||
105 | /* | |
106 | * If the beacon interval we obtained from the peer | |
107 | * is too large, we'll have to wake up more often | |
108 | * (and in IBSS case, we'll beacon too much) | |
109 | * | |
110 | * For example, if max_beacon_val is 4096, and the | |
111 | * requested beacon interval is 7000, we'll have to | |
112 | * use 3500 to be able to wake up on the beacons. | |
113 | * | |
114 | * This could badly influence beacon detection stats. | |
115 | */ | |
2c2f3b33 TW |
116 | |
117 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
118 | new_val = beacon_val / beacon_factor; | |
119 | ||
120 | if (!new_val) | |
121 | new_val = max_beacon_val; | |
122 | ||
123 | return new_val; | |
124 | } | |
125 | ||
47313e34 | 126 | int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
2c2f3b33 TW |
127 | { |
128 | u64 tsf; | |
129 | s32 interval_tm, rem; | |
2c2f3b33 TW |
130 | struct ieee80211_conf *conf = NULL; |
131 | u16 beacon_int; | |
47313e34 | 132 | struct ieee80211_vif *vif = ctx->vif; |
2c2f3b33 | 133 | |
8c222544 | 134 | conf = &priv->hw->conf; |
2c2f3b33 | 135 | |
b1eea297 | 136 | lockdep_assert_held(&priv->mutex); |
948f5a2f | 137 | |
246ed355 | 138 | memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
948f5a2f | 139 | |
246ed355 JB |
140 | ctx->timing.timestamp = cpu_to_le64(priv->timestamp); |
141 | ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); | |
2c2f3b33 | 142 | |
47313e34 | 143 | beacon_int = vif ? vif->bss_conf.beacon_int : 0; |
2c2f3b33 | 144 | |
47313e34 JB |
145 | /* |
146 | * TODO: For IBSS we need to get atim_window from mac80211, | |
147 | * for now just always use 0 | |
148 | */ | |
149 | ctx->timing.atim_window = 0; | |
2c2f3b33 | 150 | |
bde4530e | 151 | if (ctx->ctxid == IWL_RXON_CTX_PAN && |
f1f270b2 JB |
152 | (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION) && |
153 | iwl_is_associated(priv, IWL_RXON_CTX_BSS) && | |
154 | priv->contexts[IWL_RXON_CTX_BSS].vif && | |
155 | priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) { | |
bde4530e JB |
156 | ctx->timing.beacon_interval = |
157 | priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval; | |
158 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
f1f270b2 JB |
159 | } else if (ctx->ctxid == IWL_RXON_CTX_BSS && |
160 | iwl_is_associated(priv, IWL_RXON_CTX_PAN) && | |
161 | priv->contexts[IWL_RXON_CTX_PAN].vif && | |
162 | priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int && | |
163 | (!iwl_is_associated_ctx(ctx) || !ctx->vif || | |
164 | !ctx->vif->bss_conf.beacon_int)) { | |
165 | ctx->timing.beacon_interval = | |
166 | priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval; | |
167 | beacon_int = le16_to_cpu(ctx->timing.beacon_interval); | |
bde4530e JB |
168 | } else { |
169 | beacon_int = iwl_adjust_beacon_interval(beacon_int, | |
ab9e212e | 170 | IWL_MAX_UCODE_BEACON_INTERVAL * TIME_UNIT); |
bde4530e JB |
171 | ctx->timing.beacon_interval = cpu_to_le16(beacon_int); |
172 | } | |
2c2f3b33 | 173 | |
bbb05cb5 JB |
174 | ctx->beacon_int = beacon_int; |
175 | ||
2c2f3b33 | 176 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ |
f8525e55 | 177 | interval_tm = beacon_int * TIME_UNIT; |
2c2f3b33 | 178 | rem = do_div(tsf, interval_tm); |
246ed355 | 179 | ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); |
2c2f3b33 | 180 | |
47313e34 | 181 | ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1; |
2491fa42 | 182 | |
2c2f3b33 TW |
183 | IWL_DEBUG_ASSOC(priv, |
184 | "beacon interval %d beacon timer %d beacon tim %d\n", | |
246ed355 JB |
185 | le16_to_cpu(ctx->timing.beacon_interval), |
186 | le32_to_cpu(ctx->timing.beacon_init_val), | |
187 | le16_to_cpu(ctx->timing.atim_window)); | |
948f5a2f | 188 | |
e10a0533 | 189 | return iwl_dvm_send_cmd_pdu(priv, ctx->rxon_timing_cmd, |
e419d62d | 190 | CMD_SYNC, sizeof(ctx->timing), &ctx->timing); |
2c2f3b33 | 191 | } |
2c2f3b33 | 192 | |
246ed355 JB |
193 | void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx, |
194 | int hw_decrypt) | |
8ccde88a | 195 | { |
246ed355 | 196 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a SO |
197 | |
198 | if (hw_decrypt) | |
199 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
200 | else | |
201 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
202 | ||
203 | } | |
8ccde88a | 204 | |
dacefedb | 205 | /* validate RXON structure is valid */ |
246ed355 | 206 | int iwl_check_rxon_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx) |
8ccde88a | 207 | { |
246ed355 | 208 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
c914ac26 | 209 | u32 errors = 0; |
8ccde88a SO |
210 | |
211 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
dacefedb JB |
212 | if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) { |
213 | IWL_WARN(priv, "check 2.4G: wrong narrow\n"); | |
c914ac26 | 214 | errors |= BIT(0); |
dacefedb JB |
215 | } |
216 | if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) { | |
217 | IWL_WARN(priv, "check 2.4G: wrong radar\n"); | |
c914ac26 | 218 | errors |= BIT(1); |
dacefedb | 219 | } |
8ccde88a | 220 | } else { |
dacefedb JB |
221 | if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) { |
222 | IWL_WARN(priv, "check 5.2G: not short slot!\n"); | |
c914ac26 | 223 | errors |= BIT(2); |
dacefedb JB |
224 | } |
225 | if (rxon->flags & RXON_FLG_CCK_MSK) { | |
226 | IWL_WARN(priv, "check 5.2G: CCK!\n"); | |
c914ac26 | 227 | errors |= BIT(3); |
dacefedb JB |
228 | } |
229 | } | |
230 | if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) { | |
231 | IWL_WARN(priv, "mac/bssid mcast!\n"); | |
c914ac26 | 232 | errors |= BIT(4); |
8ccde88a | 233 | } |
8ccde88a SO |
234 | |
235 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
dacefedb JB |
236 | if ((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0 && |
237 | (rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0) { | |
238 | IWL_WARN(priv, "neither 1 nor 6 are basic\n"); | |
c914ac26 | 239 | errors |= BIT(5); |
dacefedb | 240 | } |
8ccde88a | 241 | |
dacefedb JB |
242 | if (le16_to_cpu(rxon->assoc_id) > 2007) { |
243 | IWL_WARN(priv, "aid > 2007\n"); | |
c914ac26 | 244 | errors |= BIT(6); |
dacefedb | 245 | } |
8ccde88a | 246 | |
dacefedb JB |
247 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) |
248 | == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) { | |
249 | IWL_WARN(priv, "CCK and short slot\n"); | |
c914ac26 | 250 | errors |= BIT(7); |
dacefedb | 251 | } |
8ccde88a | 252 | |
dacefedb JB |
253 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) |
254 | == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) { | |
255 | IWL_WARN(priv, "CCK and auto detect"); | |
c914ac26 | 256 | errors |= BIT(8); |
dacefedb | 257 | } |
8ccde88a | 258 | |
dacefedb JB |
259 | if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK | |
260 | RXON_FLG_TGG_PROTECT_MSK)) == | |
261 | RXON_FLG_TGG_PROTECT_MSK) { | |
262 | IWL_WARN(priv, "TGg but no auto-detect\n"); | |
c914ac26 | 263 | errors |= BIT(9); |
dacefedb | 264 | } |
8ccde88a | 265 | |
c914ac26 JB |
266 | if (rxon->channel == 0) { |
267 | IWL_WARN(priv, "zero channel is invalid\n"); | |
268 | errors |= BIT(10); | |
8ccde88a | 269 | } |
c914ac26 JB |
270 | |
271 | WARN(errors, "Invalid RXON (%#x), channel %d", | |
272 | errors, le16_to_cpu(rxon->channel)); | |
273 | ||
274 | return errors ? -EINVAL : 0; | |
8ccde88a | 275 | } |
8ccde88a SO |
276 | |
277 | /** | |
278 | * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed | |
279 | * @priv: staging_rxon is compared to active_rxon | |
280 | * | |
281 | * If the RXON structure is changing enough to require a new tune, | |
282 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
283 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
284 | */ | |
246ed355 JB |
285 | int iwl_full_rxon_required(struct iwl_priv *priv, |
286 | struct iwl_rxon_context *ctx) | |
8ccde88a | 287 | { |
246ed355 JB |
288 | const struct iwl_rxon_cmd *staging = &ctx->staging; |
289 | const struct iwl_rxon_cmd *active = &ctx->active; | |
290 | ||
291 | #define CHK(cond) \ | |
292 | if ((cond)) { \ | |
293 | IWL_DEBUG_INFO(priv, "need full RXON - " #cond "\n"); \ | |
294 | return 1; \ | |
295 | } | |
296 | ||
297 | #define CHK_NEQ(c1, c2) \ | |
298 | if ((c1) != (c2)) { \ | |
299 | IWL_DEBUG_INFO(priv, "need full RXON - " \ | |
300 | #c1 " != " #c2 " - %d != %d\n", \ | |
301 | (c1), (c2)); \ | |
302 | return 1; \ | |
303 | } | |
8ccde88a SO |
304 | |
305 | /* These items are only settable from the full RXON command */ | |
246ed355 JB |
306 | CHK(!iwl_is_associated_ctx(ctx)); |
307 | CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr)); | |
308 | CHK(compare_ether_addr(staging->node_addr, active->node_addr)); | |
309 | CHK(compare_ether_addr(staging->wlap_bssid_addr, | |
310 | active->wlap_bssid_addr)); | |
311 | CHK_NEQ(staging->dev_type, active->dev_type); | |
312 | CHK_NEQ(staging->channel, active->channel); | |
313 | CHK_NEQ(staging->air_propagation, active->air_propagation); | |
314 | CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates, | |
315 | active->ofdm_ht_single_stream_basic_rates); | |
316 | CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates, | |
317 | active->ofdm_ht_dual_stream_basic_rates); | |
318 | CHK_NEQ(staging->ofdm_ht_triple_stream_basic_rates, | |
319 | active->ofdm_ht_triple_stream_basic_rates); | |
320 | CHK_NEQ(staging->assoc_id, active->assoc_id); | |
8ccde88a SO |
321 | |
322 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
323 | * be updated with the RXON_ASSOC command -- however only some | |
324 | * flag transitions are allowed using RXON_ASSOC */ | |
325 | ||
326 | /* Check if we are not switching bands */ | |
246ed355 JB |
327 | CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK, |
328 | active->flags & RXON_FLG_BAND_24G_MSK); | |
8ccde88a SO |
329 | |
330 | /* Check if we are switching association toggle */ | |
246ed355 JB |
331 | CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK, |
332 | active->filter_flags & RXON_FILTER_ASSOC_MSK); | |
333 | ||
334 | #undef CHK | |
335 | #undef CHK_NEQ | |
8ccde88a SO |
336 | |
337 | return 0; | |
338 | } | |
8ccde88a | 339 | |
246ed355 JB |
340 | static void _iwl_set_rxon_ht(struct iwl_priv *priv, |
341 | struct iwl_ht_config *ht_conf, | |
342 | struct iwl_rxon_context *ctx) | |
47c5196e | 343 | { |
246ed355 | 344 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
47c5196e | 345 | |
7e6a5886 | 346 | if (!ctx->ht.enabled) { |
a2b0f02e | 347 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | |
42eb7c64 | 348 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | |
7aafef1c | 349 | RXON_FLG_HT40_PROT_MSK | |
42eb7c64 | 350 | RXON_FLG_HT_PROT_MSK); |
47c5196e | 351 | return; |
42eb7c64 | 352 | } |
47c5196e | 353 | |
7e6a5886 | 354 | /* FIXME: if the definition of ht.protection changed, the "translation" |
a2b0f02e WYG |
355 | * will be needed for rxon->flags |
356 | */ | |
7e6a5886 | 357 | rxon->flags |= cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS); |
a2b0f02e WYG |
358 | |
359 | /* Set up channel bandwidth: | |
7aafef1c | 360 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ |
a2b0f02e WYG |
361 | /* clear the HT channel mode before set the mode */ |
362 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK | | |
363 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
7e6a5886 | 364 | if (iwl_is_ht40_tx_allowed(priv, ctx, NULL)) { |
7aafef1c | 365 | /* pure ht40 */ |
7e6a5886 | 366 | if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
a2b0f02e | 367 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
508b08e7 | 368 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 369 | switch (ctx->ht.extension_chan_offset) { |
508b08e7 WYG |
370 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
371 | rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
372 | break; | |
373 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
374 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
375 | break; | |
376 | } | |
377 | } else { | |
a2b0f02e | 378 | /* Note: control channel is opposite of extension channel */ |
7e6a5886 | 379 | switch (ctx->ht.extension_chan_offset) { |
a2b0f02e WYG |
380 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: |
381 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
382 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
383 | break; | |
384 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
385 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
386 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; | |
387 | break; | |
388 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
389 | default: | |
390 | /* channel location only valid if in Mixed mode */ | |
391 | IWL_ERR(priv, "invalid extension channel offset\n"); | |
392 | break; | |
393 | } | |
394 | } | |
395 | } else { | |
396 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
47c5196e TW |
397 | } |
398 | ||
e3f10cea | 399 | iwlagn_set_rxon_chain(priv, ctx); |
47c5196e | 400 | |
02bb1bea | 401 | IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X " |
ae5eb026 | 402 | "extension channel offset 0x%x\n", |
7e6a5886 JB |
403 | le32_to_cpu(rxon->flags), ctx->ht.protection, |
404 | ctx->ht.extension_chan_offset); | |
47c5196e | 405 | } |
246ed355 JB |
406 | |
407 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf) | |
408 | { | |
409 | struct iwl_rxon_context *ctx; | |
410 | ||
411 | for_each_context(priv, ctx) | |
412 | _iwl_set_rxon_ht(priv, ht_conf, ctx); | |
413 | } | |
47c5196e | 414 | |
246ed355 | 415 | /* Return valid, unused, channel for a passive scan to reset the RF */ |
14023641 | 416 | u8 iwl_get_single_channel_number(struct iwl_priv *priv, |
246ed355 | 417 | enum ieee80211_band band) |
14023641 AK |
418 | { |
419 | const struct iwl_channel_info *ch_info; | |
420 | int i; | |
421 | u8 channel = 0; | |
246ed355 JB |
422 | u8 min, max; |
423 | struct iwl_rxon_context *ctx; | |
14023641 | 424 | |
14023641 | 425 | if (band == IEEE80211_BAND_5GHZ) { |
246ed355 JB |
426 | min = 14; |
427 | max = priv->channel_count; | |
14023641 | 428 | } else { |
246ed355 JB |
429 | min = 0; |
430 | max = 14; | |
431 | } | |
432 | ||
433 | for (i = min; i < max; i++) { | |
434 | bool busy = false; | |
435 | ||
436 | for_each_context(priv, ctx) { | |
437 | busy = priv->channel_info[i].channel == | |
438 | le16_to_cpu(ctx->staging.channel); | |
439 | if (busy) | |
440 | break; | |
14023641 | 441 | } |
246ed355 JB |
442 | |
443 | if (busy) | |
444 | continue; | |
445 | ||
446 | channel = priv->channel_info[i].channel; | |
447 | ch_info = iwl_get_channel_info(priv, band, channel); | |
448 | if (is_channel_valid(ch_info)) | |
449 | break; | |
14023641 AK |
450 | } |
451 | ||
452 | return channel; | |
453 | } | |
14023641 | 454 | |
bf85ea4f | 455 | /** |
3edb5fd6 SZ |
456 | * iwl_set_rxon_channel - Set the band and channel values in staging RXON |
457 | * @ch: requested channel as a pointer to struct ieee80211_channel | |
bf85ea4f | 458 | |
bf85ea4f | 459 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields |
3edb5fd6 | 460 | * in the staging RXON flag structure based on the ch->band |
bf85ea4f | 461 | */ |
dd63b84e | 462 | void iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch, |
246ed355 | 463 | struct iwl_rxon_context *ctx) |
bf85ea4f | 464 | { |
17e72782 | 465 | enum ieee80211_band band = ch->band; |
81e95430 | 466 | u16 channel = ch->hw_value; |
17e72782 | 467 | |
246ed355 | 468 | if ((le16_to_cpu(ctx->staging.channel) == channel) && |
bf85ea4f | 469 | (priv->band == band)) |
dd63b84e | 470 | return; |
bf85ea4f | 471 | |
246ed355 | 472 | ctx->staging.channel = cpu_to_le16(channel); |
bf85ea4f | 473 | if (band == IEEE80211_BAND_5GHZ) |
246ed355 | 474 | ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK; |
bf85ea4f | 475 | else |
246ed355 | 476 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
bf85ea4f AK |
477 | |
478 | priv->band = band; | |
479 | ||
e1623446 | 480 | IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band); |
bf85ea4f | 481 | |
bf85ea4f | 482 | } |
bf85ea4f | 483 | |
79d07325 | 484 | void iwl_set_flags_for_band(struct iwl_priv *priv, |
246ed355 | 485 | struct iwl_rxon_context *ctx, |
79d07325 WYG |
486 | enum ieee80211_band band, |
487 | struct ieee80211_vif *vif) | |
8ccde88a SO |
488 | { |
489 | if (band == IEEE80211_BAND_5GHZ) { | |
246ed355 | 490 | ctx->staging.flags &= |
8ccde88a SO |
491 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
492 | | RXON_FLG_CCK_MSK); | |
246ed355 | 493 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a SO |
494 | } else { |
495 | /* Copied from iwl_post_associate() */ | |
c213d745 | 496 | if (vif && vif->bss_conf.use_short_slot) |
246ed355 | 497 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 498 | else |
246ed355 | 499 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
8ccde88a | 500 | |
246ed355 JB |
501 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; |
502 | ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
503 | ctx->staging.flags &= ~RXON_FLG_CCK_MSK; | |
8ccde88a SO |
504 | } |
505 | } | |
8ccde88a SO |
506 | |
507 | /* | |
508 | * initialize rxon structure with default values from eeprom | |
509 | */ | |
1dda6d28 | 510 | void iwl_connection_init_rx_config(struct iwl_priv *priv, |
d0fe478c | 511 | struct iwl_rxon_context *ctx) |
8ccde88a SO |
512 | { |
513 | const struct iwl_channel_info *ch_info; | |
514 | ||
246ed355 | 515 | memset(&ctx->staging, 0, sizeof(ctx->staging)); |
8ccde88a | 516 | |
d0fe478c JB |
517 | if (!ctx->vif) { |
518 | ctx->staging.dev_type = ctx->unused_devtype; | |
519 | } else switch (ctx->vif->type) { | |
8ccde88a | 520 | case NL80211_IFTYPE_AP: |
d0fe478c | 521 | ctx->staging.dev_type = ctx->ap_devtype; |
8ccde88a SO |
522 | break; |
523 | ||
524 | case NL80211_IFTYPE_STATION: | |
d0fe478c | 525 | ctx->staging.dev_type = ctx->station_devtype; |
246ed355 | 526 | ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; |
8ccde88a SO |
527 | break; |
528 | ||
529 | case NL80211_IFTYPE_ADHOC: | |
d0fe478c | 530 | ctx->staging.dev_type = ctx->ibss_devtype; |
246ed355 JB |
531 | ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK; |
532 | ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK | | |
8ccde88a SO |
533 | RXON_FILTER_ACCEPT_GRP_MSK; |
534 | break; | |
535 | ||
8ccde88a | 536 | default: |
d0fe478c JB |
537 | IWL_ERR(priv, "Unsupported interface type %d\n", |
538 | ctx->vif->type); | |
8ccde88a SO |
539 | break; |
540 | } | |
541 | ||
542 | #if 0 | |
543 | /* TODO: Figure out when short_preamble would be set and cache from | |
544 | * that */ | |
545 | if (!hw_to_local(priv->hw)->short_preamble) | |
246ed355 | 546 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a | 547 | else |
246ed355 | 548 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
8ccde88a SO |
549 | #endif |
550 | ||
551 | ch_info = iwl_get_channel_info(priv, priv->band, | |
246ed355 | 552 | le16_to_cpu(ctx->active.channel)); |
8ccde88a SO |
553 | |
554 | if (!ch_info) | |
555 | ch_info = &priv->channel_info[0]; | |
556 | ||
246ed355 | 557 | ctx->staging.channel = cpu_to_le16(ch_info->channel); |
8ccde88a SO |
558 | priv->band = ch_info->band; |
559 | ||
d0fe478c | 560 | iwl_set_flags_for_band(priv, ctx, priv->band, ctx->vif); |
8ccde88a | 561 | |
246ed355 | 562 | ctx->staging.ofdm_basic_rates = |
8ccde88a | 563 | (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
246ed355 | 564 | ctx->staging.cck_basic_rates = |
8ccde88a SO |
565 | (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; |
566 | ||
a2b0f02e | 567 | /* clear both MIX and PURE40 mode flag */ |
246ed355 | 568 | ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED | |
a2b0f02e | 569 | RXON_FLG_CHANNEL_MODE_PURE_40); |
d0fe478c JB |
570 | if (ctx->vif) |
571 | memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN); | |
7684c408 | 572 | |
246ed355 JB |
573 | ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff; |
574 | ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff; | |
575 | ctx->staging.ofdm_ht_triple_stream_basic_rates = 0xff; | |
8ccde88a | 576 | } |
8ccde88a | 577 | |
79d07325 | 578 | void iwl_set_rate(struct iwl_priv *priv) |
8ccde88a SO |
579 | { |
580 | const struct ieee80211_supported_band *hw = NULL; | |
581 | struct ieee80211_rate *rate; | |
246ed355 | 582 | struct iwl_rxon_context *ctx; |
8ccde88a SO |
583 | int i; |
584 | ||
585 | hw = iwl_get_hw_mode(priv, priv->band); | |
586 | if (!hw) { | |
587 | IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n"); | |
588 | return; | |
589 | } | |
590 | ||
591 | priv->active_rate = 0; | |
8ccde88a SO |
592 | |
593 | for (i = 0; i < hw->n_bitrates; i++) { | |
594 | rate = &(hw->bitrates[i]); | |
5027309b | 595 | if (rate->hw_value < IWL_RATE_COUNT_LEGACY) |
8ccde88a SO |
596 | priv->active_rate |= (1 << rate->hw_value); |
597 | } | |
598 | ||
4a02886b | 599 | IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate); |
8ccde88a | 600 | |
246ed355 JB |
601 | for_each_context(priv, ctx) { |
602 | ctx->staging.cck_basic_rates = | |
603 | (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF; | |
4a02886b | 604 | |
246ed355 JB |
605 | ctx->staging.ofdm_basic_rates = |
606 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
607 | } | |
8ccde88a | 608 | } |
79d07325 WYG |
609 | |
610 | void iwl_chswitch_done(struct iwl_priv *priv, bool is_success) | |
611 | { | |
8bd413e6 JB |
612 | /* |
613 | * MULTI-FIXME | |
ade4c649 | 614 | * See iwlagn_mac_channel_switch. |
8bd413e6 JB |
615 | */ |
616 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
617 | ||
83626404 | 618 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
79d07325 WYG |
619 | return; |
620 | ||
83626404 | 621 | if (test_and_clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status)) |
8bd413e6 | 622 | ieee80211_chswitch_done(ctx->vif, is_success); |
79d07325 | 623 | } |
8ccde88a | 624 | |
8ccde88a | 625 | #ifdef CONFIG_IWLWIFI_DEBUG |
14991a9d EG |
626 | void iwl_print_rx_config_cmd(struct iwl_priv *priv, |
627 | enum iwl_rxon_context_id ctxid) | |
8ccde88a | 628 | { |
522376d2 | 629 | struct iwl_rxon_context *ctx = &priv->contexts[ctxid]; |
246ed355 | 630 | struct iwl_rxon_cmd *rxon = &ctx->staging; |
8ccde88a | 631 | |
e1623446 | 632 | IWL_DEBUG_RADIO(priv, "RX CONFIG:\n"); |
3d816c77 | 633 | iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e1623446 TW |
634 | IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
635 | IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); | |
636 | IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n", | |
8ccde88a | 637 | le32_to_cpu(rxon->filter_flags)); |
e1623446 TW |
638 | IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type); |
639 | IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n", | |
8ccde88a | 640 | rxon->ofdm_basic_rates); |
e1623446 TW |
641 | IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); |
642 | IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr); | |
643 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
644 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | |
8ccde88a | 645 | } |
6686d17e | 646 | #endif |
e649437f | 647 | |
b7e21bf0 | 648 | void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand) |
8ccde88a | 649 | { |
491bc292 WYG |
650 | unsigned int reload_msec; |
651 | unsigned long reload_jiffies; | |
652 | ||
3e6895c5 | 653 | #ifdef CONFIG_IWLWIFI_DEBUG |
a8bceb39 | 654 | if (iwl_have_debug_level(IWL_DL_FW_ERRORS)) |
3e6895c5 EG |
655 | iwl_print_rx_config_cmd(priv, IWL_RXON_CTX_BSS); |
656 | #endif | |
657 | ||
8f7ffbe2 DS |
658 | /* uCode is no longer loaded. */ |
659 | priv->ucode_loaded = false; | |
660 | ||
8ccde88a | 661 | /* Set the FW error flag -- cleared on iwl_down */ |
63013ae3 | 662 | set_bit(STATUS_FW_ERROR, &priv->shrd->status); |
8ccde88a SO |
663 | |
664 | /* Cancel currently queued command. */ | |
63013ae3 | 665 | clear_bit(STATUS_HCMD_ACTIVE, &priv->shrd->status); |
8ccde88a | 666 | |
4bd14dd5 | 667 | iwl_abort_notification_waits(&priv->notif_wait); |
e74fe233 | 668 | |
e649437f JB |
669 | /* Keep the restart process from trying to send host |
670 | * commands by clearing the ready bit */ | |
83626404 | 671 | clear_bit(STATUS_READY, &priv->status); |
e649437f | 672 | |
69a10b29 | 673 | wake_up(&trans(priv)->wait_command_queue); |
e649437f JB |
674 | |
675 | if (!ondemand) { | |
676 | /* | |
677 | * If firmware keep reloading, then it indicate something | |
678 | * serious wrong and firmware having problem to recover | |
679 | * from it. Instead of keep trying which will fill the syslog | |
680 | * and hang the system, let's just stop it | |
681 | */ | |
682 | reload_jiffies = jiffies; | |
683 | reload_msec = jiffies_to_msecs((long) reload_jiffies - | |
684 | (long) priv->reload_jiffies); | |
685 | priv->reload_jiffies = reload_jiffies; | |
686 | if (reload_msec <= IWL_MIN_RELOAD_DURATION) { | |
687 | priv->reload_count++; | |
688 | if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) { | |
689 | IWL_ERR(priv, "BUG_ON, Stop restarting\n"); | |
690 | return; | |
691 | } | |
692 | } else | |
693 | priv->reload_count = 0; | |
694 | } | |
695 | ||
83626404 | 696 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) { |
9d143e9a | 697 | if (iwlagn_mod_params.restart_fw) { |
9ca06f0a | 698 | IWL_DEBUG_FW_ERRORS(priv, |
e649437f | 699 | "Restarting adapter due to uCode error.\n"); |
1ee158d8 | 700 | queue_work(priv->workqueue, &priv->restart); |
e649437f | 701 | } else |
9ca06f0a | 702 | IWL_DEBUG_FW_ERRORS(priv, |
e649437f JB |
703 | "Detected FW error, but not restarting\n"); |
704 | } | |
705 | } | |
706 | ||
630fe9b6 TW |
707 | int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force) |
708 | { | |
a25a66ac SG |
709 | int ret; |
710 | s8 prev_tx_power; | |
f844a709 SG |
711 | bool defer; |
712 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
a25a66ac | 713 | |
b1eea297 | 714 | lockdep_assert_held(&priv->mutex); |
a25a66ac SG |
715 | |
716 | if (priv->tx_power_user_lmt == tx_power && !force) | |
717 | return 0; | |
718 | ||
b744cb79 WYG |
719 | if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) { |
720 | IWL_WARN(priv, | |
721 | "Requested user TXPOWER %d below lower limit %d.\n", | |
daf518de | 722 | tx_power, |
b744cb79 | 723 | IWLAGN_TX_POWER_TARGET_POWER_MIN); |
630fe9b6 TW |
724 | return -EINVAL; |
725 | } | |
726 | ||
dc1b0973 | 727 | if (tx_power > priv->tx_power_device_lmt) { |
08f2d58d WYG |
728 | IWL_WARN(priv, |
729 | "Requested user TXPOWER %d above upper limit %d.\n", | |
dc1b0973 | 730 | tx_power, priv->tx_power_device_lmt); |
630fe9b6 TW |
731 | return -EINVAL; |
732 | } | |
733 | ||
83626404 | 734 | if (!iwl_is_ready_rf(priv)) |
a25a66ac | 735 | return -EIO; |
630fe9b6 | 736 | |
f844a709 SG |
737 | /* scan complete and commit_rxon use tx_power_next value, |
738 | * it always need to be updated for newest request */ | |
a25a66ac | 739 | priv->tx_power_next = tx_power; |
f844a709 SG |
740 | |
741 | /* do not set tx power when scanning or channel changing */ | |
83626404 | 742 | defer = test_bit(STATUS_SCANNING, &priv->status) || |
f844a709 SG |
743 | memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)); |
744 | if (defer && !force) { | |
745 | IWL_DEBUG_INFO(priv, "Deferring tx power set\n"); | |
a25a66ac | 746 | return 0; |
5eadd94b | 747 | } |
630fe9b6 | 748 | |
a25a66ac SG |
749 | prev_tx_power = priv->tx_power_user_lmt; |
750 | priv->tx_power_user_lmt = tx_power; | |
751 | ||
5beaaf37 | 752 | ret = iwlagn_send_tx_power(priv); |
a25a66ac SG |
753 | |
754 | /* if fail to set tx_power, restore the orig. tx power */ | |
755 | if (ret) { | |
756 | priv->tx_power_user_lmt = prev_tx_power; | |
757 | priv->tx_power_next = prev_tx_power; | |
758 | } | |
630fe9b6 TW |
759 | return ret; |
760 | } | |
630fe9b6 | 761 | |
65b52bde | 762 | void iwl_send_bt_config(struct iwl_priv *priv) |
17f841cd SO |
763 | { |
764 | struct iwl_bt_cmd bt_cmd = { | |
456d0f76 WYG |
765 | .lead_time = BT_LEAD_TIME_DEF, |
766 | .max_kill = BT_MAX_KILL_DEF, | |
17f841cd SO |
767 | .kill_ack_mask = 0, |
768 | .kill_cts_mask = 0, | |
769 | }; | |
770 | ||
b60eec9b | 771 | if (!iwlagn_mod_params.bt_coex_active) |
06702a73 WYG |
772 | bt_cmd.flags = BT_COEX_DISABLE; |
773 | else | |
774 | bt_cmd.flags = BT_COEX_ENABLE; | |
775 | ||
f21dd005 | 776 | priv->bt_enable_flag = bt_cmd.flags; |
06702a73 WYG |
777 | IWL_DEBUG_INFO(priv, "BT coex %s\n", |
778 | (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); | |
779 | ||
e10a0533 | 780 | if (iwl_dvm_send_cmd_pdu(priv, REPLY_BT_CONFIG, |
e419d62d | 781 | CMD_SYNC, sizeof(struct iwl_bt_cmd), &bt_cmd)) |
65b52bde | 782 | IWL_ERR(priv, "failed to send BT Coex Config\n"); |
17f841cd | 783 | } |
17f841cd | 784 | |
ef8d5529 | 785 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear) |
49ea8596 | 786 | { |
ef8d5529 WYG |
787 | struct iwl_statistics_cmd statistics_cmd = { |
788 | .configuration_flags = | |
789 | clear ? IWL_STATS_CONF_CLEAR_STATS : 0, | |
49ea8596 | 790 | }; |
ef8d5529 WYG |
791 | |
792 | if (flags & CMD_ASYNC) | |
e10a0533 | 793 | return iwl_dvm_send_cmd_pdu(priv, REPLY_STATISTICS_CMD, |
e419d62d | 794 | CMD_ASYNC, |
ef8d5529 | 795 | sizeof(struct iwl_statistics_cmd), |
e419d62d | 796 | &statistics_cmd); |
ef8d5529 | 797 | else |
e10a0533 | 798 | return iwl_dvm_send_cmd_pdu(priv, REPLY_STATISTICS_CMD, |
e419d62d | 799 | CMD_SYNC, |
ef8d5529 WYG |
800 | sizeof(struct iwl_statistics_cmd), |
801 | &statistics_cmd); | |
49ea8596 | 802 | } |
7e8c519e | 803 | |
488829f1 | 804 | |
727882d6 | 805 | |
d8052319 | 806 | |
20594eb0 WYG |
807 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
808 | ||
809 | #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) | |
810 | ||
811 | void iwl_reset_traffic_log(struct iwl_priv *priv) | |
812 | { | |
813 | priv->tx_traffic_idx = 0; | |
814 | priv->rx_traffic_idx = 0; | |
815 | if (priv->tx_traffic) | |
816 | memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
817 | if (priv->rx_traffic) | |
818 | memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE); | |
819 | } | |
820 | ||
821 | int iwl_alloc_traffic_mem(struct iwl_priv *priv) | |
822 | { | |
823 | u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE; | |
824 | ||
a8bceb39 | 825 | if (iwl_have_debug_level(IWL_DL_TX)) { |
20594eb0 WYG |
826 | if (!priv->tx_traffic) { |
827 | priv->tx_traffic = | |
828 | kzalloc(traffic_size, GFP_KERNEL); | |
829 | if (!priv->tx_traffic) | |
830 | return -ENOMEM; | |
831 | } | |
832 | } | |
a8bceb39 | 833 | if (iwl_have_debug_level(IWL_DL_RX)) { |
20594eb0 WYG |
834 | if (!priv->rx_traffic) { |
835 | priv->rx_traffic = | |
836 | kzalloc(traffic_size, GFP_KERNEL); | |
837 | if (!priv->rx_traffic) | |
838 | return -ENOMEM; | |
839 | } | |
840 | } | |
841 | iwl_reset_traffic_log(priv); | |
842 | return 0; | |
843 | } | |
20594eb0 WYG |
844 | |
845 | void iwl_free_traffic_mem(struct iwl_priv *priv) | |
846 | { | |
847 | kfree(priv->tx_traffic); | |
848 | priv->tx_traffic = NULL; | |
849 | ||
850 | kfree(priv->rx_traffic); | |
851 | priv->rx_traffic = NULL; | |
852 | } | |
20594eb0 WYG |
853 | |
854 | void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv, | |
855 | u16 length, struct ieee80211_hdr *header) | |
856 | { | |
857 | __le16 fc; | |
858 | u16 len; | |
859 | ||
a8bceb39 | 860 | if (likely(!iwl_have_debug_level(IWL_DL_TX))) |
20594eb0 WYG |
861 | return; |
862 | ||
863 | if (!priv->tx_traffic) | |
864 | return; | |
865 | ||
866 | fc = header->frame_control; | |
867 | if (ieee80211_is_data(fc)) { | |
868 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
869 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
870 | memcpy((priv->tx_traffic + | |
871 | (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
872 | header, len); | |
873 | priv->tx_traffic_idx = | |
874 | (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
875 | } | |
876 | } | |
20594eb0 WYG |
877 | |
878 | void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv, | |
879 | u16 length, struct ieee80211_hdr *header) | |
880 | { | |
881 | __le16 fc; | |
882 | u16 len; | |
883 | ||
a8bceb39 | 884 | if (likely(!iwl_have_debug_level(IWL_DL_RX))) |
20594eb0 WYG |
885 | return; |
886 | ||
887 | if (!priv->rx_traffic) | |
888 | return; | |
889 | ||
890 | fc = header->frame_control; | |
891 | if (ieee80211_is_data(fc)) { | |
892 | len = (length > IWL_TRAFFIC_ENTRY_SIZE) | |
893 | ? IWL_TRAFFIC_ENTRY_SIZE : length; | |
894 | memcpy((priv->rx_traffic + | |
895 | (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)), | |
896 | header, len); | |
897 | priv->rx_traffic_idx = | |
898 | (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES; | |
899 | } | |
900 | } | |
22fdf3c9 WYG |
901 | |
902 | const char *get_mgmt_string(int cmd) | |
903 | { | |
904 | switch (cmd) { | |
905 | IWL_CMD(MANAGEMENT_ASSOC_REQ); | |
906 | IWL_CMD(MANAGEMENT_ASSOC_RESP); | |
907 | IWL_CMD(MANAGEMENT_REASSOC_REQ); | |
908 | IWL_CMD(MANAGEMENT_REASSOC_RESP); | |
909 | IWL_CMD(MANAGEMENT_PROBE_REQ); | |
910 | IWL_CMD(MANAGEMENT_PROBE_RESP); | |
911 | IWL_CMD(MANAGEMENT_BEACON); | |
912 | IWL_CMD(MANAGEMENT_ATIM); | |
913 | IWL_CMD(MANAGEMENT_DISASSOC); | |
914 | IWL_CMD(MANAGEMENT_AUTH); | |
915 | IWL_CMD(MANAGEMENT_DEAUTH); | |
916 | IWL_CMD(MANAGEMENT_ACTION); | |
917 | default: | |
918 | return "UNKNOWN"; | |
919 | ||
920 | } | |
921 | } | |
922 | ||
923 | const char *get_ctrl_string(int cmd) | |
924 | { | |
925 | switch (cmd) { | |
926 | IWL_CMD(CONTROL_BACK_REQ); | |
927 | IWL_CMD(CONTROL_BACK); | |
928 | IWL_CMD(CONTROL_PSPOLL); | |
929 | IWL_CMD(CONTROL_RTS); | |
930 | IWL_CMD(CONTROL_CTS); | |
931 | IWL_CMD(CONTROL_ACK); | |
932 | IWL_CMD(CONTROL_CFEND); | |
933 | IWL_CMD(CONTROL_CFENDACK); | |
934 | default: | |
935 | return "UNKNOWN"; | |
936 | ||
937 | } | |
938 | } | |
939 | ||
7163b8a4 | 940 | void iwl_clear_traffic_stats(struct iwl_priv *priv) |
22fdf3c9 WYG |
941 | { |
942 | memset(&priv->tx_stats, 0, sizeof(struct traffic_stats)); | |
22fdf3c9 WYG |
943 | memset(&priv->rx_stats, 0, sizeof(struct traffic_stats)); |
944 | } | |
945 | ||
946 | /* | |
947 | * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will | |
948 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass. | |
949 | * Use debugFs to display the rx/rx_statistics | |
950 | * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL | |
951 | * information will be recorded, but DATA pkt still will be recorded | |
952 | * for the reason of iwl_led.c need to control the led blinking based on | |
953 | * number of tx and rx data. | |
954 | * | |
955 | */ | |
956 | void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len) | |
957 | { | |
958 | struct traffic_stats *stats; | |
959 | ||
960 | if (is_tx) | |
961 | stats = &priv->tx_stats; | |
962 | else | |
963 | stats = &priv->rx_stats; | |
964 | ||
965 | if (ieee80211_is_mgmt(fc)) { | |
966 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
967 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
968 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
969 | break; | |
970 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
971 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
972 | break; | |
973 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
974 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
975 | break; | |
976 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
977 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
978 | break; | |
979 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
980 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
981 | break; | |
982 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
983 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
984 | break; | |
985 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
986 | stats->mgmt[MANAGEMENT_BEACON]++; | |
987 | break; | |
988 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
989 | stats->mgmt[MANAGEMENT_ATIM]++; | |
990 | break; | |
991 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
992 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
993 | break; | |
994 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
995 | stats->mgmt[MANAGEMENT_AUTH]++; | |
996 | break; | |
997 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
998 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
999 | break; | |
1000 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
1001 | stats->mgmt[MANAGEMENT_ACTION]++; | |
1002 | break; | |
1003 | } | |
1004 | } else if (ieee80211_is_ctl(fc)) { | |
1005 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
1006 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
1007 | stats->ctrl[CONTROL_BACK_REQ]++; | |
1008 | break; | |
1009 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
1010 | stats->ctrl[CONTROL_BACK]++; | |
1011 | break; | |
1012 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
1013 | stats->ctrl[CONTROL_PSPOLL]++; | |
1014 | break; | |
1015 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
1016 | stats->ctrl[CONTROL_RTS]++; | |
1017 | break; | |
1018 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
1019 | stats->ctrl[CONTROL_CTS]++; | |
1020 | break; | |
1021 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
1022 | stats->ctrl[CONTROL_ACK]++; | |
1023 | break; | |
1024 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
1025 | stats->ctrl[CONTROL_CFEND]++; | |
1026 | break; | |
1027 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
1028 | stats->ctrl[CONTROL_CFENDACK]++; | |
1029 | break; | |
1030 | } | |
1031 | } else { | |
1032 | /* data */ | |
1033 | stats->data_cnt++; | |
1034 | stats->data_bytes += len; | |
1035 | } | |
1036 | } | |
20594eb0 WYG |
1037 | #endif |
1038 | ||
a93e7973 | 1039 | static void iwl_force_rf_reset(struct iwl_priv *priv) |
afbdd69a | 1040 | { |
83626404 | 1041 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
afbdd69a WYG |
1042 | return; |
1043 | ||
246ed355 | 1044 | if (!iwl_is_any_associated(priv)) { |
afbdd69a WYG |
1045 | IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n"); |
1046 | return; | |
1047 | } | |
1048 | /* | |
1049 | * There is no easy and better way to force reset the radio, | |
1050 | * the only known method is switching channel which will force to | |
1051 | * reset and tune the radio. | |
1052 | * Use internal short scan (single channel) operation to should | |
1053 | * achieve this objective. | |
1054 | * Driver should reset the radio when number of consecutive missed | |
1055 | * beacon, or any other uCode error condition detected. | |
1056 | */ | |
1057 | IWL_DEBUG_INFO(priv, "perform radio reset.\n"); | |
1058 | iwl_internal_short_hw_scan(priv); | |
afbdd69a | 1059 | } |
a93e7973 | 1060 | |
a93e7973 | 1061 | |
c04f9f22 | 1062 | int iwl_force_reset(struct iwl_priv *priv, int mode, bool external) |
a93e7973 | 1063 | { |
8a472da4 WYG |
1064 | struct iwl_force_reset *force_reset; |
1065 | ||
83626404 | 1066 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
a93e7973 WYG |
1067 | return -EINVAL; |
1068 | ||
8a472da4 WYG |
1069 | if (mode >= IWL_MAX_FORCE_RESET) { |
1070 | IWL_DEBUG_INFO(priv, "invalid reset request.\n"); | |
1071 | return -EINVAL; | |
1072 | } | |
1073 | force_reset = &priv->force_reset[mode]; | |
1074 | force_reset->reset_request_count++; | |
c04f9f22 WYG |
1075 | if (!external) { |
1076 | if (force_reset->last_force_reset_jiffies && | |
1077 | time_after(force_reset->last_force_reset_jiffies + | |
1078 | force_reset->reset_duration, jiffies)) { | |
1079 | IWL_DEBUG_INFO(priv, "force reset rejected\n"); | |
1080 | force_reset->reset_reject_count++; | |
1081 | return -EAGAIN; | |
1082 | } | |
a93e7973 | 1083 | } |
8a472da4 WYG |
1084 | force_reset->reset_success_count++; |
1085 | force_reset->last_force_reset_jiffies = jiffies; | |
a93e7973 | 1086 | IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode); |
a93e7973 WYG |
1087 | switch (mode) { |
1088 | case IWL_RF_RESET: | |
1089 | iwl_force_rf_reset(priv); | |
1090 | break; | |
1091 | case IWL_FW_RESET: | |
c04f9f22 WYG |
1092 | /* |
1093 | * if the request is from external(ex: debugfs), | |
1094 | * then always perform the request in regardless the module | |
1095 | * parameter setting | |
1096 | * if the request is from internal (uCode error or driver | |
1097 | * detect failure), then fw_restart module parameter | |
1098 | * need to be check before performing firmware reload | |
1099 | */ | |
9d143e9a | 1100 | if (!external && !iwlagn_mod_params.restart_fw) { |
c04f9f22 WYG |
1101 | IWL_DEBUG_INFO(priv, "Cancel firmware reload based on " |
1102 | "module parameter setting\n"); | |
1103 | break; | |
1104 | } | |
a93e7973 | 1105 | IWL_ERR(priv, "On demand firmware reload\n"); |
e649437f | 1106 | iwlagn_fw_error(priv, true); |
a93e7973 | 1107 | break; |
a93e7973 | 1108 | } |
a93e7973 WYG |
1109 | return 0; |
1110 | } | |
b74e31a9 | 1111 | |
d4daaea6 | 1112 | |
317d09f7 WYG |
1113 | int iwl_cmd_echo_test(struct iwl_priv *priv) |
1114 | { | |
7e4005cc | 1115 | int ret; |
317d09f7 WYG |
1116 | struct iwl_host_cmd cmd = { |
1117 | .id = REPLY_ECHO, | |
89db3b97 | 1118 | .len = { 0 }, |
317d09f7 WYG |
1119 | .flags = CMD_SYNC, |
1120 | }; | |
1121 | ||
e10a0533 | 1122 | ret = iwl_dvm_send_cmd(priv, &cmd); |
7e4005cc WYG |
1123 | if (ret) |
1124 | IWL_ERR(priv, "echo testing fail: 0X%x\n", ret); | |
1125 | else | |
1126 | IWL_DEBUG_INFO(priv, "echo testing pass\n"); | |
1127 | return ret; | |
317d09f7 WYG |
1128 | } |
1129 | ||
f22be624 | 1130 | static inline int iwl_check_stuck_queue(struct iwl_priv *priv, int txq) |
b74e31a9 | 1131 | { |
f22be624 | 1132 | if (iwl_trans_check_stuck_queue(trans(priv), txq)) { |
317d09f7 | 1133 | int ret; |
317d09f7 | 1134 | ret = iwl_force_reset(priv, IWL_FW_RESET, false); |
22de94de | 1135 | return (ret == -EAGAIN) ? 0 : 1; |
b74e31a9 WYG |
1136 | } |
1137 | return 0; | |
1138 | } | |
1139 | ||
22de94de SG |
1140 | /* |
1141 | * Making watchdog tick be a quarter of timeout assure we will | |
1142 | * discover the queue hung between timeout and 1.25*timeout | |
1143 | */ | |
1144 | #define IWL_WD_TICK(timeout) ((timeout) / 4) | |
1145 | ||
1146 | /* | |
1147 | * Watchdog timer callback, we check each tx queue for stuck, if if hung | |
1148 | * we reset the firmware. If everything is fine just rearm the timer. | |
1149 | */ | |
1150 | void iwl_bg_watchdog(unsigned long data) | |
b74e31a9 WYG |
1151 | { |
1152 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
1153 | int cnt; | |
22de94de | 1154 | unsigned long timeout; |
b74e31a9 | 1155 | |
83626404 | 1156 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b74e31a9 WYG |
1157 | return; |
1158 | ||
83626404 | 1159 | if (iwl_is_rfkill(priv)) |
46e7741e WYG |
1160 | return; |
1161 | ||
e7a09438 | 1162 | timeout = hw_params(priv).wd_timeout; |
22de94de SG |
1163 | if (timeout == 0) |
1164 | return; | |
1165 | ||
342bbf3f | 1166 | /* monitor and check for stuck queues */ |
3cc241ad | 1167 | for (cnt = 0; cnt < cfg(priv)->base_params->num_of_queues; cnt++) |
342bbf3f JB |
1168 | if (iwl_check_stuck_queue(priv, cnt)) |
1169 | return; | |
22de94de SG |
1170 | |
1171 | mod_timer(&priv->watchdog, jiffies + | |
1172 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
b74e31a9 | 1173 | } |
22de94de SG |
1174 | |
1175 | void iwl_setup_watchdog(struct iwl_priv *priv) | |
1176 | { | |
e7a09438 | 1177 | unsigned int timeout = hw_params(priv).wd_timeout; |
afbdd69a | 1178 | |
9995ffe5 WYG |
1179 | if (!iwlagn_mod_params.wd_disable) { |
1180 | /* use system default */ | |
38622419 | 1181 | if (timeout && !cfg(priv)->base_params->wd_disable) |
9995ffe5 WYG |
1182 | mod_timer(&priv->watchdog, |
1183 | jiffies + | |
1184 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1185 | else | |
1186 | del_timer(&priv->watchdog); | |
1187 | } else { | |
1188 | /* module parameter overwrite default configuration */ | |
1189 | if (timeout && iwlagn_mod_params.wd_disable == 2) | |
1190 | mod_timer(&priv->watchdog, | |
1191 | jiffies + | |
1192 | msecs_to_jiffies(IWL_WD_TICK(timeout))); | |
1193 | else | |
1194 | del_timer(&priv->watchdog); | |
1195 | } | |
22de94de | 1196 | } |
a0ee74cf | 1197 | |
8c222544 EG |
1198 | /** |
1199 | * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time | |
1200 | * @priv -- pointer to iwl_priv data structure | |
1201 | * @tsf_bits -- number of bits need to shift for masking) | |
1202 | */ | |
1203 | static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv, | |
1204 | u16 tsf_bits) | |
1205 | { | |
1206 | return (1 << tsf_bits) - 1; | |
1207 | } | |
1208 | ||
1209 | /** | |
1210 | * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time | |
1211 | * @priv -- pointer to iwl_priv data structure | |
1212 | * @tsf_bits -- number of bits need to shift for masking) | |
1213 | */ | |
1214 | static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv, | |
1215 | u16 tsf_bits) | |
1216 | { | |
1217 | return ((1 << (32 - tsf_bits)) - 1) << tsf_bits; | |
1218 | } | |
1219 | ||
a0ee74cf WYG |
1220 | /* |
1221 | * extended beacon time format | |
1222 | * time in usec will be changed into a 32-bit value in extended:internal format | |
1223 | * the extended part is the beacon counts | |
1224 | * the internal part is the time in usec within one beacon interval | |
1225 | */ | |
1226 | u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval) | |
1227 | { | |
1228 | u32 quot; | |
1229 | u32 rem; | |
1230 | u32 interval = beacon_interval * TIME_UNIT; | |
1231 | ||
1232 | if (!interval || !usec) | |
1233 | return 0; | |
1234 | ||
1235 | quot = (usec / interval) & | |
403ba56a DF |
1236 | (iwl_beacon_time_mask_high(priv, IWLAGN_EXT_BEACON_TIME_POS) >> |
1237 | IWLAGN_EXT_BEACON_TIME_POS); | |
a0ee74cf | 1238 | rem = (usec % interval) & iwl_beacon_time_mask_low(priv, |
403ba56a | 1239 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1240 | |
403ba56a | 1241 | return (quot << IWLAGN_EXT_BEACON_TIME_POS) + rem; |
a0ee74cf | 1242 | } |
a0ee74cf WYG |
1243 | |
1244 | /* base is usually what we get from ucode with each received frame, | |
1245 | * the same as HW timer counter counting down | |
1246 | */ | |
1247 | __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, | |
1248 | u32 addon, u32 beacon_interval) | |
1249 | { | |
1250 | u32 base_low = base & iwl_beacon_time_mask_low(priv, | |
403ba56a | 1251 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1252 | u32 addon_low = addon & iwl_beacon_time_mask_low(priv, |
403ba56a | 1253 | IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf WYG |
1254 | u32 interval = beacon_interval * TIME_UNIT; |
1255 | u32 res = (base & iwl_beacon_time_mask_high(priv, | |
403ba56a | 1256 | IWLAGN_EXT_BEACON_TIME_POS)) + |
a0ee74cf | 1257 | (addon & iwl_beacon_time_mask_high(priv, |
403ba56a | 1258 | IWLAGN_EXT_BEACON_TIME_POS)); |
a0ee74cf WYG |
1259 | |
1260 | if (base_low > addon_low) | |
1261 | res += base_low - addon_low; | |
1262 | else if (base_low < addon_low) { | |
1263 | res += interval + base_low - addon_low; | |
403ba56a | 1264 | res += (1 << IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf | 1265 | } else |
403ba56a | 1266 | res += (1 << IWLAGN_EXT_BEACON_TIME_POS); |
a0ee74cf WYG |
1267 | |
1268 | return cpu_to_le32(res); | |
1269 | } | |
a0ee74cf | 1270 | |
7120d989 | 1271 | void iwl_set_hw_rfkill_state(struct iwl_op_mode *op_mode, bool state) |
3e10caeb | 1272 | { |
7120d989 EG |
1273 | struct iwl_priv *priv = IWL_OP_MODE_GET_DVM(op_mode); |
1274 | ||
c9eec95c | 1275 | if (state) |
83626404 | 1276 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
c9eec95c | 1277 | else |
83626404 | 1278 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
c9eec95c | 1279 | |
3e10caeb EG |
1280 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, state); |
1281 | } | |
7a10e3e4 | 1282 | |
ed277c93 | 1283 | void iwl_free_skb(struct iwl_op_mode *op_mode, struct sk_buff *skb) |
909e9b23 EG |
1284 | { |
1285 | struct ieee80211_tx_info *info; | |
1286 | ||
1287 | info = IEEE80211_SKB_CB(skb); | |
354928dd | 1288 | kmem_cache_free(iwl_tx_cmd_pool, (info->driver_data[1])); |
909e9b23 EG |
1289 | dev_kfree_skb_any(skb); |
1290 | } |