Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
b481de9c ZY |
43 | #include <net/mac80211.h> |
44 | ||
45 | #include <asm/div64.h> | |
46 | ||
a3139c59 SO |
47 | #define DRV_NAME "iwlagn" |
48 | ||
6bc913bd | 49 | #include "iwl-eeprom.h" |
3e0d4cb1 | 50 | #include "iwl-dev.h" |
fee1247a | 51 | #include "iwl-core.h" |
3395f6e9 | 52 | #include "iwl-io.h" |
b481de9c | 53 | #include "iwl-helpers.h" |
6974e363 | 54 | #include "iwl-sta.h" |
f0832f13 | 55 | #include "iwl-calib.h" |
b481de9c | 56 | |
416e1438 | 57 | |
b481de9c ZY |
58 | /****************************************************************************** |
59 | * | |
60 | * module boiler plate | |
61 | * | |
62 | ******************************************************************************/ | |
63 | ||
b481de9c ZY |
64 | /* |
65 | * module name, copyright, version, etc. | |
b481de9c | 66 | */ |
d783b061 | 67 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 68 | |
0a6857e7 | 69 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
70 | #define VD "d" |
71 | #else | |
72 | #define VD | |
73 | #endif | |
74 | ||
4fc22b21 | 75 | #ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT |
b481de9c ZY |
76 | #define VS "s" |
77 | #else | |
78 | #define VS | |
79 | #endif | |
80 | ||
df48c323 | 81 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 87 | MODULE_LICENSE("GPL"); |
4fc22b21 | 88 | MODULE_ALIAS("iwl4965"); |
b481de9c | 89 | |
b481de9c | 90 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 91 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
92 | * the functionality provided here |
93 | */ | |
94 | ||
95 | /**************************************************************/ | |
96 | ||
b481de9c | 97 | /** |
5b9f8cd3 | 98 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 99 | * |
01ebd063 | 100 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
101 | * the active_rxon structure is updated with the new data. This |
102 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
103 | * a HW tune is required based on the RXON structure changes. | |
104 | */ | |
5b9f8cd3 | 105 | static int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
106 | { |
107 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 108 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
109 | int ret; |
110 | bool new_assoc = | |
111 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 112 | |
fee1247a | 113 | if (!iwl_is_alive(priv)) |
43d59b32 | 114 | return -EBUSY; |
b481de9c ZY |
115 | |
116 | /* always get timestamp with Rx frame */ | |
117 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
a326a5d0 EG |
118 | /* allow CTS-to-self if possible. this is relevant only for |
119 | * 5000, but will not damage 4965 */ | |
120 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
b481de9c | 121 | |
8ccde88a | 122 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 123 | if (ret) { |
15b1687c | 124 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
125 | return -EINVAL; |
126 | } | |
127 | ||
128 | /* If we don't need to send a full RXON, we can use | |
5b9f8cd3 | 129 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 130 | * and other flags for the current radio configuration. */ |
54559703 | 131 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
132 | ret = iwl_send_rxon_assoc(priv); |
133 | if (ret) { | |
15b1687c | 134 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 135 | return ret; |
b481de9c ZY |
136 | } |
137 | ||
138 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
139 | return 0; |
140 | } | |
141 | ||
142 | /* station table will be cleared */ | |
143 | priv->assoc_station_added = 0; | |
144 | ||
b481de9c ZY |
145 | /* If we are currently associated and the new config requires |
146 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
147 | * we must clear the associated from the active configuration | |
148 | * before we apply the new config */ | |
43d59b32 | 149 | if (iwl_is_associated(priv) && new_assoc) { |
b481de9c ZY |
150 | IWL_DEBUG_INFO("Toggling associated bit on current RXON\n"); |
151 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
152 | ||
43d59b32 | 153 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 154 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
155 | &priv->active_rxon); |
156 | ||
157 | /* If the mask clearing failed then we set | |
158 | * active_rxon back to what it was previously */ | |
43d59b32 | 159 | if (ret) { |
b481de9c | 160 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 161 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 162 | return ret; |
b481de9c | 163 | } |
b481de9c ZY |
164 | } |
165 | ||
166 | IWL_DEBUG_INFO("Sending RXON\n" | |
167 | "* with%s RXON_FILTER_ASSOC_MSK\n" | |
168 | "* channel = %d\n" | |
e174961c | 169 | "* bssid = %pM\n", |
43d59b32 | 170 | (new_assoc ? "" : "out"), |
b481de9c | 171 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 172 | priv->staging_rxon.bssid_addr); |
b481de9c | 173 | |
5b9f8cd3 | 174 | iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto); |
43d59b32 EG |
175 | |
176 | /* Apply the new configuration | |
177 | * RXON unassoc clears the station table in uCode, send it before | |
178 | * we add the bcast station. If assoc bit is set, we will send RXON | |
179 | * after having added the bcast and bssid station. | |
180 | */ | |
181 | if (!new_assoc) { | |
182 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 183 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 184 | if (ret) { |
15b1687c | 185 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
186 | return ret; |
187 | } | |
188 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
189 | } |
190 | ||
37deb2a0 | 191 | iwl_clear_stations_table(priv); |
556f8db7 | 192 | |
b481de9c ZY |
193 | if (!priv->error_recovering) |
194 | priv->start_calib = 0; | |
195 | ||
b481de9c | 196 | /* Add the broadcast address so we can send broadcast frames */ |
4f40e4d9 | 197 | if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) == |
43d59b32 | 198 | IWL_INVALID_STATION) { |
15b1687c | 199 | IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n"); |
b481de9c ZY |
200 | return -EIO; |
201 | } | |
202 | ||
203 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
204 | * add the IWL_AP_ID to the station rate table */ | |
9185159d | 205 | if (new_assoc) { |
05c914fe | 206 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
9185159d TW |
207 | ret = iwl_rxon_add_station(priv, |
208 | priv->active_rxon.bssid_addr, 1); | |
209 | if (ret == IWL_INVALID_STATION) { | |
15b1687c WT |
210 | IWL_ERR(priv, |
211 | "Error adding AP address for TX.\n"); | |
9185159d TW |
212 | return -EIO; |
213 | } | |
214 | priv->assoc_station_added = 1; | |
215 | if (priv->default_wep_key && | |
216 | iwl_send_static_wepkey_cmd(priv, 0)) | |
15b1687c WT |
217 | IWL_ERR(priv, |
218 | "Could not send WEP static key.\n"); | |
b481de9c | 219 | } |
43d59b32 EG |
220 | |
221 | /* Apply the new configuration | |
222 | * RXON assoc doesn't clear the station table in uCode, | |
223 | */ | |
224 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
225 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
226 | if (ret) { | |
15b1687c | 227 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
228 | return ret; |
229 | } | |
230 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
231 | } |
232 | ||
36da7d70 ZY |
233 | iwl_init_sensitivity(priv); |
234 | ||
235 | /* If we issue a new RXON command which required a tune then we must | |
236 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
237 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
238 | if (ret) { | |
15b1687c | 239 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
240 | return ret; |
241 | } | |
242 | ||
b481de9c ZY |
243 | return 0; |
244 | } | |
245 | ||
5b9f8cd3 | 246 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
247 | { |
248 | ||
c7de35cd | 249 | iwl_set_rxon_chain(priv); |
5b9f8cd3 | 250 | iwl_commit_rxon(priv); |
5da4b55f MA |
251 | } |
252 | ||
fcab423d | 253 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
254 | { |
255 | struct list_head *element; | |
256 | ||
257 | IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n", | |
258 | priv->frames_count); | |
259 | ||
260 | while (!list_empty(&priv->free_frames)) { | |
261 | element = priv->free_frames.next; | |
262 | list_del(element); | |
fcab423d | 263 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
264 | priv->frames_count--; |
265 | } | |
266 | ||
267 | if (priv->frames_count) { | |
39aadf8c | 268 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
269 | priv->frames_count); |
270 | priv->frames_count = 0; | |
271 | } | |
272 | } | |
273 | ||
fcab423d | 274 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 275 | { |
fcab423d | 276 | struct iwl_frame *frame; |
b481de9c ZY |
277 | struct list_head *element; |
278 | if (list_empty(&priv->free_frames)) { | |
279 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
280 | if (!frame) { | |
15b1687c | 281 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
282 | return NULL; |
283 | } | |
284 | ||
285 | priv->frames_count++; | |
286 | return frame; | |
287 | } | |
288 | ||
289 | element = priv->free_frames.next; | |
290 | list_del(element); | |
fcab423d | 291 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
292 | } |
293 | ||
fcab423d | 294 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
295 | { |
296 | memset(frame, 0, sizeof(*frame)); | |
297 | list_add(&frame->list, &priv->free_frames); | |
298 | } | |
299 | ||
4bf64efd TW |
300 | static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv, |
301 | struct ieee80211_hdr *hdr, | |
73ec1cc2 | 302 | int left) |
b481de9c | 303 | { |
3109ece1 | 304 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
305 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
306 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
307 | return 0; |
308 | ||
309 | if (priv->ibss_beacon->len > left) | |
310 | return 0; | |
311 | ||
312 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
313 | ||
314 | return priv->ibss_beacon->len; | |
315 | } | |
316 | ||
5b9f8cd3 | 317 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
4bf64efd TW |
318 | struct iwl_frame *frame, u8 rate) |
319 | { | |
320 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
321 | unsigned int frame_size; | |
322 | ||
323 | tx_beacon_cmd = &frame->u.beacon; | |
324 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
325 | ||
326 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; | |
327 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
328 | ||
329 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, | |
4bf64efd TW |
330 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
331 | ||
332 | BUG_ON(frame_size > MAX_MPDU_SIZE); | |
333 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
334 | ||
335 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | |
336 | tx_beacon_cmd->tx.rate_n_flags = | |
337 | iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); | |
338 | else | |
339 | tx_beacon_cmd->tx.rate_n_flags = | |
340 | iwl_hw_set_rate_n_flags(rate, 0); | |
341 | ||
342 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
343 | TX_CMD_FLG_TSF_MSK | | |
344 | TX_CMD_FLG_STA_RATE_MSK; | |
345 | ||
346 | return sizeof(*tx_beacon_cmd) + frame_size; | |
347 | } | |
5b9f8cd3 | 348 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 349 | { |
fcab423d | 350 | struct iwl_frame *frame; |
b481de9c ZY |
351 | unsigned int frame_size; |
352 | int rc; | |
353 | u8 rate; | |
354 | ||
fcab423d | 355 | frame = iwl_get_free_frame(priv); |
b481de9c ZY |
356 | |
357 | if (!frame) { | |
15b1687c | 358 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
359 | "command.\n"); |
360 | return -ENOMEM; | |
361 | } | |
362 | ||
5b9f8cd3 | 363 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 364 | |
5b9f8cd3 | 365 | frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 366 | |
857485c0 | 367 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
368 | &frame->u.cmd[0]); |
369 | ||
fcab423d | 370 | iwl_free_frame(priv, frame); |
b481de9c ZY |
371 | |
372 | return rc; | |
373 | } | |
374 | ||
7aaa1d79 SO |
375 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
376 | { | |
377 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
378 | ||
379 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
380 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
381 | addr |= | |
382 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
383 | ||
384 | return addr; | |
385 | } | |
386 | ||
387 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
388 | { | |
389 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
390 | ||
391 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
392 | } | |
393 | ||
394 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
395 | dma_addr_t addr, u16 len) | |
396 | { | |
397 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
398 | u16 hi_n_len = len << 4; | |
399 | ||
400 | put_unaligned_le32(addr, &tb->lo); | |
401 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
402 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
403 | ||
404 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
405 | ||
406 | tfd->num_tbs = idx + 1; | |
407 | } | |
408 | ||
409 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
410 | { | |
411 | return tfd->num_tbs & 0x1f; | |
412 | } | |
413 | ||
414 | /** | |
415 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
416 | * @priv - driver private data | |
417 | * @txq - tx queue | |
418 | * | |
419 | * Does NOT advance any TFD circular buffer read/write indexes | |
420 | * Does NOT free the TFD itself (which is within circular buffer) | |
421 | */ | |
422 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
423 | { | |
59606ffa | 424 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
425 | struct iwl_tfd *tfd; |
426 | struct pci_dev *dev = priv->pci_dev; | |
427 | int index = txq->q.read_ptr; | |
428 | int i; | |
429 | int num_tbs; | |
430 | ||
431 | tfd = &tfd_tmp[index]; | |
432 | ||
433 | /* Sanity check on number of chunks */ | |
434 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
435 | ||
436 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
437 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
438 | /* @todo issue fatal error, it is quite serious situation */ | |
439 | return; | |
440 | } | |
441 | ||
442 | /* Unmap tx_cmd */ | |
443 | if (num_tbs) | |
444 | pci_unmap_single(dev, | |
445 | pci_unmap_addr(&txq->cmd[index]->meta, mapping), | |
446 | pci_unmap_len(&txq->cmd[index]->meta, len), | |
447 | PCI_DMA_TODEVICE); | |
448 | ||
449 | /* Unmap chunks, if any. */ | |
450 | for (i = 1; i < num_tbs; i++) { | |
451 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
452 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
453 | ||
454 | if (txq->txb) { | |
455 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
456 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
457 | } | |
458 | } | |
459 | } | |
460 | ||
461 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
462 | struct iwl_tx_queue *txq, | |
463 | dma_addr_t addr, u16 len, | |
464 | u8 reset, u8 pad) | |
465 | { | |
466 | struct iwl_queue *q; | |
59606ffa | 467 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
468 | u32 num_tbs; |
469 | ||
470 | q = &txq->q; | |
59606ffa SO |
471 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
472 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
473 | |
474 | if (reset) | |
475 | memset(tfd, 0, sizeof(*tfd)); | |
476 | ||
477 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
478 | ||
479 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
480 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
481 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
482 | IWL_NUM_OF_TBS); | |
483 | return -EINVAL; | |
484 | } | |
485 | ||
486 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
487 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
488 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
489 | (unsigned long long)addr); | |
490 | ||
491 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
a8e74e27 SO |
496 | /* |
497 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
498 | * given Tx queue, and enable the DMA channel used for that queue. | |
499 | * | |
500 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
501 | * channels supported in hardware. | |
502 | */ | |
503 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
504 | struct iwl_tx_queue *txq) | |
505 | { | |
506 | int ret; | |
507 | unsigned long flags; | |
508 | int txq_id = txq->q.id; | |
509 | ||
510 | spin_lock_irqsave(&priv->lock, flags); | |
511 | ret = iwl_grab_nic_access(priv); | |
512 | if (ret) { | |
513 | spin_unlock_irqrestore(&priv->lock, flags); | |
514 | return ret; | |
515 | } | |
516 | ||
517 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
518 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
519 | txq->q.dma_addr >> 8); | |
520 | ||
521 | iwl_release_nic_access(priv); | |
522 | spin_unlock_irqrestore(&priv->lock, flags); | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | ||
b481de9c ZY |
528 | /****************************************************************************** |
529 | * | |
530 | * Misc. internal state and helper functions | |
531 | * | |
532 | ******************************************************************************/ | |
b481de9c | 533 | |
5b9f8cd3 | 534 | static void iwl_ht_conf(struct iwl_priv *priv, |
d1141dfb EG |
535 | struct ieee80211_bss_conf *bss_conf) |
536 | { | |
ae5eb026 | 537 | struct ieee80211_sta_ht_cap *ht_conf; |
d1141dfb | 538 | struct iwl_ht_info *iwl_conf = &priv->current_ht_config; |
ae5eb026 | 539 | struct ieee80211_sta *sta; |
d1141dfb EG |
540 | |
541 | IWL_DEBUG_MAC80211("enter: \n"); | |
542 | ||
d1141dfb EG |
543 | if (!iwl_conf->is_ht) |
544 | return; | |
545 | ||
ae5eb026 JB |
546 | |
547 | /* | |
548 | * It is totally wrong to base global information on something | |
549 | * that is valid only when associated, alas, this driver works | |
550 | * that way and I don't know how to fix it. | |
551 | */ | |
552 | ||
553 | rcu_read_lock(); | |
554 | sta = ieee80211_find_sta(priv->hw, priv->bssid); | |
555 | if (!sta) { | |
556 | rcu_read_unlock(); | |
557 | return; | |
558 | } | |
559 | ht_conf = &sta->ht_cap; | |
560 | ||
d1141dfb | 561 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20) |
a9841013 | 562 | iwl_conf->sgf |= HT_SHORT_GI_20MHZ; |
d1141dfb | 563 | if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40) |
a9841013 | 564 | iwl_conf->sgf |= HT_SHORT_GI_40MHZ; |
d1141dfb EG |
565 | |
566 | iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD); | |
567 | iwl_conf->max_amsdu_size = | |
568 | !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU); | |
569 | ||
570 | iwl_conf->supported_chan_width = | |
d9fe60de | 571 | !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40); |
ae5eb026 | 572 | |
094d05dc S |
573 | /* |
574 | * XXX: The HT configuration needs to be moved into iwl_mac_config() | |
575 | * to be done there correctly. | |
576 | */ | |
577 | ||
578 | iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE; | |
de27e64e | 579 | if (conf_is_ht40_minus(&priv->hw->conf)) |
094d05dc | 580 | iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW; |
de27e64e | 581 | else if (conf_is_ht40_plus(&priv->hw->conf)) |
094d05dc S |
582 | iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE; |
583 | ||
d1141dfb | 584 | /* If no above or below channel supplied disable FAT channel */ |
d9fe60de | 585 | if (iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_ABOVE && |
094d05dc | 586 | iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
d1141dfb EG |
587 | iwl_conf->supported_chan_width = 0; |
588 | ||
12837be1 RR |
589 | iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2); |
590 | ||
d9fe60de | 591 | memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16); |
d1141dfb | 592 | |
094d05dc | 593 | iwl_conf->tx_chan_width = iwl_conf->supported_chan_width != 0; |
d1141dfb | 594 | iwl_conf->ht_protection = |
ae5eb026 | 595 | bss_conf->ht.operation_mode & IEEE80211_HT_OP_MODE_PROTECTION; |
d1141dfb | 596 | iwl_conf->non_GF_STA_present = |
ae5eb026 JB |
597 | !!(bss_conf->ht.operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); |
598 | ||
599 | rcu_read_unlock(); | |
d1141dfb | 600 | |
d1141dfb EG |
601 | IWL_DEBUG_MAC80211("leave\n"); |
602 | } | |
603 | ||
b481de9c ZY |
604 | /* |
605 | * QoS support | |
606 | */ | |
1ff50bda | 607 | static void iwl_activate_qos(struct iwl_priv *priv, u8 force) |
b481de9c | 608 | { |
b481de9c ZY |
609 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
610 | return; | |
611 | ||
b481de9c ZY |
612 | priv->qos_data.def_qos_parm.qos_flags = 0; |
613 | ||
614 | if (priv->qos_data.qos_cap.q_AP.queue_request && | |
615 | !priv->qos_data.qos_cap.q_AP.txop_request) | |
616 | priv->qos_data.def_qos_parm.qos_flags |= | |
617 | QOS_PARAM_FLG_TXOP_TYPE_MSK; | |
b481de9c ZY |
618 | if (priv->qos_data.qos_active) |
619 | priv->qos_data.def_qos_parm.qos_flags |= | |
620 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; | |
621 | ||
fd105e79 | 622 | if (priv->current_ht_config.is_ht) |
f1f1f5c7 | 623 | priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; |
f1f1f5c7 | 624 | |
3109ece1 | 625 | if (force || iwl_is_associated(priv)) { |
f1f1f5c7 TW |
626 | IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n", |
627 | priv->qos_data.qos_active, | |
628 | priv->qos_data.def_qos_parm.qos_flags); | |
b481de9c | 629 | |
1ff50bda EG |
630 | iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM, |
631 | sizeof(struct iwl_qosparam_cmd), | |
632 | &priv->qos_data.def_qos_parm, NULL); | |
b481de9c ZY |
633 | } |
634 | } | |
635 | ||
b481de9c | 636 | #define MAX_UCODE_BEACON_INTERVAL 4096 |
b481de9c | 637 | |
3195c1f3 | 638 | static u16 iwl_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
639 | { |
640 | u16 new_val = 0; | |
641 | u16 beacon_factor = 0; | |
642 | ||
3195c1f3 TW |
643 | beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL) |
644 | / MAX_UCODE_BEACON_INTERVAL; | |
b481de9c ZY |
645 | new_val = beacon_val / beacon_factor; |
646 | ||
3195c1f3 | 647 | return new_val; |
b481de9c ZY |
648 | } |
649 | ||
3195c1f3 | 650 | static void iwl_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c | 651 | { |
3195c1f3 TW |
652 | u64 tsf; |
653 | s32 interval_tm, rem; | |
b481de9c ZY |
654 | unsigned long flags; |
655 | struct ieee80211_conf *conf = NULL; | |
656 | u16 beacon_int = 0; | |
657 | ||
658 | conf = ieee80211_get_hw_conf(priv->hw); | |
659 | ||
660 | spin_lock_irqsave(&priv->lock, flags); | |
3195c1f3 | 661 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); |
b5d7be5e | 662 | priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval); |
b481de9c | 663 | |
05c914fe | 664 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
3195c1f3 | 665 | beacon_int = iwl_adjust_beacon_interval(priv->beacon_int); |
b481de9c ZY |
666 | priv->rxon_timing.atim_window = 0; |
667 | } else { | |
3195c1f3 TW |
668 | beacon_int = iwl_adjust_beacon_interval(conf->beacon_int); |
669 | ||
b481de9c ZY |
670 | /* TODO: we need to get atim_window from upper stack |
671 | * for now we set to 0 */ | |
672 | priv->rxon_timing.atim_window = 0; | |
673 | } | |
674 | ||
3195c1f3 | 675 | priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int); |
b481de9c | 676 | |
3195c1f3 TW |
677 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ |
678 | interval_tm = beacon_int * 1024; | |
679 | rem = do_div(tsf, interval_tm); | |
680 | priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem); | |
681 | ||
682 | spin_unlock_irqrestore(&priv->lock, flags); | |
683 | IWL_DEBUG_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n", | |
684 | le16_to_cpu(priv->rxon_timing.beacon_interval), | |
685 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
686 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
b481de9c ZY |
687 | } |
688 | ||
5b9f8cd3 | 689 | static int iwl_set_mode(struct iwl_priv *priv, int mode) |
b481de9c | 690 | { |
5b9f8cd3 | 691 | iwl_connection_init_rx_config(priv, mode); |
8ccde88a | 692 | iwl_set_rxon_chain(priv); |
b481de9c ZY |
693 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
694 | ||
37deb2a0 | 695 | iwl_clear_stations_table(priv); |
b481de9c | 696 | |
fde3571f | 697 | /* dont commit rxon if rf-kill is on*/ |
fee1247a | 698 | if (!iwl_is_ready_rf(priv)) |
fde3571f MA |
699 | return -EAGAIN; |
700 | ||
701 | cancel_delayed_work(&priv->scan_check); | |
2a421b91 | 702 | if (iwl_scan_cancel_timeout(priv, 100)) { |
39aadf8c | 703 | IWL_WARN(priv, "Aborted scan still in progress after 100ms\n"); |
fde3571f MA |
704 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); |
705 | return -EAGAIN; | |
706 | } | |
707 | ||
5b9f8cd3 | 708 | iwl_commit_rxon(priv); |
b481de9c ZY |
709 | |
710 | return 0; | |
711 | } | |
712 | ||
b481de9c ZY |
713 | /****************************************************************************** |
714 | * | |
715 | * Generic RX handler implementations | |
716 | * | |
717 | ******************************************************************************/ | |
885ba202 TW |
718 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
719 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 720 | { |
db11d634 | 721 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
885ba202 | 722 | struct iwl_alive_resp *palive; |
b481de9c ZY |
723 | struct delayed_work *pwork; |
724 | ||
725 | palive = &pkt->u.alive_frame; | |
726 | ||
727 | IWL_DEBUG_INFO("Alive ucode status 0x%08X revision " | |
728 | "0x%01X 0x%01X\n", | |
729 | palive->is_valid, palive->ver_type, | |
730 | palive->ver_subtype); | |
731 | ||
732 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
733 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
734 | memcpy(&priv->card_alive_init, | |
735 | &pkt->u.alive_frame, | |
885ba202 | 736 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
737 | pwork = &priv->init_alive_start; |
738 | } else { | |
739 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
740 | memcpy(&priv->card_alive, &pkt->u.alive_frame, | |
885ba202 | 741 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
742 | pwork = &priv->alive_start; |
743 | } | |
744 | ||
745 | /* We delay the ALIVE response by 5ms to | |
746 | * give the HW RF Kill time to activate... */ | |
747 | if (palive->is_valid == UCODE_VALID_OK) | |
748 | queue_delayed_work(priv->workqueue, pwork, | |
749 | msecs_to_jiffies(5)); | |
750 | else | |
39aadf8c | 751 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
752 | } |
753 | ||
5b9f8cd3 | 754 | static void iwl_rx_reply_error(struct iwl_priv *priv, |
a55360e4 | 755 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 756 | { |
db11d634 | 757 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c | 758 | |
15b1687c | 759 | IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) " |
b481de9c ZY |
760 | "seq 0x%04X ser 0x%08X\n", |
761 | le32_to_cpu(pkt->u.err_resp.error_type), | |
762 | get_cmd_string(pkt->u.err_resp.cmd_id), | |
763 | pkt->u.err_resp.cmd_id, | |
764 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
765 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
766 | } | |
767 | ||
5b9f8cd3 | 768 | static void iwl_rx_pm_sleep_notif(struct iwl_priv *priv, |
a55360e4 | 769 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 770 | { |
0a6857e7 | 771 | #ifdef CONFIG_IWLWIFI_DEBUG |
db11d634 | 772 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
2aa6ab86 | 773 | struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif); |
b481de9c ZY |
774 | IWL_DEBUG_RX("sleep mode: %d, src: %d\n", |
775 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); | |
776 | #endif | |
777 | } | |
778 | ||
5b9f8cd3 | 779 | static void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv, |
a55360e4 | 780 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 781 | { |
db11d634 | 782 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
783 | IWL_DEBUG_RADIO("Dumping %d bytes of unhandled " |
784 | "notification for %s:\n", | |
785 | le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd)); | |
bf403db8 | 786 | iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len)); |
b481de9c ZY |
787 | } |
788 | ||
5b9f8cd3 | 789 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 790 | { |
c79dd5b5 TW |
791 | struct iwl_priv *priv = |
792 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
793 | struct sk_buff *beacon; |
794 | ||
795 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 796 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
797 | |
798 | if (!beacon) { | |
15b1687c | 799 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
800 | return; |
801 | } | |
802 | ||
803 | mutex_lock(&priv->mutex); | |
804 | /* new beacon skb is allocated every time; dispose previous.*/ | |
805 | if (priv->ibss_beacon) | |
806 | dev_kfree_skb(priv->ibss_beacon); | |
807 | ||
808 | priv->ibss_beacon = beacon; | |
809 | mutex_unlock(&priv->mutex); | |
810 | ||
5b9f8cd3 | 811 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
812 | } |
813 | ||
4e39317d | 814 | /** |
5b9f8cd3 | 815 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
816 | * |
817 | * This callback is provided in order to send a statistics request. | |
818 | * | |
819 | * This timer function is continually reset to execute within | |
820 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
821 | * was received. We need to ensure we receive the statistics in order | |
822 | * to update the temperature used for calibrating the TXPOWER. | |
823 | */ | |
5b9f8cd3 | 824 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
825 | { |
826 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
827 | ||
828 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
829 | return; | |
830 | ||
61780ee3 MA |
831 | /* dont send host command if rf-kill is on */ |
832 | if (!iwl_is_ready_rf(priv)) | |
833 | return; | |
834 | ||
4e39317d EG |
835 | iwl_send_statistics_request(priv, CMD_ASYNC); |
836 | } | |
837 | ||
5b9f8cd3 | 838 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 839 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 840 | { |
0a6857e7 | 841 | #ifdef CONFIG_IWLWIFI_DEBUG |
db11d634 | 842 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
2aa6ab86 TW |
843 | struct iwl4965_beacon_notif *beacon = |
844 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 845 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c ZY |
846 | |
847 | IWL_DEBUG_RX("beacon status %x retries %d iss %d " | |
848 | "tsf %d %d rate %d\n", | |
25a6572c | 849 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
850 | beacon->beacon_notify_hdr.failure_frame, |
851 | le32_to_cpu(beacon->ibss_mgr_status), | |
852 | le32_to_cpu(beacon->high_tsf), | |
853 | le32_to_cpu(beacon->low_tsf), rate); | |
854 | #endif | |
855 | ||
05c914fe | 856 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
857 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
858 | queue_work(priv->workqueue, &priv->beacon_update); | |
859 | } | |
860 | ||
b481de9c ZY |
861 | /* Handle notification from uCode that card's power state is changing |
862 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 863 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 864 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 865 | { |
db11d634 | 866 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
867 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
868 | unsigned long status = priv->status; | |
869 | ||
870 | IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n", | |
871 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | |
872 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
873 | ||
874 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
875 | RF_CARD_DISABLED)) { | |
876 | ||
3395f6e9 | 877 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
878 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
879 | ||
3395f6e9 TW |
880 | if (!iwl_grab_nic_access(priv)) { |
881 | iwl_write_direct32( | |
b481de9c ZY |
882 | priv, HBUS_TARG_MBX_C, |
883 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
884 | ||
3395f6e9 | 885 | iwl_release_nic_access(priv); |
b481de9c ZY |
886 | } |
887 | ||
888 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 889 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 890 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
3395f6e9 TW |
891 | if (!iwl_grab_nic_access(priv)) { |
892 | iwl_write_direct32( | |
b481de9c ZY |
893 | priv, HBUS_TARG_MBX_C, |
894 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
895 | ||
3395f6e9 | 896 | iwl_release_nic_access(priv); |
b481de9c ZY |
897 | } |
898 | } | |
899 | ||
900 | if (flags & RF_CARD_DISABLED) { | |
3395f6e9 | 901 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c | 902 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
3395f6e9 TW |
903 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
904 | if (!iwl_grab_nic_access(priv)) | |
905 | iwl_release_nic_access(priv); | |
b481de9c ZY |
906 | } |
907 | } | |
908 | ||
909 | if (flags & HW_CARD_DISABLED) | |
910 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
911 | else | |
912 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
913 | ||
914 | ||
915 | if (flags & SW_CARD_DISABLED) | |
916 | set_bit(STATUS_RF_KILL_SW, &priv->status); | |
917 | else | |
918 | clear_bit(STATUS_RF_KILL_SW, &priv->status); | |
919 | ||
920 | if (!(flags & RXON_CARD_DISABLED)) | |
2a421b91 | 921 | iwl_scan_cancel(priv); |
b481de9c ZY |
922 | |
923 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
924 | test_bit(STATUS_RF_KILL_HW, &priv->status)) || | |
925 | (test_bit(STATUS_RF_KILL_SW, &status) != | |
926 | test_bit(STATUS_RF_KILL_SW, &priv->status))) | |
927 | queue_work(priv->workqueue, &priv->rf_kill); | |
928 | else | |
929 | wake_up_interruptible(&priv->wait_command_queue); | |
930 | } | |
931 | ||
5b9f8cd3 | 932 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b TW |
933 | { |
934 | int ret; | |
935 | unsigned long flags; | |
936 | ||
937 | spin_lock_irqsave(&priv->lock, flags); | |
938 | ret = iwl_grab_nic_access(priv); | |
939 | if (ret) | |
940 | goto err; | |
941 | ||
942 | if (src == IWL_PWR_SRC_VAUX) { | |
943 | u32 val; | |
e7b63581 | 944 | ret = pci_read_config_dword(priv->pci_dev, PCI_CFG_POWER_SOURCE, |
e2e3c57b TW |
945 | &val); |
946 | ||
947 | if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) | |
948 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
949 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
950 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
951 | } else { | |
952 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
953 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
954 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
955 | } | |
956 | ||
957 | iwl_release_nic_access(priv); | |
958 | err: | |
959 | spin_unlock_irqrestore(&priv->lock, flags); | |
960 | return ret; | |
961 | } | |
962 | ||
b481de9c | 963 | /** |
5b9f8cd3 | 964 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
965 | * |
966 | * Setup the RX handlers for each of the reply types sent from the uCode | |
967 | * to the host. | |
968 | * | |
969 | * This function chains into the hardware specific files for them to setup | |
970 | * any hardware specific handlers as well. | |
971 | */ | |
653fa4a0 | 972 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 973 | { |
885ba202 | 974 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
975 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
976 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
5b9f8cd3 | 977 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 978 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
979 | iwl_rx_pm_debug_statistics_notif; |
980 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 981 | |
9fbab516 BC |
982 | /* |
983 | * The same handler is used for both the REPLY to a discrete | |
984 | * statistics request from the host as well as for the periodic | |
985 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 986 | */ |
8f91aecb EG |
987 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics; |
988 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; | |
2a421b91 | 989 | |
21c339bf | 990 | iwl_setup_spectrum_handlers(priv); |
2a421b91 TW |
991 | iwl_setup_rx_scan_handlers(priv); |
992 | ||
37a44211 | 993 | /* status change handler */ |
5b9f8cd3 | 994 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 995 | |
c1354754 TW |
996 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
997 | iwl_rx_missed_beacon_notif; | |
37a44211 | 998 | /* Rx handlers */ |
1781a07f EG |
999 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy; |
1000 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx; | |
653fa4a0 EG |
1001 | /* block ack */ |
1002 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba; | |
9fbab516 | 1003 | /* Set up hardware specific Rx handlers */ |
d4789efe | 1004 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
1005 | } |
1006 | ||
b481de9c | 1007 | /** |
a55360e4 | 1008 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
1009 | * |
1010 | * Uses the priv->rx_handlers callback function array to invoke | |
1011 | * the appropriate handlers, including command responses, | |
1012 | * frame-received notifications, and other notifications. | |
1013 | */ | |
a55360e4 | 1014 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 1015 | { |
a55360e4 | 1016 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 1017 | struct iwl_rx_packet *pkt; |
a55360e4 | 1018 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
1019 | u32 r, i; |
1020 | int reclaim; | |
1021 | unsigned long flags; | |
5c0eef96 | 1022 | u8 fill_rx = 0; |
d68ab680 | 1023 | u32 count = 8; |
b481de9c | 1024 | |
6440adb5 BC |
1025 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
1026 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 1027 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
1028 | i = rxq->read; |
1029 | ||
1030 | /* Rx interrupt, but nothing sent from uCode */ | |
1031 | if (i == r) | |
f3d67999 | 1032 | IWL_DEBUG(IWL_DL_RX, "r = %d, i = %d\n", r, i); |
b481de9c | 1033 | |
a55360e4 | 1034 | if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2)) |
5c0eef96 MA |
1035 | fill_rx = 1; |
1036 | ||
b481de9c ZY |
1037 | while (i != r) { |
1038 | rxb = rxq->queue[i]; | |
1039 | ||
9fbab516 | 1040 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
1041 | * then a bug has been introduced in the queue refilling |
1042 | * routines -- catch it here */ | |
1043 | BUG_ON(rxb == NULL); | |
1044 | ||
1045 | rxq->queue[i] = NULL; | |
1046 | ||
e91af0af JB |
1047 | dma_sync_single_range_for_cpu( |
1048 | &priv->pci_dev->dev, rxb->real_dma_addr, | |
1049 | rxb->aligned_dma_addr - rxb->real_dma_addr, | |
1050 | priv->hw_params.rx_buf_size, | |
1051 | PCI_DMA_FROMDEVICE); | |
db11d634 | 1052 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
1053 | |
1054 | /* Reclaim a command buffer only if this packet is a response | |
1055 | * to a (driver-originated) command. | |
1056 | * If the packet (e.g. Rx frame) originated from uCode, | |
1057 | * there is no command buffer to reclaim. | |
1058 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1059 | * but apparently a few don't get set; catch them here. */ | |
1060 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1061 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 1062 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 1063 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 1064 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
1065 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
1066 | (pkt->hdr.cmd != REPLY_TX); | |
1067 | ||
1068 | /* Based on type of command response or notification, | |
1069 | * handle those that need handling via function in | |
5b9f8cd3 | 1070 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 1071 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
f3d67999 EK |
1072 | IWL_DEBUG(IWL_DL_RX, "r = %d, i = %d, %s, 0x%02x\n", r, |
1073 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
b481de9c ZY |
1074 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
1075 | } else { | |
1076 | /* No handling needed */ | |
f3d67999 | 1077 | IWL_DEBUG(IWL_DL_RX, |
b481de9c ZY |
1078 | "r %d i %d No handler needed for %s, 0x%02x\n", |
1079 | r, i, get_cmd_string(pkt->hdr.cmd), | |
1080 | pkt->hdr.cmd); | |
1081 | } | |
1082 | ||
1083 | if (reclaim) { | |
9fbab516 | 1084 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 1085 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
1086 | * as we reclaim the driver command queue */ |
1087 | if (rxb && rxb->skb) | |
17b88929 | 1088 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1089 | else |
39aadf8c | 1090 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1091 | } |
1092 | ||
1093 | /* For now we just don't re-use anything. We can tweak this | |
1094 | * later to try and re-use notification packets and SKBs that | |
1095 | * fail to Rx correctly */ | |
1096 | if (rxb->skb != NULL) { | |
1097 | priv->alloc_rxb_skb--; | |
1098 | dev_kfree_skb_any(rxb->skb); | |
1099 | rxb->skb = NULL; | |
1100 | } | |
1101 | ||
4018517a JB |
1102 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
1103 | priv->hw_params.rx_buf_size + 256, | |
9ee1ba47 | 1104 | PCI_DMA_FROMDEVICE); |
b481de9c ZY |
1105 | spin_lock_irqsave(&rxq->lock, flags); |
1106 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
1107 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1108 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
1109 | /* If there are a lot of unused frames, |
1110 | * restock the Rx queue so ucode wont assert. */ | |
1111 | if (fill_rx) { | |
1112 | count++; | |
1113 | if (count >= 8) { | |
1114 | priv->rxq.read = i; | |
f1bc4ac6 | 1115 | iwl_rx_queue_restock(priv); |
5c0eef96 MA |
1116 | count = 0; |
1117 | } | |
1118 | } | |
b481de9c ZY |
1119 | } |
1120 | ||
1121 | /* Backtrack one entry */ | |
1122 | priv->rxq.read = i; | |
a55360e4 TW |
1123 | iwl_rx_queue_restock(priv); |
1124 | } | |
a55360e4 | 1125 | |
0359facc MA |
1126 | /* call this function to flush any scheduled tasklet */ |
1127 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
1128 | { | |
a96a27f9 | 1129 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1130 | synchronize_irq(priv->pci_dev->irq); |
1131 | tasklet_kill(&priv->irq_tasklet); | |
1132 | } | |
1133 | ||
5b9f8cd3 | 1134 | static void iwl_error_recovery(struct iwl_priv *priv) |
b481de9c ZY |
1135 | { |
1136 | unsigned long flags; | |
1137 | ||
1138 | memcpy(&priv->staging_rxon, &priv->recovery_rxon, | |
1139 | sizeof(priv->staging_rxon)); | |
1140 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5b9f8cd3 | 1141 | iwl_commit_rxon(priv); |
b481de9c | 1142 | |
4f40e4d9 | 1143 | iwl_rxon_add_station(priv, priv->bssid, 1); |
b481de9c ZY |
1144 | |
1145 | spin_lock_irqsave(&priv->lock, flags); | |
1146 | priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id); | |
1147 | priv->error_recovering = 0; | |
1148 | spin_unlock_irqrestore(&priv->lock, flags); | |
1149 | } | |
1150 | ||
5b9f8cd3 | 1151 | static void iwl_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
1152 | { |
1153 | u32 inta, handled = 0; | |
1154 | u32 inta_fh; | |
1155 | unsigned long flags; | |
0a6857e7 | 1156 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1157 | u32 inta_mask; |
1158 | #endif | |
1159 | ||
1160 | spin_lock_irqsave(&priv->lock, flags); | |
1161 | ||
1162 | /* Ack/clear/reset pending uCode interrupts. | |
1163 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1164 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
1165 | inta = iwl_read32(priv, CSR_INT); |
1166 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1167 | |
1168 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1169 | * Any new interrupts that happen after this, either while we're | |
1170 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
1171 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1172 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1173 | |
0a6857e7 | 1174 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 1175 | if (priv->debug_level & IWL_DL_ISR) { |
9fbab516 | 1176 | /* just for debug */ |
3395f6e9 | 1177 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
b481de9c ZY |
1178 | IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
1179 | inta, inta_mask, inta_fh); | |
1180 | } | |
1181 | #endif | |
1182 | ||
1183 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
1184 | * atomic, make sure that inta covers all the interrupts that | |
1185 | * we've discovered, even if FH interrupt came in just after | |
1186 | * reading CSR_INT. */ | |
6f83eaa1 | 1187 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 1188 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1189 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
1190 | inta |= CSR_INT_BIT_FH_TX; |
1191 | ||
1192 | /* Now service all interrupt bits discovered above. */ | |
1193 | if (inta & CSR_INT_BIT_HW_ERR) { | |
15b1687c | 1194 | IWL_ERR(priv, "Microcode HW error detected. Restarting.\n"); |
b481de9c ZY |
1195 | |
1196 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 1197 | iwl_disable_interrupts(priv); |
b481de9c | 1198 | |
5b9f8cd3 | 1199 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1200 | |
1201 | handled |= CSR_INT_BIT_HW_ERR; | |
1202 | ||
1203 | spin_unlock_irqrestore(&priv->lock, flags); | |
1204 | ||
1205 | return; | |
1206 | } | |
1207 | ||
0a6857e7 | 1208 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 1209 | if (priv->debug_level & (IWL_DL_ISR)) { |
b481de9c | 1210 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
25c03d8e JP |
1211 | if (inta & CSR_INT_BIT_SCD) |
1212 | IWL_DEBUG_ISR("Scheduler finished to transmit " | |
1213 | "the frame/frames.\n"); | |
b481de9c ZY |
1214 | |
1215 | /* Alive notification via Rx interrupt will do the real work */ | |
1216 | if (inta & CSR_INT_BIT_ALIVE) | |
1217 | IWL_DEBUG_ISR("Alive interrupt\n"); | |
1218 | } | |
1219 | #endif | |
1220 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1221 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1222 | |
9fbab516 | 1223 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1224 | if (inta & CSR_INT_BIT_RF_KILL) { |
1225 | int hw_rf_kill = 0; | |
3395f6e9 | 1226 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1227 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1228 | hw_rf_kill = 1; | |
1229 | ||
f3d67999 | 1230 | IWL_DEBUG(IWL_DL_RF_KILL, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1231 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1232 | |
a9efa652 | 1233 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1234 | * the driver allows loading the ucode even if the radio |
1235 | * is killed. Hence update the killswitch state here. The | |
1236 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1237 | */ |
6cd0b1cb HS |
1238 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1239 | if (hw_rf_kill) | |
1240 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1241 | else | |
1242 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
1243 | queue_work(priv->workqueue, &priv->rf_kill); | |
edb34228 | 1244 | } |
b481de9c ZY |
1245 | |
1246 | handled |= CSR_INT_BIT_RF_KILL; | |
1247 | } | |
1248 | ||
9fbab516 | 1249 | /* Chip got too hot and stopped itself */ |
b481de9c | 1250 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1251 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
b481de9c ZY |
1252 | handled |= CSR_INT_BIT_CT_KILL; |
1253 | } | |
1254 | ||
1255 | /* Error detected by uCode */ | |
1256 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1257 | IWL_ERR(priv, "Microcode SW error detected. " |
1258 | " Restarting 0x%X.\n", inta); | |
5b9f8cd3 | 1259 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1260 | handled |= CSR_INT_BIT_SW_ERR; |
1261 | } | |
1262 | ||
1263 | /* uCode wakes up after power-down sleep */ | |
1264 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1265 | IWL_DEBUG_ISR("Wakeup interrupt\n"); | |
a55360e4 | 1266 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
babcebfa TW |
1267 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1268 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1269 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1270 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1271 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1272 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c ZY |
1273 | |
1274 | handled |= CSR_INT_BIT_WAKEUP; | |
1275 | } | |
1276 | ||
1277 | /* All uCode command responses, including Tx command responses, | |
1278 | * Rx "responses" (frame-received notification), and other | |
1279 | * notifications from uCode come through here*/ | |
1280 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1281 | iwl_rx_handle(priv); |
b481de9c ZY |
1282 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1283 | } | |
1284 | ||
1285 | if (inta & CSR_INT_BIT_FH_TX) { | |
1286 | IWL_DEBUG_ISR("Tx interrupt\n"); | |
1287 | handled |= CSR_INT_BIT_FH_TX; | |
dbb983b7 RR |
1288 | /* FH finished to write, send event */ |
1289 | priv->ucode_write_complete = 1; | |
1290 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1291 | } |
1292 | ||
1293 | if (inta & ~handled) | |
15b1687c | 1294 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
b481de9c ZY |
1295 | |
1296 | if (inta & ~CSR_INI_SET_MASK) { | |
39aadf8c | 1297 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
b481de9c | 1298 | inta & ~CSR_INI_SET_MASK); |
39aadf8c | 1299 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1300 | } |
1301 | ||
1302 | /* Re-enable all interrupts */ | |
0359facc MA |
1303 | /* only Re-enable if diabled by irq */ |
1304 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1305 | iwl_enable_interrupts(priv); |
b481de9c | 1306 | |
0a6857e7 | 1307 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 1308 | if (priv->debug_level & (IWL_DL_ISR)) { |
3395f6e9 TW |
1309 | inta = iwl_read32(priv, CSR_INT); |
1310 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1311 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
1312 | IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
1313 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
1314 | } | |
1315 | #endif | |
1316 | spin_unlock_irqrestore(&priv->lock, flags); | |
1317 | } | |
1318 | ||
5b9f8cd3 | 1319 | static irqreturn_t iwl_isr(int irq, void *data) |
b481de9c | 1320 | { |
c79dd5b5 | 1321 | struct iwl_priv *priv = data; |
b481de9c ZY |
1322 | u32 inta, inta_mask; |
1323 | u32 inta_fh; | |
1324 | if (!priv) | |
1325 | return IRQ_NONE; | |
1326 | ||
1327 | spin_lock(&priv->lock); | |
1328 | ||
1329 | /* Disable (but don't clear!) interrupts here to avoid | |
1330 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
1331 | * If we have something to service, the tasklet will re-enable ints. | |
1332 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
3395f6e9 TW |
1333 | inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */ |
1334 | iwl_write32(priv, CSR_INT_MASK, 0x00000000); | |
b481de9c ZY |
1335 | |
1336 | /* Discover which interrupts are active/pending */ | |
3395f6e9 TW |
1337 | inta = iwl_read32(priv, CSR_INT); |
1338 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
b481de9c ZY |
1339 | |
1340 | /* Ignore interrupt if there's nothing in NIC to service. | |
1341 | * This may be due to IRQ shared with another device, | |
1342 | * or due to sporadic interrupts thrown from our NIC. */ | |
1343 | if (!inta && !inta_fh) { | |
1344 | IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); | |
1345 | goto none; | |
1346 | } | |
1347 | ||
1348 | if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) { | |
66fbb541 ON |
1349 | /* Hardware disappeared. It might have already raised |
1350 | * an interrupt */ | |
39aadf8c | 1351 | IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta); |
66fbb541 | 1352 | goto unplugged; |
b481de9c ZY |
1353 | } |
1354 | ||
1355 | IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | |
1356 | inta, inta_mask, inta_fh); | |
1357 | ||
25c03d8e JP |
1358 | inta &= ~CSR_INT_BIT_SCD; |
1359 | ||
5b9f8cd3 | 1360 | /* iwl_irq_tasklet() will service interrupts and re-enable them */ |
25c03d8e JP |
1361 | if (likely(inta || inta_fh)) |
1362 | tasklet_schedule(&priv->irq_tasklet); | |
b481de9c | 1363 | |
66fbb541 ON |
1364 | unplugged: |
1365 | spin_unlock(&priv->lock); | |
b481de9c ZY |
1366 | return IRQ_HANDLED; |
1367 | ||
1368 | none: | |
1369 | /* re-enable interrupts here since we don't have anything to service. */ | |
0359facc MA |
1370 | /* only Re-enable if diabled by irq */ |
1371 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1372 | iwl_enable_interrupts(priv); |
b481de9c ZY |
1373 | spin_unlock(&priv->lock); |
1374 | return IRQ_NONE; | |
1375 | } | |
1376 | ||
b481de9c ZY |
1377 | /****************************************************************************** |
1378 | * | |
1379 | * uCode download functions | |
1380 | * | |
1381 | ******************************************************************************/ | |
1382 | ||
5b9f8cd3 | 1383 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1384 | { |
98c92211 TW |
1385 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1386 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1387 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1388 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1389 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1390 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1391 | } |
1392 | ||
5b9f8cd3 | 1393 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1394 | { |
1395 | /* Remove all resets to allow NIC to operate */ | |
1396 | iwl_write32(priv, CSR_RESET, 0); | |
1397 | } | |
1398 | ||
1399 | ||
b481de9c | 1400 | /** |
5b9f8cd3 | 1401 | * iwl_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
1402 | * |
1403 | * Copy into buffers for card to fetch via bus-mastering | |
1404 | */ | |
5b9f8cd3 | 1405 | static int iwl_read_ucode(struct iwl_priv *priv) |
b481de9c | 1406 | { |
14b3d338 | 1407 | struct iwl_ucode *ucode; |
a0987a8d | 1408 | int ret = -EINVAL, index; |
b481de9c | 1409 | const struct firmware *ucode_raw; |
a0987a8d RC |
1410 | const char *name_pre = priv->cfg->fw_name_pre; |
1411 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
1412 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
1413 | char buf[25]; | |
b481de9c ZY |
1414 | u8 *src; |
1415 | size_t len; | |
a0987a8d | 1416 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
1417 | |
1418 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
1419 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
1420 | for (index = api_max; index >= api_min; index--) { |
1421 | sprintf(buf, "%s%d%s", name_pre, index, ".ucode"); | |
1422 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
1423 | if (ret < 0) { | |
15b1687c | 1424 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
1425 | buf, ret); |
1426 | if (ret == -ENOENT) | |
1427 | continue; | |
1428 | else | |
1429 | goto error; | |
1430 | } else { | |
1431 | if (index < api_max) | |
15b1687c WT |
1432 | IWL_ERR(priv, "Loaded firmware %s, " |
1433 | "which is deprecated. " | |
1434 | "Please use API v%u instead.\n", | |
a0987a8d | 1435 | buf, api_max); |
15b1687c | 1436 | |
a0987a8d RC |
1437 | IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n", |
1438 | buf, ucode_raw->size); | |
1439 | break; | |
1440 | } | |
b481de9c ZY |
1441 | } |
1442 | ||
a0987a8d RC |
1443 | if (ret < 0) |
1444 | goto error; | |
b481de9c ZY |
1445 | |
1446 | /* Make sure that we got at least our header! */ | |
1447 | if (ucode_raw->size < sizeof(*ucode)) { | |
15b1687c | 1448 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 1449 | ret = -EINVAL; |
b481de9c ZY |
1450 | goto err_release; |
1451 | } | |
1452 | ||
1453 | /* Data from ucode file: header followed by uCode images */ | |
1454 | ucode = (void *)ucode_raw->data; | |
1455 | ||
c02b3acd | 1456 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 1457 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
b481de9c ZY |
1458 | inst_size = le32_to_cpu(ucode->inst_size); |
1459 | data_size = le32_to_cpu(ucode->data_size); | |
1460 | init_size = le32_to_cpu(ucode->init_size); | |
1461 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
1462 | boot_size = le32_to_cpu(ucode->boot_size); | |
1463 | ||
a0987a8d RC |
1464 | /* api_ver should match the api version forming part of the |
1465 | * firmware filename ... but we don't check for that and only rely | |
1466 | * on the API version read from firware header from here on forward */ | |
1467 | ||
1468 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 1469 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1470 | "Driver supports v%u, firmware is v%u.\n", |
1471 | api_max, api_ver); | |
1472 | priv->ucode_ver = 0; | |
1473 | ret = -EINVAL; | |
1474 | goto err_release; | |
1475 | } | |
1476 | if (api_ver != api_max) | |
978785a3 | 1477 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1478 | "got v%u. New firmware can be obtained " |
1479 | "from http://www.intellinuxwireless.org.\n", | |
1480 | api_max, api_ver); | |
1481 | ||
978785a3 TW |
1482 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
1483 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1484 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1485 | IWL_UCODE_API(priv->ucode_ver), | |
1486 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d RC |
1487 | |
1488 | IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n", | |
1489 | priv->ucode_ver); | |
b481de9c ZY |
1490 | IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", |
1491 | inst_size); | |
1492 | IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", | |
1493 | data_size); | |
1494 | IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", | |
1495 | init_size); | |
1496 | IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", | |
1497 | init_data_size); | |
1498 | IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", | |
1499 | boot_size); | |
1500 | ||
1501 | /* Verify size of file vs. image size info in file's header */ | |
1502 | if (ucode_raw->size < sizeof(*ucode) + | |
1503 | inst_size + data_size + init_size + | |
1504 | init_data_size + boot_size) { | |
1505 | ||
1506 | IWL_DEBUG_INFO("uCode file size %d too small\n", | |
1507 | (int)ucode_raw->size); | |
90e759d1 | 1508 | ret = -EINVAL; |
b481de9c ZY |
1509 | goto err_release; |
1510 | } | |
1511 | ||
1512 | /* Verify that uCode images will fit in card's SRAM */ | |
099b40b7 | 1513 | if (inst_size > priv->hw_params.max_inst_size) { |
90e759d1 TW |
1514 | IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n", |
1515 | inst_size); | |
1516 | ret = -EINVAL; | |
b481de9c ZY |
1517 | goto err_release; |
1518 | } | |
1519 | ||
099b40b7 | 1520 | if (data_size > priv->hw_params.max_data_size) { |
90e759d1 TW |
1521 | IWL_DEBUG_INFO("uCode data len %d too large to fit in\n", |
1522 | data_size); | |
1523 | ret = -EINVAL; | |
b481de9c ZY |
1524 | goto err_release; |
1525 | } | |
099b40b7 | 1526 | if (init_size > priv->hw_params.max_inst_size) { |
b481de9c | 1527 | IWL_DEBUG_INFO |
90e759d1 TW |
1528 | ("uCode init instr len %d too large to fit in\n", |
1529 | init_size); | |
1530 | ret = -EINVAL; | |
b481de9c ZY |
1531 | goto err_release; |
1532 | } | |
099b40b7 | 1533 | if (init_data_size > priv->hw_params.max_data_size) { |
b481de9c | 1534 | IWL_DEBUG_INFO |
90e759d1 TW |
1535 | ("uCode init data len %d too large to fit in\n", |
1536 | init_data_size); | |
1537 | ret = -EINVAL; | |
b481de9c ZY |
1538 | goto err_release; |
1539 | } | |
099b40b7 | 1540 | if (boot_size > priv->hw_params.max_bsm_size) { |
b481de9c | 1541 | IWL_DEBUG_INFO |
90e759d1 TW |
1542 | ("uCode boot instr len %d too large to fit in\n", |
1543 | boot_size); | |
1544 | ret = -EINVAL; | |
b481de9c ZY |
1545 | goto err_release; |
1546 | } | |
1547 | ||
1548 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1549 | ||
1550 | /* Runtime instructions and 2 copies of data: | |
1551 | * 1) unmodified from disk | |
1552 | * 2) backup cache for save/restore during power-downs */ | |
1553 | priv->ucode_code.len = inst_size; | |
98c92211 | 1554 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
1555 | |
1556 | priv->ucode_data.len = data_size; | |
98c92211 | 1557 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
1558 | |
1559 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 1560 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1561 | |
1f304e4e ZY |
1562 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1563 | !priv->ucode_data_backup.v_addr) | |
1564 | goto err_pci_alloc; | |
1565 | ||
b481de9c | 1566 | /* Initialization instructions and data */ |
90e759d1 TW |
1567 | if (init_size && init_data_size) { |
1568 | priv->ucode_init.len = init_size; | |
98c92211 | 1569 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
1570 | |
1571 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 1572 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1573 | |
1574 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1575 | goto err_pci_alloc; | |
1576 | } | |
b481de9c ZY |
1577 | |
1578 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
1579 | if (boot_size) { |
1580 | priv->ucode_boot.len = boot_size; | |
98c92211 | 1581 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1582 | |
90e759d1 TW |
1583 | if (!priv->ucode_boot.v_addr) |
1584 | goto err_pci_alloc; | |
1585 | } | |
b481de9c ZY |
1586 | |
1587 | /* Copy images into buffers for card's bus-master reads ... */ | |
1588 | ||
1589 | /* Runtime instructions (first block of data in file) */ | |
1590 | src = &ucode->data[0]; | |
1591 | len = priv->ucode_code.len; | |
90e759d1 | 1592 | IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c ZY |
1593 | memcpy(priv->ucode_code.v_addr, src, len); |
1594 | IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", | |
1595 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); | |
1596 | ||
1597 | /* Runtime data (2nd block) | |
5b9f8cd3 | 1598 | * NOTE: Copy into backup buffer will be done in iwl_up() */ |
b481de9c ZY |
1599 | src = &ucode->data[inst_size]; |
1600 | len = priv->ucode_data.len; | |
90e759d1 | 1601 | IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
1602 | memcpy(priv->ucode_data.v_addr, src, len); |
1603 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
1604 | ||
1605 | /* Initialization instructions (3rd block) */ | |
1606 | if (init_size) { | |
1607 | src = &ucode->data[inst_size + data_size]; | |
1608 | len = priv->ucode_init.len; | |
90e759d1 TW |
1609 | IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n", |
1610 | len); | |
b481de9c ZY |
1611 | memcpy(priv->ucode_init.v_addr, src, len); |
1612 | } | |
1613 | ||
1614 | /* Initialization data (4th block) */ | |
1615 | if (init_data_size) { | |
1616 | src = &ucode->data[inst_size + data_size + init_size]; | |
1617 | len = priv->ucode_init_data.len; | |
90e759d1 TW |
1618 | IWL_DEBUG_INFO("Copying (but not loading) init data len %Zd\n", |
1619 | len); | |
b481de9c ZY |
1620 | memcpy(priv->ucode_init_data.v_addr, src, len); |
1621 | } | |
1622 | ||
1623 | /* Bootstrap instructions (5th block) */ | |
1624 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
1625 | len = priv->ucode_boot.len; | |
90e759d1 | 1626 | IWL_DEBUG_INFO("Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
1627 | memcpy(priv->ucode_boot.v_addr, src, len); |
1628 | ||
1629 | /* We have our copies now, allow OS release its copies */ | |
1630 | release_firmware(ucode_raw); | |
1631 | return 0; | |
1632 | ||
1633 | err_pci_alloc: | |
15b1687c | 1634 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 1635 | ret = -ENOMEM; |
5b9f8cd3 | 1636 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
1637 | |
1638 | err_release: | |
1639 | release_firmware(ucode_raw); | |
1640 | ||
1641 | error: | |
90e759d1 | 1642 | return ret; |
b481de9c ZY |
1643 | } |
1644 | ||
ada17513 MA |
1645 | /* temporary */ |
1646 | static int iwl_mac_beacon_update(struct ieee80211_hw *hw, | |
1647 | struct sk_buff *skb); | |
1648 | ||
b481de9c | 1649 | /** |
4a4a9e81 | 1650 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 1651 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 1652 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 1653 | */ |
4a4a9e81 | 1654 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 1655 | { |
57aab75a | 1656 | int ret = 0; |
b481de9c ZY |
1657 | |
1658 | IWL_DEBUG_INFO("Runtime Alive received.\n"); | |
1659 | ||
1660 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
1661 | /* We had an error bringing up the hardware, so take it | |
1662 | * all the way back down so we can try again */ | |
1663 | IWL_DEBUG_INFO("Alive failed.\n"); | |
1664 | goto restart; | |
1665 | } | |
1666 | ||
1667 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
1668 | * This is a paranoid check, because we would not have gotten the | |
1669 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 1670 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
1671 | /* Runtime instruction load was bad; |
1672 | * take it all the way back down so we can try again */ | |
1673 | IWL_DEBUG_INFO("Bad runtime uCode load.\n"); | |
1674 | goto restart; | |
1675 | } | |
1676 | ||
37deb2a0 | 1677 | iwl_clear_stations_table(priv); |
57aab75a TW |
1678 | ret = priv->cfg->ops->lib->alive_notify(priv); |
1679 | if (ret) { | |
39aadf8c WT |
1680 | IWL_WARN(priv, |
1681 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
1682 | goto restart; |
1683 | } | |
1684 | ||
5b9f8cd3 | 1685 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
1686 | set_bit(STATUS_ALIVE, &priv->status); |
1687 | ||
fee1247a | 1688 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
1689 | return; |
1690 | ||
36d6825b | 1691 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
1692 | |
1693 | priv->active_rate = priv->rates_mask; | |
1694 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
1695 | ||
3109ece1 | 1696 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
1697 | struct iwl_rxon_cmd *active_rxon = |
1698 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
b481de9c ZY |
1699 | |
1700 | memcpy(&priv->staging_rxon, &priv->active_rxon, | |
1701 | sizeof(priv->staging_rxon)); | |
1702 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
1703 | } else { | |
1704 | /* Initialize our rx_config data */ | |
5b9f8cd3 | 1705 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
8ccde88a | 1706 | iwl_set_rxon_chain(priv); |
b481de9c ZY |
1707 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1708 | } | |
1709 | ||
9fbab516 | 1710 | /* Configure Bluetooth device coexistence support */ |
5b9f8cd3 | 1711 | iwl_send_bt_config(priv); |
b481de9c | 1712 | |
4a4a9e81 TW |
1713 | iwl_reset_run_time_calib(priv); |
1714 | ||
b481de9c | 1715 | /* Configure the adapter for unassociated operation */ |
5b9f8cd3 | 1716 | iwl_commit_rxon(priv); |
b481de9c ZY |
1717 | |
1718 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 1719 | iwl_rf_kill_ct_config(priv); |
5a66926a | 1720 | |
fe00b5a5 RC |
1721 | iwl_leds_register(priv); |
1722 | ||
b481de9c | 1723 | IWL_DEBUG_INFO("ALIVE processing complete.\n"); |
a9f46786 | 1724 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 1725 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c ZY |
1726 | |
1727 | if (priv->error_recovering) | |
5b9f8cd3 | 1728 | iwl_error_recovery(priv); |
b481de9c | 1729 | |
58d0f361 | 1730 | iwl_power_update_mode(priv, 1); |
c46fbefa | 1731 | |
ada17513 MA |
1732 | /* reassociate for ADHOC mode */ |
1733 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
1734 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
1735 | priv->vif); | |
1736 | if (beacon) | |
1737 | iwl_mac_beacon_update(priv->hw, beacon); | |
1738 | } | |
1739 | ||
1740 | ||
c46fbefa | 1741 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
5b9f8cd3 | 1742 | iwl_set_mode(priv, priv->iw_mode); |
c46fbefa | 1743 | |
b481de9c ZY |
1744 | return; |
1745 | ||
1746 | restart: | |
1747 | queue_work(priv->workqueue, &priv->restart); | |
1748 | } | |
1749 | ||
4e39317d | 1750 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 1751 | |
5b9f8cd3 | 1752 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1753 | { |
1754 | unsigned long flags; | |
1755 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c ZY |
1756 | |
1757 | IWL_DEBUG_INFO(DRV_NAME " is going down\n"); | |
1758 | ||
b481de9c ZY |
1759 | if (!exit_pending) |
1760 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
1761 | ||
ab53d8af MA |
1762 | iwl_leds_unregister(priv); |
1763 | ||
37deb2a0 | 1764 | iwl_clear_stations_table(priv); |
b481de9c ZY |
1765 | |
1766 | /* Unblock any waiting calls */ | |
1767 | wake_up_interruptible_all(&priv->wait_command_queue); | |
1768 | ||
b481de9c ZY |
1769 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
1770 | * exiting the module */ | |
1771 | if (!exit_pending) | |
1772 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
1773 | ||
1774 | /* stop and reset the on-board processor */ | |
3395f6e9 | 1775 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
1776 | |
1777 | /* tell the device to stop sending interrupts */ | |
0359facc | 1778 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 1779 | iwl_disable_interrupts(priv); |
0359facc MA |
1780 | spin_unlock_irqrestore(&priv->lock, flags); |
1781 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
1782 | |
1783 | if (priv->mac80211_registered) | |
1784 | ieee80211_stop_queues(priv->hw); | |
1785 | ||
5b9f8cd3 | 1786 | /* If we have not previously called iwl_init() then |
b481de9c | 1787 | * clear all bits but the RF Kill and SUSPEND bits and return */ |
fee1247a | 1788 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
1789 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1790 | STATUS_RF_KILL_HW | | |
1791 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
1792 | STATUS_RF_KILL_SW | | |
9788864e RC |
1793 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1794 | STATUS_GEO_CONFIGURED | | |
b481de9c | 1795 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
052ec3f1 MA |
1796 | STATUS_IN_SUSPEND | |
1797 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
1798 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
1799 | goto exit; |
1800 | } | |
1801 | ||
1802 | /* ...otherwise clear out all the status bits but the RF Kill and | |
1803 | * SUSPEND bits and continue taking the NIC down. */ | |
1804 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << | |
1805 | STATUS_RF_KILL_HW | | |
1806 | test_bit(STATUS_RF_KILL_SW, &priv->status) << | |
1807 | STATUS_RF_KILL_SW | | |
9788864e RC |
1808 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1809 | STATUS_GEO_CONFIGURED | | |
b481de9c ZY |
1810 | test_bit(STATUS_IN_SUSPEND, &priv->status) << |
1811 | STATUS_IN_SUSPEND | | |
1812 | test_bit(STATUS_FW_ERROR, &priv->status) << | |
052ec3f1 MA |
1813 | STATUS_FW_ERROR | |
1814 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
1815 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
1816 | |
1817 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 | 1818 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 1819 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
1820 | spin_unlock_irqrestore(&priv->lock, flags); |
1821 | ||
da1bc453 | 1822 | iwl_txq_ctx_stop(priv); |
b3bbacb7 | 1823 | iwl_rxq_stop(priv); |
b481de9c ZY |
1824 | |
1825 | spin_lock_irqsave(&priv->lock, flags); | |
3395f6e9 TW |
1826 | if (!iwl_grab_nic_access(priv)) { |
1827 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | |
b481de9c | 1828 | APMG_CLK_VAL_DMA_CLK_RQT); |
3395f6e9 | 1829 | iwl_release_nic_access(priv); |
b481de9c ZY |
1830 | } |
1831 | spin_unlock_irqrestore(&priv->lock, flags); | |
1832 | ||
1833 | udelay(5); | |
1834 | ||
7f066108 | 1835 | /* FIXME: apm_ops.suspend(priv) */ |
d535311e GG |
1836 | if (exit_pending || test_bit(STATUS_IN_SUSPEND, &priv->status)) |
1837 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
1838 | else | |
1839 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
b481de9c | 1840 | exit: |
885ba202 | 1841 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
1842 | |
1843 | if (priv->ibss_beacon) | |
1844 | dev_kfree_skb(priv->ibss_beacon); | |
1845 | priv->ibss_beacon = NULL; | |
1846 | ||
1847 | /* clear out any free frames */ | |
fcab423d | 1848 | iwl_clear_free_frames(priv); |
b481de9c ZY |
1849 | } |
1850 | ||
5b9f8cd3 | 1851 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1852 | { |
1853 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1854 | __iwl_down(priv); |
b481de9c | 1855 | mutex_unlock(&priv->mutex); |
b24d22b1 | 1856 | |
4e39317d | 1857 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
1858 | } |
1859 | ||
1860 | #define MAX_HW_RESTARTS 5 | |
1861 | ||
5b9f8cd3 | 1862 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 1863 | { |
57aab75a TW |
1864 | int i; |
1865 | int ret; | |
b481de9c ZY |
1866 | |
1867 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 1868 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
1869 | return -EIO; |
1870 | } | |
1871 | ||
e903fbd4 | 1872 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 1873 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
1874 | return -EIO; |
1875 | } | |
1876 | ||
e655b9f0 | 1877 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 1878 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 1879 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1880 | else |
e655b9f0 | 1881 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1882 | |
c1842d61 | 1883 | if (iwl_is_rfkill(priv)) { |
5b9f8cd3 | 1884 | iwl_enable_interrupts(priv); |
39aadf8c | 1885 | IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n", |
3bff19c2 | 1886 | test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW"); |
c1842d61 | 1887 | return 0; |
b481de9c ZY |
1888 | } |
1889 | ||
3395f6e9 | 1890 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 1891 | |
1053d35f | 1892 | ret = iwl_hw_nic_init(priv); |
57aab75a | 1893 | if (ret) { |
15b1687c | 1894 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 1895 | return ret; |
b481de9c ZY |
1896 | } |
1897 | ||
1898 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
1899 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1900 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
1901 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1902 | ||
1903 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 1904 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 1905 | iwl_enable_interrupts(priv); |
b481de9c ZY |
1906 | |
1907 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
1908 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1909 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
1910 | |
1911 | /* Copy original ucode data image from disk into backup cache. | |
1912 | * This will be used to initialize the on-board processor's | |
1913 | * data SRAM for a clean start when the runtime program first loads. */ | |
1914 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 1915 | priv->ucode_data.len); |
b481de9c | 1916 | |
b481de9c ZY |
1917 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
1918 | ||
37deb2a0 | 1919 | iwl_clear_stations_table(priv); |
b481de9c ZY |
1920 | |
1921 | /* load bootstrap state machine, | |
1922 | * load bootstrap program into processor's memory, | |
1923 | * prepare to load the "initialize" uCode */ | |
57aab75a | 1924 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 1925 | |
57aab75a | 1926 | if (ret) { |
15b1687c WT |
1927 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
1928 | ret); | |
b481de9c ZY |
1929 | continue; |
1930 | } | |
1931 | ||
f3d5b45b EG |
1932 | /* Clear out the uCode error bit if it is set */ |
1933 | clear_bit(STATUS_FW_ERROR, &priv->status); | |
1934 | ||
b481de9c | 1935 | /* start card; "initialize" will load runtime ucode */ |
5b9f8cd3 | 1936 | iwl_nic_start(priv); |
b481de9c | 1937 | |
b481de9c ZY |
1938 | IWL_DEBUG_INFO(DRV_NAME " is coming up\n"); |
1939 | ||
1940 | return 0; | |
1941 | } | |
1942 | ||
1943 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 1944 | __iwl_down(priv); |
64e72c3e | 1945 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
1946 | |
1947 | /* tried to restart and config the device for as long as our | |
1948 | * patience could withstand */ | |
15b1687c | 1949 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
1950 | return -EIO; |
1951 | } | |
1952 | ||
1953 | ||
1954 | /***************************************************************************** | |
1955 | * | |
1956 | * Workqueue callbacks | |
1957 | * | |
1958 | *****************************************************************************/ | |
1959 | ||
4a4a9e81 | 1960 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 1961 | { |
c79dd5b5 TW |
1962 | struct iwl_priv *priv = |
1963 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
1964 | |
1965 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1966 | return; | |
1967 | ||
1968 | mutex_lock(&priv->mutex); | |
f3ccc08c | 1969 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
1970 | mutex_unlock(&priv->mutex); |
1971 | } | |
1972 | ||
4a4a9e81 | 1973 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 1974 | { |
c79dd5b5 TW |
1975 | struct iwl_priv *priv = |
1976 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
1977 | |
1978 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1979 | return; | |
1980 | ||
1981 | mutex_lock(&priv->mutex); | |
4a4a9e81 | 1982 | iwl_alive_start(priv); |
b481de9c ZY |
1983 | mutex_unlock(&priv->mutex); |
1984 | } | |
1985 | ||
16e727e8 EG |
1986 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
1987 | { | |
1988 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
1989 | run_time_calib_work); | |
1990 | ||
1991 | mutex_lock(&priv->mutex); | |
1992 | ||
1993 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
1994 | test_bit(STATUS_SCANNING, &priv->status)) { | |
1995 | mutex_unlock(&priv->mutex); | |
1996 | return; | |
1997 | } | |
1998 | ||
1999 | if (priv->start_calib) { | |
2000 | iwl_chain_noise_calibration(priv, &priv->statistics); | |
2001 | ||
2002 | iwl_sensitivity_calibration(priv, &priv->statistics); | |
2003 | } | |
2004 | ||
2005 | mutex_unlock(&priv->mutex); | |
2006 | return; | |
2007 | } | |
2008 | ||
5b9f8cd3 | 2009 | static void iwl_bg_up(struct work_struct *data) |
b481de9c | 2010 | { |
c79dd5b5 | 2011 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
2012 | |
2013 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2014 | return; | |
2015 | ||
2016 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2017 | __iwl_up(priv); |
b481de9c | 2018 | mutex_unlock(&priv->mutex); |
80fcc9e2 | 2019 | iwl_rfkill_set_hw_state(priv); |
b481de9c ZY |
2020 | } |
2021 | ||
5b9f8cd3 | 2022 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2023 | { |
c79dd5b5 | 2024 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2025 | |
2026 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2027 | return; | |
2028 | ||
5b9f8cd3 | 2029 | iwl_down(priv); |
b481de9c ZY |
2030 | queue_work(priv->workqueue, &priv->up); |
2031 | } | |
2032 | ||
5b9f8cd3 | 2033 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2034 | { |
c79dd5b5 TW |
2035 | struct iwl_priv *priv = |
2036 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2037 | |
2038 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2039 | return; | |
2040 | ||
2041 | mutex_lock(&priv->mutex); | |
a55360e4 | 2042 | iwl_rx_replenish(priv); |
b481de9c ZY |
2043 | mutex_unlock(&priv->mutex); |
2044 | } | |
2045 | ||
7878a5a4 MA |
2046 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
2047 | ||
5b9f8cd3 | 2048 | static void iwl_post_associate(struct iwl_priv *priv) |
b481de9c | 2049 | { |
b481de9c | 2050 | struct ieee80211_conf *conf = NULL; |
857485c0 | 2051 | int ret = 0; |
1ff50bda | 2052 | unsigned long flags; |
b481de9c | 2053 | |
05c914fe | 2054 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 2055 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
2056 | return; |
2057 | } | |
2058 | ||
e174961c JB |
2059 | IWL_DEBUG_ASSOC("Associated as %d to: %pM\n", |
2060 | priv->assoc_id, priv->active_rxon.bssid_addr); | |
b481de9c ZY |
2061 | |
2062 | ||
2063 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2064 | return; | |
2065 | ||
b481de9c | 2066 | |
508e32e1 | 2067 | if (!priv->vif || !priv->is_open) |
948c171c | 2068 | return; |
508e32e1 | 2069 | |
c90a74ba | 2070 | iwl_power_cancel_timeout(priv); |
2a421b91 | 2071 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 2072 | |
b481de9c ZY |
2073 | conf = ieee80211_get_hw_conf(priv->hw); |
2074 | ||
2075 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5b9f8cd3 | 2076 | iwl_commit_rxon(priv); |
b481de9c | 2077 | |
3195c1f3 | 2078 | iwl_setup_rxon_timing(priv); |
857485c0 | 2079 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2080 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2081 | if (ret) |
39aadf8c | 2082 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2083 | "Attempting to continue.\n"); |
2084 | ||
2085 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2086 | ||
42eb7c64 | 2087 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 2088 | |
c7de35cd | 2089 | iwl_set_rxon_chain(priv); |
b481de9c ZY |
2090 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
2091 | ||
2092 | IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n", | |
2093 | priv->assoc_id, priv->beacon_int); | |
2094 | ||
2095 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2096 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2097 | else | |
2098 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2099 | ||
2100 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2101 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2102 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2103 | else | |
2104 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2105 | ||
05c914fe | 2106 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2107 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
2108 | ||
2109 | } | |
2110 | ||
5b9f8cd3 | 2111 | iwl_commit_rxon(priv); |
b481de9c ZY |
2112 | |
2113 | switch (priv->iw_mode) { | |
05c914fe | 2114 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2115 | break; |
2116 | ||
05c914fe | 2117 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 2118 | |
c46fbefa AK |
2119 | /* assume default assoc id */ |
2120 | priv->assoc_id = 1; | |
b481de9c | 2121 | |
4f40e4d9 | 2122 | iwl_rxon_add_station(priv, priv->bssid, 0); |
5b9f8cd3 | 2123 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2124 | |
2125 | break; | |
2126 | ||
2127 | default: | |
15b1687c | 2128 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 2129 | __func__, priv->iw_mode); |
b481de9c ZY |
2130 | break; |
2131 | } | |
2132 | ||
05c914fe | 2133 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2134 | priv->assoc_station_added = 1; |
2135 | ||
1ff50bda EG |
2136 | spin_lock_irqsave(&priv->lock, flags); |
2137 | iwl_activate_qos(priv, 0); | |
2138 | spin_unlock_irqrestore(&priv->lock, flags); | |
292ae174 | 2139 | |
04816448 GE |
2140 | /* the chain noise calibration will enabled PM upon completion |
2141 | * If chain noise has already been run, then we need to enable | |
2142 | * power management here */ | |
2143 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
2144 | iwl_power_enable_management(priv); | |
c90a74ba EG |
2145 | |
2146 | /* Enable Rx differential gain and sensitivity calibrations */ | |
2147 | iwl_chain_noise_reset(priv); | |
2148 | priv->start_calib = 1; | |
2149 | ||
508e32e1 RC |
2150 | } |
2151 | ||
b481de9c ZY |
2152 | /***************************************************************************** |
2153 | * | |
2154 | * mac80211 entry point functions | |
2155 | * | |
2156 | *****************************************************************************/ | |
2157 | ||
154b25ce | 2158 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2159 | |
5b9f8cd3 | 2160 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2161 | { |
c79dd5b5 | 2162 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2163 | int ret; |
b481de9c ZY |
2164 | |
2165 | IWL_DEBUG_MAC80211("enter\n"); | |
2166 | ||
2167 | /* we should be verifying the device is ready to be opened */ | |
2168 | mutex_lock(&priv->mutex); | |
2169 | ||
c1adf9fb | 2170 | memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd)); |
5a66926a ZY |
2171 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
2172 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 2173 | |
5a66926a | 2174 | if (!priv->ucode_code.len) { |
5b9f8cd3 | 2175 | ret = iwl_read_ucode(priv); |
5a66926a | 2176 | if (ret) { |
15b1687c | 2177 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a | 2178 | mutex_unlock(&priv->mutex); |
6cd0b1cb | 2179 | return ret; |
5a66926a ZY |
2180 | } |
2181 | } | |
b481de9c | 2182 | |
5b9f8cd3 | 2183 | ret = __iwl_up(priv); |
5a66926a | 2184 | |
b481de9c | 2185 | mutex_unlock(&priv->mutex); |
5a66926a | 2186 | |
80fcc9e2 AG |
2187 | iwl_rfkill_set_hw_state(priv); |
2188 | ||
e655b9f0 | 2189 | if (ret) |
6cd0b1cb | 2190 | return ret; |
e655b9f0 | 2191 | |
c1842d61 TW |
2192 | if (iwl_is_rfkill(priv)) |
2193 | goto out; | |
2194 | ||
e655b9f0 ZY |
2195 | IWL_DEBUG_INFO("Start UP work done.\n"); |
2196 | ||
2197 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | |
2198 | return 0; | |
2199 | ||
fe9b6b72 | 2200 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2201 | * mac80211 will not be run successfully. */ |
154b25ce EG |
2202 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
2203 | test_bit(STATUS_READY, &priv->status), | |
2204 | UCODE_READY_TIMEOUT); | |
2205 | if (!ret) { | |
2206 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 2207 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 2208 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 2209 | return -ETIMEDOUT; |
5a66926a | 2210 | } |
fe9b6b72 | 2211 | } |
0a078ffa | 2212 | |
c1842d61 | 2213 | out: |
0a078ffa | 2214 | priv->is_open = 1; |
b481de9c ZY |
2215 | IWL_DEBUG_MAC80211("leave\n"); |
2216 | return 0; | |
2217 | } | |
2218 | ||
5b9f8cd3 | 2219 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2220 | { |
c79dd5b5 | 2221 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
2222 | |
2223 | IWL_DEBUG_MAC80211("enter\n"); | |
948c171c | 2224 | |
e655b9f0 ZY |
2225 | if (!priv->is_open) { |
2226 | IWL_DEBUG_MAC80211("leave - skip\n"); | |
2227 | return; | |
2228 | } | |
2229 | ||
b481de9c | 2230 | priv->is_open = 0; |
5a66926a | 2231 | |
fee1247a | 2232 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
2233 | /* stop mac, cancel any scan request and clear |
2234 | * RXON_FILTER_ASSOC_MSK BIT | |
2235 | */ | |
5a66926a | 2236 | mutex_lock(&priv->mutex); |
2a421b91 | 2237 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2238 | mutex_unlock(&priv->mutex); |
fde3571f MA |
2239 | } |
2240 | ||
5b9f8cd3 | 2241 | iwl_down(priv); |
5a66926a ZY |
2242 | |
2243 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
2244 | |
2245 | /* enable interrupts again in order to receive rfkill changes */ | |
2246 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
2247 | iwl_enable_interrupts(priv); | |
948c171c | 2248 | |
b481de9c | 2249 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
2250 | } |
2251 | ||
5b9f8cd3 | 2252 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2253 | { |
c79dd5b5 | 2254 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2255 | |
f3674227 | 2256 | IWL_DEBUG_MACDUMP("enter\n"); |
b481de9c | 2257 | |
b481de9c | 2258 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2259 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2260 | |
e039fa4a | 2261 | if (iwl_tx_skb(priv, skb)) |
b481de9c ZY |
2262 | dev_kfree_skb_any(skb); |
2263 | ||
f3674227 | 2264 | IWL_DEBUG_MACDUMP("leave\n"); |
637f8837 | 2265 | return NETDEV_TX_OK; |
b481de9c ZY |
2266 | } |
2267 | ||
5b9f8cd3 | 2268 | static int iwl_mac_add_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
2269 | struct ieee80211_if_init_conf *conf) |
2270 | { | |
c79dd5b5 | 2271 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
2272 | unsigned long flags; |
2273 | ||
32bfd35d | 2274 | IWL_DEBUG_MAC80211("enter: type %d\n", conf->type); |
b481de9c | 2275 | |
32bfd35d JB |
2276 | if (priv->vif) { |
2277 | IWL_DEBUG_MAC80211("leave - vif != NULL\n"); | |
75849d28 | 2278 | return -EOPNOTSUPP; |
b481de9c ZY |
2279 | } |
2280 | ||
2281 | spin_lock_irqsave(&priv->lock, flags); | |
32bfd35d | 2282 | priv->vif = conf->vif; |
60294de3 | 2283 | priv->iw_mode = conf->type; |
b481de9c ZY |
2284 | |
2285 | spin_unlock_irqrestore(&priv->lock, flags); | |
2286 | ||
2287 | mutex_lock(&priv->mutex); | |
864792e3 TW |
2288 | |
2289 | if (conf->mac_addr) { | |
e174961c | 2290 | IWL_DEBUG_MAC80211("Set %pM\n", conf->mac_addr); |
864792e3 TW |
2291 | memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN); |
2292 | } | |
b481de9c | 2293 | |
5b9f8cd3 | 2294 | if (iwl_set_mode(priv, conf->type) == -EAGAIN) |
c46fbefa AK |
2295 | /* we are not ready, will run again when ready */ |
2296 | set_bit(STATUS_MODE_PENDING, &priv->status); | |
5a66926a | 2297 | |
b481de9c ZY |
2298 | mutex_unlock(&priv->mutex); |
2299 | ||
5a66926a | 2300 | IWL_DEBUG_MAC80211("leave\n"); |
b481de9c ZY |
2301 | return 0; |
2302 | } | |
2303 | ||
2304 | /** | |
5b9f8cd3 | 2305 | * iwl_mac_config - mac80211 config callback |
b481de9c ZY |
2306 | * |
2307 | * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to | |
2308 | * be set inappropriately and the driver currently sets the hardware up to | |
2309 | * use it whenever needed. | |
2310 | */ | |
5b9f8cd3 | 2311 | static int iwl_mac_config(struct ieee80211_hw *hw, u32 changed) |
b481de9c | 2312 | { |
c79dd5b5 | 2313 | struct iwl_priv *priv = hw->priv; |
bf85ea4f | 2314 | const struct iwl_channel_info *ch_info; |
e8975581 | 2315 | struct ieee80211_conf *conf = &hw->conf; |
b481de9c | 2316 | unsigned long flags; |
76bb77e0 | 2317 | int ret = 0; |
82a66bbb | 2318 | u16 channel; |
b481de9c ZY |
2319 | |
2320 | mutex_lock(&priv->mutex); | |
8318d78a | 2321 | IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value); |
b481de9c | 2322 | |
de27e64e | 2323 | priv->current_ht_config.is_ht = conf_is_ht(conf); |
ae5eb026 | 2324 | |
14a08a7f | 2325 | if (conf->radio_enabled && iwl_radio_kill_sw_enable_radio(priv)) { |
64e72c3e | 2326 | IWL_DEBUG_MAC80211("leave - RF-KILL - waiting for uCode\n"); |
14a08a7f | 2327 | goto out; |
64e72c3e MA |
2328 | } |
2329 | ||
14a08a7f EG |
2330 | if (!conf->radio_enabled) |
2331 | iwl_radio_kill_sw_disable_radio(priv); | |
2332 | ||
fee1247a | 2333 | if (!iwl_is_ready(priv)) { |
b481de9c | 2334 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
76bb77e0 ZY |
2335 | ret = -EIO; |
2336 | goto out; | |
b481de9c ZY |
2337 | } |
2338 | ||
1ea87396 | 2339 | if (unlikely(!priv->cfg->mod_params->disable_hw_scan && |
b481de9c | 2340 | test_bit(STATUS_SCANNING, &priv->status))) { |
a0646470 | 2341 | IWL_DEBUG_MAC80211("leave - scanning\n"); |
b481de9c | 2342 | mutex_unlock(&priv->mutex); |
a0646470 | 2343 | return 0; |
b481de9c ZY |
2344 | } |
2345 | ||
82a66bbb TW |
2346 | channel = ieee80211_frequency_to_channel(conf->channel->center_freq); |
2347 | ch_info = iwl_get_channel_info(priv, conf->channel->band, channel); | |
b481de9c | 2348 | if (!is_channel_valid(ch_info)) { |
b481de9c | 2349 | IWL_DEBUG_MAC80211("leave - invalid channel\n"); |
76bb77e0 ZY |
2350 | ret = -EINVAL; |
2351 | goto out; | |
b481de9c ZY |
2352 | } |
2353 | ||
05c914fe | 2354 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && |
398f9e76 | 2355 | !is_channel_ibss(ch_info)) { |
15b1687c | 2356 | IWL_ERR(priv, "channel %d in band %d not IBSS channel\n", |
398f9e76 AK |
2357 | conf->channel->hw_value, conf->channel->band); |
2358 | ret = -EINVAL; | |
2359 | goto out; | |
2360 | } | |
2361 | ||
82a66bbb TW |
2362 | spin_lock_irqsave(&priv->lock, flags); |
2363 | ||
b5d7be5e | 2364 | |
78330fdd | 2365 | /* if we are switching from ht to 2.4 clear flags |
b481de9c ZY |
2366 | * from any ht related info since 2.4 does not |
2367 | * support ht */ | |
82a66bbb | 2368 | if ((le16_to_cpu(priv->staging_rxon.channel) != channel) |
b481de9c ZY |
2369 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH |
2370 | && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) | |
2371 | #endif | |
2372 | ) | |
2373 | priv->staging_rxon.flags = 0; | |
b481de9c | 2374 | |
17e72782 | 2375 | iwl_set_rxon_channel(priv, conf->channel); |
b481de9c | 2376 | |
82a66bbb | 2377 | iwl_set_flags_for_band(priv, conf->channel->band); |
b481de9c ZY |
2378 | |
2379 | /* The list of supported rates and rate mask can be different | |
8318d78a | 2380 | * for each band; since the band may have changed, reset |
b481de9c | 2381 | * the rate mask to what mac80211 lists */ |
5b9f8cd3 | 2382 | iwl_set_rate(priv); |
b481de9c ZY |
2383 | |
2384 | spin_unlock_irqrestore(&priv->lock, flags); | |
2385 | ||
2386 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH | |
2387 | if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) { | |
5b9f8cd3 | 2388 | iwl_hw_channel_switch(priv, conf->channel); |
76bb77e0 | 2389 | goto out; |
b481de9c ZY |
2390 | } |
2391 | #endif | |
2392 | ||
b481de9c ZY |
2393 | if (!conf->radio_enabled) { |
2394 | IWL_DEBUG_MAC80211("leave - radio disabled\n"); | |
76bb77e0 | 2395 | goto out; |
b481de9c ZY |
2396 | } |
2397 | ||
fee1247a | 2398 | if (iwl_is_rfkill(priv)) { |
b481de9c | 2399 | IWL_DEBUG_MAC80211("leave - RF kill\n"); |
76bb77e0 ZY |
2400 | ret = -EIO; |
2401 | goto out; | |
b481de9c ZY |
2402 | } |
2403 | ||
e602cb18 EK |
2404 | if (conf->flags & IEEE80211_CONF_PS) |
2405 | ret = iwl_power_set_user_mode(priv, IWL_POWER_INDEX_3); | |
2406 | else | |
2407 | ret = iwl_power_set_user_mode(priv, IWL_POWER_MODE_CAM); | |
2408 | if (ret) | |
2409 | IWL_DEBUG_MAC80211("Error setting power level\n"); | |
2410 | ||
630fe9b6 TW |
2411 | IWL_DEBUG_MAC80211("TX Power old=%d new=%d\n", |
2412 | priv->tx_power_user_lmt, conf->power_level); | |
2413 | ||
2414 | iwl_set_tx_power(priv, conf->power_level, false); | |
2415 | ||
5b9f8cd3 | 2416 | iwl_set_rate(priv); |
b481de9c | 2417 | |
7b841727 RF |
2418 | /* call to ensure that 4965 rx_chain is set properly in monitor mode */ |
2419 | iwl_set_rxon_chain(priv); | |
2420 | ||
b481de9c ZY |
2421 | if (memcmp(&priv->active_rxon, |
2422 | &priv->staging_rxon, sizeof(priv->staging_rxon))) | |
5b9f8cd3 | 2423 | iwl_commit_rxon(priv); |
b481de9c ZY |
2424 | else |
2425 | IWL_DEBUG_INFO("No re-sending same RXON configuration.\n"); | |
2426 | ||
2427 | IWL_DEBUG_MAC80211("leave\n"); | |
2428 | ||
a0646470 | 2429 | out: |
5a66926a | 2430 | mutex_unlock(&priv->mutex); |
76bb77e0 | 2431 | return ret; |
b481de9c ZY |
2432 | } |
2433 | ||
5b9f8cd3 | 2434 | static void iwl_config_ap(struct iwl_priv *priv) |
b481de9c | 2435 | { |
857485c0 | 2436 | int ret = 0; |
1ff50bda | 2437 | unsigned long flags; |
b481de9c | 2438 | |
d986bcd1 | 2439 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
2440 | return; |
2441 | ||
2442 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 2443 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
2444 | |
2445 | /* RXON - unassoc (to set timing command) */ | |
2446 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5b9f8cd3 | 2447 | iwl_commit_rxon(priv); |
b481de9c ZY |
2448 | |
2449 | /* RXON Timing */ | |
3195c1f3 | 2450 | iwl_setup_rxon_timing(priv); |
857485c0 | 2451 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2452 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2453 | if (ret) |
39aadf8c | 2454 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2455 | "Attempting to continue.\n"); |
2456 | ||
c7de35cd | 2457 | iwl_set_rxon_chain(priv); |
b481de9c ZY |
2458 | |
2459 | /* FIXME: what should be the assoc_id for AP? */ | |
2460 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
2461 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2462 | priv->staging_rxon.flags |= | |
2463 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2464 | else | |
2465 | priv->staging_rxon.flags &= | |
2466 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2467 | ||
2468 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2469 | if (priv->assoc_capability & | |
2470 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2471 | priv->staging_rxon.flags |= | |
2472 | RXON_FLG_SHORT_SLOT_MSK; | |
2473 | else | |
2474 | priv->staging_rxon.flags &= | |
2475 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2476 | ||
05c914fe | 2477 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2478 | priv->staging_rxon.flags &= |
2479 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2480 | } | |
2481 | /* restore RXON assoc */ | |
2482 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
5b9f8cd3 | 2483 | iwl_commit_rxon(priv); |
1ff50bda EG |
2484 | spin_lock_irqsave(&priv->lock, flags); |
2485 | iwl_activate_qos(priv, 1); | |
2486 | spin_unlock_irqrestore(&priv->lock, flags); | |
4f40e4d9 | 2487 | iwl_rxon_add_station(priv, iwl_bcast_addr, 0); |
e1493deb | 2488 | } |
5b9f8cd3 | 2489 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2490 | |
2491 | /* FIXME - we need to add code here to detect a totally new | |
2492 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
2493 | * clear sta table, add BCAST sta... */ | |
2494 | } | |
2495 | ||
9d139c81 | 2496 | |
5b9f8cd3 | 2497 | static int iwl_mac_config_interface(struct ieee80211_hw *hw, |
32bfd35d | 2498 | struct ieee80211_vif *vif, |
b481de9c ZY |
2499 | struct ieee80211_if_conf *conf) |
2500 | { | |
c79dd5b5 | 2501 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
2502 | int rc; |
2503 | ||
2504 | if (conf == NULL) | |
2505 | return -EIO; | |
2506 | ||
b716bb91 EG |
2507 | if (priv->vif != vif) { |
2508 | IWL_DEBUG_MAC80211("leave - priv->vif != vif\n"); | |
b716bb91 EG |
2509 | return 0; |
2510 | } | |
2511 | ||
05c914fe | 2512 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC && |
9d139c81 JB |
2513 | conf->changed & IEEE80211_IFCC_BEACON) { |
2514 | struct sk_buff *beacon = ieee80211_beacon_get(hw, vif); | |
2515 | if (!beacon) | |
2516 | return -ENOMEM; | |
ada17513 | 2517 | mutex_lock(&priv->mutex); |
5b9f8cd3 | 2518 | rc = iwl_mac_beacon_update(hw, beacon); |
ada17513 | 2519 | mutex_unlock(&priv->mutex); |
9d139c81 JB |
2520 | if (rc) |
2521 | return rc; | |
2522 | } | |
2523 | ||
fee1247a | 2524 | if (!iwl_is_alive(priv)) |
5a66926a ZY |
2525 | return -EAGAIN; |
2526 | ||
b481de9c ZY |
2527 | mutex_lock(&priv->mutex); |
2528 | ||
b481de9c | 2529 | if (conf->bssid) |
e174961c | 2530 | IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid); |
b481de9c | 2531 | |
4150c572 JB |
2532 | /* |
2533 | * very dubious code was here; the probe filtering flag is never set: | |
2534 | * | |
b481de9c ZY |
2535 | if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) && |
2536 | !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) { | |
4150c572 | 2537 | */ |
b481de9c | 2538 | |
05c914fe | 2539 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
b481de9c ZY |
2540 | if (!conf->bssid) { |
2541 | conf->bssid = priv->mac_addr; | |
2542 | memcpy(priv->bssid, priv->mac_addr, ETH_ALEN); | |
e174961c JB |
2543 | IWL_DEBUG_MAC80211("bssid was set to: %pM\n", |
2544 | conf->bssid); | |
b481de9c ZY |
2545 | } |
2546 | if (priv->ibss_beacon) | |
2547 | dev_kfree_skb(priv->ibss_beacon); | |
2548 | ||
9d139c81 | 2549 | priv->ibss_beacon = ieee80211_beacon_get(hw, vif); |
b481de9c ZY |
2550 | } |
2551 | ||
fee1247a | 2552 | if (iwl_is_rfkill(priv)) |
fde3571f MA |
2553 | goto done; |
2554 | ||
b481de9c ZY |
2555 | if (conf->bssid && !is_zero_ether_addr(conf->bssid) && |
2556 | !is_multicast_ether_addr(conf->bssid)) { | |
2557 | /* If there is currently a HW scan going on in the background | |
2558 | * then we need to cancel it else the RXON below will fail. */ | |
2a421b91 | 2559 | if (iwl_scan_cancel_timeout(priv, 100)) { |
39aadf8c | 2560 | IWL_WARN(priv, "Aborted scan still in progress " |
b481de9c ZY |
2561 | "after 100ms\n"); |
2562 | IWL_DEBUG_MAC80211("leaving - scan abort failed.\n"); | |
2563 | mutex_unlock(&priv->mutex); | |
2564 | return -EAGAIN; | |
2565 | } | |
2566 | memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN); | |
2567 | ||
2568 | /* TODO: Audit driver for usage of these members and see | |
2569 | * if mac80211 deprecates them (priv->bssid looks like it | |
2570 | * shouldn't be there, but I haven't scanned the IBSS code | |
2571 | * to verify) - jpk */ | |
2572 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | |
2573 | ||
05c914fe | 2574 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
5b9f8cd3 | 2575 | iwl_config_ap(priv); |
b481de9c | 2576 | else { |
5b9f8cd3 | 2577 | rc = iwl_commit_rxon(priv); |
05c914fe | 2578 | if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc) |
4f40e4d9 | 2579 | iwl_rxon_add_station( |
b481de9c ZY |
2580 | priv, priv->active_rxon.bssid_addr, 1); |
2581 | } | |
2582 | ||
2583 | } else { | |
2a421b91 | 2584 | iwl_scan_cancel_timeout(priv, 100); |
b481de9c | 2585 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
5b9f8cd3 | 2586 | iwl_commit_rxon(priv); |
b481de9c ZY |
2587 | } |
2588 | ||
fde3571f | 2589 | done: |
b481de9c ZY |
2590 | IWL_DEBUG_MAC80211("leave\n"); |
2591 | mutex_unlock(&priv->mutex); | |
2592 | ||
2593 | return 0; | |
2594 | } | |
2595 | ||
5b9f8cd3 | 2596 | static void iwl_mac_remove_interface(struct ieee80211_hw *hw, |
b481de9c ZY |
2597 | struct ieee80211_if_init_conf *conf) |
2598 | { | |
c79dd5b5 | 2599 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
2600 | |
2601 | IWL_DEBUG_MAC80211("enter\n"); | |
2602 | ||
2603 | mutex_lock(&priv->mutex); | |
948c171c | 2604 | |
fee1247a | 2605 | if (iwl_is_ready_rf(priv)) { |
2a421b91 | 2606 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2607 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
5b9f8cd3 | 2608 | iwl_commit_rxon(priv); |
fde3571f | 2609 | } |
32bfd35d JB |
2610 | if (priv->vif == conf->vif) { |
2611 | priv->vif = NULL; | |
b481de9c | 2612 | memset(priv->bssid, 0, ETH_ALEN); |
b481de9c ZY |
2613 | } |
2614 | mutex_unlock(&priv->mutex); | |
2615 | ||
2616 | IWL_DEBUG_MAC80211("leave\n"); | |
2617 | ||
2618 | } | |
471b3efd | 2619 | |
3109ece1 | 2620 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
5b9f8cd3 | 2621 | static void iwl_bss_info_changed(struct ieee80211_hw *hw, |
471b3efd JB |
2622 | struct ieee80211_vif *vif, |
2623 | struct ieee80211_bss_conf *bss_conf, | |
2624 | u32 changes) | |
220173b0 | 2625 | { |
c79dd5b5 | 2626 | struct iwl_priv *priv = hw->priv; |
220173b0 | 2627 | |
3109ece1 TW |
2628 | IWL_DEBUG_MAC80211("changes = 0x%X\n", changes); |
2629 | ||
471b3efd | 2630 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { |
3109ece1 TW |
2631 | IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n", |
2632 | bss_conf->use_short_preamble); | |
471b3efd | 2633 | if (bss_conf->use_short_preamble) |
220173b0 TW |
2634 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
2635 | else | |
2636 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2637 | } | |
2638 | ||
471b3efd | 2639 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { |
3109ece1 | 2640 | IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); |
8318d78a | 2641 | if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) |
220173b0 TW |
2642 | priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK; |
2643 | else | |
2644 | priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK; | |
2645 | } | |
2646 | ||
98952d5d | 2647 | if (changes & BSS_CHANGED_HT) { |
5b9f8cd3 | 2648 | iwl_ht_conf(priv, bss_conf); |
c7de35cd | 2649 | iwl_set_rxon_chain(priv); |
98952d5d TW |
2650 | } |
2651 | ||
471b3efd | 2652 | if (changes & BSS_CHANGED_ASSOC) { |
3109ece1 | 2653 | IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc); |
508e32e1 RC |
2654 | /* This should never happen as this function should |
2655 | * never be called from interrupt context. */ | |
2656 | if (WARN_ON_ONCE(in_interrupt())) | |
2657 | return; | |
3109ece1 TW |
2658 | if (bss_conf->assoc) { |
2659 | priv->assoc_id = bss_conf->aid; | |
2660 | priv->beacon_int = bss_conf->beacon_int; | |
b5d7be5e | 2661 | priv->power_data.dtim_period = bss_conf->dtim_period; |
3109ece1 TW |
2662 | priv->timestamp = bss_conf->timestamp; |
2663 | priv->assoc_capability = bss_conf->assoc_capability; | |
9ccacb86 TW |
2664 | |
2665 | /* we have just associated, don't start scan too early | |
2666 | * leave time for EAPOL exchange to complete | |
2667 | */ | |
3109ece1 TW |
2668 | priv->next_scan_jiffies = jiffies + |
2669 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
508e32e1 | 2670 | mutex_lock(&priv->mutex); |
5b9f8cd3 | 2671 | iwl_post_associate(priv); |
508e32e1 | 2672 | mutex_unlock(&priv->mutex); |
3109ece1 TW |
2673 | } else { |
2674 | priv->assoc_id = 0; | |
2675 | IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc); | |
2676 | } | |
2677 | } else if (changes && iwl_is_associated(priv) && priv->assoc_id) { | |
2678 | IWL_DEBUG_MAC80211("Associated Changes %d\n", changes); | |
7e8c519e | 2679 | iwl_send_rxon_assoc(priv); |
471b3efd JB |
2680 | } |
2681 | ||
220173b0 | 2682 | } |
b481de9c | 2683 | |
cb43dc25 | 2684 | static int iwl_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t ssid_len) |
b481de9c | 2685 | { |
b481de9c | 2686 | unsigned long flags; |
c79dd5b5 | 2687 | struct iwl_priv *priv = hw->priv; |
8d09a5e1 | 2688 | int ret; |
b481de9c ZY |
2689 | |
2690 | IWL_DEBUG_MAC80211("enter\n"); | |
2691 | ||
052c4b9f | 2692 | mutex_lock(&priv->mutex); |
b481de9c ZY |
2693 | spin_lock_irqsave(&priv->lock, flags); |
2694 | ||
fee1247a | 2695 | if (!iwl_is_ready_rf(priv)) { |
cb43dc25 | 2696 | ret = -EIO; |
b481de9c ZY |
2697 | IWL_DEBUG_MAC80211("leave - not ready or exit pending\n"); |
2698 | goto out_unlock; | |
2699 | } | |
2700 | ||
8d09a5e1 TW |
2701 | /* We don't schedule scan within next_scan_jiffies period. |
2702 | * Avoid scanning during possible EAPOL exchange, return | |
2703 | * success immediately. | |
2704 | */ | |
7878a5a4 | 2705 | if (priv->next_scan_jiffies && |
cb43dc25 | 2706 | time_after(priv->next_scan_jiffies, jiffies)) { |
681c0050 | 2707 | IWL_DEBUG_SCAN("scan rejected: within next scan period\n"); |
8d09a5e1 TW |
2708 | queue_work(priv->workqueue, &priv->scan_completed); |
2709 | ret = 0; | |
7878a5a4 MA |
2710 | goto out_unlock; |
2711 | } | |
8d09a5e1 | 2712 | |
b481de9c | 2713 | /* if we just finished scan ask for delay */ |
681c0050 | 2714 | if (iwl_is_associated(priv) && priv->last_scan_jiffies && |
cb43dc25 | 2715 | time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN, jiffies)) { |
681c0050 | 2716 | IWL_DEBUG_SCAN("scan rejected: within previous scan period\n"); |
8d09a5e1 TW |
2717 | queue_work(priv->workqueue, &priv->scan_completed); |
2718 | ret = 0; | |
b481de9c ZY |
2719 | goto out_unlock; |
2720 | } | |
8d09a5e1 | 2721 | |
cb43dc25 | 2722 | if (ssid_len) { |
b481de9c | 2723 | priv->one_direct_scan = 1; |
cb43dc25 | 2724 | priv->direct_ssid_len = min_t(u8, ssid_len, IW_ESSID_MAX_SIZE); |
b481de9c | 2725 | memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len); |
cb43dc25 | 2726 | } else { |
948c171c | 2727 | priv->one_direct_scan = 0; |
cb43dc25 | 2728 | } |
b481de9c | 2729 | |
cb43dc25 | 2730 | ret = iwl_scan_initiate(priv); |
b481de9c ZY |
2731 | |
2732 | IWL_DEBUG_MAC80211("leave\n"); | |
2733 | ||
2734 | out_unlock: | |
2735 | spin_unlock_irqrestore(&priv->lock, flags); | |
052c4b9f | 2736 | mutex_unlock(&priv->mutex); |
b481de9c | 2737 | |
cb43dc25 | 2738 | return ret; |
b481de9c ZY |
2739 | } |
2740 | ||
5b9f8cd3 | 2741 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
ab885f8c EG |
2742 | struct ieee80211_key_conf *keyconf, const u8 *addr, |
2743 | u32 iv32, u16 *phase1key) | |
2744 | { | |
ab885f8c | 2745 | |
9f58671e | 2746 | struct iwl_priv *priv = hw->priv; |
ab885f8c EG |
2747 | IWL_DEBUG_MAC80211("enter\n"); |
2748 | ||
9f58671e | 2749 | iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key); |
ab885f8c EG |
2750 | |
2751 | IWL_DEBUG_MAC80211("leave\n"); | |
2752 | } | |
2753 | ||
5b9f8cd3 | 2754 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
2755 | struct ieee80211_vif *vif, |
2756 | struct ieee80211_sta *sta, | |
b481de9c ZY |
2757 | struct ieee80211_key_conf *key) |
2758 | { | |
c79dd5b5 | 2759 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
2760 | const u8 *addr; |
2761 | int ret; | |
2762 | u8 sta_id; | |
2763 | bool is_default_wep_key = false; | |
b481de9c ZY |
2764 | |
2765 | IWL_DEBUG_MAC80211("enter\n"); | |
2766 | ||
099b40b7 | 2767 | if (priv->hw_params.sw_crypto) { |
b481de9c ZY |
2768 | IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n"); |
2769 | return -EOPNOTSUPP; | |
2770 | } | |
42986796 | 2771 | addr = sta ? sta->addr : iwl_bcast_addr; |
947b13a7 | 2772 | sta_id = iwl_find_station(priv, addr); |
6974e363 | 2773 | if (sta_id == IWL_INVALID_STATION) { |
e174961c JB |
2774 | IWL_DEBUG_MAC80211("leave - %pM not in station map.\n", |
2775 | addr); | |
6974e363 | 2776 | return -EINVAL; |
b481de9c | 2777 | |
deb09c43 | 2778 | } |
b481de9c | 2779 | |
6974e363 | 2780 | mutex_lock(&priv->mutex); |
2a421b91 | 2781 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 EG |
2782 | mutex_unlock(&priv->mutex); |
2783 | ||
2784 | /* If we are getting WEP group key and we didn't receive any key mapping | |
2785 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2786 | * in 1X mode. | |
2787 | * In legacy wep mode, we use another host command to the uCode */ | |
5425e490 | 2788 | if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id && |
05c914fe | 2789 | priv->iw_mode != NL80211_IFTYPE_AP) { |
6974e363 EG |
2790 | if (cmd == SET_KEY) |
2791 | is_default_wep_key = !priv->key_mapping_key; | |
2792 | else | |
ccc038ab EG |
2793 | is_default_wep_key = |
2794 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2795 | } |
052c4b9f | 2796 | |
b481de9c | 2797 | switch (cmd) { |
deb09c43 | 2798 | case SET_KEY: |
6974e363 EG |
2799 | if (is_default_wep_key) |
2800 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 2801 | else |
7480513f | 2802 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 EG |
2803 | |
2804 | IWL_DEBUG_MAC80211("enable hwcrypto key\n"); | |
b481de9c ZY |
2805 | break; |
2806 | case DISABLE_KEY: | |
6974e363 EG |
2807 | if (is_default_wep_key) |
2808 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 2809 | else |
3ec47732 | 2810 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 EG |
2811 | |
2812 | IWL_DEBUG_MAC80211("disable hwcrypto key\n"); | |
b481de9c ZY |
2813 | break; |
2814 | default: | |
deb09c43 | 2815 | ret = -EINVAL; |
b481de9c ZY |
2816 | } |
2817 | ||
2818 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c | 2819 | |
deb09c43 | 2820 | return ret; |
b481de9c ZY |
2821 | } |
2822 | ||
5b9f8cd3 | 2823 | static int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, |
b481de9c ZY |
2824 | const struct ieee80211_tx_queue_params *params) |
2825 | { | |
c79dd5b5 | 2826 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
2827 | unsigned long flags; |
2828 | int q; | |
b481de9c ZY |
2829 | |
2830 | IWL_DEBUG_MAC80211("enter\n"); | |
2831 | ||
fee1247a | 2832 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
2833 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
2834 | return -EIO; | |
2835 | } | |
2836 | ||
2837 | if (queue >= AC_NUM) { | |
2838 | IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue); | |
2839 | return 0; | |
2840 | } | |
2841 | ||
b481de9c ZY |
2842 | q = AC_NUM - 1 - queue; |
2843 | ||
2844 | spin_lock_irqsave(&priv->lock, flags); | |
2845 | ||
2846 | priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min); | |
2847 | priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max); | |
2848 | priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs; | |
2849 | priv->qos_data.def_qos_parm.ac[q].edca_txop = | |
3330d7be | 2850 | cpu_to_le16((params->txop * 32)); |
b481de9c ZY |
2851 | |
2852 | priv->qos_data.def_qos_parm.ac[q].reserved1 = 0; | |
2853 | priv->qos_data.qos_active = 1; | |
2854 | ||
05c914fe | 2855 | if (priv->iw_mode == NL80211_IFTYPE_AP) |
1ff50bda | 2856 | iwl_activate_qos(priv, 1); |
3109ece1 | 2857 | else if (priv->assoc_id && iwl_is_associated(priv)) |
1ff50bda | 2858 | iwl_activate_qos(priv, 0); |
b481de9c | 2859 | |
1ff50bda | 2860 | spin_unlock_irqrestore(&priv->lock, flags); |
b481de9c | 2861 | |
b481de9c ZY |
2862 | IWL_DEBUG_MAC80211("leave\n"); |
2863 | return 0; | |
2864 | } | |
2865 | ||
5b9f8cd3 | 2866 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
d783b061 | 2867 | enum ieee80211_ampdu_mlme_action action, |
17741cdc | 2868 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
d783b061 TW |
2869 | { |
2870 | struct iwl_priv *priv = hw->priv; | |
d783b061 | 2871 | |
e174961c JB |
2872 | IWL_DEBUG_HT("A-MPDU action on addr %pM tid %d\n", |
2873 | sta->addr, tid); | |
d783b061 TW |
2874 | |
2875 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2876 | return -EACCES; | |
2877 | ||
2878 | switch (action) { | |
2879 | case IEEE80211_AMPDU_RX_START: | |
2880 | IWL_DEBUG_HT("start Rx\n"); | |
9f58671e | 2881 | return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn); |
d783b061 TW |
2882 | case IEEE80211_AMPDU_RX_STOP: |
2883 | IWL_DEBUG_HT("stop Rx\n"); | |
9f58671e | 2884 | return iwl_sta_rx_agg_stop(priv, sta->addr, tid); |
d783b061 TW |
2885 | case IEEE80211_AMPDU_TX_START: |
2886 | IWL_DEBUG_HT("start Tx\n"); | |
17741cdc | 2887 | return iwl_tx_agg_start(priv, sta->addr, tid, ssn); |
d783b061 TW |
2888 | case IEEE80211_AMPDU_TX_STOP: |
2889 | IWL_DEBUG_HT("stop Tx\n"); | |
17741cdc | 2890 | return iwl_tx_agg_stop(priv, sta->addr, tid); |
d783b061 TW |
2891 | default: |
2892 | IWL_DEBUG_HT("unknown\n"); | |
2893 | return -EINVAL; | |
2894 | break; | |
2895 | } | |
2896 | return 0; | |
2897 | } | |
9f58671e | 2898 | |
5b9f8cd3 | 2899 | static int iwl_mac_get_tx_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2900 | struct ieee80211_tx_queue_stats *stats) |
2901 | { | |
c79dd5b5 | 2902 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2903 | int i, avail; |
16466903 | 2904 | struct iwl_tx_queue *txq; |
443cfd45 | 2905 | struct iwl_queue *q; |
b481de9c ZY |
2906 | unsigned long flags; |
2907 | ||
2908 | IWL_DEBUG_MAC80211("enter\n"); | |
2909 | ||
fee1247a | 2910 | if (!iwl_is_ready_rf(priv)) { |
b481de9c ZY |
2911 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
2912 | return -EIO; | |
2913 | } | |
2914 | ||
2915 | spin_lock_irqsave(&priv->lock, flags); | |
2916 | ||
2917 | for (i = 0; i < AC_NUM; i++) { | |
2918 | txq = &priv->txq[i]; | |
2919 | q = &txq->q; | |
443cfd45 | 2920 | avail = iwl_queue_space(q); |
b481de9c | 2921 | |
57ffc589 JB |
2922 | stats[i].len = q->n_window - avail; |
2923 | stats[i].limit = q->n_window - q->high_mark; | |
2924 | stats[i].count = q->n_window; | |
b481de9c ZY |
2925 | |
2926 | } | |
2927 | spin_unlock_irqrestore(&priv->lock, flags); | |
2928 | ||
2929 | IWL_DEBUG_MAC80211("leave\n"); | |
2930 | ||
2931 | return 0; | |
2932 | } | |
2933 | ||
5b9f8cd3 | 2934 | static int iwl_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2935 | struct ieee80211_low_level_stats *stats) |
2936 | { | |
bf403db8 EK |
2937 | struct iwl_priv *priv = hw->priv; |
2938 | ||
2939 | priv = hw->priv; | |
b481de9c ZY |
2940 | IWL_DEBUG_MAC80211("enter\n"); |
2941 | IWL_DEBUG_MAC80211("leave\n"); | |
2942 | ||
2943 | return 0; | |
2944 | } | |
2945 | ||
5b9f8cd3 | 2946 | static void iwl_mac_reset_tsf(struct ieee80211_hw *hw) |
b481de9c | 2947 | { |
c79dd5b5 | 2948 | struct iwl_priv *priv = hw->priv; |
b481de9c ZY |
2949 | unsigned long flags; |
2950 | ||
2951 | mutex_lock(&priv->mutex); | |
2952 | IWL_DEBUG_MAC80211("enter\n"); | |
2953 | ||
b481de9c | 2954 | spin_lock_irqsave(&priv->lock, flags); |
fd105e79 | 2955 | memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info)); |
b481de9c | 2956 | spin_unlock_irqrestore(&priv->lock, flags); |
b481de9c | 2957 | |
c7de35cd | 2958 | iwl_reset_qos(priv); |
b481de9c | 2959 | |
b481de9c ZY |
2960 | spin_lock_irqsave(&priv->lock, flags); |
2961 | priv->assoc_id = 0; | |
2962 | priv->assoc_capability = 0; | |
b481de9c ZY |
2963 | priv->assoc_station_added = 0; |
2964 | ||
2965 | /* new association get rid of ibss beacon skb */ | |
2966 | if (priv->ibss_beacon) | |
2967 | dev_kfree_skb(priv->ibss_beacon); | |
2968 | ||
2969 | priv->ibss_beacon = NULL; | |
2970 | ||
2971 | priv->beacon_int = priv->hw->conf.beacon_int; | |
3109ece1 | 2972 | priv->timestamp = 0; |
05c914fe | 2973 | if ((priv->iw_mode == NL80211_IFTYPE_STATION)) |
b481de9c ZY |
2974 | priv->beacon_int = 0; |
2975 | ||
2976 | spin_unlock_irqrestore(&priv->lock, flags); | |
2977 | ||
fee1247a | 2978 | if (!iwl_is_ready_rf(priv)) { |
fde3571f MA |
2979 | IWL_DEBUG_MAC80211("leave - not ready\n"); |
2980 | mutex_unlock(&priv->mutex); | |
2981 | return; | |
2982 | } | |
2983 | ||
052c4b9f | 2984 | /* we are restarting association process |
2985 | * clear RXON_FILTER_ASSOC_MSK bit | |
2986 | */ | |
05c914fe | 2987 | if (priv->iw_mode != NL80211_IFTYPE_AP) { |
2a421b91 | 2988 | iwl_scan_cancel_timeout(priv, 100); |
052c4b9f | 2989 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
5b9f8cd3 | 2990 | iwl_commit_rxon(priv); |
052c4b9f | 2991 | } |
2992 | ||
5da4b55f MA |
2993 | iwl_power_update_mode(priv, 0); |
2994 | ||
b481de9c | 2995 | /* Per mac80211.h: This is only used in IBSS mode... */ |
05c914fe | 2996 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
052c4b9f | 2997 | |
c90a74ba EG |
2998 | /* switch to CAM during association period. |
2999 | * the ucode will block any association/authentication | |
3000 | * frome during assiciation period if it can not hear | |
3001 | * the AP because of PM. the timer enable PM back is | |
3002 | * association do not complete | |
3003 | */ | |
3004 | if (priv->hw->conf.channel->flags & (IEEE80211_CHAN_PASSIVE_SCAN | | |
3005 | IEEE80211_CHAN_RADAR)) | |
3006 | iwl_power_disable_management(priv, 3000); | |
3007 | ||
b481de9c ZY |
3008 | IWL_DEBUG_MAC80211("leave - not in IBSS\n"); |
3009 | mutex_unlock(&priv->mutex); | |
3010 | return; | |
3011 | } | |
3012 | ||
5b9f8cd3 | 3013 | iwl_set_rate(priv); |
b481de9c ZY |
3014 | |
3015 | mutex_unlock(&priv->mutex); | |
3016 | ||
3017 | IWL_DEBUG_MAC80211("leave\n"); | |
b481de9c ZY |
3018 | } |
3019 | ||
5b9f8cd3 | 3020 | static int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3021 | { |
c79dd5b5 | 3022 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3023 | unsigned long flags; |
2ff75b78 | 3024 | __le64 timestamp; |
b481de9c | 3025 | |
b481de9c ZY |
3026 | IWL_DEBUG_MAC80211("enter\n"); |
3027 | ||
fee1247a | 3028 | if (!iwl_is_ready_rf(priv)) { |
b481de9c | 3029 | IWL_DEBUG_MAC80211("leave - RF not ready\n"); |
b481de9c ZY |
3030 | return -EIO; |
3031 | } | |
3032 | ||
05c914fe | 3033 | if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { |
b481de9c | 3034 | IWL_DEBUG_MAC80211("leave - not IBSS\n"); |
b481de9c ZY |
3035 | return -EIO; |
3036 | } | |
3037 | ||
3038 | spin_lock_irqsave(&priv->lock, flags); | |
3039 | ||
3040 | if (priv->ibss_beacon) | |
3041 | dev_kfree_skb(priv->ibss_beacon); | |
3042 | ||
3043 | priv->ibss_beacon = skb; | |
3044 | ||
3045 | priv->assoc_id = 0; | |
2ff75b78 | 3046 | timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; |
b94d8eea | 3047 | priv->timestamp = le64_to_cpu(timestamp); |
b481de9c ZY |
3048 | |
3049 | IWL_DEBUG_MAC80211("leave\n"); | |
3050 | spin_unlock_irqrestore(&priv->lock, flags); | |
3051 | ||
c7de35cd | 3052 | iwl_reset_qos(priv); |
b481de9c | 3053 | |
5b9f8cd3 | 3054 | iwl_post_associate(priv); |
b481de9c | 3055 | |
b481de9c ZY |
3056 | |
3057 | return 0; | |
3058 | } | |
3059 | ||
b481de9c ZY |
3060 | /***************************************************************************** |
3061 | * | |
3062 | * sysfs attributes | |
3063 | * | |
3064 | *****************************************************************************/ | |
3065 | ||
0a6857e7 | 3066 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3067 | |
3068 | /* | |
3069 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 3070 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
3071 | * used for controlling the debug level. |
3072 | * | |
3073 | * See the level definitions in iwl for details. | |
3074 | */ | |
3075 | ||
8cf769c6 EK |
3076 | static ssize_t show_debug_level(struct device *d, |
3077 | struct device_attribute *attr, char *buf) | |
b481de9c | 3078 | { |
8cf769c6 EK |
3079 | struct iwl_priv *priv = d->driver_data; |
3080 | ||
3081 | return sprintf(buf, "0x%08X\n", priv->debug_level); | |
b481de9c | 3082 | } |
8cf769c6 EK |
3083 | static ssize_t store_debug_level(struct device *d, |
3084 | struct device_attribute *attr, | |
b481de9c ZY |
3085 | const char *buf, size_t count) |
3086 | { | |
8cf769c6 | 3087 | struct iwl_priv *priv = d->driver_data; |
9257746f TW |
3088 | unsigned long val; |
3089 | int ret; | |
b481de9c | 3090 | |
9257746f TW |
3091 | ret = strict_strtoul(buf, 0, &val); |
3092 | if (ret) | |
978785a3 | 3093 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
b481de9c | 3094 | else |
8cf769c6 | 3095 | priv->debug_level = val; |
b481de9c ZY |
3096 | |
3097 | return strnlen(buf, count); | |
3098 | } | |
3099 | ||
8cf769c6 EK |
3100 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3101 | show_debug_level, store_debug_level); | |
3102 | ||
b481de9c | 3103 | |
0a6857e7 | 3104 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3105 | |
b481de9c | 3106 | |
bc6f59bc TW |
3107 | static ssize_t show_version(struct device *d, |
3108 | struct device_attribute *attr, char *buf) | |
3109 | { | |
3110 | struct iwl_priv *priv = d->driver_data; | |
885ba202 | 3111 | struct iwl_alive_resp *palive = &priv->card_alive; |
f236a265 TW |
3112 | ssize_t pos = 0; |
3113 | u16 eeprom_ver; | |
bc6f59bc TW |
3114 | |
3115 | if (palive->is_valid) | |
f236a265 TW |
3116 | pos += sprintf(buf + pos, |
3117 | "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n" | |
3118 | "fw type: 0x%01X 0x%01X\n", | |
bc6f59bc TW |
3119 | palive->ucode_major, palive->ucode_minor, |
3120 | palive->sw_rev[0], palive->sw_rev[1], | |
3121 | palive->ver_type, palive->ver_subtype); | |
bc6f59bc | 3122 | else |
f236a265 TW |
3123 | pos += sprintf(buf + pos, "fw not loaded\n"); |
3124 | ||
3125 | if (priv->eeprom) { | |
3126 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); | |
3127 | pos += sprintf(buf + pos, "EEPROM version: 0x%x\n", | |
3128 | eeprom_ver); | |
3129 | } else { | |
3130 | pos += sprintf(buf + pos, "EEPROM not initialzed\n"); | |
3131 | } | |
3132 | ||
3133 | return pos; | |
bc6f59bc TW |
3134 | } |
3135 | ||
3136 | static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL); | |
3137 | ||
b481de9c ZY |
3138 | static ssize_t show_temperature(struct device *d, |
3139 | struct device_attribute *attr, char *buf) | |
3140 | { | |
c79dd5b5 | 3141 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c | 3142 | |
fee1247a | 3143 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3144 | return -EAGAIN; |
3145 | ||
91dbc5bd | 3146 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
3147 | } |
3148 | ||
3149 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3150 | ||
b481de9c ZY |
3151 | static ssize_t show_tx_power(struct device *d, |
3152 | struct device_attribute *attr, char *buf) | |
3153 | { | |
c79dd5b5 | 3154 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
91f39e8e JS |
3155 | |
3156 | if (!iwl_is_ready_rf(priv)) | |
3157 | return sprintf(buf, "off\n"); | |
3158 | else | |
3159 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
3160 | } |
3161 | ||
3162 | static ssize_t store_tx_power(struct device *d, | |
3163 | struct device_attribute *attr, | |
3164 | const char *buf, size_t count) | |
3165 | { | |
c79dd5b5 | 3166 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
9257746f TW |
3167 | unsigned long val; |
3168 | int ret; | |
b481de9c | 3169 | |
9257746f TW |
3170 | ret = strict_strtoul(buf, 10, &val); |
3171 | if (ret) | |
978785a3 | 3172 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
b481de9c | 3173 | else |
630fe9b6 | 3174 | iwl_set_tx_power(priv, val, false); |
b481de9c ZY |
3175 | |
3176 | return count; | |
3177 | } | |
3178 | ||
3179 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3180 | ||
3181 | static ssize_t show_flags(struct device *d, | |
3182 | struct device_attribute *attr, char *buf) | |
3183 | { | |
c79dd5b5 | 3184 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
3185 | |
3186 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
3187 | } | |
3188 | ||
3189 | static ssize_t store_flags(struct device *d, | |
3190 | struct device_attribute *attr, | |
3191 | const char *buf, size_t count) | |
3192 | { | |
c79dd5b5 | 3193 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
9257746f TW |
3194 | unsigned long val; |
3195 | u32 flags; | |
3196 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 3197 | if (ret) |
9257746f TW |
3198 | return ret; |
3199 | flags = (u32)val; | |
b481de9c ZY |
3200 | |
3201 | mutex_lock(&priv->mutex); | |
3202 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
3203 | /* Cancel any currently running scans... */ | |
2a421b91 | 3204 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3205 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3206 | else { |
9257746f | 3207 | IWL_DEBUG_INFO("Commit rxon.flags = 0x%04X\n", flags); |
b481de9c | 3208 | priv->staging_rxon.flags = cpu_to_le32(flags); |
5b9f8cd3 | 3209 | iwl_commit_rxon(priv); |
b481de9c ZY |
3210 | } |
3211 | } | |
3212 | mutex_unlock(&priv->mutex); | |
3213 | ||
3214 | return count; | |
3215 | } | |
3216 | ||
3217 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
3218 | ||
3219 | static ssize_t show_filter_flags(struct device *d, | |
3220 | struct device_attribute *attr, char *buf) | |
3221 | { | |
c79dd5b5 | 3222 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
b481de9c ZY |
3223 | |
3224 | return sprintf(buf, "0x%04X\n", | |
3225 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
3226 | } | |
3227 | ||
3228 | static ssize_t store_filter_flags(struct device *d, | |
3229 | struct device_attribute *attr, | |
3230 | const char *buf, size_t count) | |
3231 | { | |
c79dd5b5 | 3232 | struct iwl_priv *priv = (struct iwl_priv *)d->driver_data; |
9257746f TW |
3233 | unsigned long val; |
3234 | u32 filter_flags; | |
3235 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 3236 | if (ret) |
9257746f TW |
3237 | return ret; |
3238 | filter_flags = (u32)val; | |
b481de9c ZY |
3239 | |
3240 | mutex_lock(&priv->mutex); | |
3241 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
3242 | /* Cancel any currently running scans... */ | |
2a421b91 | 3243 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3244 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c ZY |
3245 | else { |
3246 | IWL_DEBUG_INFO("Committing rxon.filter_flags = " | |
3247 | "0x%04X\n", filter_flags); | |
3248 | priv->staging_rxon.filter_flags = | |
3249 | cpu_to_le32(filter_flags); | |
5b9f8cd3 | 3250 | iwl_commit_rxon(priv); |
b481de9c ZY |
3251 | } |
3252 | } | |
3253 | mutex_unlock(&priv->mutex); | |
3254 | ||
3255 | return count; | |
3256 | } | |
3257 | ||
3258 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
3259 | store_filter_flags); | |
3260 | ||
b481de9c ZY |
3261 | static ssize_t store_power_level(struct device *d, |
3262 | struct device_attribute *attr, | |
3263 | const char *buf, size_t count) | |
3264 | { | |
c79dd5b5 | 3265 | struct iwl_priv *priv = dev_get_drvdata(d); |
298df1f6 | 3266 | int ret; |
9257746f TW |
3267 | unsigned long mode; |
3268 | ||
b481de9c | 3269 | |
b481de9c ZY |
3270 | mutex_lock(&priv->mutex); |
3271 | ||
fee1247a | 3272 | if (!iwl_is_ready(priv)) { |
298df1f6 | 3273 | ret = -EAGAIN; |
b481de9c ZY |
3274 | goto out; |
3275 | } | |
3276 | ||
9257746f | 3277 | ret = strict_strtoul(buf, 10, &mode); |
926f0b2e | 3278 | if (ret) |
9257746f TW |
3279 | goto out; |
3280 | ||
298df1f6 EK |
3281 | ret = iwl_power_set_user_mode(priv, mode); |
3282 | if (ret) { | |
5da4b55f MA |
3283 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); |
3284 | goto out; | |
b481de9c | 3285 | } |
298df1f6 | 3286 | ret = count; |
b481de9c ZY |
3287 | |
3288 | out: | |
3289 | mutex_unlock(&priv->mutex); | |
298df1f6 | 3290 | return ret; |
b481de9c ZY |
3291 | } |
3292 | ||
b481de9c ZY |
3293 | static ssize_t show_power_level(struct device *d, |
3294 | struct device_attribute *attr, char *buf) | |
3295 | { | |
c79dd5b5 | 3296 | struct iwl_priv *priv = dev_get_drvdata(d); |
298df1f6 EK |
3297 | int mode = priv->power_data.user_power_setting; |
3298 | int system = priv->power_data.system_power_setting; | |
5da4b55f | 3299 | int level = priv->power_data.power_mode; |
b481de9c ZY |
3300 | char *p = buf; |
3301 | ||
298df1f6 EK |
3302 | switch (system) { |
3303 | case IWL_POWER_SYS_AUTO: | |
3304 | p += sprintf(p, "SYSTEM:auto"); | |
b481de9c | 3305 | break; |
298df1f6 EK |
3306 | case IWL_POWER_SYS_AC: |
3307 | p += sprintf(p, "SYSTEM:ac"); | |
3308 | break; | |
3309 | case IWL_POWER_SYS_BATTERY: | |
3310 | p += sprintf(p, "SYSTEM:battery"); | |
b481de9c | 3311 | break; |
b481de9c | 3312 | } |
298df1f6 | 3313 | |
c3056065 AK |
3314 | p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO) ? |
3315 | "fixed" : "auto"); | |
298df1f6 EK |
3316 | p += sprintf(p, "\tINDEX:%d", level); |
3317 | p += sprintf(p, "\n"); | |
3ac7f146 | 3318 | return p - buf + 1; |
b481de9c ZY |
3319 | } |
3320 | ||
3321 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
3322 | store_power_level); | |
3323 | ||
b481de9c ZY |
3324 | |
3325 | static ssize_t show_statistics(struct device *d, | |
3326 | struct device_attribute *attr, char *buf) | |
3327 | { | |
c79dd5b5 | 3328 | struct iwl_priv *priv = dev_get_drvdata(d); |
8f91aecb | 3329 | u32 size = sizeof(struct iwl_notif_statistics); |
b481de9c | 3330 | u32 len = 0, ofs = 0; |
3ac7f146 | 3331 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
3332 | int rc = 0; |
3333 | ||
fee1247a | 3334 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3335 | return -EAGAIN; |
3336 | ||
3337 | mutex_lock(&priv->mutex); | |
49ea8596 | 3338 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
3339 | mutex_unlock(&priv->mutex); |
3340 | ||
3341 | if (rc) { | |
3342 | len = sprintf(buf, | |
3343 | "Error sending statistics request: 0x%08X\n", rc); | |
3344 | return len; | |
3345 | } | |
3346 | ||
3347 | while (size && (PAGE_SIZE - len)) { | |
3348 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3349 | PAGE_SIZE - len, 1); | |
3350 | len = strlen(buf); | |
3351 | if (PAGE_SIZE - len) | |
3352 | buf[len++] = '\n'; | |
3353 | ||
3354 | ofs += 16; | |
3355 | size -= min(size, 16U); | |
3356 | } | |
3357 | ||
3358 | return len; | |
3359 | } | |
3360 | ||
3361 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
3362 | ||
b481de9c | 3363 | |
b481de9c ZY |
3364 | /***************************************************************************** |
3365 | * | |
3366 | * driver setup and teardown | |
3367 | * | |
3368 | *****************************************************************************/ | |
3369 | ||
4e39317d | 3370 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
3371 | { |
3372 | priv->workqueue = create_workqueue(DRV_NAME); | |
3373 | ||
3374 | init_waitqueue_head(&priv->wait_command_queue); | |
3375 | ||
5b9f8cd3 EG |
3376 | INIT_WORK(&priv->up, iwl_bg_up); |
3377 | INIT_WORK(&priv->restart, iwl_bg_restart); | |
3378 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
3379 | INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill); | |
3380 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); | |
16e727e8 | 3381 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
3382 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
3383 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 3384 | |
2a421b91 | 3385 | iwl_setup_scan_deferred_work(priv); |
c90a74ba | 3386 | iwl_setup_power_deferred_work(priv); |
bb8c093b | 3387 | |
4e39317d EG |
3388 | if (priv->cfg->ops->lib->setup_deferred_work) |
3389 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3390 | ||
3391 | init_timer(&priv->statistics_periodic); | |
3392 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3393 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c ZY |
3394 | |
3395 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
5b9f8cd3 | 3396 | iwl_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
3397 | } |
3398 | ||
4e39317d | 3399 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3400 | { |
4e39317d EG |
3401 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3402 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3403 | |
3ae6a054 | 3404 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c | 3405 | cancel_delayed_work(&priv->scan_check); |
c90a74ba | 3406 | cancel_delayed_work_sync(&priv->set_power_save); |
b481de9c | 3407 | cancel_delayed_work(&priv->alive_start); |
b481de9c | 3408 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 3409 | del_timer_sync(&priv->statistics_periodic); |
b481de9c ZY |
3410 | } |
3411 | ||
5b9f8cd3 | 3412 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c ZY |
3413 | &dev_attr_flags.attr, |
3414 | &dev_attr_filter_flags.attr, | |
b481de9c | 3415 | &dev_attr_power_level.attr, |
b481de9c | 3416 | &dev_attr_statistics.attr, |
b481de9c | 3417 | &dev_attr_temperature.attr, |
b481de9c | 3418 | &dev_attr_tx_power.attr, |
8cf769c6 EK |
3419 | #ifdef CONFIG_IWLWIFI_DEBUG |
3420 | &dev_attr_debug_level.attr, | |
3421 | #endif | |
bc6f59bc | 3422 | &dev_attr_version.attr, |
b481de9c ZY |
3423 | |
3424 | NULL | |
3425 | }; | |
3426 | ||
5b9f8cd3 | 3427 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 3428 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 3429 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
3430 | }; |
3431 | ||
5b9f8cd3 EG |
3432 | static struct ieee80211_ops iwl_hw_ops = { |
3433 | .tx = iwl_mac_tx, | |
3434 | .start = iwl_mac_start, | |
3435 | .stop = iwl_mac_stop, | |
3436 | .add_interface = iwl_mac_add_interface, | |
3437 | .remove_interface = iwl_mac_remove_interface, | |
3438 | .config = iwl_mac_config, | |
3439 | .config_interface = iwl_mac_config_interface, | |
3440 | .configure_filter = iwl_configure_filter, | |
3441 | .set_key = iwl_mac_set_key, | |
3442 | .update_tkip_key = iwl_mac_update_tkip_key, | |
3443 | .get_stats = iwl_mac_get_stats, | |
3444 | .get_tx_stats = iwl_mac_get_tx_stats, | |
3445 | .conf_tx = iwl_mac_conf_tx, | |
3446 | .reset_tsf = iwl_mac_reset_tsf, | |
3447 | .bss_info_changed = iwl_bss_info_changed, | |
3448 | .ampdu_action = iwl_mac_ampdu_action, | |
cb43dc25 | 3449 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
3450 | }; |
3451 | ||
5b9f8cd3 | 3452 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3453 | { |
3454 | int err = 0; | |
c79dd5b5 | 3455 | struct iwl_priv *priv; |
b481de9c | 3456 | struct ieee80211_hw *hw; |
82b9a121 | 3457 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 3458 | unsigned long flags; |
6cd0b1cb | 3459 | u16 pci_cmd; |
b481de9c | 3460 | |
316c30d9 AK |
3461 | /************************ |
3462 | * 1. Allocating HW data | |
3463 | ************************/ | |
3464 | ||
6440adb5 BC |
3465 | /* Disabling hardware scan means that mac80211 will perform scans |
3466 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 3467 | if (cfg->mod_params->disable_hw_scan) { |
bf403db8 EK |
3468 | if (cfg->mod_params->debug & IWL_DL_INFO) |
3469 | dev_printk(KERN_DEBUG, &(pdev->dev), | |
3470 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 3471 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
3472 | } |
3473 | ||
5b9f8cd3 | 3474 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 3475 | if (!hw) { |
b481de9c ZY |
3476 | err = -ENOMEM; |
3477 | goto out; | |
3478 | } | |
1d0a082d AK |
3479 | priv = hw->priv; |
3480 | /* At this point both hw and priv are allocated. */ | |
3481 | ||
b481de9c ZY |
3482 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3483 | ||
3484 | IWL_DEBUG_INFO("*** LOAD DRIVER ***\n"); | |
82b9a121 | 3485 | priv->cfg = cfg; |
b481de9c | 3486 | priv->pci_dev = pdev; |
316c30d9 | 3487 | |
0a6857e7 | 3488 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 3489 | priv->debug_level = priv->cfg->mod_params->debug; |
b481de9c ZY |
3490 | atomic_set(&priv->restrict_refcnt, 0); |
3491 | #endif | |
b481de9c | 3492 | |
316c30d9 AK |
3493 | /************************** |
3494 | * 2. Initializing PCI bus | |
3495 | **************************/ | |
3496 | if (pci_enable_device(pdev)) { | |
3497 | err = -ENODEV; | |
3498 | goto out_ieee80211_free_hw; | |
3499 | } | |
3500 | ||
3501 | pci_set_master(pdev); | |
3502 | ||
093d874c | 3503 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 3504 | if (!err) |
093d874c | 3505 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 3506 | if (err) { |
093d874c | 3507 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3508 | if (!err) |
093d874c | 3509 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3510 | /* both attempts failed: */ |
316c30d9 | 3511 | if (err) { |
978785a3 | 3512 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 3513 | goto out_pci_disable_device; |
cc2a8ea8 | 3514 | } |
316c30d9 AK |
3515 | } |
3516 | ||
3517 | err = pci_request_regions(pdev, DRV_NAME); | |
3518 | if (err) | |
3519 | goto out_pci_disable_device; | |
3520 | ||
3521 | pci_set_drvdata(pdev, priv); | |
3522 | ||
316c30d9 AK |
3523 | |
3524 | /*********************** | |
3525 | * 3. Read REV register | |
3526 | ***********************/ | |
3527 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3528 | if (!priv->hw_base) { | |
3529 | err = -ENODEV; | |
3530 | goto out_pci_release_regions; | |
3531 | } | |
3532 | ||
3533 | IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n", | |
3534 | (unsigned long long) pci_resource_len(pdev, 0)); | |
3535 | IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base); | |
3536 | ||
b661c819 | 3537 | iwl_hw_detect(priv); |
978785a3 | 3538 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", |
b661c819 | 3539 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 3540 | |
e7b63581 TW |
3541 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3542 | * PCI Tx retries from interfering with C3 CPU state */ | |
3543 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3544 | ||
91238714 TW |
3545 | /* amp init */ |
3546 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
316c30d9 | 3547 | if (err < 0) { |
91238714 | 3548 | IWL_DEBUG_INFO("Failed to init APMG\n"); |
316c30d9 AK |
3549 | goto out_iounmap; |
3550 | } | |
91238714 TW |
3551 | /***************** |
3552 | * 4. Read EEPROM | |
3553 | *****************/ | |
316c30d9 AK |
3554 | /* Read the EEPROM */ |
3555 | err = iwl_eeprom_init(priv); | |
3556 | if (err) { | |
15b1687c | 3557 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
3558 | goto out_iounmap; |
3559 | } | |
8614f360 TW |
3560 | err = iwl_eeprom_check_version(priv); |
3561 | if (err) | |
3562 | goto out_iounmap; | |
3563 | ||
02883017 | 3564 | /* extract MAC Address */ |
316c30d9 | 3565 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e174961c | 3566 | IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
3567 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
3568 | ||
3569 | /************************ | |
3570 | * 5. Setup HW constants | |
3571 | ************************/ | |
da154e30 | 3572 | if (iwl_set_hw_params(priv)) { |
15b1687c | 3573 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3574 | goto out_free_eeprom; |
316c30d9 AK |
3575 | } |
3576 | ||
3577 | /******************* | |
6ba87956 | 3578 | * 6. Setup priv |
316c30d9 | 3579 | *******************/ |
b481de9c | 3580 | |
6ba87956 | 3581 | err = iwl_init_drv(priv); |
bf85ea4f | 3582 | if (err) |
399f4900 | 3583 | goto out_free_eeprom; |
bf85ea4f | 3584 | /* At this point both hw and priv are initialized. */ |
316c30d9 AK |
3585 | |
3586 | /********************************** | |
3587 | * 7. Initialize module parameters | |
3588 | **********************************/ | |
3589 | ||
3590 | /* Disable radio (SW RF KILL) via parameter when loading driver */ | |
1ea87396 | 3591 | if (priv->cfg->mod_params->disable) { |
316c30d9 AK |
3592 | set_bit(STATUS_RF_KILL_SW, &priv->status); |
3593 | IWL_DEBUG_INFO("Radio disabled.\n"); | |
3594 | } | |
3595 | ||
316c30d9 AK |
3596 | /******************** |
3597 | * 8. Setup services | |
3598 | ********************/ | |
0359facc | 3599 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 3600 | iwl_disable_interrupts(priv); |
0359facc | 3601 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 3602 | |
6cd0b1cb HS |
3603 | pci_enable_msi(priv->pci_dev); |
3604 | ||
3605 | err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED, | |
3606 | DRV_NAME, priv); | |
3607 | if (err) { | |
3608 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3609 | goto out_disable_msi; | |
3610 | } | |
5b9f8cd3 | 3611 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 3612 | if (err) { |
15b1687c | 3613 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
6ba87956 | 3614 | goto out_uninit_drv; |
316c30d9 AK |
3615 | } |
3616 | ||
4e39317d | 3617 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3618 | iwl_setup_rx_handlers(priv); |
316c30d9 | 3619 | |
6ba87956 | 3620 | /********************************** |
6cd0b1cb | 3621 | * 9. Setup and register mac80211 |
6ba87956 TW |
3622 | **********************************/ |
3623 | ||
6cd0b1cb HS |
3624 | /* enable interrupts if needed: hw bug w/a */ |
3625 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
3626 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3627 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3628 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3629 | } | |
3630 | ||
3631 | iwl_enable_interrupts(priv); | |
3632 | ||
6ba87956 TW |
3633 | err = iwl_setup_mac(priv); |
3634 | if (err) | |
3635 | goto out_remove_sysfs; | |
3636 | ||
3637 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
3638 | if (err) | |
15b1687c | 3639 | IWL_ERR(priv, "failed to create debugfs files\n"); |
6ba87956 | 3640 | |
6cd0b1cb HS |
3641 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3642 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3643 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3644 | else | |
3645 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3646 | |
58d0f361 EG |
3647 | err = iwl_rfkill_init(priv); |
3648 | if (err) | |
15b1687c | 3649 | IWL_ERR(priv, "Unable to initialize RFKILL system. " |
58d0f361 | 3650 | "Ignoring error: %d\n", err); |
6cd0b1cb HS |
3651 | else |
3652 | iwl_rfkill_set_hw_state(priv); | |
3653 | ||
58d0f361 | 3654 | iwl_power_initialize(priv); |
b481de9c ZY |
3655 | return 0; |
3656 | ||
316c30d9 | 3657 | out_remove_sysfs: |
5b9f8cd3 | 3658 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
6cd0b1cb HS |
3659 | out_disable_msi: |
3660 | pci_disable_msi(priv->pci_dev); | |
3661 | pci_disable_device(priv->pci_dev); | |
6ba87956 TW |
3662 | out_uninit_drv: |
3663 | iwl_uninit_drv(priv); | |
073d3f5f TW |
3664 | out_free_eeprom: |
3665 | iwl_eeprom_free(priv); | |
b481de9c ZY |
3666 | out_iounmap: |
3667 | pci_iounmap(pdev, priv->hw_base); | |
3668 | out_pci_release_regions: | |
3669 | pci_release_regions(pdev); | |
316c30d9 | 3670 | pci_set_drvdata(pdev, NULL); |
b481de9c ZY |
3671 | out_pci_disable_device: |
3672 | pci_disable_device(pdev); | |
b481de9c ZY |
3673 | out_ieee80211_free_hw: |
3674 | ieee80211_free_hw(priv->hw); | |
3675 | out: | |
3676 | return err; | |
3677 | } | |
3678 | ||
5b9f8cd3 | 3679 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 3680 | { |
c79dd5b5 | 3681 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 3682 | unsigned long flags; |
b481de9c ZY |
3683 | |
3684 | if (!priv) | |
3685 | return; | |
3686 | ||
3687 | IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n"); | |
3688 | ||
67249625 | 3689 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 3690 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 3691 | |
5b9f8cd3 EG |
3692 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3693 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3694 | * we need to set STATUS_EXIT_PENDING bit. |
3695 | */ | |
3696 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
3697 | if (priv->mac80211_registered) { |
3698 | ieee80211_unregister_hw(priv->hw); | |
3699 | priv->mac80211_registered = 0; | |
0b124c31 | 3700 | } else { |
5b9f8cd3 | 3701 | iwl_down(priv); |
c4f55232 RR |
3702 | } |
3703 | ||
0359facc MA |
3704 | /* make sure we flush any pending irq or |
3705 | * tasklet for the driver | |
3706 | */ | |
3707 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3708 | iwl_disable_interrupts(priv); |
0359facc MA |
3709 | spin_unlock_irqrestore(&priv->lock, flags); |
3710 | ||
3711 | iwl_synchronize_irq(priv); | |
3712 | ||
58d0f361 | 3713 | iwl_rfkill_unregister(priv); |
5b9f8cd3 | 3714 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3715 | |
3716 | if (priv->rxq.bd) | |
a55360e4 | 3717 | iwl_rx_queue_free(priv, &priv->rxq); |
1053d35f | 3718 | iwl_hw_txq_ctx_free(priv); |
b481de9c | 3719 | |
37deb2a0 | 3720 | iwl_clear_stations_table(priv); |
073d3f5f | 3721 | iwl_eeprom_free(priv); |
b481de9c | 3722 | |
b481de9c | 3723 | |
948c171c MA |
3724 | /*netif_stop_queue(dev); */ |
3725 | flush_workqueue(priv->workqueue); | |
3726 | ||
5b9f8cd3 | 3727 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3728 | * priv->workqueue... so we can't take down the workqueue |
3729 | * until now... */ | |
3730 | destroy_workqueue(priv->workqueue); | |
3731 | priv->workqueue = NULL; | |
3732 | ||
6cd0b1cb HS |
3733 | free_irq(priv->pci_dev->irq, priv); |
3734 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3735 | pci_iounmap(pdev, priv->hw_base); |
3736 | pci_release_regions(pdev); | |
3737 | pci_disable_device(pdev); | |
3738 | pci_set_drvdata(pdev, NULL); | |
3739 | ||
6ba87956 | 3740 | iwl_uninit_drv(priv); |
b481de9c ZY |
3741 | |
3742 | if (priv->ibss_beacon) | |
3743 | dev_kfree_skb(priv->ibss_beacon); | |
3744 | ||
3745 | ieee80211_free_hw(priv->hw); | |
3746 | } | |
3747 | ||
3748 | #ifdef CONFIG_PM | |
3749 | ||
5b9f8cd3 | 3750 | static int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
b481de9c | 3751 | { |
c79dd5b5 | 3752 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
b481de9c | 3753 | |
e655b9f0 ZY |
3754 | if (priv->is_open) { |
3755 | set_bit(STATUS_IN_SUSPEND, &priv->status); | |
5b9f8cd3 | 3756 | iwl_mac_stop(priv->hw); |
e655b9f0 ZY |
3757 | priv->is_open = 1; |
3758 | } | |
b481de9c | 3759 | |
6cd0b1cb HS |
3760 | pci_save_state(pdev); |
3761 | pci_disable_device(pdev); | |
b481de9c ZY |
3762 | pci_set_power_state(pdev, PCI_D3hot); |
3763 | ||
b481de9c ZY |
3764 | return 0; |
3765 | } | |
3766 | ||
5b9f8cd3 | 3767 | static int iwl_pci_resume(struct pci_dev *pdev) |
b481de9c | 3768 | { |
c79dd5b5 | 3769 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
450154e4 | 3770 | int ret; |
b481de9c | 3771 | |
b481de9c | 3772 | pci_set_power_state(pdev, PCI_D0); |
450154e4 WT |
3773 | ret = pci_enable_device(pdev); |
3774 | if (ret) | |
3775 | return ret; | |
6cd0b1cb HS |
3776 | pci_restore_state(pdev); |
3777 | iwl_enable_interrupts(priv); | |
b481de9c | 3778 | |
e655b9f0 | 3779 | if (priv->is_open) |
5b9f8cd3 | 3780 | iwl_mac_start(priv->hw); |
b481de9c | 3781 | |
e655b9f0 | 3782 | clear_bit(STATUS_IN_SUSPEND, &priv->status); |
b481de9c ZY |
3783 | return 0; |
3784 | } | |
3785 | ||
3786 | #endif /* CONFIG_PM */ | |
3787 | ||
3788 | /***************************************************************************** | |
3789 | * | |
3790 | * driver and module entry point | |
3791 | * | |
3792 | *****************************************************************************/ | |
3793 | ||
fed9017e RR |
3794 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
3795 | static struct pci_device_id iwl_hw_card_ids[] = { | |
4fc22b21 | 3796 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
3797 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
3798 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 3799 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 3800 | #ifdef CONFIG_IWL5000 |
47408639 EK |
3801 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)}, |
3802 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)}, | |
3803 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, | |
3804 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, | |
3805 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, | |
3806 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, | |
5a6a256e | 3807 | {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)}, |
47408639 EK |
3808 | {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)}, |
3809 | {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)}, | |
3810 | {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)}, | |
e96a8495 TW |
3811 | /* 5350 WiFi/WiMax */ |
3812 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, | |
3813 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, | |
3814 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, | |
7100e924 TW |
3815 | /* 5150 Wifi/WiMax */ |
3816 | {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
3817 | {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
e1228374 JS |
3818 | /* 6000/6050 Series */ |
3819 | {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)}, | |
3820 | {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)}, | |
3821 | {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)}, | |
3822 | {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)}, | |
3823 | {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)}, | |
3824 | {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)}, | |
3825 | {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)}, | |
3826 | {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)}, | |
3827 | {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
3828 | {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)}, | |
3829 | {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
c5d05698 JS |
3830 | /* 100 Series WiFi */ |
3831 | {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl100_bgn_cfg)}, | |
3832 | {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl100_bgn_cfg)}, | |
5a6a256e | 3833 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 3834 | |
fed9017e RR |
3835 | {0} |
3836 | }; | |
3837 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
3838 | ||
3839 | static struct pci_driver iwl_driver = { | |
b481de9c | 3840 | .name = DRV_NAME, |
fed9017e | 3841 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
3842 | .probe = iwl_pci_probe, |
3843 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 3844 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
3845 | .suspend = iwl_pci_suspend, |
3846 | .resume = iwl_pci_resume, | |
b481de9c ZY |
3847 | #endif |
3848 | }; | |
3849 | ||
5b9f8cd3 | 3850 | static int __init iwl_init(void) |
b481de9c ZY |
3851 | { |
3852 | ||
3853 | int ret; | |
3854 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3855 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3856 | |
e227ceac | 3857 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3858 | if (ret) { |
a3139c59 SO |
3859 | printk(KERN_ERR DRV_NAME |
3860 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
3861 | return ret; |
3862 | } | |
3863 | ||
fed9017e | 3864 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 3865 | if (ret) { |
a3139c59 | 3866 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 3867 | goto error_register; |
b481de9c | 3868 | } |
b481de9c ZY |
3869 | |
3870 | return ret; | |
897e1cf2 | 3871 | |
897e1cf2 | 3872 | error_register: |
e227ceac | 3873 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3874 | return ret; |
b481de9c ZY |
3875 | } |
3876 | ||
5b9f8cd3 | 3877 | static void __exit iwl_exit(void) |
b481de9c | 3878 | { |
fed9017e | 3879 | pci_unregister_driver(&iwl_driver); |
e227ceac | 3880 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3881 | } |
3882 | ||
5b9f8cd3 EG |
3883 | module_exit(iwl_exit); |
3884 | module_init(iwl_init); |