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iwl3945: Add restart_fw module parameter
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
b481de9c 44#include "iwl-3945.h"
e6148917 45#include "iwl-eeprom.h"
5d08cd1d 46#include "iwl-helpers.h"
5747d47f 47#include "iwl-core.h"
d9829a67 48#include "iwl-agn-rs.h"
b481de9c
ZY		 49
50#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
51 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
52 IWL_RATE_##r##M_IEEE, \
53 IWL_RATE_##ip##M_INDEX, \
54 IWL_RATE_##in##M_INDEX, \
55 IWL_RATE_##rp##M_INDEX, \
56 IWL_RATE_##rn##M_INDEX, \
57 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 58 IWL_RATE_##np##M_INDEX, \
59 IWL_RATE_##r##M_INDEX_TABLE, \
60 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 61
62/*
63 * Parameter order:
64 * rate, prev rate, next rate, prev tgg rate, next tgg rate
65 *
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
68 *
69 */
d9829a67 70const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 71 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 75 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 83};
84
bb8c093b 85/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 86#define IWL_EVT_DISABLE (0)
87#define IWL_EVT_DISABLE_SIZE (1532/32)
88
89/**
bb8c093b 90 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 91 *
92 * Disable an event by writing "1"s into "disable"
93 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
94 * Default values of 0 enable uCode events to be logged.
95 * Use for only special debugging. This function is just a placeholder as-is,
96 * you'll need to provide the special bits! ...
97 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 98void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 99{
af7cca2a 100 int ret;
b481de9c
ZY		 101 int i;
102 u32 base; /* SRAM address of event log header */
103 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
104 u32 array_size; /* # of u32 entries in array */
105 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
106 0x00000000, /* 31 - 0 Event id numbers */
107 0x00000000, /* 63 - 32 */
108 0x00000000, /* 95 - 64 */
109 0x00000000, /* 127 - 96 */
110 0x00000000, /* 159 - 128 */
111 0x00000000, /* 191 - 160 */
112 0x00000000, /* 223 - 192 */
113 0x00000000, /* 255 - 224 */
114 0x00000000, /* 287 - 256 */
115 0x00000000, /* 319 - 288 */
116 0x00000000, /* 351 - 320 */
117 0x00000000, /* 383 - 352 */
118 0x00000000, /* 415 - 384 */
119 0x00000000, /* 447 - 416 */
120 0x00000000, /* 479 - 448 */
121 0x00000000, /* 511 - 480 */
122 0x00000000, /* 543 - 512 */
123 0x00000000, /* 575 - 544 */
124 0x00000000, /* 607 - 576 */
125 0x00000000, /* 639 - 608 */
126 0x00000000, /* 671 - 640 */
127 0x00000000, /* 703 - 672 */
128 0x00000000, /* 735 - 704 */
129 0x00000000, /* 767 - 736 */
130 0x00000000, /* 799 - 768 */
131 0x00000000, /* 831 - 800 */
132 0x00000000, /* 863 - 832 */
133 0x00000000, /* 895 - 864 */
134 0x00000000, /* 927 - 896 */
135 0x00000000, /* 959 - 928 */
136 0x00000000, /* 991 - 960 */
137 0x00000000, /* 1023 - 992 */
138 0x00000000, /* 1055 - 1024 */
139 0x00000000, /* 1087 - 1056 */
140 0x00000000, /* 1119 - 1088 */
141 0x00000000, /* 1151 - 1120 */
142 0x00000000, /* 1183 - 1152 */
143 0x00000000, /* 1215 - 1184 */
144 0x00000000, /* 1247 - 1216 */
145 0x00000000, /* 1279 - 1248 */
146 0x00000000, /* 1311 - 1280 */
147 0x00000000, /* 1343 - 1312 */
148 0x00000000, /* 1375 - 1344 */
149 0x00000000, /* 1407 - 1376 */
150 0x00000000, /* 1439 - 1408 */
151 0x00000000, /* 1471 - 1440 */
152 0x00000000, /* 1503 - 1472 */
153 };
154
155 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 156 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 157 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 158 return;
159 }
160
5d49f498 161 ret = iwl_grab_nic_access(priv);
af7cca2a 162 if (ret) {
39aadf8c 163 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 164 return;
165 }
166
5d49f498
AK		 167 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
168 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
169 iwl_release_nic_access(priv);
b481de9c
ZY		 170
171 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
172 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
173 disable_ptr);
5d49f498 174 ret = iwl_grab_nic_access(priv);
b481de9c 175 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 176 iwl_write_targ_mem(priv,
af7cca2a
TW		 177 disable_ptr + (i * sizeof(u32)),
178 evt_disable[i]);
b481de9c 179
5d49f498 180 iwl_release_nic_access(priv);
b481de9c
ZY		 181 } else {
182 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
183 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
184 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
185 disable_ptr, array_size);
186 }
187
188}
189
17744ff6
TW		 190static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
191{
192 int idx;
193
194 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
195 if (iwl3945_rates[idx].plcp == plcp)
196 return idx;
197 return -1;
198}
199
d08853a3 200#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 201#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
202
203static const char *iwl3945_get_tx_fail_reason(u32 status)
204{
205 switch (status & TX_STATUS_MSK) {
206 case TX_STATUS_SUCCESS:
207 return "SUCCESS";
208 TX_STATUS_ENTRY(SHORT_LIMIT);
209 TX_STATUS_ENTRY(LONG_LIMIT);
210 TX_STATUS_ENTRY(FIFO_UNDERRUN);
211 TX_STATUS_ENTRY(MGMNT_ABORT);
212 TX_STATUS_ENTRY(NEXT_FRAG);
213 TX_STATUS_ENTRY(LIFE_EXPIRE);
214 TX_STATUS_ENTRY(DEST_PS);
215 TX_STATUS_ENTRY(ABORTED);
216 TX_STATUS_ENTRY(BT_RETRY);
217 TX_STATUS_ENTRY(STA_INVALID);
218 TX_STATUS_ENTRY(FRAG_DROPPED);
219 TX_STATUS_ENTRY(TID_DISABLE);
220 TX_STATUS_ENTRY(FRAME_FLUSHED);
221 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
222 TX_STATUS_ENTRY(TX_LOCKED);
223 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
224 }
225
226 return "UNKNOWN";
227}
228#else
229static inline const char *iwl3945_get_tx_fail_reason(u32 status)
230{
231 return "";
232}
233#endif
234
e6a9854b
JB		 235/*
236 * get ieee prev rate from rate scale table.
237 * for A and B mode we need to overright prev
238 * value
239 */
4a8a4322 240int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 241{
242 int next_rate = iwl3945_get_prev_ieee_rate(rate);
243
244 switch (priv->band) {
245 case IEEE80211_BAND_5GHZ:
246 if (rate == IWL_RATE_12M_INDEX)
247 next_rate = IWL_RATE_9M_INDEX;
248 else if (rate == IWL_RATE_6M_INDEX)
249 next_rate = IWL_RATE_6M_INDEX;
250 break;
7262796a
AM		 251 case IEEE80211_BAND_2GHZ:
252 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
253 iwl3945_is_associated(priv)) {
254 if (rate == IWL_RATE_11M_INDEX)
255 next_rate = IWL_RATE_5M_INDEX;
256 }
e6a9854b 257 break;
7262796a 258
e6a9854b
JB		 259 default:
260 break;
261 }
262
263 return next_rate;
264}
265
91c066f2
TW		 266
267/**
268 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
269 *
270 * When FW advances 'R' index, all entries between old and new 'R' index
271 * need to be reclaimed. As result, some free space forms. If there is
272 * enough free space (> low mark), wake the stack that feeds us.
273 */
4a8a4322 274static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 275 int txq_id, int index)
276{
188cf6c7 277 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 278 struct iwl_queue *q = &txq->q;
dbb6654c 279 struct iwl_tx_info *tx_info;
91c066f2
TW		 280
281 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
282
283 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
284 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
285
286 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 287 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 288 tx_info->skb[0] = NULL;
7aaa1d79 289 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 290 }
291
d20b3c65 292 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 293 (txq_id != IWL_CMD_QUEUE_NUM) &&
294 priv->mac80211_registered)
295 ieee80211_wake_queue(priv->hw, txq_id);
296}
297
298/**
299 * iwl3945_rx_reply_tx - Handle Tx response
300 */
4a8a4322 301static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 302 struct iwl_rx_mem_buffer *rxb)
91c066f2 303{
3d24a9f7 304 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 305 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
306 int txq_id = SEQ_TO_QUEUE(sequence);
307 int index = SEQ_TO_INDEX(sequence);
188cf6c7 308 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 309 struct ieee80211_tx_info *info;
91c066f2
TW		 310 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
311 u32 status = le32_to_cpu(tx_resp->status);
312 int rate_idx;
74221d07 313 int fail;
91c066f2 314
625a381a 315 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 316 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 317 "is out of range [0-%d] %d %d\n", txq_id,
318 index, txq->q.n_bd, txq->q.write_ptr,
319 txq->q.read_ptr);
320 return;
321 }
322
e039fa4a 323 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 324 ieee80211_tx_info_clear_status(info);
325
326 /* Fill the MRR chain with some info about on-chip retransmissions */
327 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
328 if (info->band == IEEE80211_BAND_5GHZ)
329 rate_idx -= IWL_FIRST_OFDM_RATE;
330
331 fail = tx_resp->failure_frame;
74221d07
AM		 332
333 info->status.rates[0].idx = rate_idx;
334 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 335
91c066f2 336 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 337 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
338 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 339
340 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
341 txq_id, iwl3945_get_tx_fail_reason(status), status,
342 tx_resp->rate, tx_resp->failure_frame);
343
91c066f2
TW		 344 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
345 iwl3945_tx_queue_reclaim(priv, txq_id, index);
346
347 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 348 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 349}
350
351
352
b481de9c
ZY		 353/*****************************************************************************
354 *
355 * Intel PRO/Wireless 3945ABG/BG Network Connection
356 *
357 * RX handler implementations
358 *
b481de9c
ZY		 359 *****************************************************************************/
360
4a8a4322 361void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 362{
3d24a9f7 363 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 364 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 365 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 366 le32_to_cpu(pkt->len));
367
f2c7e521 368 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 369
ab53d8af
MA		 370 iwl3945_led_background(priv);
371
b481de9c
ZY		 372 priv->last_statistics_time = jiffies;
373}
374
17744ff6
TW		 375/******************************************************************************
376 *
377 * Misc. internal state and helper functions
378 *
379 ******************************************************************************/
d08853a3 380#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 381
382/**
383 * iwl3945_report_frame - dump frame to syslog during debug sessions
384 *
385 * You may hack this function to show different aspects of received frames,
386 * including selective frame dumps.
387 * group100 parameter selects whether to show 1 out of 100 good frames.
388 */
d08853a3 389static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 390 struct iwl_rx_packet *pkt,
17744ff6
TW		 391 struct ieee80211_hdr *header, int group100)
392{
393 u32 to_us;
394 u32 print_summary = 0;
395 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
396 u32 hundred = 0;
397 u32 dataframe = 0;
fd7c8a40 398 __le16 fc;
17744ff6
TW		 399 u16 seq_ctl;
400 u16 channel;
401 u16 phy_flags;
402 u16 length;
403 u16 status;
404 u16 bcn_tmr;
405 u32 tsf_low;
406 u64 tsf;
407 u8 rssi;
408 u8 agc;
409 u16 sig_avg;
410 u16 noise_diff;
411 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
412 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
413 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
414 u8 *data = IWL_RX_DATA(pkt);
415
416 /* MAC header */
fd7c8a40 417 fc = header->frame_control;
17744ff6
TW		 418 seq_ctl = le16_to_cpu(header->seq_ctrl);
419
420 /* metadata */
421 channel = le16_to_cpu(rx_hdr->channel);
422 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
423 length = le16_to_cpu(rx_hdr->len);
424
425 /* end-of-frame status and timestamp */
426 status = le32_to_cpu(rx_end->status);
427 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
428 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
429 tsf = le64_to_cpu(rx_end->timestamp);
430
431 /* signal statistics */
432 rssi = rx_stats->rssi;
433 agc = rx_stats->agc;
434 sig_avg = le16_to_cpu(rx_stats->sig_avg);
435 noise_diff = le16_to_cpu(rx_stats->noise_diff);
436
437 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
438
439 /* if data frame is to us and all is good,
440 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 441 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
442 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 443 dataframe = 1;
444 if (!group100)
445 print_summary = 1; /* print each frame */
446 else if (priv->framecnt_to_us < 100) {
447 priv->framecnt_to_us++;
448 print_summary = 0;
449 } else {
450 priv->framecnt_to_us = 0;
451 print_summary = 1;
452 hundred = 1;
453 }
454 } else {
455 /* print summary for all other frames */
456 print_summary = 1;
457 }
458
459 if (print_summary) {
460 char *title;
0ff1cca0 461 int rate;
17744ff6
TW		 462
463 if (hundred)
464 title = "100Frames";
fd7c8a40 465 else if (ieee80211_has_retry(fc))
17744ff6 466 title = "Retry";
fd7c8a40 467 else if (ieee80211_is_assoc_resp(fc))
17744ff6 468 title = "AscRsp";
fd7c8a40 469 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 470 title = "RasRsp";
fd7c8a40 471 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 472 title = "PrbRsp";
473 print_dump = 1; /* dump frame contents */
474 } else if (ieee80211_is_beacon(fc)) {
475 title = "Beacon";
476 print_dump = 1; /* dump frame contents */
477 } else if (ieee80211_is_atim(fc))
478 title = "ATIM";
479 else if (ieee80211_is_auth(fc))
480 title = "Auth";
481 else if (ieee80211_is_deauth(fc))
482 title = "DeAuth";
483 else if (ieee80211_is_disassoc(fc))
484 title = "DisAssoc";
485 else
486 title = "Frame";
487
488 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
489 if (rate == -1)
490 rate = 0;
491 else
492 rate = iwl3945_rates[rate].ieee / 2;
493
494 /* print frame summary.
495 * MAC addresses show just the last byte (for brevity),
496 * but you can hack it to show more, if you'd like to. */
497 if (dataframe)
498 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 499 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 500 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 501 length, rssi, channel, rate);
502 else {
503 /* src/dst addresses assume managed mode */
504 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
505 "src=0x%02x, rssi=%u, tim=%lu usec, "
506 "phy=0x%02x, chnl=%d\n",
fd7c8a40 507 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 508 header->addr3[5], rssi,
509 tsf_low - priv->scan_start_tsf,
510 phy_flags, channel);
511 }
512 }
513 if (print_dump)
40b8ec0b 514 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 515}
d08853a3
SO		 516
517static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
518 struct iwl_rx_packet *pkt,
519 struct ieee80211_hdr *header, int group100)
520{
521 if (priv->debug_level & IWL_DL_RX)
522 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
523}
524
17744ff6 525#else
4a8a4322 526static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 527 struct iwl_rx_packet *pkt,
17744ff6
TW		 528 struct ieee80211_hdr *header, int group100)
529{
530}
531#endif
532
4bd9b4f3 533/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 534static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 535 struct ieee80211_hdr *header)
536{
537 /* Filter incoming packets to determine if they are targeted toward
538 * this network, discarding packets coming from ourselves */
539 switch (priv->iw_mode) {
05c914fe 540 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 541 /* packets to our IBSS update information */
542 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 543 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 544 /* packets to our IBSS update information */
545 return !compare_ether_addr(header->addr2, priv->bssid);
546 default:
547 return 1;
548 }
549}
17744ff6 550
4a8a4322 551static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 552 struct iwl_rx_mem_buffer *rxb,
12342c47 553 struct ieee80211_rx_status *stats)
b481de9c 554{
3d24a9f7 555 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
699669f3 556#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 557 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 558#endif
bb8c093b
CH		 559 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
560 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 561 short len = le16_to_cpu(rx_hdr->len);
562
563 /* We received data from the HW, so stop the watchdog */
3d24a9f7 564 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
b481de9c
ZY		 565 IWL_DEBUG_DROP("Corruption detected!\n");
566 return;
567 }
568
569 /* We only process data packets if the interface is open */
570 if (unlikely(!priv->is_open)) {
571 IWL_DEBUG_DROP_LIMIT
572 ("Dropping packet while interface is not open.\n");
573 return;
574 }
b481de9c
ZY		 575
576 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
577 /* Set the size of the skb to the size of the frame */
578 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
579
9c74d9fb 580 if (!iwl3945_mod_params.sw_crypto)
bb8c093b 581 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 582 le32_to_cpu(rx_end->status), stats);
583
ab53d8af 584#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 585 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 586 priv->rxtxpackets += len;
587#endif
b481de9c
ZY		 588 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
589 rxb->skb = NULL;
590}
591
7878a5a4
MA		 592#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
593
4a8a4322 594static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 595 struct iwl_rx_mem_buffer *rxb)
b481de9c 596{
17744ff6
TW		 597 struct ieee80211_hdr *header;
598 struct ieee80211_rx_status rx_status;
3d24a9f7 599 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 600 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
601 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
602 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 603 int snr;
b481de9c
ZY		 604 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
605 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 606 u8 network_packet;
17744ff6 607
17744ff6
TW		 608 rx_status.flag = 0;
609 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 610 rx_status.freq =
c0186078 611 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 612 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
613 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
614
615 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 616 if (rx_status.band == IEEE80211_BAND_5GHZ)
617 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 618
6f0a2c4d
BR		 619 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
620 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
621
622 /* set the preamble flag if appropriate */
623 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
624 rx_status.flag |= RX_FLAG_SHORTPRE;
625
b481de9c
ZY		 626 if ((unlikely(rx_stats->phy_count > 20))) {
627 IWL_DEBUG_DROP
628 ("dsp size out of range [0,20]: "
629 "%d/n", rx_stats->phy_count);
630 return;
631 }
632
633 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
634 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
635 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
636 return;
637 }
638
56decd3c 639
b481de9c
ZY		 640
641 /* Convert 3945's rssi indicator to dBm */
250bdd21 642 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 643
644 /* Set default noise value to -127 */
645 if (priv->last_rx_noise == 0)
646 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
647
648 /* 3945 provides noise info for OFDM frames only.
649 * sig_avg and noise_diff are measured by the 3945's digital signal
650 * processor (DSP), and indicate linear levels of signal level and
651 * distortion/noise within the packet preamble after
652 * automatic gain control (AGC). sig_avg should stay fairly
653 * constant if the radio's AGC is working well.
654 * Since these values are linear (not dB or dBm), linear
655 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
656 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
657 * to obtain noise level in dBm.
17744ff6 658 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 659 if (rx_stats_noise_diff) {
660 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 661 rx_status.noise = rx_status.signal -
17744ff6 662 iwl3945_calc_db_from_ratio(snr);
566bfe5a 663 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 664 rx_status.noise);
b481de9c
ZY		 665
666 /* If noise info not available, calculate signal quality indicator (%)
667 * using just the dBm signal level. */
668 } else {
17744ff6 669 rx_status.noise = priv->last_rx_noise;
566bfe5a 670 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 671 }
672
673
674 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 675 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 676 rx_stats_sig_avg, rx_stats_noise_diff);
677
b481de9c
ZY		 678 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
679
bb8c093b 680 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 681
17744ff6
TW		 682 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
683 network_packet ? '*' : ' ',
684 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 685 rx_status.signal, rx_status.signal,
686 rx_status.noise, rx_status.rate_idx);
b481de9c 687
d08853a3
SO		 688 /* Set "1" to report good data frames in groups of 100 */
689 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 690
691 if (network_packet) {
692 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
693 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 694 priv->last_rx_rssi = rx_status.signal;
17744ff6 695 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 696 }
697
12e5e22d 698 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 699}
700
7aaa1d79
SO		 701int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
702 struct iwl_tx_queue *txq,
703 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 704{
705 int count;
7aaa1d79 706 struct iwl_queue *q;
59606ffa 707 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 708
709 q = &txq->q;
59606ffa
SO		 710 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
711 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 712
713 if (reset)
714 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 715
716 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 717
718 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 719 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 720 NUM_TFD_CHUNKS);
721 return -EINVAL;
722 }
723
dbb6654c
WT		 724 tfd->tbs[count].addr = cpu_to_le32(addr);
725 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 726
727 count++;
728
729 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
730 TFD_CTL_PAD_SET(pad));
731
732 return 0;
733}
734
735/**
bb8c093b 736 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 737 *
738 * Does NOT advance any indexes
739 */
7aaa1d79 740void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 741{
59606ffa 742 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
dbb6654c 743 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
b481de9c
ZY		 744 struct pci_dev *dev = priv->pci_dev;
745 int i;
746 int counter;
747
748 /* classify bd */
749 if (txq->q.id == IWL_CMD_QUEUE_NUM)
750 /* nothing to cleanup after for host commands */
7aaa1d79 751 return;
b481de9c
ZY		 752
753 /* sanity check */
dbb6654c 754 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 755 if (counter > NUM_TFD_CHUNKS) {
15b1687c 756 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 757 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 758 return;
b481de9c
ZY		 759 }
760
761 /* unmap chunks if any */
762
763 for (i = 1; i < counter; i++) {
dbb6654c
WT		 764 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
765 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 766 if (txq->txb[txq->q.read_ptr].skb[0]) {
767 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
768 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 769 /* Can be called from interrupt context */
770 dev_kfree_skb_any(skb);
fc4b6853 771 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 772 }
773 }
774 }
7aaa1d79 775 return ;
b481de9c
ZY		 776}
777
4a8a4322 778u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 779{
c93007ef 780 int i, start = IWL_AP_ID;
b481de9c
ZY		 781 int ret = IWL_INVALID_STATION;
782 unsigned long flags;
783
c93007ef
SO		 784 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
785 (priv->iw_mode == NL80211_IFTYPE_AP))
786 start = IWL_STA_ID;
787
788 if (is_broadcast_ether_addr(addr))
3832ec9d 789 return priv->hw_params.bcast_sta_id;
c93007ef 790
b481de9c 791 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 792 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 793 if ((priv->stations_39[i].used) &&
b481de9c 794 (!compare_ether_addr
f2c7e521 795 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 796 ret = i;
797 goto out;
798 }
799
e174961c
JB		 800 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
801 addr, priv->num_stations);
b481de9c
ZY		 802 out:
803 spin_unlock_irqrestore(&priv->sta_lock, flags);
804 return ret;
805}
806
807/**
bb8c093b 808 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 809 *
810*/
c2d79b48 811void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 812 struct ieee80211_tx_info *info,
b481de9c
ZY		 813 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
814{
e039fa4a 815 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 816 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 817 u16 rate_mask;
818 int rate;
819 u8 rts_retry_limit;
820 u8 data_retry_limit;
821 __le32 tx_flags;
fd7c8a40 822 __le16 fc = hdr->frame_control;
c2d79b48 823 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 824
bb8c093b 825 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 826 tx_flags = tx->tx_flags;
b481de9c
ZY		 827
828 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 829 * in this running context */
b481de9c
ZY		 830 rate_mask = IWL_RATES_MASK;
831
b481de9c
ZY		 832 if (tx_id >= IWL_CMD_QUEUE_NUM)
833 rts_retry_limit = 3;
834 else
835 rts_retry_limit = 7;
836
fd7c8a40 837 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 838 data_retry_limit = 3;
839 if (data_retry_limit < rts_retry_limit)
840 rts_retry_limit = data_retry_limit;
841 } else
842 data_retry_limit = IWL_DEFAULT_TX_RETRY;
843
844 if (priv->data_retry_limit != -1)
845 data_retry_limit = priv->data_retry_limit;
846
fd7c8a40
HH		 847 if (ieee80211_is_mgmt(fc)) {
848 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
849 case cpu_to_le16(IEEE80211_STYPE_AUTH):
850 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
851 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
852 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 853 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
854 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
855 tx_flags |= TX_CMD_FLG_CTS_MSK;
856 }
857 break;
858 default:
859 break;
860 }
861 }
862
c2d79b48
WT		 863 tx->rts_retry_limit = rts_retry_limit;
864 tx->data_retry_limit = data_retry_limit;
865 tx->rate = rate;
866 tx->tx_flags = tx_flags;
b481de9c
ZY		 867
868 /* OFDM */
c2d79b48 869 tx->supp_rates[0] =
14577f23 870 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 871
872 /* CCK */
c2d79b48 873 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 874
875 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
876 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 877 tx->rate, le32_to_cpu(tx->tx_flags),
878 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 879}
880
4a8a4322 881u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 882{
883 unsigned long flags_spin;
bb8c093b 884 struct iwl3945_station_entry *station;
b481de9c
ZY		 885
886 if (sta_id == IWL_INVALID_STATION)
887 return IWL_INVALID_STATION;
888
889 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 890 station = &priv->stations_39[sta_id];
b481de9c
ZY		 891
892 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
893 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 894 station->sta.mode = STA_CONTROL_MODIFY_MSK;
895
896 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
897
bb8c093b 898 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 899 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
900 sta_id, tx_rate);
901 return sta_id;
902}
903
854682ed 904static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c
ZY		 905{
906 int rc;
907 unsigned long flags;
908
909 spin_lock_irqsave(&priv->lock, flags);
5d49f498 910 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 911 if (rc) {
912 spin_unlock_irqrestore(&priv->lock, flags);
913 return rc;
914 }
915
854682ed 916 if (src == IWL_PWR_SRC_VAUX) {
b481de9c
ZY		 917 u32 val;
918
919 rc = pci_read_config_dword(priv->pci_dev,
920 PCI_POWER_SOURCE, &val);
921 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
5d49f498 922 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 923 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
924 ~APMG_PS_CTRL_MSK_PWR_SRC);
5d49f498 925 iwl_release_nic_access(priv);
b481de9c 926
5d49f498 927 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 928 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
929 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
930 } else
5d49f498 931 iwl_release_nic_access(priv);
b481de9c 932 } else {
5d49f498 933 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 934 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
935 ~APMG_PS_CTRL_MSK_PWR_SRC);
936
5d49f498
AK		 937 iwl_release_nic_access(priv);
938 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 939 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
940 }
941 spin_unlock_irqrestore(&priv->lock, flags);
942
943 return rc;
944}
945
4a8a4322 946static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY		 947{
948 int rc;
949 unsigned long flags;
950
951 spin_lock_irqsave(&priv->lock, flags);
5d49f498 952 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 953 if (rc) {
954 spin_unlock_irqrestore(&priv->lock, flags);
955 return rc;
956 }
957
5d49f498 958 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 959 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 960 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
961 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 962 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
963 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
964 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
965 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
966 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
967 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
968 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
969 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 970
971 /* fake read to flush all prev I/O */
5d49f498 972 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 973
5d49f498 974 iwl_release_nic_access(priv);
b481de9c
ZY		 975 spin_unlock_irqrestore(&priv->lock, flags);
976
977 return 0;
978}
979
4a8a4322 980static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c
ZY		 981{
982 int rc;
983 unsigned long flags;
984
985 spin_lock_irqsave(&priv->lock, flags);
5d49f498 986 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 987 if (rc) {
988 spin_unlock_irqrestore(&priv->lock, flags);
989 return rc;
990 }
991
992 /* bypass mode */
5d49f498 993 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 994
995 /* RA 0 is active */
5d49f498 996 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 997
998 /* all 6 fifo are active */
5d49f498 999 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1000
5d49f498
AK		 1001 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1002 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1003 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1004 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1005
5d49f498 1006 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 1007 priv->shared_phys);
b481de9c 1008
5d49f498 1009 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1010 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1011 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1012 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1013 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1014 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1015 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1016 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1017
5d49f498 1018 iwl_release_nic_access(priv);
b481de9c
ZY		 1019 spin_unlock_irqrestore(&priv->lock, flags);
1020
1021 return 0;
1022}
1023
1024/**
1025 * iwl3945_txq_ctx_reset - Reset TX queue context
1026 *
1027 * Destroys all DMA structures and initialize them again
1028 */
4a8a4322 1029static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1030{
1031 int rc;
1032 int txq_id, slots_num;
1033
bb8c093b 1034 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1035
1036 /* Tx CMD queue */
1037 rc = iwl3945_tx_reset(priv);
1038 if (rc)
1039 goto error;
1040
1041 /* Tx queue(s) */
1042 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1043 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1044 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 1045 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1046 txq_id);
b481de9c 1047 if (rc) {
15b1687c 1048 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1049 goto error;
1050 }
1051 }
1052
1053 return rc;
1054
1055 error:
bb8c093b 1056 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1057 return rc;
1058}
1059
01ec616d 1060static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1061{
01ec616d 1062 int ret = 0;
b481de9c 1063
bb8c093b 1064 iwl3945_power_init_handle(priv);
b481de9c 1065
5d49f498 1066 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1067 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1068
1069 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1070 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1071 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1072
01ec616d
KA		 1073 /* set "initialization complete" bit to move adapter
1074 * D0U* --> D0A* state */
5d49f498 1075 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d
KA		 1076
1077 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1078 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1079 if (ret < 0) {
b481de9c 1080 IWL_DEBUG_INFO("Failed to init the card\n");
01ec616d 1081 goto out;
b481de9c
ZY		 1082 }
1083
01ec616d
KA		 1084 ret = iwl_grab_nic_access(priv);
1085 if (ret)
1086 goto out;
1087
1088 /* enable DMA */
1089 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1090 APMG_CLK_VAL_BSM_CLK_RQT);
1091
b481de9c 1092 udelay(20);
01ec616d
KA		 1093
1094 /* disable L1-Active */
5d49f498 1095 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1096 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1097
5d49f498 1098 iwl_release_nic_access(priv);
01ec616d
KA		 1099out:
1100 return ret;
1101}
b481de9c 1102
01ec616d
KA		 1103static void iwl3945_nic_config(struct iwl_priv *priv)
1104{
e6148917 1105 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1106 unsigned long flags;
1107 u8 rev_id = 0;
b481de9c 1108
b481de9c
ZY		 1109 spin_lock_irqsave(&priv->lock, flags);
1110
1111 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1112 IWL_DEBUG_INFO("RTP type \n");
1113 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1114 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
5d49f498 1115 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1116 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1117 } else {
6f83eaa1 1118 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
5d49f498 1119 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1120 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1121 }
1122
e6148917 1123 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
b481de9c 1124 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
5d49f498 1125 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1126 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1127 } else
1128 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1129
e6148917 1130 if ((eeprom->board_revision & 0xF0) == 0xD0) {
b481de9c 1131 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
e6148917 1132 eeprom->board_revision);
5d49f498 1133 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1134 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1135 } else {
1136 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
e6148917 1137 eeprom->board_revision);
5d49f498 1138 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1139 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1140 }
1141
e6148917 1142 if (eeprom->almgor_m_version <= 1) {
5d49f498 1143 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1144 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c 1145 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
e6148917 1146 eeprom->almgor_m_version);
b481de9c
ZY		 1147 } else {
1148 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
e6148917 1149 eeprom->almgor_m_version);
5d49f498 1150 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1151 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1152 }
1153 spin_unlock_irqrestore(&priv->lock, flags);
1154
e6148917 1155 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 1156 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1157
e6148917 1158 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c 1159 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1160}
1161
1162int iwl3945_hw_nic_init(struct iwl_priv *priv)
1163{
1164 u8 rev_id;
1165 int rc;
1166 unsigned long flags;
1167 struct iwl_rx_queue *rxq = &priv->rxq;
1168
1169 spin_lock_irqsave(&priv->lock, flags);
1170 priv->cfg->ops->lib->apm_ops.init(priv);
1171 spin_unlock_irqrestore(&priv->lock, flags);
1172
1173 /* Determine HW type */
1174 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1175 if (rc)
1176 return rc;
1177 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1178
854682ed
KA		 1179 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1180 if(rc)
1181 return rc;
1182
01ec616d 1183 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1184
1185 /* Allocate the RX queue, or reset if it is already allocated */
1186 if (!rxq->bd) {
51af3d3f 1187 rc = iwl_rx_queue_alloc(priv);
b481de9c 1188 if (rc) {
15b1687c 1189 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1190 return -ENOMEM;
1191 }
1192 } else
51af3d3f 1193 iwl_rx_queue_reset(priv, rxq);
b481de9c 1194
bb8c093b 1195 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1196
1197 iwl3945_rx_init(priv, rxq);
1198
1199 spin_lock_irqsave(&priv->lock, flags);
1200
1201 /* Look at using this instead:
1202 rxq->need_update = 1;
141c43a3 1203 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1204 */
1205
5d49f498 1206 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1207 if (rc) {
1208 spin_unlock_irqrestore(&priv->lock, flags);
1209 return rc;
1210 }
5d49f498
AK		 1211 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1212 iwl_release_nic_access(priv);
b481de9c
ZY		 1213
1214 spin_unlock_irqrestore(&priv->lock, flags);
1215
1216 rc = iwl3945_txq_ctx_reset(priv);
1217 if (rc)
1218 return rc;
1219
1220 set_bit(STATUS_INIT, &priv->status);
1221
1222 return 0;
1223}
1224
1225/**
bb8c093b 1226 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1227 *
1228 * Destroy all TX DMA queues and structures
1229 */
4a8a4322 1230void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1231{
1232 int txq_id;
1233
1234 /* Tx queues */
1235 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
a8e74e27 1236 iwl_tx_queue_free(priv, txq_id);
b481de9c
ZY		 1237}
1238
4a8a4322 1239void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1240{
bddadf86 1241 int txq_id;
b481de9c
ZY		 1242 unsigned long flags;
1243
1244 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1245 if (iwl_grab_nic_access(priv)) {
b481de9c 1246 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1247 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1248 return;
1249 }
1250
1251 /* stop SCD */
5d49f498 1252 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1253
1254 /* reset TFD queues */
bddadf86 1255 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
5d49f498
AK		 1256 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1257 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1258 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1259 1000);
1260 }
1261
5d49f498 1262 iwl_release_nic_access(priv);
b481de9c
ZY		 1263 spin_unlock_irqrestore(&priv->lock, flags);
1264
bb8c093b 1265 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1266}
1267
01ec616d 1268static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1269{
01ec616d 1270 int ret = 0;
b481de9c
ZY		 1271 unsigned long flags;
1272
1273 spin_lock_irqsave(&priv->lock, flags);
1274
1275 /* set stop master bit */
5d49f498 1276 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1277
01ec616d
KA		 1278 iwl_poll_direct_bit(priv, CSR_RESET,
1279 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1280
01ec616d
KA		 1281 if (ret < 0)
1282 goto out;
b481de9c 1283
01ec616d 1284out:
b481de9c
ZY		 1285 spin_unlock_irqrestore(&priv->lock, flags);
1286 IWL_DEBUG_INFO("stop master\n");
1287
01ec616d
KA		 1288 return ret;
1289}
1290
1291static void iwl3945_apm_stop(struct iwl_priv *priv)
1292{
1293 unsigned long flags;
1294
1295 iwl3945_apm_stop_master(priv);
1296
1297 spin_lock_irqsave(&priv->lock, flags);
1298
1299 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1300
1301 udelay(10);
1302 /* clear "init complete" move adapter D0A* --> D0U state */
1303 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1304 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1305}
1306
e52119c5 1307static int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c
ZY		 1308{
1309 int rc;
1310 unsigned long flags;
1311
01ec616d 1312 iwl3945_apm_stop_master(priv);
b481de9c
ZY		 1313
1314 spin_lock_irqsave(&priv->lock, flags);
1315
5d49f498 1316 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
e9414b6b
AM		 1317 udelay(10);
1318
1319 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 1320
5d49f498 1321 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1322 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1323
5d49f498 1324 rc = iwl_grab_nic_access(priv);
b481de9c 1325 if (!rc) {
5d49f498 1326 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1327 APMG_CLK_VAL_BSM_CLK_RQT);
1328
5d49f498
AK		 1329 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1330 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1331 0xFFFFFFFF);
1332
1333 /* enable DMA */
5d49f498 1334 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1335 APMG_CLK_VAL_DMA_CLK_RQT |
1336 APMG_CLK_VAL_BSM_CLK_RQT);
1337 udelay(10);
1338
5d49f498 1339 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1340 APMG_PS_CTRL_VAL_RESET_REQ);
1341 udelay(5);
5d49f498 1342 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1343 APMG_PS_CTRL_VAL_RESET_REQ);
5d49f498 1344 iwl_release_nic_access(priv);
b481de9c
ZY		 1345 }
1346
1347 /* Clear the 'host command active' bit... */
1348 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1349
1350 wake_up_interruptible(&priv->wait_command_queue);
1351 spin_unlock_irqrestore(&priv->lock, flags);
1352
1353 return rc;
1354}
1355
1356/**
bb8c093b 1357 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1358 * return index delta into power gain settings table
1359*/
bb8c093b 1360static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1361{
1362 return (new_reading - old_reading) * (-11) / 100;
1363}
1364
1365/**
bb8c093b 1366 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1367 */
bb8c093b 1368static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1369{
3ac7f146 1370 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1371}
1372
4a8a4322 1373int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1374{
5d49f498 1375 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1376}
1377
1378/**
bb8c093b 1379 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1380 * get the current temperature by reading from NIC
1381*/
4a8a4322 1382static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1383{
e6148917 1384 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1385 int temperature;
1386
bb8c093b 1387 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1388
1389 /* driver's okay range is -260 to +25.
1390 * human readable okay range is 0 to +285 */
1391 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1392
1393 /* handle insane temp reading */
bb8c093b 1394 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1395 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1396
1397 /* if really really hot(?),
1398 * substitute the 3rd band/group's temp measured at factory */
1399 if (priv->last_temperature > 100)
e6148917 1400 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1401 else /* else use most recent "sane" value from driver */
1402 temperature = priv->last_temperature;
1403 }
1404
1405 return temperature; /* raw, not "human readable" */
1406}
1407
1408/* Adjust Txpower only if temperature variance is greater than threshold.
1409 *
1410 * Both are lower than older versions' 9 degrees */
1411#define IWL_TEMPERATURE_LIMIT_TIMER 6
1412
1413/**
1414 * is_temp_calib_needed - determines if new calibration is needed
1415 *
1416 * records new temperature in tx_mgr->temperature.
1417 * replaces tx_mgr->last_temperature *only* if calib needed
1418 * (assumes caller will actually do the calibration!). */
4a8a4322 1419static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1420{
1421 int temp_diff;
1422
bb8c093b 1423 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1424 temp_diff = priv->temperature - priv->last_temperature;
1425
1426 /* get absolute value */
1427 if (temp_diff < 0) {
1428 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1429 temp_diff = -temp_diff;
1430 } else if (temp_diff == 0)
1431 IWL_DEBUG_POWER("Same temp,\n");
1432 else
1433 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1434
1435 /* if we don't need calibration, *don't* update last_temperature */
1436 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1437 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1438 return 0;
1439 }
1440
1441 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1442
1443 /* assume that caller will actually do calib ...
1444 * update the "last temperature" value */
1445 priv->last_temperature = priv->temperature;
1446 return 1;
1447}
1448
1449#define IWL_MAX_GAIN_ENTRIES 78
1450#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1451#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1452
1453/* radio and DSP power table, each step is 1/2 dB.
1454 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1455static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1456 {
1457 {251, 127}, /* 2.4 GHz, highest power */
1458 {251, 127},
1459 {251, 127},
1460 {251, 127},
1461 {251, 125},
1462 {251, 110},
1463 {251, 105},
1464 {251, 98},
1465 {187, 125},
1466 {187, 115},
1467 {187, 108},
1468 {187, 99},
1469 {243, 119},
1470 {243, 111},
1471 {243, 105},
1472 {243, 97},
1473 {243, 92},
1474 {211, 106},
1475 {211, 100},
1476 {179, 120},
1477 {179, 113},
1478 {179, 107},
1479 {147, 125},
1480 {147, 119},
1481 {147, 112},
1482 {147, 106},
1483 {147, 101},
1484 {147, 97},
1485 {147, 91},
1486 {115, 107},
1487 {235, 121},
1488 {235, 115},
1489 {235, 109},
1490 {203, 127},
1491 {203, 121},
1492 {203, 115},
1493 {203, 108},
1494 {203, 102},
1495 {203, 96},
1496 {203, 92},
1497 {171, 110},
1498 {171, 104},
1499 {171, 98},
1500 {139, 116},
1501 {227, 125},
1502 {227, 119},
1503 {227, 113},
1504 {227, 107},
1505 {227, 101},
1506 {227, 96},
1507 {195, 113},
1508 {195, 106},
1509 {195, 102},
1510 {195, 95},
1511 {163, 113},
1512 {163, 106},
1513 {163, 102},
1514 {163, 95},
1515 {131, 113},
1516 {131, 106},
1517 {131, 102},
1518 {131, 95},
1519 {99, 113},
1520 {99, 106},
1521 {99, 102},
1522 {99, 95},
1523 {67, 113},
1524 {67, 106},
1525 {67, 102},
1526 {67, 95},
1527 {35, 113},
1528 {35, 106},
1529 {35, 102},
1530 {35, 95},
1531 {3, 113},
1532 {3, 106},
1533 {3, 102},
1534 {3, 95} }, /* 2.4 GHz, lowest power */
1535 {
1536 {251, 127}, /* 5.x GHz, highest power */
1537 {251, 120},
1538 {251, 114},
1539 {219, 119},
1540 {219, 101},
1541 {187, 113},
1542 {187, 102},
1543 {155, 114},
1544 {155, 103},
1545 {123, 117},
1546 {123, 107},
1547 {123, 99},
1548 {123, 92},
1549 {91, 108},
1550 {59, 125},
1551 {59, 118},
1552 {59, 109},
1553 {59, 102},
1554 {59, 96},
1555 {59, 90},
1556 {27, 104},
1557 {27, 98},
1558 {27, 92},
1559 {115, 118},
1560 {115, 111},
1561 {115, 104},
1562 {83, 126},
1563 {83, 121},
1564 {83, 113},
1565 {83, 105},
1566 {83, 99},
1567 {51, 118},
1568 {51, 111},
1569 {51, 104},
1570 {51, 98},
1571 {19, 116},
1572 {19, 109},
1573 {19, 102},
1574 {19, 98},
1575 {19, 93},
1576 {171, 113},
1577 {171, 107},
1578 {171, 99},
1579 {139, 120},
1580 {139, 113},
1581 {139, 107},
1582 {139, 99},
1583 {107, 120},
1584 {107, 113},
1585 {107, 107},
1586 {107, 99},
1587 {75, 120},
1588 {75, 113},
1589 {75, 107},
1590 {75, 99},
1591 {43, 120},
1592 {43, 113},
1593 {43, 107},
1594 {43, 99},
1595 {11, 120},
1596 {11, 113},
1597 {11, 107},
1598 {11, 99},
1599 {131, 107},
1600 {131, 99},
1601 {99, 120},
1602 {99, 113},
1603 {99, 107},
1604 {99, 99},
1605 {67, 120},
1606 {67, 113},
1607 {67, 107},
1608 {67, 99},
1609 {35, 120},
1610 {35, 113},
1611 {35, 107},
1612 {35, 99},
1613 {3, 120} } /* 5.x GHz, lowest power */
1614};
1615
bb8c093b 1616static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1617{
1618 if (index < 0)
1619 return 0;
1620 if (index >= IWL_MAX_GAIN_ENTRIES)
1621 return IWL_MAX_GAIN_ENTRIES - 1;
1622 return (u8) index;
1623}
1624
1625/* Kick off thermal recalibration check every 60 seconds */
1626#define REG_RECALIB_PERIOD (60)
1627
1628/**
bb8c093b 1629 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1630 *
1631 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1632 * or 6 Mbit (OFDM) rates.
1633 */
4a8a4322 1634static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1635 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1636 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1637 int band_index)
1638{
bb8c093b 1639 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1640 s8 power;
1641 u8 power_index;
1642
1643 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1644
1645 /* use this channel group's 6Mbit clipping/saturation pwr,
1646 * but cap at regulatory scan power restriction (set during init
1647 * based on eeprom channel data) for this channel. */
14577f23 1648 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1649
1650 /* further limit to user's max power preference.
1651 * FIXME: Other spectrum management power limitations do not
1652 * seem to apply?? */
62ea9c5b 1653 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1654 scan_power_info->requested_power = power;
1655
1656 /* find difference between new scan *power* and current "normal"
1657 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1658 * current "normal" temperature-compensated Tx power *index* for
1659 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1660 * *index*. */
1661 power_index = ch_info->power_info[rate_index].power_table_index
1662 - (power - ch_info->power_info
14577f23 1663 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1664
1665 /* store reference index that we use when adjusting *all* scan
1666 * powers. So we can accommodate user (all channel) or spectrum
1667 * management (single channel) power changes "between" temperature
1668 * feedback compensation procedures.
1669 * don't force fit this reference index into gain table; it may be a
1670 * negative number. This will help avoid errors when we're at
1671 * the lower bounds (highest gains, for warmest temperatures)
1672 * of the table. */
1673
1674 /* don't exceed table bounds for "real" setting */
bb8c093b 1675 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1676
1677 scan_power_info->power_table_index = power_index;
1678 scan_power_info->tpc.tx_gain =
1679 power_gain_table[band_index][power_index].tx_gain;
1680 scan_power_info->tpc.dsp_atten =
1681 power_gain_table[band_index][power_index].dsp_atten;
1682}
1683
1684/**
75bcfae9 1685 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1686 *
1687 * Configures power settings for all rates for the current channel,
1688 * using values from channel info struct, and send to NIC
1689 */
75bcfae9 1690int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1691{
14577f23 1692 int rate_idx, i;
d20b3c65 1693 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1694 struct iwl3945_txpowertable_cmd txpower = {
f2c7e521 1695 .channel = priv->active39_rxon.channel,
b481de9c
ZY		 1696 };
1697
8318d78a 1698 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1699 ch_info = iwl_get_channel_info(priv,
8318d78a 1700 priv->band,
f2c7e521 1701 le16_to_cpu(priv->active39_rxon.channel));
b481de9c 1702 if (!ch_info) {
15b1687c
WT		 1703 IWL_ERR(priv,
1704 "Failed to get channel info for channel %d [%d]\n",
1705 le16_to_cpu(priv->active39_rxon.channel), priv->band);
b481de9c
ZY		 1706 return -EINVAL;
1707 }
1708
1709 if (!is_channel_valid(ch_info)) {
1710 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1711 "non-Tx channel.\n");
1712 return 0;
1713 }
1714
1715 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1716 /* Fill OFDM rate */
1717 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1718 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1719
1720 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1721 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1722
1723 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1724 le16_to_cpu(txpower.channel),
1725 txpower.band,
14577f23
MA		 1726 txpower.power[i].tpc.tx_gain,
1727 txpower.power[i].tpc.dsp_atten,
1728 txpower.power[i].rate);
1729 }
1730 /* Fill CCK rates */
1731 for (rate_idx = IWL_FIRST_CCK_RATE;
1732 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1733 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1734 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1735
1736 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1737 le16_to_cpu(txpower.channel),
1738 txpower.band,
1739 txpower.power[i].tpc.tx_gain,
1740 txpower.power[i].tpc.dsp_atten,
1741 txpower.power[i].rate);
b481de9c
ZY		 1742 }
1743
518099a8
SO		 1744 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1745 sizeof(struct iwl3945_txpowertable_cmd),
1746 &txpower);
b481de9c
ZY		 1747
1748}
1749
1750/**
bb8c093b 1751 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1752 * @ch_info: Channel to update. Uses power_info.requested_power.
1753 *
1754 * Replace requested_power and base_power_index ch_info fields for
1755 * one channel.
1756 *
1757 * Called if user or spectrum management changes power preferences.
1758 * Takes into account h/w and modulation limitations (clip power).
1759 *
1760 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1761 *
1762 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1763 * properly fill out the scan powers, and actual h/w gain settings,
1764 * and send changes to NIC
1765 */
4a8a4322 1766static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1767 struct iwl_channel_info *ch_info)
b481de9c 1768{
bb8c093b 1769 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1770 int power_changed = 0;
1771 int i;
1772 const s8 *clip_pwrs;
1773 int power;
1774
1775 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1776 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1777
1778 /* Get this channel's rate-to-current-power settings table */
1779 power_info = ch_info->power_info;
1780
1781 /* update OFDM Txpower settings */
14577f23 1782 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1783 i++, ++power_info) {
1784 int delta_idx;
1785
1786 /* limit new power to be no more than h/w capability */
1787 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1788 if (power == power_info->requested_power)
1789 continue;
1790
1791 /* find difference between old and new requested powers,
1792 * update base (non-temp-compensated) power index */
1793 delta_idx = (power - power_info->requested_power) * 2;
1794 power_info->base_power_index -= delta_idx;
1795
1796 /* save new requested power value */
1797 power_info->requested_power = power;
1798
1799 power_changed = 1;
1800 }
1801
1802 /* update CCK Txpower settings, based on OFDM 12M setting ...
1803 * ... all CCK power settings for a given channel are the *same*. */
1804 if (power_changed) {
1805 power =
14577f23 1806 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1807 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1808
bb8c093b 1809 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1810 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1811 power_info->requested_power = power;
1812 power_info->base_power_index =
14577f23 1813 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1814 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1815 ++power_info;
1816 }
1817 }
1818
1819 return 0;
1820}
1821
1822/**
bb8c093b 1823 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1824 *
1825 * NOTE: Returned power limit may be less (but not more) than requested,
1826 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1827 * (no consideration for h/w clipping limitations).
1828 */
d20b3c65 1829static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1830{
1831 s8 max_power;
1832
1833#if 0
1834 /* if we're using TGd limits, use lower of TGd or EEPROM */
1835 if (ch_info->tgd_data.max_power != 0)
1836 max_power = min(ch_info->tgd_data.max_power,
1837 ch_info->eeprom.max_power_avg);
1838
1839 /* else just use EEPROM limits */
1840 else
1841#endif
1842 max_power = ch_info->eeprom.max_power_avg;
1843
1844 return min(max_power, ch_info->max_power_avg);
1845}
1846
1847/**
bb8c093b 1848 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1849 *
1850 * Compensate txpower settings of *all* channels for temperature.
1851 * This only accounts for the difference between current temperature
1852 * and the factory calibration temperatures, and bases the new settings
1853 * on the channel's base_power_index.
1854 *
1855 * If RxOn is "associated", this sends the new Txpower to NIC!
1856 */
4a8a4322 1857static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1858{
d20b3c65 1859 struct iwl_channel_info *ch_info = NULL;
e6148917 1860 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1861 int delta_index;
1862 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1863 u8 a_band;
1864 u8 rate_index;
1865 u8 scan_tbl_index;
1866 u8 i;
1867 int ref_temp;
1868 int temperature = priv->temperature;
1869
1870 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1871 for (i = 0; i < priv->channel_count; i++) {
1872 ch_info = &priv->channel_info[i];
1873 a_band = is_channel_a_band(ch_info);
1874
1875 /* Get this chnlgrp's factory calibration temperature */
e6148917 1876 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1877 temperature;
1878
a96a27f9 1879 /* get power index adjustment based on current and factory
b481de9c 1880 * temps */
bb8c093b 1881 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1882 ref_temp);
1883
1884 /* set tx power value for all rates, OFDM and CCK */
1885 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1886 rate_index++) {
1887 int power_idx =
1888 ch_info->power_info[rate_index].base_power_index;
1889
1890 /* temperature compensate */
1891 power_idx += delta_index;
1892
1893 /* stay within table range */
bb8c093b 1894 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1895 ch_info->power_info[rate_index].
1896 power_table_index = (u8) power_idx;
1897 ch_info->power_info[rate_index].tpc =
1898 power_gain_table[a_band][power_idx];
1899 }
1900
1901 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1902 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1903
1904 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1905 for (scan_tbl_index = 0;
1906 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1907 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1908 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1909 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1910 actual_index, clip_pwrs,
1911 ch_info, a_band);
1912 }
1913 }
1914
1915 /* send Txpower command for current channel to ucode */
75bcfae9 1916 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1917}
1918
4a8a4322 1919int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1920{
d20b3c65 1921 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1922 s8 max_power;
1923 u8 a_band;
1924 u8 i;
1925
62ea9c5b 1926 if (priv->tx_power_user_lmt == power) {
b481de9c
ZY		 1927 IWL_DEBUG_POWER("Requested Tx power same as current "
1928 "limit: %ddBm.\n", power);
1929 return 0;
1930 }
1931
1932 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1933 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1934
1935 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1936
1937 for (i = 0; i < priv->channel_count; i++) {
1938 ch_info = &priv->channel_info[i];
1939 a_band = is_channel_a_band(ch_info);
1940
1941 /* find minimum power of all user and regulatory constraints
1942 * (does not consider h/w clipping limitations) */
bb8c093b 1943 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1944 max_power = min(power, max_power);
1945 if (max_power != ch_info->curr_txpow) {
1946 ch_info->curr_txpow = max_power;
1947
1948 /* this considers the h/w clipping limitations */
bb8c093b 1949 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1950 }
1951 }
1952
1953 /* update txpower settings for all channels,
1954 * send to NIC if associated. */
1955 is_temp_calib_needed(priv);
bb8c093b 1956 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1957
1958 return 0;
1959}
1960
1961/* will add 3945 channel switch cmd handling later */
4a8a4322 1962int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1963{
1964 return 0;
1965}
1966
1967/**
1968 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1969 *
1970 * -- reset periodic timer
1971 * -- see if temp has changed enough to warrant re-calibration ... if so:
1972 * -- correct coeffs for temp (can reset temp timer)
1973 * -- save this temp as "last",
1974 * -- send new set of gain settings to NIC
1975 * NOTE: This should continue working, even when we're not associated,
1976 * so we can keep our internal table of scan powers current. */
4a8a4322 1977void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1978{
1979 /* This will kick in the "brute force"
bb8c093b 1980 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1981 if (!is_temp_calib_needed(priv))
1982 goto reschedule;
1983
1984 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1985 * This is based *only* on current temperature,
1986 * ignoring any previous power measurements */
bb8c093b 1987 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1988
1989 reschedule:
1990 queue_delayed_work(priv->workqueue,
1991 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1992}
1993
416e1438 1994static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1995{
4a8a4322 1996 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1997 thermal_periodic.work);
1998
1999 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2000 return;
2001
2002 mutex_lock(&priv->mutex);
2003 iwl3945_reg_txpower_periodic(priv);
2004 mutex_unlock(&priv->mutex);
2005}
2006
2007/**
bb8c093b 2008 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2009 * for the channel.
2010 *
2011 * This function is used when initializing channel-info structs.
2012 *
2013 * NOTE: These channel groups do *NOT* match the bands above!
2014 * These channel groups are based on factory-tested channels;
2015 * on A-band, EEPROM's "group frequency" entries represent the top
2016 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2017 */
4a8a4322 2018static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2019 const struct iwl_channel_info *ch_info)
b481de9c 2020{
e6148917
SO		 2021 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2022 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2023 u8 group;
2024 u16 group_index = 0; /* based on factory calib frequencies */
2025 u8 grp_channel;
2026
2027 /* Find the group index for the channel ... don't use index 1(?) */
2028 if (is_channel_a_band(ch_info)) {
2029 for (group = 1; group < 5; group++) {
2030 grp_channel = ch_grp[group].group_channel;
2031 if (ch_info->channel <= grp_channel) {
2032 group_index = group;
2033 break;
2034 }
2035 }
2036 /* group 4 has a few channels *above* its factory cal freq */
2037 if (group == 5)
2038 group_index = 4;
2039 } else
2040 group_index = 0; /* 2.4 GHz, group 0 */
2041
2042 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2043 group_index);
2044 return group_index;
2045}
2046
2047/**
bb8c093b 2048 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2049 *
2050 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2051 * into radio/DSP gain settings table for requested power.
2052 */
4a8a4322 2053static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2054 s8 requested_power,
2055 s32 setting_index, s32 *new_index)
2056{
bb8c093b 2057 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2058 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2059 s32 index0, index1;
2060 s32 power = 2 * requested_power;
2061 s32 i;
bb8c093b 2062 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2063 s32 gains0, gains1;
2064 s32 res;
2065 s32 denominator;
2066
e6148917 2067 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2068 samples = chnl_grp->samples;
2069 for (i = 0; i < 5; i++) {
2070 if (power == samples[i].power) {
2071 *new_index = samples[i].gain_index;
2072 return 0;
2073 }
2074 }
2075
2076 if (power > samples[1].power) {
2077 index0 = 0;
2078 index1 = 1;
2079 } else if (power > samples[2].power) {
2080 index0 = 1;
2081 index1 = 2;
2082 } else if (power > samples[3].power) {
2083 index0 = 2;
2084 index1 = 3;
2085 } else {
2086 index0 = 3;
2087 index1 = 4;
2088 }
2089
2090 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2091 if (denominator == 0)
2092 return -EINVAL;
2093 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2094 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2095 res = gains0 + (gains1 - gains0) *
2096 ((s32) power - (s32) samples[index0].power) / denominator +
2097 (1 << 18);
2098 *new_index = res >> 19;
2099 return 0;
2100}
2101
4a8a4322 2102static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2103{
2104 u32 i;
2105 s32 rate_index;
e6148917 2106 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2107 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2108
2109 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2110
2111 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2112 s8 *clip_pwrs; /* table of power levels for each rate */
2113 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2114 group = &eeprom->groups[i];
b481de9c
ZY		 2115
2116 /* sanity check on factory saturation power value */
2117 if (group->saturation_power < 40) {
39aadf8c 2118 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2119 "less than minimum expected 40\n",
2120 group->saturation_power);
2121 return;
2122 }
2123
2124 /*
2125 * Derive requested power levels for each rate, based on
2126 * hardware capabilities (saturation power for band).
2127 * Basic value is 3dB down from saturation, with further
2128 * power reductions for highest 3 data rates. These
2129 * backoffs provide headroom for high rate modulation
2130 * power peaks, without too much distortion (clipping).
2131 */
2132 /* we'll fill in this array with h/w max power levels */
f2c7e521 2133 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2134
2135 /* divide factory saturation power by 2 to find -3dB level */
2136 satur_pwr = (s8) (group->saturation_power >> 1);
2137
2138 /* fill in channel group's nominal powers for each rate */
2139 for (rate_index = 0;
2140 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2141 switch (rate_index) {
14577f23 2142 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2143 if (i == 0) /* B/G */
2144 *clip_pwrs = satur_pwr;
2145 else /* A */
2146 *clip_pwrs = satur_pwr - 5;
2147 break;
14577f23 2148 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2149 if (i == 0)
2150 *clip_pwrs = satur_pwr - 7;
2151 else
2152 *clip_pwrs = satur_pwr - 10;
2153 break;
14577f23 2154 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2155 if (i == 0)
2156 *clip_pwrs = satur_pwr - 9;
2157 else
2158 *clip_pwrs = satur_pwr - 12;
2159 break;
2160 default:
2161 *clip_pwrs = satur_pwr;
2162 break;
2163 }
2164 }
2165 }
2166}
2167
2168/**
2169 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2170 *
2171 * Second pass (during init) to set up priv->channel_info
2172 *
2173 * Set up Tx-power settings in our channel info database for each VALID
2174 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2175 * and current temperature.
2176 *
2177 * Since this is based on current temperature (at init time), these values may
2178 * not be valid for very long, but it gives us a starting/default point,
2179 * and allows us to active (i.e. using Tx) scan.
2180 *
2181 * This does *not* write values to NIC, just sets up our internal table.
2182 */
4a8a4322 2183int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2184{
d20b3c65 2185 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2186 struct iwl3945_channel_power_info *pwr_info;
e6148917 2187 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2188 int delta_index;
2189 u8 rate_index;
2190 u8 scan_tbl_index;
2191 const s8 *clip_pwrs; /* array of power levels for each rate */
2192 u8 gain, dsp_atten;
2193 s8 power;
2194 u8 pwr_index, base_pwr_index, a_band;
2195 u8 i;
2196 int temperature;
2197
2198 /* save temperature reference,
2199 * so we can determine next time to calibrate */
bb8c093b 2200 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2201 priv->last_temperature = temperature;
2202
bb8c093b 2203 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2204
2205 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2206 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2207 i++, ch_info++) {
2208 a_band = is_channel_a_band(ch_info);
2209 if (!is_channel_valid(ch_info))
2210 continue;
2211
2212 /* find this channel's channel group (*not* "band") index */
2213 ch_info->group_index =
bb8c093b 2214 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2215
2216 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2217 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2218
2219 /* calculate power index *adjustment* value according to
2220 * diff between current temperature and factory temperature */
bb8c093b 2221 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2222 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2223 temperature);
2224
2225 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2226 ch_info->channel, delta_index, temperature +
2227 IWL_TEMP_CONVERT);
2228
2229 /* set tx power value for all OFDM rates */
2230 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2231 rate_index++) {
25a4ccea 2232 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2233 int rc;
2234
2235 /* use channel group's clip-power table,
2236 * but don't exceed channel's max power */
2237 s8 pwr = min(ch_info->max_power_avg,
2238 clip_pwrs[rate_index]);
2239
2240 pwr_info = &ch_info->power_info[rate_index];
2241
2242 /* get base (i.e. at factory-measured temperature)
2243 * power table index for this rate's power */
bb8c093b 2244 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2245 ch_info->group_index,
2246 &power_idx);
2247 if (rc) {
15b1687c 2248 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2249 return rc;
2250 }
2251 pwr_info->base_power_index = (u8) power_idx;
2252
2253 /* temperature compensate */
2254 power_idx += delta_index;
2255
2256 /* stay within range of gain table */
bb8c093b 2257 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2258
bb8c093b 2259 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2260 pwr_info->requested_power = pwr;
2261 pwr_info->power_table_index = (u8) power_idx;
2262 pwr_info->tpc.tx_gain =
2263 power_gain_table[a_band][power_idx].tx_gain;
2264 pwr_info->tpc.dsp_atten =
2265 power_gain_table[a_band][power_idx].dsp_atten;
2266 }
2267
2268 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2269 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2270 power = pwr_info->requested_power +
2271 IWL_CCK_FROM_OFDM_POWER_DIFF;
2272 pwr_index = pwr_info->power_table_index +
2273 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2274 base_pwr_index = pwr_info->base_power_index +
2275 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2276
2277 /* stay within table range */
bb8c093b 2278 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2279 gain = power_gain_table[a_band][pwr_index].tx_gain;
2280 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2281
bb8c093b 2282 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2283 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2284 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2285 for (rate_index = 0;
2286 rate_index < IWL_CCK_RATES; rate_index++) {
2287 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2288 pwr_info->requested_power = power;
2289 pwr_info->power_table_index = pwr_index;
2290 pwr_info->base_power_index = base_pwr_index;
2291 pwr_info->tpc.tx_gain = gain;
2292 pwr_info->tpc.dsp_atten = dsp_atten;
2293 }
2294
2295 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2296 for (scan_tbl_index = 0;
2297 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2298 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2299 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2300 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2301 actual_index, clip_pwrs, ch_info, a_band);
2302 }
2303 }
2304
2305 return 0;
2306}
2307
4a8a4322 2308int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2309{
2310 int rc;
2311 unsigned long flags;
2312
2313 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2314 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2315 if (rc) {
2316 spin_unlock_irqrestore(&priv->lock, flags);
2317 return rc;
2318 }
2319
5d49f498
AK		 2320 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2321 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2322 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2323 if (rc < 0)
15b1687c 2324 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2325
5d49f498 2326 iwl_release_nic_access(priv);
b481de9c
ZY		 2327 spin_unlock_irqrestore(&priv->lock, flags);
2328
2329 return 0;
2330}
2331
188cf6c7 2332int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c
ZY		 2333{
2334 int rc;
2335 unsigned long flags;
2336 int txq_id = txq->q.id;
2337
3832ec9d 2338 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2339
2340 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2341
2342 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2343 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2344 if (rc) {
2345 spin_unlock_irqrestore(&priv->lock, flags);
2346 return rc;
2347 }
5d49f498
AK		 2348 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2349 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2350
5d49f498 2351 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2352 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2353 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2354 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2355 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2356 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
5d49f498 2357 iwl_release_nic_access(priv);
b481de9c
ZY		 2358
2359 /* fake read to flush all prev. writes */
5d49f498 2360 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2361 spin_unlock_irqrestore(&priv->lock, flags);
2362
2363 return 0;
2364}
2365
42427b4e
KA		 2366/*
2367 * HCMD utils
2368 */
2369static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2370{
2371 switch (cmd_id) {
2372 case REPLY_RXON:
2373 return (u16) sizeof(struct iwl3945_rxon_cmd);
2374 default:
2375 return len;
2376 }
2377}
2378
b481de9c
ZY		 2379/**
2380 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2381 */
4a8a4322 2382int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2383{
14577f23 2384 int rc, i, index, prev_index;
bb8c093b 2385 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2386 .reserved = {0, 0, 0},
2387 };
bb8c093b 2388 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2389
bb8c093b
CH		 2390 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2391 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2392
2393 table[index].rate_n_flags =
bb8c093b 2394 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2395 table[index].try_cnt = priv->retry_rate;
bb8c093b 2396 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2397 table[index].next_rate_index =
2398 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2399 }
2400
8318d78a
JB		 2401 switch (priv->band) {
2402 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2403 IWL_DEBUG_RATE("Select A mode rate scale\n");
2404 /* If one of the following CCK rates is used,
2405 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2406 for (i = IWL_RATE_1M_INDEX_TABLE;
2407 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2408 table[i].next_rate_index =
2409 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2410
2411 /* Don't fall back to CCK rates */
7262796a
AM		 2412 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2413 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2414
2415 /* Don't drop out of OFDM rates */
14577f23 2416 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2417 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2418 break;
2419
8318d78a
JB		 2420 case IEEE80211_BAND_2GHZ:
2421 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2422 /* If an OFDM rate is used, have it fall back to the
2423 * 1M CCK rates */
b481de9c 2424
7262796a
AM		 2425 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2426 iwl3945_is_associated(priv)) {
2427
2428 index = IWL_FIRST_CCK_RATE;
2429 for (i = IWL_RATE_6M_INDEX_TABLE;
2430 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2431 table[i].next_rate_index =
2432 iwl3945_rates[index].table_rs_index;
2433
2434 index = IWL_RATE_11M_INDEX_TABLE;
2435 /* CCK shouldn't fall back to OFDM... */
2436 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2437 }
b481de9c
ZY		 2438 break;
2439
2440 default:
8318d78a 2441 WARN_ON(1);
b481de9c
ZY		 2442 break;
2443 }
2444
2445 /* Update the rate scaling for control frame Tx */
2446 rate_cmd.table_id = 0;
518099a8 2447 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2448 &rate_cmd);
2449 if (rc)
2450 return rc;
2451
2452 /* Update the rate scaling for data frame Tx */
2453 rate_cmd.table_id = 1;
518099a8 2454 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2455 &rate_cmd);
2456}
2457
796083cb 2458/* Called when initializing driver */
4a8a4322 2459int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2460{
3832ec9d
AK		 2461 memset((void *)&priv->hw_params, 0,
2462 sizeof(struct iwl_hw_params));
b481de9c 2463
3832ec9d 2464 priv->shared_virt =
b481de9c 2465 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2466 sizeof(struct iwl3945_shared),
3832ec9d 2467 &priv->shared_phys);
b481de9c 2468
3832ec9d 2469 if (!priv->shared_virt) {
15b1687c 2470 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2471 mutex_unlock(&priv->mutex);
2472 return -ENOMEM;
2473 }
2474
a8e74e27 2475 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
1e33dc64 2476 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
3832ec9d
AK		 2477 priv->hw_params.max_pkt_size = 2342;
2478 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2479 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2480 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2481 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2482
141c43a3
WT		 2483 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2484
b481de9c
ZY		 2485 return 0;
2486}
2487
4a8a4322 2488unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2489 struct iwl3945_frame *frame, u8 rate)
b481de9c 2490{
bb8c093b 2491 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2492 unsigned int frame_size;
2493
bb8c093b 2494 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2495 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2496
3832ec9d 2497 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2498 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2499
bb8c093b 2500 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2501 tx_beacon_cmd->frame,
b481de9c
ZY		 2502 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2503
2504 BUG_ON(frame_size > MAX_MPDU_SIZE);
2505 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2506
2507 tx_beacon_cmd->tx.rate = rate;
2508 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2509 TX_CMD_FLG_TSF_MSK);
2510
14577f23
MA		 2511 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2512 tx_beacon_cmd->tx.supp_rates[0] =
2513 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2514
b481de9c 2515 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2516 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2517
3ac7f146 2518 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2519}
2520
4a8a4322 2521void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2522{
91c066f2 2523 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2524 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2525}
2526
4a8a4322 2527void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2528{
2529 INIT_DELAYED_WORK(&priv->thermal_periodic,
2530 iwl3945_bg_reg_txpower_periodic);
2531}
2532
4a8a4322 2533void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2534{
2535 cancel_delayed_work(&priv->thermal_periodic);
2536}
2537
0164b9b4
KA		 2538/* check contents of special bootstrap uCode SRAM */
2539static int iwl3945_verify_bsm(struct iwl_priv *priv)
2540 {
2541 __le32 *image = priv->ucode_boot.v_addr;
2542 u32 len = priv->ucode_boot.len;
2543 u32 reg;
2544 u32 val;
2545
2546 IWL_DEBUG_INFO("Begin verify bsm\n");
2547
2548 /* verify BSM SRAM contents */
2549 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2550 for (reg = BSM_SRAM_LOWER_BOUND;
2551 reg < BSM_SRAM_LOWER_BOUND + len;
2552 reg += sizeof(u32), image++) {
2553 val = iwl_read_prph(priv, reg);
2554 if (val != le32_to_cpu(*image)) {
2555 IWL_ERR(priv, "BSM uCode verification failed at "
2556 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2557 BSM_SRAM_LOWER_BOUND,
2558 reg - BSM_SRAM_LOWER_BOUND, len,
2559 val, le32_to_cpu(*image));
2560 return -EIO;
2561 }
2562 }
2563
2564 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2565
2566 return 0;
2567}
2568
e6148917
SO		 2569
2570/******************************************************************************
2571 *
2572 * EEPROM related functions
2573 *
2574 ******************************************************************************/
2575
2576/*
2577 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2578 * embedded controller) as EEPROM reader; each read is a series of pulses
2579 * to/from the EEPROM chip, not a single event, so even reads could conflict
2580 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2581 * simply claims ownership, which should be safe when this function is called
2582 * (i.e. before loading uCode!).
2583 */
2584static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2585{
2586 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2587 return 0;
2588}
2589
2590
2591static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2592{
2593 return;
2594}
2595
0164b9b4
KA		 2596 /**
2597 * iwl3945_load_bsm - Load bootstrap instructions
2598 *
2599 * BSM operation:
2600 *
2601 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2602 * in special SRAM that does not power down during RFKILL. When powering back
2603 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2604 * the bootstrap program into the on-board processor, and starts it.
2605 *
2606 * The bootstrap program loads (via DMA) instructions and data for a new
2607 * program from host DRAM locations indicated by the host driver in the
2608 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2609 * automatically.
2610 *
2611 * When initializing the NIC, the host driver points the BSM to the
2612 * "initialize" uCode image. This uCode sets up some internal data, then
2613 * notifies host via "initialize alive" that it is complete.
2614 *
2615 * The host then replaces the BSM_DRAM_* pointer values to point to the
2616 * normal runtime uCode instructions and a backup uCode data cache buffer
2617 * (filled initially with starting data values for the on-board processor),
2618 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2619 * which begins normal operation.
2620 *
2621 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2622 * the backup data cache in DRAM before SRAM is powered down.
2623 *
2624 * When powering back up, the BSM loads the bootstrap program. This reloads
2625 * the runtime uCode instructions and the backup data cache into SRAM,
2626 * and re-launches the runtime uCode from where it left off.
2627 */
2628static int iwl3945_load_bsm(struct iwl_priv *priv)
2629{
2630 __le32 *image = priv->ucode_boot.v_addr;
2631 u32 len = priv->ucode_boot.len;
2632 dma_addr_t pinst;
2633 dma_addr_t pdata;
2634 u32 inst_len;
2635 u32 data_len;
2636 int rc;
2637 int i;
2638 u32 done;
2639 u32 reg_offset;
2640
2641 IWL_DEBUG_INFO("Begin load bsm\n");
2642
2643 /* make sure bootstrap program is no larger than BSM's SRAM size */
2644 if (len > IWL39_MAX_BSM_SIZE)
2645 return -EINVAL;
2646
2647 /* Tell bootstrap uCode where to find the "Initialize" uCode
2648 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2649 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2650 * after the "initialize" uCode has run, to point to
2651 * runtime/protocol instructions and backup data cache. */
2652 pinst = priv->ucode_init.p_addr;
2653 pdata = priv->ucode_init_data.p_addr;
2654 inst_len = priv->ucode_init.len;
2655 data_len = priv->ucode_init_data.len;
2656
2657 rc = iwl_grab_nic_access(priv);
2658 if (rc)
2659 return rc;
2660
2661 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2662 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2663 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2664 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2665
2666 /* Fill BSM memory with bootstrap instructions */
2667 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2668 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2669 reg_offset += sizeof(u32), image++)
2670 _iwl_write_prph(priv, reg_offset,
2671 le32_to_cpu(*image));
2672
2673 rc = iwl3945_verify_bsm(priv);
2674 if (rc) {
2675 iwl_release_nic_access(priv);
2676 return rc;
2677 }
2678
2679 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2680 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2681 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2682 IWL39_RTC_INST_LOWER_BOUND);
2683 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2684
2685 /* Load bootstrap code into instruction SRAM now,
2686 * to prepare to load "initialize" uCode */
2687 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2688 BSM_WR_CTRL_REG_BIT_START);
2689
2690 /* Wait for load of bootstrap uCode to finish */
2691 for (i = 0; i < 100; i++) {
2692 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2693 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2694 break;
2695 udelay(10);
2696 }
2697 if (i < 100)
2698 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2699 else {
2700 IWL_ERR(priv, "BSM write did not complete!\n");
2701 return -EIO;
2702 }
2703
2704 /* Enable future boot loads whenever power management unit triggers it
2705 * (e.g. when powering back up after power-save shutdown) */
2706 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2707 BSM_WR_CTRL_REG_BIT_START_EN);
2708
2709 iwl_release_nic_access(priv);
2710
2711 return 0;
2712}
2713
2714static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2715 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2716 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2717 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2718 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2719 .apm_ops = {
2720 .init = iwl3945_apm_init,
2721 .reset = iwl3945_apm_reset,
2722 .stop = iwl3945_apm_stop,
2723 .config = iwl3945_nic_config,
854682ed 2724 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2725 },
e6148917
SO		 2726 .eeprom_ops = {
2727 .regulatory_bands = {
2728 EEPROM_REGULATORY_BAND_1_CHANNELS,
2729 EEPROM_REGULATORY_BAND_2_CHANNELS,
2730 EEPROM_REGULATORY_BAND_3_CHANNELS,
2731 EEPROM_REGULATORY_BAND_4_CHANNELS,
2732 EEPROM_REGULATORY_BAND_5_CHANNELS,
2733 IWL3945_EEPROM_IMG_SIZE,
2734 IWL3945_EEPROM_IMG_SIZE,
2735 },
2736 .verify_signature = iwlcore_eeprom_verify_signature,
2737 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2738 .release_semaphore = iwl3945_eeprom_release_semaphore,
2739 .query_addr = iwlcore_eeprom_query_addr,
2740 },
75bcfae9 2741 .send_tx_power = iwl3945_send_tx_power,
0164b9b4
KA		 2742};
2743
42427b4e
KA		 2744static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2745 .get_hcmd_size = iwl3945_get_hcmd_size,
2746};
2747
0164b9b4
KA		 2748static struct iwl_ops iwl3945_ops = {
2749 .lib = &iwl3945_lib,
42427b4e 2750 .utils = &iwl3945_hcmd_utils,
0164b9b4
KA		 2751};
2752
c0f20d91 2753static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2754 .name = "3945BG",
a0987a8d
RC		 2755 .fw_name_pre = IWL3945_FW_PRE,
2756 .ucode_api_max = IWL3945_UCODE_API_MAX,
2757 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2758 .sku = IWL_SKU_G,
e6148917
SO		 2759 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2760 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2761 .ops = &iwl3945_ops,
df878d8f 2762 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2763};
2764
c0f20d91 2765static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2766 .name = "3945ABG",
a0987a8d
RC		 2767 .fw_name_pre = IWL3945_FW_PRE,
2768 .ucode_api_max = IWL3945_UCODE_API_MAX,
2769 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2770 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2771 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2772 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2773 .ops = &iwl3945_ops,
df878d8f 2774 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2775};
2776
bb8c093b 2777struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2778 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2779 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2780 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2781 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2782 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2783 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2784 {0}
2785};
2786
bb8c093b 2787MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)