projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: support "pure 40MHz" in RXON command
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
17f841cd 44#include "iwl-sta.h"
b481de9c 45#include "iwl-3945.h"
e6148917 46#include "iwl-eeprom.h"
5d08cd1d 47#include "iwl-helpers.h"
5747d47f 48#include "iwl-core.h"
d9829a67 49#include "iwl-agn-rs.h"
b481de9c
ZY		 50
51#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
52 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 59 IWL_RATE_##np##M_INDEX, \
60 IWL_RATE_##r##M_INDEX_TABLE, \
61 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 62
63/*
64 * Parameter order:
65 * rate, prev rate, next rate, prev tgg rate, next tgg rate
66 *
67 * If there isn't a valid next or previous rate then INV is used which
68 * maps to IWL_RATE_INVALID
69 *
70 */
d9829a67 71const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 72 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
73 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
74 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
75 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 76 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
77 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
78 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
79 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
80 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
81 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
82 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
83 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 84};
85
bb8c093b 86/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 87#define IWL_EVT_DISABLE (0)
88#define IWL_EVT_DISABLE_SIZE (1532/32)
89
90/**
bb8c093b 91 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 92 *
93 * Disable an event by writing "1"s into "disable"
94 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
95 * Default values of 0 enable uCode events to be logged.
96 * Use for only special debugging. This function is just a placeholder as-is,
97 * you'll need to provide the special bits! ...
98 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 99void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 100{
b481de9c
ZY		 101 int i;
102 u32 base; /* SRAM address of event log header */
103 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
104 u32 array_size; /* # of u32 entries in array */
105 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
106 0x00000000, /* 31 - 0 Event id numbers */
107 0x00000000, /* 63 - 32 */
108 0x00000000, /* 95 - 64 */
109 0x00000000, /* 127 - 96 */
110 0x00000000, /* 159 - 128 */
111 0x00000000, /* 191 - 160 */
112 0x00000000, /* 223 - 192 */
113 0x00000000, /* 255 - 224 */
114 0x00000000, /* 287 - 256 */
115 0x00000000, /* 319 - 288 */
116 0x00000000, /* 351 - 320 */
117 0x00000000, /* 383 - 352 */
118 0x00000000, /* 415 - 384 */
119 0x00000000, /* 447 - 416 */
120 0x00000000, /* 479 - 448 */
121 0x00000000, /* 511 - 480 */
122 0x00000000, /* 543 - 512 */
123 0x00000000, /* 575 - 544 */
124 0x00000000, /* 607 - 576 */
125 0x00000000, /* 639 - 608 */
126 0x00000000, /* 671 - 640 */
127 0x00000000, /* 703 - 672 */
128 0x00000000, /* 735 - 704 */
129 0x00000000, /* 767 - 736 */
130 0x00000000, /* 799 - 768 */
131 0x00000000, /* 831 - 800 */
132 0x00000000, /* 863 - 832 */
133 0x00000000, /* 895 - 864 */
134 0x00000000, /* 927 - 896 */
135 0x00000000, /* 959 - 928 */
136 0x00000000, /* 991 - 960 */
137 0x00000000, /* 1023 - 992 */
138 0x00000000, /* 1055 - 1024 */
139 0x00000000, /* 1087 - 1056 */
140 0x00000000, /* 1119 - 1088 */
141 0x00000000, /* 1151 - 1120 */
142 0x00000000, /* 1183 - 1152 */
143 0x00000000, /* 1215 - 1184 */
144 0x00000000, /* 1247 - 1216 */
145 0x00000000, /* 1279 - 1248 */
146 0x00000000, /* 1311 - 1280 */
147 0x00000000, /* 1343 - 1312 */
148 0x00000000, /* 1375 - 1344 */
149 0x00000000, /* 1407 - 1376 */
150 0x00000000, /* 1439 - 1408 */
151 0x00000000, /* 1471 - 1440 */
152 0x00000000, /* 1503 - 1472 */
153 };
154
155 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 156 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 157 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 158 return;
159 }
160
5d49f498
AK		 161 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
162 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 163
164 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 165 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 166 disable_ptr);
b481de9c 167 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 168 iwl_write_targ_mem(priv,
af7cca2a
TW		 169 disable_ptr + (i * sizeof(u32)),
170 evt_disable[i]);
b481de9c 171
b481de9c 172 } else {
e1623446
TW		 173 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
174 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
175 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 176 disable_ptr, array_size);
177 }
178
179}
180
17744ff6
TW		 181static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
182{
183 int idx;
184
185 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
186 if (iwl3945_rates[idx].plcp == plcp)
187 return idx;
188 return -1;
189}
190
d08853a3 191#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 192#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
193
194static const char *iwl3945_get_tx_fail_reason(u32 status)
195{
196 switch (status & TX_STATUS_MSK) {
197 case TX_STATUS_SUCCESS:
198 return "SUCCESS";
199 TX_STATUS_ENTRY(SHORT_LIMIT);
200 TX_STATUS_ENTRY(LONG_LIMIT);
201 TX_STATUS_ENTRY(FIFO_UNDERRUN);
202 TX_STATUS_ENTRY(MGMNT_ABORT);
203 TX_STATUS_ENTRY(NEXT_FRAG);
204 TX_STATUS_ENTRY(LIFE_EXPIRE);
205 TX_STATUS_ENTRY(DEST_PS);
206 TX_STATUS_ENTRY(ABORTED);
207 TX_STATUS_ENTRY(BT_RETRY);
208 TX_STATUS_ENTRY(STA_INVALID);
209 TX_STATUS_ENTRY(FRAG_DROPPED);
210 TX_STATUS_ENTRY(TID_DISABLE);
211 TX_STATUS_ENTRY(FRAME_FLUSHED);
212 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
213 TX_STATUS_ENTRY(TX_LOCKED);
214 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
215 }
216
217 return "UNKNOWN";
218}
219#else
220static inline const char *iwl3945_get_tx_fail_reason(u32 status)
221{
222 return "";
223}
224#endif
225
e6a9854b
JB		 226/*
227 * get ieee prev rate from rate scale table.
228 * for A and B mode we need to overright prev
229 * value
230 */
4a8a4322 231int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 232{
233 int next_rate = iwl3945_get_prev_ieee_rate(rate);
234
235 switch (priv->band) {
236 case IEEE80211_BAND_5GHZ:
237 if (rate == IWL_RATE_12M_INDEX)
238 next_rate = IWL_RATE_9M_INDEX;
239 else if (rate == IWL_RATE_6M_INDEX)
240 next_rate = IWL_RATE_6M_INDEX;
241 break;
7262796a
AM		 242 case IEEE80211_BAND_2GHZ:
243 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 244 iwl_is_associated(priv)) {
7262796a
AM		 245 if (rate == IWL_RATE_11M_INDEX)
246 next_rate = IWL_RATE_5M_INDEX;
247 }
e6a9854b 248 break;
7262796a 249
e6a9854b
JB		 250 default:
251 break;
252 }
253
254 return next_rate;
255}
256
91c066f2
TW		 257
258/**
259 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
260 *
261 * When FW advances 'R' index, all entries between old and new 'R' index
262 * need to be reclaimed. As result, some free space forms. If there is
263 * enough free space (> low mark), wake the stack that feeds us.
264 */
4a8a4322 265static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 266 int txq_id, int index)
267{
188cf6c7 268 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 269 struct iwl_queue *q = &txq->q;
dbb6654c 270 struct iwl_tx_info *tx_info;
91c066f2
TW		 271
272 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
273
274 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
275 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
276
277 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 278 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 279 tx_info->skb[0] = NULL;
7aaa1d79 280 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 281 }
282
d20b3c65 283 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 284 (txq_id != IWL_CMD_QUEUE_NUM) &&
285 priv->mac80211_registered)
e4e72fb4 286 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 287}
288
289/**
290 * iwl3945_rx_reply_tx - Handle Tx response
291 */
4a8a4322 292static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 293 struct iwl_rx_mem_buffer *rxb)
91c066f2 294{
3d24a9f7 295 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 296 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
297 int txq_id = SEQ_TO_QUEUE(sequence);
298 int index = SEQ_TO_INDEX(sequence);
188cf6c7 299 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 300 struct ieee80211_tx_info *info;
91c066f2
TW		 301 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
302 u32 status = le32_to_cpu(tx_resp->status);
303 int rate_idx;
74221d07 304 int fail;
91c066f2 305
625a381a 306 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 307 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 308 "is out of range [0-%d] %d %d\n", txq_id,
309 index, txq->q.n_bd, txq->q.write_ptr,
310 txq->q.read_ptr);
311 return;
312 }
313
e039fa4a 314 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 315 ieee80211_tx_info_clear_status(info);
316
317 /* Fill the MRR chain with some info about on-chip retransmissions */
318 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
319 if (info->band == IEEE80211_BAND_5GHZ)
320 rate_idx -= IWL_FIRST_OFDM_RATE;
321
322 fail = tx_resp->failure_frame;
74221d07
AM		 323
324 info->status.rates[0].idx = rate_idx;
325 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 326
91c066f2 327 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 328 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
329 IEEE80211_TX_STAT_ACK : 0;
91c066f2 330
e1623446 331 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 332 txq_id, iwl3945_get_tx_fail_reason(status), status,
333 tx_resp->rate, tx_resp->failure_frame);
334
e1623446 335 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 336 iwl3945_tx_queue_reclaim(priv, txq_id, index);
337
338 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 339 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 340}
341
342
343
b481de9c
ZY		 344/*****************************************************************************
345 *
346 * Intel PRO/Wireless 3945ABG/BG Network Connection
347 *
348 * RX handler implementations
349 *
b481de9c
ZY		 350 *****************************************************************************/
351
4a8a4322 352void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 353{
3d24a9f7 354 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
e1623446 355 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 356 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 357 le32_to_cpu(pkt->len));
358
f2c7e521 359 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 360
ab53d8af
MA		 361 iwl3945_led_background(priv);
362
b481de9c
ZY		 363 priv->last_statistics_time = jiffies;
364}
365
17744ff6
TW		 366/******************************************************************************
367 *
368 * Misc. internal state and helper functions
369 *
370 ******************************************************************************/
d08853a3 371#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 372
373/**
374 * iwl3945_report_frame - dump frame to syslog during debug sessions
375 *
376 * You may hack this function to show different aspects of received frames,
377 * including selective frame dumps.
378 * group100 parameter selects whether to show 1 out of 100 good frames.
379 */
d08853a3 380static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 381 struct iwl_rx_packet *pkt,
17744ff6
TW		 382 struct ieee80211_hdr *header, int group100)
383{
384 u32 to_us;
385 u32 print_summary = 0;
386 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
387 u32 hundred = 0;
388 u32 dataframe = 0;
fd7c8a40 389 __le16 fc;
17744ff6
TW		 390 u16 seq_ctl;
391 u16 channel;
392 u16 phy_flags;
393 u16 length;
394 u16 status;
395 u16 bcn_tmr;
396 u32 tsf_low;
397 u64 tsf;
398 u8 rssi;
399 u8 agc;
400 u16 sig_avg;
401 u16 noise_diff;
402 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
403 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
404 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
405 u8 *data = IWL_RX_DATA(pkt);
406
407 /* MAC header */
fd7c8a40 408 fc = header->frame_control;
17744ff6
TW		 409 seq_ctl = le16_to_cpu(header->seq_ctrl);
410
411 /* metadata */
412 channel = le16_to_cpu(rx_hdr->channel);
413 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
414 length = le16_to_cpu(rx_hdr->len);
415
416 /* end-of-frame status and timestamp */
417 status = le32_to_cpu(rx_end->status);
418 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
419 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
420 tsf = le64_to_cpu(rx_end->timestamp);
421
422 /* signal statistics */
423 rssi = rx_stats->rssi;
424 agc = rx_stats->agc;
425 sig_avg = le16_to_cpu(rx_stats->sig_avg);
426 noise_diff = le16_to_cpu(rx_stats->noise_diff);
427
428 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
429
430 /* if data frame is to us and all is good,
431 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 432 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
433 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 434 dataframe = 1;
435 if (!group100)
436 print_summary = 1; /* print each frame */
437 else if (priv->framecnt_to_us < 100) {
438 priv->framecnt_to_us++;
439 print_summary = 0;
440 } else {
441 priv->framecnt_to_us = 0;
442 print_summary = 1;
443 hundred = 1;
444 }
445 } else {
446 /* print summary for all other frames */
447 print_summary = 1;
448 }
449
450 if (print_summary) {
451 char *title;
0ff1cca0 452 int rate;
17744ff6
TW		 453
454 if (hundred)
455 title = "100Frames";
fd7c8a40 456 else if (ieee80211_has_retry(fc))
17744ff6 457 title = "Retry";
fd7c8a40 458 else if (ieee80211_is_assoc_resp(fc))
17744ff6 459 title = "AscRsp";
fd7c8a40 460 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 461 title = "RasRsp";
fd7c8a40 462 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 463 title = "PrbRsp";
464 print_dump = 1; /* dump frame contents */
465 } else if (ieee80211_is_beacon(fc)) {
466 title = "Beacon";
467 print_dump = 1; /* dump frame contents */
468 } else if (ieee80211_is_atim(fc))
469 title = "ATIM";
470 else if (ieee80211_is_auth(fc))
471 title = "Auth";
472 else if (ieee80211_is_deauth(fc))
473 title = "DeAuth";
474 else if (ieee80211_is_disassoc(fc))
475 title = "DisAssoc";
476 else
477 title = "Frame";
478
479 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
480 if (rate == -1)
481 rate = 0;
482 else
483 rate = iwl3945_rates[rate].ieee / 2;
484
485 /* print frame summary.
486 * MAC addresses show just the last byte (for brevity),
487 * but you can hack it to show more, if you'd like to. */
488 if (dataframe)
e1623446 489 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 490 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 491 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 492 length, rssi, channel, rate);
493 else {
494 /* src/dst addresses assume managed mode */
e1623446 495 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 496 "src=0x%02x, rssi=%u, tim=%lu usec, "
497 "phy=0x%02x, chnl=%d\n",
fd7c8a40 498 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 499 header->addr3[5], rssi,
500 tsf_low - priv->scan_start_tsf,
501 phy_flags, channel);
502 }
503 }
504 if (print_dump)
40b8ec0b 505 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 506}
d08853a3
SO		 507
508static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
509 struct iwl_rx_packet *pkt,
510 struct ieee80211_hdr *header, int group100)
511{
512 if (priv->debug_level & IWL_DL_RX)
513 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
514}
515
17744ff6 516#else
4a8a4322 517static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 518 struct iwl_rx_packet *pkt,
17744ff6
TW		 519 struct ieee80211_hdr *header, int group100)
520{
521}
522#endif
523
4bd9b4f3 524/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 525static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 526 struct ieee80211_hdr *header)
527{
528 /* Filter incoming packets to determine if they are targeted toward
529 * this network, discarding packets coming from ourselves */
530 switch (priv->iw_mode) {
05c914fe 531 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 532 /* packets to our IBSS update information */
533 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 534 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 535 /* packets to our IBSS update information */
536 return !compare_ether_addr(header->addr2, priv->bssid);
537 default:
538 return 1;
539 }
540}
17744ff6 541
4a8a4322 542static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 543 struct iwl_rx_mem_buffer *rxb,
12342c47 544 struct ieee80211_rx_status *stats)
b481de9c 545{
3d24a9f7 546 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
5c8df2d5 547#ifdef CONFIG_IWLWIFI_LEDS
4bd9b4f3 548 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 549#endif
bb8c093b
CH		 550 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
551 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 552 short len = le16_to_cpu(rx_hdr->len);
553
554 /* We received data from the HW, so stop the watchdog */
3d24a9f7 555 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
e1623446 556 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 557 return;
558 }
559
560 /* We only process data packets if the interface is open */
561 if (unlikely(!priv->is_open)) {
e1623446
TW		 562 IWL_DEBUG_DROP_LIMIT(priv,
563 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 564 return;
565 }
b481de9c
ZY		 566
567 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
568 /* Set the size of the skb to the size of the frame */
569 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
570
9c74d9fb 571 if (!iwl3945_mod_params.sw_crypto)
8ccde88a
SO		 572 iwl_set_decrypted_flag(priv,
573 (struct ieee80211_hdr *)rxb->skb->data,
b481de9c
ZY		 574 le32_to_cpu(rx_end->status), stats);
575
5c8df2d5 576#ifdef CONFIG_IWLWIFI_LEDS
4bd9b4f3 577 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 578 priv->rxtxpackets += len;
579#endif
b481de9c
ZY		 580 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
581 rxb->skb = NULL;
582}
583
7878a5a4
MA		 584#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
585
4a8a4322 586static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 587 struct iwl_rx_mem_buffer *rxb)
b481de9c 588{
17744ff6
TW		 589 struct ieee80211_hdr *header;
590 struct ieee80211_rx_status rx_status;
3d24a9f7 591 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 592 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
593 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
594 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 595 int snr;
b481de9c
ZY		 596 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
597 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 598 u8 network_packet;
17744ff6 599
17744ff6
TW		 600 rx_status.flag = 0;
601 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 602 rx_status.freq =
c0186078 603 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 604 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
605 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
606
607 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 608 if (rx_status.band == IEEE80211_BAND_5GHZ)
609 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 610
6f0a2c4d
BR		 611 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
612 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
613
614 /* set the preamble flag if appropriate */
615 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
616 rx_status.flag |= RX_FLAG_SHORTPRE;
617
b481de9c 618 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 619 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
620 rx_stats->phy_count);
b481de9c
ZY		 621 return;
622 }
623
624 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
625 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 626 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 627 return;
628 }
629
56decd3c 630
b481de9c
ZY		 631
632 /* Convert 3945's rssi indicator to dBm */
250bdd21 633 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 634
635 /* Set default noise value to -127 */
636 if (priv->last_rx_noise == 0)
637 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
638
639 /* 3945 provides noise info for OFDM frames only.
640 * sig_avg and noise_diff are measured by the 3945's digital signal
641 * processor (DSP), and indicate linear levels of signal level and
642 * distortion/noise within the packet preamble after
643 * automatic gain control (AGC). sig_avg should stay fairly
644 * constant if the radio's AGC is working well.
645 * Since these values are linear (not dB or dBm), linear
646 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
647 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
648 * to obtain noise level in dBm.
17744ff6 649 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 650 if (rx_stats_noise_diff) {
651 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 652 rx_status.noise = rx_status.signal -
17744ff6 653 iwl3945_calc_db_from_ratio(snr);
566bfe5a 654 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 655 rx_status.noise);
b481de9c
ZY		 656
657 /* If noise info not available, calculate signal quality indicator (%)
658 * using just the dBm signal level. */
659 } else {
17744ff6 660 rx_status.noise = priv->last_rx_noise;
566bfe5a 661 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 662 }
663
664
e1623446 665 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 666 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 667 rx_stats_sig_avg, rx_stats_noise_diff);
668
b481de9c
ZY		 669 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
670
bb8c093b 671 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 672
e1623446 673 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
17744ff6
TW		 674 network_packet ? '*' : ' ',
675 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 676 rx_status.signal, rx_status.signal,
677 rx_status.noise, rx_status.rate_idx);
b481de9c 678
d08853a3
SO		 679 /* Set "1" to report good data frames in groups of 100 */
680 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 681
682 if (network_packet) {
683 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
684 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 685 priv->last_rx_rssi = rx_status.signal;
17744ff6 686 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 687 }
688
12e5e22d 689 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 690}
691
7aaa1d79
SO		 692int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
693 struct iwl_tx_queue *txq,
694 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 695{
696 int count;
7aaa1d79 697 struct iwl_queue *q;
59606ffa 698 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 699
700 q = &txq->q;
59606ffa
SO		 701 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
702 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 703
704 if (reset)
705 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 706
707 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 708
709 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 710 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 711 NUM_TFD_CHUNKS);
712 return -EINVAL;
713 }
714
dbb6654c
WT		 715 tfd->tbs[count].addr = cpu_to_le32(addr);
716 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 717
718 count++;
719
720 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
721 TFD_CTL_PAD_SET(pad));
722
723 return 0;
724}
725
726/**
bb8c093b 727 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 728 *
729 * Does NOT advance any indexes
730 */
7aaa1d79 731void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 732{
59606ffa 733 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 734 int index = txq->q.read_ptr;
735 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 736 struct pci_dev *dev = priv->pci_dev;
737 int i;
738 int counter;
739
b481de9c 740 /* sanity check */
dbb6654c 741 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 742 if (counter > NUM_TFD_CHUNKS) {
15b1687c 743 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 744 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 745 return;
b481de9c
ZY		 746 }
747
fd9377ee
RC		 748 /* Unmap tx_cmd */
749 if (counter)
750 pci_unmap_single(dev,
751 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
752 pci_unmap_len(&txq->cmd[index]->meta, len),
753 PCI_DMA_TODEVICE);
754
b481de9c
ZY		 755 /* unmap chunks if any */
756
757 for (i = 1; i < counter; i++) {
dbb6654c
WT		 758 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
759 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 760 if (txq->txb[txq->q.read_ptr].skb[0]) {
761 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
762 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 763 /* Can be called from interrupt context */
764 dev_kfree_skb_any(skb);
fc4b6853 765 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 766 }
767 }
768 }
7aaa1d79 769 return ;
b481de9c
ZY		 770}
771
4a8a4322 772u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 773{
c93007ef 774 int i, start = IWL_AP_ID;
b481de9c
ZY		 775 int ret = IWL_INVALID_STATION;
776 unsigned long flags;
777
c93007ef
SO		 778 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
779 (priv->iw_mode == NL80211_IFTYPE_AP))
780 start = IWL_STA_ID;
781
782 if (is_broadcast_ether_addr(addr))
3832ec9d 783 return priv->hw_params.bcast_sta_id;
c93007ef 784
b481de9c 785 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 786 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 787 if ((priv->stations_39[i].used) &&
b481de9c 788 (!compare_ether_addr
f2c7e521 789 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 790 ret = i;
791 goto out;
792 }
793
e1623446 794 IWL_DEBUG_INFO(priv, "can not find STA %pM (total %d)\n",
e174961c 795 addr, priv->num_stations);
b481de9c
ZY		 796 out:
797 spin_unlock_irqrestore(&priv->sta_lock, flags);
798 return ret;
799}
800
801/**
bb8c093b 802 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 803 *
804*/
c2d79b48 805void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 806 struct ieee80211_tx_info *info,
b481de9c
ZY		 807 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
808{
e039fa4a 809 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 810 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 811 u16 rate_mask;
812 int rate;
813 u8 rts_retry_limit;
814 u8 data_retry_limit;
815 __le32 tx_flags;
fd7c8a40 816 __le16 fc = hdr->frame_control;
c2d79b48 817 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 818
bb8c093b 819 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 820 tx_flags = tx->tx_flags;
b481de9c
ZY		 821
822 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 823 * in this running context */
b481de9c
ZY		 824 rate_mask = IWL_RATES_MASK;
825
b481de9c
ZY		 826 if (tx_id >= IWL_CMD_QUEUE_NUM)
827 rts_retry_limit = 3;
828 else
829 rts_retry_limit = 7;
830
fd7c8a40 831 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 832 data_retry_limit = 3;
833 if (data_retry_limit < rts_retry_limit)
834 rts_retry_limit = data_retry_limit;
835 } else
836 data_retry_limit = IWL_DEFAULT_TX_RETRY;
837
838 if (priv->data_retry_limit != -1)
839 data_retry_limit = priv->data_retry_limit;
840
fd7c8a40
HH		 841 if (ieee80211_is_mgmt(fc)) {
842 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
843 case cpu_to_le16(IEEE80211_STYPE_AUTH):
844 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
845 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
846 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 847 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
848 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
849 tx_flags |= TX_CMD_FLG_CTS_MSK;
850 }
851 break;
852 default:
853 break;
854 }
855 }
856
c2d79b48
WT		 857 tx->rts_retry_limit = rts_retry_limit;
858 tx->data_retry_limit = data_retry_limit;
859 tx->rate = rate;
860 tx->tx_flags = tx_flags;
b481de9c
ZY		 861
862 /* OFDM */
c2d79b48 863 tx->supp_rates[0] =
14577f23 864 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 865
866 /* CCK */
c2d79b48 867 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c 868
e1623446 869 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 870 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 871 tx->rate, le32_to_cpu(tx->tx_flags),
872 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 873}
874
4a8a4322 875u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 876{
877 unsigned long flags_spin;
bb8c093b 878 struct iwl3945_station_entry *station;
b481de9c
ZY		 879
880 if (sta_id == IWL_INVALID_STATION)
881 return IWL_INVALID_STATION;
882
883 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 884 station = &priv->stations_39[sta_id];
b481de9c
ZY		 885
886 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
887 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 888 station->sta.mode = STA_CONTROL_MODIFY_MSK;
889
890 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
891
17f841cd
SO		 892 iwl_send_add_sta(priv,
893 (struct iwl_addsta_cmd *)&station->sta, flags);
e1623446 894 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 895 sta_id, tx_rate);
896 return sta_id;
897}
898
854682ed 899static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 900{
854682ed 901 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 902 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 903 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 904 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
905 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 906
5d49f498 907 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 908 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
909 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 910 }
b481de9c 911 } else {
5d49f498 912 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 913 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
914 ~APMG_PS_CTRL_MSK_PWR_SRC);
915
5d49f498 916 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 917 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
918 }
b481de9c 919
a8b50a0a 920 return 0;
b481de9c
ZY		 921}
922
4a8a4322 923static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 924{
5d49f498 925 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 926 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 927 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
928 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 929 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
930 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
931 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
932 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
933 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
934 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
935 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
936 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 937
938 /* fake read to flush all prev I/O */
5d49f498 939 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 940
b481de9c
ZY		 941 return 0;
942}
943
4a8a4322 944static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 945{
b481de9c
ZY		 946
947 /* bypass mode */
5d49f498 948 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 949
950 /* RA 0 is active */
5d49f498 951 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 952
953 /* all 6 fifo are active */
5d49f498 954 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 955
5d49f498
AK		 956 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
957 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
958 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
959 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 960
5d49f498 961 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 962 priv->shared_phys);
b481de9c 963
5d49f498 964 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 965 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
966 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
967 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
968 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
969 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
970 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
971 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 972
b481de9c
ZY		 973
974 return 0;
975}
976
977/**
978 * iwl3945_txq_ctx_reset - Reset TX queue context
979 *
980 * Destroys all DMA structures and initialize them again
981 */
4a8a4322 982static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 983{
984 int rc;
985 int txq_id, slots_num;
986
bb8c093b 987 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 988
989 /* Tx CMD queue */
990 rc = iwl3945_tx_reset(priv);
991 if (rc)
992 goto error;
993
994 /* Tx queue(s) */
21c02a1a 995 for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 996 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
997 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 998 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
999 txq_id);
b481de9c 1000 if (rc) {
15b1687c 1001 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1002 goto error;
1003 }
1004 }
1005
1006 return rc;
1007
1008 error:
bb8c093b 1009 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1010 return rc;
1011}
1012
01ec616d 1013static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1014{
a8b50a0a 1015 int ret;
b481de9c 1016
d25aabb0 1017 iwl_power_initialize(priv);
b481de9c 1018
5d49f498 1019 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1020 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1021
1022 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1023 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1024 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1025
01ec616d
KA		 1026 /* set "initialization complete" bit to move adapter
1027 * D0U* --> D0A* state */
5d49f498 1028 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d 1029
ddcb5c78 1030 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
01ec616d
KA		 1031 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1032 if (ret < 0) {
e1623446 1033 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
01ec616d 1034 goto out;
b481de9c
ZY		 1035 }
1036
01ec616d
KA		 1037 /* enable DMA */
1038 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1039 APMG_CLK_VAL_BSM_CLK_RQT);
1040
b481de9c 1041 udelay(20);
01ec616d
KA		 1042
1043 /* disable L1-Active */
5d49f498 1044 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1045 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1046
01ec616d
KA		 1047out:
1048 return ret;
1049}
b481de9c 1050
01ec616d
KA		 1051static void iwl3945_nic_config(struct iwl_priv *priv)
1052{
e6148917 1053 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1054 unsigned long flags;
1055 u8 rev_id = 0;
b481de9c 1056
b481de9c
ZY		 1057 spin_lock_irqsave(&priv->lock, flags);
1058
43121432
AK		 1059 /* Determine HW type */
1060 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1061
1062 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1063
b481de9c 1064 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
e1623446 1065 IWL_DEBUG_INFO(priv, "RTP type \n");
b481de9c 1066 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1067 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1068 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1069 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1070 } else {
e1623446 1071 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1072 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1073 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1074 }
1075
e6148917 1076 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1077 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1078 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1079 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1080 } else
e1623446 1081 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1082
e6148917 1083 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1084 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1085 eeprom->board_revision);
5d49f498 1086 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1087 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1088 } else {
e1623446 1089 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1090 eeprom->board_revision);
5d49f498 1091 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1092 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1093 }
1094
e6148917 1095 if (eeprom->almgor_m_version <= 1) {
5d49f498 1096 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1097 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1098 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1099 eeprom->almgor_m_version);
b481de9c 1100 } else {
e1623446 1101 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1102 eeprom->almgor_m_version);
5d49f498 1103 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1104 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1105 }
1106 spin_unlock_irqrestore(&priv->lock, flags);
1107
e6148917 1108 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1109 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1110
e6148917 1111 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1112 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1113}
1114
1115int iwl3945_hw_nic_init(struct iwl_priv *priv)
1116{
01ec616d
KA		 1117 int rc;
1118 unsigned long flags;
1119 struct iwl_rx_queue *rxq = &priv->rxq;
1120
1121 spin_lock_irqsave(&priv->lock, flags);
1122 priv->cfg->ops->lib->apm_ops.init(priv);
1123 spin_unlock_irqrestore(&priv->lock, flags);
1124
854682ed 1125 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1126 if (rc)
854682ed
KA		 1127 return rc;
1128
01ec616d 1129 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1130
1131 /* Allocate the RX queue, or reset if it is already allocated */
1132 if (!rxq->bd) {
51af3d3f 1133 rc = iwl_rx_queue_alloc(priv);
b481de9c 1134 if (rc) {
15b1687c 1135 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1136 return -ENOMEM;
1137 }
1138 } else
df833b1d 1139 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1140
bb8c093b 1141 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1142
1143 iwl3945_rx_init(priv, rxq);
1144
b481de9c
ZY		 1145
1146 /* Look at using this instead:
1147 rxq->need_update = 1;
141c43a3 1148 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1149 */
1150
5d49f498 1151 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1152
1153 rc = iwl3945_txq_ctx_reset(priv);
1154 if (rc)
1155 return rc;
1156
1157 set_bit(STATUS_INIT, &priv->status);
1158
1159 return 0;
1160}
1161
1162/**
bb8c093b 1163 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1164 *
1165 * Destroy all TX DMA queues and structures
1166 */
4a8a4322 1167void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1168{
1169 int txq_id;
1170
1171 /* Tx queues */
21c02a1a 1172 for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++)
3e5d238f
AK		 1173 if (txq_id == IWL_CMD_QUEUE_NUM)
1174 iwl_cmd_queue_free(priv);
1175 else
1176 iwl_tx_queue_free(priv, txq_id);
1177
b481de9c
ZY		 1178}
1179
4a8a4322 1180void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1181{
bddadf86 1182 int txq_id;
b481de9c
ZY		 1183
1184 /* stop SCD */
5d49f498 1185 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1186
1187 /* reset TFD queues */
21c02a1a 1188 for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1189 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1190 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1191 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1192 1000);
1193 }
1194
bb8c093b 1195 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1196}
1197
01ec616d 1198static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1199{
01ec616d 1200 int ret = 0;
b481de9c
ZY		 1201 unsigned long flags;
1202
1203 spin_lock_irqsave(&priv->lock, flags);
1204
1205 /* set stop master bit */
5d49f498 1206 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1207
01ec616d
KA		 1208 iwl_poll_direct_bit(priv, CSR_RESET,
1209 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1210
01ec616d
KA		 1211 if (ret < 0)
1212 goto out;
b481de9c 1213
01ec616d 1214out:
b481de9c 1215 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 1216 IWL_DEBUG_INFO(priv, "stop master\n");
b481de9c 1217
01ec616d
KA		 1218 return ret;
1219}
1220
1221static void iwl3945_apm_stop(struct iwl_priv *priv)
1222{
1223 unsigned long flags;
1224
1225 iwl3945_apm_stop_master(priv);
1226
1227 spin_lock_irqsave(&priv->lock, flags);
1228
1229 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1230
1231 udelay(10);
1232 /* clear "init complete" move adapter D0A* --> D0U state */
1233 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1234 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1235}
1236
e52119c5 1237static int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c 1238{
01ec616d 1239 iwl3945_apm_stop_master(priv);
b481de9c 1240
b481de9c 1241
5d49f498 1242 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
e9414b6b
AM		 1243 udelay(10);
1244
1245 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 1246
5d49f498 1247 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1248 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1249
a8b50a0a
MA		 1250 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1251 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 1252
a8b50a0a
MA		 1253 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1254 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1255 0xFFFFFFFF);
1256
a8b50a0a
MA		 1257 /* enable DMA */
1258 iwl_write_prph(priv, APMG_CLK_EN_REG,
1259 APMG_CLK_VAL_DMA_CLK_RQT |
1260 APMG_CLK_VAL_BSM_CLK_RQT);
1261 udelay(10);
b481de9c 1262
a8b50a0a 1263 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1264 APMG_PS_CTRL_VAL_RESET_REQ);
a8b50a0a
MA		 1265 udelay(5);
1266 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1267 APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c
ZY		 1268
1269 /* Clear the 'host command active' bit... */
1270 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1271
1272 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1273
a8b50a0a 1274 return 0;
b481de9c
ZY		 1275}
1276
1277/**
bb8c093b 1278 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1279 * return index delta into power gain settings table
1280*/
bb8c093b 1281static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1282{
1283 return (new_reading - old_reading) * (-11) / 100;
1284}
1285
1286/**
bb8c093b 1287 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1288 */
bb8c093b 1289static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1290{
3ac7f146 1291 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1292}
1293
4a8a4322 1294int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1295{
5d49f498 1296 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1297}
1298
1299/**
bb8c093b 1300 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1301 * get the current temperature by reading from NIC
1302*/
4a8a4322 1303static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1304{
e6148917 1305 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1306 int temperature;
1307
bb8c093b 1308 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1309
1310 /* driver's okay range is -260 to +25.
1311 * human readable okay range is 0 to +285 */
e1623446 1312 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1313
1314 /* handle insane temp reading */
bb8c093b 1315 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1316 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1317
1318 /* if really really hot(?),
1319 * substitute the 3rd band/group's temp measured at factory */
1320 if (priv->last_temperature > 100)
e6148917 1321 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1322 else /* else use most recent "sane" value from driver */
1323 temperature = priv->last_temperature;
1324 }
1325
1326 return temperature; /* raw, not "human readable" */
1327}
1328
1329/* Adjust Txpower only if temperature variance is greater than threshold.
1330 *
1331 * Both are lower than older versions' 9 degrees */
1332#define IWL_TEMPERATURE_LIMIT_TIMER 6
1333
1334/**
1335 * is_temp_calib_needed - determines if new calibration is needed
1336 *
1337 * records new temperature in tx_mgr->temperature.
1338 * replaces tx_mgr->last_temperature *only* if calib needed
1339 * (assumes caller will actually do the calibration!). */
4a8a4322 1340static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1341{
1342 int temp_diff;
1343
bb8c093b 1344 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1345 temp_diff = priv->temperature - priv->last_temperature;
1346
1347 /* get absolute value */
1348 if (temp_diff < 0) {
e1623446 1349 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1350 temp_diff = -temp_diff;
1351 } else if (temp_diff == 0)
e1623446 1352 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1353 else
e1623446 1354 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1355
1356 /* if we don't need calibration, *don't* update last_temperature */
1357 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1358 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1359 return 0;
1360 }
1361
e1623446 1362 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1363
1364 /* assume that caller will actually do calib ...
1365 * update the "last temperature" value */
1366 priv->last_temperature = priv->temperature;
1367 return 1;
1368}
1369
1370#define IWL_MAX_GAIN_ENTRIES 78
1371#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1372#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1373
1374/* radio and DSP power table, each step is 1/2 dB.
1375 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1376static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1377 {
1378 {251, 127}, /* 2.4 GHz, highest power */
1379 {251, 127},
1380 {251, 127},
1381 {251, 127},
1382 {251, 125},
1383 {251, 110},
1384 {251, 105},
1385 {251, 98},
1386 {187, 125},
1387 {187, 115},
1388 {187, 108},
1389 {187, 99},
1390 {243, 119},
1391 {243, 111},
1392 {243, 105},
1393 {243, 97},
1394 {243, 92},
1395 {211, 106},
1396 {211, 100},
1397 {179, 120},
1398 {179, 113},
1399 {179, 107},
1400 {147, 125},
1401 {147, 119},
1402 {147, 112},
1403 {147, 106},
1404 {147, 101},
1405 {147, 97},
1406 {147, 91},
1407 {115, 107},
1408 {235, 121},
1409 {235, 115},
1410 {235, 109},
1411 {203, 127},
1412 {203, 121},
1413 {203, 115},
1414 {203, 108},
1415 {203, 102},
1416 {203, 96},
1417 {203, 92},
1418 {171, 110},
1419 {171, 104},
1420 {171, 98},
1421 {139, 116},
1422 {227, 125},
1423 {227, 119},
1424 {227, 113},
1425 {227, 107},
1426 {227, 101},
1427 {227, 96},
1428 {195, 113},
1429 {195, 106},
1430 {195, 102},
1431 {195, 95},
1432 {163, 113},
1433 {163, 106},
1434 {163, 102},
1435 {163, 95},
1436 {131, 113},
1437 {131, 106},
1438 {131, 102},
1439 {131, 95},
1440 {99, 113},
1441 {99, 106},
1442 {99, 102},
1443 {99, 95},
1444 {67, 113},
1445 {67, 106},
1446 {67, 102},
1447 {67, 95},
1448 {35, 113},
1449 {35, 106},
1450 {35, 102},
1451 {35, 95},
1452 {3, 113},
1453 {3, 106},
1454 {3, 102},
1455 {3, 95} }, /* 2.4 GHz, lowest power */
1456 {
1457 {251, 127}, /* 5.x GHz, highest power */
1458 {251, 120},
1459 {251, 114},
1460 {219, 119},
1461 {219, 101},
1462 {187, 113},
1463 {187, 102},
1464 {155, 114},
1465 {155, 103},
1466 {123, 117},
1467 {123, 107},
1468 {123, 99},
1469 {123, 92},
1470 {91, 108},
1471 {59, 125},
1472 {59, 118},
1473 {59, 109},
1474 {59, 102},
1475 {59, 96},
1476 {59, 90},
1477 {27, 104},
1478 {27, 98},
1479 {27, 92},
1480 {115, 118},
1481 {115, 111},
1482 {115, 104},
1483 {83, 126},
1484 {83, 121},
1485 {83, 113},
1486 {83, 105},
1487 {83, 99},
1488 {51, 118},
1489 {51, 111},
1490 {51, 104},
1491 {51, 98},
1492 {19, 116},
1493 {19, 109},
1494 {19, 102},
1495 {19, 98},
1496 {19, 93},
1497 {171, 113},
1498 {171, 107},
1499 {171, 99},
1500 {139, 120},
1501 {139, 113},
1502 {139, 107},
1503 {139, 99},
1504 {107, 120},
1505 {107, 113},
1506 {107, 107},
1507 {107, 99},
1508 {75, 120},
1509 {75, 113},
1510 {75, 107},
1511 {75, 99},
1512 {43, 120},
1513 {43, 113},
1514 {43, 107},
1515 {43, 99},
1516 {11, 120},
1517 {11, 113},
1518 {11, 107},
1519 {11, 99},
1520 {131, 107},
1521 {131, 99},
1522 {99, 120},
1523 {99, 113},
1524 {99, 107},
1525 {99, 99},
1526 {67, 120},
1527 {67, 113},
1528 {67, 107},
1529 {67, 99},
1530 {35, 120},
1531 {35, 113},
1532 {35, 107},
1533 {35, 99},
1534 {3, 120} } /* 5.x GHz, lowest power */
1535};
1536
bb8c093b 1537static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1538{
1539 if (index < 0)
1540 return 0;
1541 if (index >= IWL_MAX_GAIN_ENTRIES)
1542 return IWL_MAX_GAIN_ENTRIES - 1;
1543 return (u8) index;
1544}
1545
1546/* Kick off thermal recalibration check every 60 seconds */
1547#define REG_RECALIB_PERIOD (60)
1548
1549/**
bb8c093b 1550 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1551 *
1552 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1553 * or 6 Mbit (OFDM) rates.
1554 */
4a8a4322 1555static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1556 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1557 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1558 int band_index)
1559{
bb8c093b 1560 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1561 s8 power;
1562 u8 power_index;
1563
1564 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1565
1566 /* use this channel group's 6Mbit clipping/saturation pwr,
1567 * but cap at regulatory scan power restriction (set during init
1568 * based on eeprom channel data) for this channel. */
14577f23 1569 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1570
1571 /* further limit to user's max power preference.
1572 * FIXME: Other spectrum management power limitations do not
1573 * seem to apply?? */
62ea9c5b 1574 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1575 scan_power_info->requested_power = power;
1576
1577 /* find difference between new scan *power* and current "normal"
1578 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1579 * current "normal" temperature-compensated Tx power *index* for
1580 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1581 * *index*. */
1582 power_index = ch_info->power_info[rate_index].power_table_index
1583 - (power - ch_info->power_info
14577f23 1584 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1585
1586 /* store reference index that we use when adjusting *all* scan
1587 * powers. So we can accommodate user (all channel) or spectrum
1588 * management (single channel) power changes "between" temperature
1589 * feedback compensation procedures.
1590 * don't force fit this reference index into gain table; it may be a
1591 * negative number. This will help avoid errors when we're at
1592 * the lower bounds (highest gains, for warmest temperatures)
1593 * of the table. */
1594
1595 /* don't exceed table bounds for "real" setting */
bb8c093b 1596 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1597
1598 scan_power_info->power_table_index = power_index;
1599 scan_power_info->tpc.tx_gain =
1600 power_gain_table[band_index][power_index].tx_gain;
1601 scan_power_info->tpc.dsp_atten =
1602 power_gain_table[band_index][power_index].dsp_atten;
1603}
1604
1605/**
75bcfae9 1606 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1607 *
1608 * Configures power settings for all rates for the current channel,
1609 * using values from channel info struct, and send to NIC
1610 */
dfb39e82 1611static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1612{
14577f23 1613 int rate_idx, i;
d20b3c65 1614 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1615 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1616 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1617 };
1618
8318d78a 1619 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1620 ch_info = iwl_get_channel_info(priv,
8318d78a 1621 priv->band,
8ccde88a 1622 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1623 if (!ch_info) {
15b1687c
WT		 1624 IWL_ERR(priv,
1625 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1626 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1627 return -EINVAL;
1628 }
1629
1630 if (!is_channel_valid(ch_info)) {
e1623446 1631 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1632 "non-Tx channel.\n");
1633 return 0;
1634 }
1635
1636 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1637 /* Fill OFDM rate */
1638 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1639 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1640
1641 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1642 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1643
e1623446 1644 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1645 le16_to_cpu(txpower.channel),
1646 txpower.band,
14577f23
MA		 1647 txpower.power[i].tpc.tx_gain,
1648 txpower.power[i].tpc.dsp_atten,
1649 txpower.power[i].rate);
1650 }
1651 /* Fill CCK rates */
1652 for (rate_idx = IWL_FIRST_CCK_RATE;
1653 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1654 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1655 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1656
e1623446 1657 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1658 le16_to_cpu(txpower.channel),
1659 txpower.band,
1660 txpower.power[i].tpc.tx_gain,
1661 txpower.power[i].tpc.dsp_atten,
1662 txpower.power[i].rate);
b481de9c
ZY		 1663 }
1664
518099a8
SO		 1665 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1666 sizeof(struct iwl3945_txpowertable_cmd),
1667 &txpower);
b481de9c
ZY		 1668
1669}
1670
1671/**
bb8c093b 1672 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1673 * @ch_info: Channel to update. Uses power_info.requested_power.
1674 *
1675 * Replace requested_power and base_power_index ch_info fields for
1676 * one channel.
1677 *
1678 * Called if user or spectrum management changes power preferences.
1679 * Takes into account h/w and modulation limitations (clip power).
1680 *
1681 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1682 *
1683 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1684 * properly fill out the scan powers, and actual h/w gain settings,
1685 * and send changes to NIC
1686 */
4a8a4322 1687static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1688 struct iwl_channel_info *ch_info)
b481de9c 1689{
bb8c093b 1690 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1691 int power_changed = 0;
1692 int i;
1693 const s8 *clip_pwrs;
1694 int power;
1695
1696 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1697 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1698
1699 /* Get this channel's rate-to-current-power settings table */
1700 power_info = ch_info->power_info;
1701
1702 /* update OFDM Txpower settings */
14577f23 1703 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1704 i++, ++power_info) {
1705 int delta_idx;
1706
1707 /* limit new power to be no more than h/w capability */
1708 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1709 if (power == power_info->requested_power)
1710 continue;
1711
1712 /* find difference between old and new requested powers,
1713 * update base (non-temp-compensated) power index */
1714 delta_idx = (power - power_info->requested_power) * 2;
1715 power_info->base_power_index -= delta_idx;
1716
1717 /* save new requested power value */
1718 power_info->requested_power = power;
1719
1720 power_changed = 1;
1721 }
1722
1723 /* update CCK Txpower settings, based on OFDM 12M setting ...
1724 * ... all CCK power settings for a given channel are the *same*. */
1725 if (power_changed) {
1726 power =
14577f23 1727 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1728 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1729
bb8c093b 1730 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1731 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1732 power_info->requested_power = power;
1733 power_info->base_power_index =
14577f23 1734 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1735 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1736 ++power_info;
1737 }
1738 }
1739
1740 return 0;
1741}
1742
1743/**
bb8c093b 1744 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1745 *
1746 * NOTE: Returned power limit may be less (but not more) than requested,
1747 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1748 * (no consideration for h/w clipping limitations).
1749 */
d20b3c65 1750static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1751{
1752 s8 max_power;
1753
1754#if 0
1755 /* if we're using TGd limits, use lower of TGd or EEPROM */
1756 if (ch_info->tgd_data.max_power != 0)
1757 max_power = min(ch_info->tgd_data.max_power,
1758 ch_info->eeprom.max_power_avg);
1759
1760 /* else just use EEPROM limits */
1761 else
1762#endif
1763 max_power = ch_info->eeprom.max_power_avg;
1764
1765 return min(max_power, ch_info->max_power_avg);
1766}
1767
1768/**
bb8c093b 1769 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1770 *
1771 * Compensate txpower settings of *all* channels for temperature.
1772 * This only accounts for the difference between current temperature
1773 * and the factory calibration temperatures, and bases the new settings
1774 * on the channel's base_power_index.
1775 *
1776 * If RxOn is "associated", this sends the new Txpower to NIC!
1777 */
4a8a4322 1778static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1779{
d20b3c65 1780 struct iwl_channel_info *ch_info = NULL;
e6148917 1781 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1782 int delta_index;
1783 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1784 u8 a_band;
1785 u8 rate_index;
1786 u8 scan_tbl_index;
1787 u8 i;
1788 int ref_temp;
1789 int temperature = priv->temperature;
1790
1791 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1792 for (i = 0; i < priv->channel_count; i++) {
1793 ch_info = &priv->channel_info[i];
1794 a_band = is_channel_a_band(ch_info);
1795
1796 /* Get this chnlgrp's factory calibration temperature */
e6148917 1797 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1798 temperature;
1799
a96a27f9 1800 /* get power index adjustment based on current and factory
b481de9c 1801 * temps */
bb8c093b 1802 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1803 ref_temp);
1804
1805 /* set tx power value for all rates, OFDM and CCK */
1806 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1807 rate_index++) {
1808 int power_idx =
1809 ch_info->power_info[rate_index].base_power_index;
1810
1811 /* temperature compensate */
1812 power_idx += delta_index;
1813
1814 /* stay within table range */
bb8c093b 1815 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1816 ch_info->power_info[rate_index].
1817 power_table_index = (u8) power_idx;
1818 ch_info->power_info[rate_index].tpc =
1819 power_gain_table[a_band][power_idx];
1820 }
1821
1822 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1823 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1824
1825 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1826 for (scan_tbl_index = 0;
1827 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1828 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1829 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1830 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1831 actual_index, clip_pwrs,
1832 ch_info, a_band);
1833 }
1834 }
1835
1836 /* send Txpower command for current channel to ucode */
75bcfae9 1837 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1838}
1839
4a8a4322 1840int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1841{
d20b3c65 1842 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1843 s8 max_power;
1844 u8 a_band;
1845 u8 i;
1846
62ea9c5b 1847 if (priv->tx_power_user_lmt == power) {
e1623446 1848 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1849 "limit: %ddBm.\n", power);
1850 return 0;
1851 }
1852
e1623446 1853 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1854 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1855
1856 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1857
1858 for (i = 0; i < priv->channel_count; i++) {
1859 ch_info = &priv->channel_info[i];
1860 a_band = is_channel_a_band(ch_info);
1861
1862 /* find minimum power of all user and regulatory constraints
1863 * (does not consider h/w clipping limitations) */
bb8c093b 1864 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1865 max_power = min(power, max_power);
1866 if (max_power != ch_info->curr_txpow) {
1867 ch_info->curr_txpow = max_power;
1868
1869 /* this considers the h/w clipping limitations */
bb8c093b 1870 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1871 }
1872 }
1873
1874 /* update txpower settings for all channels,
1875 * send to NIC if associated. */
1876 is_temp_calib_needed(priv);
bb8c093b 1877 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1878
1879 return 0;
1880}
1881
5bbe233b
AK		 1882static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1883{
1884 int rc = 0;
1885 struct iwl_rx_packet *res = NULL;
1886 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1887 struct iwl_host_cmd cmd = {
1888 .id = REPLY_RXON_ASSOC,
1889 .len = sizeof(rxon_assoc),
1890 .meta.flags = CMD_WANT_SKB,
1891 .data = &rxon_assoc,
1892 };
1893 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1894 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1895
1896 if ((rxon1->flags == rxon2->flags) &&
1897 (rxon1->filter_flags == rxon2->filter_flags) &&
1898 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1899 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1900 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1901 return 0;
1902 }
1903
1904 rxon_assoc.flags = priv->staging_rxon.flags;
1905 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1906 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1907 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1908 rxon_assoc.reserved = 0;
1909
1910 rc = iwl_send_cmd_sync(priv, &cmd);
1911 if (rc)
1912 return rc;
1913
1914 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
1915 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1916 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1917 rc = -EIO;
1918 }
1919
1920 priv->alloc_rxb_skb--;
1921 dev_kfree_skb_any(cmd.meta.u.skb);
1922
1923 return rc;
1924}
1925
e0158e61
AK		 1926/**
1927 * iwl3945_commit_rxon - commit staging_rxon to hardware
1928 *
1929 * The RXON command in staging_rxon is committed to the hardware and
1930 * the active_rxon structure is updated with the new data. This
1931 * function correctly transitions out of the RXON_ASSOC_MSK state if
1932 * a HW tune is required based on the RXON structure changes.
1933 */
1934static int iwl3945_commit_rxon(struct iwl_priv *priv)
1935{
1936 /* cast away the const for active_rxon in this function */
1937 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1938 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1939 int rc = 0;
1940 bool new_assoc =
1941 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1942
1943 if (!iwl_is_alive(priv))
1944 return -1;
1945
1946 /* always get timestamp with Rx frame */
1947 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1948
1949 /* select antenna */
1950 staging_rxon->flags &=
1951 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1952 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1953
1954 rc = iwl_check_rxon_cmd(priv);
1955 if (rc) {
1956 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1957 return -EINVAL;
1958 }
1959
1960 /* If we don't need to send a full RXON, we can use
1961 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1962 * and other flags for the current radio configuration. */
1963 if (!iwl_full_rxon_required(priv)) {
1964 rc = iwl_send_rxon_assoc(priv);
1965 if (rc) {
1966 IWL_ERR(priv, "Error setting RXON_ASSOC "
1967 "configuration (%d).\n", rc);
1968 return rc;
1969 }
1970
1971 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1972
1973 return 0;
1974 }
1975
1976 /* If we are currently associated and the new config requires
1977 * an RXON_ASSOC and the new config wants the associated mask enabled,
1978 * we must clear the associated from the active configuration
1979 * before we apply the new config */
1980 if (iwl_is_associated(priv) && new_assoc) {
1981 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1982 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1983
1984 /*
1985 * reserved4 and 5 could have been filled by the iwlcore code.
1986 * Let's clear them before pushing to the 3945.
1987 */
1988 active_rxon->reserved4 = 0;
1989 active_rxon->reserved5 = 0;
1990 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1991 sizeof(struct iwl3945_rxon_cmd),
1992 &priv->active_rxon);
1993
1994 /* If the mask clearing failed then we set
1995 * active_rxon back to what it was previously */
1996 if (rc) {
1997 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1998 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1999 "configuration (%d).\n", rc);
2000 return rc;
2001 }
2002 }
2003
2004 IWL_DEBUG_INFO(priv, "Sending RXON\n"
2005 "* with%s RXON_FILTER_ASSOC_MSK\n"
2006 "* channel = %d\n"
2007 "* bssid = %pM\n",
2008 (new_assoc ? "" : "out"),
2009 le16_to_cpu(staging_rxon->channel),
2010 staging_rxon->bssid_addr);
2011
2012 /*
2013 * reserved4 and 5 could have been filled by the iwlcore code.
2014 * Let's clear them before pushing to the 3945.
2015 */
2016 staging_rxon->reserved4 = 0;
2017 staging_rxon->reserved5 = 0;
2018
2019 iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
2020
2021 /* Apply the new configuration */
2022 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
2023 sizeof(struct iwl3945_rxon_cmd),
2024 staging_rxon);
2025 if (rc) {
2026 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
2027 return rc;
2028 }
2029
2030 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
2031
40ace5b3 2032 priv->cfg->ops->smgmt->clear_station_table(priv);
e0158e61
AK		 2033
2034 /* If we issue a new RXON command which required a tune then we must
2035 * send a new TXPOWER command or we won't be able to Tx any frames */
2036 rc = priv->cfg->ops->lib->send_tx_power(priv);
2037 if (rc) {
2038 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
2039 return rc;
2040 }
2041
2042 /* Add the broadcast address so we can send broadcast frames */
06fd3d86 2043 if (priv->cfg->ops->smgmt->add_station(priv, iwl_bcast_addr, 0, 0, NULL) ==
e0158e61
AK		 2044 IWL_INVALID_STATION) {
2045 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
2046 return -EIO;
2047 }
2048
2049 /* If we have set the ASSOC_MSK and we are in BSS mode then
2050 * add the IWL_AP_ID to the station rate table */
2051 if (iwl_is_associated(priv) &&
2052 (priv->iw_mode == NL80211_IFTYPE_STATION))
40ace5b3 2053 if (priv->cfg->ops->smgmt->add_station(priv,
06fd3d86 2054 priv->active_rxon.bssid_addr, 1, 0, NULL)
e0158e61
AK		 2055 == IWL_INVALID_STATION) {
2056 IWL_ERR(priv, "Error adding AP address for transmit\n");
2057 return -EIO;
2058 }
2059
2060 /* Init the hardware's rate fallback order based on the band */
2061 rc = iwl3945_init_hw_rate_table(priv);
2062 if (rc) {
2063 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
2064 return -EIO;
2065 }
2066
2067 return 0;
2068}
2069
b481de9c 2070/* will add 3945 channel switch cmd handling later */
4a8a4322 2071int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2072{
2073 return 0;
2074}
2075
2076/**
2077 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
2078 *
2079 * -- reset periodic timer
2080 * -- see if temp has changed enough to warrant re-calibration ... if so:
2081 * -- correct coeffs for temp (can reset temp timer)
2082 * -- save this temp as "last",
2083 * -- send new set of gain settings to NIC
2084 * NOTE: This should continue working, even when we're not associated,
2085 * so we can keep our internal table of scan powers current. */
4a8a4322 2086void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 2087{
2088 /* This will kick in the "brute force"
bb8c093b 2089 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2090 if (!is_temp_calib_needed(priv))
2091 goto reschedule;
2092
2093 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2094 * This is based *only* on current temperature,
2095 * ignoring any previous power measurements */
bb8c093b 2096 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2097
2098 reschedule:
2099 queue_delayed_work(priv->workqueue,
2100 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2101}
2102
416e1438 2103static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2104{
4a8a4322 2105 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2106 thermal_periodic.work);
2107
2108 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2109 return;
2110
2111 mutex_lock(&priv->mutex);
2112 iwl3945_reg_txpower_periodic(priv);
2113 mutex_unlock(&priv->mutex);
2114}
2115
2116/**
bb8c093b 2117 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2118 * for the channel.
2119 *
2120 * This function is used when initializing channel-info structs.
2121 *
2122 * NOTE: These channel groups do *NOT* match the bands above!
2123 * These channel groups are based on factory-tested channels;
2124 * on A-band, EEPROM's "group frequency" entries represent the top
2125 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2126 */
4a8a4322 2127static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2128 const struct iwl_channel_info *ch_info)
b481de9c 2129{
e6148917
SO		 2130 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2131 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2132 u8 group;
2133 u16 group_index = 0; /* based on factory calib frequencies */
2134 u8 grp_channel;
2135
2136 /* Find the group index for the channel ... don't use index 1(?) */
2137 if (is_channel_a_band(ch_info)) {
2138 for (group = 1; group < 5; group++) {
2139 grp_channel = ch_grp[group].group_channel;
2140 if (ch_info->channel <= grp_channel) {
2141 group_index = group;
2142 break;
2143 }
2144 }
2145 /* group 4 has a few channels *above* its factory cal freq */
2146 if (group == 5)
2147 group_index = 4;
2148 } else
2149 group_index = 0; /* 2.4 GHz, group 0 */
2150
e1623446 2151 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2152 group_index);
2153 return group_index;
2154}
2155
2156/**
bb8c093b 2157 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2158 *
2159 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2160 * into radio/DSP gain settings table for requested power.
2161 */
4a8a4322 2162static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2163 s8 requested_power,
2164 s32 setting_index, s32 *new_index)
2165{
bb8c093b 2166 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2167 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2168 s32 index0, index1;
2169 s32 power = 2 * requested_power;
2170 s32 i;
bb8c093b 2171 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2172 s32 gains0, gains1;
2173 s32 res;
2174 s32 denominator;
2175
e6148917 2176 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2177 samples = chnl_grp->samples;
2178 for (i = 0; i < 5; i++) {
2179 if (power == samples[i].power) {
2180 *new_index = samples[i].gain_index;
2181 return 0;
2182 }
2183 }
2184
2185 if (power > samples[1].power) {
2186 index0 = 0;
2187 index1 = 1;
2188 } else if (power > samples[2].power) {
2189 index0 = 1;
2190 index1 = 2;
2191 } else if (power > samples[3].power) {
2192 index0 = 2;
2193 index1 = 3;
2194 } else {
2195 index0 = 3;
2196 index1 = 4;
2197 }
2198
2199 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2200 if (denominator == 0)
2201 return -EINVAL;
2202 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2203 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2204 res = gains0 + (gains1 - gains0) *
2205 ((s32) power - (s32) samples[index0].power) / denominator +
2206 (1 << 18);
2207 *new_index = res >> 19;
2208 return 0;
2209}
2210
4a8a4322 2211static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2212{
2213 u32 i;
2214 s32 rate_index;
e6148917 2215 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2216 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2217
e1623446 2218 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2219
2220 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2221 s8 *clip_pwrs; /* table of power levels for each rate */
2222 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2223 group = &eeprom->groups[i];
b481de9c
ZY		 2224
2225 /* sanity check on factory saturation power value */
2226 if (group->saturation_power < 40) {
39aadf8c 2227 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2228 "less than minimum expected 40\n",
2229 group->saturation_power);
2230 return;
2231 }
2232
2233 /*
2234 * Derive requested power levels for each rate, based on
2235 * hardware capabilities (saturation power for band).
2236 * Basic value is 3dB down from saturation, with further
2237 * power reductions for highest 3 data rates. These
2238 * backoffs provide headroom for high rate modulation
2239 * power peaks, without too much distortion (clipping).
2240 */
2241 /* we'll fill in this array with h/w max power levels */
f2c7e521 2242 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2243
2244 /* divide factory saturation power by 2 to find -3dB level */
2245 satur_pwr = (s8) (group->saturation_power >> 1);
2246
2247 /* fill in channel group's nominal powers for each rate */
2248 for (rate_index = 0;
2249 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2250 switch (rate_index) {
14577f23 2251 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2252 if (i == 0) /* B/G */
2253 *clip_pwrs = satur_pwr;
2254 else /* A */
2255 *clip_pwrs = satur_pwr - 5;
2256 break;
14577f23 2257 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2258 if (i == 0)
2259 *clip_pwrs = satur_pwr - 7;
2260 else
2261 *clip_pwrs = satur_pwr - 10;
2262 break;
14577f23 2263 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2264 if (i == 0)
2265 *clip_pwrs = satur_pwr - 9;
2266 else
2267 *clip_pwrs = satur_pwr - 12;
2268 break;
2269 default:
2270 *clip_pwrs = satur_pwr;
2271 break;
2272 }
2273 }
2274 }
2275}
2276
2277/**
2278 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2279 *
2280 * Second pass (during init) to set up priv->channel_info
2281 *
2282 * Set up Tx-power settings in our channel info database for each VALID
2283 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2284 * and current temperature.
2285 *
2286 * Since this is based on current temperature (at init time), these values may
2287 * not be valid for very long, but it gives us a starting/default point,
2288 * and allows us to active (i.e. using Tx) scan.
2289 *
2290 * This does *not* write values to NIC, just sets up our internal table.
2291 */
4a8a4322 2292int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2293{
d20b3c65 2294 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2295 struct iwl3945_channel_power_info *pwr_info;
e6148917 2296 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2297 int delta_index;
2298 u8 rate_index;
2299 u8 scan_tbl_index;
2300 const s8 *clip_pwrs; /* array of power levels for each rate */
2301 u8 gain, dsp_atten;
2302 s8 power;
2303 u8 pwr_index, base_pwr_index, a_band;
2304 u8 i;
2305 int temperature;
2306
2307 /* save temperature reference,
2308 * so we can determine next time to calibrate */
bb8c093b 2309 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2310 priv->last_temperature = temperature;
2311
bb8c093b 2312 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2313
2314 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2315 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2316 i++, ch_info++) {
2317 a_band = is_channel_a_band(ch_info);
2318 if (!is_channel_valid(ch_info))
2319 continue;
2320
2321 /* find this channel's channel group (*not* "band") index */
2322 ch_info->group_index =
bb8c093b 2323 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2324
2325 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2326 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2327
2328 /* calculate power index *adjustment* value according to
2329 * diff between current temperature and factory temperature */
bb8c093b 2330 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2331 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2332 temperature);
2333
e1623446 2334 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2335 ch_info->channel, delta_index, temperature +
2336 IWL_TEMP_CONVERT);
2337
2338 /* set tx power value for all OFDM rates */
2339 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2340 rate_index++) {
25a4ccea 2341 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2342 int rc;
2343
2344 /* use channel group's clip-power table,
2345 * but don't exceed channel's max power */
2346 s8 pwr = min(ch_info->max_power_avg,
2347 clip_pwrs[rate_index]);
2348
2349 pwr_info = &ch_info->power_info[rate_index];
2350
2351 /* get base (i.e. at factory-measured temperature)
2352 * power table index for this rate's power */
bb8c093b 2353 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2354 ch_info->group_index,
2355 &power_idx);
2356 if (rc) {
15b1687c 2357 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2358 return rc;
2359 }
2360 pwr_info->base_power_index = (u8) power_idx;
2361
2362 /* temperature compensate */
2363 power_idx += delta_index;
2364
2365 /* stay within range of gain table */
bb8c093b 2366 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2367
bb8c093b 2368 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2369 pwr_info->requested_power = pwr;
2370 pwr_info->power_table_index = (u8) power_idx;
2371 pwr_info->tpc.tx_gain =
2372 power_gain_table[a_band][power_idx].tx_gain;
2373 pwr_info->tpc.dsp_atten =
2374 power_gain_table[a_band][power_idx].dsp_atten;
2375 }
2376
2377 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2378 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2379 power = pwr_info->requested_power +
2380 IWL_CCK_FROM_OFDM_POWER_DIFF;
2381 pwr_index = pwr_info->power_table_index +
2382 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2383 base_pwr_index = pwr_info->base_power_index +
2384 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2385
2386 /* stay within table range */
bb8c093b 2387 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2388 gain = power_gain_table[a_band][pwr_index].tx_gain;
2389 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2390
bb8c093b 2391 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2392 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2393 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2394 for (rate_index = 0;
2395 rate_index < IWL_CCK_RATES; rate_index++) {
2396 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2397 pwr_info->requested_power = power;
2398 pwr_info->power_table_index = pwr_index;
2399 pwr_info->base_power_index = base_pwr_index;
2400 pwr_info->tpc.tx_gain = gain;
2401 pwr_info->tpc.dsp_atten = dsp_atten;
2402 }
2403
2404 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2405 for (scan_tbl_index = 0;
2406 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2407 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2408 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2409 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2410 actual_index, clip_pwrs, ch_info, a_band);
2411 }
2412 }
2413
2414 return 0;
2415}
2416
4a8a4322 2417int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2418{
2419 int rc;
b481de9c 2420
5d49f498
AK		 2421 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2422 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2423 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2424 if (rc < 0)
15b1687c 2425 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2426
b481de9c
ZY		 2427 return 0;
2428}
2429
188cf6c7 2430int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2431{
b481de9c
ZY		 2432 int txq_id = txq->q.id;
2433
3832ec9d 2434 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2435
2436 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2437
5d49f498
AK		 2438 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2439 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2440
5d49f498 2441 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2442 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2443 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2444 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2445 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2446 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2447
2448 /* fake read to flush all prev. writes */
5d49f498 2449 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2450
2451 return 0;
2452}
2453
42427b4e
KA		 2454/*
2455 * HCMD utils
2456 */
2457static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2458{
2459 switch (cmd_id) {
2460 case REPLY_RXON:
d25aabb0
WT		 2461 return sizeof(struct iwl3945_rxon_cmd);
2462 case POWER_TABLE_CMD:
2463 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2464 default:
2465 return len;
2466 }
2467}
2468
17f841cd
SO		 2469static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2470{
2471 u16 size = (u16)sizeof(struct iwl3945_addsta_cmd);
2472 memcpy(data, cmd, size);
2473 return size;
2474}
2475
b481de9c
ZY		 2476/**
2477 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2478 */
4a8a4322 2479int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2480{
14577f23 2481 int rc, i, index, prev_index;
bb8c093b 2482 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2483 .reserved = {0, 0, 0},
2484 };
bb8c093b 2485 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2486
bb8c093b
CH		 2487 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2488 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2489
2490 table[index].rate_n_flags =
bb8c093b 2491 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2492 table[index].try_cnt = priv->retry_rate;
bb8c093b 2493 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2494 table[index].next_rate_index =
2495 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2496 }
2497
8318d78a
JB		 2498 switch (priv->band) {
2499 case IEEE80211_BAND_5GHZ:
e1623446 2500 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2501 /* If one of the following CCK rates is used,
2502 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2503 for (i = IWL_RATE_1M_INDEX_TABLE;
2504 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2505 table[i].next_rate_index =
2506 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2507
2508 /* Don't fall back to CCK rates */
7262796a
AM		 2509 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2510 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2511
2512 /* Don't drop out of OFDM rates */
14577f23 2513 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2514 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2515 break;
2516
8318d78a 2517 case IEEE80211_BAND_2GHZ:
e1623446 2518 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2519 /* If an OFDM rate is used, have it fall back to the
2520 * 1M CCK rates */
b481de9c 2521
7262796a 2522 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2523 iwl_is_associated(priv)) {
7262796a
AM		 2524
2525 index = IWL_FIRST_CCK_RATE;
2526 for (i = IWL_RATE_6M_INDEX_TABLE;
2527 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2528 table[i].next_rate_index =
2529 iwl3945_rates[index].table_rs_index;
2530
2531 index = IWL_RATE_11M_INDEX_TABLE;
2532 /* CCK shouldn't fall back to OFDM... */
2533 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2534 }
b481de9c
ZY		 2535 break;
2536
2537 default:
8318d78a 2538 WARN_ON(1);
b481de9c
ZY		 2539 break;
2540 }
2541
2542 /* Update the rate scaling for control frame Tx */
2543 rate_cmd.table_id = 0;
518099a8 2544 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2545 &rate_cmd);
2546 if (rc)
2547 return rc;
2548
2549 /* Update the rate scaling for data frame Tx */
2550 rate_cmd.table_id = 1;
518099a8 2551 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2552 &rate_cmd);
2553}
2554
796083cb 2555/* Called when initializing driver */
4a8a4322 2556int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2557{
3832ec9d
AK		 2558 memset((void *)&priv->hw_params, 0,
2559 sizeof(struct iwl_hw_params));
b481de9c 2560
3832ec9d 2561 priv->shared_virt =
b481de9c 2562 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2563 sizeof(struct iwl3945_shared),
3832ec9d 2564 &priv->shared_phys);
b481de9c 2565
3832ec9d 2566 if (!priv->shared_virt) {
15b1687c 2567 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2568 mutex_unlock(&priv->mutex);
2569 return -ENOMEM;
2570 }
2571
21c02a1a
AK		 2572 /* Assign number of Usable TX queues */
2573 priv->hw_params.max_txq_num = TFD_QUEUE_MAX;
2574
a8e74e27 2575 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
1e33dc64 2576 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
3832ec9d
AK		 2577 priv->hw_params.max_pkt_size = 2342;
2578 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2579 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2580 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2581 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2582
141c43a3
WT		 2583 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2584
b481de9c
ZY		 2585 return 0;
2586}
2587
4a8a4322 2588unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2589 struct iwl3945_frame *frame, u8 rate)
b481de9c 2590{
bb8c093b 2591 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2592 unsigned int frame_size;
2593
bb8c093b 2594 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2595 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2596
3832ec9d 2597 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2598 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2599
bb8c093b 2600 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2601 tx_beacon_cmd->frame,
b481de9c
ZY		 2602 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2603
2604 BUG_ON(frame_size > MAX_MPDU_SIZE);
2605 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2606
2607 tx_beacon_cmd->tx.rate = rate;
2608 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2609 TX_CMD_FLG_TSF_MSK);
2610
14577f23
MA		 2611 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2612 tx_beacon_cmd->tx.supp_rates[0] =
2613 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2614
b481de9c 2615 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2616 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2617
3ac7f146 2618 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2619}
2620
4a8a4322 2621void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2622{
91c066f2 2623 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2624 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2625}
2626
4a8a4322 2627void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2628{
2629 INIT_DELAYED_WORK(&priv->thermal_periodic,
2630 iwl3945_bg_reg_txpower_periodic);
2631}
2632
4a8a4322 2633void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2634{
2635 cancel_delayed_work(&priv->thermal_periodic);
2636}
2637
0164b9b4
KA		 2638/* check contents of special bootstrap uCode SRAM */
2639static int iwl3945_verify_bsm(struct iwl_priv *priv)
2640 {
2641 __le32 *image = priv->ucode_boot.v_addr;
2642 u32 len = priv->ucode_boot.len;
2643 u32 reg;
2644 u32 val;
2645
e1623446 2646 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2647
2648 /* verify BSM SRAM contents */
2649 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2650 for (reg = BSM_SRAM_LOWER_BOUND;
2651 reg < BSM_SRAM_LOWER_BOUND + len;
2652 reg += sizeof(u32), image++) {
2653 val = iwl_read_prph(priv, reg);
2654 if (val != le32_to_cpu(*image)) {
2655 IWL_ERR(priv, "BSM uCode verification failed at "
2656 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2657 BSM_SRAM_LOWER_BOUND,
2658 reg - BSM_SRAM_LOWER_BOUND, len,
2659 val, le32_to_cpu(*image));
2660 return -EIO;
2661 }
2662 }
2663
e1623446 2664 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2665
2666 return 0;
2667}
2668
e6148917
SO		 2669
2670/******************************************************************************
2671 *
2672 * EEPROM related functions
2673 *
2674 ******************************************************************************/
2675
2676/*
2677 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2678 * embedded controller) as EEPROM reader; each read is a series of pulses
2679 * to/from the EEPROM chip, not a single event, so even reads could conflict
2680 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2681 * simply claims ownership, which should be safe when this function is called
2682 * (i.e. before loading uCode!).
2683 */
2684static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2685{
2686 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2687 return 0;
2688}
2689
2690
2691static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2692{
2693 return;
2694}
2695
0164b9b4
KA		 2696 /**
2697 * iwl3945_load_bsm - Load bootstrap instructions
2698 *
2699 * BSM operation:
2700 *
2701 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2702 * in special SRAM that does not power down during RFKILL. When powering back
2703 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2704 * the bootstrap program into the on-board processor, and starts it.
2705 *
2706 * The bootstrap program loads (via DMA) instructions and data for a new
2707 * program from host DRAM locations indicated by the host driver in the
2708 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2709 * automatically.
2710 *
2711 * When initializing the NIC, the host driver points the BSM to the
2712 * "initialize" uCode image. This uCode sets up some internal data, then
2713 * notifies host via "initialize alive" that it is complete.
2714 *
2715 * The host then replaces the BSM_DRAM_* pointer values to point to the
2716 * normal runtime uCode instructions and a backup uCode data cache buffer
2717 * (filled initially with starting data values for the on-board processor),
2718 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2719 * which begins normal operation.
2720 *
2721 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2722 * the backup data cache in DRAM before SRAM is powered down.
2723 *
2724 * When powering back up, the BSM loads the bootstrap program. This reloads
2725 * the runtime uCode instructions and the backup data cache into SRAM,
2726 * and re-launches the runtime uCode from where it left off.
2727 */
2728static int iwl3945_load_bsm(struct iwl_priv *priv)
2729{
2730 __le32 *image = priv->ucode_boot.v_addr;
2731 u32 len = priv->ucode_boot.len;
2732 dma_addr_t pinst;
2733 dma_addr_t pdata;
2734 u32 inst_len;
2735 u32 data_len;
2736 int rc;
2737 int i;
2738 u32 done;
2739 u32 reg_offset;
2740
e1623446 2741 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2742
2743 /* make sure bootstrap program is no larger than BSM's SRAM size */
2744 if (len > IWL39_MAX_BSM_SIZE)
2745 return -EINVAL;
2746
2747 /* Tell bootstrap uCode where to find the "Initialize" uCode
2748 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2749 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2750 * after the "initialize" uCode has run, to point to
2751 * runtime/protocol instructions and backup data cache. */
2752 pinst = priv->ucode_init.p_addr;
2753 pdata = priv->ucode_init_data.p_addr;
2754 inst_len = priv->ucode_init.len;
2755 data_len = priv->ucode_init_data.len;
2756
0164b9b4
KA		 2757 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2758 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2759 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2760 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2761
2762 /* Fill BSM memory with bootstrap instructions */
2763 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2764 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2765 reg_offset += sizeof(u32), image++)
2766 _iwl_write_prph(priv, reg_offset,
2767 le32_to_cpu(*image));
2768
2769 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2770 if (rc)
0164b9b4 2771 return rc;
0164b9b4
KA		 2772
2773 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2774 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2775 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2776 IWL39_RTC_INST_LOWER_BOUND);
2777 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2778
2779 /* Load bootstrap code into instruction SRAM now,
2780 * to prepare to load "initialize" uCode */
2781 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2782 BSM_WR_CTRL_REG_BIT_START);
2783
2784 /* Wait for load of bootstrap uCode to finish */
2785 for (i = 0; i < 100; i++) {
2786 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2787 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2788 break;
2789 udelay(10);
2790 }
2791 if (i < 100)
e1623446 2792 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2793 else {
2794 IWL_ERR(priv, "BSM write did not complete!\n");
2795 return -EIO;
2796 }
2797
2798 /* Enable future boot loads whenever power management unit triggers it
2799 * (e.g. when powering back up after power-save shutdown) */
2800 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2801 BSM_WR_CTRL_REG_BIT_START_EN);
2802
0164b9b4
KA		 2803 return 0;
2804}
2805
5bbe233b
AK		 2806static struct iwl_hcmd_ops iwl3945_hcmd = {
2807 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2808 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2809};
2810
0164b9b4 2811static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2812 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2813 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2814 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2815 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2816 .apm_ops = {
2817 .init = iwl3945_apm_init,
2818 .reset = iwl3945_apm_reset,
2819 .stop = iwl3945_apm_stop,
2820 .config = iwl3945_nic_config,
854682ed 2821 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2822 },
e6148917
SO		 2823 .eeprom_ops = {
2824 .regulatory_bands = {
2825 EEPROM_REGULATORY_BAND_1_CHANNELS,
2826 EEPROM_REGULATORY_BAND_2_CHANNELS,
2827 EEPROM_REGULATORY_BAND_3_CHANNELS,
2828 EEPROM_REGULATORY_BAND_4_CHANNELS,
2829 EEPROM_REGULATORY_BAND_5_CHANNELS,
a89d03c4
RC		 2830 EEPROM_REGULATORY_BAND_NO_FAT,
2831 EEPROM_REGULATORY_BAND_NO_FAT,
e6148917
SO		 2832 },
2833 .verify_signature = iwlcore_eeprom_verify_signature,
2834 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2835 .release_semaphore = iwl3945_eeprom_release_semaphore,
2836 .query_addr = iwlcore_eeprom_query_addr,
2837 },
75bcfae9 2838 .send_tx_power = iwl3945_send_tx_power,
c2436980 2839 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2840 .post_associate = iwl3945_post_associate,
60690a6a 2841 .config_ap = iwl3945_config_ap,
0164b9b4
KA		 2842};
2843
79fa455a
AK		 2844static struct iwl_station_mgmt_ops iwl3945_station_mgmt = {
2845 .add_station = iwl3945_add_station,
2846#if 0
2847 .remove_station = iwl3945_remove_station,
2848#endif
2849 .find_station = iwl3945_hw_find_station,
2850 .clear_station_table = iwl3945_clear_stations_table,
0164b9b4
KA		 2851};
2852
42427b4e
KA		 2853static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2854 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2855 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
42427b4e
KA		 2856};
2857
0164b9b4
KA		 2858static struct iwl_ops iwl3945_ops = {
2859 .lib = &iwl3945_lib,
5bbe233b 2860 .hcmd = &iwl3945_hcmd,
42427b4e 2861 .utils = &iwl3945_hcmd_utils,
79fa455a 2862 .smgmt = &iwl3945_station_mgmt,
0164b9b4
KA		 2863};
2864
c0f20d91 2865static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2866 .name = "3945BG",
a0987a8d
RC		 2867 .fw_name_pre = IWL3945_FW_PRE,
2868 .ucode_api_max = IWL3945_UCODE_API_MAX,
2869 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2870 .sku = IWL_SKU_G,
e6148917
SO		 2871 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2872 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2873 .ops = &iwl3945_ops,
df878d8f 2874 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2875};
2876
c0f20d91 2877static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2878 .name = "3945ABG",
a0987a8d
RC		 2879 .fw_name_pre = IWL3945_FW_PRE,
2880 .ucode_api_max = IWL3945_UCODE_API_MAX,
2881 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2882 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2883 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2884 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2885 .ops = &iwl3945_ops,
df878d8f 2886 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2887};
2888
bb8c093b 2889struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2890 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2891 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2892 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2893 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2894 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2895 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2896 {0}
2897};
2898
bb8c093b 2899MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)