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wl1251: re-disable PG10 chips
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
17f841cd 44#include "iwl-sta.h"
b481de9c 45#include "iwl-3945.h"
e6148917 46#include "iwl-eeprom.h"
5d08cd1d 47#include "iwl-helpers.h"
5747d47f 48#include "iwl-core.h"
e932a609
JB		 49#include "iwl-led.h"
50#include "iwl-3945-led.h"
b481de9c
ZY		 51
52#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
53 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 60 IWL_RATE_##np##M_INDEX, \
61 IWL_RATE_##r##M_INDEX_TABLE, \
62 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 63
64/*
65 * Parameter order:
66 * rate, prev rate, next rate, prev tgg rate, next tgg rate
67 *
68 * If there isn't a valid next or previous rate then INV is used which
69 * maps to IWL_RATE_INVALID
70 *
71 */
d9829a67 72const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 73 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
74 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
75 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
76 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 77 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
78 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
79 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
80 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
81 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
82 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
83 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
84 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 85};
86
bb8c093b 87/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 88#define IWL_EVT_DISABLE (0)
89#define IWL_EVT_DISABLE_SIZE (1532/32)
90
91/**
bb8c093b 92 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 93 *
94 * Disable an event by writing "1"s into "disable"
95 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
96 * Default values of 0 enable uCode events to be logged.
97 * Use for only special debugging. This function is just a placeholder as-is,
98 * you'll need to provide the special bits! ...
99 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 100void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 101{
b481de9c
ZY		 102 int i;
103 u32 base; /* SRAM address of event log header */
104 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
105 u32 array_size; /* # of u32 entries in array */
106 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107 0x00000000, /* 31 - 0 Event id numbers */
108 0x00000000, /* 63 - 32 */
109 0x00000000, /* 95 - 64 */
110 0x00000000, /* 127 - 96 */
111 0x00000000, /* 159 - 128 */
112 0x00000000, /* 191 - 160 */
113 0x00000000, /* 223 - 192 */
114 0x00000000, /* 255 - 224 */
115 0x00000000, /* 287 - 256 */
116 0x00000000, /* 319 - 288 */
117 0x00000000, /* 351 - 320 */
118 0x00000000, /* 383 - 352 */
119 0x00000000, /* 415 - 384 */
120 0x00000000, /* 447 - 416 */
121 0x00000000, /* 479 - 448 */
122 0x00000000, /* 511 - 480 */
123 0x00000000, /* 543 - 512 */
124 0x00000000, /* 575 - 544 */
125 0x00000000, /* 607 - 576 */
126 0x00000000, /* 639 - 608 */
127 0x00000000, /* 671 - 640 */
128 0x00000000, /* 703 - 672 */
129 0x00000000, /* 735 - 704 */
130 0x00000000, /* 767 - 736 */
131 0x00000000, /* 799 - 768 */
132 0x00000000, /* 831 - 800 */
133 0x00000000, /* 863 - 832 */
134 0x00000000, /* 895 - 864 */
135 0x00000000, /* 927 - 896 */
136 0x00000000, /* 959 - 928 */
137 0x00000000, /* 991 - 960 */
138 0x00000000, /* 1023 - 992 */
139 0x00000000, /* 1055 - 1024 */
140 0x00000000, /* 1087 - 1056 */
141 0x00000000, /* 1119 - 1088 */
142 0x00000000, /* 1151 - 1120 */
143 0x00000000, /* 1183 - 1152 */
144 0x00000000, /* 1215 - 1184 */
145 0x00000000, /* 1247 - 1216 */
146 0x00000000, /* 1279 - 1248 */
147 0x00000000, /* 1311 - 1280 */
148 0x00000000, /* 1343 - 1312 */
149 0x00000000, /* 1375 - 1344 */
150 0x00000000, /* 1407 - 1376 */
151 0x00000000, /* 1439 - 1408 */
152 0x00000000, /* 1471 - 1440 */
153 0x00000000, /* 1503 - 1472 */
154 };
155
156 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 157 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 158 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 159 return;
160 }
161
5d49f498
AK		 162 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
163 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 164
165 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 166 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 167 disable_ptr);
b481de9c 168 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 169 iwl_write_targ_mem(priv,
af7cca2a
TW		 170 disable_ptr + (i * sizeof(u32)),
171 evt_disable[i]);
b481de9c 172
b481de9c 173 } else {
e1623446
TW		 174 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
175 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
176 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 177 disable_ptr, array_size);
178 }
179
180}
181
17744ff6
TW		 182static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
183{
184 int idx;
185
186 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
187 if (iwl3945_rates[idx].plcp == plcp)
188 return idx;
189 return -1;
190}
191
d08853a3 192#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 193#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
194
195static const char *iwl3945_get_tx_fail_reason(u32 status)
196{
197 switch (status & TX_STATUS_MSK) {
198 case TX_STATUS_SUCCESS:
199 return "SUCCESS";
200 TX_STATUS_ENTRY(SHORT_LIMIT);
201 TX_STATUS_ENTRY(LONG_LIMIT);
202 TX_STATUS_ENTRY(FIFO_UNDERRUN);
203 TX_STATUS_ENTRY(MGMNT_ABORT);
204 TX_STATUS_ENTRY(NEXT_FRAG);
205 TX_STATUS_ENTRY(LIFE_EXPIRE);
206 TX_STATUS_ENTRY(DEST_PS);
207 TX_STATUS_ENTRY(ABORTED);
208 TX_STATUS_ENTRY(BT_RETRY);
209 TX_STATUS_ENTRY(STA_INVALID);
210 TX_STATUS_ENTRY(FRAG_DROPPED);
211 TX_STATUS_ENTRY(TID_DISABLE);
212 TX_STATUS_ENTRY(FRAME_FLUSHED);
213 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
214 TX_STATUS_ENTRY(TX_LOCKED);
215 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
216 }
217
218 return "UNKNOWN";
219}
220#else
221static inline const char *iwl3945_get_tx_fail_reason(u32 status)
222{
223 return "";
224}
225#endif
226
e6a9854b
JB		 227/*
228 * get ieee prev rate from rate scale table.
229 * for A and B mode we need to overright prev
230 * value
231 */
4a8a4322 232int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 233{
234 int next_rate = iwl3945_get_prev_ieee_rate(rate);
235
236 switch (priv->band) {
237 case IEEE80211_BAND_5GHZ:
238 if (rate == IWL_RATE_12M_INDEX)
239 next_rate = IWL_RATE_9M_INDEX;
240 else if (rate == IWL_RATE_6M_INDEX)
241 next_rate = IWL_RATE_6M_INDEX;
242 break;
7262796a
AM		 243 case IEEE80211_BAND_2GHZ:
244 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 245 iwl_is_associated(priv)) {
7262796a
AM		 246 if (rate == IWL_RATE_11M_INDEX)
247 next_rate = IWL_RATE_5M_INDEX;
248 }
e6a9854b 249 break;
7262796a 250
e6a9854b
JB		 251 default:
252 break;
253 }
254
255 return next_rate;
256}
257
91c066f2
TW		 258
259/**
260 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
261 *
262 * When FW advances 'R' index, all entries between old and new 'R' index
263 * need to be reclaimed. As result, some free space forms. If there is
264 * enough free space (> low mark), wake the stack that feeds us.
265 */
4a8a4322 266static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 267 int txq_id, int index)
268{
188cf6c7 269 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 270 struct iwl_queue *q = &txq->q;
dbb6654c 271 struct iwl_tx_info *tx_info;
91c066f2
TW		 272
273 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
274
275 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
276 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
277
278 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 279 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 280 tx_info->skb[0] = NULL;
7aaa1d79 281 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 282 }
283
d20b3c65 284 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 285 (txq_id != IWL_CMD_QUEUE_NUM) &&
286 priv->mac80211_registered)
e4e72fb4 287 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 288}
289
290/**
291 * iwl3945_rx_reply_tx - Handle Tx response
292 */
4a8a4322 293static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 294 struct iwl_rx_mem_buffer *rxb)
91c066f2 295{
2f301227 296 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 297 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
298 int txq_id = SEQ_TO_QUEUE(sequence);
299 int index = SEQ_TO_INDEX(sequence);
188cf6c7 300 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 301 struct ieee80211_tx_info *info;
91c066f2
TW		 302 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
303 u32 status = le32_to_cpu(tx_resp->status);
304 int rate_idx;
74221d07 305 int fail;
91c066f2 306
625a381a 307 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 308 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 309 "is out of range [0-%d] %d %d\n", txq_id,
310 index, txq->q.n_bd, txq->q.write_ptr,
311 txq->q.read_ptr);
312 return;
313 }
314
e039fa4a 315 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 316 ieee80211_tx_info_clear_status(info);
317
318 /* Fill the MRR chain with some info about on-chip retransmissions */
319 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
320 if (info->band == IEEE80211_BAND_5GHZ)
321 rate_idx -= IWL_FIRST_OFDM_RATE;
322
323 fail = tx_resp->failure_frame;
74221d07
AM		 324
325 info->status.rates[0].idx = rate_idx;
326 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 327
91c066f2 328 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 329 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
330 IEEE80211_TX_STAT_ACK : 0;
91c066f2 331
e1623446 332 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 333 txq_id, iwl3945_get_tx_fail_reason(status), status,
334 tx_resp->rate, tx_resp->failure_frame);
335
e1623446 336 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 337 iwl3945_tx_queue_reclaim(priv, txq_id, index);
338
339 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 340 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 341}
342
343
344
b481de9c
ZY		 345/*****************************************************************************
346 *
347 * Intel PRO/Wireless 3945ABG/BG Network Connection
348 *
349 * RX handler implementations
350 *
b481de9c
ZY		 351 *****************************************************************************/
352
396887a2
DH		 353void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
354 struct iwl_rx_mem_buffer *rxb)
b481de9c 355{
2f301227 356 struct iwl_rx_packet *pkt = rxb_addr(rxb);
e1623446 357 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 358 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 359 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
b481de9c 360
f2c7e521 361 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 362
e932a609 363 iwl_leds_background(priv);
b481de9c
ZY		 364}
365
17744ff6
TW		 366/******************************************************************************
367 *
368 * Misc. internal state and helper functions
369 *
370 ******************************************************************************/
d08853a3 371#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 372
373/**
374 * iwl3945_report_frame - dump frame to syslog during debug sessions
375 *
376 * You may hack this function to show different aspects of received frames,
377 * including selective frame dumps.
378 * group100 parameter selects whether to show 1 out of 100 good frames.
379 */
d08853a3 380static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 381 struct iwl_rx_packet *pkt,
17744ff6
TW		 382 struct ieee80211_hdr *header, int group100)
383{
384 u32 to_us;
385 u32 print_summary = 0;
386 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
387 u32 hundred = 0;
388 u32 dataframe = 0;
fd7c8a40 389 __le16 fc;
17744ff6
TW		 390 u16 seq_ctl;
391 u16 channel;
392 u16 phy_flags;
393 u16 length;
394 u16 status;
395 u16 bcn_tmr;
396 u32 tsf_low;
397 u64 tsf;
398 u8 rssi;
399 u8 agc;
400 u16 sig_avg;
401 u16 noise_diff;
402 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
403 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
404 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
405 u8 *data = IWL_RX_DATA(pkt);
406
407 /* MAC header */
fd7c8a40 408 fc = header->frame_control;
17744ff6
TW		 409 seq_ctl = le16_to_cpu(header->seq_ctrl);
410
411 /* metadata */
412 channel = le16_to_cpu(rx_hdr->channel);
413 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
414 length = le16_to_cpu(rx_hdr->len);
415
416 /* end-of-frame status and timestamp */
417 status = le32_to_cpu(rx_end->status);
418 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
419 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
420 tsf = le64_to_cpu(rx_end->timestamp);
421
422 /* signal statistics */
423 rssi = rx_stats->rssi;
424 agc = rx_stats->agc;
425 sig_avg = le16_to_cpu(rx_stats->sig_avg);
426 noise_diff = le16_to_cpu(rx_stats->noise_diff);
427
428 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
429
430 /* if data frame is to us and all is good,
431 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 432 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
433 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 434 dataframe = 1;
435 if (!group100)
436 print_summary = 1; /* print each frame */
437 else if (priv->framecnt_to_us < 100) {
438 priv->framecnt_to_us++;
439 print_summary = 0;
440 } else {
441 priv->framecnt_to_us = 0;
442 print_summary = 1;
443 hundred = 1;
444 }
445 } else {
446 /* print summary for all other frames */
447 print_summary = 1;
448 }
449
450 if (print_summary) {
451 char *title;
0ff1cca0 452 int rate;
17744ff6
TW		 453
454 if (hundred)
455 title = "100Frames";
fd7c8a40 456 else if (ieee80211_has_retry(fc))
17744ff6 457 title = "Retry";
fd7c8a40 458 else if (ieee80211_is_assoc_resp(fc))
17744ff6 459 title = "AscRsp";
fd7c8a40 460 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 461 title = "RasRsp";
fd7c8a40 462 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 463 title = "PrbRsp";
464 print_dump = 1; /* dump frame contents */
465 } else if (ieee80211_is_beacon(fc)) {
466 title = "Beacon";
467 print_dump = 1; /* dump frame contents */
468 } else if (ieee80211_is_atim(fc))
469 title = "ATIM";
470 else if (ieee80211_is_auth(fc))
471 title = "Auth";
472 else if (ieee80211_is_deauth(fc))
473 title = "DeAuth";
474 else if (ieee80211_is_disassoc(fc))
475 title = "DisAssoc";
476 else
477 title = "Frame";
478
479 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
480 if (rate == -1)
481 rate = 0;
482 else
483 rate = iwl3945_rates[rate].ieee / 2;
484
485 /* print frame summary.
486 * MAC addresses show just the last byte (for brevity),
487 * but you can hack it to show more, if you'd like to. */
488 if (dataframe)
e1623446 489 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 490 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 491 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 492 length, rssi, channel, rate);
493 else {
494 /* src/dst addresses assume managed mode */
e1623446 495 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 496 "src=0x%02x, rssi=%u, tim=%lu usec, "
497 "phy=0x%02x, chnl=%d\n",
fd7c8a40 498 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 499 header->addr3[5], rssi,
500 tsf_low - priv->scan_start_tsf,
501 phy_flags, channel);
502 }
503 }
504 if (print_dump)
3d816c77 505 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 506}
d08853a3
SO		 507
508static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
509 struct iwl_rx_packet *pkt,
510 struct ieee80211_hdr *header, int group100)
511{
3d816c77 512 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 513 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
514}
515
17744ff6 516#else
4a8a4322 517static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 518 struct iwl_rx_packet *pkt,
17744ff6
TW		 519 struct ieee80211_hdr *header, int group100)
520{
521}
522#endif
523
4bd9b4f3 524/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 525static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 526 struct ieee80211_hdr *header)
527{
528 /* Filter incoming packets to determine if they are targeted toward
529 * this network, discarding packets coming from ourselves */
530 switch (priv->iw_mode) {
05c914fe 531 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 532 /* packets to our IBSS update information */
533 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 534 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 535 /* packets to our IBSS update information */
536 return !compare_ether_addr(header->addr2, priv->bssid);
537 default:
538 return 1;
539 }
540}
17744ff6 541
4a8a4322 542static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 543 struct iwl_rx_mem_buffer *rxb,
12342c47 544 struct ieee80211_rx_status *stats)
b481de9c 545{
2f301227 546 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 547 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 548 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
549 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 550 u16 len = le16_to_cpu(rx_hdr->len);
551 struct sk_buff *skb;
552 int ret;
b481de9c
ZY		 553
554 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 555 if (unlikely(len + IWL39_RX_FRAME_SIZE >
556 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 557 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 558 return;
559 }
560
561 /* We only process data packets if the interface is open */
562 if (unlikely(!priv->is_open)) {
e1623446
TW		 563 IWL_DEBUG_DROP_LIMIT(priv,
564 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 565 return;
566 }
b481de9c 567
2f301227
ZY		 568 skb = alloc_skb(IWL_LINK_HDR_MAX, GFP_ATOMIC);
569 if (!skb) {
570 IWL_ERR(priv, "alloc_skb failed\n");
571 return;
572 }
b481de9c 573
9c74d9fb 574 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 575 iwl_set_decrypted_flag(priv,
2f301227 576 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 577 le32_to_cpu(rx_end->status), stats);
578
2f301227
ZY		 579 skb_add_rx_frag(skb, 0, rxb->page,
580 (void *)rx_hdr->payload - (void *)pkt, len);
581
582 /* mac80211 currently doesn't support paged SKB. Convert it to
583 * linear SKB for management frame and data frame requires
584 * software decryption or software defragementation. */
585 if (ieee80211_is_mgmt(hdr->frame_control) ||
586 ieee80211_has_protected(hdr->frame_control) ||
587 ieee80211_has_morefrags(hdr->frame_control) ||
588 le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
589 ret = skb_linearize(skb);
590 else
591 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
592 0 : -ENOMEM;
593
594 if (ret) {
595 kfree_skb(skb);
596 goto out;
597 }
598
22fdf3c9
WYG		 599 iwl_update_stats(priv, false, hdr->frame_control, len);
600
2f301227
ZY		 601 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
602 ieee80211_rx(priv->hw, skb);
603
604 out:
605 priv->alloc_rxb_page--;
606 rxb->page = NULL;
b481de9c
ZY		 607}
608
7878a5a4
MA		 609#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
610
4a8a4322 611static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 612 struct iwl_rx_mem_buffer *rxb)
b481de9c 613{
17744ff6
TW		 614 struct ieee80211_hdr *header;
615 struct ieee80211_rx_status rx_status;
2f301227 616 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 617 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
618 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
619 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 620 int snr;
b481de9c
ZY		 621 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
622 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 623 u8 network_packet;
17744ff6 624
17744ff6
TW		 625 rx_status.flag = 0;
626 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 627 rx_status.freq =
c0186078 628 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 629 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
630 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
631
632 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 633 if (rx_status.band == IEEE80211_BAND_5GHZ)
634 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 635
9024adf5 636 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 637 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
638
639 /* set the preamble flag if appropriate */
640 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
641 rx_status.flag |= RX_FLAG_SHORTPRE;
642
b481de9c 643 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 644 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
645 rx_stats->phy_count);
b481de9c
ZY		 646 return;
647 }
648
649 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
650 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 651 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 652 return;
653 }
654
56decd3c 655
b481de9c
ZY		 656
657 /* Convert 3945's rssi indicator to dBm */
250bdd21 658 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 659
660 /* Set default noise value to -127 */
661 if (priv->last_rx_noise == 0)
662 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
663
664 /* 3945 provides noise info for OFDM frames only.
665 * sig_avg and noise_diff are measured by the 3945's digital signal
666 * processor (DSP), and indicate linear levels of signal level and
667 * distortion/noise within the packet preamble after
668 * automatic gain control (AGC). sig_avg should stay fairly
669 * constant if the radio's AGC is working well.
670 * Since these values are linear (not dB or dBm), linear
671 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
672 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
673 * to obtain noise level in dBm.
17744ff6 674 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 675 if (rx_stats_noise_diff) {
676 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 677 rx_status.noise = rx_status.signal -
17744ff6 678 iwl3945_calc_db_from_ratio(snr);
566bfe5a 679 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 680 rx_status.noise);
b481de9c
ZY		 681
682 /* If noise info not available, calculate signal quality indicator (%)
683 * using just the dBm signal level. */
684 } else {
17744ff6 685 rx_status.noise = priv->last_rx_noise;
566bfe5a 686 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 687 }
688
689
e1623446 690 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 691 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 692 rx_stats_sig_avg, rx_stats_noise_diff);
693
b481de9c
ZY		 694 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
695
bb8c093b 696 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 697
e1623446 698 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
17744ff6
TW		 699 network_packet ? '*' : ' ',
700 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 701 rx_status.signal, rx_status.signal,
702 rx_status.noise, rx_status.rate_idx);
b481de9c 703
d08853a3
SO		 704 /* Set "1" to report good data frames in groups of 100 */
705 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 706 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 707
708 if (network_packet) {
709 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
710 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 711 priv->last_rx_rssi = rx_status.signal;
17744ff6 712 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 713 }
714
12e5e22d 715 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 716}
717
7aaa1d79
SO		 718int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
719 struct iwl_tx_queue *txq,
720 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 721{
722 int count;
7aaa1d79 723 struct iwl_queue *q;
59606ffa 724 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 725
726 q = &txq->q;
59606ffa
SO		 727 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
728 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 729
730 if (reset)
731 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 732
733 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 734
735 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 736 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 737 NUM_TFD_CHUNKS);
738 return -EINVAL;
739 }
740
dbb6654c
WT		 741 tfd->tbs[count].addr = cpu_to_le32(addr);
742 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 743
744 count++;
745
746 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
747 TFD_CTL_PAD_SET(pad));
748
749 return 0;
750}
751
752/**
bb8c093b 753 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 754 *
755 * Does NOT advance any indexes
756 */
7aaa1d79 757void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 758{
59606ffa 759 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 760 int index = txq->q.read_ptr;
761 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 762 struct pci_dev *dev = priv->pci_dev;
763 int i;
764 int counter;
765
b481de9c 766 /* sanity check */
dbb6654c 767 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 768 if (counter > NUM_TFD_CHUNKS) {
15b1687c 769 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 770 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 771 return;
b481de9c
ZY		 772 }
773
fd9377ee
RC		 774 /* Unmap tx_cmd */
775 if (counter)
776 pci_unmap_single(dev,
c2acea8e
JB		 777 pci_unmap_addr(&txq->meta[index], mapping),
778 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 779 PCI_DMA_TODEVICE);
780
b481de9c
ZY		 781 /* unmap chunks if any */
782
783 for (i = 1; i < counter; i++) {
dbb6654c
WT		 784 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
785 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 786 if (txq->txb[txq->q.read_ptr].skb[0]) {
787 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
788 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 789 /* Can be called from interrupt context */
790 dev_kfree_skb_any(skb);
fc4b6853 791 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 792 }
793 }
794 }
7aaa1d79 795 return ;
b481de9c
ZY		 796}
797
b481de9c 798/**
bb8c093b 799 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 800 *
801*/
c2acea8e
JB		 802void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
803 struct iwl_device_cmd *cmd,
804 struct ieee80211_tx_info *info,
805 struct ieee80211_hdr *hdr,
806 int sta_id, int tx_id)
b481de9c 807{
e039fa4a 808 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 809 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 810 u16 rate_mask;
811 int rate;
812 u8 rts_retry_limit;
813 u8 data_retry_limit;
814 __le32 tx_flags;
fd7c8a40 815 __le16 fc = hdr->frame_control;
9744c91f 816 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 817
bb8c093b 818 rate = iwl3945_rates[rate_index].plcp;
9744c91f 819 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 820
821 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 822 * in this running context */
b481de9c
ZY		 823 rate_mask = IWL_RATES_MASK;
824
768db982
AK		 825
826 /* Set retry limit on DATA packets and Probe Responses*/
827 if (ieee80211_is_probe_resp(fc))
828 data_retry_limit = 3;
829 else
830 data_retry_limit = IWL_DEFAULT_TX_RETRY;
831 tx_cmd->data_retry_limit = data_retry_limit;
832
b481de9c
ZY		 833 if (tx_id >= IWL_CMD_QUEUE_NUM)
834 rts_retry_limit = 3;
835 else
836 rts_retry_limit = 7;
837
768db982
AK		 838 if (data_retry_limit < rts_retry_limit)
839 rts_retry_limit = data_retry_limit;
840 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 841
fd7c8a40
HH		 842 if (ieee80211_is_mgmt(fc)) {
843 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
844 case cpu_to_le16(IEEE80211_STYPE_AUTH):
845 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
846 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
847 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 848 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
849 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
850 tx_flags |= TX_CMD_FLG_CTS_MSK;
851 }
852 break;
853 default:
854 break;
855 }
856 }
857
9744c91f
AK		 858 tx_cmd->rate = rate;
859 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 860
861 /* OFDM */
9744c91f 862 tx_cmd->supp_rates[0] =
14577f23 863 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 864
865 /* CCK */
9744c91f 866 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 867
e1623446 868 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 869 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 870 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
871 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 872}
873
4a8a4322 874u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 875{
876 unsigned long flags_spin;
c587de0b 877 struct iwl_station_entry *station;
b481de9c
ZY		 878
879 if (sta_id == IWL_INVALID_STATION)
880 return IWL_INVALID_STATION;
881
882 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 883 station = &priv->stations[sta_id];
b481de9c
ZY		 884
885 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
886 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 887 station->sta.mode = STA_CONTROL_MODIFY_MSK;
888
889 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
890
c587de0b 891 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 892 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 893 sta_id, tx_rate);
894 return sta_id;
895}
896
854682ed 897static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 898{
854682ed 899 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 900 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 901 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 902 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
903 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 904
5d49f498 905 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 906 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
907 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 908 }
b481de9c 909 } else {
5d49f498 910 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 911 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
912 ~APMG_PS_CTRL_MSK_PWR_SRC);
913
5d49f498 914 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 915 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
916 }
b481de9c 917
a8b50a0a 918 return 0;
b481de9c
ZY		 919}
920
4a8a4322 921static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 922{
5d49f498 923 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 924 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 925 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
926 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 927 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
928 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
929 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
930 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
931 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
932 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
933 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
934 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 935
936 /* fake read to flush all prev I/O */
5d49f498 937 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 938
b481de9c
ZY		 939 return 0;
940}
941
4a8a4322 942static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 943{
b481de9c
ZY		 944
945 /* bypass mode */
5d49f498 946 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 947
948 /* RA 0 is active */
5d49f498 949 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 950
951 /* all 6 fifo are active */
5d49f498 952 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 953
5d49f498
AK		 954 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
955 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
956 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
957 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 958
5d49f498 959 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 960 priv->shared_phys);
b481de9c 961
5d49f498 962 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 963 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
964 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
965 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
966 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
967 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
968 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
969 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 970
b481de9c
ZY		 971
972 return 0;
973}
974
975/**
976 * iwl3945_txq_ctx_reset - Reset TX queue context
977 *
978 * Destroys all DMA structures and initialize them again
979 */
4a8a4322 980static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 981{
982 int rc;
983 int txq_id, slots_num;
984
bb8c093b 985 iwl3945_hw_txq_ctx_free(priv);
b481de9c 986
88804e2b
WYG		 987 /* allocate tx queue structure */
988 rc = iwl_alloc_txq_mem(priv);
989 if (rc)
990 return rc;
991
b481de9c
ZY		 992 /* Tx CMD queue */
993 rc = iwl3945_tx_reset(priv);
994 if (rc)
995 goto error;
996
997 /* Tx queue(s) */
5905a1aa 998 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 999 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1000 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 1001 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1002 txq_id);
b481de9c 1003 if (rc) {
15b1687c 1004 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1005 goto error;
1006 }
1007 }
1008
1009 return rc;
1010
1011 error:
bb8c093b 1012 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1013 return rc;
1014}
1015
f33269b8
BC		 1016/*
1017 * Start up NIC's basic functionality after it has been reset
1018 * (e.g. after platform boot, or shutdown via iwl3945_apm_stop())
1019 * NOTE: This does not load uCode nor start the embedded processor
1020 */
01ec616d 1021static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1022{
a8b50a0a 1023 int ret;
b481de9c 1024
f33269b8
BC		 1025 /* Configure chip clock phase-lock-loop */
1026 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1027
1028 /*
1029 * Disable L0S exit timer (platform NMI Work/Around)
1030 * (does this do anything on 3945, or just 4965 and beyond?)
1031 */
5d49f498 1032 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1033 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1034
f33269b8 1035 /* Disable L0s without affecting L1; don't wait for ICH (L0s bug W/A) */
01ec616d
KA		 1036 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1037 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1038
f33269b8
BC		 1039 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1040 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1041
1042 /*
1043 * Set "initialization complete" bit to move adapter from
1044 * D0U* --> D0A* (powered-up active) state.
1045 */
5d49f498 1046 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d 1047
f33269b8
BC		 1048 /*
1049 * Wait for clock stabilization; once stabilized, access to
1050 * device-internal resources is supported, e.g. iwl_write_prph()
1051 * and accesses to uCode SRAM.
1052 */
1739d332
AK		 1053 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1054 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1055 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
01ec616d 1056 if (ret < 0) {
e1623446 1057 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
01ec616d 1058 goto out;
b481de9c
ZY		 1059 }
1060
f33269b8 1061 /* Enable DMA and BSM clocks, wait for them to stabilize */
01ec616d
KA		 1062 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1063 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 1064 udelay(20);
01ec616d 1065
f33269b8
BC		 1066 /* Clear APMG (NIC's internal power management) interrupts */
1067 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1068 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1069
1070 /* Reset radio chip */
1071 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1072 udelay(5);
1073 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1074
1075 /* Disable L1-Active */
5d49f498 1076 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1077 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1078
01ec616d
KA		 1079out:
1080 return ret;
1081}
b481de9c 1082
01ec616d
KA		 1083static void iwl3945_nic_config(struct iwl_priv *priv)
1084{
e6148917 1085 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1086 unsigned long flags;
1087 u8 rev_id = 0;
b481de9c 1088
b481de9c
ZY		 1089 spin_lock_irqsave(&priv->lock, flags);
1090
43121432
AK		 1091 /* Determine HW type */
1092 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1093
1094 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1095
b481de9c 1096 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
e1623446 1097 IWL_DEBUG_INFO(priv, "RTP type \n");
b481de9c 1098 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1099 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1100 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1101 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1102 } else {
e1623446 1103 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1104 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1105 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1106 }
1107
e6148917 1108 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1109 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1110 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1111 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1112 } else
e1623446 1113 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1114
e6148917 1115 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1116 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1117 eeprom->board_revision);
5d49f498 1118 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1119 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1120 } else {
e1623446 1121 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1122 eeprom->board_revision);
5d49f498 1123 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1124 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1125 }
1126
e6148917 1127 if (eeprom->almgor_m_version <= 1) {
5d49f498 1128 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1129 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1130 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1131 eeprom->almgor_m_version);
b481de9c 1132 } else {
e1623446 1133 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1134 eeprom->almgor_m_version);
5d49f498 1135 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1136 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1137 }
1138 spin_unlock_irqrestore(&priv->lock, flags);
1139
e6148917 1140 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1141 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1142
e6148917 1143 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1144 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1145}
1146
1147int iwl3945_hw_nic_init(struct iwl_priv *priv)
1148{
01ec616d
KA		 1149 int rc;
1150 unsigned long flags;
1151 struct iwl_rx_queue *rxq = &priv->rxq;
1152
1153 spin_lock_irqsave(&priv->lock, flags);
1154 priv->cfg->ops->lib->apm_ops.init(priv);
1155 spin_unlock_irqrestore(&priv->lock, flags);
1156
854682ed 1157 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1158 if (rc)
854682ed
KA		 1159 return rc;
1160
01ec616d 1161 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1162
1163 /* Allocate the RX queue, or reset if it is already allocated */
1164 if (!rxq->bd) {
51af3d3f 1165 rc = iwl_rx_queue_alloc(priv);
b481de9c 1166 if (rc) {
15b1687c 1167 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1168 return -ENOMEM;
1169 }
1170 } else
df833b1d 1171 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1172
bb8c093b 1173 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1174
1175 iwl3945_rx_init(priv, rxq);
1176
b481de9c
ZY		 1177
1178 /* Look at using this instead:
1179 rxq->need_update = 1;
141c43a3 1180 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1181 */
1182
5d49f498 1183 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1184
1185 rc = iwl3945_txq_ctx_reset(priv);
1186 if (rc)
1187 return rc;
1188
1189 set_bit(STATUS_INIT, &priv->status);
1190
1191 return 0;
1192}
1193
1194/**
bb8c093b 1195 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1196 *
1197 * Destroy all TX DMA queues and structures
1198 */
4a8a4322 1199void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1200{
1201 int txq_id;
1202
1203 /* Tx queues */
88804e2b
WYG		 1204 if (priv->txq)
1205 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1206 txq_id++)
1207 if (txq_id == IWL_CMD_QUEUE_NUM)
1208 iwl_cmd_queue_free(priv);
1209 else
1210 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1211
88804e2b
WYG		 1212 /* free tx queue structure */
1213 iwl_free_txq_mem(priv);
b481de9c
ZY		 1214}
1215
4a8a4322 1216void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1217{
bddadf86 1218 int txq_id;
b481de9c
ZY		 1219
1220 /* stop SCD */
5d49f498 1221 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1222
1223 /* reset TFD queues */
5905a1aa 1224 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1225 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1226 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1227 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1228 1000);
1229 }
1230
bb8c093b 1231 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1232}
1233
b481de9c 1234/**
bb8c093b 1235 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1236 * return index delta into power gain settings table
1237*/
bb8c093b 1238static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1239{
1240 return (new_reading - old_reading) * (-11) / 100;
1241}
1242
1243/**
bb8c093b 1244 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1245 */
bb8c093b 1246static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1247{
3ac7f146 1248 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1249}
1250
4a8a4322 1251int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1252{
5d49f498 1253 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1254}
1255
1256/**
bb8c093b 1257 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1258 * get the current temperature by reading from NIC
1259*/
4a8a4322 1260static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1261{
e6148917 1262 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1263 int temperature;
1264
bb8c093b 1265 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1266
1267 /* driver's okay range is -260 to +25.
1268 * human readable okay range is 0 to +285 */
e1623446 1269 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1270
1271 /* handle insane temp reading */
bb8c093b 1272 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1273 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1274
1275 /* if really really hot(?),
1276 * substitute the 3rd band/group's temp measured at factory */
1277 if (priv->last_temperature > 100)
e6148917 1278 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1279 else /* else use most recent "sane" value from driver */
1280 temperature = priv->last_temperature;
1281 }
1282
1283 return temperature; /* raw, not "human readable" */
1284}
1285
1286/* Adjust Txpower only if temperature variance is greater than threshold.
1287 *
1288 * Both are lower than older versions' 9 degrees */
1289#define IWL_TEMPERATURE_LIMIT_TIMER 6
1290
1291/**
1292 * is_temp_calib_needed - determines if new calibration is needed
1293 *
1294 * records new temperature in tx_mgr->temperature.
1295 * replaces tx_mgr->last_temperature *only* if calib needed
1296 * (assumes caller will actually do the calibration!). */
4a8a4322 1297static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1298{
1299 int temp_diff;
1300
bb8c093b 1301 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1302 temp_diff = priv->temperature - priv->last_temperature;
1303
1304 /* get absolute value */
1305 if (temp_diff < 0) {
e1623446 1306 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1307 temp_diff = -temp_diff;
1308 } else if (temp_diff == 0)
e1623446 1309 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1310 else
e1623446 1311 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1312
1313 /* if we don't need calibration, *don't* update last_temperature */
1314 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1315 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1316 return 0;
1317 }
1318
e1623446 1319 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1320
1321 /* assume that caller will actually do calib ...
1322 * update the "last temperature" value */
1323 priv->last_temperature = priv->temperature;
1324 return 1;
1325}
1326
1327#define IWL_MAX_GAIN_ENTRIES 78
1328#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1329#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1330
1331/* radio and DSP power table, each step is 1/2 dB.
1332 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1333static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1334 {
1335 {251, 127}, /* 2.4 GHz, highest power */
1336 {251, 127},
1337 {251, 127},
1338 {251, 127},
1339 {251, 125},
1340 {251, 110},
1341 {251, 105},
1342 {251, 98},
1343 {187, 125},
1344 {187, 115},
1345 {187, 108},
1346 {187, 99},
1347 {243, 119},
1348 {243, 111},
1349 {243, 105},
1350 {243, 97},
1351 {243, 92},
1352 {211, 106},
1353 {211, 100},
1354 {179, 120},
1355 {179, 113},
1356 {179, 107},
1357 {147, 125},
1358 {147, 119},
1359 {147, 112},
1360 {147, 106},
1361 {147, 101},
1362 {147, 97},
1363 {147, 91},
1364 {115, 107},
1365 {235, 121},
1366 {235, 115},
1367 {235, 109},
1368 {203, 127},
1369 {203, 121},
1370 {203, 115},
1371 {203, 108},
1372 {203, 102},
1373 {203, 96},
1374 {203, 92},
1375 {171, 110},
1376 {171, 104},
1377 {171, 98},
1378 {139, 116},
1379 {227, 125},
1380 {227, 119},
1381 {227, 113},
1382 {227, 107},
1383 {227, 101},
1384 {227, 96},
1385 {195, 113},
1386 {195, 106},
1387 {195, 102},
1388 {195, 95},
1389 {163, 113},
1390 {163, 106},
1391 {163, 102},
1392 {163, 95},
1393 {131, 113},
1394 {131, 106},
1395 {131, 102},
1396 {131, 95},
1397 {99, 113},
1398 {99, 106},
1399 {99, 102},
1400 {99, 95},
1401 {67, 113},
1402 {67, 106},
1403 {67, 102},
1404 {67, 95},
1405 {35, 113},
1406 {35, 106},
1407 {35, 102},
1408 {35, 95},
1409 {3, 113},
1410 {3, 106},
1411 {3, 102},
1412 {3, 95} }, /* 2.4 GHz, lowest power */
1413 {
1414 {251, 127}, /* 5.x GHz, highest power */
1415 {251, 120},
1416 {251, 114},
1417 {219, 119},
1418 {219, 101},
1419 {187, 113},
1420 {187, 102},
1421 {155, 114},
1422 {155, 103},
1423 {123, 117},
1424 {123, 107},
1425 {123, 99},
1426 {123, 92},
1427 {91, 108},
1428 {59, 125},
1429 {59, 118},
1430 {59, 109},
1431 {59, 102},
1432 {59, 96},
1433 {59, 90},
1434 {27, 104},
1435 {27, 98},
1436 {27, 92},
1437 {115, 118},
1438 {115, 111},
1439 {115, 104},
1440 {83, 126},
1441 {83, 121},
1442 {83, 113},
1443 {83, 105},
1444 {83, 99},
1445 {51, 118},
1446 {51, 111},
1447 {51, 104},
1448 {51, 98},
1449 {19, 116},
1450 {19, 109},
1451 {19, 102},
1452 {19, 98},
1453 {19, 93},
1454 {171, 113},
1455 {171, 107},
1456 {171, 99},
1457 {139, 120},
1458 {139, 113},
1459 {139, 107},
1460 {139, 99},
1461 {107, 120},
1462 {107, 113},
1463 {107, 107},
1464 {107, 99},
1465 {75, 120},
1466 {75, 113},
1467 {75, 107},
1468 {75, 99},
1469 {43, 120},
1470 {43, 113},
1471 {43, 107},
1472 {43, 99},
1473 {11, 120},
1474 {11, 113},
1475 {11, 107},
1476 {11, 99},
1477 {131, 107},
1478 {131, 99},
1479 {99, 120},
1480 {99, 113},
1481 {99, 107},
1482 {99, 99},
1483 {67, 120},
1484 {67, 113},
1485 {67, 107},
1486 {67, 99},
1487 {35, 120},
1488 {35, 113},
1489 {35, 107},
1490 {35, 99},
1491 {3, 120} } /* 5.x GHz, lowest power */
1492};
1493
bb8c093b 1494static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1495{
1496 if (index < 0)
1497 return 0;
1498 if (index >= IWL_MAX_GAIN_ENTRIES)
1499 return IWL_MAX_GAIN_ENTRIES - 1;
1500 return (u8) index;
1501}
1502
1503/* Kick off thermal recalibration check every 60 seconds */
1504#define REG_RECALIB_PERIOD (60)
1505
1506/**
bb8c093b 1507 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1508 *
1509 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1510 * or 6 Mbit (OFDM) rates.
1511 */
4a8a4322 1512static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1513 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1514 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1515 int band_index)
1516{
bb8c093b 1517 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1518 s8 power;
1519 u8 power_index;
1520
1521 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1522
1523 /* use this channel group's 6Mbit clipping/saturation pwr,
1524 * but cap at regulatory scan power restriction (set during init
1525 * based on eeprom channel data) for this channel. */
14577f23 1526 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1527
1528 /* further limit to user's max power preference.
1529 * FIXME: Other spectrum management power limitations do not
1530 * seem to apply?? */
62ea9c5b 1531 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1532 scan_power_info->requested_power = power;
1533
1534 /* find difference between new scan *power* and current "normal"
1535 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1536 * current "normal" temperature-compensated Tx power *index* for
1537 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1538 * *index*. */
1539 power_index = ch_info->power_info[rate_index].power_table_index
1540 - (power - ch_info->power_info
14577f23 1541 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1542
1543 /* store reference index that we use when adjusting *all* scan
1544 * powers. So we can accommodate user (all channel) or spectrum
1545 * management (single channel) power changes "between" temperature
1546 * feedback compensation procedures.
1547 * don't force fit this reference index into gain table; it may be a
1548 * negative number. This will help avoid errors when we're at
1549 * the lower bounds (highest gains, for warmest temperatures)
1550 * of the table. */
1551
1552 /* don't exceed table bounds for "real" setting */
bb8c093b 1553 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1554
1555 scan_power_info->power_table_index = power_index;
1556 scan_power_info->tpc.tx_gain =
1557 power_gain_table[band_index][power_index].tx_gain;
1558 scan_power_info->tpc.dsp_atten =
1559 power_gain_table[band_index][power_index].dsp_atten;
1560}
1561
1562/**
75bcfae9 1563 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1564 *
1565 * Configures power settings for all rates for the current channel,
1566 * using values from channel info struct, and send to NIC
1567 */
dfb39e82 1568static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1569{
14577f23 1570 int rate_idx, i;
d20b3c65 1571 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1572 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1573 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1574 };
1575
8318d78a 1576 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1577 ch_info = iwl_get_channel_info(priv,
8318d78a 1578 priv->band,
8ccde88a 1579 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1580 if (!ch_info) {
15b1687c
WT		 1581 IWL_ERR(priv,
1582 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1583 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1584 return -EINVAL;
1585 }
1586
1587 if (!is_channel_valid(ch_info)) {
e1623446 1588 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1589 "non-Tx channel.\n");
1590 return 0;
1591 }
1592
1593 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1594 /* Fill OFDM rate */
1595 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1596 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1597
1598 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1599 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1600
e1623446 1601 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1602 le16_to_cpu(txpower.channel),
1603 txpower.band,
14577f23
MA		 1604 txpower.power[i].tpc.tx_gain,
1605 txpower.power[i].tpc.dsp_atten,
1606 txpower.power[i].rate);
1607 }
1608 /* Fill CCK rates */
1609 for (rate_idx = IWL_FIRST_CCK_RATE;
1610 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1611 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1612 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1613
e1623446 1614 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1615 le16_to_cpu(txpower.channel),
1616 txpower.band,
1617 txpower.power[i].tpc.tx_gain,
1618 txpower.power[i].tpc.dsp_atten,
1619 txpower.power[i].rate);
b481de9c
ZY		 1620 }
1621
518099a8
SO		 1622 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1623 sizeof(struct iwl3945_txpowertable_cmd),
1624 &txpower);
b481de9c
ZY		 1625
1626}
1627
1628/**
bb8c093b 1629 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1630 * @ch_info: Channel to update. Uses power_info.requested_power.
1631 *
1632 * Replace requested_power and base_power_index ch_info fields for
1633 * one channel.
1634 *
1635 * Called if user or spectrum management changes power preferences.
1636 * Takes into account h/w and modulation limitations (clip power).
1637 *
1638 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1639 *
1640 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1641 * properly fill out the scan powers, and actual h/w gain settings,
1642 * and send changes to NIC
1643 */
4a8a4322 1644static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1645 struct iwl_channel_info *ch_info)
b481de9c 1646{
bb8c093b 1647 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1648 int power_changed = 0;
1649 int i;
1650 const s8 *clip_pwrs;
1651 int power;
1652
1653 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1654 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1655
1656 /* Get this channel's rate-to-current-power settings table */
1657 power_info = ch_info->power_info;
1658
1659 /* update OFDM Txpower settings */
14577f23 1660 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1661 i++, ++power_info) {
1662 int delta_idx;
1663
1664 /* limit new power to be no more than h/w capability */
1665 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1666 if (power == power_info->requested_power)
1667 continue;
1668
1669 /* find difference between old and new requested powers,
1670 * update base (non-temp-compensated) power index */
1671 delta_idx = (power - power_info->requested_power) * 2;
1672 power_info->base_power_index -= delta_idx;
1673
1674 /* save new requested power value */
1675 power_info->requested_power = power;
1676
1677 power_changed = 1;
1678 }
1679
1680 /* update CCK Txpower settings, based on OFDM 12M setting ...
1681 * ... all CCK power settings for a given channel are the *same*. */
1682 if (power_changed) {
1683 power =
14577f23 1684 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1685 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1686
bb8c093b 1687 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1688 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1689 power_info->requested_power = power;
1690 power_info->base_power_index =
14577f23 1691 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1692 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1693 ++power_info;
1694 }
1695 }
1696
1697 return 0;
1698}
1699
1700/**
bb8c093b 1701 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1702 *
1703 * NOTE: Returned power limit may be less (but not more) than requested,
1704 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1705 * (no consideration for h/w clipping limitations).
1706 */
d20b3c65 1707static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1708{
1709 s8 max_power;
1710
1711#if 0
1712 /* if we're using TGd limits, use lower of TGd or EEPROM */
1713 if (ch_info->tgd_data.max_power != 0)
1714 max_power = min(ch_info->tgd_data.max_power,
1715 ch_info->eeprom.max_power_avg);
1716
1717 /* else just use EEPROM limits */
1718 else
1719#endif
1720 max_power = ch_info->eeprom.max_power_avg;
1721
1722 return min(max_power, ch_info->max_power_avg);
1723}
1724
1725/**
bb8c093b 1726 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1727 *
1728 * Compensate txpower settings of *all* channels for temperature.
1729 * This only accounts for the difference between current temperature
1730 * and the factory calibration temperatures, and bases the new settings
1731 * on the channel's base_power_index.
1732 *
1733 * If RxOn is "associated", this sends the new Txpower to NIC!
1734 */
4a8a4322 1735static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1736{
d20b3c65 1737 struct iwl_channel_info *ch_info = NULL;
e6148917 1738 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1739 int delta_index;
1740 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1741 u8 a_band;
1742 u8 rate_index;
1743 u8 scan_tbl_index;
1744 u8 i;
1745 int ref_temp;
1746 int temperature = priv->temperature;
1747
1748 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1749 for (i = 0; i < priv->channel_count; i++) {
1750 ch_info = &priv->channel_info[i];
1751 a_band = is_channel_a_band(ch_info);
1752
1753 /* Get this chnlgrp's factory calibration temperature */
e6148917 1754 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1755 temperature;
1756
a96a27f9 1757 /* get power index adjustment based on current and factory
b481de9c 1758 * temps */
bb8c093b 1759 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1760 ref_temp);
1761
1762 /* set tx power value for all rates, OFDM and CCK */
1763 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1764 rate_index++) {
1765 int power_idx =
1766 ch_info->power_info[rate_index].base_power_index;
1767
1768 /* temperature compensate */
1769 power_idx += delta_index;
1770
1771 /* stay within table range */
bb8c093b 1772 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1773 ch_info->power_info[rate_index].
1774 power_table_index = (u8) power_idx;
1775 ch_info->power_info[rate_index].tpc =
1776 power_gain_table[a_band][power_idx];
1777 }
1778
1779 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1780 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1781
1782 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1783 for (scan_tbl_index = 0;
1784 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1785 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1786 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1787 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1788 actual_index, clip_pwrs,
1789 ch_info, a_band);
1790 }
1791 }
1792
1793 /* send Txpower command for current channel to ucode */
75bcfae9 1794 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1795}
1796
4a8a4322 1797int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1798{
d20b3c65 1799 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1800 s8 max_power;
1801 u8 a_band;
1802 u8 i;
1803
62ea9c5b 1804 if (priv->tx_power_user_lmt == power) {
e1623446 1805 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1806 "limit: %ddBm.\n", power);
1807 return 0;
1808 }
1809
e1623446 1810 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1811 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1812
1813 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1814
1815 for (i = 0; i < priv->channel_count; i++) {
1816 ch_info = &priv->channel_info[i];
1817 a_band = is_channel_a_band(ch_info);
1818
1819 /* find minimum power of all user and regulatory constraints
1820 * (does not consider h/w clipping limitations) */
bb8c093b 1821 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1822 max_power = min(power, max_power);
1823 if (max_power != ch_info->curr_txpow) {
1824 ch_info->curr_txpow = max_power;
1825
1826 /* this considers the h/w clipping limitations */
bb8c093b 1827 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1828 }
1829 }
1830
1831 /* update txpower settings for all channels,
1832 * send to NIC if associated. */
1833 is_temp_calib_needed(priv);
bb8c093b 1834 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1835
1836 return 0;
1837}
1838
5bbe233b
AK		 1839static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1840{
1841 int rc = 0;
2f301227 1842 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1843 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1844 struct iwl_host_cmd cmd = {
1845 .id = REPLY_RXON_ASSOC,
1846 .len = sizeof(rxon_assoc),
c2acea8e 1847 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1848 .data = &rxon_assoc,
1849 };
1850 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1851 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1852
1853 if ((rxon1->flags == rxon2->flags) &&
1854 (rxon1->filter_flags == rxon2->filter_flags) &&
1855 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1856 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1857 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1858 return 0;
1859 }
1860
1861 rxon_assoc.flags = priv->staging_rxon.flags;
1862 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1863 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1864 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1865 rxon_assoc.reserved = 0;
1866
1867 rc = iwl_send_cmd_sync(priv, &cmd);
1868 if (rc)
1869 return rc;
1870
2f301227
ZY		 1871 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1872 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1873 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1874 rc = -EIO;
1875 }
1876
2f301227
ZY		 1877 priv->alloc_rxb_page--;
1878 free_pages(cmd.reply_page, priv->hw_params.rx_page_order);
5bbe233b
AK		 1879
1880 return rc;
1881}
1882
e0158e61
AK		 1883/**
1884 * iwl3945_commit_rxon - commit staging_rxon to hardware
1885 *
1886 * The RXON command in staging_rxon is committed to the hardware and
1887 * the active_rxon structure is updated with the new data. This
1888 * function correctly transitions out of the RXON_ASSOC_MSK state if
1889 * a HW tune is required based on the RXON structure changes.
1890 */
1891static int iwl3945_commit_rxon(struct iwl_priv *priv)
1892{
1893 /* cast away the const for active_rxon in this function */
1894 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1895 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1896 int rc = 0;
1897 bool new_assoc =
1898 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1899
1900 if (!iwl_is_alive(priv))
1901 return -1;
1902
1903 /* always get timestamp with Rx frame */
1904 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1905
1906 /* select antenna */
1907 staging_rxon->flags &=
1908 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1909 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1910
1911 rc = iwl_check_rxon_cmd(priv);
1912 if (rc) {
1913 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1914 return -EINVAL;
1915 }
1916
1917 /* If we don't need to send a full RXON, we can use
1918 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1919 * and other flags for the current radio configuration. */
1920 if (!iwl_full_rxon_required(priv)) {
1921 rc = iwl_send_rxon_assoc(priv);
1922 if (rc) {
1923 IWL_ERR(priv, "Error setting RXON_ASSOC "
1924 "configuration (%d).\n", rc);
1925 return rc;
1926 }
1927
1928 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1929
1930 return 0;
1931 }
1932
1933 /* If we are currently associated and the new config requires
1934 * an RXON_ASSOC and the new config wants the associated mask enabled,
1935 * we must clear the associated from the active configuration
1936 * before we apply the new config */
1937 if (iwl_is_associated(priv) && new_assoc) {
1938 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1939 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1940
1941 /*
1942 * reserved4 and 5 could have been filled by the iwlcore code.
1943 * Let's clear them before pushing to the 3945.
1944 */
1945 active_rxon->reserved4 = 0;
1946 active_rxon->reserved5 = 0;
1947 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1948 sizeof(struct iwl3945_rxon_cmd),
1949 &priv->active_rxon);
1950
1951 /* If the mask clearing failed then we set
1952 * active_rxon back to what it was previously */
1953 if (rc) {
1954 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1955 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1956 "configuration (%d).\n", rc);
1957 return rc;
1958 }
1959 }
1960
1961 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1962 "* with%s RXON_FILTER_ASSOC_MSK\n"
1963 "* channel = %d\n"
1964 "* bssid = %pM\n",
1965 (new_assoc ? "" : "out"),
1966 le16_to_cpu(staging_rxon->channel),
1967 staging_rxon->bssid_addr);
1968
1969 /*
1970 * reserved4 and 5 could have been filled by the iwlcore code.
1971 * Let's clear them before pushing to the 3945.
1972 */
1973 staging_rxon->reserved4 = 0;
1974 staging_rxon->reserved5 = 0;
1975
90e8e424 1976 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1977
1978 /* Apply the new configuration */
1979 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1980 sizeof(struct iwl3945_rxon_cmd),
1981 staging_rxon);
1982 if (rc) {
1983 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1984 return rc;
1985 }
1986
1987 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1988
c587de0b 1989 iwl_clear_stations_table(priv);
e0158e61
AK		 1990
1991 /* If we issue a new RXON command which required a tune then we must
1992 * send a new TXPOWER command or we won't be able to Tx any frames */
1993 rc = priv->cfg->ops->lib->send_tx_power(priv);
1994 if (rc) {
1995 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1996 return rc;
1997 }
1998
1999 /* Add the broadcast address so we can send broadcast frames */
c587de0b 2000 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
e0158e61
AK		 2001 IWL_INVALID_STATION) {
2002 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
2003 return -EIO;
2004 }
2005
2006 /* If we have set the ASSOC_MSK and we are in BSS mode then
2007 * add the IWL_AP_ID to the station rate table */
2008 if (iwl_is_associated(priv) &&
2009 (priv->iw_mode == NL80211_IFTYPE_STATION))
c587de0b
TW		 2010 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
2011 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
e0158e61
AK		 2012 IWL_ERR(priv, "Error adding AP address for transmit\n");
2013 return -EIO;
2014 }
2015
2016 /* Init the hardware's rate fallback order based on the band */
2017 rc = iwl3945_init_hw_rate_table(priv);
2018 if (rc) {
2019 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
2020 return -EIO;
2021 }
2022
2023 return 0;
2024}
2025
b481de9c 2026/* will add 3945 channel switch cmd handling later */
4a8a4322 2027int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2028{
2029 return 0;
2030}
2031
2032/**
2033 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
2034 *
2035 * -- reset periodic timer
2036 * -- see if temp has changed enough to warrant re-calibration ... if so:
2037 * -- correct coeffs for temp (can reset temp timer)
2038 * -- save this temp as "last",
2039 * -- send new set of gain settings to NIC
2040 * NOTE: This should continue working, even when we're not associated,
2041 * so we can keep our internal table of scan powers current. */
4a8a4322 2042void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 2043{
2044 /* This will kick in the "brute force"
bb8c093b 2045 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2046 if (!is_temp_calib_needed(priv))
2047 goto reschedule;
2048
2049 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2050 * This is based *only* on current temperature,
2051 * ignoring any previous power measurements */
bb8c093b 2052 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2053
2054 reschedule:
2055 queue_delayed_work(priv->workqueue,
2056 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2057}
2058
416e1438 2059static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2060{
4a8a4322 2061 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2062 thermal_periodic.work);
2063
2064 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2065 return;
2066
2067 mutex_lock(&priv->mutex);
2068 iwl3945_reg_txpower_periodic(priv);
2069 mutex_unlock(&priv->mutex);
2070}
2071
2072/**
bb8c093b 2073 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2074 * for the channel.
2075 *
2076 * This function is used when initializing channel-info structs.
2077 *
2078 * NOTE: These channel groups do *NOT* match the bands above!
2079 * These channel groups are based on factory-tested channels;
2080 * on A-band, EEPROM's "group frequency" entries represent the top
2081 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2082 */
4a8a4322 2083static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2084 const struct iwl_channel_info *ch_info)
b481de9c 2085{
e6148917
SO		 2086 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2087 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2088 u8 group;
2089 u16 group_index = 0; /* based on factory calib frequencies */
2090 u8 grp_channel;
2091
2092 /* Find the group index for the channel ... don't use index 1(?) */
2093 if (is_channel_a_band(ch_info)) {
2094 for (group = 1; group < 5; group++) {
2095 grp_channel = ch_grp[group].group_channel;
2096 if (ch_info->channel <= grp_channel) {
2097 group_index = group;
2098 break;
2099 }
2100 }
2101 /* group 4 has a few channels *above* its factory cal freq */
2102 if (group == 5)
2103 group_index = 4;
2104 } else
2105 group_index = 0; /* 2.4 GHz, group 0 */
2106
e1623446 2107 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2108 group_index);
2109 return group_index;
2110}
2111
2112/**
bb8c093b 2113 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2114 *
2115 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2116 * into radio/DSP gain settings table for requested power.
2117 */
4a8a4322 2118static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2119 s8 requested_power,
2120 s32 setting_index, s32 *new_index)
2121{
bb8c093b 2122 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2123 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2124 s32 index0, index1;
2125 s32 power = 2 * requested_power;
2126 s32 i;
bb8c093b 2127 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2128 s32 gains0, gains1;
2129 s32 res;
2130 s32 denominator;
2131
e6148917 2132 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2133 samples = chnl_grp->samples;
2134 for (i = 0; i < 5; i++) {
2135 if (power == samples[i].power) {
2136 *new_index = samples[i].gain_index;
2137 return 0;
2138 }
2139 }
2140
2141 if (power > samples[1].power) {
2142 index0 = 0;
2143 index1 = 1;
2144 } else if (power > samples[2].power) {
2145 index0 = 1;
2146 index1 = 2;
2147 } else if (power > samples[3].power) {
2148 index0 = 2;
2149 index1 = 3;
2150 } else {
2151 index0 = 3;
2152 index1 = 4;
2153 }
2154
2155 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2156 if (denominator == 0)
2157 return -EINVAL;
2158 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2159 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2160 res = gains0 + (gains1 - gains0) *
2161 ((s32) power - (s32) samples[index0].power) / denominator +
2162 (1 << 18);
2163 *new_index = res >> 19;
2164 return 0;
2165}
2166
4a8a4322 2167static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2168{
2169 u32 i;
2170 s32 rate_index;
e6148917 2171 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2172 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2173
e1623446 2174 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2175
2176 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2177 s8 *clip_pwrs; /* table of power levels for each rate */
2178 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2179 group = &eeprom->groups[i];
b481de9c
ZY		 2180
2181 /* sanity check on factory saturation power value */
2182 if (group->saturation_power < 40) {
39aadf8c 2183 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2184 "less than minimum expected 40\n",
2185 group->saturation_power);
2186 return;
2187 }
2188
2189 /*
2190 * Derive requested power levels for each rate, based on
2191 * hardware capabilities (saturation power for band).
2192 * Basic value is 3dB down from saturation, with further
2193 * power reductions for highest 3 data rates. These
2194 * backoffs provide headroom for high rate modulation
2195 * power peaks, without too much distortion (clipping).
2196 */
2197 /* we'll fill in this array with h/w max power levels */
f2c7e521 2198 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2199
2200 /* divide factory saturation power by 2 to find -3dB level */
2201 satur_pwr = (s8) (group->saturation_power >> 1);
2202
2203 /* fill in channel group's nominal powers for each rate */
2204 for (rate_index = 0;
2205 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2206 switch (rate_index) {
14577f23 2207 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2208 if (i == 0) /* B/G */
2209 *clip_pwrs = satur_pwr;
2210 else /* A */
2211 *clip_pwrs = satur_pwr - 5;
2212 break;
14577f23 2213 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2214 if (i == 0)
2215 *clip_pwrs = satur_pwr - 7;
2216 else
2217 *clip_pwrs = satur_pwr - 10;
2218 break;
14577f23 2219 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2220 if (i == 0)
2221 *clip_pwrs = satur_pwr - 9;
2222 else
2223 *clip_pwrs = satur_pwr - 12;
2224 break;
2225 default:
2226 *clip_pwrs = satur_pwr;
2227 break;
2228 }
2229 }
2230 }
2231}
2232
2233/**
2234 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2235 *
2236 * Second pass (during init) to set up priv->channel_info
2237 *
2238 * Set up Tx-power settings in our channel info database for each VALID
2239 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2240 * and current temperature.
2241 *
2242 * Since this is based on current temperature (at init time), these values may
2243 * not be valid for very long, but it gives us a starting/default point,
2244 * and allows us to active (i.e. using Tx) scan.
2245 *
2246 * This does *not* write values to NIC, just sets up our internal table.
2247 */
4a8a4322 2248int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2249{
d20b3c65 2250 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2251 struct iwl3945_channel_power_info *pwr_info;
e6148917 2252 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2253 int delta_index;
2254 u8 rate_index;
2255 u8 scan_tbl_index;
2256 const s8 *clip_pwrs; /* array of power levels for each rate */
2257 u8 gain, dsp_atten;
2258 s8 power;
2259 u8 pwr_index, base_pwr_index, a_band;
2260 u8 i;
2261 int temperature;
2262
2263 /* save temperature reference,
2264 * so we can determine next time to calibrate */
bb8c093b 2265 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2266 priv->last_temperature = temperature;
2267
bb8c093b 2268 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2269
2270 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2271 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2272 i++, ch_info++) {
2273 a_band = is_channel_a_band(ch_info);
2274 if (!is_channel_valid(ch_info))
2275 continue;
2276
2277 /* find this channel's channel group (*not* "band") index */
2278 ch_info->group_index =
bb8c093b 2279 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2280
2281 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2282 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2283
2284 /* calculate power index *adjustment* value according to
2285 * diff between current temperature and factory temperature */
bb8c093b 2286 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2287 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2288 temperature);
2289
e1623446 2290 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2291 ch_info->channel, delta_index, temperature +
2292 IWL_TEMP_CONVERT);
2293
2294 /* set tx power value for all OFDM rates */
2295 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2296 rate_index++) {
25a4ccea 2297 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2298 int rc;
2299
2300 /* use channel group's clip-power table,
2301 * but don't exceed channel's max power */
2302 s8 pwr = min(ch_info->max_power_avg,
2303 clip_pwrs[rate_index]);
2304
2305 pwr_info = &ch_info->power_info[rate_index];
2306
2307 /* get base (i.e. at factory-measured temperature)
2308 * power table index for this rate's power */
bb8c093b 2309 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2310 ch_info->group_index,
2311 &power_idx);
2312 if (rc) {
15b1687c 2313 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2314 return rc;
2315 }
2316 pwr_info->base_power_index = (u8) power_idx;
2317
2318 /* temperature compensate */
2319 power_idx += delta_index;
2320
2321 /* stay within range of gain table */
bb8c093b 2322 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2323
bb8c093b 2324 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2325 pwr_info->requested_power = pwr;
2326 pwr_info->power_table_index = (u8) power_idx;
2327 pwr_info->tpc.tx_gain =
2328 power_gain_table[a_band][power_idx].tx_gain;
2329 pwr_info->tpc.dsp_atten =
2330 power_gain_table[a_band][power_idx].dsp_atten;
2331 }
2332
2333 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2334 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2335 power = pwr_info->requested_power +
2336 IWL_CCK_FROM_OFDM_POWER_DIFF;
2337 pwr_index = pwr_info->power_table_index +
2338 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2339 base_pwr_index = pwr_info->base_power_index +
2340 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2341
2342 /* stay within table range */
bb8c093b 2343 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2344 gain = power_gain_table[a_band][pwr_index].tx_gain;
2345 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2346
bb8c093b 2347 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2348 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2349 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2350 for (rate_index = 0;
2351 rate_index < IWL_CCK_RATES; rate_index++) {
2352 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2353 pwr_info->requested_power = power;
2354 pwr_info->power_table_index = pwr_index;
2355 pwr_info->base_power_index = base_pwr_index;
2356 pwr_info->tpc.tx_gain = gain;
2357 pwr_info->tpc.dsp_atten = dsp_atten;
2358 }
2359
2360 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2361 for (scan_tbl_index = 0;
2362 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2363 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2364 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2365 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2366 actual_index, clip_pwrs, ch_info, a_band);
2367 }
2368 }
2369
2370 return 0;
2371}
2372
4a8a4322 2373int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2374{
2375 int rc;
b481de9c 2376
5d49f498
AK		 2377 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2378 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2379 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2380 if (rc < 0)
15b1687c 2381 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2382
b481de9c
ZY		 2383 return 0;
2384}
2385
188cf6c7 2386int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2387{
b481de9c
ZY		 2388 int txq_id = txq->q.id;
2389
3832ec9d 2390 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2391
2392 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2393
5d49f498
AK		 2394 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2395 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2396
5d49f498 2397 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2398 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2399 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2400 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2401 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2402 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2403
2404 /* fake read to flush all prev. writes */
5d49f498 2405 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2406
2407 return 0;
2408}
2409
42427b4e
KA		 2410/*
2411 * HCMD utils
2412 */
2413static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2414{
2415 switch (cmd_id) {
2416 case REPLY_RXON:
d25aabb0
WT		 2417 return sizeof(struct iwl3945_rxon_cmd);
2418 case POWER_TABLE_CMD:
2419 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2420 default:
2421 return len;
2422 }
2423}
2424
c587de0b 2425
17f841cd
SO		 2426static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2427{
c587de0b
TW		 2428 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2429 addsta->mode = cmd->mode;
2430 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2431 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2432 addsta->station_flags = cmd->station_flags;
2433 addsta->station_flags_msk = cmd->station_flags_msk;
2434 addsta->tid_disable_tx = cpu_to_le16(0);
2435 addsta->rate_n_flags = cmd->rate_n_flags;
2436 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2437 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2438 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2439
2440 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2441}
2442
c587de0b 2443
b481de9c
ZY		 2444/**
2445 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2446 */
4a8a4322 2447int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2448{
14577f23 2449 int rc, i, index, prev_index;
bb8c093b 2450 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2451 .reserved = {0, 0, 0},
2452 };
bb8c093b 2453 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2454
bb8c093b
CH		 2455 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2456 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2457
2458 table[index].rate_n_flags =
bb8c093b 2459 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2460 table[index].try_cnt = priv->retry_rate;
bb8c093b 2461 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2462 table[index].next_rate_index =
2463 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2464 }
2465
8318d78a
JB		 2466 switch (priv->band) {
2467 case IEEE80211_BAND_5GHZ:
e1623446 2468 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2469 /* If one of the following CCK rates is used,
2470 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2471 for (i = IWL_RATE_1M_INDEX_TABLE;
2472 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2473 table[i].next_rate_index =
2474 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2475
2476 /* Don't fall back to CCK rates */
7262796a
AM		 2477 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2478 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2479
2480 /* Don't drop out of OFDM rates */
14577f23 2481 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2482 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2483 break;
2484
8318d78a 2485 case IEEE80211_BAND_2GHZ:
e1623446 2486 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2487 /* If an OFDM rate is used, have it fall back to the
2488 * 1M CCK rates */
b481de9c 2489
7262796a 2490 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2491 iwl_is_associated(priv)) {
7262796a
AM		 2492
2493 index = IWL_FIRST_CCK_RATE;
2494 for (i = IWL_RATE_6M_INDEX_TABLE;
2495 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2496 table[i].next_rate_index =
2497 iwl3945_rates[index].table_rs_index;
2498
2499 index = IWL_RATE_11M_INDEX_TABLE;
2500 /* CCK shouldn't fall back to OFDM... */
2501 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2502 }
b481de9c
ZY		 2503 break;
2504
2505 default:
8318d78a 2506 WARN_ON(1);
b481de9c
ZY		 2507 break;
2508 }
2509
2510 /* Update the rate scaling for control frame Tx */
2511 rate_cmd.table_id = 0;
518099a8 2512 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2513 &rate_cmd);
2514 if (rc)
2515 return rc;
2516
2517 /* Update the rate scaling for data frame Tx */
2518 rate_cmd.table_id = 1;
518099a8 2519 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2520 &rate_cmd);
2521}
2522
796083cb 2523/* Called when initializing driver */
4a8a4322 2524int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2525{
3832ec9d
AK		 2526 memset((void *)&priv->hw_params, 0,
2527 sizeof(struct iwl_hw_params));
b481de9c 2528
3832ec9d 2529 priv->shared_virt =
b481de9c 2530 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2531 sizeof(struct iwl3945_shared),
3832ec9d 2532 &priv->shared_phys);
b481de9c 2533
3832ec9d 2534 if (!priv->shared_virt) {
15b1687c 2535 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2536 mutex_unlock(&priv->mutex);
2537 return -ENOMEM;
2538 }
2539
21c02a1a 2540 /* Assign number of Usable TX queues */
88804e2b 2541 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2542
a8e74e27 2543 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2544 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2545 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2546 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2547 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2548 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2549
141c43a3 2550 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2551 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2552
b481de9c
ZY		 2553 return 0;
2554}
2555
4a8a4322 2556unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2557 struct iwl3945_frame *frame, u8 rate)
b481de9c 2558{
bb8c093b 2559 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2560 unsigned int frame_size;
2561
bb8c093b 2562 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2563 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2564
3832ec9d 2565 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2566 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2567
bb8c093b 2568 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2569 tx_beacon_cmd->frame,
b481de9c
ZY		 2570 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2571
2572 BUG_ON(frame_size > MAX_MPDU_SIZE);
2573 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2574
2575 tx_beacon_cmd->tx.rate = rate;
2576 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2577 TX_CMD_FLG_TSF_MSK);
2578
14577f23
MA		 2579 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2580 tx_beacon_cmd->tx.supp_rates[0] =
2581 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2582
b481de9c 2583 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2584 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2585
3ac7f146 2586 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2587}
2588
4a8a4322 2589void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2590{
91c066f2 2591 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2592 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2593}
2594
4a8a4322 2595void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2596{
2597 INIT_DELAYED_WORK(&priv->thermal_periodic,
2598 iwl3945_bg_reg_txpower_periodic);
2599}
2600
4a8a4322 2601void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2602{
2603 cancel_delayed_work(&priv->thermal_periodic);
2604}
2605
0164b9b4
KA		 2606/* check contents of special bootstrap uCode SRAM */
2607static int iwl3945_verify_bsm(struct iwl_priv *priv)
2608 {
2609 __le32 *image = priv->ucode_boot.v_addr;
2610 u32 len = priv->ucode_boot.len;
2611 u32 reg;
2612 u32 val;
2613
e1623446 2614 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2615
2616 /* verify BSM SRAM contents */
2617 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2618 for (reg = BSM_SRAM_LOWER_BOUND;
2619 reg < BSM_SRAM_LOWER_BOUND + len;
2620 reg += sizeof(u32), image++) {
2621 val = iwl_read_prph(priv, reg);
2622 if (val != le32_to_cpu(*image)) {
2623 IWL_ERR(priv, "BSM uCode verification failed at "
2624 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2625 BSM_SRAM_LOWER_BOUND,
2626 reg - BSM_SRAM_LOWER_BOUND, len,
2627 val, le32_to_cpu(*image));
2628 return -EIO;
2629 }
2630 }
2631
e1623446 2632 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2633
2634 return 0;
2635}
2636
e6148917
SO		 2637
2638/******************************************************************************
2639 *
2640 * EEPROM related functions
2641 *
2642 ******************************************************************************/
2643
2644/*
2645 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2646 * embedded controller) as EEPROM reader; each read is a series of pulses
2647 * to/from the EEPROM chip, not a single event, so even reads could conflict
2648 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2649 * simply claims ownership, which should be safe when this function is called
2650 * (i.e. before loading uCode!).
2651 */
2652static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2653{
2654 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2655 return 0;
2656}
2657
2658
2659static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2660{
2661 return;
2662}
2663
0164b9b4
KA		 2664 /**
2665 * iwl3945_load_bsm - Load bootstrap instructions
2666 *
2667 * BSM operation:
2668 *
2669 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2670 * in special SRAM that does not power down during RFKILL. When powering back
2671 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2672 * the bootstrap program into the on-board processor, and starts it.
2673 *
2674 * The bootstrap program loads (via DMA) instructions and data for a new
2675 * program from host DRAM locations indicated by the host driver in the
2676 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2677 * automatically.
2678 *
2679 * When initializing the NIC, the host driver points the BSM to the
2680 * "initialize" uCode image. This uCode sets up some internal data, then
2681 * notifies host via "initialize alive" that it is complete.
2682 *
2683 * The host then replaces the BSM_DRAM_* pointer values to point to the
2684 * normal runtime uCode instructions and a backup uCode data cache buffer
2685 * (filled initially with starting data values for the on-board processor),
2686 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2687 * which begins normal operation.
2688 *
2689 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2690 * the backup data cache in DRAM before SRAM is powered down.
2691 *
2692 * When powering back up, the BSM loads the bootstrap program. This reloads
2693 * the runtime uCode instructions and the backup data cache into SRAM,
2694 * and re-launches the runtime uCode from where it left off.
2695 */
2696static int iwl3945_load_bsm(struct iwl_priv *priv)
2697{
2698 __le32 *image = priv->ucode_boot.v_addr;
2699 u32 len = priv->ucode_boot.len;
2700 dma_addr_t pinst;
2701 dma_addr_t pdata;
2702 u32 inst_len;
2703 u32 data_len;
2704 int rc;
2705 int i;
2706 u32 done;
2707 u32 reg_offset;
2708
e1623446 2709 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2710
2711 /* make sure bootstrap program is no larger than BSM's SRAM size */
2712 if (len > IWL39_MAX_BSM_SIZE)
2713 return -EINVAL;
2714
2715 /* Tell bootstrap uCode where to find the "Initialize" uCode
2716 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2717 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2718 * after the "initialize" uCode has run, to point to
2719 * runtime/protocol instructions and backup data cache. */
2720 pinst = priv->ucode_init.p_addr;
2721 pdata = priv->ucode_init_data.p_addr;
2722 inst_len = priv->ucode_init.len;
2723 data_len = priv->ucode_init_data.len;
2724
0164b9b4
KA		 2725 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2726 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2727 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2728 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2729
2730 /* Fill BSM memory with bootstrap instructions */
2731 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2732 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2733 reg_offset += sizeof(u32), image++)
2734 _iwl_write_prph(priv, reg_offset,
2735 le32_to_cpu(*image));
2736
2737 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2738 if (rc)
0164b9b4 2739 return rc;
0164b9b4
KA		 2740
2741 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2742 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2743 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2744 IWL39_RTC_INST_LOWER_BOUND);
2745 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2746
2747 /* Load bootstrap code into instruction SRAM now,
2748 * to prepare to load "initialize" uCode */
2749 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2750 BSM_WR_CTRL_REG_BIT_START);
2751
2752 /* Wait for load of bootstrap uCode to finish */
2753 for (i = 0; i < 100; i++) {
2754 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2755 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2756 break;
2757 udelay(10);
2758 }
2759 if (i < 100)
e1623446 2760 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2761 else {
2762 IWL_ERR(priv, "BSM write did not complete!\n");
2763 return -EIO;
2764 }
2765
2766 /* Enable future boot loads whenever power management unit triggers it
2767 * (e.g. when powering back up after power-save shutdown) */
2768 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2769 BSM_WR_CTRL_REG_BIT_START_EN);
2770
0164b9b4
KA		 2771 return 0;
2772}
2773
cc0f555d
JS		 2774#define IWL3945_UCODE_GET(item) \
2775static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2776 u32 api_ver) \
2777{ \
2778 return le32_to_cpu(ucode->u.v1.item); \
2779}
2780
2781static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2782{
2783 return UCODE_HEADER_SIZE(1);
2784}
2785static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2786 u32 api_ver)
2787{
2788 return 0;
2789}
2790static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2791 u32 api_ver)
2792{
2793 return (u8 *) ucode->u.v1.data;
2794}
2795
2796IWL3945_UCODE_GET(inst_size);
2797IWL3945_UCODE_GET(data_size);
2798IWL3945_UCODE_GET(init_size);
2799IWL3945_UCODE_GET(init_data_size);
2800IWL3945_UCODE_GET(boot_size);
2801
5bbe233b
AK		 2802static struct iwl_hcmd_ops iwl3945_hcmd = {
2803 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2804 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2805};
2806
cc0f555d
JS		 2807static struct iwl_ucode_ops iwl3945_ucode = {
2808 .get_header_size = iwl3945_ucode_get_header_size,
2809 .get_build = iwl3945_ucode_get_build,
2810 .get_inst_size = iwl3945_ucode_get_inst_size,
2811 .get_data_size = iwl3945_ucode_get_data_size,
2812 .get_init_size = iwl3945_ucode_get_init_size,
2813 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2814 .get_boot_size = iwl3945_ucode_get_boot_size,
2815 .get_data = iwl3945_ucode_get_data,
2816};
2817
0164b9b4 2818static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2819 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2820 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2821 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2822 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2823 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2824 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2825 .apm_ops = {
2826 .init = iwl3945_apm_init,
d68b603c 2827 .stop = iwl_apm_stop,
01ec616d 2828 .config = iwl3945_nic_config,
854682ed 2829 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2830 },
e6148917
SO		 2831 .eeprom_ops = {
2832 .regulatory_bands = {
2833 EEPROM_REGULATORY_BAND_1_CHANNELS,
2834 EEPROM_REGULATORY_BAND_2_CHANNELS,
2835 EEPROM_REGULATORY_BAND_3_CHANNELS,
2836 EEPROM_REGULATORY_BAND_4_CHANNELS,
2837 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2838 EEPROM_REGULATORY_BAND_NO_HT40,
2839 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2840 },
2841 .verify_signature = iwlcore_eeprom_verify_signature,
2842 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2843 .release_semaphore = iwl3945_eeprom_release_semaphore,
2844 .query_addr = iwlcore_eeprom_query_addr,
2845 },
75bcfae9 2846 .send_tx_power = iwl3945_send_tx_power,
c2436980 2847 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2848 .post_associate = iwl3945_post_associate,
ef850d7c 2849 .isr = iwl_isr_legacy,
60690a6a 2850 .config_ap = iwl3945_config_ap,
0164b9b4
KA		 2851};
2852
42427b4e
KA		 2853static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2854 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2855 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2856 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
42427b4e
KA		 2857};
2858
0164b9b4 2859static struct iwl_ops iwl3945_ops = {
cc0f555d 2860 .ucode = &iwl3945_ucode,
0164b9b4 2861 .lib = &iwl3945_lib,
5bbe233b 2862 .hcmd = &iwl3945_hcmd,
42427b4e 2863 .utils = &iwl3945_hcmd_utils,
e932a609 2864 .led = &iwl3945_led_ops,
0164b9b4
KA		 2865};
2866
c0f20d91 2867static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2868 .name = "3945BG",
a0987a8d
RC		 2869 .fw_name_pre = IWL3945_FW_PRE,
2870 .ucode_api_max = IWL3945_UCODE_API_MAX,
2871 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2872 .sku = IWL_SKU_G,
e6148917
SO		 2873 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2874 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2875 .ops = &iwl3945_ops,
88804e2b 2876 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2877 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2878 .use_isr_legacy = true,
2879 .ht_greenfield_support = false,
f2d0d0e2 2880 .led_compensation = 64,
82b9a121
TW		 2881};
2882
c0f20d91 2883static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2884 .name = "3945ABG",
a0987a8d
RC		 2885 .fw_name_pre = IWL3945_FW_PRE,
2886 .ucode_api_max = IWL3945_UCODE_API_MAX,
2887 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2888 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2889 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2890 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2891 .ops = &iwl3945_ops,
88804e2b 2892 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2893 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2894 .use_isr_legacy = true,
2895 .ht_greenfield_support = false,
f2d0d0e2 2896 .led_compensation = 64,
82b9a121
TW		 2897};
2898
bb8c093b 2899struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2900 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2901 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2902 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2903 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2904 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2905 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2906 {0}
2907};
2908
bb8c093b 2909MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)