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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
bddadf86 41#include "iwl-3945-fh.h"
600c0e11 42#include "iwl-commands.h"
b481de9c 43#include "iwl-3945.h"
5d08cd1d 44#include "iwl-helpers.h"
5747d47f 45#include "iwl-core.h"
d9829a67 46#include "iwl-agn-rs.h"
b481de9c
ZY		 47
48#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_##r##M_IEEE, \
51 IWL_RATE_##ip##M_INDEX, \
52 IWL_RATE_##in##M_INDEX, \
53 IWL_RATE_##rp##M_INDEX, \
54 IWL_RATE_##rn##M_INDEX, \
55 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 56 IWL_RATE_##np##M_INDEX, \
57 IWL_RATE_##r##M_INDEX_TABLE, \
58 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 59
60/*
61 * Parameter order:
62 * rate, prev rate, next rate, prev tgg rate, next tgg rate
63 *
64 * If there isn't a valid next or previous rate then INV is used which
65 * maps to IWL_RATE_INVALID
66 *
67 */
d9829a67 68const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 69 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
70 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
71 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
72 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 73 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
74 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
75 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
76 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
77 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
78 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
79 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
80 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 81};
82
bb8c093b 83/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 84#define IWL_EVT_DISABLE (0)
85#define IWL_EVT_DISABLE_SIZE (1532/32)
86
87/**
bb8c093b 88 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 89 *
90 * Disable an event by writing "1"s into "disable"
91 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
92 * Default values of 0 enable uCode events to be logged.
93 * Use for only special debugging. This function is just a placeholder as-is,
94 * you'll need to provide the special bits! ...
95 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 96void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 97{
af7cca2a 98 int ret;
b481de9c
ZY		 99 int i;
100 u32 base; /* SRAM address of event log header */
101 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
102 u32 array_size; /* # of u32 entries in array */
103 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
104 0x00000000, /* 31 - 0 Event id numbers */
105 0x00000000, /* 63 - 32 */
106 0x00000000, /* 95 - 64 */
107 0x00000000, /* 127 - 96 */
108 0x00000000, /* 159 - 128 */
109 0x00000000, /* 191 - 160 */
110 0x00000000, /* 223 - 192 */
111 0x00000000, /* 255 - 224 */
112 0x00000000, /* 287 - 256 */
113 0x00000000, /* 319 - 288 */
114 0x00000000, /* 351 - 320 */
115 0x00000000, /* 383 - 352 */
116 0x00000000, /* 415 - 384 */
117 0x00000000, /* 447 - 416 */
118 0x00000000, /* 479 - 448 */
119 0x00000000, /* 511 - 480 */
120 0x00000000, /* 543 - 512 */
121 0x00000000, /* 575 - 544 */
122 0x00000000, /* 607 - 576 */
123 0x00000000, /* 639 - 608 */
124 0x00000000, /* 671 - 640 */
125 0x00000000, /* 703 - 672 */
126 0x00000000, /* 735 - 704 */
127 0x00000000, /* 767 - 736 */
128 0x00000000, /* 799 - 768 */
129 0x00000000, /* 831 - 800 */
130 0x00000000, /* 863 - 832 */
131 0x00000000, /* 895 - 864 */
132 0x00000000, /* 927 - 896 */
133 0x00000000, /* 959 - 928 */
134 0x00000000, /* 991 - 960 */
135 0x00000000, /* 1023 - 992 */
136 0x00000000, /* 1055 - 1024 */
137 0x00000000, /* 1087 - 1056 */
138 0x00000000, /* 1119 - 1088 */
139 0x00000000, /* 1151 - 1120 */
140 0x00000000, /* 1183 - 1152 */
141 0x00000000, /* 1215 - 1184 */
142 0x00000000, /* 1247 - 1216 */
143 0x00000000, /* 1279 - 1248 */
144 0x00000000, /* 1311 - 1280 */
145 0x00000000, /* 1343 - 1312 */
146 0x00000000, /* 1375 - 1344 */
147 0x00000000, /* 1407 - 1376 */
148 0x00000000, /* 1439 - 1408 */
149 0x00000000, /* 1471 - 1440 */
150 0x00000000, /* 1503 - 1472 */
151 };
152
153 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 154 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 155 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 156 return;
157 }
158
5d49f498 159 ret = iwl_grab_nic_access(priv);
af7cca2a 160 if (ret) {
39aadf8c 161 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 162 return;
163 }
164
5d49f498
AK		 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
167 iwl_release_nic_access(priv);
b481de9c
ZY		 168
169 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
170 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
171 disable_ptr);
5d49f498 172 ret = iwl_grab_nic_access(priv);
b481de9c 173 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 174 iwl_write_targ_mem(priv,
af7cca2a
TW		 175 disable_ptr + (i * sizeof(u32)),
176 evt_disable[i]);
b481de9c 177
5d49f498 178 iwl_release_nic_access(priv);
b481de9c
ZY		 179 } else {
180 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
181 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
182 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
183 disable_ptr, array_size);
184 }
185
186}
187
17744ff6
TW		 188static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
189{
190 int idx;
191
192 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
193 if (iwl3945_rates[idx].plcp == plcp)
194 return idx;
195 return -1;
196}
197
b481de9c
ZY		 198/**
199 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
200 * @priv: eeprom and antenna fields are used to determine antenna flags
201 *
f2c7e521 202 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
b481de9c
ZY		 203 * priv->antenna specifies the antenna diversity mode:
204 *
a96a27f9 205 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 206 * IWL_ANTENNA_MAIN - Force MAIN antenna
207 * IWL_ANTENNA_AUX - Force AUX antenna
208 */
4a8a4322 209__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
b481de9c
ZY		 210{
211 switch (priv->antenna) {
212 case IWL_ANTENNA_DIVERSITY:
213 return 0;
214
215 case IWL_ANTENNA_MAIN:
f2c7e521 216 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 217 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
218 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
219
220 case IWL_ANTENNA_AUX:
f2c7e521 221 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 222 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
223 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
224 }
225
226 /* bad antenna selector value */
15b1687c 227 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
b481de9c
ZY		 228 return 0; /* "diversity" is default if error */
229}
230
91c066f2
TW		 231#ifdef CONFIG_IWL3945_DEBUG
232#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
233
234static const char *iwl3945_get_tx_fail_reason(u32 status)
235{
236 switch (status & TX_STATUS_MSK) {
237 case TX_STATUS_SUCCESS:
238 return "SUCCESS";
239 TX_STATUS_ENTRY(SHORT_LIMIT);
240 TX_STATUS_ENTRY(LONG_LIMIT);
241 TX_STATUS_ENTRY(FIFO_UNDERRUN);
242 TX_STATUS_ENTRY(MGMNT_ABORT);
243 TX_STATUS_ENTRY(NEXT_FRAG);
244 TX_STATUS_ENTRY(LIFE_EXPIRE);
245 TX_STATUS_ENTRY(DEST_PS);
246 TX_STATUS_ENTRY(ABORTED);
247 TX_STATUS_ENTRY(BT_RETRY);
248 TX_STATUS_ENTRY(STA_INVALID);
249 TX_STATUS_ENTRY(FRAG_DROPPED);
250 TX_STATUS_ENTRY(TID_DISABLE);
251 TX_STATUS_ENTRY(FRAME_FLUSHED);
252 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
253 TX_STATUS_ENTRY(TX_LOCKED);
254 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
255 }
256
257 return "UNKNOWN";
258}
259#else
260static inline const char *iwl3945_get_tx_fail_reason(u32 status)
261{
262 return "";
263}
264#endif
265
e6a9854b
JB		 266/*
267 * get ieee prev rate from rate scale table.
268 * for A and B mode we need to overright prev
269 * value
270 */
4a8a4322 271int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 272{
273 int next_rate = iwl3945_get_prev_ieee_rate(rate);
274
275 switch (priv->band) {
276 case IEEE80211_BAND_5GHZ:
277 if (rate == IWL_RATE_12M_INDEX)
278 next_rate = IWL_RATE_9M_INDEX;
279 else if (rate == IWL_RATE_6M_INDEX)
280 next_rate = IWL_RATE_6M_INDEX;
281 break;
7262796a
AM		 282 case IEEE80211_BAND_2GHZ:
283 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
284 iwl3945_is_associated(priv)) {
285 if (rate == IWL_RATE_11M_INDEX)
286 next_rate = IWL_RATE_5M_INDEX;
287 }
e6a9854b 288 break;
7262796a 289
e6a9854b
JB		 290 default:
291 break;
292 }
293
294 return next_rate;
295}
296
91c066f2
TW		 297
298/**
299 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
300 *
301 * When FW advances 'R' index, all entries between old and new 'R' index
302 * need to be reclaimed. As result, some free space forms. If there is
303 * enough free space (> low mark), wake the stack that feeds us.
304 */
4a8a4322 305static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 306 int txq_id, int index)
307{
f2c7e521 308 struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
d20b3c65 309 struct iwl_queue *q = &txq->q;
91c066f2
TW		 310 struct iwl3945_tx_info *tx_info;
311
312 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
313
314 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
315 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
316
317 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 318 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2
TW		 319 tx_info->skb[0] = NULL;
320 iwl3945_hw_txq_free_tfd(priv, txq);
321 }
322
d20b3c65 323 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 324 (txq_id != IWL_CMD_QUEUE_NUM) &&
325 priv->mac80211_registered)
326 ieee80211_wake_queue(priv->hw, txq_id);
327}
328
329/**
330 * iwl3945_rx_reply_tx - Handle Tx response
331 */
4a8a4322 332static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 333 struct iwl_rx_mem_buffer *rxb)
91c066f2 334{
3d24a9f7 335 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 336 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
337 int txq_id = SEQ_TO_QUEUE(sequence);
338 int index = SEQ_TO_INDEX(sequence);
f2c7e521 339 struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
e039fa4a 340 struct ieee80211_tx_info *info;
91c066f2
TW		 341 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
342 u32 status = le32_to_cpu(tx_resp->status);
343 int rate_idx;
74221d07 344 int fail;
91c066f2
TW		 345
346 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
15b1687c 347 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 348 "is out of range [0-%d] %d %d\n", txq_id,
349 index, txq->q.n_bd, txq->q.write_ptr,
350 txq->q.read_ptr);
351 return;
352 }
353
e039fa4a 354 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 355 ieee80211_tx_info_clear_status(info);
356
357 /* Fill the MRR chain with some info about on-chip retransmissions */
358 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
359 if (info->band == IEEE80211_BAND_5GHZ)
360 rate_idx -= IWL_FIRST_OFDM_RATE;
361
362 fail = tx_resp->failure_frame;
74221d07
AM		 363
364 info->status.rates[0].idx = rate_idx;
365 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 366
91c066f2 367 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 368 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
369 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 370
371 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
372 txq_id, iwl3945_get_tx_fail_reason(status), status,
373 tx_resp->rate, tx_resp->failure_frame);
374
91c066f2
TW		 375 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
376 iwl3945_tx_queue_reclaim(priv, txq_id, index);
377
378 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 379 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 380}
381
382
383
b481de9c
ZY		 384/*****************************************************************************
385 *
386 * Intel PRO/Wireless 3945ABG/BG Network Connection
387 *
388 * RX handler implementations
389 *
b481de9c
ZY		 390 *****************************************************************************/
391
4a8a4322 392void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 393{
3d24a9f7 394 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 395 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 396 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 397 le32_to_cpu(pkt->len));
398
f2c7e521 399 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 400
ab53d8af
MA		 401 iwl3945_led_background(priv);
402
b481de9c
ZY		 403 priv->last_statistics_time = jiffies;
404}
405
17744ff6
TW		 406/******************************************************************************
407 *
408 * Misc. internal state and helper functions
409 *
410 ******************************************************************************/
411#ifdef CONFIG_IWL3945_DEBUG
412
413/**
414 * iwl3945_report_frame - dump frame to syslog during debug sessions
415 *
416 * You may hack this function to show different aspects of received frames,
417 * including selective frame dumps.
418 * group100 parameter selects whether to show 1 out of 100 good frames.
419 */
4a8a4322 420static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 421 struct iwl_rx_packet *pkt,
17744ff6
TW		 422 struct ieee80211_hdr *header, int group100)
423{
424 u32 to_us;
425 u32 print_summary = 0;
426 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
427 u32 hundred = 0;
428 u32 dataframe = 0;
fd7c8a40 429 __le16 fc;
17744ff6
TW		 430 u16 seq_ctl;
431 u16 channel;
432 u16 phy_flags;
433 u16 length;
434 u16 status;
435 u16 bcn_tmr;
436 u32 tsf_low;
437 u64 tsf;
438 u8 rssi;
439 u8 agc;
440 u16 sig_avg;
441 u16 noise_diff;
442 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
443 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
444 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
445 u8 *data = IWL_RX_DATA(pkt);
446
447 /* MAC header */
fd7c8a40 448 fc = header->frame_control;
17744ff6
TW		 449 seq_ctl = le16_to_cpu(header->seq_ctrl);
450
451 /* metadata */
452 channel = le16_to_cpu(rx_hdr->channel);
453 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
454 length = le16_to_cpu(rx_hdr->len);
455
456 /* end-of-frame status and timestamp */
457 status = le32_to_cpu(rx_end->status);
458 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
459 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
460 tsf = le64_to_cpu(rx_end->timestamp);
461
462 /* signal statistics */
463 rssi = rx_stats->rssi;
464 agc = rx_stats->agc;
465 sig_avg = le16_to_cpu(rx_stats->sig_avg);
466 noise_diff = le16_to_cpu(rx_stats->noise_diff);
467
468 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
469
470 /* if data frame is to us and all is good,
471 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 472 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
473 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 474 dataframe = 1;
475 if (!group100)
476 print_summary = 1; /* print each frame */
477 else if (priv->framecnt_to_us < 100) {
478 priv->framecnt_to_us++;
479 print_summary = 0;
480 } else {
481 priv->framecnt_to_us = 0;
482 print_summary = 1;
483 hundred = 1;
484 }
485 } else {
486 /* print summary for all other frames */
487 print_summary = 1;
488 }
489
490 if (print_summary) {
491 char *title;
0ff1cca0 492 int rate;
17744ff6
TW		 493
494 if (hundred)
495 title = "100Frames";
fd7c8a40 496 else if (ieee80211_has_retry(fc))
17744ff6 497 title = "Retry";
fd7c8a40 498 else if (ieee80211_is_assoc_resp(fc))
17744ff6 499 title = "AscRsp";
fd7c8a40 500 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 501 title = "RasRsp";
fd7c8a40 502 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 503 title = "PrbRsp";
504 print_dump = 1; /* dump frame contents */
505 } else if (ieee80211_is_beacon(fc)) {
506 title = "Beacon";
507 print_dump = 1; /* dump frame contents */
508 } else if (ieee80211_is_atim(fc))
509 title = "ATIM";
510 else if (ieee80211_is_auth(fc))
511 title = "Auth";
512 else if (ieee80211_is_deauth(fc))
513 title = "DeAuth";
514 else if (ieee80211_is_disassoc(fc))
515 title = "DisAssoc";
516 else
517 title = "Frame";
518
519 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
520 if (rate == -1)
521 rate = 0;
522 else
523 rate = iwl3945_rates[rate].ieee / 2;
524
525 /* print frame summary.
526 * MAC addresses show just the last byte (for brevity),
527 * but you can hack it to show more, if you'd like to. */
528 if (dataframe)
529 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 530 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 531 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 532 length, rssi, channel, rate);
533 else {
534 /* src/dst addresses assume managed mode */
535 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
536 "src=0x%02x, rssi=%u, tim=%lu usec, "
537 "phy=0x%02x, chnl=%d\n",
fd7c8a40 538 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 539 header->addr3[5], rssi,
540 tsf_low - priv->scan_start_tsf,
541 phy_flags, channel);
542 }
543 }
544 if (print_dump)
40b8ec0b 545 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6
TW		 546}
547#else
4a8a4322 548static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 549 struct iwl_rx_packet *pkt,
17744ff6
TW		 550 struct ieee80211_hdr *header, int group100)
551{
552}
553#endif
554
4bd9b4f3 555/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 556static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 557 struct ieee80211_hdr *header)
558{
559 /* Filter incoming packets to determine if they are targeted toward
560 * this network, discarding packets coming from ourselves */
561 switch (priv->iw_mode) {
05c914fe 562 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 563 /* packets to our IBSS update information */
564 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 565 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 566 /* packets to our IBSS update information */
567 return !compare_ether_addr(header->addr2, priv->bssid);
568 default:
569 return 1;
570 }
571}
17744ff6 572
4a8a4322 573static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 574 struct iwl_rx_mem_buffer *rxb,
12342c47 575 struct ieee80211_rx_status *stats)
b481de9c 576{
3d24a9f7 577 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
699669f3 578#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 579 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 580#endif
bb8c093b
CH		 581 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
582 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 583 short len = le16_to_cpu(rx_hdr->len);
584
585 /* We received data from the HW, so stop the watchdog */
3d24a9f7 586 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
b481de9c
ZY		 587 IWL_DEBUG_DROP("Corruption detected!\n");
588 return;
589 }
590
591 /* We only process data packets if the interface is open */
592 if (unlikely(!priv->is_open)) {
593 IWL_DEBUG_DROP_LIMIT
594 ("Dropping packet while interface is not open.\n");
595 return;
596 }
b481de9c
ZY		 597
598 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
599 /* Set the size of the skb to the size of the frame */
600 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
601
df878d8f 602 if (iwl3945_mod_params.sw_crypto)
bb8c093b 603 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 604 le32_to_cpu(rx_end->status), stats);
605
ab53d8af 606#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 607 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 608 priv->rxtxpackets += len;
609#endif
b481de9c
ZY		 610 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
611 rxb->skb = NULL;
612}
613
7878a5a4
MA		 614#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
615
4a8a4322 616static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 617 struct iwl_rx_mem_buffer *rxb)
b481de9c 618{
17744ff6
TW		 619 struct ieee80211_hdr *header;
620 struct ieee80211_rx_status rx_status;
3d24a9f7 621 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 622 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
623 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
624 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 625 int snr;
b481de9c
ZY		 626 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
627 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 628 u8 network_packet;
17744ff6 629
17744ff6
TW		 630 rx_status.flag = 0;
631 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 632 rx_status.freq =
c0186078 633 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 634 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
635 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
636
637 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 638 if (rx_status.band == IEEE80211_BAND_5GHZ)
639 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 640
6f0a2c4d
BR		 641 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
642 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
643
644 /* set the preamble flag if appropriate */
645 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
646 rx_status.flag |= RX_FLAG_SHORTPRE;
647
b481de9c
ZY		 648 if ((unlikely(rx_stats->phy_count > 20))) {
649 IWL_DEBUG_DROP
650 ("dsp size out of range [0,20]: "
651 "%d/n", rx_stats->phy_count);
652 return;
653 }
654
655 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
656 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
657 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
658 return;
659 }
660
56decd3c 661
b481de9c
ZY		 662
663 /* Convert 3945's rssi indicator to dBm */
250bdd21 664 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 665
666 /* Set default noise value to -127 */
667 if (priv->last_rx_noise == 0)
668 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
669
670 /* 3945 provides noise info for OFDM frames only.
671 * sig_avg and noise_diff are measured by the 3945's digital signal
672 * processor (DSP), and indicate linear levels of signal level and
673 * distortion/noise within the packet preamble after
674 * automatic gain control (AGC). sig_avg should stay fairly
675 * constant if the radio's AGC is working well.
676 * Since these values are linear (not dB or dBm), linear
677 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
678 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
679 * to obtain noise level in dBm.
17744ff6 680 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 681 if (rx_stats_noise_diff) {
682 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 683 rx_status.noise = rx_status.signal -
17744ff6 684 iwl3945_calc_db_from_ratio(snr);
566bfe5a 685 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 686 rx_status.noise);
b481de9c
ZY		 687
688 /* If noise info not available, calculate signal quality indicator (%)
689 * using just the dBm signal level. */
690 } else {
17744ff6 691 rx_status.noise = priv->last_rx_noise;
566bfe5a 692 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 693 }
694
695
696 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 697 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 698 rx_stats_sig_avg, rx_stats_noise_diff);
699
b481de9c
ZY		 700 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
701
bb8c093b 702 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 703
17744ff6
TW		 704 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
705 network_packet ? '*' : ' ',
706 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 707 rx_status.signal, rx_status.signal,
708 rx_status.noise, rx_status.rate_idx);
b481de9c 709
17744ff6 710#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 711 if (priv->debug_level & (IWL_DL_RX))
b481de9c 712 /* Set "1" to report good data frames in groups of 100 */
17744ff6 713 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 714#endif
715
716 if (network_packet) {
717 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
718 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 719 priv->last_rx_rssi = rx_status.signal;
17744ff6 720 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 721 }
722
12e5e22d 723 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 724}
725
4a8a4322 726int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 727 dma_addr_t addr, u16 len)
728{
729 int count;
730 u32 pad;
bb8c093b 731 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 732
733 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
734 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
735
736 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 737 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 738 NUM_TFD_CHUNKS);
739 return -EINVAL;
740 }
741
742 tfd->pa[count].addr = cpu_to_le32(addr);
743 tfd->pa[count].len = cpu_to_le32(len);
744
745 count++;
746
747 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
748 TFD_CTL_PAD_SET(pad));
749
750 return 0;
751}
752
753/**
bb8c093b 754 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 755 *
756 * Does NOT advance any indexes
757 */
4a8a4322 758int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 759{
bb8c093b
CH		 760 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
761 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 762 struct pci_dev *dev = priv->pci_dev;
763 int i;
764 int counter;
765
766 /* classify bd */
767 if (txq->q.id == IWL_CMD_QUEUE_NUM)
768 /* nothing to cleanup after for host commands */
769 return 0;
770
771 /* sanity check */
772 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
773 if (counter > NUM_TFD_CHUNKS) {
15b1687c 774 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c
ZY		 775 /* @todo issue fatal error, it is quite serious situation */
776 return 0;
777 }
778
779 /* unmap chunks if any */
780
781 for (i = 1; i < counter; i++) {
782 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
783 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 784 if (txq->txb[txq->q.read_ptr].skb[0]) {
785 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
786 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 787 /* Can be called from interrupt context */
788 dev_kfree_skb_any(skb);
fc4b6853 789 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 790 }
791 }
792 }
793 return 0;
794}
795
4a8a4322 796u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 797{
c93007ef 798 int i, start = IWL_AP_ID;
b481de9c
ZY		 799 int ret = IWL_INVALID_STATION;
800 unsigned long flags;
801
c93007ef
SO		 802 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
803 (priv->iw_mode == NL80211_IFTYPE_AP))
804 start = IWL_STA_ID;
805
806 if (is_broadcast_ether_addr(addr))
3832ec9d 807 return priv->hw_params.bcast_sta_id;
c93007ef 808
b481de9c 809 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 810 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 811 if ((priv->stations_39[i].used) &&
b481de9c 812 (!compare_ether_addr
f2c7e521 813 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 814 ret = i;
815 goto out;
816 }
817
e174961c
JB		 818 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
819 addr, priv->num_stations);
b481de9c
ZY		 820 out:
821 spin_unlock_irqrestore(&priv->sta_lock, flags);
822 return ret;
823}
824
825/**
bb8c093b 826 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 827 *
828*/
c2d79b48 829void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 830 struct ieee80211_tx_info *info,
b481de9c
ZY		 831 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
832{
e039fa4a 833 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 834 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 835 u16 rate_mask;
836 int rate;
837 u8 rts_retry_limit;
838 u8 data_retry_limit;
839 __le32 tx_flags;
fd7c8a40 840 __le16 fc = hdr->frame_control;
c2d79b48 841 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 842
bb8c093b 843 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 844 tx_flags = tx->tx_flags;
b481de9c
ZY		 845
846 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 847 * in this running context */
b481de9c
ZY		 848 rate_mask = IWL_RATES_MASK;
849
b481de9c
ZY		 850 if (tx_id >= IWL_CMD_QUEUE_NUM)
851 rts_retry_limit = 3;
852 else
853 rts_retry_limit = 7;
854
fd7c8a40 855 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 856 data_retry_limit = 3;
857 if (data_retry_limit < rts_retry_limit)
858 rts_retry_limit = data_retry_limit;
859 } else
860 data_retry_limit = IWL_DEFAULT_TX_RETRY;
861
862 if (priv->data_retry_limit != -1)
863 data_retry_limit = priv->data_retry_limit;
864
fd7c8a40
HH		 865 if (ieee80211_is_mgmt(fc)) {
866 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
867 case cpu_to_le16(IEEE80211_STYPE_AUTH):
868 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
869 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
870 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 871 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
872 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
873 tx_flags |= TX_CMD_FLG_CTS_MSK;
874 }
875 break;
876 default:
877 break;
878 }
879 }
880
c2d79b48
WT		 881 tx->rts_retry_limit = rts_retry_limit;
882 tx->data_retry_limit = data_retry_limit;
883 tx->rate = rate;
884 tx->tx_flags = tx_flags;
b481de9c
ZY		 885
886 /* OFDM */
c2d79b48 887 tx->supp_rates[0] =
14577f23 888 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 889
890 /* CCK */
c2d79b48 891 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 892
893 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
894 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 895 tx->rate, le32_to_cpu(tx->tx_flags),
896 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 897}
898
4a8a4322 899u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 900{
901 unsigned long flags_spin;
bb8c093b 902 struct iwl3945_station_entry *station;
b481de9c
ZY		 903
904 if (sta_id == IWL_INVALID_STATION)
905 return IWL_INVALID_STATION;
906
907 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 908 station = &priv->stations_39[sta_id];
b481de9c
ZY		 909
910 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
911 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 912 station->sta.mode = STA_CONTROL_MODIFY_MSK;
913
914 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
915
bb8c093b 916 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 917 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
918 sta_id, tx_rate);
919 return sta_id;
920}
921
854682ed 922static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c
ZY		 923{
924 int rc;
925 unsigned long flags;
926
927 spin_lock_irqsave(&priv->lock, flags);
5d49f498 928 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 929 if (rc) {
930 spin_unlock_irqrestore(&priv->lock, flags);
931 return rc;
932 }
933
854682ed 934 if (src == IWL_PWR_SRC_VAUX) {
b481de9c
ZY		 935 u32 val;
936
937 rc = pci_read_config_dword(priv->pci_dev,
938 PCI_POWER_SOURCE, &val);
939 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
5d49f498 940 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 941 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
942 ~APMG_PS_CTRL_MSK_PWR_SRC);
5d49f498 943 iwl_release_nic_access(priv);
b481de9c 944
5d49f498 945 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 946 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
947 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
948 } else
5d49f498 949 iwl_release_nic_access(priv);
b481de9c 950 } else {
5d49f498 951 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 952 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
953 ~APMG_PS_CTRL_MSK_PWR_SRC);
954
5d49f498
AK		 955 iwl_release_nic_access(priv);
956 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 957 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
958 }
959 spin_unlock_irqrestore(&priv->lock, flags);
960
961 return rc;
962}
963
4a8a4322 964static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY		 965{
966 int rc;
967 unsigned long flags;
968
969 spin_lock_irqsave(&priv->lock, flags);
5d49f498 970 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 971 if (rc) {
972 spin_unlock_irqrestore(&priv->lock, flags);
973 return rc;
974 }
975
5d49f498 976 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 977 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 978 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
979 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 980 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
981 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
982 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
983 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
984 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
985 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
986 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
987 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 988
989 /* fake read to flush all prev I/O */
5d49f498 990 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 991
5d49f498 992 iwl_release_nic_access(priv);
b481de9c
ZY		 993 spin_unlock_irqrestore(&priv->lock, flags);
994
995 return 0;
996}
997
4a8a4322 998static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c
ZY		 999{
1000 int rc;
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1004 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1005 if (rc) {
1006 spin_unlock_irqrestore(&priv->lock, flags);
1007 return rc;
1008 }
1009
1010 /* bypass mode */
5d49f498 1011 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1012
1013 /* RA 0 is active */
5d49f498 1014 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1015
1016 /* all 6 fifo are active */
5d49f498 1017 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1018
5d49f498
AK		 1019 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1020 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1021 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1022 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1023
5d49f498 1024 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 1025 priv->shared_phys);
b481de9c 1026
5d49f498 1027 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1028 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1029 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1030 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1031 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1032 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1033 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1034 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1035
5d49f498 1036 iwl_release_nic_access(priv);
b481de9c
ZY		 1037 spin_unlock_irqrestore(&priv->lock, flags);
1038
1039 return 0;
1040}
1041
1042/**
1043 * iwl3945_txq_ctx_reset - Reset TX queue context
1044 *
1045 * Destroys all DMA structures and initialize them again
1046 */
4a8a4322 1047static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1048{
1049 int rc;
1050 int txq_id, slots_num;
1051
bb8c093b 1052 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1053
1054 /* Tx CMD queue */
1055 rc = iwl3945_tx_reset(priv);
1056 if (rc)
1057 goto error;
1058
1059 /* Tx queue(s) */
1060 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1061 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1062 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
f2c7e521 1063 rc = iwl3945_tx_queue_init(priv, &priv->txq39[txq_id], slots_num,
b481de9c
ZY		 1064 txq_id);
1065 if (rc) {
15b1687c 1066 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1067 goto error;
1068 }
1069 }
1070
1071 return rc;
1072
1073 error:
bb8c093b 1074 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1075 return rc;
1076}
1077
01ec616d 1078static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1079{
01ec616d 1080 int ret = 0;
b481de9c 1081
bb8c093b 1082 iwl3945_power_init_handle(priv);
b481de9c 1083
5d49f498 1084 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1085 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1086
1087 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1088 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1089 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1090
01ec616d
KA		 1091 /* set "initialization complete" bit to move adapter
1092 * D0U* --> D0A* state */
5d49f498 1093 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d
KA		 1094
1095 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1096 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1097 if (ret < 0) {
b481de9c 1098 IWL_DEBUG_INFO("Failed to init the card\n");
01ec616d 1099 goto out;
b481de9c
ZY		 1100 }
1101
01ec616d
KA		 1102 ret = iwl_grab_nic_access(priv);
1103 if (ret)
1104 goto out;
1105
1106 /* enable DMA */
1107 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1108 APMG_CLK_VAL_BSM_CLK_RQT);
1109
b481de9c 1110 udelay(20);
01ec616d
KA		 1111
1112 /* disable L1-Active */
5d49f498 1113 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1114 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1115
5d49f498 1116 iwl_release_nic_access(priv);
01ec616d
KA		 1117out:
1118 return ret;
1119}
b481de9c 1120
01ec616d
KA		 1121static void iwl3945_nic_config(struct iwl_priv *priv)
1122{
1123 unsigned long flags;
1124 u8 rev_id = 0;
b481de9c 1125
b481de9c
ZY		 1126 spin_lock_irqsave(&priv->lock, flags);
1127
1128 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1129 IWL_DEBUG_INFO("RTP type \n");
1130 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1131 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
5d49f498 1132 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1133 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1134 } else {
6f83eaa1 1135 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
5d49f498 1136 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1137 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1138 }
1139
f2c7e521 1140 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
b481de9c 1141 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
5d49f498 1142 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1143 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1144 } else
1145 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1146
f2c7e521 1147 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
b481de9c 1148 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1149 priv->eeprom39.board_revision);
5d49f498 1150 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1151 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1152 } else {
1153 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1154 priv->eeprom39.board_revision);
5d49f498 1155 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1156 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1157 }
1158
f2c7e521 1159 if (priv->eeprom39.almgor_m_version <= 1) {
5d49f498 1160 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1161 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c 1162 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
f2c7e521 1163 priv->eeprom39.almgor_m_version);
b481de9c
ZY		 1164 } else {
1165 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
f2c7e521 1166 priv->eeprom39.almgor_m_version);
5d49f498 1167 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1168 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1169 }
1170 spin_unlock_irqrestore(&priv->lock, flags);
1171
f2c7e521 1172 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 1173 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1174
f2c7e521 1175 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c 1176 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1177}
1178
1179int iwl3945_hw_nic_init(struct iwl_priv *priv)
1180{
1181 u8 rev_id;
1182 int rc;
1183 unsigned long flags;
1184 struct iwl_rx_queue *rxq = &priv->rxq;
1185
1186 spin_lock_irqsave(&priv->lock, flags);
1187 priv->cfg->ops->lib->apm_ops.init(priv);
1188 spin_unlock_irqrestore(&priv->lock, flags);
1189
1190 /* Determine HW type */
1191 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1192 if (rc)
1193 return rc;
1194 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1195
854682ed
KA		 1196 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1197 if(rc)
1198 return rc;
1199
01ec616d 1200 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1201
1202 /* Allocate the RX queue, or reset if it is already allocated */
1203 if (!rxq->bd) {
bb8c093b 1204 rc = iwl3945_rx_queue_alloc(priv);
b481de9c 1205 if (rc) {
15b1687c 1206 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1207 return -ENOMEM;
1208 }
1209 } else
bb8c093b 1210 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1211
bb8c093b 1212 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1213
1214 iwl3945_rx_init(priv, rxq);
1215
1216 spin_lock_irqsave(&priv->lock, flags);
1217
1218 /* Look at using this instead:
1219 rxq->need_update = 1;
bb8c093b 1220 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1221 */
1222
5d49f498 1223 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1224 if (rc) {
1225 spin_unlock_irqrestore(&priv->lock, flags);
1226 return rc;
1227 }
5d49f498
AK		 1228 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1229 iwl_release_nic_access(priv);
b481de9c
ZY		 1230
1231 spin_unlock_irqrestore(&priv->lock, flags);
1232
1233 rc = iwl3945_txq_ctx_reset(priv);
1234 if (rc)
1235 return rc;
1236
1237 set_bit(STATUS_INIT, &priv->status);
1238
1239 return 0;
1240}
1241
1242/**
bb8c093b 1243 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1244 *
1245 * Destroy all TX DMA queues and structures
1246 */
4a8a4322 1247void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1248{
1249 int txq_id;
1250
1251 /* Tx queues */
1252 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
f2c7e521 1253 iwl3945_tx_queue_free(priv, &priv->txq39[txq_id]);
b481de9c
ZY		 1254}
1255
4a8a4322 1256void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1257{
bddadf86 1258 int txq_id;
b481de9c
ZY		 1259 unsigned long flags;
1260
1261 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1262 if (iwl_grab_nic_access(priv)) {
b481de9c 1263 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1264 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1265 return;
1266 }
1267
1268 /* stop SCD */
5d49f498 1269 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1270
1271 /* reset TFD queues */
bddadf86 1272 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
5d49f498
AK		 1273 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1274 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1275 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1276 1000);
1277 }
1278
5d49f498 1279 iwl_release_nic_access(priv);
b481de9c
ZY		 1280 spin_unlock_irqrestore(&priv->lock, flags);
1281
bb8c093b 1282 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1283}
1284
01ec616d 1285static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1286{
01ec616d 1287 int ret = 0;
b481de9c
ZY		 1288 unsigned long flags;
1289
1290 spin_lock_irqsave(&priv->lock, flags);
1291
1292 /* set stop master bit */
5d49f498 1293 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1294
01ec616d
KA		 1295 iwl_poll_direct_bit(priv, CSR_RESET,
1296 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1297
01ec616d
KA		 1298 if (ret < 0)
1299 goto out;
b481de9c 1300
01ec616d 1301out:
b481de9c
ZY		 1302 spin_unlock_irqrestore(&priv->lock, flags);
1303 IWL_DEBUG_INFO("stop master\n");
1304
01ec616d
KA		 1305 return ret;
1306}
1307
1308static void iwl3945_apm_stop(struct iwl_priv *priv)
1309{
1310 unsigned long flags;
1311
1312 iwl3945_apm_stop_master(priv);
1313
1314 spin_lock_irqsave(&priv->lock, flags);
1315
1316 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1317
1318 udelay(10);
1319 /* clear "init complete" move adapter D0A* --> D0U state */
1320 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1321 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1322}
1323
01ec616d 1324int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c
ZY		 1325{
1326 int rc;
1327 unsigned long flags;
1328
01ec616d 1329 iwl3945_apm_stop_master(priv);
b481de9c
ZY		 1330
1331 spin_lock_irqsave(&priv->lock, flags);
1332
5d49f498 1333 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1334
5d49f498 1335 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1336 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1337
5d49f498 1338 rc = iwl_grab_nic_access(priv);
b481de9c 1339 if (!rc) {
5d49f498 1340 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1341 APMG_CLK_VAL_BSM_CLK_RQT);
1342
1343 udelay(10);
1344
5d49f498 1345 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1346 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1347
5d49f498
AK		 1348 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1349 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1350 0xFFFFFFFF);
1351
1352 /* enable DMA */
5d49f498 1353 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1354 APMG_CLK_VAL_DMA_CLK_RQT |
1355 APMG_CLK_VAL_BSM_CLK_RQT);
1356 udelay(10);
1357
5d49f498 1358 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1359 APMG_PS_CTRL_VAL_RESET_REQ);
1360 udelay(5);
5d49f498 1361 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1362 APMG_PS_CTRL_VAL_RESET_REQ);
5d49f498 1363 iwl_release_nic_access(priv);
b481de9c
ZY		 1364 }
1365
1366 /* Clear the 'host command active' bit... */
1367 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1368
1369 wake_up_interruptible(&priv->wait_command_queue);
1370 spin_unlock_irqrestore(&priv->lock, flags);
1371
1372 return rc;
1373}
1374
1375/**
bb8c093b 1376 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1377 * return index delta into power gain settings table
1378*/
bb8c093b 1379static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1380{
1381 return (new_reading - old_reading) * (-11) / 100;
1382}
1383
1384/**
bb8c093b 1385 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1386 */
bb8c093b 1387static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1388{
3ac7f146 1389 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1390}
1391
4a8a4322 1392int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1393{
5d49f498 1394 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1395}
1396
1397/**
bb8c093b 1398 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1399 * get the current temperature by reading from NIC
1400*/
4a8a4322 1401static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 1402{
1403 int temperature;
1404
bb8c093b 1405 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1406
1407 /* driver's okay range is -260 to +25.
1408 * human readable okay range is 0 to +285 */
1409 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1410
1411 /* handle insane temp reading */
bb8c093b 1412 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1413 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1414
1415 /* if really really hot(?),
1416 * substitute the 3rd band/group's temp measured at factory */
1417 if (priv->last_temperature > 100)
f2c7e521 1418 temperature = priv->eeprom39.groups[2].temperature;
b481de9c
ZY		 1419 else /* else use most recent "sane" value from driver */
1420 temperature = priv->last_temperature;
1421 }
1422
1423 return temperature; /* raw, not "human readable" */
1424}
1425
1426/* Adjust Txpower only if temperature variance is greater than threshold.
1427 *
1428 * Both are lower than older versions' 9 degrees */
1429#define IWL_TEMPERATURE_LIMIT_TIMER 6
1430
1431/**
1432 * is_temp_calib_needed - determines if new calibration is needed
1433 *
1434 * records new temperature in tx_mgr->temperature.
1435 * replaces tx_mgr->last_temperature *only* if calib needed
1436 * (assumes caller will actually do the calibration!). */
4a8a4322 1437static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1438{
1439 int temp_diff;
1440
bb8c093b 1441 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1442 temp_diff = priv->temperature - priv->last_temperature;
1443
1444 /* get absolute value */
1445 if (temp_diff < 0) {
1446 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1447 temp_diff = -temp_diff;
1448 } else if (temp_diff == 0)
1449 IWL_DEBUG_POWER("Same temp,\n");
1450 else
1451 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1452
1453 /* if we don't need calibration, *don't* update last_temperature */
1454 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1455 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1456 return 0;
1457 }
1458
1459 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1460
1461 /* assume that caller will actually do calib ...
1462 * update the "last temperature" value */
1463 priv->last_temperature = priv->temperature;
1464 return 1;
1465}
1466
1467#define IWL_MAX_GAIN_ENTRIES 78
1468#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1469#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1470
1471/* radio and DSP power table, each step is 1/2 dB.
1472 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1473static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1474 {
1475 {251, 127}, /* 2.4 GHz, highest power */
1476 {251, 127},
1477 {251, 127},
1478 {251, 127},
1479 {251, 125},
1480 {251, 110},
1481 {251, 105},
1482 {251, 98},
1483 {187, 125},
1484 {187, 115},
1485 {187, 108},
1486 {187, 99},
1487 {243, 119},
1488 {243, 111},
1489 {243, 105},
1490 {243, 97},
1491 {243, 92},
1492 {211, 106},
1493 {211, 100},
1494 {179, 120},
1495 {179, 113},
1496 {179, 107},
1497 {147, 125},
1498 {147, 119},
1499 {147, 112},
1500 {147, 106},
1501 {147, 101},
1502 {147, 97},
1503 {147, 91},
1504 {115, 107},
1505 {235, 121},
1506 {235, 115},
1507 {235, 109},
1508 {203, 127},
1509 {203, 121},
1510 {203, 115},
1511 {203, 108},
1512 {203, 102},
1513 {203, 96},
1514 {203, 92},
1515 {171, 110},
1516 {171, 104},
1517 {171, 98},
1518 {139, 116},
1519 {227, 125},
1520 {227, 119},
1521 {227, 113},
1522 {227, 107},
1523 {227, 101},
1524 {227, 96},
1525 {195, 113},
1526 {195, 106},
1527 {195, 102},
1528 {195, 95},
1529 {163, 113},
1530 {163, 106},
1531 {163, 102},
1532 {163, 95},
1533 {131, 113},
1534 {131, 106},
1535 {131, 102},
1536 {131, 95},
1537 {99, 113},
1538 {99, 106},
1539 {99, 102},
1540 {99, 95},
1541 {67, 113},
1542 {67, 106},
1543 {67, 102},
1544 {67, 95},
1545 {35, 113},
1546 {35, 106},
1547 {35, 102},
1548 {35, 95},
1549 {3, 113},
1550 {3, 106},
1551 {3, 102},
1552 {3, 95} }, /* 2.4 GHz, lowest power */
1553 {
1554 {251, 127}, /* 5.x GHz, highest power */
1555 {251, 120},
1556 {251, 114},
1557 {219, 119},
1558 {219, 101},
1559 {187, 113},
1560 {187, 102},
1561 {155, 114},
1562 {155, 103},
1563 {123, 117},
1564 {123, 107},
1565 {123, 99},
1566 {123, 92},
1567 {91, 108},
1568 {59, 125},
1569 {59, 118},
1570 {59, 109},
1571 {59, 102},
1572 {59, 96},
1573 {59, 90},
1574 {27, 104},
1575 {27, 98},
1576 {27, 92},
1577 {115, 118},
1578 {115, 111},
1579 {115, 104},
1580 {83, 126},
1581 {83, 121},
1582 {83, 113},
1583 {83, 105},
1584 {83, 99},
1585 {51, 118},
1586 {51, 111},
1587 {51, 104},
1588 {51, 98},
1589 {19, 116},
1590 {19, 109},
1591 {19, 102},
1592 {19, 98},
1593 {19, 93},
1594 {171, 113},
1595 {171, 107},
1596 {171, 99},
1597 {139, 120},
1598 {139, 113},
1599 {139, 107},
1600 {139, 99},
1601 {107, 120},
1602 {107, 113},
1603 {107, 107},
1604 {107, 99},
1605 {75, 120},
1606 {75, 113},
1607 {75, 107},
1608 {75, 99},
1609 {43, 120},
1610 {43, 113},
1611 {43, 107},
1612 {43, 99},
1613 {11, 120},
1614 {11, 113},
1615 {11, 107},
1616 {11, 99},
1617 {131, 107},
1618 {131, 99},
1619 {99, 120},
1620 {99, 113},
1621 {99, 107},
1622 {99, 99},
1623 {67, 120},
1624 {67, 113},
1625 {67, 107},
1626 {67, 99},
1627 {35, 120},
1628 {35, 113},
1629 {35, 107},
1630 {35, 99},
1631 {3, 120} } /* 5.x GHz, lowest power */
1632};
1633
bb8c093b 1634static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1635{
1636 if (index < 0)
1637 return 0;
1638 if (index >= IWL_MAX_GAIN_ENTRIES)
1639 return IWL_MAX_GAIN_ENTRIES - 1;
1640 return (u8) index;
1641}
1642
1643/* Kick off thermal recalibration check every 60 seconds */
1644#define REG_RECALIB_PERIOD (60)
1645
1646/**
bb8c093b 1647 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1648 *
1649 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1650 * or 6 Mbit (OFDM) rates.
1651 */
4a8a4322 1652static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1653 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1654 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1655 int band_index)
1656{
bb8c093b 1657 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1658 s8 power;
1659 u8 power_index;
1660
1661 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1662
1663 /* use this channel group's 6Mbit clipping/saturation pwr,
1664 * but cap at regulatory scan power restriction (set during init
1665 * based on eeprom channel data) for this channel. */
14577f23 1666 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1667
1668 /* further limit to user's max power preference.
1669 * FIXME: Other spectrum management power limitations do not
1670 * seem to apply?? */
1671 power = min(power, priv->user_txpower_limit);
1672 scan_power_info->requested_power = power;
1673
1674 /* find difference between new scan *power* and current "normal"
1675 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1676 * current "normal" temperature-compensated Tx power *index* for
1677 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1678 * *index*. */
1679 power_index = ch_info->power_info[rate_index].power_table_index
1680 - (power - ch_info->power_info
14577f23 1681 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1682
1683 /* store reference index that we use when adjusting *all* scan
1684 * powers. So we can accommodate user (all channel) or spectrum
1685 * management (single channel) power changes "between" temperature
1686 * feedback compensation procedures.
1687 * don't force fit this reference index into gain table; it may be a
1688 * negative number. This will help avoid errors when we're at
1689 * the lower bounds (highest gains, for warmest temperatures)
1690 * of the table. */
1691
1692 /* don't exceed table bounds for "real" setting */
bb8c093b 1693 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1694
1695 scan_power_info->power_table_index = power_index;
1696 scan_power_info->tpc.tx_gain =
1697 power_gain_table[band_index][power_index].tx_gain;
1698 scan_power_info->tpc.dsp_atten =
1699 power_gain_table[band_index][power_index].dsp_atten;
1700}
1701
1702/**
bb8c093b 1703 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1704 *
1705 * Configures power settings for all rates for the current channel,
1706 * using values from channel info struct, and send to NIC
1707 */
4a8a4322 1708int iwl3945_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 1709{
14577f23 1710 int rate_idx, i;
d20b3c65 1711 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1712 struct iwl3945_txpowertable_cmd txpower = {
f2c7e521 1713 .channel = priv->active39_rxon.channel,
b481de9c
ZY		 1714 };
1715
8318d78a 1716 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1717 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1718 priv->band,
f2c7e521 1719 le16_to_cpu(priv->active39_rxon.channel));
b481de9c 1720 if (!ch_info) {
15b1687c
WT		 1721 IWL_ERR(priv,
1722 "Failed to get channel info for channel %d [%d]\n",
1723 le16_to_cpu(priv->active39_rxon.channel), priv->band);
b481de9c
ZY		 1724 return -EINVAL;
1725 }
1726
1727 if (!is_channel_valid(ch_info)) {
1728 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1729 "non-Tx channel.\n");
1730 return 0;
1731 }
1732
1733 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1734 /* Fill OFDM rate */
1735 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1736 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1737
1738 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1739 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1740
1741 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1742 le16_to_cpu(txpower.channel),
1743 txpower.band,
14577f23
MA		 1744 txpower.power[i].tpc.tx_gain,
1745 txpower.power[i].tpc.dsp_atten,
1746 txpower.power[i].rate);
1747 }
1748 /* Fill CCK rates */
1749 for (rate_idx = IWL_FIRST_CCK_RATE;
1750 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1751 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1752 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1753
1754 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1755 le16_to_cpu(txpower.channel),
1756 txpower.band,
1757 txpower.power[i].tpc.tx_gain,
1758 txpower.power[i].tpc.dsp_atten,
1759 txpower.power[i].rate);
b481de9c
ZY		 1760 }
1761
bb8c093b
CH		 1762 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1763 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1764
1765}
1766
1767/**
bb8c093b 1768 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1769 * @ch_info: Channel to update. Uses power_info.requested_power.
1770 *
1771 * Replace requested_power and base_power_index ch_info fields for
1772 * one channel.
1773 *
1774 * Called if user or spectrum management changes power preferences.
1775 * Takes into account h/w and modulation limitations (clip power).
1776 *
1777 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1778 *
1779 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1780 * properly fill out the scan powers, and actual h/w gain settings,
1781 * and send changes to NIC
1782 */
4a8a4322 1783static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1784 struct iwl_channel_info *ch_info)
b481de9c 1785{
bb8c093b 1786 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1787 int power_changed = 0;
1788 int i;
1789 const s8 *clip_pwrs;
1790 int power;
1791
1792 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1793 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1794
1795 /* Get this channel's rate-to-current-power settings table */
1796 power_info = ch_info->power_info;
1797
1798 /* update OFDM Txpower settings */
14577f23 1799 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1800 i++, ++power_info) {
1801 int delta_idx;
1802
1803 /* limit new power to be no more than h/w capability */
1804 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1805 if (power == power_info->requested_power)
1806 continue;
1807
1808 /* find difference between old and new requested powers,
1809 * update base (non-temp-compensated) power index */
1810 delta_idx = (power - power_info->requested_power) * 2;
1811 power_info->base_power_index -= delta_idx;
1812
1813 /* save new requested power value */
1814 power_info->requested_power = power;
1815
1816 power_changed = 1;
1817 }
1818
1819 /* update CCK Txpower settings, based on OFDM 12M setting ...
1820 * ... all CCK power settings for a given channel are the *same*. */
1821 if (power_changed) {
1822 power =
14577f23 1823 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1824 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1825
bb8c093b 1826 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1827 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1828 power_info->requested_power = power;
1829 power_info->base_power_index =
14577f23 1830 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1831 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1832 ++power_info;
1833 }
1834 }
1835
1836 return 0;
1837}
1838
1839/**
bb8c093b 1840 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1841 *
1842 * NOTE: Returned power limit may be less (but not more) than requested,
1843 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1844 * (no consideration for h/w clipping limitations).
1845 */
d20b3c65 1846static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1847{
1848 s8 max_power;
1849
1850#if 0
1851 /* if we're using TGd limits, use lower of TGd or EEPROM */
1852 if (ch_info->tgd_data.max_power != 0)
1853 max_power = min(ch_info->tgd_data.max_power,
1854 ch_info->eeprom.max_power_avg);
1855
1856 /* else just use EEPROM limits */
1857 else
1858#endif
1859 max_power = ch_info->eeprom.max_power_avg;
1860
1861 return min(max_power, ch_info->max_power_avg);
1862}
1863
1864/**
bb8c093b 1865 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1866 *
1867 * Compensate txpower settings of *all* channels for temperature.
1868 * This only accounts for the difference between current temperature
1869 * and the factory calibration temperatures, and bases the new settings
1870 * on the channel's base_power_index.
1871 *
1872 * If RxOn is "associated", this sends the new Txpower to NIC!
1873 */
4a8a4322 1874static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1875{
d20b3c65 1876 struct iwl_channel_info *ch_info = NULL;
b481de9c
ZY		 1877 int delta_index;
1878 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1879 u8 a_band;
1880 u8 rate_index;
1881 u8 scan_tbl_index;
1882 u8 i;
1883 int ref_temp;
1884 int temperature = priv->temperature;
1885
1886 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1887 for (i = 0; i < priv->channel_count; i++) {
1888 ch_info = &priv->channel_info[i];
1889 a_band = is_channel_a_band(ch_info);
1890
1891 /* Get this chnlgrp's factory calibration temperature */
f2c7e521 1892 ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 1893 temperature;
1894
a96a27f9 1895 /* get power index adjustment based on current and factory
b481de9c 1896 * temps */
bb8c093b 1897 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1898 ref_temp);
1899
1900 /* set tx power value for all rates, OFDM and CCK */
1901 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1902 rate_index++) {
1903 int power_idx =
1904 ch_info->power_info[rate_index].base_power_index;
1905
1906 /* temperature compensate */
1907 power_idx += delta_index;
1908
1909 /* stay within table range */
bb8c093b 1910 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1911 ch_info->power_info[rate_index].
1912 power_table_index = (u8) power_idx;
1913 ch_info->power_info[rate_index].tpc =
1914 power_gain_table[a_band][power_idx];
1915 }
1916
1917 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1918 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1919
1920 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1921 for (scan_tbl_index = 0;
1922 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1923 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1924 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1925 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1926 actual_index, clip_pwrs,
1927 ch_info, a_band);
1928 }
1929 }
1930
1931 /* send Txpower command for current channel to ucode */
bb8c093b 1932 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1933}
1934
4a8a4322 1935int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1936{
d20b3c65 1937 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1938 s8 max_power;
1939 u8 a_band;
1940 u8 i;
1941
1942 if (priv->user_txpower_limit == power) {
1943 IWL_DEBUG_POWER("Requested Tx power same as current "
1944 "limit: %ddBm.\n", power);
1945 return 0;
1946 }
1947
1948 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1949 priv->user_txpower_limit = power;
1950
1951 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1952
1953 for (i = 0; i < priv->channel_count; i++) {
1954 ch_info = &priv->channel_info[i];
1955 a_band = is_channel_a_band(ch_info);
1956
1957 /* find minimum power of all user and regulatory constraints
1958 * (does not consider h/w clipping limitations) */
bb8c093b 1959 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1960 max_power = min(power, max_power);
1961 if (max_power != ch_info->curr_txpow) {
1962 ch_info->curr_txpow = max_power;
1963
1964 /* this considers the h/w clipping limitations */
bb8c093b 1965 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1966 }
1967 }
1968
1969 /* update txpower settings for all channels,
1970 * send to NIC if associated. */
1971 is_temp_calib_needed(priv);
bb8c093b 1972 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1973
1974 return 0;
1975}
1976
1977/* will add 3945 channel switch cmd handling later */
4a8a4322 1978int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1979{
1980 return 0;
1981}
1982
1983/**
1984 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1985 *
1986 * -- reset periodic timer
1987 * -- see if temp has changed enough to warrant re-calibration ... if so:
1988 * -- correct coeffs for temp (can reset temp timer)
1989 * -- save this temp as "last",
1990 * -- send new set of gain settings to NIC
1991 * NOTE: This should continue working, even when we're not associated,
1992 * so we can keep our internal table of scan powers current. */
4a8a4322 1993void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1994{
1995 /* This will kick in the "brute force"
bb8c093b 1996 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1997 if (!is_temp_calib_needed(priv))
1998 goto reschedule;
1999
2000 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2001 * This is based *only* on current temperature,
2002 * ignoring any previous power measurements */
bb8c093b 2003 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2004
2005 reschedule:
2006 queue_delayed_work(priv->workqueue,
2007 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2008}
2009
416e1438 2010static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2011{
4a8a4322 2012 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2013 thermal_periodic.work);
2014
2015 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2016 return;
2017
2018 mutex_lock(&priv->mutex);
2019 iwl3945_reg_txpower_periodic(priv);
2020 mutex_unlock(&priv->mutex);
2021}
2022
2023/**
bb8c093b 2024 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2025 * for the channel.
2026 *
2027 * This function is used when initializing channel-info structs.
2028 *
2029 * NOTE: These channel groups do *NOT* match the bands above!
2030 * These channel groups are based on factory-tested channels;
2031 * on A-band, EEPROM's "group frequency" entries represent the top
2032 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2033 */
4a8a4322 2034static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2035 const struct iwl_channel_info *ch_info)
b481de9c 2036{
f2c7e521 2037 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0];
b481de9c
ZY		 2038 u8 group;
2039 u16 group_index = 0; /* based on factory calib frequencies */
2040 u8 grp_channel;
2041
2042 /* Find the group index for the channel ... don't use index 1(?) */
2043 if (is_channel_a_band(ch_info)) {
2044 for (group = 1; group < 5; group++) {
2045 grp_channel = ch_grp[group].group_channel;
2046 if (ch_info->channel <= grp_channel) {
2047 group_index = group;
2048 break;
2049 }
2050 }
2051 /* group 4 has a few channels *above* its factory cal freq */
2052 if (group == 5)
2053 group_index = 4;
2054 } else
2055 group_index = 0; /* 2.4 GHz, group 0 */
2056
2057 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2058 group_index);
2059 return group_index;
2060}
2061
2062/**
bb8c093b 2063 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2064 *
2065 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2066 * into radio/DSP gain settings table for requested power.
2067 */
4a8a4322 2068static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2069 s8 requested_power,
2070 s32 setting_index, s32 *new_index)
2071{
bb8c093b 2072 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2073 s32 index0, index1;
2074 s32 power = 2 * requested_power;
2075 s32 i;
bb8c093b 2076 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2077 s32 gains0, gains1;
2078 s32 res;
2079 s32 denominator;
2080
f2c7e521 2081 chnl_grp = &priv->eeprom39.groups[setting_index];
b481de9c
ZY		 2082 samples = chnl_grp->samples;
2083 for (i = 0; i < 5; i++) {
2084 if (power == samples[i].power) {
2085 *new_index = samples[i].gain_index;
2086 return 0;
2087 }
2088 }
2089
2090 if (power > samples[1].power) {
2091 index0 = 0;
2092 index1 = 1;
2093 } else if (power > samples[2].power) {
2094 index0 = 1;
2095 index1 = 2;
2096 } else if (power > samples[3].power) {
2097 index0 = 2;
2098 index1 = 3;
2099 } else {
2100 index0 = 3;
2101 index1 = 4;
2102 }
2103
2104 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2105 if (denominator == 0)
2106 return -EINVAL;
2107 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2108 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2109 res = gains0 + (gains1 - gains0) *
2110 ((s32) power - (s32) samples[index0].power) / denominator +
2111 (1 << 18);
2112 *new_index = res >> 19;
2113 return 0;
2114}
2115
4a8a4322 2116static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2117{
2118 u32 i;
2119 s32 rate_index;
bb8c093b 2120 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2121
2122 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2123
2124 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2125 s8 *clip_pwrs; /* table of power levels for each rate */
2126 s8 satur_pwr; /* saturation power for each chnl group */
f2c7e521 2127 group = &priv->eeprom39.groups[i];
b481de9c
ZY		 2128
2129 /* sanity check on factory saturation power value */
2130 if (group->saturation_power < 40) {
39aadf8c 2131 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2132 "less than minimum expected 40\n",
2133 group->saturation_power);
2134 return;
2135 }
2136
2137 /*
2138 * Derive requested power levels for each rate, based on
2139 * hardware capabilities (saturation power for band).
2140 * Basic value is 3dB down from saturation, with further
2141 * power reductions for highest 3 data rates. These
2142 * backoffs provide headroom for high rate modulation
2143 * power peaks, without too much distortion (clipping).
2144 */
2145 /* we'll fill in this array with h/w max power levels */
f2c7e521 2146 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2147
2148 /* divide factory saturation power by 2 to find -3dB level */
2149 satur_pwr = (s8) (group->saturation_power >> 1);
2150
2151 /* fill in channel group's nominal powers for each rate */
2152 for (rate_index = 0;
2153 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2154 switch (rate_index) {
14577f23 2155 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2156 if (i == 0) /* B/G */
2157 *clip_pwrs = satur_pwr;
2158 else /* A */
2159 *clip_pwrs = satur_pwr - 5;
2160 break;
14577f23 2161 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2162 if (i == 0)
2163 *clip_pwrs = satur_pwr - 7;
2164 else
2165 *clip_pwrs = satur_pwr - 10;
2166 break;
14577f23 2167 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2168 if (i == 0)
2169 *clip_pwrs = satur_pwr - 9;
2170 else
2171 *clip_pwrs = satur_pwr - 12;
2172 break;
2173 default:
2174 *clip_pwrs = satur_pwr;
2175 break;
2176 }
2177 }
2178 }
2179}
2180
2181/**
2182 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2183 *
2184 * Second pass (during init) to set up priv->channel_info
2185 *
2186 * Set up Tx-power settings in our channel info database for each VALID
2187 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2188 * and current temperature.
2189 *
2190 * Since this is based on current temperature (at init time), these values may
2191 * not be valid for very long, but it gives us a starting/default point,
2192 * and allows us to active (i.e. using Tx) scan.
2193 *
2194 * This does *not* write values to NIC, just sets up our internal table.
2195 */
4a8a4322 2196int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2197{
d20b3c65 2198 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2199 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2200 int delta_index;
2201 u8 rate_index;
2202 u8 scan_tbl_index;
2203 const s8 *clip_pwrs; /* array of power levels for each rate */
2204 u8 gain, dsp_atten;
2205 s8 power;
2206 u8 pwr_index, base_pwr_index, a_band;
2207 u8 i;
2208 int temperature;
2209
2210 /* save temperature reference,
2211 * so we can determine next time to calibrate */
bb8c093b 2212 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2213 priv->last_temperature = temperature;
2214
bb8c093b 2215 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2216
2217 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2218 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2219 i++, ch_info++) {
2220 a_band = is_channel_a_band(ch_info);
2221 if (!is_channel_valid(ch_info))
2222 continue;
2223
2224 /* find this channel's channel group (*not* "band") index */
2225 ch_info->group_index =
bb8c093b 2226 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2227
2228 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2229 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2230
2231 /* calculate power index *adjustment* value according to
2232 * diff between current temperature and factory temperature */
bb8c093b 2233 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
f2c7e521 2234 priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 2235 temperature);
2236
2237 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2238 ch_info->channel, delta_index, temperature +
2239 IWL_TEMP_CONVERT);
2240
2241 /* set tx power value for all OFDM rates */
2242 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2243 rate_index++) {
25a4ccea 2244 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2245 int rc;
2246
2247 /* use channel group's clip-power table,
2248 * but don't exceed channel's max power */
2249 s8 pwr = min(ch_info->max_power_avg,
2250 clip_pwrs[rate_index]);
2251
2252 pwr_info = &ch_info->power_info[rate_index];
2253
2254 /* get base (i.e. at factory-measured temperature)
2255 * power table index for this rate's power */
bb8c093b 2256 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2257 ch_info->group_index,
2258 &power_idx);
2259 if (rc) {
15b1687c 2260 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2261 return rc;
2262 }
2263 pwr_info->base_power_index = (u8) power_idx;
2264
2265 /* temperature compensate */
2266 power_idx += delta_index;
2267
2268 /* stay within range of gain table */
bb8c093b 2269 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2270
bb8c093b 2271 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2272 pwr_info->requested_power = pwr;
2273 pwr_info->power_table_index = (u8) power_idx;
2274 pwr_info->tpc.tx_gain =
2275 power_gain_table[a_band][power_idx].tx_gain;
2276 pwr_info->tpc.dsp_atten =
2277 power_gain_table[a_band][power_idx].dsp_atten;
2278 }
2279
2280 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2281 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2282 power = pwr_info->requested_power +
2283 IWL_CCK_FROM_OFDM_POWER_DIFF;
2284 pwr_index = pwr_info->power_table_index +
2285 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2286 base_pwr_index = pwr_info->base_power_index +
2287 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2288
2289 /* stay within table range */
bb8c093b 2290 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2291 gain = power_gain_table[a_band][pwr_index].tx_gain;
2292 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2293
bb8c093b 2294 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2295 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2296 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2297 for (rate_index = 0;
2298 rate_index < IWL_CCK_RATES; rate_index++) {
2299 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2300 pwr_info->requested_power = power;
2301 pwr_info->power_table_index = pwr_index;
2302 pwr_info->base_power_index = base_pwr_index;
2303 pwr_info->tpc.tx_gain = gain;
2304 pwr_info->tpc.dsp_atten = dsp_atten;
2305 }
2306
2307 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2308 for (scan_tbl_index = 0;
2309 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2310 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2311 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2312 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2313 actual_index, clip_pwrs, ch_info, a_band);
2314 }
2315 }
2316
2317 return 0;
2318}
2319
4a8a4322 2320int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2321{
2322 int rc;
2323 unsigned long flags;
2324
2325 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2326 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2327 if (rc) {
2328 spin_unlock_irqrestore(&priv->lock, flags);
2329 return rc;
2330 }
2331
5d49f498
AK		 2332 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2333 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2334 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2335 if (rc < 0)
15b1687c 2336 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2337
5d49f498 2338 iwl_release_nic_access(priv);
b481de9c
ZY		 2339 spin_unlock_irqrestore(&priv->lock, flags);
2340
2341 return 0;
2342}
2343
4a8a4322 2344int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2345{
2346 int rc;
2347 unsigned long flags;
2348 int txq_id = txq->q.id;
2349
3832ec9d 2350 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2351
2352 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2353
2354 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2355 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2356 if (rc) {
2357 spin_unlock_irqrestore(&priv->lock, flags);
2358 return rc;
2359 }
5d49f498
AK		 2360 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2361 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2362
5d49f498 2363 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2364 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2365 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2366 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2367 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2368 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
5d49f498 2369 iwl_release_nic_access(priv);
b481de9c
ZY		 2370
2371 /* fake read to flush all prev. writes */
5d49f498 2372 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2373 spin_unlock_irqrestore(&priv->lock, flags);
2374
2375 return 0;
2376}
2377
b481de9c
ZY		 2378/**
2379 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2380 */
4a8a4322 2381int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2382{
14577f23 2383 int rc, i, index, prev_index;
bb8c093b 2384 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2385 .reserved = {0, 0, 0},
2386 };
bb8c093b 2387 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2388
bb8c093b
CH		 2389 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2390 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2391
2392 table[index].rate_n_flags =
bb8c093b 2393 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2394 table[index].try_cnt = priv->retry_rate;
bb8c093b 2395 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2396 table[index].next_rate_index =
2397 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2398 }
2399
8318d78a
JB		 2400 switch (priv->band) {
2401 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2402 IWL_DEBUG_RATE("Select A mode rate scale\n");
2403 /* If one of the following CCK rates is used,
2404 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2405 for (i = IWL_RATE_1M_INDEX_TABLE;
2406 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2407 table[i].next_rate_index =
2408 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2409
2410 /* Don't fall back to CCK rates */
7262796a
AM		 2411 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2412 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2413
2414 /* Don't drop out of OFDM rates */
14577f23 2415 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2416 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2417 break;
2418
8318d78a
JB		 2419 case IEEE80211_BAND_2GHZ:
2420 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2421 /* If an OFDM rate is used, have it fall back to the
2422 * 1M CCK rates */
b481de9c 2423
7262796a
AM		 2424 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2425 iwl3945_is_associated(priv)) {
2426
2427 index = IWL_FIRST_CCK_RATE;
2428 for (i = IWL_RATE_6M_INDEX_TABLE;
2429 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2430 table[i].next_rate_index =
2431 iwl3945_rates[index].table_rs_index;
2432
2433 index = IWL_RATE_11M_INDEX_TABLE;
2434 /* CCK shouldn't fall back to OFDM... */
2435 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2436 }
b481de9c
ZY		 2437 break;
2438
2439 default:
8318d78a 2440 WARN_ON(1);
b481de9c
ZY		 2441 break;
2442 }
2443
2444 /* Update the rate scaling for control frame Tx */
2445 rate_cmd.table_id = 0;
bb8c093b 2446 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2447 &rate_cmd);
2448 if (rc)
2449 return rc;
2450
2451 /* Update the rate scaling for data frame Tx */
2452 rate_cmd.table_id = 1;
bb8c093b 2453 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2454 &rate_cmd);
2455}
2456
796083cb 2457/* Called when initializing driver */
4a8a4322 2458int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2459{
3832ec9d
AK		 2460 memset((void *)&priv->hw_params, 0,
2461 sizeof(struct iwl_hw_params));
b481de9c 2462
3832ec9d 2463 priv->shared_virt =
b481de9c 2464 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2465 sizeof(struct iwl3945_shared),
3832ec9d 2466 &priv->shared_phys);
b481de9c 2467
3832ec9d 2468 if (!priv->shared_virt) {
15b1687c 2469 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2470 mutex_unlock(&priv->mutex);
2471 return -ENOMEM;
2472 }
2473
3832ec9d
AK		 2474 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE;
2475 priv->hw_params.max_pkt_size = 2342;
2476 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2477 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2478 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2479 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2480
3832ec9d 2481 priv->hw_params.tx_ant_num = 2;
b481de9c
ZY		 2482 return 0;
2483}
2484
4a8a4322 2485unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2486 struct iwl3945_frame *frame, u8 rate)
b481de9c 2487{
bb8c093b 2488 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2489 unsigned int frame_size;
2490
bb8c093b 2491 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2492 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2493
3832ec9d 2494 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2495 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2496
bb8c093b 2497 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2498 tx_beacon_cmd->frame,
b481de9c
ZY		 2499 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2500
2501 BUG_ON(frame_size > MAX_MPDU_SIZE);
2502 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2503
2504 tx_beacon_cmd->tx.rate = rate;
2505 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2506 TX_CMD_FLG_TSF_MSK);
2507
14577f23
MA		 2508 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2509 tx_beacon_cmd->tx.supp_rates[0] =
2510 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2511
b481de9c 2512 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2513 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2514
3ac7f146 2515 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2516}
2517
4a8a4322 2518void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2519{
91c066f2 2520 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2521 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2522}
2523
4a8a4322 2524void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2525{
2526 INIT_DELAYED_WORK(&priv->thermal_periodic,
2527 iwl3945_bg_reg_txpower_periodic);
2528}
2529
4a8a4322 2530void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2531{
2532 cancel_delayed_work(&priv->thermal_periodic);
2533}
2534
0164b9b4
KA		 2535/* check contents of special bootstrap uCode SRAM */
2536static int iwl3945_verify_bsm(struct iwl_priv *priv)
2537 {
2538 __le32 *image = priv->ucode_boot.v_addr;
2539 u32 len = priv->ucode_boot.len;
2540 u32 reg;
2541 u32 val;
2542
2543 IWL_DEBUG_INFO("Begin verify bsm\n");
2544
2545 /* verify BSM SRAM contents */
2546 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2547 for (reg = BSM_SRAM_LOWER_BOUND;
2548 reg < BSM_SRAM_LOWER_BOUND + len;
2549 reg += sizeof(u32), image++) {
2550 val = iwl_read_prph(priv, reg);
2551 if (val != le32_to_cpu(*image)) {
2552 IWL_ERR(priv, "BSM uCode verification failed at "
2553 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2554 BSM_SRAM_LOWER_BOUND,
2555 reg - BSM_SRAM_LOWER_BOUND, len,
2556 val, le32_to_cpu(*image));
2557 return -EIO;
2558 }
2559 }
2560
2561 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2562
2563 return 0;
2564}
2565
2566 /**
2567 * iwl3945_load_bsm - Load bootstrap instructions
2568 *
2569 * BSM operation:
2570 *
2571 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2572 * in special SRAM that does not power down during RFKILL. When powering back
2573 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2574 * the bootstrap program into the on-board processor, and starts it.
2575 *
2576 * The bootstrap program loads (via DMA) instructions and data for a new
2577 * program from host DRAM locations indicated by the host driver in the
2578 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2579 * automatically.
2580 *
2581 * When initializing the NIC, the host driver points the BSM to the
2582 * "initialize" uCode image. This uCode sets up some internal data, then
2583 * notifies host via "initialize alive" that it is complete.
2584 *
2585 * The host then replaces the BSM_DRAM_* pointer values to point to the
2586 * normal runtime uCode instructions and a backup uCode data cache buffer
2587 * (filled initially with starting data values for the on-board processor),
2588 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2589 * which begins normal operation.
2590 *
2591 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2592 * the backup data cache in DRAM before SRAM is powered down.
2593 *
2594 * When powering back up, the BSM loads the bootstrap program. This reloads
2595 * the runtime uCode instructions and the backup data cache into SRAM,
2596 * and re-launches the runtime uCode from where it left off.
2597 */
2598static int iwl3945_load_bsm(struct iwl_priv *priv)
2599{
2600 __le32 *image = priv->ucode_boot.v_addr;
2601 u32 len = priv->ucode_boot.len;
2602 dma_addr_t pinst;
2603 dma_addr_t pdata;
2604 u32 inst_len;
2605 u32 data_len;
2606 int rc;
2607 int i;
2608 u32 done;
2609 u32 reg_offset;
2610
2611 IWL_DEBUG_INFO("Begin load bsm\n");
2612
2613 /* make sure bootstrap program is no larger than BSM's SRAM size */
2614 if (len > IWL39_MAX_BSM_SIZE)
2615 return -EINVAL;
2616
2617 /* Tell bootstrap uCode where to find the "Initialize" uCode
2618 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2619 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2620 * after the "initialize" uCode has run, to point to
2621 * runtime/protocol instructions and backup data cache. */
2622 pinst = priv->ucode_init.p_addr;
2623 pdata = priv->ucode_init_data.p_addr;
2624 inst_len = priv->ucode_init.len;
2625 data_len = priv->ucode_init_data.len;
2626
2627 rc = iwl_grab_nic_access(priv);
2628 if (rc)
2629 return rc;
2630
2631 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2632 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2633 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2634 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2635
2636 /* Fill BSM memory with bootstrap instructions */
2637 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2638 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2639 reg_offset += sizeof(u32), image++)
2640 _iwl_write_prph(priv, reg_offset,
2641 le32_to_cpu(*image));
2642
2643 rc = iwl3945_verify_bsm(priv);
2644 if (rc) {
2645 iwl_release_nic_access(priv);
2646 return rc;
2647 }
2648
2649 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2650 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2651 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2652 IWL39_RTC_INST_LOWER_BOUND);
2653 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2654
2655 /* Load bootstrap code into instruction SRAM now,
2656 * to prepare to load "initialize" uCode */
2657 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2658 BSM_WR_CTRL_REG_BIT_START);
2659
2660 /* Wait for load of bootstrap uCode to finish */
2661 for (i = 0; i < 100; i++) {
2662 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2663 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2664 break;
2665 udelay(10);
2666 }
2667 if (i < 100)
2668 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2669 else {
2670 IWL_ERR(priv, "BSM write did not complete!\n");
2671 return -EIO;
2672 }
2673
2674 /* Enable future boot loads whenever power management unit triggers it
2675 * (e.g. when powering back up after power-save shutdown) */
2676 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2677 BSM_WR_CTRL_REG_BIT_START_EN);
2678
2679 iwl_release_nic_access(priv);
2680
2681 return 0;
2682}
2683
2684static struct iwl_lib_ops iwl3945_lib = {
2685 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2686 .apm_ops = {
2687 .init = iwl3945_apm_init,
2688 .reset = iwl3945_apm_reset,
2689 .stop = iwl3945_apm_stop,
2690 .config = iwl3945_nic_config,
854682ed 2691 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2692 },
0164b9b4
KA		 2693};
2694
2695static struct iwl_ops iwl3945_ops = {
2696 .lib = &iwl3945_lib,
2697};
2698
c0f20d91 2699static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2700 .name = "3945BG",
a0987a8d
RC		 2701 .fw_name_pre = IWL3945_FW_PRE,
2702 .ucode_api_max = IWL3945_UCODE_API_MAX,
2703 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2704 .sku = IWL_SKU_G,
0164b9b4 2705 .ops = &iwl3945_ops,
df878d8f 2706 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2707};
2708
c0f20d91 2709static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2710 .name = "3945ABG",
a0987a8d
RC		 2711 .fw_name_pre = IWL3945_FW_PRE,
2712 .ucode_api_max = IWL3945_UCODE_API_MAX,
2713 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2714 .sku = IWL_SKU_A|IWL_SKU_G,
0164b9b4 2715 .ops = &iwl3945_ops,
df878d8f 2716 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2717};
2718
bb8c093b 2719struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2720 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2721 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2722 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2723 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2724 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2725 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2726 {0}
2727};
2728
bb8c093b 2729MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)