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iwlwifi: Update iwlwifi version stamp to 1.1.19
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <net/mac80211.h>
39
40#include <linux/etherdevice.h>
b481de9c 41
1156b2c6
ZY		 42#define IWL 3945
43
b481de9c
ZY		 44#include "iwlwifi.h"
45#include "iwl-helpers.h"
46#include "iwl-3945.h"
47#include "iwl-3945-rs.h"
48
49#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_##r##M_IEEE, \
52 IWL_RATE_##ip##M_INDEX, \
53 IWL_RATE_##in##M_INDEX, \
54 IWL_RATE_##rp##M_INDEX, \
55 IWL_RATE_##rn##M_INDEX, \
56 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 57 IWL_RATE_##np##M_INDEX, \
58 IWL_RATE_##r##M_INDEX_TABLE, \
59 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 60
61/*
62 * Parameter order:
63 * rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
69const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
14577f23
MA		 70 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 74 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 82};
83
84/* 1 = enable the iwl_disable_events() function */
85#define IWL_EVT_DISABLE (0)
86#define IWL_EVT_DISABLE_SIZE (1532/32)
87
88/**
89 * iwl_disable_events - Disable selected events in uCode event log
90 *
91 * Disable an event by writing "1"s into "disable"
92 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
93 * Default values of 0 enable uCode events to be logged.
94 * Use for only special debugging. This function is just a placeholder as-is,
95 * you'll need to provide the special bits! ...
96 * ... and set IWL_EVT_DISABLE to 1. */
97void iwl_disable_events(struct iwl_priv *priv)
98{
af7cca2a 99 int ret;
b481de9c
ZY		 100 int i;
101 u32 base; /* SRAM address of event log header */
102 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
103 u32 array_size; /* # of u32 entries in array */
104 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
105 0x00000000, /* 31 - 0 Event id numbers */
106 0x00000000, /* 63 - 32 */
107 0x00000000, /* 95 - 64 */
108 0x00000000, /* 127 - 96 */
109 0x00000000, /* 159 - 128 */
110 0x00000000, /* 191 - 160 */
111 0x00000000, /* 223 - 192 */
112 0x00000000, /* 255 - 224 */
113 0x00000000, /* 287 - 256 */
114 0x00000000, /* 319 - 288 */
115 0x00000000, /* 351 - 320 */
116 0x00000000, /* 383 - 352 */
117 0x00000000, /* 415 - 384 */
118 0x00000000, /* 447 - 416 */
119 0x00000000, /* 479 - 448 */
120 0x00000000, /* 511 - 480 */
121 0x00000000, /* 543 - 512 */
122 0x00000000, /* 575 - 544 */
123 0x00000000, /* 607 - 576 */
124 0x00000000, /* 639 - 608 */
125 0x00000000, /* 671 - 640 */
126 0x00000000, /* 703 - 672 */
127 0x00000000, /* 735 - 704 */
128 0x00000000, /* 767 - 736 */
129 0x00000000, /* 799 - 768 */
130 0x00000000, /* 831 - 800 */
131 0x00000000, /* 863 - 832 */
132 0x00000000, /* 895 - 864 */
133 0x00000000, /* 927 - 896 */
134 0x00000000, /* 959 - 928 */
135 0x00000000, /* 991 - 960 */
136 0x00000000, /* 1023 - 992 */
137 0x00000000, /* 1055 - 1024 */
138 0x00000000, /* 1087 - 1056 */
139 0x00000000, /* 1119 - 1088 */
140 0x00000000, /* 1151 - 1120 */
141 0x00000000, /* 1183 - 1152 */
142 0x00000000, /* 1215 - 1184 */
143 0x00000000, /* 1247 - 1216 */
144 0x00000000, /* 1279 - 1248 */
145 0x00000000, /* 1311 - 1280 */
146 0x00000000, /* 1343 - 1312 */
147 0x00000000, /* 1375 - 1344 */
148 0x00000000, /* 1407 - 1376 */
149 0x00000000, /* 1439 - 1408 */
150 0x00000000, /* 1471 - 1440 */
151 0x00000000, /* 1503 - 1472 */
152 };
153
154 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
155 if (!iwl_hw_valid_rtc_data_addr(base)) {
156 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
157 return;
158 }
159
ac17a947 160 ret = iwl_grab_nic_access(priv);
af7cca2a 161 if (ret) {
b481de9c
ZY		 162 IWL_WARNING("Can not read from adapter at this time.\n");
163 return;
164 }
165
af7cca2a
TW		 166 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
167 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
ac17a947 168 iwl_release_nic_access(priv);
b481de9c
ZY		 169
170 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
171 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
172 disable_ptr);
ac17a947 173 ret = iwl_grab_nic_access(priv);
b481de9c 174 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
af7cca2a
TW		 175 iwl_write_targ_mem(priv,
176 disable_ptr + (i * sizeof(u32)),
177 evt_disable[i]);
b481de9c 178
ac17a947 179 iwl_release_nic_access(priv);
b481de9c
ZY		 180 } else {
181 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
182 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
183 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
184 disable_ptr, array_size);
185 }
186
187}
188
189/**
190 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
191 * @priv: eeprom and antenna fields are used to determine antenna flags
192 *
193 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
194 * priv->antenna specifies the antenna diversity mode:
195 *
196 * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
197 * IWL_ANTENNA_MAIN - Force MAIN antenna
198 * IWL_ANTENNA_AUX - Force AUX antenna
199 */
200__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
201{
202 switch (priv->antenna) {
203 case IWL_ANTENNA_DIVERSITY:
204 return 0;
205
206 case IWL_ANTENNA_MAIN:
207 if (priv->eeprom.antenna_switch_type)
208 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
209 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
210
211 case IWL_ANTENNA_AUX:
212 if (priv->eeprom.antenna_switch_type)
213 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
214 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
215 }
216
217 /* bad antenna selector value */
218 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
219 return 0; /* "diversity" is default if error */
220}
221
222/*****************************************************************************
223 *
224 * Intel PRO/Wireless 3945ABG/BG Network Connection
225 *
226 * RX handler implementations
227 *
228 * Used by iwl-base.c
229 *
230 *****************************************************************************/
231
232void iwl_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
233{
234 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
235 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
236 (int)sizeof(struct iwl_notif_statistics),
237 le32_to_cpu(pkt->len));
238
239 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
240
241 priv->last_statistics_time = jiffies;
242}
243
244static void iwl3945_handle_data_packet(struct iwl_priv *priv, int is_data,
245 struct iwl_rx_mem_buffer *rxb,
246 struct ieee80211_rx_status *stats,
247 u16 phy_flags)
248{
249 struct ieee80211_hdr *hdr;
250 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
251 struct iwl_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
252 struct iwl_rx_frame_end *rx_end = IWL_RX_END(pkt);
253 short len = le16_to_cpu(rx_hdr->len);
254
255 /* We received data from the HW, so stop the watchdog */
256 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
257 IWL_DEBUG_DROP("Corruption detected!\n");
258 return;
259 }
260
261 /* We only process data packets if the interface is open */
262 if (unlikely(!priv->is_open)) {
263 IWL_DEBUG_DROP_LIMIT
264 ("Dropping packet while interface is not open.\n");
265 return;
266 }
267 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
268 if (iwl_param_hwcrypto)
269 iwl_set_decrypted_flag(priv, rxb->skb,
270 le32_to_cpu(rx_end->status),
271 stats);
272 iwl_handle_data_packet_monitor(priv, rxb, IWL_RX_DATA(pkt),
273 len, stats, phy_flags);
274 return;
275 }
276
277 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
278 /* Set the size of the skb to the size of the frame */
279 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
280
281 hdr = (void *)rxb->skb->data;
282
283 if (iwl_param_hwcrypto)
284 iwl_set_decrypted_flag(priv, rxb->skb,
285 le32_to_cpu(rx_end->status), stats);
286
287 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
288 rxb->skb = NULL;
289}
290
291static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
292 struct iwl_rx_mem_buffer *rxb)
293{
294 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
295 struct iwl_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
296 struct iwl_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
297 struct iwl_rx_frame_end *rx_end = IWL_RX_END(pkt);
298 struct ieee80211_hdr *header;
299 u16 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
300 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
301 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
302 struct ieee80211_rx_status stats = {
303 .mactime = le64_to_cpu(rx_end->timestamp),
304 .freq = ieee80211chan2mhz(le16_to_cpu(rx_hdr->channel)),
305 .channel = le16_to_cpu(rx_hdr->channel),
306 .phymode = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
307 MODE_IEEE80211G : MODE_IEEE80211A,
308 .antenna = 0,
309 .rate = rx_hdr->rate,
310 .flag = 0,
311 };
312 u8 network_packet;
313 int snr;
314
315 if ((unlikely(rx_stats->phy_count > 20))) {
316 IWL_DEBUG_DROP
317 ("dsp size out of range [0,20]: "
318 "%d/n", rx_stats->phy_count);
319 return;
320 }
321
322 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
323 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
324 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
325 return;
326 }
327
328 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
329 iwl3945_handle_data_packet(priv, 1, rxb, &stats, phy_flags);
330 return;
331 }
332
333 /* Convert 3945's rssi indicator to dBm */
334 stats.ssi = rx_stats->rssi - IWL_RSSI_OFFSET;
335
336 /* Set default noise value to -127 */
337 if (priv->last_rx_noise == 0)
338 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
339
340 /* 3945 provides noise info for OFDM frames only.
341 * sig_avg and noise_diff are measured by the 3945's digital signal
342 * processor (DSP), and indicate linear levels of signal level and
343 * distortion/noise within the packet preamble after
344 * automatic gain control (AGC). sig_avg should stay fairly
345 * constant if the radio's AGC is working well.
346 * Since these values are linear (not dB or dBm), linear
347 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
348 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
349 * to obtain noise level in dBm.
350 * Calculate stats.signal (quality indicator in %) based on SNR. */
351 if (rx_stats_noise_diff) {
352 snr = rx_stats_sig_avg / rx_stats_noise_diff;
353 stats.noise = stats.ssi - iwl_calc_db_from_ratio(snr);
354 stats.signal = iwl_calc_sig_qual(stats.ssi, stats.noise);
355
356 /* If noise info not available, calculate signal quality indicator (%)
357 * using just the dBm signal level. */
358 } else {
359 stats.noise = priv->last_rx_noise;
360 stats.signal = iwl_calc_sig_qual(stats.ssi, 0);
361 }
362
363
364 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
365 stats.ssi, stats.noise, stats.signal,
366 rx_stats_sig_avg, rx_stats_noise_diff);
367
368 stats.freq = ieee80211chan2mhz(stats.channel);
369
370 /* can be covered by iwl_report_frame() in most cases */
371/* IWL_DEBUG_RX("RX status: 0x%08X\n", rx_end->status); */
372
373 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
374
375 network_packet = iwl_is_network_packet(priv, header);
376
377#ifdef CONFIG_IWLWIFI_DEBUG
378 if (iwl_debug_level & IWL_DL_STATS && net_ratelimit())
379 IWL_DEBUG_STATS
380 ("[%c] %d RSSI: %d Signal: %u, Noise: %u, Rate: %u\n",
381 network_packet ? '*' : ' ',
382 stats.channel, stats.ssi, stats.ssi,
383 stats.ssi, stats.rate);
384
385 if (iwl_debug_level & (IWL_DL_RX))
386 /* Set "1" to report good data frames in groups of 100 */
387 iwl_report_frame(priv, pkt, header, 1);
388#endif
389
390 if (network_packet) {
391 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
392 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
393 priv->last_rx_rssi = stats.ssi;
394 priv->last_rx_noise = stats.noise;
395 }
396
397 switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) {
398 case IEEE80211_FTYPE_MGMT:
399 switch (le16_to_cpu(header->frame_control) &
400 IEEE80211_FCTL_STYPE) {
401 case IEEE80211_STYPE_PROBE_RESP:
402 case IEEE80211_STYPE_BEACON:{
403 /* If this is a beacon or probe response for
404 * our network then cache the beacon
405 * timestamp */
406 if ((((priv->iw_mode == IEEE80211_IF_TYPE_STA)
407 && !compare_ether_addr(header->addr2,
408 priv->bssid)) ||
409 ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
410 && !compare_ether_addr(header->addr3,
411 priv->bssid)))) {
412 struct ieee80211_mgmt *mgmt =
413 (struct ieee80211_mgmt *)header;
414 __le32 *pos;
415 pos =
416 (__le32 *) & mgmt->u.beacon.
417 timestamp;
418 priv->timestamp0 = le32_to_cpu(pos[0]);
419 priv->timestamp1 = le32_to_cpu(pos[1]);
420 priv->beacon_int = le16_to_cpu(
421 mgmt->u.beacon.beacon_int);
422 if (priv->call_post_assoc_from_beacon &&
423 (priv->iw_mode ==
424 IEEE80211_IF_TYPE_STA))
425 queue_work(priv->workqueue,
426 &priv->post_associate.work);
427
428 priv->call_post_assoc_from_beacon = 0;
429 }
430
431 break;
432 }
433
434 case IEEE80211_STYPE_ACTION:
435 /* TODO: Parse 802.11h frames for CSA... */
436 break;
437
438 /*
439 * TODO: There is no callback function from upper
440 * stack to inform us when associated status. this
441 * work around to sniff assoc_resp management frame
442 * and finish the association process.
443 */
444 case IEEE80211_STYPE_ASSOC_RESP:
445 case IEEE80211_STYPE_REASSOC_RESP:{
446 struct ieee80211_mgmt *mgnt =
447 (struct ieee80211_mgmt *)header;
448 priv->assoc_id = (~((1 << 15) | (1 << 14)) &
449 le16_to_cpu(mgnt->u.
450 assoc_resp.aid));
451 priv->assoc_capability =
452 le16_to_cpu(mgnt->u.assoc_resp.capab_info);
453 if (priv->beacon_int)
454 queue_work(priv->workqueue,
455 &priv->post_associate.work);
456 else
457 priv->call_post_assoc_from_beacon = 1;
458 break;
459 }
460
461 case IEEE80211_STYPE_PROBE_REQ:{
0795af57
JP		 462 DECLARE_MAC_BUF(mac1);
463 DECLARE_MAC_BUF(mac2);
464 DECLARE_MAC_BUF(mac3);
b481de9c
ZY		 465 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
466 IWL_DEBUG_DROP
0795af57
JP		 467 ("Dropping (non network): %s"
468 ", %s, %s\n",
469 print_mac(mac1, header->addr1),
470 print_mac(mac2, header->addr2),
471 print_mac(mac3, header->addr3));
b481de9c
ZY		 472 return;
473 }
474 }
475
476 iwl3945_handle_data_packet(priv, 0, rxb, &stats, phy_flags);
477 break;
478
479 case IEEE80211_FTYPE_CTL:
480 break;
481
0795af57
JP		 482 case IEEE80211_FTYPE_DATA: {
483 DECLARE_MAC_BUF(mac1);
484 DECLARE_MAC_BUF(mac2);
485 DECLARE_MAC_BUF(mac3);
486
b481de9c 487 if (unlikely(is_duplicate_packet(priv, header)))
0795af57
JP		 488 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
489 print_mac(mac1, header->addr1),
490 print_mac(mac2, header->addr2),
491 print_mac(mac3, header->addr3));
b481de9c
ZY		 492 else
493 iwl3945_handle_data_packet(priv, 1, rxb, &stats,
494 phy_flags);
495 break;
496 }
0795af57 497 }
b481de9c
ZY		 498}
499
500int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
501 dma_addr_t addr, u16 len)
502{
503 int count;
504 u32 pad;
505 struct iwl_tfd_frame *tfd = (struct iwl_tfd_frame *)ptr;
506
507 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
508 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
509
510 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
511 IWL_ERROR("Error can not send more than %d chunks\n",
512 NUM_TFD_CHUNKS);
513 return -EINVAL;
514 }
515
516 tfd->pa[count].addr = cpu_to_le32(addr);
517 tfd->pa[count].len = cpu_to_le32(len);
518
519 count++;
520
521 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
522 TFD_CTL_PAD_SET(pad));
523
524 return 0;
525}
526
527/**
fc4b6853 528 * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 529 *
530 * Does NOT advance any indexes
531 */
532int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
533{
534 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
fc4b6853 535 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 536 struct pci_dev *dev = priv->pci_dev;
537 int i;
538 int counter;
539
540 /* classify bd */
541 if (txq->q.id == IWL_CMD_QUEUE_NUM)
542 /* nothing to cleanup after for host commands */
543 return 0;
544
545 /* sanity check */
546 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
547 if (counter > NUM_TFD_CHUNKS) {
548 IWL_ERROR("Too many chunks: %i\n", counter);
549 /* @todo issue fatal error, it is quite serious situation */
550 return 0;
551 }
552
553 /* unmap chunks if any */
554
555 for (i = 1; i < counter; i++) {
556 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
557 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 558 if (txq->txb[txq->q.read_ptr].skb[0]) {
559 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
560 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 561 /* Can be called from interrupt context */
562 dev_kfree_skb_any(skb);
fc4b6853 563 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 564 }
565 }
566 }
567 return 0;
568}
569
570u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *addr)
571{
572 int i;
573 int ret = IWL_INVALID_STATION;
574 unsigned long flags;
0795af57 575 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 576
577 spin_lock_irqsave(&priv->sta_lock, flags);
578 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
579 if ((priv->stations[i].used) &&
580 (!compare_ether_addr
581 (priv->stations[i].sta.sta.addr, addr))) {
582 ret = i;
583 goto out;
584 }
585
0795af57
JP		 586 IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
587 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 588 out:
589 spin_unlock_irqrestore(&priv->sta_lock, flags);
590 return ret;
591}
592
593/**
594 * iwl_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
595 *
596*/
597void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv,
598 struct iwl_cmd *cmd,
599 struct ieee80211_tx_control *ctrl,
600 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
601{
602 unsigned long flags;
603 u16 rate_index = min(ctrl->tx_rate & 0xffff, IWL_RATE_COUNT - 1);
604 u16 rate_mask;
605 int rate;
606 u8 rts_retry_limit;
607 u8 data_retry_limit;
608 __le32 tx_flags;
609 u16 fc = le16_to_cpu(hdr->frame_control);
610
611 rate = iwl_rates[rate_index].plcp;
612 tx_flags = cmd->cmd.tx.tx_flags;
613
614 /* We need to figure out how to get the sta->supp_rates while
615 * in this running context; perhaps encoding into ctrl->tx_rate? */
616 rate_mask = IWL_RATES_MASK;
617
618 spin_lock_irqsave(&priv->sta_lock, flags);
619
620 priv->stations[sta_id].current_rate.rate_n_flags = rate;
621
622 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
623 (sta_id != IWL3945_BROADCAST_ID) &&
624 (sta_id != IWL_MULTICAST_ID))
625 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
626
627 spin_unlock_irqrestore(&priv->sta_lock, flags);
628
629 if (tx_id >= IWL_CMD_QUEUE_NUM)
630 rts_retry_limit = 3;
631 else
632 rts_retry_limit = 7;
633
634 if (ieee80211_is_probe_response(fc)) {
635 data_retry_limit = 3;
636 if (data_retry_limit < rts_retry_limit)
637 rts_retry_limit = data_retry_limit;
638 } else
639 data_retry_limit = IWL_DEFAULT_TX_RETRY;
640
641 if (priv->data_retry_limit != -1)
642 data_retry_limit = priv->data_retry_limit;
643
644 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
645 switch (fc & IEEE80211_FCTL_STYPE) {
646 case IEEE80211_STYPE_AUTH:
647 case IEEE80211_STYPE_DEAUTH:
648 case IEEE80211_STYPE_ASSOC_REQ:
649 case IEEE80211_STYPE_REASSOC_REQ:
650 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
651 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
652 tx_flags |= TX_CMD_FLG_CTS_MSK;
653 }
654 break;
655 default:
656 break;
657 }
658 }
659
660 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
661 cmd->cmd.tx.data_retry_limit = data_retry_limit;
662 cmd->cmd.tx.rate = rate;
663 cmd->cmd.tx.tx_flags = tx_flags;
664
665 /* OFDM */
14577f23
MA		 666 cmd->cmd.tx.supp_rates[0] =
667 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 668
669 /* CCK */
14577f23 670 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 671
672 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
673 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
674 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
675 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
676}
677
678u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
679{
680 unsigned long flags_spin;
681 struct iwl_station_entry *station;
682
683 if (sta_id == IWL_INVALID_STATION)
684 return IWL_INVALID_STATION;
685
686 spin_lock_irqsave(&priv->sta_lock, flags_spin);
687 station = &priv->stations[sta_id];
688
689 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
690 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
691 station->current_rate.rate_n_flags = tx_rate;
692 station->sta.mode = STA_CONTROL_MODIFY_MSK;
693
694 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
695
696 iwl_send_add_station(priv, &station->sta, flags);
697 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
698 sta_id, tx_rate);
699 return sta_id;
700}
701
702void iwl_hw_card_show_info(struct iwl_priv *priv)
703{
704 IWL_DEBUG_INFO("3945ABG HW Version %u.%u.%u\n",
705 ((priv->eeprom.board_revision >> 8) & 0x0F),
706 ((priv->eeprom.board_revision >> 8) >> 4),
707 (priv->eeprom.board_revision & 0x00FF));
708
709 IWL_DEBUG_INFO("3945ABG PBA Number %.*s\n",
710 (int)sizeof(priv->eeprom.board_pba_number),
711 priv->eeprom.board_pba_number);
712
713 IWL_DEBUG_INFO("EEPROM_ANTENNA_SWITCH_TYPE is 0x%02X\n",
714 priv->eeprom.antenna_switch_type);
715}
716
717static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
718{
719 int rc;
720 unsigned long flags;
721
722 spin_lock_irqsave(&priv->lock, flags);
ac17a947 723 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 724 if (rc) {
725 spin_unlock_irqrestore(&priv->lock, flags);
726 return rc;
727 }
728
729 if (!pwr_max) {
730 u32 val;
731
732 rc = pci_read_config_dword(priv->pci_dev,
733 PCI_POWER_SOURCE, &val);
734 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
d8609652 735 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 736 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
737 ~APMG_PS_CTRL_MSK_PWR_SRC);
ac17a947 738 iwl_release_nic_access(priv);
b481de9c
ZY		 739
740 iwl_poll_bit(priv, CSR_GPIO_IN,
741 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
742 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
743 } else
ac17a947 744 iwl_release_nic_access(priv);
b481de9c 745 } else {
d8609652 746 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 747 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
748 ~APMG_PS_CTRL_MSK_PWR_SRC);
749
ac17a947 750 iwl_release_nic_access(priv);
b481de9c
ZY		 751 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
752 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
753 }
754 spin_unlock_irqrestore(&priv->lock, flags);
755
756 return rc;
757}
758
759static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
760{
761 int rc;
762 unsigned long flags;
763
764 spin_lock_irqsave(&priv->lock, flags);
ac17a947 765 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 766 if (rc) {
767 spin_unlock_irqrestore(&priv->lock, flags);
768 return rc;
769 }
770
ac17a947
TW		 771 iwl_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
772 iwl_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
b481de9c
ZY		 773 priv->hw_setting.shared_phys +
774 offsetof(struct iwl_shared, rx_read_ptr[0]));
ac17a947
TW		 775 iwl_write_direct32(priv, FH_RCSR_WPTR(0), 0);
776 iwl_write_direct32(priv, FH_RCSR_CONFIG(0),
b481de9c
ZY		 777 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
778 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
779 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
780 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
781 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
782 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
783 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
784 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
785
786 /* fake read to flush all prev I/O */
ac17a947 787 iwl_read_direct32(priv, FH_RSSR_CTRL);
b481de9c 788
ac17a947 789 iwl_release_nic_access(priv);
b481de9c
ZY		 790 spin_unlock_irqrestore(&priv->lock, flags);
791
792 return 0;
793}
794
795static int iwl3945_tx_reset(struct iwl_priv *priv)
796{
797 int rc;
798 unsigned long flags;
799
800 spin_lock_irqsave(&priv->lock, flags);
ac17a947 801 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 802 if (rc) {
803 spin_unlock_irqrestore(&priv->lock, flags);
804 return rc;
805 }
806
807 /* bypass mode */
70883109 808 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 809
810 /* RA 0 is active */
70883109 811 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 812
813 /* all 6 fifo are active */
70883109 814 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 815
70883109
EG		 816 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
817 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
818 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
819 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 820
ac17a947 821 iwl_write_direct32(priv, FH_TSSR_CBB_BASE,
b481de9c
ZY		 822 priv->hw_setting.shared_phys);
823
ac17a947 824 iwl_write_direct32(priv, FH_TSSR_MSG_CONFIG,
b481de9c
ZY		 825 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
826 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
827 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
828 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
829 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
830 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
831 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
832
ac17a947 833 iwl_release_nic_access(priv);
b481de9c
ZY		 834 spin_unlock_irqrestore(&priv->lock, flags);
835
836 return 0;
837}
838
839/**
840 * iwl3945_txq_ctx_reset - Reset TX queue context
841 *
842 * Destroys all DMA structures and initialize them again
843 */
844static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
845{
846 int rc;
847 int txq_id, slots_num;
848
849 iwl_hw_txq_ctx_free(priv);
850
851 /* Tx CMD queue */
852 rc = iwl3945_tx_reset(priv);
853 if (rc)
854 goto error;
855
856 /* Tx queue(s) */
857 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
858 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
859 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
860 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
861 txq_id);
862 if (rc) {
863 IWL_ERROR("Tx %d queue init failed\n", txq_id);
864 goto error;
865 }
866 }
867
868 return rc;
869
870 error:
871 iwl_hw_txq_ctx_free(priv);
872 return rc;
873}
874
875int iwl_hw_nic_init(struct iwl_priv *priv)
876{
877 u8 rev_id;
878 int rc;
879 unsigned long flags;
880 struct iwl_rx_queue *rxq = &priv->rxq;
881
882 iwl_power_init_handle(priv);
883
884 spin_lock_irqsave(&priv->lock, flags);
885 iwl_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24));
886 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
887 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
888
889 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
890 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
891 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
892 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
893 if (rc < 0) {
894 spin_unlock_irqrestore(&priv->lock, flags);
895 IWL_DEBUG_INFO("Failed to init the card\n");
896 return rc;
897 }
898
ac17a947 899 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 900 if (rc) {
901 spin_unlock_irqrestore(&priv->lock, flags);
902 return rc;
903 }
d8609652 904 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 905 APMG_CLK_VAL_DMA_CLK_RQT |
906 APMG_CLK_VAL_BSM_CLK_RQT);
907 udelay(20);
d8609652 908 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c 909 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
ac17a947 910 iwl_release_nic_access(priv);
b481de9c
ZY		 911 spin_unlock_irqrestore(&priv->lock, flags);
912
913 /* Determine HW type */
914 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
915 if (rc)
916 return rc;
917 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
918
919 iwl3945_nic_set_pwr_src(priv, 1);
920 spin_lock_irqsave(&priv->lock, flags);
921
922 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
923 IWL_DEBUG_INFO("RTP type \n");
924 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
925 IWL_DEBUG_INFO("ALM-MB type\n");
926 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
927 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB);
928 } else {
929 IWL_DEBUG_INFO("ALM-MM type\n");
930 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
931 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM);
932 }
933
934 spin_unlock_irqrestore(&priv->lock, flags);
935
936 /* Initialize the EEPROM */
937 rc = iwl_eeprom_init(priv);
938 if (rc)
939 return rc;
940
941 spin_lock_irqsave(&priv->lock, flags);
942 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
943 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
944 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
945 CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC);
946 } else
947 IWL_DEBUG_INFO("SKU OP mode is basic\n");
948
949 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
950 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
951 priv->eeprom.board_revision);
952 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
953 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
954 } else {
955 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
956 priv->eeprom.board_revision);
957 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
958 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
959 }
960
961 if (priv->eeprom.almgor_m_version <= 1) {
962 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
963 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
964 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
965 priv->eeprom.almgor_m_version);
966 } else {
967 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
968 priv->eeprom.almgor_m_version);
969 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
970 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
971 }
972 spin_unlock_irqrestore(&priv->lock, flags);
973
974 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
975 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
976
977 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
978 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
979
980 /* Allocate the RX queue, or reset if it is already allocated */
981 if (!rxq->bd) {
982 rc = iwl_rx_queue_alloc(priv);
983 if (rc) {
984 IWL_ERROR("Unable to initialize Rx queue\n");
985 return -ENOMEM;
986 }
987 } else
988 iwl_rx_queue_reset(priv, rxq);
989
990 iwl_rx_replenish(priv);
991
992 iwl3945_rx_init(priv, rxq);
993
994 spin_lock_irqsave(&priv->lock, flags);
995
996 /* Look at using this instead:
997 rxq->need_update = 1;
998 iwl_rx_queue_update_write_ptr(priv, rxq);
999 */
1000
ac17a947 1001 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1002 if (rc) {
1003 spin_unlock_irqrestore(&priv->lock, flags);
1004 return rc;
1005 }
ac17a947
TW		 1006 iwl_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1007 iwl_release_nic_access(priv);
b481de9c
ZY		 1008
1009 spin_unlock_irqrestore(&priv->lock, flags);
1010
1011 rc = iwl3945_txq_ctx_reset(priv);
1012 if (rc)
1013 return rc;
1014
1015 set_bit(STATUS_INIT, &priv->status);
1016
1017 return 0;
1018}
1019
1020/**
1021 * iwl_hw_txq_ctx_free - Free TXQ Context
1022 *
1023 * Destroy all TX DMA queues and structures
1024 */
1025void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
1026{
1027 int txq_id;
1028
1029 /* Tx queues */
1030 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1031 iwl_tx_queue_free(priv, &priv->txq[txq_id]);
1032}
1033
1034void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
1035{
1036 int queue;
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&priv->lock, flags);
ac17a947 1040 if (iwl_grab_nic_access(priv)) {
b481de9c
ZY		 1041 spin_unlock_irqrestore(&priv->lock, flags);
1042 iwl_hw_txq_ctx_free(priv);
1043 return;
1044 }
1045
1046 /* stop SCD */
70883109 1047 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1048
1049 /* reset TFD queues */
1050 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
ac17a947
TW		 1051 iwl_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1052 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
b481de9c
ZY		 1053 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1054 1000);
1055 }
1056
ac17a947 1057 iwl_release_nic_access(priv);
b481de9c
ZY		 1058 spin_unlock_irqrestore(&priv->lock, flags);
1059
1060 iwl_hw_txq_ctx_free(priv);
1061}
1062
1063int iwl_hw_nic_stop_master(struct iwl_priv *priv)
1064{
1065 int rc = 0;
1066 u32 reg_val;
1067 unsigned long flags;
1068
1069 spin_lock_irqsave(&priv->lock, flags);
1070
1071 /* set stop master bit */
1072 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1073
1074 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
1075
1076 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1077 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1078 IWL_DEBUG_INFO("Card in power save, master is already "
1079 "stopped\n");
1080 else {
1081 rc = iwl_poll_bit(priv, CSR_RESET,
1082 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1083 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1084 if (rc < 0) {
1085 spin_unlock_irqrestore(&priv->lock, flags);
1086 return rc;
1087 }
1088 }
1089
1090 spin_unlock_irqrestore(&priv->lock, flags);
1091 IWL_DEBUG_INFO("stop master\n");
1092
1093 return rc;
1094}
1095
1096int iwl_hw_nic_reset(struct iwl_priv *priv)
1097{
1098 int rc;
1099 unsigned long flags;
1100
1101 iwl_hw_nic_stop_master(priv);
1102
1103 spin_lock_irqsave(&priv->lock, flags);
1104
1105 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1106
1107 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
1108 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1109 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1110
ac17a947 1111 rc = iwl_grab_nic_access(priv);
b481de9c 1112 if (!rc) {
d8609652 1113 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1114 APMG_CLK_VAL_BSM_CLK_RQT);
1115
1116 udelay(10);
1117
1118 iwl_set_bit(priv, CSR_GP_CNTRL,
1119 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1120
d8609652
TW		 1121 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1122 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1123 0xFFFFFFFF);
1124
1125 /* enable DMA */
d8609652 1126 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1127 APMG_CLK_VAL_DMA_CLK_RQT |
1128 APMG_CLK_VAL_BSM_CLK_RQT);
1129 udelay(10);
1130
d8609652 1131 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1132 APMG_PS_CTRL_VAL_RESET_REQ);
1133 udelay(5);
d8609652 1134 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1135 APMG_PS_CTRL_VAL_RESET_REQ);
ac17a947 1136 iwl_release_nic_access(priv);
b481de9c
ZY		 1137 }
1138
1139 /* Clear the 'host command active' bit... */
1140 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1141
1142 wake_up_interruptible(&priv->wait_command_queue);
1143 spin_unlock_irqrestore(&priv->lock, flags);
1144
1145 return rc;
1146}
1147
1148/**
bbc5807b
IS		 1149 * iwl_hw_reg_adjust_power_by_temp
1150 * return index delta into power gain settings table
1151*/
b481de9c
ZY		 1152static int iwl_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1153{
1154 return (new_reading - old_reading) * (-11) / 100;
1155}
1156
1157/**
1158 * iwl_hw_reg_temp_out_of_range - Keep temperature in sane range
1159 */
1160static inline int iwl_hw_reg_temp_out_of_range(int temperature)
1161{
1162 return (((temperature < -260) || (temperature > 25)) ? 1 : 0);
1163}
1164
1165int iwl_hw_get_temperature(struct iwl_priv *priv)
1166{
1167 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1168}
1169
1170/**
bbc5807b
IS		 1171 * iwl_hw_reg_txpower_get_temperature
1172 * get the current temperature by reading from NIC
1173*/
b481de9c
ZY		 1174static int iwl_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1175{
1176 int temperature;
1177
1178 temperature = iwl_hw_get_temperature(priv);
1179
1180 /* driver's okay range is -260 to +25.
1181 * human readable okay range is 0 to +285 */
1182 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1183
1184 /* handle insane temp reading */
1185 if (iwl_hw_reg_temp_out_of_range(temperature)) {
1186 IWL_ERROR("Error bad temperature value %d\n", temperature);
1187
1188 /* if really really hot(?),
1189 * substitute the 3rd band/group's temp measured at factory */
1190 if (priv->last_temperature > 100)
1191 temperature = priv->eeprom.groups[2].temperature;
1192 else /* else use most recent "sane" value from driver */
1193 temperature = priv->last_temperature;
1194 }
1195
1196 return temperature; /* raw, not "human readable" */
1197}
1198
1199/* Adjust Txpower only if temperature variance is greater than threshold.
1200 *
1201 * Both are lower than older versions' 9 degrees */
1202#define IWL_TEMPERATURE_LIMIT_TIMER 6
1203
1204/**
1205 * is_temp_calib_needed - determines if new calibration is needed
1206 *
1207 * records new temperature in tx_mgr->temperature.
1208 * replaces tx_mgr->last_temperature *only* if calib needed
1209 * (assumes caller will actually do the calibration!). */
1210static int is_temp_calib_needed(struct iwl_priv *priv)
1211{
1212 int temp_diff;
1213
1214 priv->temperature = iwl_hw_reg_txpower_get_temperature(priv);
1215 temp_diff = priv->temperature - priv->last_temperature;
1216
1217 /* get absolute value */
1218 if (temp_diff < 0) {
1219 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1220 temp_diff = -temp_diff;
1221 } else if (temp_diff == 0)
1222 IWL_DEBUG_POWER("Same temp,\n");
1223 else
1224 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1225
1226 /* if we don't need calibration, *don't* update last_temperature */
1227 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1228 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1229 return 0;
1230 }
1231
1232 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1233
1234 /* assume that caller will actually do calib ...
1235 * update the "last temperature" value */
1236 priv->last_temperature = priv->temperature;
1237 return 1;
1238}
1239
1240#define IWL_MAX_GAIN_ENTRIES 78
1241#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1242#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1243
1244/* radio and DSP power table, each step is 1/2 dB.
1245 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1246static struct iwl_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1247 {
1248 {251, 127}, /* 2.4 GHz, highest power */
1249 {251, 127},
1250 {251, 127},
1251 {251, 127},
1252 {251, 125},
1253 {251, 110},
1254 {251, 105},
1255 {251, 98},
1256 {187, 125},
1257 {187, 115},
1258 {187, 108},
1259 {187, 99},
1260 {243, 119},
1261 {243, 111},
1262 {243, 105},
1263 {243, 97},
1264 {243, 92},
1265 {211, 106},
1266 {211, 100},
1267 {179, 120},
1268 {179, 113},
1269 {179, 107},
1270 {147, 125},
1271 {147, 119},
1272 {147, 112},
1273 {147, 106},
1274 {147, 101},
1275 {147, 97},
1276 {147, 91},
1277 {115, 107},
1278 {235, 121},
1279 {235, 115},
1280 {235, 109},
1281 {203, 127},
1282 {203, 121},
1283 {203, 115},
1284 {203, 108},
1285 {203, 102},
1286 {203, 96},
1287 {203, 92},
1288 {171, 110},
1289 {171, 104},
1290 {171, 98},
1291 {139, 116},
1292 {227, 125},
1293 {227, 119},
1294 {227, 113},
1295 {227, 107},
1296 {227, 101},
1297 {227, 96},
1298 {195, 113},
1299 {195, 106},
1300 {195, 102},
1301 {195, 95},
1302 {163, 113},
1303 {163, 106},
1304 {163, 102},
1305 {163, 95},
1306 {131, 113},
1307 {131, 106},
1308 {131, 102},
1309 {131, 95},
1310 {99, 113},
1311 {99, 106},
1312 {99, 102},
1313 {99, 95},
1314 {67, 113},
1315 {67, 106},
1316 {67, 102},
1317 {67, 95},
1318 {35, 113},
1319 {35, 106},
1320 {35, 102},
1321 {35, 95},
1322 {3, 113},
1323 {3, 106},
1324 {3, 102},
1325 {3, 95} }, /* 2.4 GHz, lowest power */
1326 {
1327 {251, 127}, /* 5.x GHz, highest power */
1328 {251, 120},
1329 {251, 114},
1330 {219, 119},
1331 {219, 101},
1332 {187, 113},
1333 {187, 102},
1334 {155, 114},
1335 {155, 103},
1336 {123, 117},
1337 {123, 107},
1338 {123, 99},
1339 {123, 92},
1340 {91, 108},
1341 {59, 125},
1342 {59, 118},
1343 {59, 109},
1344 {59, 102},
1345 {59, 96},
1346 {59, 90},
1347 {27, 104},
1348 {27, 98},
1349 {27, 92},
1350 {115, 118},
1351 {115, 111},
1352 {115, 104},
1353 {83, 126},
1354 {83, 121},
1355 {83, 113},
1356 {83, 105},
1357 {83, 99},
1358 {51, 118},
1359 {51, 111},
1360 {51, 104},
1361 {51, 98},
1362 {19, 116},
1363 {19, 109},
1364 {19, 102},
1365 {19, 98},
1366 {19, 93},
1367 {171, 113},
1368 {171, 107},
1369 {171, 99},
1370 {139, 120},
1371 {139, 113},
1372 {139, 107},
1373 {139, 99},
1374 {107, 120},
1375 {107, 113},
1376 {107, 107},
1377 {107, 99},
1378 {75, 120},
1379 {75, 113},
1380 {75, 107},
1381 {75, 99},
1382 {43, 120},
1383 {43, 113},
1384 {43, 107},
1385 {43, 99},
1386 {11, 120},
1387 {11, 113},
1388 {11, 107},
1389 {11, 99},
1390 {131, 107},
1391 {131, 99},
1392 {99, 120},
1393 {99, 113},
1394 {99, 107},
1395 {99, 99},
1396 {67, 120},
1397 {67, 113},
1398 {67, 107},
1399 {67, 99},
1400 {35, 120},
1401 {35, 113},
1402 {35, 107},
1403 {35, 99},
1404 {3, 120} } /* 5.x GHz, lowest power */
1405};
1406
1407static inline u8 iwl_hw_reg_fix_power_index(int index)
1408{
1409 if (index < 0)
1410 return 0;
1411 if (index >= IWL_MAX_GAIN_ENTRIES)
1412 return IWL_MAX_GAIN_ENTRIES - 1;
1413 return (u8) index;
1414}
1415
1416/* Kick off thermal recalibration check every 60 seconds */
1417#define REG_RECALIB_PERIOD (60)
1418
1419/**
1420 * iwl_hw_reg_set_scan_power - Set Tx power for scan probe requests
1421 *
1422 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1423 * or 6 Mbit (OFDM) rates.
1424 */
1425static void iwl_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1426 s32 rate_index, const s8 *clip_pwrs,
1427 struct iwl_channel_info *ch_info,
1428 int band_index)
1429{
1430 struct iwl_scan_power_info *scan_power_info;
1431 s8 power;
1432 u8 power_index;
1433
1434 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1435
1436 /* use this channel group's 6Mbit clipping/saturation pwr,
1437 * but cap at regulatory scan power restriction (set during init
1438 * based on eeprom channel data) for this channel. */
14577f23 1439 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1440
1441 /* further limit to user's max power preference.
1442 * FIXME: Other spectrum management power limitations do not
1443 * seem to apply?? */
1444 power = min(power, priv->user_txpower_limit);
1445 scan_power_info->requested_power = power;
1446
1447 /* find difference between new scan *power* and current "normal"
1448 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1449 * current "normal" temperature-compensated Tx power *index* for
1450 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1451 * *index*. */
1452 power_index = ch_info->power_info[rate_index].power_table_index
1453 - (power - ch_info->power_info
14577f23 1454 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1455
1456 /* store reference index that we use when adjusting *all* scan
1457 * powers. So we can accommodate user (all channel) or spectrum
1458 * management (single channel) power changes "between" temperature
1459 * feedback compensation procedures.
1460 * don't force fit this reference index into gain table; it may be a
1461 * negative number. This will help avoid errors when we're at
1462 * the lower bounds (highest gains, for warmest temperatures)
1463 * of the table. */
1464
1465 /* don't exceed table bounds for "real" setting */
1466 power_index = iwl_hw_reg_fix_power_index(power_index);
1467
1468 scan_power_info->power_table_index = power_index;
1469 scan_power_info->tpc.tx_gain =
1470 power_gain_table[band_index][power_index].tx_gain;
1471 scan_power_info->tpc.dsp_atten =
1472 power_gain_table[band_index][power_index].dsp_atten;
1473}
1474
1475/**
1476 * iwl_hw_reg_send_txpower - fill in Tx Power command with gain settings
1477 *
1478 * Configures power settings for all rates for the current channel,
1479 * using values from channel info struct, and send to NIC
1480 */
1481int iwl_hw_reg_send_txpower(struct iwl_priv *priv)
1482{
14577f23 1483 int rate_idx, i;
b481de9c
ZY		 1484 const struct iwl_channel_info *ch_info = NULL;
1485 struct iwl_txpowertable_cmd txpower = {
1486 .channel = priv->active_rxon.channel,
1487 };
1488
1489 txpower.band = (priv->phymode == MODE_IEEE80211A) ? 0 : 1;
1490 ch_info = iwl_get_channel_info(priv,
1491 priv->phymode,
1492 le16_to_cpu(priv->active_rxon.channel));
1493 if (!ch_info) {
1494 IWL_ERROR
1495 ("Failed to get channel info for channel %d [%d]\n",
1496 le16_to_cpu(priv->active_rxon.channel), priv->phymode);
1497 return -EINVAL;
1498 }
1499
1500 if (!is_channel_valid(ch_info)) {
1501 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1502 "non-Tx channel.\n");
1503 return 0;
1504 }
1505
1506 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1507 /* Fill OFDM rate */
1508 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1509 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1510
1511 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1512 txpower.power[i].rate = iwl_rates[rate_idx].plcp;
b481de9c
ZY		 1513
1514 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1515 le16_to_cpu(txpower.channel),
1516 txpower.band,
14577f23
MA		 1517 txpower.power[i].tpc.tx_gain,
1518 txpower.power[i].tpc.dsp_atten,
1519 txpower.power[i].rate);
1520 }
1521 /* Fill CCK rates */
1522 for (rate_idx = IWL_FIRST_CCK_RATE;
1523 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1524 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1525 txpower.power[i].rate = iwl_rates[rate_idx].plcp;
1526
1527 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1528 le16_to_cpu(txpower.channel),
1529 txpower.band,
1530 txpower.power[i].tpc.tx_gain,
1531 txpower.power[i].tpc.dsp_atten,
1532 txpower.power[i].rate);
b481de9c
ZY		 1533 }
1534
1535 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
14577f23 1536 sizeof(struct iwl_txpowertable_cmd), &txpower);
b481de9c
ZY		 1537
1538}
1539
1540/**
1541 * iwl_hw_reg_set_new_power - Configures power tables at new levels
1542 * @ch_info: Channel to update. Uses power_info.requested_power.
1543 *
1544 * Replace requested_power and base_power_index ch_info fields for
1545 * one channel.
1546 *
1547 * Called if user or spectrum management changes power preferences.
1548 * Takes into account h/w and modulation limitations (clip power).
1549 *
1550 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1551 *
1552 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1553 * properly fill out the scan powers, and actual h/w gain settings,
1554 * and send changes to NIC
1555 */
1556static int iwl_hw_reg_set_new_power(struct iwl_priv *priv,
1557 struct iwl_channel_info *ch_info)
1558{
1559 struct iwl_channel_power_info *power_info;
1560 int power_changed = 0;
1561 int i;
1562 const s8 *clip_pwrs;
1563 int power;
1564
1565 /* Get this chnlgrp's rate-to-max/clip-powers table */
1566 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1567
1568 /* Get this channel's rate-to-current-power settings table */
1569 power_info = ch_info->power_info;
1570
1571 /* update OFDM Txpower settings */
14577f23 1572 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1573 i++, ++power_info) {
1574 int delta_idx;
1575
1576 /* limit new power to be no more than h/w capability */
1577 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1578 if (power == power_info->requested_power)
1579 continue;
1580
1581 /* find difference between old and new requested powers,
1582 * update base (non-temp-compensated) power index */
1583 delta_idx = (power - power_info->requested_power) * 2;
1584 power_info->base_power_index -= delta_idx;
1585
1586 /* save new requested power value */
1587 power_info->requested_power = power;
1588
1589 power_changed = 1;
1590 }
1591
1592 /* update CCK Txpower settings, based on OFDM 12M setting ...
1593 * ... all CCK power settings for a given channel are the *same*. */
1594 if (power_changed) {
1595 power =
14577f23 1596 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1597 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1598
1599 /* do all CCK rates' iwl_channel_power_info structures */
14577f23 1600 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1601 power_info->requested_power = power;
1602 power_info->base_power_index =
14577f23 1603 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1604 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1605 ++power_info;
1606 }
1607 }
1608
1609 return 0;
1610}
1611
1612/**
1613 * iwl_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1614 *
1615 * NOTE: Returned power limit may be less (but not more) than requested,
1616 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1617 * (no consideration for h/w clipping limitations).
1618 */
1619static int iwl_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1620{
1621 s8 max_power;
1622
1623#if 0
1624 /* if we're using TGd limits, use lower of TGd or EEPROM */
1625 if (ch_info->tgd_data.max_power != 0)
1626 max_power = min(ch_info->tgd_data.max_power,
1627 ch_info->eeprom.max_power_avg);
1628
1629 /* else just use EEPROM limits */
1630 else
1631#endif
1632 max_power = ch_info->eeprom.max_power_avg;
1633
1634 return min(max_power, ch_info->max_power_avg);
1635}
1636
1637/**
1638 * iwl_hw_reg_comp_txpower_temp - Compensate for temperature
1639 *
1640 * Compensate txpower settings of *all* channels for temperature.
1641 * This only accounts for the difference between current temperature
1642 * and the factory calibration temperatures, and bases the new settings
1643 * on the channel's base_power_index.
1644 *
1645 * If RxOn is "associated", this sends the new Txpower to NIC!
1646 */
1647static int iwl_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1648{
1649 struct iwl_channel_info *ch_info = NULL;
1650 int delta_index;
1651 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1652 u8 a_band;
1653 u8 rate_index;
1654 u8 scan_tbl_index;
1655 u8 i;
1656 int ref_temp;
1657 int temperature = priv->temperature;
1658
1659 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1660 for (i = 0; i < priv->channel_count; i++) {
1661 ch_info = &priv->channel_info[i];
1662 a_band = is_channel_a_band(ch_info);
1663
1664 /* Get this chnlgrp's factory calibration temperature */
1665 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1666 temperature;
1667
1668 /* get power index adjustment based on curr and factory
1669 * temps */
1670 delta_index = iwl_hw_reg_adjust_power_by_temp(temperature,
1671 ref_temp);
1672
1673 /* set tx power value for all rates, OFDM and CCK */
1674 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1675 rate_index++) {
1676 int power_idx =
1677 ch_info->power_info[rate_index].base_power_index;
1678
1679 /* temperature compensate */
1680 power_idx += delta_index;
1681
1682 /* stay within table range */
1683 power_idx = iwl_hw_reg_fix_power_index(power_idx);
1684 ch_info->power_info[rate_index].
1685 power_table_index = (u8) power_idx;
1686 ch_info->power_info[rate_index].tpc =
1687 power_gain_table[a_band][power_idx];
1688 }
1689
1690 /* Get this chnlgrp's rate-to-max/clip-powers table */
1691 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1692
1693 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1694 for (scan_tbl_index = 0;
1695 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1696 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1697 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
b481de9c
ZY		 1698 iwl_hw_reg_set_scan_power(priv, scan_tbl_index,
1699 actual_index, clip_pwrs,
1700 ch_info, a_band);
1701 }
1702 }
1703
1704 /* send Txpower command for current channel to ucode */
1705 return iwl_hw_reg_send_txpower(priv);
1706}
1707
1708int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1709{
1710 struct iwl_channel_info *ch_info;
1711 s8 max_power;
1712 u8 a_band;
1713 u8 i;
1714
1715 if (priv->user_txpower_limit == power) {
1716 IWL_DEBUG_POWER("Requested Tx power same as current "
1717 "limit: %ddBm.\n", power);
1718 return 0;
1719 }
1720
1721 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1722 priv->user_txpower_limit = power;
1723
1724 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1725
1726 for (i = 0; i < priv->channel_count; i++) {
1727 ch_info = &priv->channel_info[i];
1728 a_band = is_channel_a_band(ch_info);
1729
1730 /* find minimum power of all user and regulatory constraints
1731 * (does not consider h/w clipping limitations) */
1732 max_power = iwl_hw_reg_get_ch_txpower_limit(ch_info);
1733 max_power = min(power, max_power);
1734 if (max_power != ch_info->curr_txpow) {
1735 ch_info->curr_txpow = max_power;
1736
1737 /* this considers the h/w clipping limitations */
1738 iwl_hw_reg_set_new_power(priv, ch_info);
1739 }
1740 }
1741
1742 /* update txpower settings for all channels,
1743 * send to NIC if associated. */
1744 is_temp_calib_needed(priv);
1745 iwl_hw_reg_comp_txpower_temp(priv);
1746
1747 return 0;
1748}
1749
1750/* will add 3945 channel switch cmd handling later */
1751int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1752{
1753 return 0;
1754}
1755
1756/**
1757 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1758 *
1759 * -- reset periodic timer
1760 * -- see if temp has changed enough to warrant re-calibration ... if so:
1761 * -- correct coeffs for temp (can reset temp timer)
1762 * -- save this temp as "last",
1763 * -- send new set of gain settings to NIC
1764 * NOTE: This should continue working, even when we're not associated,
1765 * so we can keep our internal table of scan powers current. */
1766void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1767{
1768 /* This will kick in the "brute force"
1769 * iwl_hw_reg_comp_txpower_temp() below */
1770 if (!is_temp_calib_needed(priv))
1771 goto reschedule;
1772
1773 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1774 * This is based *only* on current temperature,
1775 * ignoring any previous power measurements */
1776 iwl_hw_reg_comp_txpower_temp(priv);
1777
1778 reschedule:
1779 queue_delayed_work(priv->workqueue,
1780 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1781}
1782
1783void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1784{
1785 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1786 thermal_periodic.work);
1787
1788 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1789 return;
1790
1791 mutex_lock(&priv->mutex);
1792 iwl3945_reg_txpower_periodic(priv);
1793 mutex_unlock(&priv->mutex);
1794}
1795
1796/**
1797 * iwl_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1798 * for the channel.
1799 *
1800 * This function is used when initializing channel-info structs.
1801 *
1802 * NOTE: These channel groups do *NOT* match the bands above!
1803 * These channel groups are based on factory-tested channels;
1804 * on A-band, EEPROM's "group frequency" entries represent the top
1805 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1806 */
1807static u16 iwl_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1808 const struct iwl_channel_info *ch_info)
1809{
1810 struct iwl_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
1811 u8 group;
1812 u16 group_index = 0; /* based on factory calib frequencies */
1813 u8 grp_channel;
1814
1815 /* Find the group index for the channel ... don't use index 1(?) */
1816 if (is_channel_a_band(ch_info)) {
1817 for (group = 1; group < 5; group++) {
1818 grp_channel = ch_grp[group].group_channel;
1819 if (ch_info->channel <= grp_channel) {
1820 group_index = group;
1821 break;
1822 }
1823 }
1824 /* group 4 has a few channels *above* its factory cal freq */
1825 if (group == 5)
1826 group_index = 4;
1827 } else
1828 group_index = 0; /* 2.4 GHz, group 0 */
1829
1830 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
1831 group_index);
1832 return group_index;
1833}
1834
1835/**
1836 * iwl_hw_reg_get_matched_power_index - Interpolate to get nominal index
1837 *
1838 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1839 * into radio/DSP gain settings table for requested power.
1840 */
1841static int iwl_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1842 s8 requested_power,
1843 s32 setting_index, s32 *new_index)
1844{
1845 const struct iwl_eeprom_txpower_group *chnl_grp = NULL;
1846 s32 index0, index1;
1847 s32 power = 2 * requested_power;
1848 s32 i;
1849 const struct iwl_eeprom_txpower_sample *samples;
1850 s32 gains0, gains1;
1851 s32 res;
1852 s32 denominator;
1853
1854 chnl_grp = &priv->eeprom.groups[setting_index];
1855 samples = chnl_grp->samples;
1856 for (i = 0; i < 5; i++) {
1857 if (power == samples[i].power) {
1858 *new_index = samples[i].gain_index;
1859 return 0;
1860 }
1861 }
1862
1863 if (power > samples[1].power) {
1864 index0 = 0;
1865 index1 = 1;
1866 } else if (power > samples[2].power) {
1867 index0 = 1;
1868 index1 = 2;
1869 } else if (power > samples[3].power) {
1870 index0 = 2;
1871 index1 = 3;
1872 } else {
1873 index0 = 3;
1874 index1 = 4;
1875 }
1876
1877 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
1878 if (denominator == 0)
1879 return -EINVAL;
1880 gains0 = (s32) samples[index0].gain_index * (1 << 19);
1881 gains1 = (s32) samples[index1].gain_index * (1 << 19);
1882 res = gains0 + (gains1 - gains0) *
1883 ((s32) power - (s32) samples[index0].power) / denominator +
1884 (1 << 18);
1885 *new_index = res >> 19;
1886 return 0;
1887}
1888
1889static void iwl_hw_reg_init_channel_groups(struct iwl_priv *priv)
1890{
1891 u32 i;
1892 s32 rate_index;
1893 const struct iwl_eeprom_txpower_group *group;
1894
1895 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
1896
1897 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
1898 s8 *clip_pwrs; /* table of power levels for each rate */
1899 s8 satur_pwr; /* saturation power for each chnl group */
1900 group = &priv->eeprom.groups[i];
1901
1902 /* sanity check on factory saturation power value */
1903 if (group->saturation_power < 40) {
1904 IWL_WARNING("Error: saturation power is %d, "
1905 "less than minimum expected 40\n",
1906 group->saturation_power);
1907 return;
1908 }
1909
1910 /*
1911 * Derive requested power levels for each rate, based on
1912 * hardware capabilities (saturation power for band).
1913 * Basic value is 3dB down from saturation, with further
1914 * power reductions for highest 3 data rates. These
1915 * backoffs provide headroom for high rate modulation
1916 * power peaks, without too much distortion (clipping).
1917 */
1918 /* we'll fill in this array with h/w max power levels */
1919 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
1920
1921 /* divide factory saturation power by 2 to find -3dB level */
1922 satur_pwr = (s8) (group->saturation_power >> 1);
1923
1924 /* fill in channel group's nominal powers for each rate */
1925 for (rate_index = 0;
1926 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
1927 switch (rate_index) {
14577f23 1928 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 1929 if (i == 0) /* B/G */
1930 *clip_pwrs = satur_pwr;
1931 else /* A */
1932 *clip_pwrs = satur_pwr - 5;
1933 break;
14577f23 1934 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 1935 if (i == 0)
1936 *clip_pwrs = satur_pwr - 7;
1937 else
1938 *clip_pwrs = satur_pwr - 10;
1939 break;
14577f23 1940 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 1941 if (i == 0)
1942 *clip_pwrs = satur_pwr - 9;
1943 else
1944 *clip_pwrs = satur_pwr - 12;
1945 break;
1946 default:
1947 *clip_pwrs = satur_pwr;
1948 break;
1949 }
1950 }
1951 }
1952}
1953
1954/**
1955 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
1956 *
1957 * Second pass (during init) to set up priv->channel_info
1958 *
1959 * Set up Tx-power settings in our channel info database for each VALID
1960 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
1961 * and current temperature.
1962 *
1963 * Since this is based on current temperature (at init time), these values may
1964 * not be valid for very long, but it gives us a starting/default point,
1965 * and allows us to active (i.e. using Tx) scan.
1966 *
1967 * This does *not* write values to NIC, just sets up our internal table.
1968 */
1969int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
1970{
1971 struct iwl_channel_info *ch_info = NULL;
1972 struct iwl_channel_power_info *pwr_info;
1973 int delta_index;
1974 u8 rate_index;
1975 u8 scan_tbl_index;
1976 const s8 *clip_pwrs; /* array of power levels for each rate */
1977 u8 gain, dsp_atten;
1978 s8 power;
1979 u8 pwr_index, base_pwr_index, a_band;
1980 u8 i;
1981 int temperature;
1982
1983 /* save temperature reference,
1984 * so we can determine next time to calibrate */
1985 temperature = iwl_hw_reg_txpower_get_temperature(priv);
1986 priv->last_temperature = temperature;
1987
1988 iwl_hw_reg_init_channel_groups(priv);
1989
1990 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
1991 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
1992 i++, ch_info++) {
1993 a_band = is_channel_a_band(ch_info);
1994 if (!is_channel_valid(ch_info))
1995 continue;
1996
1997 /* find this channel's channel group (*not* "band") index */
1998 ch_info->group_index =
1999 iwl_hw_reg_get_ch_grp_index(priv, ch_info);
2000
2001 /* Get this chnlgrp's rate->max/clip-powers table */
2002 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2003
2004 /* calculate power index *adjustment* value according to
2005 * diff between current temperature and factory temperature */
2006 delta_index = iwl_hw_reg_adjust_power_by_temp(temperature,
2007 priv->eeprom.groups[ch_info->group_index].
2008 temperature);
2009
2010 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2011 ch_info->channel, delta_index, temperature +
2012 IWL_TEMP_CONVERT);
2013
2014 /* set tx power value for all OFDM rates */
2015 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2016 rate_index++) {
2017 s32 power_idx;
2018 int rc;
2019
2020 /* use channel group's clip-power table,
2021 * but don't exceed channel's max power */
2022 s8 pwr = min(ch_info->max_power_avg,
2023 clip_pwrs[rate_index]);
2024
2025 pwr_info = &ch_info->power_info[rate_index];
2026
2027 /* get base (i.e. at factory-measured temperature)
2028 * power table index for this rate's power */
2029 rc = iwl_hw_reg_get_matched_power_index(priv, pwr,
2030 ch_info->group_index,
2031 &power_idx);
2032 if (rc) {
2033 IWL_ERROR("Invalid power index\n");
2034 return rc;
2035 }
2036 pwr_info->base_power_index = (u8) power_idx;
2037
2038 /* temperature compensate */
2039 power_idx += delta_index;
2040
2041 /* stay within range of gain table */
2042 power_idx = iwl_hw_reg_fix_power_index(power_idx);
2043
2044 /* fill 1 OFDM rate's iwl_channel_power_info struct */
2045 pwr_info->requested_power = pwr;
2046 pwr_info->power_table_index = (u8) power_idx;
2047 pwr_info->tpc.tx_gain =
2048 power_gain_table[a_band][power_idx].tx_gain;
2049 pwr_info->tpc.dsp_atten =
2050 power_gain_table[a_band][power_idx].dsp_atten;
2051 }
2052
2053 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2054 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2055 power = pwr_info->requested_power +
2056 IWL_CCK_FROM_OFDM_POWER_DIFF;
2057 pwr_index = pwr_info->power_table_index +
2058 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2059 base_pwr_index = pwr_info->base_power_index +
2060 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2061
2062 /* stay within table range */
2063 pwr_index = iwl_hw_reg_fix_power_index(pwr_index);
2064 gain = power_gain_table[a_band][pwr_index].tx_gain;
2065 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2066
2067 /* fill each CCK rate's iwl_channel_power_info structure
2068 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2069 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2070 for (rate_index = 0;
2071 rate_index < IWL_CCK_RATES; rate_index++) {
2072 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2073 pwr_info->requested_power = power;
2074 pwr_info->power_table_index = pwr_index;
2075 pwr_info->base_power_index = base_pwr_index;
2076 pwr_info->tpc.tx_gain = gain;
2077 pwr_info->tpc.dsp_atten = dsp_atten;
2078 }
2079
2080 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2081 for (scan_tbl_index = 0;
2082 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2083 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2084 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
b481de9c
ZY		 2085 iwl_hw_reg_set_scan_power(priv, scan_tbl_index,
2086 actual_index, clip_pwrs, ch_info, a_band);
2087 }
2088 }
2089
2090 return 0;
2091}
2092
2093int iwl_hw_rxq_stop(struct iwl_priv *priv)
2094{
2095 int rc;
2096 unsigned long flags;
2097
2098 spin_lock_irqsave(&priv->lock, flags);
ac17a947 2099 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2100 if (rc) {
2101 spin_unlock_irqrestore(&priv->lock, flags);
2102 return rc;
2103 }
2104
ac17a947
TW		 2105 iwl_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2106 rc = iwl_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
b481de9c
ZY		 2107 if (rc < 0)
2108 IWL_ERROR("Can't stop Rx DMA.\n");
2109
ac17a947 2110 iwl_release_nic_access(priv);
b481de9c
ZY		 2111 spin_unlock_irqrestore(&priv->lock, flags);
2112
2113 return 0;
2114}
2115
2116int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2117{
2118 int rc;
2119 unsigned long flags;
2120 int txq_id = txq->q.id;
2121
2122 struct iwl_shared *shared_data = priv->hw_setting.shared_virt;
2123
2124 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2125
2126 spin_lock_irqsave(&priv->lock, flags);
ac17a947 2127 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2128 if (rc) {
2129 spin_unlock_irqrestore(&priv->lock, flags);
2130 return rc;
2131 }
ac17a947
TW		 2132 iwl_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2133 iwl_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
b481de9c 2134
ac17a947 2135 iwl_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
b481de9c
ZY		 2136 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2137 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2138 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2139 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2140 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
ac17a947 2141 iwl_release_nic_access(priv);
b481de9c
ZY		 2142
2143 /* fake read to flush all prev. writes */
2144 iwl_read32(priv, FH_TSSR_CBB_BASE);
2145 spin_unlock_irqrestore(&priv->lock, flags);
2146
2147 return 0;
2148}
2149
2150int iwl_hw_get_rx_read(struct iwl_priv *priv)
2151{
2152 struct iwl_shared *shared_data = priv->hw_setting.shared_virt;
2153
2154 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2155}
2156
2157/**
2158 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2159 */
2160int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2161{
14577f23 2162 int rc, i, index, prev_index;
b481de9c
ZY		 2163 struct iwl_rate_scaling_cmd rate_cmd = {
2164 .reserved = {0, 0, 0},
2165 };
2166 struct iwl_rate_scaling_info *table = rate_cmd.table;
2167
2168 for (i = 0; i < ARRAY_SIZE(iwl_rates); i++) {
14577f23
MA		 2169 index = iwl_rates[i].table_rs_index;
2170
2171 table[index].rate_n_flags =
b481de9c 2172 iwl_hw_set_rate_n_flags(iwl_rates[i].plcp, 0);
14577f23
MA		 2173 table[index].try_cnt = priv->retry_rate;
2174 prev_index = iwl_get_prev_ieee_rate(i);
2175 table[index].next_rate_index = iwl_rates[prev_index].table_rs_index;
b481de9c
ZY		 2176 }
2177
2178 switch (priv->phymode) {
2179 case MODE_IEEE80211A:
2180 IWL_DEBUG_RATE("Select A mode rate scale\n");
2181 /* If one of the following CCK rates is used,
2182 * have it fall back to the 6M OFDM rate */
14577f23
MA		 2183 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
2184 table[i].next_rate_index = iwl_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2185
2186 /* Don't fall back to CCK rates */
14577f23 2187 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2188
2189 /* Don't drop out of OFDM rates */
14577f23
MA		 2190 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2191 iwl_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2192 break;
2193
2194 case MODE_IEEE80211B:
2195 IWL_DEBUG_RATE("Select B mode rate scale\n");
2196 /* If an OFDM rate is used, have it fall back to the
2197 * 1M CCK rates */
14577f23
MA		 2198 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
2199 table[i].next_rate_index = iwl_rates[IWL_FIRST_CCK_RATE].table_rs_index;
b481de9c
ZY		 2200
2201 /* CCK shouldn't fall back to OFDM... */
14577f23 2202 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
b481de9c
ZY		 2203 break;
2204
2205 default:
2206 IWL_DEBUG_RATE("Select G mode rate scale\n");
2207 break;
2208 }
2209
2210 /* Update the rate scaling for control frame Tx */
2211 rate_cmd.table_id = 0;
2212 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2213 &rate_cmd);
2214 if (rc)
2215 return rc;
2216
2217 /* Update the rate scaling for data frame Tx */
2218 rate_cmd.table_id = 1;
2219 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2220 &rate_cmd);
2221}
2222
2223int iwl_hw_set_hw_setting(struct iwl_priv *priv)
2224{
2225 memset((void *)&priv->hw_setting, 0,
2226 sizeof(struct iwl_driver_hw_info));
2227
2228 priv->hw_setting.shared_virt =
2229 pci_alloc_consistent(priv->pci_dev,
2230 sizeof(struct iwl_shared),
2231 &priv->hw_setting.shared_phys);
2232
2233 if (!priv->hw_setting.shared_virt) {
2234 IWL_ERROR("failed to allocate pci memory\n");
2235 mutex_unlock(&priv->mutex);
2236 return -ENOMEM;
2237 }
2238
2239 priv->hw_setting.ac_queue_count = AC_NUM;
2240 priv->hw_setting.rx_buffer_size = IWL_RX_BUF_SIZE;
2241 priv->hw_setting.tx_cmd_len = sizeof(struct iwl_tx_cmd);
2242 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2243 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
b481de9c
ZY		 2244 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2245 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2246 return 0;
2247}
2248
2249unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
2250 struct iwl_frame *frame, u8 rate)
2251{
2252 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
2253 unsigned int frame_size;
2254
2255 tx_beacon_cmd = (struct iwl_tx_beacon_cmd *)&frame->u;
2256 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2257
2258 tx_beacon_cmd->tx.sta_id = IWL3945_BROADCAST_ID;
2259 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2260
2261 frame_size = iwl_fill_beacon_frame(priv,
2262 tx_beacon_cmd->frame,
2263 BROADCAST_ADDR,
2264 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2265
2266 BUG_ON(frame_size > MAX_MPDU_SIZE);
2267 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2268
2269 tx_beacon_cmd->tx.rate = rate;
2270 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2271 TX_CMD_FLG_TSF_MSK);
2272
14577f23
MA		 2273 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2274 tx_beacon_cmd->tx.supp_rates[0] =
2275 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2276
b481de9c 2277 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2278 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c
ZY		 2279
2280 return (sizeof(struct iwl_tx_beacon_cmd) + frame_size);
2281}
2282
2283void iwl_hw_rx_handler_setup(struct iwl_priv *priv)
2284{
2285 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2286}
2287
2288void iwl_hw_setup_deferred_work(struct iwl_priv *priv)
2289{
2290 INIT_DELAYED_WORK(&priv->thermal_periodic,
2291 iwl3945_bg_reg_txpower_periodic);
2292}
2293
2294void iwl_hw_cancel_deferred_work(struct iwl_priv *priv)
2295{
2296 cancel_delayed_work(&priv->thermal_periodic);
2297}
2298
2299struct pci_device_id iwl_hw_card_ids[] = {
c6f3f656
TW		 2300 {PCI_DEVICE(0x8086, 0x4222)},
2301 {PCI_DEVICE(0x8086, 0x4227)},
b481de9c
ZY		 2302 {0}
2303};
2304
91e17473 2305inline int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
b481de9c
ZY		 2306{
2307 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2308 return 0;
2309}
2310
2311MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)