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iwlwifi: kill scan39
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
b481de9c 44#include "iwl-3945.h"
5d08cd1d 45#include "iwl-helpers.h"
5747d47f 46#include "iwl-core.h"
d9829a67 47#include "iwl-agn-rs.h"
b481de9c
ZY		 48
49#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_##r##M_IEEE, \
52 IWL_RATE_##ip##M_INDEX, \
53 IWL_RATE_##in##M_INDEX, \
54 IWL_RATE_##rp##M_INDEX, \
55 IWL_RATE_##rn##M_INDEX, \
56 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 57 IWL_RATE_##np##M_INDEX, \
58 IWL_RATE_##r##M_INDEX_TABLE, \
59 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 60
61/*
62 * Parameter order:
63 * rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
d9829a67 69const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 70 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 74 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 82};
83
bb8c093b 84/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 85#define IWL_EVT_DISABLE (0)
86#define IWL_EVT_DISABLE_SIZE (1532/32)
87
88/**
bb8c093b 89 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 90 *
91 * Disable an event by writing "1"s into "disable"
92 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
93 * Default values of 0 enable uCode events to be logged.
94 * Use for only special debugging. This function is just a placeholder as-is,
95 * you'll need to provide the special bits! ...
96 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 97void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 98{
af7cca2a 99 int ret;
b481de9c
ZY		 100 int i;
101 u32 base; /* SRAM address of event log header */
102 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
103 u32 array_size; /* # of u32 entries in array */
104 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
105 0x00000000, /* 31 - 0 Event id numbers */
106 0x00000000, /* 63 - 32 */
107 0x00000000, /* 95 - 64 */
108 0x00000000, /* 127 - 96 */
109 0x00000000, /* 159 - 128 */
110 0x00000000, /* 191 - 160 */
111 0x00000000, /* 223 - 192 */
112 0x00000000, /* 255 - 224 */
113 0x00000000, /* 287 - 256 */
114 0x00000000, /* 319 - 288 */
115 0x00000000, /* 351 - 320 */
116 0x00000000, /* 383 - 352 */
117 0x00000000, /* 415 - 384 */
118 0x00000000, /* 447 - 416 */
119 0x00000000, /* 479 - 448 */
120 0x00000000, /* 511 - 480 */
121 0x00000000, /* 543 - 512 */
122 0x00000000, /* 575 - 544 */
123 0x00000000, /* 607 - 576 */
124 0x00000000, /* 639 - 608 */
125 0x00000000, /* 671 - 640 */
126 0x00000000, /* 703 - 672 */
127 0x00000000, /* 735 - 704 */
128 0x00000000, /* 767 - 736 */
129 0x00000000, /* 799 - 768 */
130 0x00000000, /* 831 - 800 */
131 0x00000000, /* 863 - 832 */
132 0x00000000, /* 895 - 864 */
133 0x00000000, /* 927 - 896 */
134 0x00000000, /* 959 - 928 */
135 0x00000000, /* 991 - 960 */
136 0x00000000, /* 1023 - 992 */
137 0x00000000, /* 1055 - 1024 */
138 0x00000000, /* 1087 - 1056 */
139 0x00000000, /* 1119 - 1088 */
140 0x00000000, /* 1151 - 1120 */
141 0x00000000, /* 1183 - 1152 */
142 0x00000000, /* 1215 - 1184 */
143 0x00000000, /* 1247 - 1216 */
144 0x00000000, /* 1279 - 1248 */
145 0x00000000, /* 1311 - 1280 */
146 0x00000000, /* 1343 - 1312 */
147 0x00000000, /* 1375 - 1344 */
148 0x00000000, /* 1407 - 1376 */
149 0x00000000, /* 1439 - 1408 */
150 0x00000000, /* 1471 - 1440 */
151 0x00000000, /* 1503 - 1472 */
152 };
153
154 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 155 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 156 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 157 return;
158 }
159
5d49f498 160 ret = iwl_grab_nic_access(priv);
af7cca2a 161 if (ret) {
39aadf8c 162 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 163 return;
164 }
165
5d49f498
AK		 166 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
167 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
168 iwl_release_nic_access(priv);
b481de9c
ZY		 169
170 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
171 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
172 disable_ptr);
5d49f498 173 ret = iwl_grab_nic_access(priv);
b481de9c 174 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 175 iwl_write_targ_mem(priv,
af7cca2a
TW		 176 disable_ptr + (i * sizeof(u32)),
177 evt_disable[i]);
b481de9c 178
5d49f498 179 iwl_release_nic_access(priv);
b481de9c
ZY		 180 } else {
181 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
182 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
183 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
184 disable_ptr, array_size);
185 }
186
187}
188
17744ff6
TW		 189static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
190{
191 int idx;
192
193 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
194 if (iwl3945_rates[idx].plcp == plcp)
195 return idx;
196 return -1;
197}
198
b481de9c
ZY		 199/**
200 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
201 * @priv: eeprom and antenna fields are used to determine antenna flags
202 *
f2c7e521 203 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
b481de9c
ZY		 204 * priv->antenna specifies the antenna diversity mode:
205 *
a96a27f9 206 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 207 * IWL_ANTENNA_MAIN - Force MAIN antenna
208 * IWL_ANTENNA_AUX - Force AUX antenna
209 */
4a8a4322 210__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
b481de9c
ZY		 211{
212 switch (priv->antenna) {
213 case IWL_ANTENNA_DIVERSITY:
214 return 0;
215
216 case IWL_ANTENNA_MAIN:
f2c7e521 217 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 218 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
219 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
220
221 case IWL_ANTENNA_AUX:
f2c7e521 222 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 223 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
224 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
225 }
226
227 /* bad antenna selector value */
15b1687c 228 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
b481de9c
ZY		 229 return 0; /* "diversity" is default if error */
230}
231
91c066f2
TW		 232#ifdef CONFIG_IWL3945_DEBUG
233#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
234
235static const char *iwl3945_get_tx_fail_reason(u32 status)
236{
237 switch (status & TX_STATUS_MSK) {
238 case TX_STATUS_SUCCESS:
239 return "SUCCESS";
240 TX_STATUS_ENTRY(SHORT_LIMIT);
241 TX_STATUS_ENTRY(LONG_LIMIT);
242 TX_STATUS_ENTRY(FIFO_UNDERRUN);
243 TX_STATUS_ENTRY(MGMNT_ABORT);
244 TX_STATUS_ENTRY(NEXT_FRAG);
245 TX_STATUS_ENTRY(LIFE_EXPIRE);
246 TX_STATUS_ENTRY(DEST_PS);
247 TX_STATUS_ENTRY(ABORTED);
248 TX_STATUS_ENTRY(BT_RETRY);
249 TX_STATUS_ENTRY(STA_INVALID);
250 TX_STATUS_ENTRY(FRAG_DROPPED);
251 TX_STATUS_ENTRY(TID_DISABLE);
252 TX_STATUS_ENTRY(FRAME_FLUSHED);
253 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
254 TX_STATUS_ENTRY(TX_LOCKED);
255 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
256 }
257
258 return "UNKNOWN";
259}
260#else
261static inline const char *iwl3945_get_tx_fail_reason(u32 status)
262{
263 return "";
264}
265#endif
266
e6a9854b
JB		 267/*
268 * get ieee prev rate from rate scale table.
269 * for A and B mode we need to overright prev
270 * value
271 */
4a8a4322 272int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 273{
274 int next_rate = iwl3945_get_prev_ieee_rate(rate);
275
276 switch (priv->band) {
277 case IEEE80211_BAND_5GHZ:
278 if (rate == IWL_RATE_12M_INDEX)
279 next_rate = IWL_RATE_9M_INDEX;
280 else if (rate == IWL_RATE_6M_INDEX)
281 next_rate = IWL_RATE_6M_INDEX;
282 break;
7262796a
AM		 283 case IEEE80211_BAND_2GHZ:
284 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
285 iwl3945_is_associated(priv)) {
286 if (rate == IWL_RATE_11M_INDEX)
287 next_rate = IWL_RATE_5M_INDEX;
288 }
e6a9854b 289 break;
7262796a 290
e6a9854b
JB		 291 default:
292 break;
293 }
294
295 return next_rate;
296}
297
91c066f2
TW		 298
299/**
300 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
301 *
302 * When FW advances 'R' index, all entries between old and new 'R' index
303 * need to be reclaimed. As result, some free space forms. If there is
304 * enough free space (> low mark), wake the stack that feeds us.
305 */
4a8a4322 306static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 307 int txq_id, int index)
308{
188cf6c7 309 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 310 struct iwl_queue *q = &txq->q;
dbb6654c 311 struct iwl_tx_info *tx_info;
91c066f2
TW		 312
313 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
314
315 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
316 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
317
318 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 319 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 320 tx_info->skb[0] = NULL;
7aaa1d79 321 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 322 }
323
d20b3c65 324 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 325 (txq_id != IWL_CMD_QUEUE_NUM) &&
326 priv->mac80211_registered)
327 ieee80211_wake_queue(priv->hw, txq_id);
328}
329
330/**
331 * iwl3945_rx_reply_tx - Handle Tx response
332 */
4a8a4322 333static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 334 struct iwl_rx_mem_buffer *rxb)
91c066f2 335{
3d24a9f7 336 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 337 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
338 int txq_id = SEQ_TO_QUEUE(sequence);
339 int index = SEQ_TO_INDEX(sequence);
188cf6c7 340 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 341 struct ieee80211_tx_info *info;
91c066f2
TW		 342 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
343 u32 status = le32_to_cpu(tx_resp->status);
344 int rate_idx;
74221d07 345 int fail;
91c066f2 346
625a381a 347 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 348 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 349 "is out of range [0-%d] %d %d\n", txq_id,
350 index, txq->q.n_bd, txq->q.write_ptr,
351 txq->q.read_ptr);
352 return;
353 }
354
e039fa4a 355 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 356 ieee80211_tx_info_clear_status(info);
357
358 /* Fill the MRR chain with some info about on-chip retransmissions */
359 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
360 if (info->band == IEEE80211_BAND_5GHZ)
361 rate_idx -= IWL_FIRST_OFDM_RATE;
362
363 fail = tx_resp->failure_frame;
74221d07
AM		 364
365 info->status.rates[0].idx = rate_idx;
366 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 367
91c066f2 368 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 369 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
370 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 371
372 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
373 txq_id, iwl3945_get_tx_fail_reason(status), status,
374 tx_resp->rate, tx_resp->failure_frame);
375
91c066f2
TW		 376 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
377 iwl3945_tx_queue_reclaim(priv, txq_id, index);
378
379 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 380 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 381}
382
383
384
b481de9c
ZY		 385/*****************************************************************************
386 *
387 * Intel PRO/Wireless 3945ABG/BG Network Connection
388 *
389 * RX handler implementations
390 *
b481de9c
ZY		 391 *****************************************************************************/
392
4a8a4322 393void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 394{
3d24a9f7 395 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 396 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 397 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 398 le32_to_cpu(pkt->len));
399
f2c7e521 400 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 401
ab53d8af
MA		 402 iwl3945_led_background(priv);
403
b481de9c
ZY		 404 priv->last_statistics_time = jiffies;
405}
406
17744ff6
TW		 407/******************************************************************************
408 *
409 * Misc. internal state and helper functions
410 *
411 ******************************************************************************/
412#ifdef CONFIG_IWL3945_DEBUG
413
414/**
415 * iwl3945_report_frame - dump frame to syslog during debug sessions
416 *
417 * You may hack this function to show different aspects of received frames,
418 * including selective frame dumps.
419 * group100 parameter selects whether to show 1 out of 100 good frames.
420 */
4a8a4322 421static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 422 struct iwl_rx_packet *pkt,
17744ff6
TW		 423 struct ieee80211_hdr *header, int group100)
424{
425 u32 to_us;
426 u32 print_summary = 0;
427 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
428 u32 hundred = 0;
429 u32 dataframe = 0;
fd7c8a40 430 __le16 fc;
17744ff6
TW		 431 u16 seq_ctl;
432 u16 channel;
433 u16 phy_flags;
434 u16 length;
435 u16 status;
436 u16 bcn_tmr;
437 u32 tsf_low;
438 u64 tsf;
439 u8 rssi;
440 u8 agc;
441 u16 sig_avg;
442 u16 noise_diff;
443 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
444 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
445 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
446 u8 *data = IWL_RX_DATA(pkt);
447
448 /* MAC header */
fd7c8a40 449 fc = header->frame_control;
17744ff6
TW		 450 seq_ctl = le16_to_cpu(header->seq_ctrl);
451
452 /* metadata */
453 channel = le16_to_cpu(rx_hdr->channel);
454 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
455 length = le16_to_cpu(rx_hdr->len);
456
457 /* end-of-frame status and timestamp */
458 status = le32_to_cpu(rx_end->status);
459 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
460 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
461 tsf = le64_to_cpu(rx_end->timestamp);
462
463 /* signal statistics */
464 rssi = rx_stats->rssi;
465 agc = rx_stats->agc;
466 sig_avg = le16_to_cpu(rx_stats->sig_avg);
467 noise_diff = le16_to_cpu(rx_stats->noise_diff);
468
469 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
470
471 /* if data frame is to us and all is good,
472 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 473 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
474 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 475 dataframe = 1;
476 if (!group100)
477 print_summary = 1; /* print each frame */
478 else if (priv->framecnt_to_us < 100) {
479 priv->framecnt_to_us++;
480 print_summary = 0;
481 } else {
482 priv->framecnt_to_us = 0;
483 print_summary = 1;
484 hundred = 1;
485 }
486 } else {
487 /* print summary for all other frames */
488 print_summary = 1;
489 }
490
491 if (print_summary) {
492 char *title;
0ff1cca0 493 int rate;
17744ff6
TW		 494
495 if (hundred)
496 title = "100Frames";
fd7c8a40 497 else if (ieee80211_has_retry(fc))
17744ff6 498 title = "Retry";
fd7c8a40 499 else if (ieee80211_is_assoc_resp(fc))
17744ff6 500 title = "AscRsp";
fd7c8a40 501 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 502 title = "RasRsp";
fd7c8a40 503 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 504 title = "PrbRsp";
505 print_dump = 1; /* dump frame contents */
506 } else if (ieee80211_is_beacon(fc)) {
507 title = "Beacon";
508 print_dump = 1; /* dump frame contents */
509 } else if (ieee80211_is_atim(fc))
510 title = "ATIM";
511 else if (ieee80211_is_auth(fc))
512 title = "Auth";
513 else if (ieee80211_is_deauth(fc))
514 title = "DeAuth";
515 else if (ieee80211_is_disassoc(fc))
516 title = "DisAssoc";
517 else
518 title = "Frame";
519
520 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
521 if (rate == -1)
522 rate = 0;
523 else
524 rate = iwl3945_rates[rate].ieee / 2;
525
526 /* print frame summary.
527 * MAC addresses show just the last byte (for brevity),
528 * but you can hack it to show more, if you'd like to. */
529 if (dataframe)
530 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 531 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 532 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 533 length, rssi, channel, rate);
534 else {
535 /* src/dst addresses assume managed mode */
536 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
537 "src=0x%02x, rssi=%u, tim=%lu usec, "
538 "phy=0x%02x, chnl=%d\n",
fd7c8a40 539 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 540 header->addr3[5], rssi,
541 tsf_low - priv->scan_start_tsf,
542 phy_flags, channel);
543 }
544 }
545 if (print_dump)
40b8ec0b 546 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6
TW		 547}
548#else
4a8a4322 549static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 550 struct iwl_rx_packet *pkt,
17744ff6
TW		 551 struct ieee80211_hdr *header, int group100)
552{
553}
554#endif
555
4bd9b4f3 556/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 557static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 558 struct ieee80211_hdr *header)
559{
560 /* Filter incoming packets to determine if they are targeted toward
561 * this network, discarding packets coming from ourselves */
562 switch (priv->iw_mode) {
05c914fe 563 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 564 /* packets to our IBSS update information */
565 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 566 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 567 /* packets to our IBSS update information */
568 return !compare_ether_addr(header->addr2, priv->bssid);
569 default:
570 return 1;
571 }
572}
17744ff6 573
4a8a4322 574static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 575 struct iwl_rx_mem_buffer *rxb,
12342c47 576 struct ieee80211_rx_status *stats)
b481de9c 577{
3d24a9f7 578 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
699669f3 579#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 580 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 581#endif
bb8c093b
CH		 582 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
583 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 584 short len = le16_to_cpu(rx_hdr->len);
585
586 /* We received data from the HW, so stop the watchdog */
3d24a9f7 587 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
b481de9c
ZY		 588 IWL_DEBUG_DROP("Corruption detected!\n");
589 return;
590 }
591
592 /* We only process data packets if the interface is open */
593 if (unlikely(!priv->is_open)) {
594 IWL_DEBUG_DROP_LIMIT
595 ("Dropping packet while interface is not open.\n");
596 return;
597 }
b481de9c
ZY		 598
599 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
600 /* Set the size of the skb to the size of the frame */
601 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
602
9c74d9fb 603 if (!iwl3945_mod_params.sw_crypto)
bb8c093b 604 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 605 le32_to_cpu(rx_end->status), stats);
606
ab53d8af 607#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 608 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 609 priv->rxtxpackets += len;
610#endif
b481de9c
ZY		 611 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
612 rxb->skb = NULL;
613}
614
7878a5a4
MA		 615#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
616
4a8a4322 617static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 618 struct iwl_rx_mem_buffer *rxb)
b481de9c 619{
17744ff6
TW		 620 struct ieee80211_hdr *header;
621 struct ieee80211_rx_status rx_status;
3d24a9f7 622 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 623 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
624 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
625 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 626 int snr;
b481de9c
ZY		 627 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
628 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 629 u8 network_packet;
17744ff6 630
17744ff6
TW		 631 rx_status.flag = 0;
632 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 633 rx_status.freq =
c0186078 634 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 635 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
636 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
637
638 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 639 if (rx_status.band == IEEE80211_BAND_5GHZ)
640 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 641
6f0a2c4d
BR		 642 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
643 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
644
645 /* set the preamble flag if appropriate */
646 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
647 rx_status.flag |= RX_FLAG_SHORTPRE;
648
b481de9c
ZY		 649 if ((unlikely(rx_stats->phy_count > 20))) {
650 IWL_DEBUG_DROP
651 ("dsp size out of range [0,20]: "
652 "%d/n", rx_stats->phy_count);
653 return;
654 }
655
656 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
657 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
658 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
659 return;
660 }
661
56decd3c 662
b481de9c
ZY		 663
664 /* Convert 3945's rssi indicator to dBm */
250bdd21 665 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 666
667 /* Set default noise value to -127 */
668 if (priv->last_rx_noise == 0)
669 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
670
671 /* 3945 provides noise info for OFDM frames only.
672 * sig_avg and noise_diff are measured by the 3945's digital signal
673 * processor (DSP), and indicate linear levels of signal level and
674 * distortion/noise within the packet preamble after
675 * automatic gain control (AGC). sig_avg should stay fairly
676 * constant if the radio's AGC is working well.
677 * Since these values are linear (not dB or dBm), linear
678 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
679 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
680 * to obtain noise level in dBm.
17744ff6 681 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 682 if (rx_stats_noise_diff) {
683 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 684 rx_status.noise = rx_status.signal -
17744ff6 685 iwl3945_calc_db_from_ratio(snr);
566bfe5a 686 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 687 rx_status.noise);
b481de9c
ZY		 688
689 /* If noise info not available, calculate signal quality indicator (%)
690 * using just the dBm signal level. */
691 } else {
17744ff6 692 rx_status.noise = priv->last_rx_noise;
566bfe5a 693 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 694 }
695
696
697 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 698 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 699 rx_stats_sig_avg, rx_stats_noise_diff);
700
b481de9c
ZY		 701 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
702
bb8c093b 703 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 704
17744ff6
TW		 705 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
706 network_packet ? '*' : ' ',
707 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 708 rx_status.signal, rx_status.signal,
709 rx_status.noise, rx_status.rate_idx);
b481de9c 710
17744ff6 711#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 712 if (priv->debug_level & (IWL_DL_RX))
b481de9c 713 /* Set "1" to report good data frames in groups of 100 */
17744ff6 714 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 715#endif
716
717 if (network_packet) {
718 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
719 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 720 priv->last_rx_rssi = rx_status.signal;
17744ff6 721 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 722 }
723
12e5e22d 724 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 725}
726
7aaa1d79
SO		 727int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
728 struct iwl_tx_queue *txq,
729 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 730{
731 int count;
7aaa1d79
SO		 732 struct iwl_queue *q;
733 struct iwl3945_tfd *tfd;
734
735 q = &txq->q;
736 tfd = &txq->tfds39[q->write_ptr];
737
738 if (reset)
739 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 740
741 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 742
743 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 744 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 745 NUM_TFD_CHUNKS);
746 return -EINVAL;
747 }
748
dbb6654c
WT		 749 tfd->tbs[count].addr = cpu_to_le32(addr);
750 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 751
752 count++;
753
754 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
755 TFD_CTL_PAD_SET(pad));
756
757 return 0;
758}
759
760/**
bb8c093b 761 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 762 *
763 * Does NOT advance any indexes
764 */
7aaa1d79 765void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 766{
188cf6c7 767 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)&txq->tfds39[0];
dbb6654c 768 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
b481de9c
ZY		 769 struct pci_dev *dev = priv->pci_dev;
770 int i;
771 int counter;
772
773 /* classify bd */
774 if (txq->q.id == IWL_CMD_QUEUE_NUM)
775 /* nothing to cleanup after for host commands */
7aaa1d79 776 return;
b481de9c
ZY		 777
778 /* sanity check */
dbb6654c 779 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 780 if (counter > NUM_TFD_CHUNKS) {
15b1687c 781 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 782 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 783 return;
b481de9c
ZY		 784 }
785
786 /* unmap chunks if any */
787
788 for (i = 1; i < counter; i++) {
dbb6654c
WT		 789 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
790 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 791 if (txq->txb[txq->q.read_ptr].skb[0]) {
792 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
793 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 794 /* Can be called from interrupt context */
795 dev_kfree_skb_any(skb);
fc4b6853 796 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 797 }
798 }
799 }
7aaa1d79 800 return ;
b481de9c
ZY		 801}
802
4a8a4322 803u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 804{
c93007ef 805 int i, start = IWL_AP_ID;
b481de9c
ZY		 806 int ret = IWL_INVALID_STATION;
807 unsigned long flags;
808
c93007ef
SO		 809 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
810 (priv->iw_mode == NL80211_IFTYPE_AP))
811 start = IWL_STA_ID;
812
813 if (is_broadcast_ether_addr(addr))
3832ec9d 814 return priv->hw_params.bcast_sta_id;
c93007ef 815
b481de9c 816 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 817 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 818 if ((priv->stations_39[i].used) &&
b481de9c 819 (!compare_ether_addr
f2c7e521 820 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 821 ret = i;
822 goto out;
823 }
824
e174961c
JB		 825 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
826 addr, priv->num_stations);
b481de9c
ZY		 827 out:
828 spin_unlock_irqrestore(&priv->sta_lock, flags);
829 return ret;
830}
831
832/**
bb8c093b 833 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 834 *
835*/
c2d79b48 836void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 837 struct ieee80211_tx_info *info,
b481de9c
ZY		 838 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
839{
e039fa4a 840 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 841 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 842 u16 rate_mask;
843 int rate;
844 u8 rts_retry_limit;
845 u8 data_retry_limit;
846 __le32 tx_flags;
fd7c8a40 847 __le16 fc = hdr->frame_control;
c2d79b48 848 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 849
bb8c093b 850 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 851 tx_flags = tx->tx_flags;
b481de9c
ZY		 852
853 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 854 * in this running context */
b481de9c
ZY		 855 rate_mask = IWL_RATES_MASK;
856
b481de9c
ZY		 857 if (tx_id >= IWL_CMD_QUEUE_NUM)
858 rts_retry_limit = 3;
859 else
860 rts_retry_limit = 7;
861
fd7c8a40 862 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 863 data_retry_limit = 3;
864 if (data_retry_limit < rts_retry_limit)
865 rts_retry_limit = data_retry_limit;
866 } else
867 data_retry_limit = IWL_DEFAULT_TX_RETRY;
868
869 if (priv->data_retry_limit != -1)
870 data_retry_limit = priv->data_retry_limit;
871
fd7c8a40
HH		 872 if (ieee80211_is_mgmt(fc)) {
873 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
874 case cpu_to_le16(IEEE80211_STYPE_AUTH):
875 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
876 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
877 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 878 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
879 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
880 tx_flags |= TX_CMD_FLG_CTS_MSK;
881 }
882 break;
883 default:
884 break;
885 }
886 }
887
c2d79b48
WT		 888 tx->rts_retry_limit = rts_retry_limit;
889 tx->data_retry_limit = data_retry_limit;
890 tx->rate = rate;
891 tx->tx_flags = tx_flags;
b481de9c
ZY		 892
893 /* OFDM */
c2d79b48 894 tx->supp_rates[0] =
14577f23 895 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 896
897 /* CCK */
c2d79b48 898 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 899
900 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
901 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 902 tx->rate, le32_to_cpu(tx->tx_flags),
903 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 904}
905
4a8a4322 906u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 907{
908 unsigned long flags_spin;
bb8c093b 909 struct iwl3945_station_entry *station;
b481de9c
ZY		 910
911 if (sta_id == IWL_INVALID_STATION)
912 return IWL_INVALID_STATION;
913
914 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 915 station = &priv->stations_39[sta_id];
b481de9c
ZY		 916
917 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
918 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 919 station->sta.mode = STA_CONTROL_MODIFY_MSK;
920
921 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
922
bb8c093b 923 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 924 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
925 sta_id, tx_rate);
926 return sta_id;
927}
928
854682ed 929static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c
ZY		 930{
931 int rc;
932 unsigned long flags;
933
934 spin_lock_irqsave(&priv->lock, flags);
5d49f498 935 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 936 if (rc) {
937 spin_unlock_irqrestore(&priv->lock, flags);
938 return rc;
939 }
940
854682ed 941 if (src == IWL_PWR_SRC_VAUX) {
b481de9c
ZY		 942 u32 val;
943
944 rc = pci_read_config_dword(priv->pci_dev,
945 PCI_POWER_SOURCE, &val);
946 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
5d49f498 947 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 948 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
949 ~APMG_PS_CTRL_MSK_PWR_SRC);
5d49f498 950 iwl_release_nic_access(priv);
b481de9c 951
5d49f498 952 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 953 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
954 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
955 } else
5d49f498 956 iwl_release_nic_access(priv);
b481de9c 957 } else {
5d49f498 958 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 959 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
960 ~APMG_PS_CTRL_MSK_PWR_SRC);
961
5d49f498
AK		 962 iwl_release_nic_access(priv);
963 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 964 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
965 }
966 spin_unlock_irqrestore(&priv->lock, flags);
967
968 return rc;
969}
970
4a8a4322 971static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY		 972{
973 int rc;
974 unsigned long flags;
975
976 spin_lock_irqsave(&priv->lock, flags);
5d49f498 977 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 978 if (rc) {
979 spin_unlock_irqrestore(&priv->lock, flags);
980 return rc;
981 }
982
5d49f498 983 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 984 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 985 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
986 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 987 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
988 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
989 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
990 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
991 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
992 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
993 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
994 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 995
996 /* fake read to flush all prev I/O */
5d49f498 997 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 998
5d49f498 999 iwl_release_nic_access(priv);
b481de9c
ZY		 1000 spin_unlock_irqrestore(&priv->lock, flags);
1001
1002 return 0;
1003}
1004
4a8a4322 1005static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1006{
1007 int rc;
1008 unsigned long flags;
1009
1010 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1011 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1012 if (rc) {
1013 spin_unlock_irqrestore(&priv->lock, flags);
1014 return rc;
1015 }
1016
1017 /* bypass mode */
5d49f498 1018 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1019
1020 /* RA 0 is active */
5d49f498 1021 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1022
1023 /* all 6 fifo are active */
5d49f498 1024 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1025
5d49f498
AK		 1026 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1027 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1028 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1029 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1030
5d49f498 1031 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 1032 priv->shared_phys);
b481de9c 1033
5d49f498 1034 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1035 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1036 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1037 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1038 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1039 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1040 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1041 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1042
5d49f498 1043 iwl_release_nic_access(priv);
b481de9c
ZY		 1044 spin_unlock_irqrestore(&priv->lock, flags);
1045
1046 return 0;
1047}
1048
1049/**
1050 * iwl3945_txq_ctx_reset - Reset TX queue context
1051 *
1052 * Destroys all DMA structures and initialize them again
1053 */
4a8a4322 1054static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1055{
1056 int rc;
1057 int txq_id, slots_num;
1058
bb8c093b 1059 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1060
1061 /* Tx CMD queue */
1062 rc = iwl3945_tx_reset(priv);
1063 if (rc)
1064 goto error;
1065
1066 /* Tx queue(s) */
1067 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1068 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1069 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
188cf6c7 1070 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 1071 txq_id);
1072 if (rc) {
15b1687c 1073 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1074 goto error;
1075 }
1076 }
1077
1078 return rc;
1079
1080 error:
bb8c093b 1081 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1082 return rc;
1083}
1084
01ec616d 1085static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1086{
01ec616d 1087 int ret = 0;
b481de9c 1088
bb8c093b 1089 iwl3945_power_init_handle(priv);
b481de9c 1090
5d49f498 1091 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1092 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1093
1094 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1095 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1096 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1097
01ec616d
KA		 1098 /* set "initialization complete" bit to move adapter
1099 * D0U* --> D0A* state */
5d49f498 1100 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d
KA		 1101
1102 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1103 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1104 if (ret < 0) {
b481de9c 1105 IWL_DEBUG_INFO("Failed to init the card\n");
01ec616d 1106 goto out;
b481de9c
ZY		 1107 }
1108
01ec616d
KA		 1109 ret = iwl_grab_nic_access(priv);
1110 if (ret)
1111 goto out;
1112
1113 /* enable DMA */
1114 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1115 APMG_CLK_VAL_BSM_CLK_RQT);
1116
b481de9c 1117 udelay(20);
01ec616d
KA		 1118
1119 /* disable L1-Active */
5d49f498 1120 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1121 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1122
5d49f498 1123 iwl_release_nic_access(priv);
01ec616d
KA		 1124out:
1125 return ret;
1126}
b481de9c 1127
01ec616d
KA		 1128static void iwl3945_nic_config(struct iwl_priv *priv)
1129{
1130 unsigned long flags;
1131 u8 rev_id = 0;
b481de9c 1132
b481de9c
ZY		 1133 spin_lock_irqsave(&priv->lock, flags);
1134
1135 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1136 IWL_DEBUG_INFO("RTP type \n");
1137 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1138 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
5d49f498 1139 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1140 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1141 } else {
6f83eaa1 1142 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
5d49f498 1143 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1144 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1145 }
1146
f2c7e521 1147 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
b481de9c 1148 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
5d49f498 1149 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1150 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1151 } else
1152 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1153
f2c7e521 1154 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
b481de9c 1155 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1156 priv->eeprom39.board_revision);
5d49f498 1157 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1158 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1159 } else {
1160 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1161 priv->eeprom39.board_revision);
5d49f498 1162 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1163 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1164 }
1165
f2c7e521 1166 if (priv->eeprom39.almgor_m_version <= 1) {
5d49f498 1167 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1168 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c 1169 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
f2c7e521 1170 priv->eeprom39.almgor_m_version);
b481de9c
ZY		 1171 } else {
1172 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
f2c7e521 1173 priv->eeprom39.almgor_m_version);
5d49f498 1174 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1175 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1176 }
1177 spin_unlock_irqrestore(&priv->lock, flags);
1178
f2c7e521 1179 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 1180 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1181
f2c7e521 1182 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c 1183 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1184}
1185
1186int iwl3945_hw_nic_init(struct iwl_priv *priv)
1187{
1188 u8 rev_id;
1189 int rc;
1190 unsigned long flags;
1191 struct iwl_rx_queue *rxq = &priv->rxq;
1192
1193 spin_lock_irqsave(&priv->lock, flags);
1194 priv->cfg->ops->lib->apm_ops.init(priv);
1195 spin_unlock_irqrestore(&priv->lock, flags);
1196
1197 /* Determine HW type */
1198 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1199 if (rc)
1200 return rc;
1201 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1202
854682ed
KA		 1203 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1204 if(rc)
1205 return rc;
1206
01ec616d 1207 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1208
1209 /* Allocate the RX queue, or reset if it is already allocated */
1210 if (!rxq->bd) {
51af3d3f 1211 rc = iwl_rx_queue_alloc(priv);
b481de9c 1212 if (rc) {
15b1687c 1213 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1214 return -ENOMEM;
1215 }
1216 } else
51af3d3f 1217 iwl_rx_queue_reset(priv, rxq);
b481de9c 1218
bb8c093b 1219 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1220
1221 iwl3945_rx_init(priv, rxq);
1222
1223 spin_lock_irqsave(&priv->lock, flags);
1224
1225 /* Look at using this instead:
1226 rxq->need_update = 1;
141c43a3 1227 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1228 */
1229
5d49f498 1230 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1231 if (rc) {
1232 spin_unlock_irqrestore(&priv->lock, flags);
1233 return rc;
1234 }
5d49f498
AK		 1235 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1236 iwl_release_nic_access(priv);
b481de9c
ZY		 1237
1238 spin_unlock_irqrestore(&priv->lock, flags);
1239
1240 rc = iwl3945_txq_ctx_reset(priv);
1241 if (rc)
1242 return rc;
1243
1244 set_bit(STATUS_INIT, &priv->status);
1245
1246 return 0;
1247}
1248
1249/**
bb8c093b 1250 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1251 *
1252 * Destroy all TX DMA queues and structures
1253 */
4a8a4322 1254void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1255{
1256 int txq_id;
1257
1258 /* Tx queues */
1259 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
188cf6c7 1260 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c
ZY		 1261}
1262
4a8a4322 1263void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1264{
bddadf86 1265 int txq_id;
b481de9c
ZY		 1266 unsigned long flags;
1267
1268 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1269 if (iwl_grab_nic_access(priv)) {
b481de9c 1270 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1271 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1272 return;
1273 }
1274
1275 /* stop SCD */
5d49f498 1276 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1277
1278 /* reset TFD queues */
bddadf86 1279 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
5d49f498
AK		 1280 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1281 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1282 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1283 1000);
1284 }
1285
5d49f498 1286 iwl_release_nic_access(priv);
b481de9c
ZY		 1287 spin_unlock_irqrestore(&priv->lock, flags);
1288
bb8c093b 1289 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1290}
1291
01ec616d 1292static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1293{
01ec616d 1294 int ret = 0;
b481de9c
ZY		 1295 unsigned long flags;
1296
1297 spin_lock_irqsave(&priv->lock, flags);
1298
1299 /* set stop master bit */
5d49f498 1300 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1301
01ec616d
KA		 1302 iwl_poll_direct_bit(priv, CSR_RESET,
1303 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1304
01ec616d
KA		 1305 if (ret < 0)
1306 goto out;
b481de9c 1307
01ec616d 1308out:
b481de9c
ZY		 1309 spin_unlock_irqrestore(&priv->lock, flags);
1310 IWL_DEBUG_INFO("stop master\n");
1311
01ec616d
KA		 1312 return ret;
1313}
1314
1315static void iwl3945_apm_stop(struct iwl_priv *priv)
1316{
1317 unsigned long flags;
1318
1319 iwl3945_apm_stop_master(priv);
1320
1321 spin_lock_irqsave(&priv->lock, flags);
1322
1323 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1324
1325 udelay(10);
1326 /* clear "init complete" move adapter D0A* --> D0U state */
1327 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1328 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1329}
1330
e52119c5 1331static int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c
ZY		 1332{
1333 int rc;
1334 unsigned long flags;
1335
01ec616d 1336 iwl3945_apm_stop_master(priv);
b481de9c
ZY		 1337
1338 spin_lock_irqsave(&priv->lock, flags);
1339
5d49f498 1340 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1341
5d49f498 1342 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1343 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1344
5d49f498 1345 rc = iwl_grab_nic_access(priv);
b481de9c 1346 if (!rc) {
5d49f498 1347 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1348 APMG_CLK_VAL_BSM_CLK_RQT);
1349
1350 udelay(10);
1351
5d49f498 1352 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1353 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1354
5d49f498
AK		 1355 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1356 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1357 0xFFFFFFFF);
1358
1359 /* enable DMA */
5d49f498 1360 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1361 APMG_CLK_VAL_DMA_CLK_RQT |
1362 APMG_CLK_VAL_BSM_CLK_RQT);
1363 udelay(10);
1364
5d49f498 1365 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1366 APMG_PS_CTRL_VAL_RESET_REQ);
1367 udelay(5);
5d49f498 1368 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1369 APMG_PS_CTRL_VAL_RESET_REQ);
5d49f498 1370 iwl_release_nic_access(priv);
b481de9c
ZY		 1371 }
1372
1373 /* Clear the 'host command active' bit... */
1374 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1375
1376 wake_up_interruptible(&priv->wait_command_queue);
1377 spin_unlock_irqrestore(&priv->lock, flags);
1378
1379 return rc;
1380}
1381
1382/**
bb8c093b 1383 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1384 * return index delta into power gain settings table
1385*/
bb8c093b 1386static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1387{
1388 return (new_reading - old_reading) * (-11) / 100;
1389}
1390
1391/**
bb8c093b 1392 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1393 */
bb8c093b 1394static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1395{
3ac7f146 1396 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1397}
1398
4a8a4322 1399int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1400{
5d49f498 1401 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1402}
1403
1404/**
bb8c093b 1405 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1406 * get the current temperature by reading from NIC
1407*/
4a8a4322 1408static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 1409{
1410 int temperature;
1411
bb8c093b 1412 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1413
1414 /* driver's okay range is -260 to +25.
1415 * human readable okay range is 0 to +285 */
1416 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1417
1418 /* handle insane temp reading */
bb8c093b 1419 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1420 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1421
1422 /* if really really hot(?),
1423 * substitute the 3rd band/group's temp measured at factory */
1424 if (priv->last_temperature > 100)
f2c7e521 1425 temperature = priv->eeprom39.groups[2].temperature;
b481de9c
ZY		 1426 else /* else use most recent "sane" value from driver */
1427 temperature = priv->last_temperature;
1428 }
1429
1430 return temperature; /* raw, not "human readable" */
1431}
1432
1433/* Adjust Txpower only if temperature variance is greater than threshold.
1434 *
1435 * Both are lower than older versions' 9 degrees */
1436#define IWL_TEMPERATURE_LIMIT_TIMER 6
1437
1438/**
1439 * is_temp_calib_needed - determines if new calibration is needed
1440 *
1441 * records new temperature in tx_mgr->temperature.
1442 * replaces tx_mgr->last_temperature *only* if calib needed
1443 * (assumes caller will actually do the calibration!). */
4a8a4322 1444static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1445{
1446 int temp_diff;
1447
bb8c093b 1448 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1449 temp_diff = priv->temperature - priv->last_temperature;
1450
1451 /* get absolute value */
1452 if (temp_diff < 0) {
1453 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1454 temp_diff = -temp_diff;
1455 } else if (temp_diff == 0)
1456 IWL_DEBUG_POWER("Same temp,\n");
1457 else
1458 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1459
1460 /* if we don't need calibration, *don't* update last_temperature */
1461 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1462 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1463 return 0;
1464 }
1465
1466 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1467
1468 /* assume that caller will actually do calib ...
1469 * update the "last temperature" value */
1470 priv->last_temperature = priv->temperature;
1471 return 1;
1472}
1473
1474#define IWL_MAX_GAIN_ENTRIES 78
1475#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1476#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1477
1478/* radio and DSP power table, each step is 1/2 dB.
1479 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1480static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1481 {
1482 {251, 127}, /* 2.4 GHz, highest power */
1483 {251, 127},
1484 {251, 127},
1485 {251, 127},
1486 {251, 125},
1487 {251, 110},
1488 {251, 105},
1489 {251, 98},
1490 {187, 125},
1491 {187, 115},
1492 {187, 108},
1493 {187, 99},
1494 {243, 119},
1495 {243, 111},
1496 {243, 105},
1497 {243, 97},
1498 {243, 92},
1499 {211, 106},
1500 {211, 100},
1501 {179, 120},
1502 {179, 113},
1503 {179, 107},
1504 {147, 125},
1505 {147, 119},
1506 {147, 112},
1507 {147, 106},
1508 {147, 101},
1509 {147, 97},
1510 {147, 91},
1511 {115, 107},
1512 {235, 121},
1513 {235, 115},
1514 {235, 109},
1515 {203, 127},
1516 {203, 121},
1517 {203, 115},
1518 {203, 108},
1519 {203, 102},
1520 {203, 96},
1521 {203, 92},
1522 {171, 110},
1523 {171, 104},
1524 {171, 98},
1525 {139, 116},
1526 {227, 125},
1527 {227, 119},
1528 {227, 113},
1529 {227, 107},
1530 {227, 101},
1531 {227, 96},
1532 {195, 113},
1533 {195, 106},
1534 {195, 102},
1535 {195, 95},
1536 {163, 113},
1537 {163, 106},
1538 {163, 102},
1539 {163, 95},
1540 {131, 113},
1541 {131, 106},
1542 {131, 102},
1543 {131, 95},
1544 {99, 113},
1545 {99, 106},
1546 {99, 102},
1547 {99, 95},
1548 {67, 113},
1549 {67, 106},
1550 {67, 102},
1551 {67, 95},
1552 {35, 113},
1553 {35, 106},
1554 {35, 102},
1555 {35, 95},
1556 {3, 113},
1557 {3, 106},
1558 {3, 102},
1559 {3, 95} }, /* 2.4 GHz, lowest power */
1560 {
1561 {251, 127}, /* 5.x GHz, highest power */
1562 {251, 120},
1563 {251, 114},
1564 {219, 119},
1565 {219, 101},
1566 {187, 113},
1567 {187, 102},
1568 {155, 114},
1569 {155, 103},
1570 {123, 117},
1571 {123, 107},
1572 {123, 99},
1573 {123, 92},
1574 {91, 108},
1575 {59, 125},
1576 {59, 118},
1577 {59, 109},
1578 {59, 102},
1579 {59, 96},
1580 {59, 90},
1581 {27, 104},
1582 {27, 98},
1583 {27, 92},
1584 {115, 118},
1585 {115, 111},
1586 {115, 104},
1587 {83, 126},
1588 {83, 121},
1589 {83, 113},
1590 {83, 105},
1591 {83, 99},
1592 {51, 118},
1593 {51, 111},
1594 {51, 104},
1595 {51, 98},
1596 {19, 116},
1597 {19, 109},
1598 {19, 102},
1599 {19, 98},
1600 {19, 93},
1601 {171, 113},
1602 {171, 107},
1603 {171, 99},
1604 {139, 120},
1605 {139, 113},
1606 {139, 107},
1607 {139, 99},
1608 {107, 120},
1609 {107, 113},
1610 {107, 107},
1611 {107, 99},
1612 {75, 120},
1613 {75, 113},
1614 {75, 107},
1615 {75, 99},
1616 {43, 120},
1617 {43, 113},
1618 {43, 107},
1619 {43, 99},
1620 {11, 120},
1621 {11, 113},
1622 {11, 107},
1623 {11, 99},
1624 {131, 107},
1625 {131, 99},
1626 {99, 120},
1627 {99, 113},
1628 {99, 107},
1629 {99, 99},
1630 {67, 120},
1631 {67, 113},
1632 {67, 107},
1633 {67, 99},
1634 {35, 120},
1635 {35, 113},
1636 {35, 107},
1637 {35, 99},
1638 {3, 120} } /* 5.x GHz, lowest power */
1639};
1640
bb8c093b 1641static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1642{
1643 if (index < 0)
1644 return 0;
1645 if (index >= IWL_MAX_GAIN_ENTRIES)
1646 return IWL_MAX_GAIN_ENTRIES - 1;
1647 return (u8) index;
1648}
1649
1650/* Kick off thermal recalibration check every 60 seconds */
1651#define REG_RECALIB_PERIOD (60)
1652
1653/**
bb8c093b 1654 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1655 *
1656 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1657 * or 6 Mbit (OFDM) rates.
1658 */
4a8a4322 1659static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1660 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1661 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1662 int band_index)
1663{
bb8c093b 1664 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1665 s8 power;
1666 u8 power_index;
1667
1668 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1669
1670 /* use this channel group's 6Mbit clipping/saturation pwr,
1671 * but cap at regulatory scan power restriction (set during init
1672 * based on eeprom channel data) for this channel. */
14577f23 1673 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1674
1675 /* further limit to user's max power preference.
1676 * FIXME: Other spectrum management power limitations do not
1677 * seem to apply?? */
1678 power = min(power, priv->user_txpower_limit);
1679 scan_power_info->requested_power = power;
1680
1681 /* find difference between new scan *power* and current "normal"
1682 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1683 * current "normal" temperature-compensated Tx power *index* for
1684 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1685 * *index*. */
1686 power_index = ch_info->power_info[rate_index].power_table_index
1687 - (power - ch_info->power_info
14577f23 1688 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1689
1690 /* store reference index that we use when adjusting *all* scan
1691 * powers. So we can accommodate user (all channel) or spectrum
1692 * management (single channel) power changes "between" temperature
1693 * feedback compensation procedures.
1694 * don't force fit this reference index into gain table; it may be a
1695 * negative number. This will help avoid errors when we're at
1696 * the lower bounds (highest gains, for warmest temperatures)
1697 * of the table. */
1698
1699 /* don't exceed table bounds for "real" setting */
bb8c093b 1700 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1701
1702 scan_power_info->power_table_index = power_index;
1703 scan_power_info->tpc.tx_gain =
1704 power_gain_table[band_index][power_index].tx_gain;
1705 scan_power_info->tpc.dsp_atten =
1706 power_gain_table[band_index][power_index].dsp_atten;
1707}
1708
1709/**
bb8c093b 1710 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1711 *
1712 * Configures power settings for all rates for the current channel,
1713 * using values from channel info struct, and send to NIC
1714 */
4a8a4322 1715int iwl3945_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 1716{
14577f23 1717 int rate_idx, i;
d20b3c65 1718 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1719 struct iwl3945_txpowertable_cmd txpower = {
f2c7e521 1720 .channel = priv->active39_rxon.channel,
b481de9c
ZY		 1721 };
1722
8318d78a 1723 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1724 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1725 priv->band,
f2c7e521 1726 le16_to_cpu(priv->active39_rxon.channel));
b481de9c 1727 if (!ch_info) {
15b1687c
WT		 1728 IWL_ERR(priv,
1729 "Failed to get channel info for channel %d [%d]\n",
1730 le16_to_cpu(priv->active39_rxon.channel), priv->band);
b481de9c
ZY		 1731 return -EINVAL;
1732 }
1733
1734 if (!is_channel_valid(ch_info)) {
1735 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1736 "non-Tx channel.\n");
1737 return 0;
1738 }
1739
1740 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1741 /* Fill OFDM rate */
1742 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1743 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1744
1745 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1746 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1747
1748 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1749 le16_to_cpu(txpower.channel),
1750 txpower.band,
14577f23
MA		 1751 txpower.power[i].tpc.tx_gain,
1752 txpower.power[i].tpc.dsp_atten,
1753 txpower.power[i].rate);
1754 }
1755 /* Fill CCK rates */
1756 for (rate_idx = IWL_FIRST_CCK_RATE;
1757 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1758 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1759 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1760
1761 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1762 le16_to_cpu(txpower.channel),
1763 txpower.band,
1764 txpower.power[i].tpc.tx_gain,
1765 txpower.power[i].tpc.dsp_atten,
1766 txpower.power[i].rate);
b481de9c
ZY		 1767 }
1768
518099a8
SO		 1769 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1770 sizeof(struct iwl3945_txpowertable_cmd),
1771 &txpower);
b481de9c
ZY		 1772
1773}
1774
1775/**
bb8c093b 1776 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1777 * @ch_info: Channel to update. Uses power_info.requested_power.
1778 *
1779 * Replace requested_power and base_power_index ch_info fields for
1780 * one channel.
1781 *
1782 * Called if user or spectrum management changes power preferences.
1783 * Takes into account h/w and modulation limitations (clip power).
1784 *
1785 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1786 *
1787 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1788 * properly fill out the scan powers, and actual h/w gain settings,
1789 * and send changes to NIC
1790 */
4a8a4322 1791static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1792 struct iwl_channel_info *ch_info)
b481de9c 1793{
bb8c093b 1794 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1795 int power_changed = 0;
1796 int i;
1797 const s8 *clip_pwrs;
1798 int power;
1799
1800 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1801 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1802
1803 /* Get this channel's rate-to-current-power settings table */
1804 power_info = ch_info->power_info;
1805
1806 /* update OFDM Txpower settings */
14577f23 1807 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1808 i++, ++power_info) {
1809 int delta_idx;
1810
1811 /* limit new power to be no more than h/w capability */
1812 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1813 if (power == power_info->requested_power)
1814 continue;
1815
1816 /* find difference between old and new requested powers,
1817 * update base (non-temp-compensated) power index */
1818 delta_idx = (power - power_info->requested_power) * 2;
1819 power_info->base_power_index -= delta_idx;
1820
1821 /* save new requested power value */
1822 power_info->requested_power = power;
1823
1824 power_changed = 1;
1825 }
1826
1827 /* update CCK Txpower settings, based on OFDM 12M setting ...
1828 * ... all CCK power settings for a given channel are the *same*. */
1829 if (power_changed) {
1830 power =
14577f23 1831 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1832 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1833
bb8c093b 1834 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1835 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1836 power_info->requested_power = power;
1837 power_info->base_power_index =
14577f23 1838 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1839 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1840 ++power_info;
1841 }
1842 }
1843
1844 return 0;
1845}
1846
1847/**
bb8c093b 1848 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1849 *
1850 * NOTE: Returned power limit may be less (but not more) than requested,
1851 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1852 * (no consideration for h/w clipping limitations).
1853 */
d20b3c65 1854static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1855{
1856 s8 max_power;
1857
1858#if 0
1859 /* if we're using TGd limits, use lower of TGd or EEPROM */
1860 if (ch_info->tgd_data.max_power != 0)
1861 max_power = min(ch_info->tgd_data.max_power,
1862 ch_info->eeprom.max_power_avg);
1863
1864 /* else just use EEPROM limits */
1865 else
1866#endif
1867 max_power = ch_info->eeprom.max_power_avg;
1868
1869 return min(max_power, ch_info->max_power_avg);
1870}
1871
1872/**
bb8c093b 1873 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1874 *
1875 * Compensate txpower settings of *all* channels for temperature.
1876 * This only accounts for the difference between current temperature
1877 * and the factory calibration temperatures, and bases the new settings
1878 * on the channel's base_power_index.
1879 *
1880 * If RxOn is "associated", this sends the new Txpower to NIC!
1881 */
4a8a4322 1882static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1883{
d20b3c65 1884 struct iwl_channel_info *ch_info = NULL;
b481de9c
ZY		 1885 int delta_index;
1886 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1887 u8 a_band;
1888 u8 rate_index;
1889 u8 scan_tbl_index;
1890 u8 i;
1891 int ref_temp;
1892 int temperature = priv->temperature;
1893
1894 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1895 for (i = 0; i < priv->channel_count; i++) {
1896 ch_info = &priv->channel_info[i];
1897 a_band = is_channel_a_band(ch_info);
1898
1899 /* Get this chnlgrp's factory calibration temperature */
f2c7e521 1900 ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 1901 temperature;
1902
a96a27f9 1903 /* get power index adjustment based on current and factory
b481de9c 1904 * temps */
bb8c093b 1905 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1906 ref_temp);
1907
1908 /* set tx power value for all rates, OFDM and CCK */
1909 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1910 rate_index++) {
1911 int power_idx =
1912 ch_info->power_info[rate_index].base_power_index;
1913
1914 /* temperature compensate */
1915 power_idx += delta_index;
1916
1917 /* stay within table range */
bb8c093b 1918 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1919 ch_info->power_info[rate_index].
1920 power_table_index = (u8) power_idx;
1921 ch_info->power_info[rate_index].tpc =
1922 power_gain_table[a_band][power_idx];
1923 }
1924
1925 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1926 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1927
1928 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1929 for (scan_tbl_index = 0;
1930 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1931 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1932 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1933 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1934 actual_index, clip_pwrs,
1935 ch_info, a_band);
1936 }
1937 }
1938
1939 /* send Txpower command for current channel to ucode */
bb8c093b 1940 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1941}
1942
4a8a4322 1943int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1944{
d20b3c65 1945 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1946 s8 max_power;
1947 u8 a_band;
1948 u8 i;
1949
1950 if (priv->user_txpower_limit == power) {
1951 IWL_DEBUG_POWER("Requested Tx power same as current "
1952 "limit: %ddBm.\n", power);
1953 return 0;
1954 }
1955
1956 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1957 priv->user_txpower_limit = power;
1958
1959 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1960
1961 for (i = 0; i < priv->channel_count; i++) {
1962 ch_info = &priv->channel_info[i];
1963 a_band = is_channel_a_band(ch_info);
1964
1965 /* find minimum power of all user and regulatory constraints
1966 * (does not consider h/w clipping limitations) */
bb8c093b 1967 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1968 max_power = min(power, max_power);
1969 if (max_power != ch_info->curr_txpow) {
1970 ch_info->curr_txpow = max_power;
1971
1972 /* this considers the h/w clipping limitations */
bb8c093b 1973 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1974 }
1975 }
1976
1977 /* update txpower settings for all channels,
1978 * send to NIC if associated. */
1979 is_temp_calib_needed(priv);
bb8c093b 1980 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1981
1982 return 0;
1983}
1984
1985/* will add 3945 channel switch cmd handling later */
4a8a4322 1986int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1987{
1988 return 0;
1989}
1990
1991/**
1992 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1993 *
1994 * -- reset periodic timer
1995 * -- see if temp has changed enough to warrant re-calibration ... if so:
1996 * -- correct coeffs for temp (can reset temp timer)
1997 * -- save this temp as "last",
1998 * -- send new set of gain settings to NIC
1999 * NOTE: This should continue working, even when we're not associated,
2000 * so we can keep our internal table of scan powers current. */
4a8a4322 2001void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 2002{
2003 /* This will kick in the "brute force"
bb8c093b 2004 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2005 if (!is_temp_calib_needed(priv))
2006 goto reschedule;
2007
2008 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2009 * This is based *only* on current temperature,
2010 * ignoring any previous power measurements */
bb8c093b 2011 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2012
2013 reschedule:
2014 queue_delayed_work(priv->workqueue,
2015 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2016}
2017
416e1438 2018static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2019{
4a8a4322 2020 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2021 thermal_periodic.work);
2022
2023 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2024 return;
2025
2026 mutex_lock(&priv->mutex);
2027 iwl3945_reg_txpower_periodic(priv);
2028 mutex_unlock(&priv->mutex);
2029}
2030
2031/**
bb8c093b 2032 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2033 * for the channel.
2034 *
2035 * This function is used when initializing channel-info structs.
2036 *
2037 * NOTE: These channel groups do *NOT* match the bands above!
2038 * These channel groups are based on factory-tested channels;
2039 * on A-band, EEPROM's "group frequency" entries represent the top
2040 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2041 */
4a8a4322 2042static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2043 const struct iwl_channel_info *ch_info)
b481de9c 2044{
f2c7e521 2045 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0];
b481de9c
ZY		 2046 u8 group;
2047 u16 group_index = 0; /* based on factory calib frequencies */
2048 u8 grp_channel;
2049
2050 /* Find the group index for the channel ... don't use index 1(?) */
2051 if (is_channel_a_band(ch_info)) {
2052 for (group = 1; group < 5; group++) {
2053 grp_channel = ch_grp[group].group_channel;
2054 if (ch_info->channel <= grp_channel) {
2055 group_index = group;
2056 break;
2057 }
2058 }
2059 /* group 4 has a few channels *above* its factory cal freq */
2060 if (group == 5)
2061 group_index = 4;
2062 } else
2063 group_index = 0; /* 2.4 GHz, group 0 */
2064
2065 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2066 group_index);
2067 return group_index;
2068}
2069
2070/**
bb8c093b 2071 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2072 *
2073 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2074 * into radio/DSP gain settings table for requested power.
2075 */
4a8a4322 2076static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2077 s8 requested_power,
2078 s32 setting_index, s32 *new_index)
2079{
bb8c093b 2080 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2081 s32 index0, index1;
2082 s32 power = 2 * requested_power;
2083 s32 i;
bb8c093b 2084 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2085 s32 gains0, gains1;
2086 s32 res;
2087 s32 denominator;
2088
f2c7e521 2089 chnl_grp = &priv->eeprom39.groups[setting_index];
b481de9c
ZY		 2090 samples = chnl_grp->samples;
2091 for (i = 0; i < 5; i++) {
2092 if (power == samples[i].power) {
2093 *new_index = samples[i].gain_index;
2094 return 0;
2095 }
2096 }
2097
2098 if (power > samples[1].power) {
2099 index0 = 0;
2100 index1 = 1;
2101 } else if (power > samples[2].power) {
2102 index0 = 1;
2103 index1 = 2;
2104 } else if (power > samples[3].power) {
2105 index0 = 2;
2106 index1 = 3;
2107 } else {
2108 index0 = 3;
2109 index1 = 4;
2110 }
2111
2112 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2113 if (denominator == 0)
2114 return -EINVAL;
2115 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2116 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2117 res = gains0 + (gains1 - gains0) *
2118 ((s32) power - (s32) samples[index0].power) / denominator +
2119 (1 << 18);
2120 *new_index = res >> 19;
2121 return 0;
2122}
2123
4a8a4322 2124static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2125{
2126 u32 i;
2127 s32 rate_index;
bb8c093b 2128 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2129
2130 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2131
2132 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2133 s8 *clip_pwrs; /* table of power levels for each rate */
2134 s8 satur_pwr; /* saturation power for each chnl group */
f2c7e521 2135 group = &priv->eeprom39.groups[i];
b481de9c
ZY		 2136
2137 /* sanity check on factory saturation power value */
2138 if (group->saturation_power < 40) {
39aadf8c 2139 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2140 "less than minimum expected 40\n",
2141 group->saturation_power);
2142 return;
2143 }
2144
2145 /*
2146 * Derive requested power levels for each rate, based on
2147 * hardware capabilities (saturation power for band).
2148 * Basic value is 3dB down from saturation, with further
2149 * power reductions for highest 3 data rates. These
2150 * backoffs provide headroom for high rate modulation
2151 * power peaks, without too much distortion (clipping).
2152 */
2153 /* we'll fill in this array with h/w max power levels */
f2c7e521 2154 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2155
2156 /* divide factory saturation power by 2 to find -3dB level */
2157 satur_pwr = (s8) (group->saturation_power >> 1);
2158
2159 /* fill in channel group's nominal powers for each rate */
2160 for (rate_index = 0;
2161 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2162 switch (rate_index) {
14577f23 2163 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2164 if (i == 0) /* B/G */
2165 *clip_pwrs = satur_pwr;
2166 else /* A */
2167 *clip_pwrs = satur_pwr - 5;
2168 break;
14577f23 2169 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2170 if (i == 0)
2171 *clip_pwrs = satur_pwr - 7;
2172 else
2173 *clip_pwrs = satur_pwr - 10;
2174 break;
14577f23 2175 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2176 if (i == 0)
2177 *clip_pwrs = satur_pwr - 9;
2178 else
2179 *clip_pwrs = satur_pwr - 12;
2180 break;
2181 default:
2182 *clip_pwrs = satur_pwr;
2183 break;
2184 }
2185 }
2186 }
2187}
2188
2189/**
2190 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2191 *
2192 * Second pass (during init) to set up priv->channel_info
2193 *
2194 * Set up Tx-power settings in our channel info database for each VALID
2195 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2196 * and current temperature.
2197 *
2198 * Since this is based on current temperature (at init time), these values may
2199 * not be valid for very long, but it gives us a starting/default point,
2200 * and allows us to active (i.e. using Tx) scan.
2201 *
2202 * This does *not* write values to NIC, just sets up our internal table.
2203 */
4a8a4322 2204int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2205{
d20b3c65 2206 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2207 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2208 int delta_index;
2209 u8 rate_index;
2210 u8 scan_tbl_index;
2211 const s8 *clip_pwrs; /* array of power levels for each rate */
2212 u8 gain, dsp_atten;
2213 s8 power;
2214 u8 pwr_index, base_pwr_index, a_band;
2215 u8 i;
2216 int temperature;
2217
2218 /* save temperature reference,
2219 * so we can determine next time to calibrate */
bb8c093b 2220 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2221 priv->last_temperature = temperature;
2222
bb8c093b 2223 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2224
2225 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2226 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2227 i++, ch_info++) {
2228 a_band = is_channel_a_band(ch_info);
2229 if (!is_channel_valid(ch_info))
2230 continue;
2231
2232 /* find this channel's channel group (*not* "band") index */
2233 ch_info->group_index =
bb8c093b 2234 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2235
2236 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2237 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2238
2239 /* calculate power index *adjustment* value according to
2240 * diff between current temperature and factory temperature */
bb8c093b 2241 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
f2c7e521 2242 priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 2243 temperature);
2244
2245 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2246 ch_info->channel, delta_index, temperature +
2247 IWL_TEMP_CONVERT);
2248
2249 /* set tx power value for all OFDM rates */
2250 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2251 rate_index++) {
25a4ccea 2252 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2253 int rc;
2254
2255 /* use channel group's clip-power table,
2256 * but don't exceed channel's max power */
2257 s8 pwr = min(ch_info->max_power_avg,
2258 clip_pwrs[rate_index]);
2259
2260 pwr_info = &ch_info->power_info[rate_index];
2261
2262 /* get base (i.e. at factory-measured temperature)
2263 * power table index for this rate's power */
bb8c093b 2264 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2265 ch_info->group_index,
2266 &power_idx);
2267 if (rc) {
15b1687c 2268 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2269 return rc;
2270 }
2271 pwr_info->base_power_index = (u8) power_idx;
2272
2273 /* temperature compensate */
2274 power_idx += delta_index;
2275
2276 /* stay within range of gain table */
bb8c093b 2277 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2278
bb8c093b 2279 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2280 pwr_info->requested_power = pwr;
2281 pwr_info->power_table_index = (u8) power_idx;
2282 pwr_info->tpc.tx_gain =
2283 power_gain_table[a_band][power_idx].tx_gain;
2284 pwr_info->tpc.dsp_atten =
2285 power_gain_table[a_band][power_idx].dsp_atten;
2286 }
2287
2288 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2289 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2290 power = pwr_info->requested_power +
2291 IWL_CCK_FROM_OFDM_POWER_DIFF;
2292 pwr_index = pwr_info->power_table_index +
2293 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2294 base_pwr_index = pwr_info->base_power_index +
2295 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2296
2297 /* stay within table range */
bb8c093b 2298 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2299 gain = power_gain_table[a_band][pwr_index].tx_gain;
2300 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2301
bb8c093b 2302 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2303 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2304 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2305 for (rate_index = 0;
2306 rate_index < IWL_CCK_RATES; rate_index++) {
2307 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2308 pwr_info->requested_power = power;
2309 pwr_info->power_table_index = pwr_index;
2310 pwr_info->base_power_index = base_pwr_index;
2311 pwr_info->tpc.tx_gain = gain;
2312 pwr_info->tpc.dsp_atten = dsp_atten;
2313 }
2314
2315 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2316 for (scan_tbl_index = 0;
2317 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2318 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2319 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2320 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2321 actual_index, clip_pwrs, ch_info, a_band);
2322 }
2323 }
2324
2325 return 0;
2326}
2327
4a8a4322 2328int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2329{
2330 int rc;
2331 unsigned long flags;
2332
2333 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2334 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2335 if (rc) {
2336 spin_unlock_irqrestore(&priv->lock, flags);
2337 return rc;
2338 }
2339
5d49f498
AK		 2340 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2341 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2342 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2343 if (rc < 0)
15b1687c 2344 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2345
5d49f498 2346 iwl_release_nic_access(priv);
b481de9c
ZY		 2347 spin_unlock_irqrestore(&priv->lock, flags);
2348
2349 return 0;
2350}
2351
188cf6c7 2352int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c
ZY		 2353{
2354 int rc;
2355 unsigned long flags;
2356 int txq_id = txq->q.id;
2357
3832ec9d 2358 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2359
2360 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2361
2362 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2363 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2364 if (rc) {
2365 spin_unlock_irqrestore(&priv->lock, flags);
2366 return rc;
2367 }
5d49f498
AK		 2368 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2369 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2370
5d49f498 2371 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2372 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2373 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2374 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2375 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2376 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
5d49f498 2377 iwl_release_nic_access(priv);
b481de9c
ZY		 2378
2379 /* fake read to flush all prev. writes */
5d49f498 2380 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2381 spin_unlock_irqrestore(&priv->lock, flags);
2382
2383 return 0;
2384}
2385
42427b4e
KA		 2386/*
2387 * HCMD utils
2388 */
2389static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2390{
2391 switch (cmd_id) {
2392 case REPLY_RXON:
2393 return (u16) sizeof(struct iwl3945_rxon_cmd);
2394 default:
2395 return len;
2396 }
2397}
2398
b481de9c
ZY		 2399/**
2400 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2401 */
4a8a4322 2402int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2403{
14577f23 2404 int rc, i, index, prev_index;
bb8c093b 2405 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2406 .reserved = {0, 0, 0},
2407 };
bb8c093b 2408 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2409
bb8c093b
CH		 2410 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2411 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2412
2413 table[index].rate_n_flags =
bb8c093b 2414 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2415 table[index].try_cnt = priv->retry_rate;
bb8c093b 2416 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2417 table[index].next_rate_index =
2418 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2419 }
2420
8318d78a
JB		 2421 switch (priv->band) {
2422 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2423 IWL_DEBUG_RATE("Select A mode rate scale\n");
2424 /* If one of the following CCK rates is used,
2425 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2426 for (i = IWL_RATE_1M_INDEX_TABLE;
2427 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2428 table[i].next_rate_index =
2429 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2430
2431 /* Don't fall back to CCK rates */
7262796a
AM		 2432 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2433 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2434
2435 /* Don't drop out of OFDM rates */
14577f23 2436 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2437 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2438 break;
2439
8318d78a
JB		 2440 case IEEE80211_BAND_2GHZ:
2441 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2442 /* If an OFDM rate is used, have it fall back to the
2443 * 1M CCK rates */
b481de9c 2444
7262796a
AM		 2445 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2446 iwl3945_is_associated(priv)) {
2447
2448 index = IWL_FIRST_CCK_RATE;
2449 for (i = IWL_RATE_6M_INDEX_TABLE;
2450 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2451 table[i].next_rate_index =
2452 iwl3945_rates[index].table_rs_index;
2453
2454 index = IWL_RATE_11M_INDEX_TABLE;
2455 /* CCK shouldn't fall back to OFDM... */
2456 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2457 }
b481de9c
ZY		 2458 break;
2459
2460 default:
8318d78a 2461 WARN_ON(1);
b481de9c
ZY		 2462 break;
2463 }
2464
2465 /* Update the rate scaling for control frame Tx */
2466 rate_cmd.table_id = 0;
518099a8 2467 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2468 &rate_cmd);
2469 if (rc)
2470 return rc;
2471
2472 /* Update the rate scaling for data frame Tx */
2473 rate_cmd.table_id = 1;
518099a8 2474 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2475 &rate_cmd);
2476}
2477
796083cb 2478/* Called when initializing driver */
4a8a4322 2479int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2480{
3832ec9d
AK		 2481 memset((void *)&priv->hw_params, 0,
2482 sizeof(struct iwl_hw_params));
b481de9c 2483
3832ec9d 2484 priv->shared_virt =
b481de9c 2485 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2486 sizeof(struct iwl3945_shared),
3832ec9d 2487 &priv->shared_phys);
b481de9c 2488
3832ec9d 2489 if (!priv->shared_virt) {
15b1687c 2490 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2491 mutex_unlock(&priv->mutex);
2492 return -ENOMEM;
2493 }
2494
1e33dc64 2495 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
3832ec9d
AK		 2496 priv->hw_params.max_pkt_size = 2342;
2497 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2498 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2499 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2500 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2501
141c43a3
WT		 2502 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2503
b481de9c
ZY		 2504 return 0;
2505}
2506
4a8a4322 2507unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2508 struct iwl3945_frame *frame, u8 rate)
b481de9c 2509{
bb8c093b 2510 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2511 unsigned int frame_size;
2512
bb8c093b 2513 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2514 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2515
3832ec9d 2516 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2517 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2518
bb8c093b 2519 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2520 tx_beacon_cmd->frame,
b481de9c
ZY		 2521 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2522
2523 BUG_ON(frame_size > MAX_MPDU_SIZE);
2524 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2525
2526 tx_beacon_cmd->tx.rate = rate;
2527 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2528 TX_CMD_FLG_TSF_MSK);
2529
14577f23
MA		 2530 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2531 tx_beacon_cmd->tx.supp_rates[0] =
2532 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2533
b481de9c 2534 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2535 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2536
3ac7f146 2537 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2538}
2539
4a8a4322 2540void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2541{
91c066f2 2542 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2543 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2544}
2545
4a8a4322 2546void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2547{
2548 INIT_DELAYED_WORK(&priv->thermal_periodic,
2549 iwl3945_bg_reg_txpower_periodic);
2550}
2551
4a8a4322 2552void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2553{
2554 cancel_delayed_work(&priv->thermal_periodic);
2555}
2556
0164b9b4
KA		 2557/* check contents of special bootstrap uCode SRAM */
2558static int iwl3945_verify_bsm(struct iwl_priv *priv)
2559 {
2560 __le32 *image = priv->ucode_boot.v_addr;
2561 u32 len = priv->ucode_boot.len;
2562 u32 reg;
2563 u32 val;
2564
2565 IWL_DEBUG_INFO("Begin verify bsm\n");
2566
2567 /* verify BSM SRAM contents */
2568 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2569 for (reg = BSM_SRAM_LOWER_BOUND;
2570 reg < BSM_SRAM_LOWER_BOUND + len;
2571 reg += sizeof(u32), image++) {
2572 val = iwl_read_prph(priv, reg);
2573 if (val != le32_to_cpu(*image)) {
2574 IWL_ERR(priv, "BSM uCode verification failed at "
2575 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2576 BSM_SRAM_LOWER_BOUND,
2577 reg - BSM_SRAM_LOWER_BOUND, len,
2578 val, le32_to_cpu(*image));
2579 return -EIO;
2580 }
2581 }
2582
2583 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2584
2585 return 0;
2586}
2587
2588 /**
2589 * iwl3945_load_bsm - Load bootstrap instructions
2590 *
2591 * BSM operation:
2592 *
2593 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2594 * in special SRAM that does not power down during RFKILL. When powering back
2595 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2596 * the bootstrap program into the on-board processor, and starts it.
2597 *
2598 * The bootstrap program loads (via DMA) instructions and data for a new
2599 * program from host DRAM locations indicated by the host driver in the
2600 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2601 * automatically.
2602 *
2603 * When initializing the NIC, the host driver points the BSM to the
2604 * "initialize" uCode image. This uCode sets up some internal data, then
2605 * notifies host via "initialize alive" that it is complete.
2606 *
2607 * The host then replaces the BSM_DRAM_* pointer values to point to the
2608 * normal runtime uCode instructions and a backup uCode data cache buffer
2609 * (filled initially with starting data values for the on-board processor),
2610 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2611 * which begins normal operation.
2612 *
2613 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2614 * the backup data cache in DRAM before SRAM is powered down.
2615 *
2616 * When powering back up, the BSM loads the bootstrap program. This reloads
2617 * the runtime uCode instructions and the backup data cache into SRAM,
2618 * and re-launches the runtime uCode from where it left off.
2619 */
2620static int iwl3945_load_bsm(struct iwl_priv *priv)
2621{
2622 __le32 *image = priv->ucode_boot.v_addr;
2623 u32 len = priv->ucode_boot.len;
2624 dma_addr_t pinst;
2625 dma_addr_t pdata;
2626 u32 inst_len;
2627 u32 data_len;
2628 int rc;
2629 int i;
2630 u32 done;
2631 u32 reg_offset;
2632
2633 IWL_DEBUG_INFO("Begin load bsm\n");
2634
2635 /* make sure bootstrap program is no larger than BSM's SRAM size */
2636 if (len > IWL39_MAX_BSM_SIZE)
2637 return -EINVAL;
2638
2639 /* Tell bootstrap uCode where to find the "Initialize" uCode
2640 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2641 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2642 * after the "initialize" uCode has run, to point to
2643 * runtime/protocol instructions and backup data cache. */
2644 pinst = priv->ucode_init.p_addr;
2645 pdata = priv->ucode_init_data.p_addr;
2646 inst_len = priv->ucode_init.len;
2647 data_len = priv->ucode_init_data.len;
2648
2649 rc = iwl_grab_nic_access(priv);
2650 if (rc)
2651 return rc;
2652
2653 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2654 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2655 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2656 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2657
2658 /* Fill BSM memory with bootstrap instructions */
2659 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2660 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2661 reg_offset += sizeof(u32), image++)
2662 _iwl_write_prph(priv, reg_offset,
2663 le32_to_cpu(*image));
2664
2665 rc = iwl3945_verify_bsm(priv);
2666 if (rc) {
2667 iwl_release_nic_access(priv);
2668 return rc;
2669 }
2670
2671 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2672 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2673 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2674 IWL39_RTC_INST_LOWER_BOUND);
2675 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2676
2677 /* Load bootstrap code into instruction SRAM now,
2678 * to prepare to load "initialize" uCode */
2679 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2680 BSM_WR_CTRL_REG_BIT_START);
2681
2682 /* Wait for load of bootstrap uCode to finish */
2683 for (i = 0; i < 100; i++) {
2684 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2685 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2686 break;
2687 udelay(10);
2688 }
2689 if (i < 100)
2690 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2691 else {
2692 IWL_ERR(priv, "BSM write did not complete!\n");
2693 return -EIO;
2694 }
2695
2696 /* Enable future boot loads whenever power management unit triggers it
2697 * (e.g. when powering back up after power-save shutdown) */
2698 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2699 BSM_WR_CTRL_REG_BIT_START_EN);
2700
2701 iwl_release_nic_access(priv);
2702
2703 return 0;
2704}
2705
2706static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2707 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2708 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
0164b9b4 2709 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2710 .apm_ops = {
2711 .init = iwl3945_apm_init,
2712 .reset = iwl3945_apm_reset,
2713 .stop = iwl3945_apm_stop,
2714 .config = iwl3945_nic_config,
854682ed 2715 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2716 },
0164b9b4
KA		 2717};
2718
42427b4e
KA		 2719static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2720 .get_hcmd_size = iwl3945_get_hcmd_size,
2721};
2722
0164b9b4
KA		 2723static struct iwl_ops iwl3945_ops = {
2724 .lib = &iwl3945_lib,
42427b4e 2725 .utils = &iwl3945_hcmd_utils,
0164b9b4
KA		 2726};
2727
c0f20d91 2728static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2729 .name = "3945BG",
a0987a8d
RC		 2730 .fw_name_pre = IWL3945_FW_PRE,
2731 .ucode_api_max = IWL3945_UCODE_API_MAX,
2732 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2733 .sku = IWL_SKU_G,
0164b9b4 2734 .ops = &iwl3945_ops,
df878d8f 2735 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2736};
2737
c0f20d91 2738static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2739 .name = "3945ABG",
a0987a8d
RC		 2740 .fw_name_pre = IWL3945_FW_PRE,
2741 .ucode_api_max = IWL3945_UCODE_API_MAX,
2742 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2743 .sku = IWL_SKU_A|IWL_SKU_G,
0164b9b4 2744 .ops = &iwl3945_ops,
df878d8f 2745 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2746};
2747
bb8c093b 2748struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2749 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2750 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2751 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2752 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2753 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2754 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2755 {0}
2756};
2757
bb8c093b 2758MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)