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mac80211: Cancel the power save timer in ieee80211_stop.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
82b9a121 41#include "iwl-3945-core.h"
b481de9c 42#include "iwl-3945.h"
5d08cd1d 43#include "iwl-helpers.h"
b481de9c
ZY		 44#include "iwl-3945-rs.h"
45
46#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_##r##M_IEEE, \
49 IWL_RATE_##ip##M_INDEX, \
50 IWL_RATE_##in##M_INDEX, \
51 IWL_RATE_##rp##M_INDEX, \
52 IWL_RATE_##rn##M_INDEX, \
53 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 54 IWL_RATE_##np##M_INDEX, \
55 IWL_RATE_##r##M_INDEX_TABLE, \
56 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 57
58/*
59 * Parameter order:
60 * rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
bb8c093b 66const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
14577f23
MA		 67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 71 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 79};
80
bb8c093b 81/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 82#define IWL_EVT_DISABLE (0)
83#define IWL_EVT_DISABLE_SIZE (1532/32)
84
85/**
bb8c093b 86 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 87 *
88 * Disable an event by writing "1"s into "disable"
89 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
90 * Default values of 0 enable uCode events to be logged.
91 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */
bb8c093b 94void iwl3945_disable_events(struct iwl3945_priv *priv)
b481de9c 95{
af7cca2a 96 int ret;
b481de9c
ZY		 97 int i;
98 u32 base; /* SRAM address of event log header */
99 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
100 u32 array_size; /* # of u32 entries in array */
101 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
102 0x00000000, /* 31 - 0 Event id numbers */
103 0x00000000, /* 63 - 32 */
104 0x00000000, /* 95 - 64 */
105 0x00000000, /* 127 - 96 */
106 0x00000000, /* 159 - 128 */
107 0x00000000, /* 191 - 160 */
108 0x00000000, /* 223 - 192 */
109 0x00000000, /* 255 - 224 */
110 0x00000000, /* 287 - 256 */
111 0x00000000, /* 319 - 288 */
112 0x00000000, /* 351 - 320 */
113 0x00000000, /* 383 - 352 */
114 0x00000000, /* 415 - 384 */
115 0x00000000, /* 447 - 416 */
116 0x00000000, /* 479 - 448 */
117 0x00000000, /* 511 - 480 */
118 0x00000000, /* 543 - 512 */
119 0x00000000, /* 575 - 544 */
120 0x00000000, /* 607 - 576 */
121 0x00000000, /* 639 - 608 */
122 0x00000000, /* 671 - 640 */
123 0x00000000, /* 703 - 672 */
124 0x00000000, /* 735 - 704 */
125 0x00000000, /* 767 - 736 */
126 0x00000000, /* 799 - 768 */
127 0x00000000, /* 831 - 800 */
128 0x00000000, /* 863 - 832 */
129 0x00000000, /* 895 - 864 */
130 0x00000000, /* 927 - 896 */
131 0x00000000, /* 959 - 928 */
132 0x00000000, /* 991 - 960 */
133 0x00000000, /* 1023 - 992 */
134 0x00000000, /* 1055 - 1024 */
135 0x00000000, /* 1087 - 1056 */
136 0x00000000, /* 1119 - 1088 */
137 0x00000000, /* 1151 - 1120 */
138 0x00000000, /* 1183 - 1152 */
139 0x00000000, /* 1215 - 1184 */
140 0x00000000, /* 1247 - 1216 */
141 0x00000000, /* 1279 - 1248 */
142 0x00000000, /* 1311 - 1280 */
143 0x00000000, /* 1343 - 1312 */
144 0x00000000, /* 1375 - 1344 */
145 0x00000000, /* 1407 - 1376 */
146 0x00000000, /* 1439 - 1408 */
147 0x00000000, /* 1471 - 1440 */
148 0x00000000, /* 1503 - 1472 */
149 };
150
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 152 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
154 return;
155 }
156
bb8c093b 157 ret = iwl3945_grab_nic_access(priv);
af7cca2a 158 if (ret) {
b481de9c
ZY		 159 IWL_WARNING("Can not read from adapter at this time.\n");
160 return;
161 }
162
bb8c093b
CH		 163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv);
b481de9c
ZY		 166
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
169 disable_ptr);
bb8c093b 170 ret = iwl3945_grab_nic_access(priv);
b481de9c 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
bb8c093b 172 iwl3945_write_targ_mem(priv,
af7cca2a
TW		 173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
b481de9c 175
bb8c093b 176 iwl3945_release_nic_access(priv);
b481de9c
ZY		 177 } else {
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
180 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
181 disable_ptr, array_size);
182 }
183
184}
185
17744ff6
TW		 186static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
187{
188 int idx;
189
190 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
191 if (iwl3945_rates[idx].plcp == plcp)
192 return idx;
193 return -1;
194}
195
b481de9c
ZY		 196/**
197 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
198 * @priv: eeprom and antenna fields are used to determine antenna flags
199 *
200 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
201 * priv->antenna specifies the antenna diversity mode:
202 *
a96a27f9 203 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 204 * IWL_ANTENNA_MAIN - Force MAIN antenna
205 * IWL_ANTENNA_AUX - Force AUX antenna
206 */
bb8c093b 207__le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
b481de9c
ZY		 208{
209 switch (priv->antenna) {
210 case IWL_ANTENNA_DIVERSITY:
211 return 0;
212
213 case IWL_ANTENNA_MAIN:
214 if (priv->eeprom.antenna_switch_type)
215 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
216 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
217
218 case IWL_ANTENNA_AUX:
219 if (priv->eeprom.antenna_switch_type)
220 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
221 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
222 }
223
224 /* bad antenna selector value */
225 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
226 return 0; /* "diversity" is default if error */
227}
228
91c066f2
TW		 229#ifdef CONFIG_IWL3945_DEBUG
230#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
231
232static const char *iwl3945_get_tx_fail_reason(u32 status)
233{
234 switch (status & TX_STATUS_MSK) {
235 case TX_STATUS_SUCCESS:
236 return "SUCCESS";
237 TX_STATUS_ENTRY(SHORT_LIMIT);
238 TX_STATUS_ENTRY(LONG_LIMIT);
239 TX_STATUS_ENTRY(FIFO_UNDERRUN);
240 TX_STATUS_ENTRY(MGMNT_ABORT);
241 TX_STATUS_ENTRY(NEXT_FRAG);
242 TX_STATUS_ENTRY(LIFE_EXPIRE);
243 TX_STATUS_ENTRY(DEST_PS);
244 TX_STATUS_ENTRY(ABORTED);
245 TX_STATUS_ENTRY(BT_RETRY);
246 TX_STATUS_ENTRY(STA_INVALID);
247 TX_STATUS_ENTRY(FRAG_DROPPED);
248 TX_STATUS_ENTRY(TID_DISABLE);
249 TX_STATUS_ENTRY(FRAME_FLUSHED);
250 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
251 TX_STATUS_ENTRY(TX_LOCKED);
252 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
253 }
254
255 return "UNKNOWN";
256}
257#else
258static inline const char *iwl3945_get_tx_fail_reason(u32 status)
259{
260 return "";
261}
262#endif
263
e6a9854b
JB		 264/*
265 * get ieee prev rate from rate scale table.
266 * for A and B mode we need to overright prev
267 * value
268 */
269int iwl3945_rs_next_rate(struct iwl3945_priv *priv, int rate)
270{
271 int next_rate = iwl3945_get_prev_ieee_rate(rate);
272
273 switch (priv->band) {
274 case IEEE80211_BAND_5GHZ:
275 if (rate == IWL_RATE_12M_INDEX)
276 next_rate = IWL_RATE_9M_INDEX;
277 else if (rate == IWL_RATE_6M_INDEX)
278 next_rate = IWL_RATE_6M_INDEX;
279 break;
7262796a
AM		 280 case IEEE80211_BAND_2GHZ:
281 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
282 iwl3945_is_associated(priv)) {
283 if (rate == IWL_RATE_11M_INDEX)
284 next_rate = IWL_RATE_5M_INDEX;
285 }
e6a9854b 286 break;
7262796a 287
e6a9854b
JB		 288 default:
289 break;
290 }
291
292 return next_rate;
293}
294
91c066f2
TW		 295
296/**
297 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
298 *
299 * When FW advances 'R' index, all entries between old and new 'R' index
300 * need to be reclaimed. As result, some free space forms. If there is
301 * enough free space (> low mark), wake the stack that feeds us.
302 */
303static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
304 int txq_id, int index)
305{
306 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
307 struct iwl3945_queue *q = &txq->q;
308 struct iwl3945_tx_info *tx_info;
309
310 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
311
312 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
313 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
314
315 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 316 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2
TW		 317 tx_info->skb[0] = NULL;
318 iwl3945_hw_txq_free_tfd(priv, txq);
319 }
320
321 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
322 (txq_id != IWL_CMD_QUEUE_NUM) &&
323 priv->mac80211_registered)
324 ieee80211_wake_queue(priv->hw, txq_id);
325}
326
327/**
328 * iwl3945_rx_reply_tx - Handle Tx response
329 */
330static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
331 struct iwl3945_rx_mem_buffer *rxb)
332{
333 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
334 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
335 int txq_id = SEQ_TO_QUEUE(sequence);
336 int index = SEQ_TO_INDEX(sequence);
337 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 338 struct ieee80211_tx_info *info;
91c066f2
TW		 339 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
340 u32 status = le32_to_cpu(tx_resp->status);
341 int rate_idx;
74221d07 342 int fail;
91c066f2
TW		 343
344 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
345 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
346 "is out of range [0-%d] %d %d\n", txq_id,
347 index, txq->q.n_bd, txq->q.write_ptr,
348 txq->q.read_ptr);
349 return;
350 }
351
e039fa4a 352 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 353 ieee80211_tx_info_clear_status(info);
354
355 /* Fill the MRR chain with some info about on-chip retransmissions */
356 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
357 if (info->band == IEEE80211_BAND_5GHZ)
358 rate_idx -= IWL_FIRST_OFDM_RATE;
359
360 fail = tx_resp->failure_frame;
74221d07
AM		 361
362 info->status.rates[0].idx = rate_idx;
363 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 364
91c066f2 365 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 366 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
367 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 368
369 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
370 txq_id, iwl3945_get_tx_fail_reason(status), status,
371 tx_resp->rate, tx_resp->failure_frame);
372
91c066f2
TW		 373 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
374 iwl3945_tx_queue_reclaim(priv, txq_id, index);
375
376 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
377 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
378}
379
380
381
b481de9c
ZY		 382/*****************************************************************************
383 *
384 * Intel PRO/Wireless 3945ABG/BG Network Connection
385 *
386 * RX handler implementations
387 *
b481de9c
ZY		 388 *****************************************************************************/
389
bb8c093b 390void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 391{
bb8c093b 392 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 393 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 394 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 395 le32_to_cpu(pkt->len));
396
397 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
398
ab53d8af
MA		 399 iwl3945_led_background(priv);
400
b481de9c
ZY		 401 priv->last_statistics_time = jiffies;
402}
403
17744ff6
TW		 404/******************************************************************************
405 *
406 * Misc. internal state and helper functions
407 *
408 ******************************************************************************/
409#ifdef CONFIG_IWL3945_DEBUG
410
411/**
412 * iwl3945_report_frame - dump frame to syslog during debug sessions
413 *
414 * You may hack this function to show different aspects of received frames,
415 * including selective frame dumps.
416 * group100 parameter selects whether to show 1 out of 100 good frames.
417 */
418static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
419 struct iwl3945_rx_packet *pkt,
420 struct ieee80211_hdr *header, int group100)
421{
422 u32 to_us;
423 u32 print_summary = 0;
424 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
425 u32 hundred = 0;
426 u32 dataframe = 0;
fd7c8a40 427 __le16 fc;
17744ff6
TW		 428 u16 seq_ctl;
429 u16 channel;
430 u16 phy_flags;
431 u16 length;
432 u16 status;
433 u16 bcn_tmr;
434 u32 tsf_low;
435 u64 tsf;
436 u8 rssi;
437 u8 agc;
438 u16 sig_avg;
439 u16 noise_diff;
440 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
441 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
442 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
443 u8 *data = IWL_RX_DATA(pkt);
444
445 /* MAC header */
fd7c8a40 446 fc = header->frame_control;
17744ff6
TW		 447 seq_ctl = le16_to_cpu(header->seq_ctrl);
448
449 /* metadata */
450 channel = le16_to_cpu(rx_hdr->channel);
451 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
452 length = le16_to_cpu(rx_hdr->len);
453
454 /* end-of-frame status and timestamp */
455 status = le32_to_cpu(rx_end->status);
456 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
457 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
458 tsf = le64_to_cpu(rx_end->timestamp);
459
460 /* signal statistics */
461 rssi = rx_stats->rssi;
462 agc = rx_stats->agc;
463 sig_avg = le16_to_cpu(rx_stats->sig_avg);
464 noise_diff = le16_to_cpu(rx_stats->noise_diff);
465
466 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
467
468 /* if data frame is to us and all is good,
469 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 470 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
471 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 472 dataframe = 1;
473 if (!group100)
474 print_summary = 1; /* print each frame */
475 else if (priv->framecnt_to_us < 100) {
476 priv->framecnt_to_us++;
477 print_summary = 0;
478 } else {
479 priv->framecnt_to_us = 0;
480 print_summary = 1;
481 hundred = 1;
482 }
483 } else {
484 /* print summary for all other frames */
485 print_summary = 1;
486 }
487
488 if (print_summary) {
489 char *title;
0ff1cca0 490 int rate;
17744ff6
TW		 491
492 if (hundred)
493 title = "100Frames";
fd7c8a40 494 else if (ieee80211_has_retry(fc))
17744ff6 495 title = "Retry";
fd7c8a40 496 else if (ieee80211_is_assoc_resp(fc))
17744ff6 497 title = "AscRsp";
fd7c8a40 498 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 499 title = "RasRsp";
fd7c8a40 500 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 501 title = "PrbRsp";
502 print_dump = 1; /* dump frame contents */
503 } else if (ieee80211_is_beacon(fc)) {
504 title = "Beacon";
505 print_dump = 1; /* dump frame contents */
506 } else if (ieee80211_is_atim(fc))
507 title = "ATIM";
508 else if (ieee80211_is_auth(fc))
509 title = "Auth";
510 else if (ieee80211_is_deauth(fc))
511 title = "DeAuth";
512 else if (ieee80211_is_disassoc(fc))
513 title = "DisAssoc";
514 else
515 title = "Frame";
516
517 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
518 if (rate == -1)
519 rate = 0;
520 else
521 rate = iwl3945_rates[rate].ieee / 2;
522
523 /* print frame summary.
524 * MAC addresses show just the last byte (for brevity),
525 * but you can hack it to show more, if you'd like to. */
526 if (dataframe)
527 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 528 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 529 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 530 length, rssi, channel, rate);
531 else {
532 /* src/dst addresses assume managed mode */
533 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
534 "src=0x%02x, rssi=%u, tim=%lu usec, "
535 "phy=0x%02x, chnl=%d\n",
fd7c8a40 536 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 537 header->addr3[5], rssi,
538 tsf_low - priv->scan_start_tsf,
539 phy_flags, channel);
540 }
541 }
542 if (print_dump)
543 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
544}
545#else
546static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
547 struct iwl3945_rx_packet *pkt,
548 struct ieee80211_hdr *header, int group100)
549{
550}
551#endif
552
4bd9b4f3
AG		 553/* This is necessary only for a number of statistics, see the caller. */
554static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
555 struct ieee80211_hdr *header)
556{
557 /* Filter incoming packets to determine if they are targeted toward
558 * this network, discarding packets coming from ourselves */
559 switch (priv->iw_mode) {
05c914fe 560 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 561 /* packets to our IBSS update information */
562 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 563 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 564 /* packets to our IBSS update information */
565 return !compare_ether_addr(header->addr2, priv->bssid);
566 default:
567 return 1;
568 }
569}
17744ff6 570
4bd9b4f3 571static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
bb8c093b 572 struct iwl3945_rx_mem_buffer *rxb,
12342c47 573 struct ieee80211_rx_status *stats)
b481de9c 574{
bb8c093b 575 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
699669f3 576#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 577 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 578#endif
bb8c093b
CH		 579 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
580 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 581 short len = le16_to_cpu(rx_hdr->len);
582
583 /* We received data from the HW, so stop the watchdog */
584 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
585 IWL_DEBUG_DROP("Corruption detected!\n");
586 return;
587 }
588
589 /* We only process data packets if the interface is open */
590 if (unlikely(!priv->is_open)) {
591 IWL_DEBUG_DROP_LIMIT
592 ("Dropping packet while interface is not open.\n");
593 return;
594 }
b481de9c
ZY		 595
596 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
597 /* Set the size of the skb to the size of the frame */
598 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
599
bb8c093b
CH		 600 if (iwl3945_param_hwcrypto)
601 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 602 le32_to_cpu(rx_end->status), stats);
603
ab53d8af 604#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 605 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 606 priv->rxtxpackets += len;
607#endif
b481de9c
ZY		 608 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
609 rxb->skb = NULL;
610}
611
7878a5a4
MA		 612#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
613
bb8c093b
CH		 614static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
615 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 616{
17744ff6
TW		 617 struct ieee80211_hdr *header;
618 struct ieee80211_rx_status rx_status;
bb8c093b
CH		 619 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
620 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
621 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
622 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 623 int snr;
b481de9c
ZY		 624 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
625 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 626 u8 network_packet;
17744ff6 627
17744ff6
TW		 628 rx_status.flag = 0;
629 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 630 rx_status.freq =
c0186078 631 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 632 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
633 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
634
635 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 636 if (rx_status.band == IEEE80211_BAND_5GHZ)
637 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 638
6f0a2c4d
BR		 639 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
640 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
641
642 /* set the preamble flag if appropriate */
643 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
644 rx_status.flag |= RX_FLAG_SHORTPRE;
645
b481de9c
ZY		 646 if ((unlikely(rx_stats->phy_count > 20))) {
647 IWL_DEBUG_DROP
648 ("dsp size out of range [0,20]: "
649 "%d/n", rx_stats->phy_count);
650 return;
651 }
652
653 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
654 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
655 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
656 return;
657 }
658
56decd3c 659
b481de9c
ZY		 660
661 /* Convert 3945's rssi indicator to dBm */
566bfe5a 662 rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
b481de9c
ZY		 663
664 /* Set default noise value to -127 */
665 if (priv->last_rx_noise == 0)
666 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
667
668 /* 3945 provides noise info for OFDM frames only.
669 * sig_avg and noise_diff are measured by the 3945's digital signal
670 * processor (DSP), and indicate linear levels of signal level and
671 * distortion/noise within the packet preamble after
672 * automatic gain control (AGC). sig_avg should stay fairly
673 * constant if the radio's AGC is working well.
674 * Since these values are linear (not dB or dBm), linear
675 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
676 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
677 * to obtain noise level in dBm.
17744ff6 678 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 679 if (rx_stats_noise_diff) {
680 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 681 rx_status.noise = rx_status.signal -
17744ff6 682 iwl3945_calc_db_from_ratio(snr);
566bfe5a 683 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 684 rx_status.noise);
b481de9c
ZY		 685
686 /* If noise info not available, calculate signal quality indicator (%)
687 * using just the dBm signal level. */
688 } else {
17744ff6 689 rx_status.noise = priv->last_rx_noise;
566bfe5a 690 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 691 }
692
693
694 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 695 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 696 rx_stats_sig_avg, rx_stats_noise_diff);
697
b481de9c
ZY		 698 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699
bb8c093b 700 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 701
17744ff6
TW		 702 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
703 network_packet ? '*' : ' ',
704 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 705 rx_status.signal, rx_status.signal,
706 rx_status.noise, rx_status.rate_idx);
b481de9c 707
17744ff6 708#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 709 if (iwl3945_debug_level & (IWL_DL_RX))
b481de9c 710 /* Set "1" to report good data frames in groups of 100 */
17744ff6 711 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 712#endif
713
714 if (network_packet) {
715 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
716 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 717 priv->last_rx_rssi = rx_status.signal;
17744ff6 718 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 719 }
720
12e5e22d 721 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 722}
723
bb8c093b 724int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
b481de9c
ZY		 725 dma_addr_t addr, u16 len)
726{
727 int count;
728 u32 pad;
bb8c093b 729 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 730
731 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
732 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
733
734 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
735 IWL_ERROR("Error can not send more than %d chunks\n",
736 NUM_TFD_CHUNKS);
737 return -EINVAL;
738 }
739
740 tfd->pa[count].addr = cpu_to_le32(addr);
741 tfd->pa[count].len = cpu_to_le32(len);
742
743 count++;
744
745 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
746 TFD_CTL_PAD_SET(pad));
747
748 return 0;
749}
750
751/**
bb8c093b 752 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 753 *
754 * Does NOT advance any indexes
755 */
bb8c093b 756int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 757{
bb8c093b
CH		 758 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
759 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 760 struct pci_dev *dev = priv->pci_dev;
761 int i;
762 int counter;
763
764 /* classify bd */
765 if (txq->q.id == IWL_CMD_QUEUE_NUM)
766 /* nothing to cleanup after for host commands */
767 return 0;
768
769 /* sanity check */
770 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
771 if (counter > NUM_TFD_CHUNKS) {
772 IWL_ERROR("Too many chunks: %i\n", counter);
773 /* @todo issue fatal error, it is quite serious situation */
774 return 0;
775 }
776
777 /* unmap chunks if any */
778
779 for (i = 1; i < counter; i++) {
780 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
781 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 782 if (txq->txb[txq->q.read_ptr].skb[0]) {
783 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
784 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 785 /* Can be called from interrupt context */
786 dev_kfree_skb_any(skb);
fc4b6853 787 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 788 }
789 }
790 }
791 return 0;
792}
793
bb8c093b 794u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
b481de9c 795{
c93007ef 796 int i, start = IWL_AP_ID;
b481de9c
ZY		 797 int ret = IWL_INVALID_STATION;
798 unsigned long flags;
799
c93007ef
SO		 800 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
801 (priv->iw_mode == NL80211_IFTYPE_AP))
802 start = IWL_STA_ID;
803
804 if (is_broadcast_ether_addr(addr))
805 return priv->hw_setting.bcast_sta_id;
806
b481de9c 807 spin_lock_irqsave(&priv->sta_lock, flags);
c93007ef 808 for (i = start; i < priv->hw_setting.max_stations; i++)
b481de9c
ZY		 809 if ((priv->stations[i].used) &&
810 (!compare_ether_addr
811 (priv->stations[i].sta.sta.addr, addr))) {
812 ret = i;
813 goto out;
814 }
815
e174961c
JB		 816 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
817 addr, priv->num_stations);
b481de9c
ZY		 818 out:
819 spin_unlock_irqrestore(&priv->sta_lock, flags);
820 return ret;
821}
822
823/**
bb8c093b 824 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 825 *
826*/
bb8c093b
CH		 827void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
828 struct iwl3945_cmd *cmd,
e039fa4a 829 struct ieee80211_tx_info *info,
b481de9c
ZY		 830 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
831{
832 unsigned long flags;
e039fa4a 833 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 834 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 835 u16 rate_mask;
836 int rate;
837 u8 rts_retry_limit;
838 u8 data_retry_limit;
839 __le32 tx_flags;
fd7c8a40 840 __le16 fc = hdr->frame_control;
b481de9c 841
bb8c093b 842 rate = iwl3945_rates[rate_index].plcp;
b481de9c
ZY		 843 tx_flags = cmd->cmd.tx.tx_flags;
844
845 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 846 * in this running context */
b481de9c
ZY		 847 rate_mask = IWL_RATES_MASK;
848
849 spin_lock_irqsave(&priv->sta_lock, flags);
850
851 priv->stations[sta_id].current_rate.rate_n_flags = rate;
852
05c914fe 853 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
a4062b8f 854 (sta_id != priv->hw_setting.bcast_sta_id) &&
b481de9c
ZY		 855 (sta_id != IWL_MULTICAST_ID))
856 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
857
858 spin_unlock_irqrestore(&priv->sta_lock, flags);
859
860 if (tx_id >= IWL_CMD_QUEUE_NUM)
861 rts_retry_limit = 3;
862 else
863 rts_retry_limit = 7;
864
fd7c8a40 865 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 866 data_retry_limit = 3;
867 if (data_retry_limit < rts_retry_limit)
868 rts_retry_limit = data_retry_limit;
869 } else
870 data_retry_limit = IWL_DEFAULT_TX_RETRY;
871
872 if (priv->data_retry_limit != -1)
873 data_retry_limit = priv->data_retry_limit;
874
fd7c8a40
HH		 875 if (ieee80211_is_mgmt(fc)) {
876 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
877 case cpu_to_le16(IEEE80211_STYPE_AUTH):
878 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
879 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
880 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 881 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
882 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
883 tx_flags |= TX_CMD_FLG_CTS_MSK;
884 }
885 break;
886 default:
887 break;
888 }
889 }
890
891 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
892 cmd->cmd.tx.data_retry_limit = data_retry_limit;
893 cmd->cmd.tx.rate = rate;
894 cmd->cmd.tx.tx_flags = tx_flags;
895
896 /* OFDM */
14577f23
MA		 897 cmd->cmd.tx.supp_rates[0] =
898 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 899
900 /* CCK */
14577f23 901 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 902
903 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
904 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
905 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
906 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
907}
908
bb8c093b 909u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 910{
911 unsigned long flags_spin;
bb8c093b 912 struct iwl3945_station_entry *station;
b481de9c
ZY		 913
914 if (sta_id == IWL_INVALID_STATION)
915 return IWL_INVALID_STATION;
916
917 spin_lock_irqsave(&priv->sta_lock, flags_spin);
918 station = &priv->stations[sta_id];
919
920 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
921 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
922 station->current_rate.rate_n_flags = tx_rate;
923 station->sta.mode = STA_CONTROL_MODIFY_MSK;
924
925 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
926
bb8c093b 927 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 928 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
929 sta_id, tx_rate);
930 return sta_id;
931}
932
bb8c093b 933static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
b481de9c
ZY		 934{
935 int rc;
936 unsigned long flags;
937
938 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 939 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 940 if (rc) {
941 spin_unlock_irqrestore(&priv->lock, flags);
942 return rc;
943 }
944
945 if (!pwr_max) {
946 u32 val;
947
948 rc = pci_read_config_dword(priv->pci_dev,
949 PCI_POWER_SOURCE, &val);
950 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
bb8c093b 951 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 952 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
953 ~APMG_PS_CTRL_MSK_PWR_SRC);
bb8c093b 954 iwl3945_release_nic_access(priv);
b481de9c 955
bb8c093b 956 iwl3945_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 957 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
958 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
959 } else
bb8c093b 960 iwl3945_release_nic_access(priv);
b481de9c 961 } else {
bb8c093b 962 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 963 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
964 ~APMG_PS_CTRL_MSK_PWR_SRC);
965
bb8c093b
CH		 966 iwl3945_release_nic_access(priv);
967 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 968 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
969 }
970 spin_unlock_irqrestore(&priv->lock, flags);
971
972 return rc;
973}
974
bb8c093b 975static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 976{
977 int rc;
978 unsigned long flags;
979
980 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 981 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 982 if (rc) {
983 spin_unlock_irqrestore(&priv->lock, flags);
984 return rc;
985 }
986
bb8c093b
CH		 987 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
988 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
b481de9c 989 priv->hw_setting.shared_phys +
bb8c093b
CH		 990 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
991 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
992 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
b481de9c
ZY		 993 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
994 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
995 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
996 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
997 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
998 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
999 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
1000 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
1001
1002 /* fake read to flush all prev I/O */
bb8c093b 1003 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
b481de9c 1004
bb8c093b 1005 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1006 spin_unlock_irqrestore(&priv->lock, flags);
1007
1008 return 0;
1009}
1010
bb8c093b 1011static int iwl3945_tx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1012{
1013 int rc;
1014 unsigned long flags;
1015
1016 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1017 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1018 if (rc) {
1019 spin_unlock_irqrestore(&priv->lock, flags);
1020 return rc;
1021 }
1022
1023 /* bypass mode */
bb8c093b 1024 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1025
1026 /* RA 0 is active */
bb8c093b 1027 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1028
1029 /* all 6 fifo are active */
bb8c093b 1030 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1031
bb8c093b
CH		 1032 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1033 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1034 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1035 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1036
bb8c093b 1037 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
b481de9c
ZY		 1038 priv->hw_setting.shared_phys);
1039
bb8c093b 1040 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
b481de9c
ZY		 1041 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1042 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1043 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1044 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1045 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1046 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1047 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1048
bb8c093b 1049 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1050 spin_unlock_irqrestore(&priv->lock, flags);
1051
1052 return 0;
1053}
1054
1055/**
1056 * iwl3945_txq_ctx_reset - Reset TX queue context
1057 *
1058 * Destroys all DMA structures and initialize them again
1059 */
bb8c093b 1060static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1061{
1062 int rc;
1063 int txq_id, slots_num;
1064
bb8c093b 1065 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1066
1067 /* Tx CMD queue */
1068 rc = iwl3945_tx_reset(priv);
1069 if (rc)
1070 goto error;
1071
1072 /* Tx queue(s) */
1073 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1074 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1075 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 1076 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 1077 txq_id);
1078 if (rc) {
1079 IWL_ERROR("Tx %d queue init failed\n", txq_id);
1080 goto error;
1081 }
1082 }
1083
1084 return rc;
1085
1086 error:
bb8c093b 1087 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1088 return rc;
1089}
1090
bb8c093b 1091int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
b481de9c
ZY		 1092{
1093 u8 rev_id;
1094 int rc;
1095 unsigned long flags;
bb8c093b 1096 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 1097
bb8c093b 1098 iwl3945_power_init_handle(priv);
b481de9c
ZY		 1099
1100 spin_lock_irqsave(&priv->lock, flags);
a693f187 1101 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
bb8c093b 1102 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 1103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1104
bb8c093b 1105 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
73d7b5ac
ZY		 1106 rc = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
1107 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c
ZY		 1108 if (rc < 0) {
1109 spin_unlock_irqrestore(&priv->lock, flags);
1110 IWL_DEBUG_INFO("Failed to init the card\n");
1111 return rc;
1112 }
1113
bb8c093b 1114 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1115 if (rc) {
1116 spin_unlock_irqrestore(&priv->lock, flags);
1117 return rc;
1118 }
bb8c093b 1119 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1120 APMG_CLK_VAL_DMA_CLK_RQT |
1121 APMG_CLK_VAL_BSM_CLK_RQT);
1122 udelay(20);
bb8c093b 1123 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c 1124 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
bb8c093b 1125 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1126 spin_unlock_irqrestore(&priv->lock, flags);
1127
1128 /* Determine HW type */
1129 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1130 if (rc)
1131 return rc;
1132 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1133
1134 iwl3945_nic_set_pwr_src(priv, 1);
1135 spin_lock_irqsave(&priv->lock, flags);
1136
1137 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1138 IWL_DEBUG_INFO("RTP type \n");
1139 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1140 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
bb8c093b 1141 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1142 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1143 } else {
6f83eaa1 1144 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
bb8c093b 1145 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1146 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1147 }
1148
b481de9c
ZY		 1149 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1150 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
bb8c093b 1151 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1152 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1153 } else
1154 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1155
1156 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1157 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1158 priv->eeprom.board_revision);
bb8c093b 1159 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1160 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1161 } else {
1162 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1163 priv->eeprom.board_revision);
bb8c093b 1164 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1165 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1166 }
1167
1168 if (priv->eeprom.almgor_m_version <= 1) {
bb8c093b 1169 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1170 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c
ZY		 1171 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1172 priv->eeprom.almgor_m_version);
1173 } else {
1174 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1175 priv->eeprom.almgor_m_version);
bb8c093b 1176 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1177 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1178 }
1179 spin_unlock_irqrestore(&priv->lock, flags);
1180
1181 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1182 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1183
1184 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1185 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1186
1187 /* Allocate the RX queue, or reset if it is already allocated */
1188 if (!rxq->bd) {
bb8c093b 1189 rc = iwl3945_rx_queue_alloc(priv);
b481de9c
ZY		 1190 if (rc) {
1191 IWL_ERROR("Unable to initialize Rx queue\n");
1192 return -ENOMEM;
1193 }
1194 } else
bb8c093b 1195 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1196
bb8c093b 1197 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1198
1199 iwl3945_rx_init(priv, rxq);
1200
1201 spin_lock_irqsave(&priv->lock, flags);
1202
1203 /* Look at using this instead:
1204 rxq->need_update = 1;
bb8c093b 1205 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1206 */
1207
bb8c093b 1208 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1209 if (rc) {
1210 spin_unlock_irqrestore(&priv->lock, flags);
1211 return rc;
1212 }
bb8c093b
CH		 1213 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1214 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1215
1216 spin_unlock_irqrestore(&priv->lock, flags);
1217
1218 rc = iwl3945_txq_ctx_reset(priv);
1219 if (rc)
1220 return rc;
1221
1222 set_bit(STATUS_INIT, &priv->status);
1223
1224 return 0;
1225}
1226
1227/**
bb8c093b 1228 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1229 *
1230 * Destroy all TX DMA queues and structures
1231 */
bb8c093b 1232void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
b481de9c
ZY		 1233{
1234 int txq_id;
1235
1236 /* Tx queues */
1237 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
bb8c093b 1238 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c
ZY		 1239}
1240
bb8c093b 1241void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 1242{
1243 int queue;
1244 unsigned long flags;
1245
1246 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1247 if (iwl3945_grab_nic_access(priv)) {
b481de9c 1248 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1249 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1250 return;
1251 }
1252
1253 /* stop SCD */
bb8c093b 1254 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1255
1256 /* reset TFD queues */
1257 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
bb8c093b
CH		 1258 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1259 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
b481de9c
ZY		 1260 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1261 1000);
1262 }
1263
bb8c093b 1264 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1265 spin_unlock_irqrestore(&priv->lock, flags);
1266
bb8c093b 1267 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1268}
1269
bb8c093b 1270int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
b481de9c
ZY		 1271{
1272 int rc = 0;
1273 u32 reg_val;
1274 unsigned long flags;
1275
1276 spin_lock_irqsave(&priv->lock, flags);
1277
1278 /* set stop master bit */
bb8c093b 1279 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1280
bb8c093b 1281 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 1282
1283 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1284 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1285 IWL_DEBUG_INFO("Card in power save, master is already "
1286 "stopped\n");
1287 else {
73d7b5ac 1288 rc = iwl3945_poll_direct_bit(priv, CSR_RESET,
b481de9c
ZY		 1289 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1290 if (rc < 0) {
1291 spin_unlock_irqrestore(&priv->lock, flags);
1292 return rc;
1293 }
1294 }
1295
1296 spin_unlock_irqrestore(&priv->lock, flags);
1297 IWL_DEBUG_INFO("stop master\n");
1298
1299 return rc;
1300}
1301
bb8c093b 1302int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1303{
1304 int rc;
1305 unsigned long flags;
1306
bb8c093b 1307 iwl3945_hw_nic_stop_master(priv);
b481de9c
ZY		 1308
1309 spin_lock_irqsave(&priv->lock, flags);
1310
bb8c093b 1311 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1312
73d7b5ac
ZY		 1313 iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
1314 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1315
bb8c093b 1316 rc = iwl3945_grab_nic_access(priv);
b481de9c 1317 if (!rc) {
bb8c093b 1318 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1319 APMG_CLK_VAL_BSM_CLK_RQT);
1320
1321 udelay(10);
1322
bb8c093b 1323 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1324 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1325
bb8c093b
CH		 1326 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1327 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1328 0xFFFFFFFF);
1329
1330 /* enable DMA */
bb8c093b 1331 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1332 APMG_CLK_VAL_DMA_CLK_RQT |
1333 APMG_CLK_VAL_BSM_CLK_RQT);
1334 udelay(10);
1335
bb8c093b 1336 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1337 APMG_PS_CTRL_VAL_RESET_REQ);
1338 udelay(5);
bb8c093b 1339 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1340 APMG_PS_CTRL_VAL_RESET_REQ);
bb8c093b 1341 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1342 }
1343
1344 /* Clear the 'host command active' bit... */
1345 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1346
1347 wake_up_interruptible(&priv->wait_command_queue);
1348 spin_unlock_irqrestore(&priv->lock, flags);
1349
1350 return rc;
1351}
1352
1353/**
bb8c093b 1354 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1355 * return index delta into power gain settings table
1356*/
bb8c093b 1357static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1358{
1359 return (new_reading - old_reading) * (-11) / 100;
1360}
1361
1362/**
bb8c093b 1363 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1364 */
bb8c093b 1365static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1366{
3ac7f146 1367 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1368}
1369
bb8c093b 1370int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
b481de9c 1371{
bb8c093b 1372 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1373}
1374
1375/**
bb8c093b 1376 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1377 * get the current temperature by reading from NIC
1378*/
bb8c093b 1379static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
b481de9c
ZY		 1380{
1381 int temperature;
1382
bb8c093b 1383 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1384
1385 /* driver's okay range is -260 to +25.
1386 * human readable okay range is 0 to +285 */
1387 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1388
1389 /* handle insane temp reading */
bb8c093b 1390 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
b481de9c
ZY		 1391 IWL_ERROR("Error bad temperature value %d\n", temperature);
1392
1393 /* if really really hot(?),
1394 * substitute the 3rd band/group's temp measured at factory */
1395 if (priv->last_temperature > 100)
1396 temperature = priv->eeprom.groups[2].temperature;
1397 else /* else use most recent "sane" value from driver */
1398 temperature = priv->last_temperature;
1399 }
1400
1401 return temperature; /* raw, not "human readable" */
1402}
1403
1404/* Adjust Txpower only if temperature variance is greater than threshold.
1405 *
1406 * Both are lower than older versions' 9 degrees */
1407#define IWL_TEMPERATURE_LIMIT_TIMER 6
1408
1409/**
1410 * is_temp_calib_needed - determines if new calibration is needed
1411 *
1412 * records new temperature in tx_mgr->temperature.
1413 * replaces tx_mgr->last_temperature *only* if calib needed
1414 * (assumes caller will actually do the calibration!). */
bb8c093b 1415static int is_temp_calib_needed(struct iwl3945_priv *priv)
b481de9c
ZY		 1416{
1417 int temp_diff;
1418
bb8c093b 1419 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1420 temp_diff = priv->temperature - priv->last_temperature;
1421
1422 /* get absolute value */
1423 if (temp_diff < 0) {
1424 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1425 temp_diff = -temp_diff;
1426 } else if (temp_diff == 0)
1427 IWL_DEBUG_POWER("Same temp,\n");
1428 else
1429 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1430
1431 /* if we don't need calibration, *don't* update last_temperature */
1432 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1433 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1434 return 0;
1435 }
1436
1437 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1438
1439 /* assume that caller will actually do calib ...
1440 * update the "last temperature" value */
1441 priv->last_temperature = priv->temperature;
1442 return 1;
1443}
1444
1445#define IWL_MAX_GAIN_ENTRIES 78
1446#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1447#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1448
1449/* radio and DSP power table, each step is 1/2 dB.
1450 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1451static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1452 {
1453 {251, 127}, /* 2.4 GHz, highest power */
1454 {251, 127},
1455 {251, 127},
1456 {251, 127},
1457 {251, 125},
1458 {251, 110},
1459 {251, 105},
1460 {251, 98},
1461 {187, 125},
1462 {187, 115},
1463 {187, 108},
1464 {187, 99},
1465 {243, 119},
1466 {243, 111},
1467 {243, 105},
1468 {243, 97},
1469 {243, 92},
1470 {211, 106},
1471 {211, 100},
1472 {179, 120},
1473 {179, 113},
1474 {179, 107},
1475 {147, 125},
1476 {147, 119},
1477 {147, 112},
1478 {147, 106},
1479 {147, 101},
1480 {147, 97},
1481 {147, 91},
1482 {115, 107},
1483 {235, 121},
1484 {235, 115},
1485 {235, 109},
1486 {203, 127},
1487 {203, 121},
1488 {203, 115},
1489 {203, 108},
1490 {203, 102},
1491 {203, 96},
1492 {203, 92},
1493 {171, 110},
1494 {171, 104},
1495 {171, 98},
1496 {139, 116},
1497 {227, 125},
1498 {227, 119},
1499 {227, 113},
1500 {227, 107},
1501 {227, 101},
1502 {227, 96},
1503 {195, 113},
1504 {195, 106},
1505 {195, 102},
1506 {195, 95},
1507 {163, 113},
1508 {163, 106},
1509 {163, 102},
1510 {163, 95},
1511 {131, 113},
1512 {131, 106},
1513 {131, 102},
1514 {131, 95},
1515 {99, 113},
1516 {99, 106},
1517 {99, 102},
1518 {99, 95},
1519 {67, 113},
1520 {67, 106},
1521 {67, 102},
1522 {67, 95},
1523 {35, 113},
1524 {35, 106},
1525 {35, 102},
1526 {35, 95},
1527 {3, 113},
1528 {3, 106},
1529 {3, 102},
1530 {3, 95} }, /* 2.4 GHz, lowest power */
1531 {
1532 {251, 127}, /* 5.x GHz, highest power */
1533 {251, 120},
1534 {251, 114},
1535 {219, 119},
1536 {219, 101},
1537 {187, 113},
1538 {187, 102},
1539 {155, 114},
1540 {155, 103},
1541 {123, 117},
1542 {123, 107},
1543 {123, 99},
1544 {123, 92},
1545 {91, 108},
1546 {59, 125},
1547 {59, 118},
1548 {59, 109},
1549 {59, 102},
1550 {59, 96},
1551 {59, 90},
1552 {27, 104},
1553 {27, 98},
1554 {27, 92},
1555 {115, 118},
1556 {115, 111},
1557 {115, 104},
1558 {83, 126},
1559 {83, 121},
1560 {83, 113},
1561 {83, 105},
1562 {83, 99},
1563 {51, 118},
1564 {51, 111},
1565 {51, 104},
1566 {51, 98},
1567 {19, 116},
1568 {19, 109},
1569 {19, 102},
1570 {19, 98},
1571 {19, 93},
1572 {171, 113},
1573 {171, 107},
1574 {171, 99},
1575 {139, 120},
1576 {139, 113},
1577 {139, 107},
1578 {139, 99},
1579 {107, 120},
1580 {107, 113},
1581 {107, 107},
1582 {107, 99},
1583 {75, 120},
1584 {75, 113},
1585 {75, 107},
1586 {75, 99},
1587 {43, 120},
1588 {43, 113},
1589 {43, 107},
1590 {43, 99},
1591 {11, 120},
1592 {11, 113},
1593 {11, 107},
1594 {11, 99},
1595 {131, 107},
1596 {131, 99},
1597 {99, 120},
1598 {99, 113},
1599 {99, 107},
1600 {99, 99},
1601 {67, 120},
1602 {67, 113},
1603 {67, 107},
1604 {67, 99},
1605 {35, 120},
1606 {35, 113},
1607 {35, 107},
1608 {35, 99},
1609 {3, 120} } /* 5.x GHz, lowest power */
1610};
1611
bb8c093b 1612static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1613{
1614 if (index < 0)
1615 return 0;
1616 if (index >= IWL_MAX_GAIN_ENTRIES)
1617 return IWL_MAX_GAIN_ENTRIES - 1;
1618 return (u8) index;
1619}
1620
1621/* Kick off thermal recalibration check every 60 seconds */
1622#define REG_RECALIB_PERIOD (60)
1623
1624/**
bb8c093b 1625 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1626 *
1627 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1628 * or 6 Mbit (OFDM) rates.
1629 */
bb8c093b 1630static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
b481de9c 1631 s32 rate_index, const s8 *clip_pwrs,
bb8c093b 1632 struct iwl3945_channel_info *ch_info,
b481de9c
ZY		 1633 int band_index)
1634{
bb8c093b 1635 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1636 s8 power;
1637 u8 power_index;
1638
1639 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1640
1641 /* use this channel group's 6Mbit clipping/saturation pwr,
1642 * but cap at regulatory scan power restriction (set during init
1643 * based on eeprom channel data) for this channel. */
14577f23 1644 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1645
1646 /* further limit to user's max power preference.
1647 * FIXME: Other spectrum management power limitations do not
1648 * seem to apply?? */
1649 power = min(power, priv->user_txpower_limit);
1650 scan_power_info->requested_power = power;
1651
1652 /* find difference between new scan *power* and current "normal"
1653 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1654 * current "normal" temperature-compensated Tx power *index* for
1655 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1656 * *index*. */
1657 power_index = ch_info->power_info[rate_index].power_table_index
1658 - (power - ch_info->power_info
14577f23 1659 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1660
1661 /* store reference index that we use when adjusting *all* scan
1662 * powers. So we can accommodate user (all channel) or spectrum
1663 * management (single channel) power changes "between" temperature
1664 * feedback compensation procedures.
1665 * don't force fit this reference index into gain table; it may be a
1666 * negative number. This will help avoid errors when we're at
1667 * the lower bounds (highest gains, for warmest temperatures)
1668 * of the table. */
1669
1670 /* don't exceed table bounds for "real" setting */
bb8c093b 1671 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1672
1673 scan_power_info->power_table_index = power_index;
1674 scan_power_info->tpc.tx_gain =
1675 power_gain_table[band_index][power_index].tx_gain;
1676 scan_power_info->tpc.dsp_atten =
1677 power_gain_table[band_index][power_index].dsp_atten;
1678}
1679
1680/**
bb8c093b 1681 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1682 *
1683 * Configures power settings for all rates for the current channel,
1684 * using values from channel info struct, and send to NIC
1685 */
bb8c093b 1686int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
b481de9c 1687{
14577f23 1688 int rate_idx, i;
bb8c093b
CH		 1689 const struct iwl3945_channel_info *ch_info = NULL;
1690 struct iwl3945_txpowertable_cmd txpower = {
b481de9c
ZY		 1691 .channel = priv->active_rxon.channel,
1692 };
1693
8318d78a 1694 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1695 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1696 priv->band,
b481de9c
ZY		 1697 le16_to_cpu(priv->active_rxon.channel));
1698 if (!ch_info) {
1699 IWL_ERROR
1700 ("Failed to get channel info for channel %d [%d]\n",
8318d78a 1701 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1702 return -EINVAL;
1703 }
1704
1705 if (!is_channel_valid(ch_info)) {
1706 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1707 "non-Tx channel.\n");
1708 return 0;
1709 }
1710
1711 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1712 /* Fill OFDM rate */
1713 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1714 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1715
1716 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1717 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1718
1719 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1720 le16_to_cpu(txpower.channel),
1721 txpower.band,
14577f23
MA		 1722 txpower.power[i].tpc.tx_gain,
1723 txpower.power[i].tpc.dsp_atten,
1724 txpower.power[i].rate);
1725 }
1726 /* Fill CCK rates */
1727 for (rate_idx = IWL_FIRST_CCK_RATE;
1728 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1729 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1730 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1731
1732 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1733 le16_to_cpu(txpower.channel),
1734 txpower.band,
1735 txpower.power[i].tpc.tx_gain,
1736 txpower.power[i].tpc.dsp_atten,
1737 txpower.power[i].rate);
b481de9c
ZY		 1738 }
1739
bb8c093b
CH		 1740 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1741 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1742
1743}
1744
1745/**
bb8c093b 1746 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1747 * @ch_info: Channel to update. Uses power_info.requested_power.
1748 *
1749 * Replace requested_power and base_power_index ch_info fields for
1750 * one channel.
1751 *
1752 * Called if user or spectrum management changes power preferences.
1753 * Takes into account h/w and modulation limitations (clip power).
1754 *
1755 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1756 *
1757 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1758 * properly fill out the scan powers, and actual h/w gain settings,
1759 * and send changes to NIC
1760 */
bb8c093b
CH		 1761static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1762 struct iwl3945_channel_info *ch_info)
b481de9c 1763{
bb8c093b 1764 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1765 int power_changed = 0;
1766 int i;
1767 const s8 *clip_pwrs;
1768 int power;
1769
1770 /* Get this chnlgrp's rate-to-max/clip-powers table */
1771 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1772
1773 /* Get this channel's rate-to-current-power settings table */
1774 power_info = ch_info->power_info;
1775
1776 /* update OFDM Txpower settings */
14577f23 1777 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1778 i++, ++power_info) {
1779 int delta_idx;
1780
1781 /* limit new power to be no more than h/w capability */
1782 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1783 if (power == power_info->requested_power)
1784 continue;
1785
1786 /* find difference between old and new requested powers,
1787 * update base (non-temp-compensated) power index */
1788 delta_idx = (power - power_info->requested_power) * 2;
1789 power_info->base_power_index -= delta_idx;
1790
1791 /* save new requested power value */
1792 power_info->requested_power = power;
1793
1794 power_changed = 1;
1795 }
1796
1797 /* update CCK Txpower settings, based on OFDM 12M setting ...
1798 * ... all CCK power settings for a given channel are the *same*. */
1799 if (power_changed) {
1800 power =
14577f23 1801 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1802 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1803
bb8c093b 1804 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1805 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1806 power_info->requested_power = power;
1807 power_info->base_power_index =
14577f23 1808 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1809 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1810 ++power_info;
1811 }
1812 }
1813
1814 return 0;
1815}
1816
1817/**
bb8c093b 1818 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1819 *
1820 * NOTE: Returned power limit may be less (but not more) than requested,
1821 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1822 * (no consideration for h/w clipping limitations).
1823 */
bb8c093b 1824static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
b481de9c
ZY		 1825{
1826 s8 max_power;
1827
1828#if 0
1829 /* if we're using TGd limits, use lower of TGd or EEPROM */
1830 if (ch_info->tgd_data.max_power != 0)
1831 max_power = min(ch_info->tgd_data.max_power,
1832 ch_info->eeprom.max_power_avg);
1833
1834 /* else just use EEPROM limits */
1835 else
1836#endif
1837 max_power = ch_info->eeprom.max_power_avg;
1838
1839 return min(max_power, ch_info->max_power_avg);
1840}
1841
1842/**
bb8c093b 1843 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1844 *
1845 * Compensate txpower settings of *all* channels for temperature.
1846 * This only accounts for the difference between current temperature
1847 * and the factory calibration temperatures, and bases the new settings
1848 * on the channel's base_power_index.
1849 *
1850 * If RxOn is "associated", this sends the new Txpower to NIC!
1851 */
bb8c093b 1852static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
b481de9c 1853{
bb8c093b 1854 struct iwl3945_channel_info *ch_info = NULL;
b481de9c
ZY		 1855 int delta_index;
1856 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1857 u8 a_band;
1858 u8 rate_index;
1859 u8 scan_tbl_index;
1860 u8 i;
1861 int ref_temp;
1862 int temperature = priv->temperature;
1863
1864 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1865 for (i = 0; i < priv->channel_count; i++) {
1866 ch_info = &priv->channel_info[i];
1867 a_band = is_channel_a_band(ch_info);
1868
1869 /* Get this chnlgrp's factory calibration temperature */
1870 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1871 temperature;
1872
a96a27f9 1873 /* get power index adjustment based on current and factory
b481de9c 1874 * temps */
bb8c093b 1875 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1876 ref_temp);
1877
1878 /* set tx power value for all rates, OFDM and CCK */
1879 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1880 rate_index++) {
1881 int power_idx =
1882 ch_info->power_info[rate_index].base_power_index;
1883
1884 /* temperature compensate */
1885 power_idx += delta_index;
1886
1887 /* stay within table range */
bb8c093b 1888 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1889 ch_info->power_info[rate_index].
1890 power_table_index = (u8) power_idx;
1891 ch_info->power_info[rate_index].tpc =
1892 power_gain_table[a_band][power_idx];
1893 }
1894
1895 /* Get this chnlgrp's rate-to-max/clip-powers table */
1896 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1897
1898 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1899 for (scan_tbl_index = 0;
1900 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1901 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1902 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1903 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1904 actual_index, clip_pwrs,
1905 ch_info, a_band);
1906 }
1907 }
1908
1909 /* send Txpower command for current channel to ucode */
bb8c093b 1910 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1911}
1912
bb8c093b 1913int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
b481de9c 1914{
bb8c093b 1915 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 1916 s8 max_power;
1917 u8 a_band;
1918 u8 i;
1919
1920 if (priv->user_txpower_limit == power) {
1921 IWL_DEBUG_POWER("Requested Tx power same as current "
1922 "limit: %ddBm.\n", power);
1923 return 0;
1924 }
1925
1926 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1927 priv->user_txpower_limit = power;
1928
1929 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1930
1931 for (i = 0; i < priv->channel_count; i++) {
1932 ch_info = &priv->channel_info[i];
1933 a_band = is_channel_a_band(ch_info);
1934
1935 /* find minimum power of all user and regulatory constraints
1936 * (does not consider h/w clipping limitations) */
bb8c093b 1937 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1938 max_power = min(power, max_power);
1939 if (max_power != ch_info->curr_txpow) {
1940 ch_info->curr_txpow = max_power;
1941
1942 /* this considers the h/w clipping limitations */
bb8c093b 1943 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1944 }
1945 }
1946
1947 /* update txpower settings for all channels,
1948 * send to NIC if associated. */
1949 is_temp_calib_needed(priv);
bb8c093b 1950 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1951
1952 return 0;
1953}
1954
1955/* will add 3945 channel switch cmd handling later */
bb8c093b 1956int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
b481de9c
ZY		 1957{
1958 return 0;
1959}
1960
1961/**
1962 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1963 *
1964 * -- reset periodic timer
1965 * -- see if temp has changed enough to warrant re-calibration ... if so:
1966 * -- correct coeffs for temp (can reset temp timer)
1967 * -- save this temp as "last",
1968 * -- send new set of gain settings to NIC
1969 * NOTE: This should continue working, even when we're not associated,
1970 * so we can keep our internal table of scan powers current. */
bb8c093b 1971void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
b481de9c
ZY		 1972{
1973 /* This will kick in the "brute force"
bb8c093b 1974 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1975 if (!is_temp_calib_needed(priv))
1976 goto reschedule;
1977
1978 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1979 * This is based *only* on current temperature,
1980 * ignoring any previous power measurements */
bb8c093b 1981 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1982
1983 reschedule:
1984 queue_delayed_work(priv->workqueue,
1985 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1986}
1987
416e1438 1988static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1989{
bb8c093b 1990 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
b481de9c
ZY		 1991 thermal_periodic.work);
1992
1993 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1994 return;
1995
1996 mutex_lock(&priv->mutex);
1997 iwl3945_reg_txpower_periodic(priv);
1998 mutex_unlock(&priv->mutex);
1999}
2000
2001/**
bb8c093b 2002 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2003 * for the channel.
2004 *
2005 * This function is used when initializing channel-info structs.
2006 *
2007 * NOTE: These channel groups do *NOT* match the bands above!
2008 * These channel groups are based on factory-tested channels;
2009 * on A-band, EEPROM's "group frequency" entries represent the top
2010 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2011 */
bb8c093b
CH		 2012static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
2013 const struct iwl3945_channel_info *ch_info)
b481de9c 2014{
bb8c093b 2015 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
b481de9c
ZY		 2016 u8 group;
2017 u16 group_index = 0; /* based on factory calib frequencies */
2018 u8 grp_channel;
2019
2020 /* Find the group index for the channel ... don't use index 1(?) */
2021 if (is_channel_a_band(ch_info)) {
2022 for (group = 1; group < 5; group++) {
2023 grp_channel = ch_grp[group].group_channel;
2024 if (ch_info->channel <= grp_channel) {
2025 group_index = group;
2026 break;
2027 }
2028 }
2029 /* group 4 has a few channels *above* its factory cal freq */
2030 if (group == 5)
2031 group_index = 4;
2032 } else
2033 group_index = 0; /* 2.4 GHz, group 0 */
2034
2035 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2036 group_index);
2037 return group_index;
2038}
2039
2040/**
bb8c093b 2041 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2042 *
2043 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2044 * into radio/DSP gain settings table for requested power.
2045 */
bb8c093b 2046static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
b481de9c
ZY		 2047 s8 requested_power,
2048 s32 setting_index, s32 *new_index)
2049{
bb8c093b 2050 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2051 s32 index0, index1;
2052 s32 power = 2 * requested_power;
2053 s32 i;
bb8c093b 2054 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2055 s32 gains0, gains1;
2056 s32 res;
2057 s32 denominator;
2058
2059 chnl_grp = &priv->eeprom.groups[setting_index];
2060 samples = chnl_grp->samples;
2061 for (i = 0; i < 5; i++) {
2062 if (power == samples[i].power) {
2063 *new_index = samples[i].gain_index;
2064 return 0;
2065 }
2066 }
2067
2068 if (power > samples[1].power) {
2069 index0 = 0;
2070 index1 = 1;
2071 } else if (power > samples[2].power) {
2072 index0 = 1;
2073 index1 = 2;
2074 } else if (power > samples[3].power) {
2075 index0 = 2;
2076 index1 = 3;
2077 } else {
2078 index0 = 3;
2079 index1 = 4;
2080 }
2081
2082 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2083 if (denominator == 0)
2084 return -EINVAL;
2085 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2086 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2087 res = gains0 + (gains1 - gains0) *
2088 ((s32) power - (s32) samples[index0].power) / denominator +
2089 (1 << 18);
2090 *new_index = res >> 19;
2091 return 0;
2092}
2093
bb8c093b 2094static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
b481de9c
ZY		 2095{
2096 u32 i;
2097 s32 rate_index;
bb8c093b 2098 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2099
2100 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2101
2102 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2103 s8 *clip_pwrs; /* table of power levels for each rate */
2104 s8 satur_pwr; /* saturation power for each chnl group */
2105 group = &priv->eeprom.groups[i];
2106
2107 /* sanity check on factory saturation power value */
2108 if (group->saturation_power < 40) {
2109 IWL_WARNING("Error: saturation power is %d, "
2110 "less than minimum expected 40\n",
2111 group->saturation_power);
2112 return;
2113 }
2114
2115 /*
2116 * Derive requested power levels for each rate, based on
2117 * hardware capabilities (saturation power for band).
2118 * Basic value is 3dB down from saturation, with further
2119 * power reductions for highest 3 data rates. These
2120 * backoffs provide headroom for high rate modulation
2121 * power peaks, without too much distortion (clipping).
2122 */
2123 /* we'll fill in this array with h/w max power levels */
2124 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
2125
2126 /* divide factory saturation power by 2 to find -3dB level */
2127 satur_pwr = (s8) (group->saturation_power >> 1);
2128
2129 /* fill in channel group's nominal powers for each rate */
2130 for (rate_index = 0;
2131 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2132 switch (rate_index) {
14577f23 2133 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2134 if (i == 0) /* B/G */
2135 *clip_pwrs = satur_pwr;
2136 else /* A */
2137 *clip_pwrs = satur_pwr - 5;
2138 break;
14577f23 2139 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2140 if (i == 0)
2141 *clip_pwrs = satur_pwr - 7;
2142 else
2143 *clip_pwrs = satur_pwr - 10;
2144 break;
14577f23 2145 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2146 if (i == 0)
2147 *clip_pwrs = satur_pwr - 9;
2148 else
2149 *clip_pwrs = satur_pwr - 12;
2150 break;
2151 default:
2152 *clip_pwrs = satur_pwr;
2153 break;
2154 }
2155 }
2156 }
2157}
2158
2159/**
2160 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2161 *
2162 * Second pass (during init) to set up priv->channel_info
2163 *
2164 * Set up Tx-power settings in our channel info database for each VALID
2165 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2166 * and current temperature.
2167 *
2168 * Since this is based on current temperature (at init time), these values may
2169 * not be valid for very long, but it gives us a starting/default point,
2170 * and allows us to active (i.e. using Tx) scan.
2171 *
2172 * This does *not* write values to NIC, just sets up our internal table.
2173 */
bb8c093b 2174int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
b481de9c 2175{
bb8c093b
CH		 2176 struct iwl3945_channel_info *ch_info = NULL;
2177 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2178 int delta_index;
2179 u8 rate_index;
2180 u8 scan_tbl_index;
2181 const s8 *clip_pwrs; /* array of power levels for each rate */
2182 u8 gain, dsp_atten;
2183 s8 power;
2184 u8 pwr_index, base_pwr_index, a_band;
2185 u8 i;
2186 int temperature;
2187
2188 /* save temperature reference,
2189 * so we can determine next time to calibrate */
bb8c093b 2190 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2191 priv->last_temperature = temperature;
2192
bb8c093b 2193 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2194
2195 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2196 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2197 i++, ch_info++) {
2198 a_band = is_channel_a_band(ch_info);
2199 if (!is_channel_valid(ch_info))
2200 continue;
2201
2202 /* find this channel's channel group (*not* "band") index */
2203 ch_info->group_index =
bb8c093b 2204 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2205
2206 /* Get this chnlgrp's rate->max/clip-powers table */
2207 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2208
2209 /* calculate power index *adjustment* value according to
2210 * diff between current temperature and factory temperature */
bb8c093b 2211 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 2212 priv->eeprom.groups[ch_info->group_index].
2213 temperature);
2214
2215 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2216 ch_info->channel, delta_index, temperature +
2217 IWL_TEMP_CONVERT);
2218
2219 /* set tx power value for all OFDM rates */
2220 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2221 rate_index++) {
25a4ccea 2222 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2223 int rc;
2224
2225 /* use channel group's clip-power table,
2226 * but don't exceed channel's max power */
2227 s8 pwr = min(ch_info->max_power_avg,
2228 clip_pwrs[rate_index]);
2229
2230 pwr_info = &ch_info->power_info[rate_index];
2231
2232 /* get base (i.e. at factory-measured temperature)
2233 * power table index for this rate's power */
bb8c093b 2234 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2235 ch_info->group_index,
2236 &power_idx);
2237 if (rc) {
2238 IWL_ERROR("Invalid power index\n");
2239 return rc;
2240 }
2241 pwr_info->base_power_index = (u8) power_idx;
2242
2243 /* temperature compensate */
2244 power_idx += delta_index;
2245
2246 /* stay within range of gain table */
bb8c093b 2247 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2248
bb8c093b 2249 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2250 pwr_info->requested_power = pwr;
2251 pwr_info->power_table_index = (u8) power_idx;
2252 pwr_info->tpc.tx_gain =
2253 power_gain_table[a_band][power_idx].tx_gain;
2254 pwr_info->tpc.dsp_atten =
2255 power_gain_table[a_band][power_idx].dsp_atten;
2256 }
2257
2258 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2259 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2260 power = pwr_info->requested_power +
2261 IWL_CCK_FROM_OFDM_POWER_DIFF;
2262 pwr_index = pwr_info->power_table_index +
2263 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2264 base_pwr_index = pwr_info->base_power_index +
2265 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2266
2267 /* stay within table range */
bb8c093b 2268 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2269 gain = power_gain_table[a_band][pwr_index].tx_gain;
2270 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2271
bb8c093b 2272 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2273 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2274 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2275 for (rate_index = 0;
2276 rate_index < IWL_CCK_RATES; rate_index++) {
2277 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2278 pwr_info->requested_power = power;
2279 pwr_info->power_table_index = pwr_index;
2280 pwr_info->base_power_index = base_pwr_index;
2281 pwr_info->tpc.tx_gain = gain;
2282 pwr_info->tpc.dsp_atten = dsp_atten;
2283 }
2284
2285 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2286 for (scan_tbl_index = 0;
2287 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2288 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2289 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2290 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2291 actual_index, clip_pwrs, ch_info, a_band);
2292 }
2293 }
2294
2295 return 0;
2296}
2297
bb8c093b 2298int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 2299{
2300 int rc;
2301 unsigned long flags;
2302
2303 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2304 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2305 if (rc) {
2306 spin_unlock_irqrestore(&priv->lock, flags);
2307 return rc;
2308 }
2309
bb8c093b 2310 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
73d7b5ac
ZY		 2311 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS,
2312 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c
ZY		 2313 if (rc < 0)
2314 IWL_ERROR("Can't stop Rx DMA.\n");
2315
bb8c093b 2316 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2317 spin_unlock_irqrestore(&priv->lock, flags);
2318
2319 return 0;
2320}
2321
bb8c093b 2322int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2323{
2324 int rc;
2325 unsigned long flags;
2326 int txq_id = txq->q.id;
2327
bb8c093b 2328 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2329
2330 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2331
2332 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2333 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2334 if (rc) {
2335 spin_unlock_irqrestore(&priv->lock, flags);
2336 return rc;
2337 }
bb8c093b
CH		 2338 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2339 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
b481de9c 2340
bb8c093b 2341 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
b481de9c
ZY		 2342 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2343 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2344 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2345 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2346 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
bb8c093b 2347 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2348
2349 /* fake read to flush all prev. writes */
bb8c093b 2350 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
b481de9c
ZY		 2351 spin_unlock_irqrestore(&priv->lock, flags);
2352
2353 return 0;
2354}
2355
bb8c093b 2356int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
b481de9c 2357{
bb8c093b 2358 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2359
2360 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2361}
2362
2363/**
2364 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2365 */
bb8c093b 2366int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
b481de9c 2367{
14577f23 2368 int rc, i, index, prev_index;
bb8c093b 2369 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2370 .reserved = {0, 0, 0},
2371 };
bb8c093b 2372 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2373
bb8c093b
CH		 2374 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2375 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2376
2377 table[index].rate_n_flags =
bb8c093b 2378 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2379 table[index].try_cnt = priv->retry_rate;
bb8c093b 2380 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2381 table[index].next_rate_index =
2382 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2383 }
2384
8318d78a
JB		 2385 switch (priv->band) {
2386 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2387 IWL_DEBUG_RATE("Select A mode rate scale\n");
2388 /* If one of the following CCK rates is used,
2389 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2390 for (i = IWL_RATE_1M_INDEX_TABLE;
2391 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2392 table[i].next_rate_index =
2393 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2394
2395 /* Don't fall back to CCK rates */
7262796a
AM		 2396 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2397 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2398
2399 /* Don't drop out of OFDM rates */
14577f23 2400 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2401 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2402 break;
2403
8318d78a
JB		 2404 case IEEE80211_BAND_2GHZ:
2405 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2406 /* If an OFDM rate is used, have it fall back to the
2407 * 1M CCK rates */
b481de9c 2408
7262796a
AM		 2409 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2410 iwl3945_is_associated(priv)) {
2411
2412 index = IWL_FIRST_CCK_RATE;
2413 for (i = IWL_RATE_6M_INDEX_TABLE;
2414 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2415 table[i].next_rate_index =
2416 iwl3945_rates[index].table_rs_index;
2417
2418 index = IWL_RATE_11M_INDEX_TABLE;
2419 /* CCK shouldn't fall back to OFDM... */
2420 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2421 }
b481de9c
ZY		 2422 break;
2423
2424 default:
8318d78a 2425 WARN_ON(1);
b481de9c
ZY		 2426 break;
2427 }
2428
2429 /* Update the rate scaling for control frame Tx */
2430 rate_cmd.table_id = 0;
bb8c093b 2431 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2432 &rate_cmd);
2433 if (rc)
2434 return rc;
2435
2436 /* Update the rate scaling for data frame Tx */
2437 rate_cmd.table_id = 1;
bb8c093b 2438 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2439 &rate_cmd);
2440}
2441
796083cb 2442/* Called when initializing driver */
bb8c093b 2443int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 2444{
2445 memset((void *)&priv->hw_setting, 0,
bb8c093b 2446 sizeof(struct iwl3945_driver_hw_info));
b481de9c
ZY		 2447
2448 priv->hw_setting.shared_virt =
2449 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2450 sizeof(struct iwl3945_shared),
b481de9c
ZY		 2451 &priv->hw_setting.shared_phys);
2452
2453 if (!priv->hw_setting.shared_virt) {
2454 IWL_ERROR("failed to allocate pci memory\n");
2455 mutex_unlock(&priv->mutex);
2456 return -ENOMEM;
2457 }
2458
9ee1ba47
RR		 2459 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2460 priv->hw_setting.max_pkt_size = 2342;
bb8c093b 2461 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
b481de9c
ZY		 2462 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2463 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
b481de9c
ZY		 2464 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2465 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822
TW		 2466
2467 priv->hw_setting.tx_ant_num = 2;
b481de9c
ZY		 2468 return 0;
2469}
2470
bb8c093b
CH		 2471unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2472 struct iwl3945_frame *frame, u8 rate)
b481de9c 2473{
bb8c093b 2474 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2475 unsigned int frame_size;
2476
bb8c093b 2477 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2478 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2479
a4062b8f 2480 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 2481 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2482
bb8c093b 2483 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2484 tx_beacon_cmd->frame,
b481de9c
ZY		 2485 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2486
2487 BUG_ON(frame_size > MAX_MPDU_SIZE);
2488 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2489
2490 tx_beacon_cmd->tx.rate = rate;
2491 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2492 TX_CMD_FLG_TSF_MSK);
2493
14577f23
MA		 2494 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2495 tx_beacon_cmd->tx.supp_rates[0] =
2496 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2497
b481de9c 2498 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2499 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2500
3ac7f146 2501 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2502}
2503
bb8c093b 2504void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
b481de9c 2505{
91c066f2 2506 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2507 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2508}
2509
bb8c093b 2510void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2511{
2512 INIT_DELAYED_WORK(&priv->thermal_periodic,
2513 iwl3945_bg_reg_txpower_periodic);
2514}
2515
bb8c093b 2516void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2517{
2518 cancel_delayed_work(&priv->thermal_periodic);
2519}
2520
82b9a121
TW		 2521static struct iwl_3945_cfg iwl3945_bg_cfg = {
2522 .name = "3945BG",
a0987a8d
RC		 2523 .fw_name_pre = IWL3945_FW_PRE,
2524 .ucode_api_max = IWL3945_UCODE_API_MAX,
2525 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121
TW		 2526 .sku = IWL_SKU_G,
2527};
2528
2529static struct iwl_3945_cfg iwl3945_abg_cfg = {
2530 .name = "3945ABG",
a0987a8d
RC		 2531 .fw_name_pre = IWL3945_FW_PRE,
2532 .ucode_api_max = IWL3945_UCODE_API_MAX,
2533 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121
TW		 2534 .sku = IWL_SKU_A|IWL_SKU_G,
2535};
2536
bb8c093b 2537struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2538 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2539 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2540 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2541 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2542 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2543 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2544 {0}
2545};
2546
bb8c093b 2547MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)