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iwl3945: Use the iwlcore geos routines
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
b481de9c 44#include "iwl-3945.h"
e6148917 45#include "iwl-eeprom.h"
5d08cd1d 46#include "iwl-helpers.h"
5747d47f 47#include "iwl-core.h"
d9829a67 48#include "iwl-agn-rs.h"
b481de9c
ZY		 49
50#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
51 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
52 IWL_RATE_##r##M_IEEE, \
53 IWL_RATE_##ip##M_INDEX, \
54 IWL_RATE_##in##M_INDEX, \
55 IWL_RATE_##rp##M_INDEX, \
56 IWL_RATE_##rn##M_INDEX, \
57 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 58 IWL_RATE_##np##M_INDEX, \
59 IWL_RATE_##r##M_INDEX_TABLE, \
60 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 61
62/*
63 * Parameter order:
64 * rate, prev rate, next rate, prev tgg rate, next tgg rate
65 *
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
68 *
69 */
d9829a67 70const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 71 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 75 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 83};
84
bb8c093b 85/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 86#define IWL_EVT_DISABLE (0)
87#define IWL_EVT_DISABLE_SIZE (1532/32)
88
89/**
bb8c093b 90 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 91 *
92 * Disable an event by writing "1"s into "disable"
93 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
94 * Default values of 0 enable uCode events to be logged.
95 * Use for only special debugging. This function is just a placeholder as-is,
96 * you'll need to provide the special bits! ...
97 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 98void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 99{
af7cca2a 100 int ret;
b481de9c
ZY		 101 int i;
102 u32 base; /* SRAM address of event log header */
103 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
104 u32 array_size; /* # of u32 entries in array */
105 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
106 0x00000000, /* 31 - 0 Event id numbers */
107 0x00000000, /* 63 - 32 */
108 0x00000000, /* 95 - 64 */
109 0x00000000, /* 127 - 96 */
110 0x00000000, /* 159 - 128 */
111 0x00000000, /* 191 - 160 */
112 0x00000000, /* 223 - 192 */
113 0x00000000, /* 255 - 224 */
114 0x00000000, /* 287 - 256 */
115 0x00000000, /* 319 - 288 */
116 0x00000000, /* 351 - 320 */
117 0x00000000, /* 383 - 352 */
118 0x00000000, /* 415 - 384 */
119 0x00000000, /* 447 - 416 */
120 0x00000000, /* 479 - 448 */
121 0x00000000, /* 511 - 480 */
122 0x00000000, /* 543 - 512 */
123 0x00000000, /* 575 - 544 */
124 0x00000000, /* 607 - 576 */
125 0x00000000, /* 639 - 608 */
126 0x00000000, /* 671 - 640 */
127 0x00000000, /* 703 - 672 */
128 0x00000000, /* 735 - 704 */
129 0x00000000, /* 767 - 736 */
130 0x00000000, /* 799 - 768 */
131 0x00000000, /* 831 - 800 */
132 0x00000000, /* 863 - 832 */
133 0x00000000, /* 895 - 864 */
134 0x00000000, /* 927 - 896 */
135 0x00000000, /* 959 - 928 */
136 0x00000000, /* 991 - 960 */
137 0x00000000, /* 1023 - 992 */
138 0x00000000, /* 1055 - 1024 */
139 0x00000000, /* 1087 - 1056 */
140 0x00000000, /* 1119 - 1088 */
141 0x00000000, /* 1151 - 1120 */
142 0x00000000, /* 1183 - 1152 */
143 0x00000000, /* 1215 - 1184 */
144 0x00000000, /* 1247 - 1216 */
145 0x00000000, /* 1279 - 1248 */
146 0x00000000, /* 1311 - 1280 */
147 0x00000000, /* 1343 - 1312 */
148 0x00000000, /* 1375 - 1344 */
149 0x00000000, /* 1407 - 1376 */
150 0x00000000, /* 1439 - 1408 */
151 0x00000000, /* 1471 - 1440 */
152 0x00000000, /* 1503 - 1472 */
153 };
154
155 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 156 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 157 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 158 return;
159 }
160
5d49f498 161 ret = iwl_grab_nic_access(priv);
af7cca2a 162 if (ret) {
39aadf8c 163 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 164 return;
165 }
166
5d49f498
AK		 167 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
168 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
169 iwl_release_nic_access(priv);
b481de9c
ZY		 170
171 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
172 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
173 disable_ptr);
5d49f498 174 ret = iwl_grab_nic_access(priv);
b481de9c 175 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 176 iwl_write_targ_mem(priv,
af7cca2a
TW		 177 disable_ptr + (i * sizeof(u32)),
178 evt_disable[i]);
b481de9c 179
5d49f498 180 iwl_release_nic_access(priv);
b481de9c
ZY		 181 } else {
182 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
183 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
184 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
185 disable_ptr, array_size);
186 }
187
188}
189
17744ff6
TW		 190static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
191{
192 int idx;
193
194 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
195 if (iwl3945_rates[idx].plcp == plcp)
196 return idx;
197 return -1;
198}
199
b481de9c
ZY		 200/**
201 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
202 * @priv: eeprom and antenna fields are used to determine antenna flags
203 *
f2c7e521 204 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
b481de9c
ZY		 205 * priv->antenna specifies the antenna diversity mode:
206 *
a96a27f9 207 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 208 * IWL_ANTENNA_MAIN - Force MAIN antenna
209 * IWL_ANTENNA_AUX - Force AUX antenna
210 */
4a8a4322 211__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
b481de9c 212{
e6148917
SO		 213 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
214
b481de9c
ZY		 215 switch (priv->antenna) {
216 case IWL_ANTENNA_DIVERSITY:
217 return 0;
218
219 case IWL_ANTENNA_MAIN:
e6148917 220 if (eeprom->antenna_switch_type)
b481de9c
ZY		 221 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
222 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
223
224 case IWL_ANTENNA_AUX:
e6148917 225 if (eeprom->antenna_switch_type)
b481de9c
ZY		 226 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
227 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
228 }
229
230 /* bad antenna selector value */
15b1687c 231 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
b481de9c
ZY		 232 return 0; /* "diversity" is default if error */
233}
234
91c066f2
TW		 235#ifdef CONFIG_IWL3945_DEBUG
236#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
237
238static const char *iwl3945_get_tx_fail_reason(u32 status)
239{
240 switch (status & TX_STATUS_MSK) {
241 case TX_STATUS_SUCCESS:
242 return "SUCCESS";
243 TX_STATUS_ENTRY(SHORT_LIMIT);
244 TX_STATUS_ENTRY(LONG_LIMIT);
245 TX_STATUS_ENTRY(FIFO_UNDERRUN);
246 TX_STATUS_ENTRY(MGMNT_ABORT);
247 TX_STATUS_ENTRY(NEXT_FRAG);
248 TX_STATUS_ENTRY(LIFE_EXPIRE);
249 TX_STATUS_ENTRY(DEST_PS);
250 TX_STATUS_ENTRY(ABORTED);
251 TX_STATUS_ENTRY(BT_RETRY);
252 TX_STATUS_ENTRY(STA_INVALID);
253 TX_STATUS_ENTRY(FRAG_DROPPED);
254 TX_STATUS_ENTRY(TID_DISABLE);
255 TX_STATUS_ENTRY(FRAME_FLUSHED);
256 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
257 TX_STATUS_ENTRY(TX_LOCKED);
258 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
259 }
260
261 return "UNKNOWN";
262}
263#else
264static inline const char *iwl3945_get_tx_fail_reason(u32 status)
265{
266 return "";
267}
268#endif
269
e6a9854b
JB		 270/*
271 * get ieee prev rate from rate scale table.
272 * for A and B mode we need to overright prev
273 * value
274 */
4a8a4322 275int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 276{
277 int next_rate = iwl3945_get_prev_ieee_rate(rate);
278
279 switch (priv->band) {
280 case IEEE80211_BAND_5GHZ:
281 if (rate == IWL_RATE_12M_INDEX)
282 next_rate = IWL_RATE_9M_INDEX;
283 else if (rate == IWL_RATE_6M_INDEX)
284 next_rate = IWL_RATE_6M_INDEX;
285 break;
7262796a
AM		 286 case IEEE80211_BAND_2GHZ:
287 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
288 iwl3945_is_associated(priv)) {
289 if (rate == IWL_RATE_11M_INDEX)
290 next_rate = IWL_RATE_5M_INDEX;
291 }
e6a9854b 292 break;
7262796a 293
e6a9854b
JB		 294 default:
295 break;
296 }
297
298 return next_rate;
299}
300
91c066f2
TW		 301
302/**
303 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
304 *
305 * When FW advances 'R' index, all entries between old and new 'R' index
306 * need to be reclaimed. As result, some free space forms. If there is
307 * enough free space (> low mark), wake the stack that feeds us.
308 */
4a8a4322 309static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 310 int txq_id, int index)
311{
188cf6c7 312 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 313 struct iwl_queue *q = &txq->q;
dbb6654c 314 struct iwl_tx_info *tx_info;
91c066f2
TW		 315
316 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
317
318 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
319 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
320
321 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 322 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 323 tx_info->skb[0] = NULL;
7aaa1d79 324 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 325 }
326
d20b3c65 327 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 328 (txq_id != IWL_CMD_QUEUE_NUM) &&
329 priv->mac80211_registered)
330 ieee80211_wake_queue(priv->hw, txq_id);
331}
332
333/**
334 * iwl3945_rx_reply_tx - Handle Tx response
335 */
4a8a4322 336static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 337 struct iwl_rx_mem_buffer *rxb)
91c066f2 338{
3d24a9f7 339 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 340 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
341 int txq_id = SEQ_TO_QUEUE(sequence);
342 int index = SEQ_TO_INDEX(sequence);
188cf6c7 343 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 344 struct ieee80211_tx_info *info;
91c066f2
TW		 345 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
346 u32 status = le32_to_cpu(tx_resp->status);
347 int rate_idx;
74221d07 348 int fail;
91c066f2 349
625a381a 350 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 351 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 352 "is out of range [0-%d] %d %d\n", txq_id,
353 index, txq->q.n_bd, txq->q.write_ptr,
354 txq->q.read_ptr);
355 return;
356 }
357
e039fa4a 358 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 359 ieee80211_tx_info_clear_status(info);
360
361 /* Fill the MRR chain with some info about on-chip retransmissions */
362 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
363 if (info->band == IEEE80211_BAND_5GHZ)
364 rate_idx -= IWL_FIRST_OFDM_RATE;
365
366 fail = tx_resp->failure_frame;
74221d07
AM		 367
368 info->status.rates[0].idx = rate_idx;
369 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 370
91c066f2 371 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 372 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
373 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 374
375 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
376 txq_id, iwl3945_get_tx_fail_reason(status), status,
377 tx_resp->rate, tx_resp->failure_frame);
378
91c066f2
TW		 379 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
380 iwl3945_tx_queue_reclaim(priv, txq_id, index);
381
382 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 383 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 384}
385
386
387
b481de9c
ZY		 388/*****************************************************************************
389 *
390 * Intel PRO/Wireless 3945ABG/BG Network Connection
391 *
392 * RX handler implementations
393 *
b481de9c
ZY		 394 *****************************************************************************/
395
4a8a4322 396void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 397{
3d24a9f7 398 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 399 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 400 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 401 le32_to_cpu(pkt->len));
402
f2c7e521 403 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 404
ab53d8af
MA		 405 iwl3945_led_background(priv);
406
b481de9c
ZY		 407 priv->last_statistics_time = jiffies;
408}
409
17744ff6
TW		 410/******************************************************************************
411 *
412 * Misc. internal state and helper functions
413 *
414 ******************************************************************************/
415#ifdef CONFIG_IWL3945_DEBUG
416
417/**
418 * iwl3945_report_frame - dump frame to syslog during debug sessions
419 *
420 * You may hack this function to show different aspects of received frames,
421 * including selective frame dumps.
422 * group100 parameter selects whether to show 1 out of 100 good frames.
423 */
4a8a4322 424static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 425 struct iwl_rx_packet *pkt,
17744ff6
TW		 426 struct ieee80211_hdr *header, int group100)
427{
428 u32 to_us;
429 u32 print_summary = 0;
430 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
431 u32 hundred = 0;
432 u32 dataframe = 0;
fd7c8a40 433 __le16 fc;
17744ff6
TW		 434 u16 seq_ctl;
435 u16 channel;
436 u16 phy_flags;
437 u16 length;
438 u16 status;
439 u16 bcn_tmr;
440 u32 tsf_low;
441 u64 tsf;
442 u8 rssi;
443 u8 agc;
444 u16 sig_avg;
445 u16 noise_diff;
446 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
447 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
448 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
449 u8 *data = IWL_RX_DATA(pkt);
450
451 /* MAC header */
fd7c8a40 452 fc = header->frame_control;
17744ff6
TW		 453 seq_ctl = le16_to_cpu(header->seq_ctrl);
454
455 /* metadata */
456 channel = le16_to_cpu(rx_hdr->channel);
457 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
458 length = le16_to_cpu(rx_hdr->len);
459
460 /* end-of-frame status and timestamp */
461 status = le32_to_cpu(rx_end->status);
462 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
463 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
464 tsf = le64_to_cpu(rx_end->timestamp);
465
466 /* signal statistics */
467 rssi = rx_stats->rssi;
468 agc = rx_stats->agc;
469 sig_avg = le16_to_cpu(rx_stats->sig_avg);
470 noise_diff = le16_to_cpu(rx_stats->noise_diff);
471
472 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
473
474 /* if data frame is to us and all is good,
475 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 476 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
477 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 478 dataframe = 1;
479 if (!group100)
480 print_summary = 1; /* print each frame */
481 else if (priv->framecnt_to_us < 100) {
482 priv->framecnt_to_us++;
483 print_summary = 0;
484 } else {
485 priv->framecnt_to_us = 0;
486 print_summary = 1;
487 hundred = 1;
488 }
489 } else {
490 /* print summary for all other frames */
491 print_summary = 1;
492 }
493
494 if (print_summary) {
495 char *title;
0ff1cca0 496 int rate;
17744ff6
TW		 497
498 if (hundred)
499 title = "100Frames";
fd7c8a40 500 else if (ieee80211_has_retry(fc))
17744ff6 501 title = "Retry";
fd7c8a40 502 else if (ieee80211_is_assoc_resp(fc))
17744ff6 503 title = "AscRsp";
fd7c8a40 504 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 505 title = "RasRsp";
fd7c8a40 506 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 507 title = "PrbRsp";
508 print_dump = 1; /* dump frame contents */
509 } else if (ieee80211_is_beacon(fc)) {
510 title = "Beacon";
511 print_dump = 1; /* dump frame contents */
512 } else if (ieee80211_is_atim(fc))
513 title = "ATIM";
514 else if (ieee80211_is_auth(fc))
515 title = "Auth";
516 else if (ieee80211_is_deauth(fc))
517 title = "DeAuth";
518 else if (ieee80211_is_disassoc(fc))
519 title = "DisAssoc";
520 else
521 title = "Frame";
522
523 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
524 if (rate == -1)
525 rate = 0;
526 else
527 rate = iwl3945_rates[rate].ieee / 2;
528
529 /* print frame summary.
530 * MAC addresses show just the last byte (for brevity),
531 * but you can hack it to show more, if you'd like to. */
532 if (dataframe)
533 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 534 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 535 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 536 length, rssi, channel, rate);
537 else {
538 /* src/dst addresses assume managed mode */
539 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
540 "src=0x%02x, rssi=%u, tim=%lu usec, "
541 "phy=0x%02x, chnl=%d\n",
fd7c8a40 542 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 543 header->addr3[5], rssi,
544 tsf_low - priv->scan_start_tsf,
545 phy_flags, channel);
546 }
547 }
548 if (print_dump)
40b8ec0b 549 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6
TW		 550}
551#else
4a8a4322 552static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 553 struct iwl_rx_packet *pkt,
17744ff6
TW		 554 struct ieee80211_hdr *header, int group100)
555{
556}
557#endif
558
4bd9b4f3 559/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 560static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 561 struct ieee80211_hdr *header)
562{
563 /* Filter incoming packets to determine if they are targeted toward
564 * this network, discarding packets coming from ourselves */
565 switch (priv->iw_mode) {
05c914fe 566 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 567 /* packets to our IBSS update information */
568 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 569 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 570 /* packets to our IBSS update information */
571 return !compare_ether_addr(header->addr2, priv->bssid);
572 default:
573 return 1;
574 }
575}
17744ff6 576
4a8a4322 577static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 578 struct iwl_rx_mem_buffer *rxb,
12342c47 579 struct ieee80211_rx_status *stats)
b481de9c 580{
3d24a9f7 581 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
699669f3 582#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 583 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 584#endif
bb8c093b
CH		 585 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
586 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 587 short len = le16_to_cpu(rx_hdr->len);
588
589 /* We received data from the HW, so stop the watchdog */
3d24a9f7 590 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
b481de9c
ZY		 591 IWL_DEBUG_DROP("Corruption detected!\n");
592 return;
593 }
594
595 /* We only process data packets if the interface is open */
596 if (unlikely(!priv->is_open)) {
597 IWL_DEBUG_DROP_LIMIT
598 ("Dropping packet while interface is not open.\n");
599 return;
600 }
b481de9c
ZY		 601
602 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
603 /* Set the size of the skb to the size of the frame */
604 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
605
9c74d9fb 606 if (!iwl3945_mod_params.sw_crypto)
bb8c093b 607 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 608 le32_to_cpu(rx_end->status), stats);
609
ab53d8af 610#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 611 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 612 priv->rxtxpackets += len;
613#endif
b481de9c
ZY		 614 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
615 rxb->skb = NULL;
616}
617
7878a5a4
MA		 618#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
619
4a8a4322 620static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 621 struct iwl_rx_mem_buffer *rxb)
b481de9c 622{
17744ff6
TW		 623 struct ieee80211_hdr *header;
624 struct ieee80211_rx_status rx_status;
3d24a9f7 625 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 626 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
627 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
628 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 629 int snr;
b481de9c
ZY		 630 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
631 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 632 u8 network_packet;
17744ff6 633
17744ff6
TW		 634 rx_status.flag = 0;
635 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 636 rx_status.freq =
c0186078 637 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 638 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
639 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
640
641 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 642 if (rx_status.band == IEEE80211_BAND_5GHZ)
643 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 644
6f0a2c4d
BR		 645 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
646 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
647
648 /* set the preamble flag if appropriate */
649 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
650 rx_status.flag |= RX_FLAG_SHORTPRE;
651
b481de9c
ZY		 652 if ((unlikely(rx_stats->phy_count > 20))) {
653 IWL_DEBUG_DROP
654 ("dsp size out of range [0,20]: "
655 "%d/n", rx_stats->phy_count);
656 return;
657 }
658
659 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
660 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
661 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
662 return;
663 }
664
56decd3c 665
b481de9c
ZY		 666
667 /* Convert 3945's rssi indicator to dBm */
250bdd21 668 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 669
670 /* Set default noise value to -127 */
671 if (priv->last_rx_noise == 0)
672 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
673
674 /* 3945 provides noise info for OFDM frames only.
675 * sig_avg and noise_diff are measured by the 3945's digital signal
676 * processor (DSP), and indicate linear levels of signal level and
677 * distortion/noise within the packet preamble after
678 * automatic gain control (AGC). sig_avg should stay fairly
679 * constant if the radio's AGC is working well.
680 * Since these values are linear (not dB or dBm), linear
681 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
682 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
683 * to obtain noise level in dBm.
17744ff6 684 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 685 if (rx_stats_noise_diff) {
686 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 687 rx_status.noise = rx_status.signal -
17744ff6 688 iwl3945_calc_db_from_ratio(snr);
566bfe5a 689 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 690 rx_status.noise);
b481de9c
ZY		 691
692 /* If noise info not available, calculate signal quality indicator (%)
693 * using just the dBm signal level. */
694 } else {
17744ff6 695 rx_status.noise = priv->last_rx_noise;
566bfe5a 696 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 697 }
698
699
700 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 701 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 702 rx_stats_sig_avg, rx_stats_noise_diff);
703
b481de9c
ZY		 704 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
705
bb8c093b 706 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 707
17744ff6
TW		 708 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
709 network_packet ? '*' : ' ',
710 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 711 rx_status.signal, rx_status.signal,
712 rx_status.noise, rx_status.rate_idx);
b481de9c 713
17744ff6 714#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 715 if (priv->debug_level & (IWL_DL_RX))
b481de9c 716 /* Set "1" to report good data frames in groups of 100 */
17744ff6 717 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 718#endif
719
720 if (network_packet) {
721 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
722 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 723 priv->last_rx_rssi = rx_status.signal;
17744ff6 724 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 725 }
726
12e5e22d 727 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 728}
729
7aaa1d79
SO		 730int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
731 struct iwl_tx_queue *txq,
732 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 733{
734 int count;
7aaa1d79 735 struct iwl_queue *q;
59606ffa 736 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 737
738 q = &txq->q;
59606ffa
SO		 739 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
740 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 741
742 if (reset)
743 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 744
745 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 746
747 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 748 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 749 NUM_TFD_CHUNKS);
750 return -EINVAL;
751 }
752
dbb6654c
WT		 753 tfd->tbs[count].addr = cpu_to_le32(addr);
754 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 755
756 count++;
757
758 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
759 TFD_CTL_PAD_SET(pad));
760
761 return 0;
762}
763
764/**
bb8c093b 765 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 766 *
767 * Does NOT advance any indexes
768 */
7aaa1d79 769void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 770{
59606ffa 771 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
dbb6654c 772 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
b481de9c
ZY		 773 struct pci_dev *dev = priv->pci_dev;
774 int i;
775 int counter;
776
777 /* classify bd */
778 if (txq->q.id == IWL_CMD_QUEUE_NUM)
779 /* nothing to cleanup after for host commands */
7aaa1d79 780 return;
b481de9c
ZY		 781
782 /* sanity check */
dbb6654c 783 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 784 if (counter > NUM_TFD_CHUNKS) {
15b1687c 785 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 786 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 787 return;
b481de9c
ZY		 788 }
789
790 /* unmap chunks if any */
791
792 for (i = 1; i < counter; i++) {
dbb6654c
WT		 793 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
794 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 795 if (txq->txb[txq->q.read_ptr].skb[0]) {
796 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
797 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 798 /* Can be called from interrupt context */
799 dev_kfree_skb_any(skb);
fc4b6853 800 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 801 }
802 }
803 }
7aaa1d79 804 return ;
b481de9c
ZY		 805}
806
4a8a4322 807u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 808{
c93007ef 809 int i, start = IWL_AP_ID;
b481de9c
ZY		 810 int ret = IWL_INVALID_STATION;
811 unsigned long flags;
812
c93007ef
SO		 813 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
814 (priv->iw_mode == NL80211_IFTYPE_AP))
815 start = IWL_STA_ID;
816
817 if (is_broadcast_ether_addr(addr))
3832ec9d 818 return priv->hw_params.bcast_sta_id;
c93007ef 819
b481de9c 820 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 821 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 822 if ((priv->stations_39[i].used) &&
b481de9c 823 (!compare_ether_addr
f2c7e521 824 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 825 ret = i;
826 goto out;
827 }
828
e174961c
JB		 829 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
830 addr, priv->num_stations);
b481de9c
ZY		 831 out:
832 spin_unlock_irqrestore(&priv->sta_lock, flags);
833 return ret;
834}
835
836/**
bb8c093b 837 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 838 *
839*/
c2d79b48 840void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 841 struct ieee80211_tx_info *info,
b481de9c
ZY		 842 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
843{
e039fa4a 844 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 845 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 846 u16 rate_mask;
847 int rate;
848 u8 rts_retry_limit;
849 u8 data_retry_limit;
850 __le32 tx_flags;
fd7c8a40 851 __le16 fc = hdr->frame_control;
c2d79b48 852 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 853
bb8c093b 854 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 855 tx_flags = tx->tx_flags;
b481de9c
ZY		 856
857 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 858 * in this running context */
b481de9c
ZY		 859 rate_mask = IWL_RATES_MASK;
860
b481de9c
ZY		 861 if (tx_id >= IWL_CMD_QUEUE_NUM)
862 rts_retry_limit = 3;
863 else
864 rts_retry_limit = 7;
865
fd7c8a40 866 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 867 data_retry_limit = 3;
868 if (data_retry_limit < rts_retry_limit)
869 rts_retry_limit = data_retry_limit;
870 } else
871 data_retry_limit = IWL_DEFAULT_TX_RETRY;
872
873 if (priv->data_retry_limit != -1)
874 data_retry_limit = priv->data_retry_limit;
875
fd7c8a40
HH		 876 if (ieee80211_is_mgmt(fc)) {
877 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
878 case cpu_to_le16(IEEE80211_STYPE_AUTH):
879 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
880 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
881 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 882 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
883 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
884 tx_flags |= TX_CMD_FLG_CTS_MSK;
885 }
886 break;
887 default:
888 break;
889 }
890 }
891
c2d79b48
WT		 892 tx->rts_retry_limit = rts_retry_limit;
893 tx->data_retry_limit = data_retry_limit;
894 tx->rate = rate;
895 tx->tx_flags = tx_flags;
b481de9c
ZY		 896
897 /* OFDM */
c2d79b48 898 tx->supp_rates[0] =
14577f23 899 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 900
901 /* CCK */
c2d79b48 902 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 903
904 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
905 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 906 tx->rate, le32_to_cpu(tx->tx_flags),
907 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 908}
909
4a8a4322 910u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 911{
912 unsigned long flags_spin;
bb8c093b 913 struct iwl3945_station_entry *station;
b481de9c
ZY		 914
915 if (sta_id == IWL_INVALID_STATION)
916 return IWL_INVALID_STATION;
917
918 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 919 station = &priv->stations_39[sta_id];
b481de9c
ZY		 920
921 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
922 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 923 station->sta.mode = STA_CONTROL_MODIFY_MSK;
924
925 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
926
bb8c093b 927 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 928 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
929 sta_id, tx_rate);
930 return sta_id;
931}
932
854682ed 933static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c
ZY		 934{
935 int rc;
936 unsigned long flags;
937
938 spin_lock_irqsave(&priv->lock, flags);
5d49f498 939 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 940 if (rc) {
941 spin_unlock_irqrestore(&priv->lock, flags);
942 return rc;
943 }
944
854682ed 945 if (src == IWL_PWR_SRC_VAUX) {
b481de9c
ZY		 946 u32 val;
947
948 rc = pci_read_config_dword(priv->pci_dev,
949 PCI_POWER_SOURCE, &val);
950 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
5d49f498 951 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 952 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
953 ~APMG_PS_CTRL_MSK_PWR_SRC);
5d49f498 954 iwl_release_nic_access(priv);
b481de9c 955
5d49f498 956 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 957 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
958 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
959 } else
5d49f498 960 iwl_release_nic_access(priv);
b481de9c 961 } else {
5d49f498 962 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 963 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
964 ~APMG_PS_CTRL_MSK_PWR_SRC);
965
5d49f498
AK		 966 iwl_release_nic_access(priv);
967 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 968 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
969 }
970 spin_unlock_irqrestore(&priv->lock, flags);
971
972 return rc;
973}
974
4a8a4322 975static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY		 976{
977 int rc;
978 unsigned long flags;
979
980 spin_lock_irqsave(&priv->lock, flags);
5d49f498 981 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 982 if (rc) {
983 spin_unlock_irqrestore(&priv->lock, flags);
984 return rc;
985 }
986
5d49f498 987 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 988 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 989 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
990 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 991 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
992 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
993 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
994 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
995 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
996 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
997 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
998 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 999
1000 /* fake read to flush all prev I/O */
5d49f498 1001 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 1002
5d49f498 1003 iwl_release_nic_access(priv);
b481de9c
ZY		 1004 spin_unlock_irqrestore(&priv->lock, flags);
1005
1006 return 0;
1007}
1008
4a8a4322 1009static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1010{
1011 int rc;
1012 unsigned long flags;
1013
1014 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1015 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1016 if (rc) {
1017 spin_unlock_irqrestore(&priv->lock, flags);
1018 return rc;
1019 }
1020
1021 /* bypass mode */
5d49f498 1022 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1023
1024 /* RA 0 is active */
5d49f498 1025 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1026
1027 /* all 6 fifo are active */
5d49f498 1028 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1029
5d49f498
AK		 1030 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1031 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1032 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1033 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1034
5d49f498 1035 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 1036 priv->shared_phys);
b481de9c 1037
5d49f498 1038 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1039 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1040 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1041 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1042 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1043 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1044 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1045 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1046
5d49f498 1047 iwl_release_nic_access(priv);
b481de9c
ZY		 1048 spin_unlock_irqrestore(&priv->lock, flags);
1049
1050 return 0;
1051}
1052
1053/**
1054 * iwl3945_txq_ctx_reset - Reset TX queue context
1055 *
1056 * Destroys all DMA structures and initialize them again
1057 */
4a8a4322 1058static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1059{
1060 int rc;
1061 int txq_id, slots_num;
1062
bb8c093b 1063 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1064
1065 /* Tx CMD queue */
1066 rc = iwl3945_tx_reset(priv);
1067 if (rc)
1068 goto error;
1069
1070 /* Tx queue(s) */
1071 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1072 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1073 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 1074 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1075 txq_id);
b481de9c 1076 if (rc) {
15b1687c 1077 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1078 goto error;
1079 }
1080 }
1081
1082 return rc;
1083
1084 error:
bb8c093b 1085 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1086 return rc;
1087}
1088
01ec616d 1089static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1090{
01ec616d 1091 int ret = 0;
b481de9c 1092
bb8c093b 1093 iwl3945_power_init_handle(priv);
b481de9c 1094
5d49f498 1095 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1096 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1097
1098 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1099 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1100 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1101
01ec616d
KA		 1102 /* set "initialization complete" bit to move adapter
1103 * D0U* --> D0A* state */
5d49f498 1104 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d
KA		 1105
1106 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1107 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1108 if (ret < 0) {
b481de9c 1109 IWL_DEBUG_INFO("Failed to init the card\n");
01ec616d 1110 goto out;
b481de9c
ZY		 1111 }
1112
01ec616d
KA		 1113 ret = iwl_grab_nic_access(priv);
1114 if (ret)
1115 goto out;
1116
1117 /* enable DMA */
1118 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1119 APMG_CLK_VAL_BSM_CLK_RQT);
1120
b481de9c 1121 udelay(20);
01ec616d
KA		 1122
1123 /* disable L1-Active */
5d49f498 1124 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1125 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1126
5d49f498 1127 iwl_release_nic_access(priv);
01ec616d
KA		 1128out:
1129 return ret;
1130}
b481de9c 1131
01ec616d
KA		 1132static void iwl3945_nic_config(struct iwl_priv *priv)
1133{
e6148917 1134 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1135 unsigned long flags;
1136 u8 rev_id = 0;
b481de9c 1137
b481de9c
ZY		 1138 spin_lock_irqsave(&priv->lock, flags);
1139
1140 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1141 IWL_DEBUG_INFO("RTP type \n");
1142 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1143 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
5d49f498 1144 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1145 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1146 } else {
6f83eaa1 1147 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
5d49f498 1148 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1149 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1150 }
1151
e6148917 1152 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
b481de9c 1153 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
5d49f498 1154 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1155 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1156 } else
1157 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1158
e6148917 1159 if ((eeprom->board_revision & 0xF0) == 0xD0) {
b481de9c 1160 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
e6148917 1161 eeprom->board_revision);
5d49f498 1162 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1163 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1164 } else {
1165 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
e6148917 1166 eeprom->board_revision);
5d49f498 1167 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1168 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1169 }
1170
e6148917 1171 if (eeprom->almgor_m_version <= 1) {
5d49f498 1172 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1173 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c 1174 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
e6148917 1175 eeprom->almgor_m_version);
b481de9c
ZY		 1176 } else {
1177 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
e6148917 1178 eeprom->almgor_m_version);
5d49f498 1179 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1180 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1181 }
1182 spin_unlock_irqrestore(&priv->lock, flags);
1183
e6148917 1184 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 1185 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1186
e6148917 1187 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c 1188 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1189}
1190
1191int iwl3945_hw_nic_init(struct iwl_priv *priv)
1192{
1193 u8 rev_id;
1194 int rc;
1195 unsigned long flags;
1196 struct iwl_rx_queue *rxq = &priv->rxq;
1197
1198 spin_lock_irqsave(&priv->lock, flags);
1199 priv->cfg->ops->lib->apm_ops.init(priv);
1200 spin_unlock_irqrestore(&priv->lock, flags);
1201
1202 /* Determine HW type */
1203 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1204 if (rc)
1205 return rc;
1206 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1207
854682ed
KA		 1208 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1209 if(rc)
1210 return rc;
1211
01ec616d 1212 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1213
1214 /* Allocate the RX queue, or reset if it is already allocated */
1215 if (!rxq->bd) {
51af3d3f 1216 rc = iwl_rx_queue_alloc(priv);
b481de9c 1217 if (rc) {
15b1687c 1218 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1219 return -ENOMEM;
1220 }
1221 } else
51af3d3f 1222 iwl_rx_queue_reset(priv, rxq);
b481de9c 1223
bb8c093b 1224 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1225
1226 iwl3945_rx_init(priv, rxq);
1227
1228 spin_lock_irqsave(&priv->lock, flags);
1229
1230 /* Look at using this instead:
1231 rxq->need_update = 1;
141c43a3 1232 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1233 */
1234
5d49f498 1235 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1236 if (rc) {
1237 spin_unlock_irqrestore(&priv->lock, flags);
1238 return rc;
1239 }
5d49f498
AK		 1240 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1241 iwl_release_nic_access(priv);
b481de9c
ZY		 1242
1243 spin_unlock_irqrestore(&priv->lock, flags);
1244
1245 rc = iwl3945_txq_ctx_reset(priv);
1246 if (rc)
1247 return rc;
1248
1249 set_bit(STATUS_INIT, &priv->status);
1250
1251 return 0;
1252}
1253
1254/**
bb8c093b 1255 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1256 *
1257 * Destroy all TX DMA queues and structures
1258 */
4a8a4322 1259void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1260{
1261 int txq_id;
1262
1263 /* Tx queues */
1264 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
a8e74e27 1265 iwl_tx_queue_free(priv, txq_id);
b481de9c
ZY		 1266}
1267
4a8a4322 1268void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1269{
bddadf86 1270 int txq_id;
b481de9c
ZY		 1271 unsigned long flags;
1272
1273 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1274 if (iwl_grab_nic_access(priv)) {
b481de9c 1275 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1276 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1277 return;
1278 }
1279
1280 /* stop SCD */
5d49f498 1281 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1282
1283 /* reset TFD queues */
bddadf86 1284 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
5d49f498
AK		 1285 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1286 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1287 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1288 1000);
1289 }
1290
5d49f498 1291 iwl_release_nic_access(priv);
b481de9c
ZY		 1292 spin_unlock_irqrestore(&priv->lock, flags);
1293
bb8c093b 1294 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1295}
1296
01ec616d 1297static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1298{
01ec616d 1299 int ret = 0;
b481de9c
ZY		 1300 unsigned long flags;
1301
1302 spin_lock_irqsave(&priv->lock, flags);
1303
1304 /* set stop master bit */
5d49f498 1305 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1306
01ec616d
KA		 1307 iwl_poll_direct_bit(priv, CSR_RESET,
1308 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1309
01ec616d
KA		 1310 if (ret < 0)
1311 goto out;
b481de9c 1312
01ec616d 1313out:
b481de9c
ZY		 1314 spin_unlock_irqrestore(&priv->lock, flags);
1315 IWL_DEBUG_INFO("stop master\n");
1316
01ec616d
KA		 1317 return ret;
1318}
1319
1320static void iwl3945_apm_stop(struct iwl_priv *priv)
1321{
1322 unsigned long flags;
1323
1324 iwl3945_apm_stop_master(priv);
1325
1326 spin_lock_irqsave(&priv->lock, flags);
1327
1328 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1329
1330 udelay(10);
1331 /* clear "init complete" move adapter D0A* --> D0U state */
1332 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1333 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1334}
1335
e52119c5 1336static int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c
ZY		 1337{
1338 int rc;
1339 unsigned long flags;
1340
01ec616d 1341 iwl3945_apm_stop_master(priv);
b481de9c
ZY		 1342
1343 spin_lock_irqsave(&priv->lock, flags);
1344
5d49f498 1345 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
e9414b6b
AM		 1346 udelay(10);
1347
1348 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 1349
5d49f498 1350 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1351 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1352
5d49f498 1353 rc = iwl_grab_nic_access(priv);
b481de9c 1354 if (!rc) {
5d49f498 1355 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1356 APMG_CLK_VAL_BSM_CLK_RQT);
1357
5d49f498
AK		 1358 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1359 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1360 0xFFFFFFFF);
1361
1362 /* enable DMA */
5d49f498 1363 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1364 APMG_CLK_VAL_DMA_CLK_RQT |
1365 APMG_CLK_VAL_BSM_CLK_RQT);
1366 udelay(10);
1367
5d49f498 1368 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1369 APMG_PS_CTRL_VAL_RESET_REQ);
1370 udelay(5);
5d49f498 1371 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1372 APMG_PS_CTRL_VAL_RESET_REQ);
5d49f498 1373 iwl_release_nic_access(priv);
b481de9c
ZY		 1374 }
1375
1376 /* Clear the 'host command active' bit... */
1377 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1378
1379 wake_up_interruptible(&priv->wait_command_queue);
1380 spin_unlock_irqrestore(&priv->lock, flags);
1381
1382 return rc;
1383}
1384
1385/**
bb8c093b 1386 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1387 * return index delta into power gain settings table
1388*/
bb8c093b 1389static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1390{
1391 return (new_reading - old_reading) * (-11) / 100;
1392}
1393
1394/**
bb8c093b 1395 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1396 */
bb8c093b 1397static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1398{
3ac7f146 1399 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1400}
1401
4a8a4322 1402int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1403{
5d49f498 1404 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1405}
1406
1407/**
bb8c093b 1408 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1409 * get the current temperature by reading from NIC
1410*/
4a8a4322 1411static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1412{
e6148917 1413 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1414 int temperature;
1415
bb8c093b 1416 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1417
1418 /* driver's okay range is -260 to +25.
1419 * human readable okay range is 0 to +285 */
1420 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1421
1422 /* handle insane temp reading */
bb8c093b 1423 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1424 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1425
1426 /* if really really hot(?),
1427 * substitute the 3rd band/group's temp measured at factory */
1428 if (priv->last_temperature > 100)
e6148917 1429 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1430 else /* else use most recent "sane" value from driver */
1431 temperature = priv->last_temperature;
1432 }
1433
1434 return temperature; /* raw, not "human readable" */
1435}
1436
1437/* Adjust Txpower only if temperature variance is greater than threshold.
1438 *
1439 * Both are lower than older versions' 9 degrees */
1440#define IWL_TEMPERATURE_LIMIT_TIMER 6
1441
1442/**
1443 * is_temp_calib_needed - determines if new calibration is needed
1444 *
1445 * records new temperature in tx_mgr->temperature.
1446 * replaces tx_mgr->last_temperature *only* if calib needed
1447 * (assumes caller will actually do the calibration!). */
4a8a4322 1448static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1449{
1450 int temp_diff;
1451
bb8c093b 1452 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1453 temp_diff = priv->temperature - priv->last_temperature;
1454
1455 /* get absolute value */
1456 if (temp_diff < 0) {
1457 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1458 temp_diff = -temp_diff;
1459 } else if (temp_diff == 0)
1460 IWL_DEBUG_POWER("Same temp,\n");
1461 else
1462 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1463
1464 /* if we don't need calibration, *don't* update last_temperature */
1465 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1466 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1467 return 0;
1468 }
1469
1470 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1471
1472 /* assume that caller will actually do calib ...
1473 * update the "last temperature" value */
1474 priv->last_temperature = priv->temperature;
1475 return 1;
1476}
1477
1478#define IWL_MAX_GAIN_ENTRIES 78
1479#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1480#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1481
1482/* radio and DSP power table, each step is 1/2 dB.
1483 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1484static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1485 {
1486 {251, 127}, /* 2.4 GHz, highest power */
1487 {251, 127},
1488 {251, 127},
1489 {251, 127},
1490 {251, 125},
1491 {251, 110},
1492 {251, 105},
1493 {251, 98},
1494 {187, 125},
1495 {187, 115},
1496 {187, 108},
1497 {187, 99},
1498 {243, 119},
1499 {243, 111},
1500 {243, 105},
1501 {243, 97},
1502 {243, 92},
1503 {211, 106},
1504 {211, 100},
1505 {179, 120},
1506 {179, 113},
1507 {179, 107},
1508 {147, 125},
1509 {147, 119},
1510 {147, 112},
1511 {147, 106},
1512 {147, 101},
1513 {147, 97},
1514 {147, 91},
1515 {115, 107},
1516 {235, 121},
1517 {235, 115},
1518 {235, 109},
1519 {203, 127},
1520 {203, 121},
1521 {203, 115},
1522 {203, 108},
1523 {203, 102},
1524 {203, 96},
1525 {203, 92},
1526 {171, 110},
1527 {171, 104},
1528 {171, 98},
1529 {139, 116},
1530 {227, 125},
1531 {227, 119},
1532 {227, 113},
1533 {227, 107},
1534 {227, 101},
1535 {227, 96},
1536 {195, 113},
1537 {195, 106},
1538 {195, 102},
1539 {195, 95},
1540 {163, 113},
1541 {163, 106},
1542 {163, 102},
1543 {163, 95},
1544 {131, 113},
1545 {131, 106},
1546 {131, 102},
1547 {131, 95},
1548 {99, 113},
1549 {99, 106},
1550 {99, 102},
1551 {99, 95},
1552 {67, 113},
1553 {67, 106},
1554 {67, 102},
1555 {67, 95},
1556 {35, 113},
1557 {35, 106},
1558 {35, 102},
1559 {35, 95},
1560 {3, 113},
1561 {3, 106},
1562 {3, 102},
1563 {3, 95} }, /* 2.4 GHz, lowest power */
1564 {
1565 {251, 127}, /* 5.x GHz, highest power */
1566 {251, 120},
1567 {251, 114},
1568 {219, 119},
1569 {219, 101},
1570 {187, 113},
1571 {187, 102},
1572 {155, 114},
1573 {155, 103},
1574 {123, 117},
1575 {123, 107},
1576 {123, 99},
1577 {123, 92},
1578 {91, 108},
1579 {59, 125},
1580 {59, 118},
1581 {59, 109},
1582 {59, 102},
1583 {59, 96},
1584 {59, 90},
1585 {27, 104},
1586 {27, 98},
1587 {27, 92},
1588 {115, 118},
1589 {115, 111},
1590 {115, 104},
1591 {83, 126},
1592 {83, 121},
1593 {83, 113},
1594 {83, 105},
1595 {83, 99},
1596 {51, 118},
1597 {51, 111},
1598 {51, 104},
1599 {51, 98},
1600 {19, 116},
1601 {19, 109},
1602 {19, 102},
1603 {19, 98},
1604 {19, 93},
1605 {171, 113},
1606 {171, 107},
1607 {171, 99},
1608 {139, 120},
1609 {139, 113},
1610 {139, 107},
1611 {139, 99},
1612 {107, 120},
1613 {107, 113},
1614 {107, 107},
1615 {107, 99},
1616 {75, 120},
1617 {75, 113},
1618 {75, 107},
1619 {75, 99},
1620 {43, 120},
1621 {43, 113},
1622 {43, 107},
1623 {43, 99},
1624 {11, 120},
1625 {11, 113},
1626 {11, 107},
1627 {11, 99},
1628 {131, 107},
1629 {131, 99},
1630 {99, 120},
1631 {99, 113},
1632 {99, 107},
1633 {99, 99},
1634 {67, 120},
1635 {67, 113},
1636 {67, 107},
1637 {67, 99},
1638 {35, 120},
1639 {35, 113},
1640 {35, 107},
1641 {35, 99},
1642 {3, 120} } /* 5.x GHz, lowest power */
1643};
1644
bb8c093b 1645static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1646{
1647 if (index < 0)
1648 return 0;
1649 if (index >= IWL_MAX_GAIN_ENTRIES)
1650 return IWL_MAX_GAIN_ENTRIES - 1;
1651 return (u8) index;
1652}
1653
1654/* Kick off thermal recalibration check every 60 seconds */
1655#define REG_RECALIB_PERIOD (60)
1656
1657/**
bb8c093b 1658 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1659 *
1660 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1661 * or 6 Mbit (OFDM) rates.
1662 */
4a8a4322 1663static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1664 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1665 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1666 int band_index)
1667{
bb8c093b 1668 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1669 s8 power;
1670 u8 power_index;
1671
1672 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1673
1674 /* use this channel group's 6Mbit clipping/saturation pwr,
1675 * but cap at regulatory scan power restriction (set during init
1676 * based on eeprom channel data) for this channel. */
14577f23 1677 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1678
1679 /* further limit to user's max power preference.
1680 * FIXME: Other spectrum management power limitations do not
1681 * seem to apply?? */
62ea9c5b 1682 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1683 scan_power_info->requested_power = power;
1684
1685 /* find difference between new scan *power* and current "normal"
1686 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1687 * current "normal" temperature-compensated Tx power *index* for
1688 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1689 * *index*. */
1690 power_index = ch_info->power_info[rate_index].power_table_index
1691 - (power - ch_info->power_info
14577f23 1692 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1693
1694 /* store reference index that we use when adjusting *all* scan
1695 * powers. So we can accommodate user (all channel) or spectrum
1696 * management (single channel) power changes "between" temperature
1697 * feedback compensation procedures.
1698 * don't force fit this reference index into gain table; it may be a
1699 * negative number. This will help avoid errors when we're at
1700 * the lower bounds (highest gains, for warmest temperatures)
1701 * of the table. */
1702
1703 /* don't exceed table bounds for "real" setting */
bb8c093b 1704 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1705
1706 scan_power_info->power_table_index = power_index;
1707 scan_power_info->tpc.tx_gain =
1708 power_gain_table[band_index][power_index].tx_gain;
1709 scan_power_info->tpc.dsp_atten =
1710 power_gain_table[band_index][power_index].dsp_atten;
1711}
1712
1713/**
75bcfae9 1714 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1715 *
1716 * Configures power settings for all rates for the current channel,
1717 * using values from channel info struct, and send to NIC
1718 */
75bcfae9 1719int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1720{
14577f23 1721 int rate_idx, i;
d20b3c65 1722 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1723 struct iwl3945_txpowertable_cmd txpower = {
f2c7e521 1724 .channel = priv->active39_rxon.channel,
b481de9c
ZY		 1725 };
1726
8318d78a 1727 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1728 ch_info = iwl_get_channel_info(priv,
8318d78a 1729 priv->band,
f2c7e521 1730 le16_to_cpu(priv->active39_rxon.channel));
b481de9c 1731 if (!ch_info) {
15b1687c
WT		 1732 IWL_ERR(priv,
1733 "Failed to get channel info for channel %d [%d]\n",
1734 le16_to_cpu(priv->active39_rxon.channel), priv->band);
b481de9c
ZY		 1735 return -EINVAL;
1736 }
1737
1738 if (!is_channel_valid(ch_info)) {
1739 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1740 "non-Tx channel.\n");
1741 return 0;
1742 }
1743
1744 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1745 /* Fill OFDM rate */
1746 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1747 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1748
1749 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1750 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1751
1752 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1753 le16_to_cpu(txpower.channel),
1754 txpower.band,
14577f23
MA		 1755 txpower.power[i].tpc.tx_gain,
1756 txpower.power[i].tpc.dsp_atten,
1757 txpower.power[i].rate);
1758 }
1759 /* Fill CCK rates */
1760 for (rate_idx = IWL_FIRST_CCK_RATE;
1761 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1762 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1763 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1764
1765 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1766 le16_to_cpu(txpower.channel),
1767 txpower.band,
1768 txpower.power[i].tpc.tx_gain,
1769 txpower.power[i].tpc.dsp_atten,
1770 txpower.power[i].rate);
b481de9c
ZY		 1771 }
1772
518099a8
SO		 1773 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1774 sizeof(struct iwl3945_txpowertable_cmd),
1775 &txpower);
b481de9c
ZY		 1776
1777}
1778
1779/**
bb8c093b 1780 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1781 * @ch_info: Channel to update. Uses power_info.requested_power.
1782 *
1783 * Replace requested_power and base_power_index ch_info fields for
1784 * one channel.
1785 *
1786 * Called if user or spectrum management changes power preferences.
1787 * Takes into account h/w and modulation limitations (clip power).
1788 *
1789 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1790 *
1791 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1792 * properly fill out the scan powers, and actual h/w gain settings,
1793 * and send changes to NIC
1794 */
4a8a4322 1795static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1796 struct iwl_channel_info *ch_info)
b481de9c 1797{
bb8c093b 1798 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1799 int power_changed = 0;
1800 int i;
1801 const s8 *clip_pwrs;
1802 int power;
1803
1804 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1805 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1806
1807 /* Get this channel's rate-to-current-power settings table */
1808 power_info = ch_info->power_info;
1809
1810 /* update OFDM Txpower settings */
14577f23 1811 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1812 i++, ++power_info) {
1813 int delta_idx;
1814
1815 /* limit new power to be no more than h/w capability */
1816 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1817 if (power == power_info->requested_power)
1818 continue;
1819
1820 /* find difference between old and new requested powers,
1821 * update base (non-temp-compensated) power index */
1822 delta_idx = (power - power_info->requested_power) * 2;
1823 power_info->base_power_index -= delta_idx;
1824
1825 /* save new requested power value */
1826 power_info->requested_power = power;
1827
1828 power_changed = 1;
1829 }
1830
1831 /* update CCK Txpower settings, based on OFDM 12M setting ...
1832 * ... all CCK power settings for a given channel are the *same*. */
1833 if (power_changed) {
1834 power =
14577f23 1835 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1836 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1837
bb8c093b 1838 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1839 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1840 power_info->requested_power = power;
1841 power_info->base_power_index =
14577f23 1842 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1843 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1844 ++power_info;
1845 }
1846 }
1847
1848 return 0;
1849}
1850
1851/**
bb8c093b 1852 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1853 *
1854 * NOTE: Returned power limit may be less (but not more) than requested,
1855 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1856 * (no consideration for h/w clipping limitations).
1857 */
d20b3c65 1858static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1859{
1860 s8 max_power;
1861
1862#if 0
1863 /* if we're using TGd limits, use lower of TGd or EEPROM */
1864 if (ch_info->tgd_data.max_power != 0)
1865 max_power = min(ch_info->tgd_data.max_power,
1866 ch_info->eeprom.max_power_avg);
1867
1868 /* else just use EEPROM limits */
1869 else
1870#endif
1871 max_power = ch_info->eeprom.max_power_avg;
1872
1873 return min(max_power, ch_info->max_power_avg);
1874}
1875
1876/**
bb8c093b 1877 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1878 *
1879 * Compensate txpower settings of *all* channels for temperature.
1880 * This only accounts for the difference between current temperature
1881 * and the factory calibration temperatures, and bases the new settings
1882 * on the channel's base_power_index.
1883 *
1884 * If RxOn is "associated", this sends the new Txpower to NIC!
1885 */
4a8a4322 1886static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1887{
d20b3c65 1888 struct iwl_channel_info *ch_info = NULL;
e6148917 1889 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1890 int delta_index;
1891 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1892 u8 a_band;
1893 u8 rate_index;
1894 u8 scan_tbl_index;
1895 u8 i;
1896 int ref_temp;
1897 int temperature = priv->temperature;
1898
1899 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1900 for (i = 0; i < priv->channel_count; i++) {
1901 ch_info = &priv->channel_info[i];
1902 a_band = is_channel_a_band(ch_info);
1903
1904 /* Get this chnlgrp's factory calibration temperature */
e6148917 1905 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1906 temperature;
1907
a96a27f9 1908 /* get power index adjustment based on current and factory
b481de9c 1909 * temps */
bb8c093b 1910 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1911 ref_temp);
1912
1913 /* set tx power value for all rates, OFDM and CCK */
1914 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1915 rate_index++) {
1916 int power_idx =
1917 ch_info->power_info[rate_index].base_power_index;
1918
1919 /* temperature compensate */
1920 power_idx += delta_index;
1921
1922 /* stay within table range */
bb8c093b 1923 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1924 ch_info->power_info[rate_index].
1925 power_table_index = (u8) power_idx;
1926 ch_info->power_info[rate_index].tpc =
1927 power_gain_table[a_band][power_idx];
1928 }
1929
1930 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1931 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1932
1933 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1934 for (scan_tbl_index = 0;
1935 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1936 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1937 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1938 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1939 actual_index, clip_pwrs,
1940 ch_info, a_band);
1941 }
1942 }
1943
1944 /* send Txpower command for current channel to ucode */
75bcfae9 1945 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1946}
1947
4a8a4322 1948int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1949{
d20b3c65 1950 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1951 s8 max_power;
1952 u8 a_band;
1953 u8 i;
1954
62ea9c5b 1955 if (priv->tx_power_user_lmt == power) {
b481de9c
ZY		 1956 IWL_DEBUG_POWER("Requested Tx power same as current "
1957 "limit: %ddBm.\n", power);
1958 return 0;
1959 }
1960
1961 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1962 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1963
1964 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1965
1966 for (i = 0; i < priv->channel_count; i++) {
1967 ch_info = &priv->channel_info[i];
1968 a_band = is_channel_a_band(ch_info);
1969
1970 /* find minimum power of all user and regulatory constraints
1971 * (does not consider h/w clipping limitations) */
bb8c093b 1972 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1973 max_power = min(power, max_power);
1974 if (max_power != ch_info->curr_txpow) {
1975 ch_info->curr_txpow = max_power;
1976
1977 /* this considers the h/w clipping limitations */
bb8c093b 1978 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1979 }
1980 }
1981
1982 /* update txpower settings for all channels,
1983 * send to NIC if associated. */
1984 is_temp_calib_needed(priv);
bb8c093b 1985 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1986
1987 return 0;
1988}
1989
1990/* will add 3945 channel switch cmd handling later */
4a8a4322 1991int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1992{
1993 return 0;
1994}
1995
1996/**
1997 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1998 *
1999 * -- reset periodic timer
2000 * -- see if temp has changed enough to warrant re-calibration ... if so:
2001 * -- correct coeffs for temp (can reset temp timer)
2002 * -- save this temp as "last",
2003 * -- send new set of gain settings to NIC
2004 * NOTE: This should continue working, even when we're not associated,
2005 * so we can keep our internal table of scan powers current. */
4a8a4322 2006void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 2007{
2008 /* This will kick in the "brute force"
bb8c093b 2009 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2010 if (!is_temp_calib_needed(priv))
2011 goto reschedule;
2012
2013 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2014 * This is based *only* on current temperature,
2015 * ignoring any previous power measurements */
bb8c093b 2016 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2017
2018 reschedule:
2019 queue_delayed_work(priv->workqueue,
2020 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2021}
2022
416e1438 2023static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2024{
4a8a4322 2025 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2026 thermal_periodic.work);
2027
2028 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2029 return;
2030
2031 mutex_lock(&priv->mutex);
2032 iwl3945_reg_txpower_periodic(priv);
2033 mutex_unlock(&priv->mutex);
2034}
2035
2036/**
bb8c093b 2037 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2038 * for the channel.
2039 *
2040 * This function is used when initializing channel-info structs.
2041 *
2042 * NOTE: These channel groups do *NOT* match the bands above!
2043 * These channel groups are based on factory-tested channels;
2044 * on A-band, EEPROM's "group frequency" entries represent the top
2045 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2046 */
4a8a4322 2047static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2048 const struct iwl_channel_info *ch_info)
b481de9c 2049{
e6148917
SO		 2050 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2051 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2052 u8 group;
2053 u16 group_index = 0; /* based on factory calib frequencies */
2054 u8 grp_channel;
2055
2056 /* Find the group index for the channel ... don't use index 1(?) */
2057 if (is_channel_a_band(ch_info)) {
2058 for (group = 1; group < 5; group++) {
2059 grp_channel = ch_grp[group].group_channel;
2060 if (ch_info->channel <= grp_channel) {
2061 group_index = group;
2062 break;
2063 }
2064 }
2065 /* group 4 has a few channels *above* its factory cal freq */
2066 if (group == 5)
2067 group_index = 4;
2068 } else
2069 group_index = 0; /* 2.4 GHz, group 0 */
2070
2071 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2072 group_index);
2073 return group_index;
2074}
2075
2076/**
bb8c093b 2077 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2078 *
2079 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2080 * into radio/DSP gain settings table for requested power.
2081 */
4a8a4322 2082static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2083 s8 requested_power,
2084 s32 setting_index, s32 *new_index)
2085{
bb8c093b 2086 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2087 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2088 s32 index0, index1;
2089 s32 power = 2 * requested_power;
2090 s32 i;
bb8c093b 2091 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2092 s32 gains0, gains1;
2093 s32 res;
2094 s32 denominator;
2095
e6148917 2096 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2097 samples = chnl_grp->samples;
2098 for (i = 0; i < 5; i++) {
2099 if (power == samples[i].power) {
2100 *new_index = samples[i].gain_index;
2101 return 0;
2102 }
2103 }
2104
2105 if (power > samples[1].power) {
2106 index0 = 0;
2107 index1 = 1;
2108 } else if (power > samples[2].power) {
2109 index0 = 1;
2110 index1 = 2;
2111 } else if (power > samples[3].power) {
2112 index0 = 2;
2113 index1 = 3;
2114 } else {
2115 index0 = 3;
2116 index1 = 4;
2117 }
2118
2119 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2120 if (denominator == 0)
2121 return -EINVAL;
2122 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2123 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2124 res = gains0 + (gains1 - gains0) *
2125 ((s32) power - (s32) samples[index0].power) / denominator +
2126 (1 << 18);
2127 *new_index = res >> 19;
2128 return 0;
2129}
2130
4a8a4322 2131static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2132{
2133 u32 i;
2134 s32 rate_index;
e6148917 2135 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2136 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2137
2138 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2139
2140 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2141 s8 *clip_pwrs; /* table of power levels for each rate */
2142 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2143 group = &eeprom->groups[i];
b481de9c
ZY		 2144
2145 /* sanity check on factory saturation power value */
2146 if (group->saturation_power < 40) {
39aadf8c 2147 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2148 "less than minimum expected 40\n",
2149 group->saturation_power);
2150 return;
2151 }
2152
2153 /*
2154 * Derive requested power levels for each rate, based on
2155 * hardware capabilities (saturation power for band).
2156 * Basic value is 3dB down from saturation, with further
2157 * power reductions for highest 3 data rates. These
2158 * backoffs provide headroom for high rate modulation
2159 * power peaks, without too much distortion (clipping).
2160 */
2161 /* we'll fill in this array with h/w max power levels */
f2c7e521 2162 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2163
2164 /* divide factory saturation power by 2 to find -3dB level */
2165 satur_pwr = (s8) (group->saturation_power >> 1);
2166
2167 /* fill in channel group's nominal powers for each rate */
2168 for (rate_index = 0;
2169 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2170 switch (rate_index) {
14577f23 2171 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2172 if (i == 0) /* B/G */
2173 *clip_pwrs = satur_pwr;
2174 else /* A */
2175 *clip_pwrs = satur_pwr - 5;
2176 break;
14577f23 2177 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2178 if (i == 0)
2179 *clip_pwrs = satur_pwr - 7;
2180 else
2181 *clip_pwrs = satur_pwr - 10;
2182 break;
14577f23 2183 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2184 if (i == 0)
2185 *clip_pwrs = satur_pwr - 9;
2186 else
2187 *clip_pwrs = satur_pwr - 12;
2188 break;
2189 default:
2190 *clip_pwrs = satur_pwr;
2191 break;
2192 }
2193 }
2194 }
2195}
2196
2197/**
2198 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2199 *
2200 * Second pass (during init) to set up priv->channel_info
2201 *
2202 * Set up Tx-power settings in our channel info database for each VALID
2203 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2204 * and current temperature.
2205 *
2206 * Since this is based on current temperature (at init time), these values may
2207 * not be valid for very long, but it gives us a starting/default point,
2208 * and allows us to active (i.e. using Tx) scan.
2209 *
2210 * This does *not* write values to NIC, just sets up our internal table.
2211 */
4a8a4322 2212int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2213{
d20b3c65 2214 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2215 struct iwl3945_channel_power_info *pwr_info;
e6148917 2216 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2217 int delta_index;
2218 u8 rate_index;
2219 u8 scan_tbl_index;
2220 const s8 *clip_pwrs; /* array of power levels for each rate */
2221 u8 gain, dsp_atten;
2222 s8 power;
2223 u8 pwr_index, base_pwr_index, a_band;
2224 u8 i;
2225 int temperature;
2226
2227 /* save temperature reference,
2228 * so we can determine next time to calibrate */
bb8c093b 2229 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2230 priv->last_temperature = temperature;
2231
bb8c093b 2232 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2233
2234 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2235 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2236 i++, ch_info++) {
2237 a_band = is_channel_a_band(ch_info);
2238 if (!is_channel_valid(ch_info))
2239 continue;
2240
2241 /* find this channel's channel group (*not* "band") index */
2242 ch_info->group_index =
bb8c093b 2243 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2244
2245 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2246 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2247
2248 /* calculate power index *adjustment* value according to
2249 * diff between current temperature and factory temperature */
bb8c093b 2250 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2251 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2252 temperature);
2253
2254 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2255 ch_info->channel, delta_index, temperature +
2256 IWL_TEMP_CONVERT);
2257
2258 /* set tx power value for all OFDM rates */
2259 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2260 rate_index++) {
25a4ccea 2261 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2262 int rc;
2263
2264 /* use channel group's clip-power table,
2265 * but don't exceed channel's max power */
2266 s8 pwr = min(ch_info->max_power_avg,
2267 clip_pwrs[rate_index]);
2268
2269 pwr_info = &ch_info->power_info[rate_index];
2270
2271 /* get base (i.e. at factory-measured temperature)
2272 * power table index for this rate's power */
bb8c093b 2273 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2274 ch_info->group_index,
2275 &power_idx);
2276 if (rc) {
15b1687c 2277 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2278 return rc;
2279 }
2280 pwr_info->base_power_index = (u8) power_idx;
2281
2282 /* temperature compensate */
2283 power_idx += delta_index;
2284
2285 /* stay within range of gain table */
bb8c093b 2286 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2287
bb8c093b 2288 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2289 pwr_info->requested_power = pwr;
2290 pwr_info->power_table_index = (u8) power_idx;
2291 pwr_info->tpc.tx_gain =
2292 power_gain_table[a_band][power_idx].tx_gain;
2293 pwr_info->tpc.dsp_atten =
2294 power_gain_table[a_band][power_idx].dsp_atten;
2295 }
2296
2297 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2298 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2299 power = pwr_info->requested_power +
2300 IWL_CCK_FROM_OFDM_POWER_DIFF;
2301 pwr_index = pwr_info->power_table_index +
2302 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2303 base_pwr_index = pwr_info->base_power_index +
2304 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2305
2306 /* stay within table range */
bb8c093b 2307 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2308 gain = power_gain_table[a_band][pwr_index].tx_gain;
2309 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2310
bb8c093b 2311 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2312 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2313 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2314 for (rate_index = 0;
2315 rate_index < IWL_CCK_RATES; rate_index++) {
2316 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2317 pwr_info->requested_power = power;
2318 pwr_info->power_table_index = pwr_index;
2319 pwr_info->base_power_index = base_pwr_index;
2320 pwr_info->tpc.tx_gain = gain;
2321 pwr_info->tpc.dsp_atten = dsp_atten;
2322 }
2323
2324 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2325 for (scan_tbl_index = 0;
2326 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2327 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2328 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2329 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2330 actual_index, clip_pwrs, ch_info, a_band);
2331 }
2332 }
2333
2334 return 0;
2335}
2336
4a8a4322 2337int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2338{
2339 int rc;
2340 unsigned long flags;
2341
2342 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2343 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2344 if (rc) {
2345 spin_unlock_irqrestore(&priv->lock, flags);
2346 return rc;
2347 }
2348
5d49f498
AK		 2349 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2350 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2351 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2352 if (rc < 0)
15b1687c 2353 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2354
5d49f498 2355 iwl_release_nic_access(priv);
b481de9c
ZY		 2356 spin_unlock_irqrestore(&priv->lock, flags);
2357
2358 return 0;
2359}
2360
188cf6c7 2361int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c
ZY		 2362{
2363 int rc;
2364 unsigned long flags;
2365 int txq_id = txq->q.id;
2366
3832ec9d 2367 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2368
2369 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2370
2371 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2372 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2373 if (rc) {
2374 spin_unlock_irqrestore(&priv->lock, flags);
2375 return rc;
2376 }
5d49f498
AK		 2377 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2378 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2379
5d49f498 2380 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2381 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2382 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2383 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2384 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2385 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
5d49f498 2386 iwl_release_nic_access(priv);
b481de9c
ZY		 2387
2388 /* fake read to flush all prev. writes */
5d49f498 2389 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2390 spin_unlock_irqrestore(&priv->lock, flags);
2391
2392 return 0;
2393}
2394
42427b4e
KA		 2395/*
2396 * HCMD utils
2397 */
2398static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2399{
2400 switch (cmd_id) {
2401 case REPLY_RXON:
2402 return (u16) sizeof(struct iwl3945_rxon_cmd);
2403 default:
2404 return len;
2405 }
2406}
2407
b481de9c
ZY		 2408/**
2409 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2410 */
4a8a4322 2411int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2412{
14577f23 2413 int rc, i, index, prev_index;
bb8c093b 2414 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2415 .reserved = {0, 0, 0},
2416 };
bb8c093b 2417 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2418
bb8c093b
CH		 2419 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2420 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2421
2422 table[index].rate_n_flags =
bb8c093b 2423 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2424 table[index].try_cnt = priv->retry_rate;
bb8c093b 2425 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2426 table[index].next_rate_index =
2427 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2428 }
2429
8318d78a
JB		 2430 switch (priv->band) {
2431 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2432 IWL_DEBUG_RATE("Select A mode rate scale\n");
2433 /* If one of the following CCK rates is used,
2434 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2435 for (i = IWL_RATE_1M_INDEX_TABLE;
2436 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2437 table[i].next_rate_index =
2438 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2439
2440 /* Don't fall back to CCK rates */
7262796a
AM		 2441 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2442 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2443
2444 /* Don't drop out of OFDM rates */
14577f23 2445 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2446 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2447 break;
2448
8318d78a
JB		 2449 case IEEE80211_BAND_2GHZ:
2450 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2451 /* If an OFDM rate is used, have it fall back to the
2452 * 1M CCK rates */
b481de9c 2453
7262796a
AM		 2454 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2455 iwl3945_is_associated(priv)) {
2456
2457 index = IWL_FIRST_CCK_RATE;
2458 for (i = IWL_RATE_6M_INDEX_TABLE;
2459 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2460 table[i].next_rate_index =
2461 iwl3945_rates[index].table_rs_index;
2462
2463 index = IWL_RATE_11M_INDEX_TABLE;
2464 /* CCK shouldn't fall back to OFDM... */
2465 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2466 }
b481de9c
ZY		 2467 break;
2468
2469 default:
8318d78a 2470 WARN_ON(1);
b481de9c
ZY		 2471 break;
2472 }
2473
2474 /* Update the rate scaling for control frame Tx */
2475 rate_cmd.table_id = 0;
518099a8 2476 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2477 &rate_cmd);
2478 if (rc)
2479 return rc;
2480
2481 /* Update the rate scaling for data frame Tx */
2482 rate_cmd.table_id = 1;
518099a8 2483 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2484 &rate_cmd);
2485}
2486
796083cb 2487/* Called when initializing driver */
4a8a4322 2488int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2489{
3832ec9d
AK		 2490 memset((void *)&priv->hw_params, 0,
2491 sizeof(struct iwl_hw_params));
b481de9c 2492
3832ec9d 2493 priv->shared_virt =
b481de9c 2494 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2495 sizeof(struct iwl3945_shared),
3832ec9d 2496 &priv->shared_phys);
b481de9c 2497
3832ec9d 2498 if (!priv->shared_virt) {
15b1687c 2499 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2500 mutex_unlock(&priv->mutex);
2501 return -ENOMEM;
2502 }
2503
a8e74e27 2504 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
1e33dc64 2505 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
3832ec9d
AK		 2506 priv->hw_params.max_pkt_size = 2342;
2507 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2508 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2509 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2510 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2511
141c43a3
WT		 2512 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2513
b481de9c
ZY		 2514 return 0;
2515}
2516
4a8a4322 2517unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2518 struct iwl3945_frame *frame, u8 rate)
b481de9c 2519{
bb8c093b 2520 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2521 unsigned int frame_size;
2522
bb8c093b 2523 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2524 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2525
3832ec9d 2526 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2527 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2528
bb8c093b 2529 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2530 tx_beacon_cmd->frame,
b481de9c
ZY		 2531 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2532
2533 BUG_ON(frame_size > MAX_MPDU_SIZE);
2534 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2535
2536 tx_beacon_cmd->tx.rate = rate;
2537 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2538 TX_CMD_FLG_TSF_MSK);
2539
14577f23
MA		 2540 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2541 tx_beacon_cmd->tx.supp_rates[0] =
2542 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2543
b481de9c 2544 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2545 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2546
3ac7f146 2547 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2548}
2549
4a8a4322 2550void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2551{
91c066f2 2552 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2553 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2554}
2555
4a8a4322 2556void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2557{
2558 INIT_DELAYED_WORK(&priv->thermal_periodic,
2559 iwl3945_bg_reg_txpower_periodic);
2560}
2561
4a8a4322 2562void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2563{
2564 cancel_delayed_work(&priv->thermal_periodic);
2565}
2566
0164b9b4
KA		 2567/* check contents of special bootstrap uCode SRAM */
2568static int iwl3945_verify_bsm(struct iwl_priv *priv)
2569 {
2570 __le32 *image = priv->ucode_boot.v_addr;
2571 u32 len = priv->ucode_boot.len;
2572 u32 reg;
2573 u32 val;
2574
2575 IWL_DEBUG_INFO("Begin verify bsm\n");
2576
2577 /* verify BSM SRAM contents */
2578 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2579 for (reg = BSM_SRAM_LOWER_BOUND;
2580 reg < BSM_SRAM_LOWER_BOUND + len;
2581 reg += sizeof(u32), image++) {
2582 val = iwl_read_prph(priv, reg);
2583 if (val != le32_to_cpu(*image)) {
2584 IWL_ERR(priv, "BSM uCode verification failed at "
2585 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2586 BSM_SRAM_LOWER_BOUND,
2587 reg - BSM_SRAM_LOWER_BOUND, len,
2588 val, le32_to_cpu(*image));
2589 return -EIO;
2590 }
2591 }
2592
2593 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2594
2595 return 0;
2596}
2597
e6148917
SO		 2598
2599/******************************************************************************
2600 *
2601 * EEPROM related functions
2602 *
2603 ******************************************************************************/
2604
2605/*
2606 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2607 * embedded controller) as EEPROM reader; each read is a series of pulses
2608 * to/from the EEPROM chip, not a single event, so even reads could conflict
2609 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2610 * simply claims ownership, which should be safe when this function is called
2611 * (i.e. before loading uCode!).
2612 */
2613static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2614{
2615 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2616 return 0;
2617}
2618
2619
2620static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2621{
2622 return;
2623}
2624
0164b9b4
KA		 2625 /**
2626 * iwl3945_load_bsm - Load bootstrap instructions
2627 *
2628 * BSM operation:
2629 *
2630 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2631 * in special SRAM that does not power down during RFKILL. When powering back
2632 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2633 * the bootstrap program into the on-board processor, and starts it.
2634 *
2635 * The bootstrap program loads (via DMA) instructions and data for a new
2636 * program from host DRAM locations indicated by the host driver in the
2637 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2638 * automatically.
2639 *
2640 * When initializing the NIC, the host driver points the BSM to the
2641 * "initialize" uCode image. This uCode sets up some internal data, then
2642 * notifies host via "initialize alive" that it is complete.
2643 *
2644 * The host then replaces the BSM_DRAM_* pointer values to point to the
2645 * normal runtime uCode instructions and a backup uCode data cache buffer
2646 * (filled initially with starting data values for the on-board processor),
2647 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2648 * which begins normal operation.
2649 *
2650 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2651 * the backup data cache in DRAM before SRAM is powered down.
2652 *
2653 * When powering back up, the BSM loads the bootstrap program. This reloads
2654 * the runtime uCode instructions and the backup data cache into SRAM,
2655 * and re-launches the runtime uCode from where it left off.
2656 */
2657static int iwl3945_load_bsm(struct iwl_priv *priv)
2658{
2659 __le32 *image = priv->ucode_boot.v_addr;
2660 u32 len = priv->ucode_boot.len;
2661 dma_addr_t pinst;
2662 dma_addr_t pdata;
2663 u32 inst_len;
2664 u32 data_len;
2665 int rc;
2666 int i;
2667 u32 done;
2668 u32 reg_offset;
2669
2670 IWL_DEBUG_INFO("Begin load bsm\n");
2671
2672 /* make sure bootstrap program is no larger than BSM's SRAM size */
2673 if (len > IWL39_MAX_BSM_SIZE)
2674 return -EINVAL;
2675
2676 /* Tell bootstrap uCode where to find the "Initialize" uCode
2677 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2678 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2679 * after the "initialize" uCode has run, to point to
2680 * runtime/protocol instructions and backup data cache. */
2681 pinst = priv->ucode_init.p_addr;
2682 pdata = priv->ucode_init_data.p_addr;
2683 inst_len = priv->ucode_init.len;
2684 data_len = priv->ucode_init_data.len;
2685
2686 rc = iwl_grab_nic_access(priv);
2687 if (rc)
2688 return rc;
2689
2690 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2691 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2692 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2693 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2694
2695 /* Fill BSM memory with bootstrap instructions */
2696 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2697 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2698 reg_offset += sizeof(u32), image++)
2699 _iwl_write_prph(priv, reg_offset,
2700 le32_to_cpu(*image));
2701
2702 rc = iwl3945_verify_bsm(priv);
2703 if (rc) {
2704 iwl_release_nic_access(priv);
2705 return rc;
2706 }
2707
2708 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2709 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2710 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2711 IWL39_RTC_INST_LOWER_BOUND);
2712 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2713
2714 /* Load bootstrap code into instruction SRAM now,
2715 * to prepare to load "initialize" uCode */
2716 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2717 BSM_WR_CTRL_REG_BIT_START);
2718
2719 /* Wait for load of bootstrap uCode to finish */
2720 for (i = 0; i < 100; i++) {
2721 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2722 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2723 break;
2724 udelay(10);
2725 }
2726 if (i < 100)
2727 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2728 else {
2729 IWL_ERR(priv, "BSM write did not complete!\n");
2730 return -EIO;
2731 }
2732
2733 /* Enable future boot loads whenever power management unit triggers it
2734 * (e.g. when powering back up after power-save shutdown) */
2735 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2736 BSM_WR_CTRL_REG_BIT_START_EN);
2737
2738 iwl_release_nic_access(priv);
2739
2740 return 0;
2741}
2742
2743static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2744 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2745 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2746 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2747 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2748 .apm_ops = {
2749 .init = iwl3945_apm_init,
2750 .reset = iwl3945_apm_reset,
2751 .stop = iwl3945_apm_stop,
2752 .config = iwl3945_nic_config,
854682ed 2753 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2754 },
e6148917
SO		 2755 .eeprom_ops = {
2756 .regulatory_bands = {
2757 EEPROM_REGULATORY_BAND_1_CHANNELS,
2758 EEPROM_REGULATORY_BAND_2_CHANNELS,
2759 EEPROM_REGULATORY_BAND_3_CHANNELS,
2760 EEPROM_REGULATORY_BAND_4_CHANNELS,
2761 EEPROM_REGULATORY_BAND_5_CHANNELS,
2762 IWL3945_EEPROM_IMG_SIZE,
2763 IWL3945_EEPROM_IMG_SIZE,
2764 },
2765 .verify_signature = iwlcore_eeprom_verify_signature,
2766 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2767 .release_semaphore = iwl3945_eeprom_release_semaphore,
2768 .query_addr = iwlcore_eeprom_query_addr,
2769 },
75bcfae9 2770 .send_tx_power = iwl3945_send_tx_power,
0164b9b4
KA		 2771};
2772
42427b4e
KA		 2773static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2774 .get_hcmd_size = iwl3945_get_hcmd_size,
2775};
2776
0164b9b4
KA		 2777static struct iwl_ops iwl3945_ops = {
2778 .lib = &iwl3945_lib,
42427b4e 2779 .utils = &iwl3945_hcmd_utils,
0164b9b4
KA		 2780};
2781
c0f20d91 2782static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2783 .name = "3945BG",
a0987a8d
RC		 2784 .fw_name_pre = IWL3945_FW_PRE,
2785 .ucode_api_max = IWL3945_UCODE_API_MAX,
2786 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2787 .sku = IWL_SKU_G,
e6148917
SO		 2788 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2789 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2790 .ops = &iwl3945_ops,
df878d8f 2791 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2792};
2793
c0f20d91 2794static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2795 .name = "3945ABG",
a0987a8d
RC		 2796 .fw_name_pre = IWL3945_FW_PRE,
2797 .ucode_api_max = IWL3945_UCODE_API_MAX,
2798 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2799 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2800 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2801 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2802 .ops = &iwl3945_ops,
df878d8f 2803 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2804};
2805
bb8c093b 2806struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2807 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2808 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2809 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2810 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2811 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2812 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2813 {0}
2814};
2815
bb8c093b 2816MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)