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iwlwifi: check return value of pci_enable_device
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
17f841cd 44#include "iwl-sta.h"
b481de9c 45#include "iwl-3945.h"
e6148917 46#include "iwl-eeprom.h"
5d08cd1d 47#include "iwl-helpers.h"
5747d47f 48#include "iwl-core.h"
d9829a67 49#include "iwl-agn-rs.h"
b481de9c
ZY		 50
51#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
52 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 59 IWL_RATE_##np##M_INDEX, \
60 IWL_RATE_##r##M_INDEX_TABLE, \
61 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 62
63/*
64 * Parameter order:
65 * rate, prev rate, next rate, prev tgg rate, next tgg rate
66 *
67 * If there isn't a valid next or previous rate then INV is used which
68 * maps to IWL_RATE_INVALID
69 *
70 */
d9829a67 71const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 72 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
73 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
74 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
75 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 76 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
77 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
78 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
79 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
80 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
81 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
82 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
83 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 84};
85
bb8c093b 86/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 87#define IWL_EVT_DISABLE (0)
88#define IWL_EVT_DISABLE_SIZE (1532/32)
89
90/**
bb8c093b 91 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 92 *
93 * Disable an event by writing "1"s into "disable"
94 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
95 * Default values of 0 enable uCode events to be logged.
96 * Use for only special debugging. This function is just a placeholder as-is,
97 * you'll need to provide the special bits! ...
98 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 99void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 100{
af7cca2a 101 int ret;
b481de9c
ZY		 102 int i;
103 u32 base; /* SRAM address of event log header */
104 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
105 u32 array_size; /* # of u32 entries in array */
106 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107 0x00000000, /* 31 - 0 Event id numbers */
108 0x00000000, /* 63 - 32 */
109 0x00000000, /* 95 - 64 */
110 0x00000000, /* 127 - 96 */
111 0x00000000, /* 159 - 128 */
112 0x00000000, /* 191 - 160 */
113 0x00000000, /* 223 - 192 */
114 0x00000000, /* 255 - 224 */
115 0x00000000, /* 287 - 256 */
116 0x00000000, /* 319 - 288 */
117 0x00000000, /* 351 - 320 */
118 0x00000000, /* 383 - 352 */
119 0x00000000, /* 415 - 384 */
120 0x00000000, /* 447 - 416 */
121 0x00000000, /* 479 - 448 */
122 0x00000000, /* 511 - 480 */
123 0x00000000, /* 543 - 512 */
124 0x00000000, /* 575 - 544 */
125 0x00000000, /* 607 - 576 */
126 0x00000000, /* 639 - 608 */
127 0x00000000, /* 671 - 640 */
128 0x00000000, /* 703 - 672 */
129 0x00000000, /* 735 - 704 */
130 0x00000000, /* 767 - 736 */
131 0x00000000, /* 799 - 768 */
132 0x00000000, /* 831 - 800 */
133 0x00000000, /* 863 - 832 */
134 0x00000000, /* 895 - 864 */
135 0x00000000, /* 927 - 896 */
136 0x00000000, /* 959 - 928 */
137 0x00000000, /* 991 - 960 */
138 0x00000000, /* 1023 - 992 */
139 0x00000000, /* 1055 - 1024 */
140 0x00000000, /* 1087 - 1056 */
141 0x00000000, /* 1119 - 1088 */
142 0x00000000, /* 1151 - 1120 */
143 0x00000000, /* 1183 - 1152 */
144 0x00000000, /* 1215 - 1184 */
145 0x00000000, /* 1247 - 1216 */
146 0x00000000, /* 1279 - 1248 */
147 0x00000000, /* 1311 - 1280 */
148 0x00000000, /* 1343 - 1312 */
149 0x00000000, /* 1375 - 1344 */
150 0x00000000, /* 1407 - 1376 */
151 0x00000000, /* 1439 - 1408 */
152 0x00000000, /* 1471 - 1440 */
153 0x00000000, /* 1503 - 1472 */
154 };
155
156 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 157 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 158 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 159 return;
160 }
161
5d49f498 162 ret = iwl_grab_nic_access(priv);
af7cca2a 163 if (ret) {
39aadf8c 164 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 165 return;
166 }
167
5d49f498
AK		 168 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
169 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
170 iwl_release_nic_access(priv);
b481de9c
ZY		 171
172 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
173 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
174 disable_ptr);
5d49f498 175 ret = iwl_grab_nic_access(priv);
b481de9c 176 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 177 iwl_write_targ_mem(priv,
af7cca2a
TW		 178 disable_ptr + (i * sizeof(u32)),
179 evt_disable[i]);
b481de9c 180
5d49f498 181 iwl_release_nic_access(priv);
b481de9c
ZY		 182 } else {
183 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
184 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
185 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
186 disable_ptr, array_size);
187 }
188
189}
190
17744ff6
TW		 191static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
192{
193 int idx;
194
195 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
196 if (iwl3945_rates[idx].plcp == plcp)
197 return idx;
198 return -1;
199}
200
d08853a3 201#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 202#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
203
204static const char *iwl3945_get_tx_fail_reason(u32 status)
205{
206 switch (status & TX_STATUS_MSK) {
207 case TX_STATUS_SUCCESS:
208 return "SUCCESS";
209 TX_STATUS_ENTRY(SHORT_LIMIT);
210 TX_STATUS_ENTRY(LONG_LIMIT);
211 TX_STATUS_ENTRY(FIFO_UNDERRUN);
212 TX_STATUS_ENTRY(MGMNT_ABORT);
213 TX_STATUS_ENTRY(NEXT_FRAG);
214 TX_STATUS_ENTRY(LIFE_EXPIRE);
215 TX_STATUS_ENTRY(DEST_PS);
216 TX_STATUS_ENTRY(ABORTED);
217 TX_STATUS_ENTRY(BT_RETRY);
218 TX_STATUS_ENTRY(STA_INVALID);
219 TX_STATUS_ENTRY(FRAG_DROPPED);
220 TX_STATUS_ENTRY(TID_DISABLE);
221 TX_STATUS_ENTRY(FRAME_FLUSHED);
222 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
223 TX_STATUS_ENTRY(TX_LOCKED);
224 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
225 }
226
227 return "UNKNOWN";
228}
229#else
230static inline const char *iwl3945_get_tx_fail_reason(u32 status)
231{
232 return "";
233}
234#endif
235
e6a9854b
JB		 236/*
237 * get ieee prev rate from rate scale table.
238 * for A and B mode we need to overright prev
239 * value
240 */
4a8a4322 241int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 242{
243 int next_rate = iwl3945_get_prev_ieee_rate(rate);
244
245 switch (priv->band) {
246 case IEEE80211_BAND_5GHZ:
247 if (rate == IWL_RATE_12M_INDEX)
248 next_rate = IWL_RATE_9M_INDEX;
249 else if (rate == IWL_RATE_6M_INDEX)
250 next_rate = IWL_RATE_6M_INDEX;
251 break;
7262796a
AM		 252 case IEEE80211_BAND_2GHZ:
253 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 254 iwl_is_associated(priv)) {
7262796a
AM		 255 if (rate == IWL_RATE_11M_INDEX)
256 next_rate = IWL_RATE_5M_INDEX;
257 }
e6a9854b 258 break;
7262796a 259
e6a9854b
JB		 260 default:
261 break;
262 }
263
264 return next_rate;
265}
266
91c066f2
TW		 267
268/**
269 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
270 *
271 * When FW advances 'R' index, all entries between old and new 'R' index
272 * need to be reclaimed. As result, some free space forms. If there is
273 * enough free space (> low mark), wake the stack that feeds us.
274 */
4a8a4322 275static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 276 int txq_id, int index)
277{
188cf6c7 278 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 279 struct iwl_queue *q = &txq->q;
dbb6654c 280 struct iwl_tx_info *tx_info;
91c066f2
TW		 281
282 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
283
284 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
285 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
286
287 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 288 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 289 tx_info->skb[0] = NULL;
7aaa1d79 290 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 291 }
292
d20b3c65 293 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 294 (txq_id != IWL_CMD_QUEUE_NUM) &&
295 priv->mac80211_registered)
296 ieee80211_wake_queue(priv->hw, txq_id);
297}
298
299/**
300 * iwl3945_rx_reply_tx - Handle Tx response
301 */
4a8a4322 302static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 303 struct iwl_rx_mem_buffer *rxb)
91c066f2 304{
3d24a9f7 305 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 306 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
307 int txq_id = SEQ_TO_QUEUE(sequence);
308 int index = SEQ_TO_INDEX(sequence);
188cf6c7 309 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 310 struct ieee80211_tx_info *info;
91c066f2
TW		 311 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
312 u32 status = le32_to_cpu(tx_resp->status);
313 int rate_idx;
74221d07 314 int fail;
91c066f2 315
625a381a 316 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 317 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 318 "is out of range [0-%d] %d %d\n", txq_id,
319 index, txq->q.n_bd, txq->q.write_ptr,
320 txq->q.read_ptr);
321 return;
322 }
323
e039fa4a 324 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 325 ieee80211_tx_info_clear_status(info);
326
327 /* Fill the MRR chain with some info about on-chip retransmissions */
328 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
329 if (info->band == IEEE80211_BAND_5GHZ)
330 rate_idx -= IWL_FIRST_OFDM_RATE;
331
332 fail = tx_resp->failure_frame;
74221d07
AM		 333
334 info->status.rates[0].idx = rate_idx;
335 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 336
91c066f2 337 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 338 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
339 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 340
341 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
342 txq_id, iwl3945_get_tx_fail_reason(status), status,
343 tx_resp->rate, tx_resp->failure_frame);
344
91c066f2
TW		 345 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
346 iwl3945_tx_queue_reclaim(priv, txq_id, index);
347
348 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 349 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 350}
351
352
353
b481de9c
ZY		 354/*****************************************************************************
355 *
356 * Intel PRO/Wireless 3945ABG/BG Network Connection
357 *
358 * RX handler implementations
359 *
b481de9c
ZY		 360 *****************************************************************************/
361
4a8a4322 362void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 363{
3d24a9f7 364 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 365 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 366 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 367 le32_to_cpu(pkt->len));
368
f2c7e521 369 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 370
ab53d8af
MA		 371 iwl3945_led_background(priv);
372
b481de9c
ZY		 373 priv->last_statistics_time = jiffies;
374}
375
17744ff6
TW		 376/******************************************************************************
377 *
378 * Misc. internal state and helper functions
379 *
380 ******************************************************************************/
d08853a3 381#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 382
383/**
384 * iwl3945_report_frame - dump frame to syslog during debug sessions
385 *
386 * You may hack this function to show different aspects of received frames,
387 * including selective frame dumps.
388 * group100 parameter selects whether to show 1 out of 100 good frames.
389 */
d08853a3 390static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 391 struct iwl_rx_packet *pkt,
17744ff6
TW		 392 struct ieee80211_hdr *header, int group100)
393{
394 u32 to_us;
395 u32 print_summary = 0;
396 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
397 u32 hundred = 0;
398 u32 dataframe = 0;
fd7c8a40 399 __le16 fc;
17744ff6
TW		 400 u16 seq_ctl;
401 u16 channel;
402 u16 phy_flags;
403 u16 length;
404 u16 status;
405 u16 bcn_tmr;
406 u32 tsf_low;
407 u64 tsf;
408 u8 rssi;
409 u8 agc;
410 u16 sig_avg;
411 u16 noise_diff;
412 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
413 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
414 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
415 u8 *data = IWL_RX_DATA(pkt);
416
417 /* MAC header */
fd7c8a40 418 fc = header->frame_control;
17744ff6
TW		 419 seq_ctl = le16_to_cpu(header->seq_ctrl);
420
421 /* metadata */
422 channel = le16_to_cpu(rx_hdr->channel);
423 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
424 length = le16_to_cpu(rx_hdr->len);
425
426 /* end-of-frame status and timestamp */
427 status = le32_to_cpu(rx_end->status);
428 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
429 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
430 tsf = le64_to_cpu(rx_end->timestamp);
431
432 /* signal statistics */
433 rssi = rx_stats->rssi;
434 agc = rx_stats->agc;
435 sig_avg = le16_to_cpu(rx_stats->sig_avg);
436 noise_diff = le16_to_cpu(rx_stats->noise_diff);
437
438 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
439
440 /* if data frame is to us and all is good,
441 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 442 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
443 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 444 dataframe = 1;
445 if (!group100)
446 print_summary = 1; /* print each frame */
447 else if (priv->framecnt_to_us < 100) {
448 priv->framecnt_to_us++;
449 print_summary = 0;
450 } else {
451 priv->framecnt_to_us = 0;
452 print_summary = 1;
453 hundred = 1;
454 }
455 } else {
456 /* print summary for all other frames */
457 print_summary = 1;
458 }
459
460 if (print_summary) {
461 char *title;
0ff1cca0 462 int rate;
17744ff6
TW		 463
464 if (hundred)
465 title = "100Frames";
fd7c8a40 466 else if (ieee80211_has_retry(fc))
17744ff6 467 title = "Retry";
fd7c8a40 468 else if (ieee80211_is_assoc_resp(fc))
17744ff6 469 title = "AscRsp";
fd7c8a40 470 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 471 title = "RasRsp";
fd7c8a40 472 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 473 title = "PrbRsp";
474 print_dump = 1; /* dump frame contents */
475 } else if (ieee80211_is_beacon(fc)) {
476 title = "Beacon";
477 print_dump = 1; /* dump frame contents */
478 } else if (ieee80211_is_atim(fc))
479 title = "ATIM";
480 else if (ieee80211_is_auth(fc))
481 title = "Auth";
482 else if (ieee80211_is_deauth(fc))
483 title = "DeAuth";
484 else if (ieee80211_is_disassoc(fc))
485 title = "DisAssoc";
486 else
487 title = "Frame";
488
489 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
490 if (rate == -1)
491 rate = 0;
492 else
493 rate = iwl3945_rates[rate].ieee / 2;
494
495 /* print frame summary.
496 * MAC addresses show just the last byte (for brevity),
497 * but you can hack it to show more, if you'd like to. */
498 if (dataframe)
499 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 500 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 501 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 502 length, rssi, channel, rate);
503 else {
504 /* src/dst addresses assume managed mode */
505 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
506 "src=0x%02x, rssi=%u, tim=%lu usec, "
507 "phy=0x%02x, chnl=%d\n",
fd7c8a40 508 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 509 header->addr3[5], rssi,
510 tsf_low - priv->scan_start_tsf,
511 phy_flags, channel);
512 }
513 }
514 if (print_dump)
40b8ec0b 515 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 516}
d08853a3
SO		 517
518static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
519 struct iwl_rx_packet *pkt,
520 struct ieee80211_hdr *header, int group100)
521{
522 if (priv->debug_level & IWL_DL_RX)
523 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
524}
525
17744ff6 526#else
4a8a4322 527static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 528 struct iwl_rx_packet *pkt,
17744ff6
TW		 529 struct ieee80211_hdr *header, int group100)
530{
531}
532#endif
533
4bd9b4f3 534/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 535static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 536 struct ieee80211_hdr *header)
537{
538 /* Filter incoming packets to determine if they are targeted toward
539 * this network, discarding packets coming from ourselves */
540 switch (priv->iw_mode) {
05c914fe 541 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 542 /* packets to our IBSS update information */
543 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 544 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 545 /* packets to our IBSS update information */
546 return !compare_ether_addr(header->addr2, priv->bssid);
547 default:
548 return 1;
549 }
550}
17744ff6 551
4a8a4322 552static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 553 struct iwl_rx_mem_buffer *rxb,
12342c47 554 struct ieee80211_rx_status *stats)
b481de9c 555{
3d24a9f7 556 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
699669f3 557#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 558 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 559#endif
bb8c093b
CH		 560 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
561 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 562 short len = le16_to_cpu(rx_hdr->len);
563
564 /* We received data from the HW, so stop the watchdog */
3d24a9f7 565 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
b481de9c
ZY		 566 IWL_DEBUG_DROP("Corruption detected!\n");
567 return;
568 }
569
570 /* We only process data packets if the interface is open */
571 if (unlikely(!priv->is_open)) {
572 IWL_DEBUG_DROP_LIMIT
573 ("Dropping packet while interface is not open.\n");
574 return;
575 }
b481de9c
ZY		 576
577 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
578 /* Set the size of the skb to the size of the frame */
579 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
580
9c74d9fb 581 if (!iwl3945_mod_params.sw_crypto)
8ccde88a
SO		 582 iwl_set_decrypted_flag(priv,
583 (struct ieee80211_hdr *)rxb->skb->data,
b481de9c
ZY		 584 le32_to_cpu(rx_end->status), stats);
585
ab53d8af 586#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 587 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 588 priv->rxtxpackets += len;
589#endif
b481de9c
ZY		 590 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
591 rxb->skb = NULL;
592}
593
7878a5a4
MA		 594#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
595
4a8a4322 596static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 597 struct iwl_rx_mem_buffer *rxb)
b481de9c 598{
17744ff6
TW		 599 struct ieee80211_hdr *header;
600 struct ieee80211_rx_status rx_status;
3d24a9f7 601 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 602 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
603 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
604 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 605 int snr;
b481de9c
ZY		 606 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
607 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 608 u8 network_packet;
17744ff6 609
17744ff6
TW		 610 rx_status.flag = 0;
611 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 612 rx_status.freq =
c0186078 613 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 614 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
615 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
616
617 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 618 if (rx_status.band == IEEE80211_BAND_5GHZ)
619 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 620
6f0a2c4d
BR		 621 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
622 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
623
624 /* set the preamble flag if appropriate */
625 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
626 rx_status.flag |= RX_FLAG_SHORTPRE;
627
b481de9c
ZY		 628 if ((unlikely(rx_stats->phy_count > 20))) {
629 IWL_DEBUG_DROP
630 ("dsp size out of range [0,20]: "
631 "%d/n", rx_stats->phy_count);
632 return;
633 }
634
635 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
636 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
637 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
638 return;
639 }
640
56decd3c 641
b481de9c
ZY		 642
643 /* Convert 3945's rssi indicator to dBm */
250bdd21 644 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 645
646 /* Set default noise value to -127 */
647 if (priv->last_rx_noise == 0)
648 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
649
650 /* 3945 provides noise info for OFDM frames only.
651 * sig_avg and noise_diff are measured by the 3945's digital signal
652 * processor (DSP), and indicate linear levels of signal level and
653 * distortion/noise within the packet preamble after
654 * automatic gain control (AGC). sig_avg should stay fairly
655 * constant if the radio's AGC is working well.
656 * Since these values are linear (not dB or dBm), linear
657 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
658 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
659 * to obtain noise level in dBm.
17744ff6 660 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 661 if (rx_stats_noise_diff) {
662 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 663 rx_status.noise = rx_status.signal -
17744ff6 664 iwl3945_calc_db_from_ratio(snr);
566bfe5a 665 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 666 rx_status.noise);
b481de9c
ZY		 667
668 /* If noise info not available, calculate signal quality indicator (%)
669 * using just the dBm signal level. */
670 } else {
17744ff6 671 rx_status.noise = priv->last_rx_noise;
566bfe5a 672 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 673 }
674
675
676 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 677 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 678 rx_stats_sig_avg, rx_stats_noise_diff);
679
b481de9c
ZY		 680 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
681
bb8c093b 682 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 683
17744ff6
TW		 684 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
685 network_packet ? '*' : ' ',
686 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 687 rx_status.signal, rx_status.signal,
688 rx_status.noise, rx_status.rate_idx);
b481de9c 689
d08853a3
SO		 690 /* Set "1" to report good data frames in groups of 100 */
691 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 692
693 if (network_packet) {
694 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
695 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 696 priv->last_rx_rssi = rx_status.signal;
17744ff6 697 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 698 }
699
12e5e22d 700 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 701}
702
7aaa1d79
SO		 703int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
704 struct iwl_tx_queue *txq,
705 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 706{
707 int count;
7aaa1d79 708 struct iwl_queue *q;
59606ffa 709 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 710
711 q = &txq->q;
59606ffa
SO		 712 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
713 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 714
715 if (reset)
716 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 717
718 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 719
720 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 721 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 722 NUM_TFD_CHUNKS);
723 return -EINVAL;
724 }
725
dbb6654c
WT		 726 tfd->tbs[count].addr = cpu_to_le32(addr);
727 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 728
729 count++;
730
731 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
732 TFD_CTL_PAD_SET(pad));
733
734 return 0;
735}
736
737/**
bb8c093b 738 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 739 *
740 * Does NOT advance any indexes
741 */
7aaa1d79 742void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 743{
59606ffa 744 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
dbb6654c 745 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
b481de9c
ZY		 746 struct pci_dev *dev = priv->pci_dev;
747 int i;
748 int counter;
749
750 /* classify bd */
751 if (txq->q.id == IWL_CMD_QUEUE_NUM)
752 /* nothing to cleanup after for host commands */
7aaa1d79 753 return;
b481de9c
ZY		 754
755 /* sanity check */
dbb6654c 756 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 757 if (counter > NUM_TFD_CHUNKS) {
15b1687c 758 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 759 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 760 return;
b481de9c
ZY		 761 }
762
763 /* unmap chunks if any */
764
765 for (i = 1; i < counter; i++) {
dbb6654c
WT		 766 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
767 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 768 if (txq->txb[txq->q.read_ptr].skb[0]) {
769 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
770 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 771 /* Can be called from interrupt context */
772 dev_kfree_skb_any(skb);
fc4b6853 773 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 774 }
775 }
776 }
7aaa1d79 777 return ;
b481de9c
ZY		 778}
779
4a8a4322 780u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 781{
c93007ef 782 int i, start = IWL_AP_ID;
b481de9c
ZY		 783 int ret = IWL_INVALID_STATION;
784 unsigned long flags;
785
c93007ef
SO		 786 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
787 (priv->iw_mode == NL80211_IFTYPE_AP))
788 start = IWL_STA_ID;
789
790 if (is_broadcast_ether_addr(addr))
3832ec9d 791 return priv->hw_params.bcast_sta_id;
c93007ef 792
b481de9c 793 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 794 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 795 if ((priv->stations_39[i].used) &&
b481de9c 796 (!compare_ether_addr
f2c7e521 797 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 798 ret = i;
799 goto out;
800 }
801
e174961c
JB		 802 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
803 addr, priv->num_stations);
b481de9c
ZY		 804 out:
805 spin_unlock_irqrestore(&priv->sta_lock, flags);
806 return ret;
807}
808
809/**
bb8c093b 810 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 811 *
812*/
c2d79b48 813void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 814 struct ieee80211_tx_info *info,
b481de9c
ZY		 815 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
816{
e039fa4a 817 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 818 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 819 u16 rate_mask;
820 int rate;
821 u8 rts_retry_limit;
822 u8 data_retry_limit;
823 __le32 tx_flags;
fd7c8a40 824 __le16 fc = hdr->frame_control;
c2d79b48 825 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 826
bb8c093b 827 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 828 tx_flags = tx->tx_flags;
b481de9c
ZY		 829
830 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 831 * in this running context */
b481de9c
ZY		 832 rate_mask = IWL_RATES_MASK;
833
b481de9c
ZY		 834 if (tx_id >= IWL_CMD_QUEUE_NUM)
835 rts_retry_limit = 3;
836 else
837 rts_retry_limit = 7;
838
fd7c8a40 839 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 840 data_retry_limit = 3;
841 if (data_retry_limit < rts_retry_limit)
842 rts_retry_limit = data_retry_limit;
843 } else
844 data_retry_limit = IWL_DEFAULT_TX_RETRY;
845
846 if (priv->data_retry_limit != -1)
847 data_retry_limit = priv->data_retry_limit;
848
fd7c8a40
HH		 849 if (ieee80211_is_mgmt(fc)) {
850 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
851 case cpu_to_le16(IEEE80211_STYPE_AUTH):
852 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
853 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
854 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 855 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
856 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
857 tx_flags |= TX_CMD_FLG_CTS_MSK;
858 }
859 break;
860 default:
861 break;
862 }
863 }
864
c2d79b48
WT		 865 tx->rts_retry_limit = rts_retry_limit;
866 tx->data_retry_limit = data_retry_limit;
867 tx->rate = rate;
868 tx->tx_flags = tx_flags;
b481de9c
ZY		 869
870 /* OFDM */
c2d79b48 871 tx->supp_rates[0] =
14577f23 872 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 873
874 /* CCK */
c2d79b48 875 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 876
877 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
878 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 879 tx->rate, le32_to_cpu(tx->tx_flags),
880 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 881}
882
4a8a4322 883u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 884{
885 unsigned long flags_spin;
bb8c093b 886 struct iwl3945_station_entry *station;
b481de9c
ZY		 887
888 if (sta_id == IWL_INVALID_STATION)
889 return IWL_INVALID_STATION;
890
891 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 892 station = &priv->stations_39[sta_id];
b481de9c
ZY		 893
894 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
895 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 896 station->sta.mode = STA_CONTROL_MODIFY_MSK;
897
898 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
899
17f841cd
SO		 900 iwl_send_add_sta(priv,
901 (struct iwl_addsta_cmd *)&station->sta, flags);
b481de9c
ZY		 902 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
903 sta_id, tx_rate);
904 return sta_id;
905}
906
854682ed 907static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c
ZY		 908{
909 int rc;
910 unsigned long flags;
911
912 spin_lock_irqsave(&priv->lock, flags);
5d49f498 913 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 914 if (rc) {
915 spin_unlock_irqrestore(&priv->lock, flags);
916 return rc;
917 }
918
854682ed 919 if (src == IWL_PWR_SRC_VAUX) {
b481de9c
ZY		 920 u32 val;
921
922 rc = pci_read_config_dword(priv->pci_dev,
923 PCI_POWER_SOURCE, &val);
924 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
5d49f498 925 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 926 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
927 ~APMG_PS_CTRL_MSK_PWR_SRC);
5d49f498 928 iwl_release_nic_access(priv);
b481de9c 929
5d49f498 930 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 931 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
932 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
933 } else
5d49f498 934 iwl_release_nic_access(priv);
b481de9c 935 } else {
5d49f498 936 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 937 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
938 ~APMG_PS_CTRL_MSK_PWR_SRC);
939
5d49f498
AK		 940 iwl_release_nic_access(priv);
941 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 942 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
943 }
944 spin_unlock_irqrestore(&priv->lock, flags);
945
946 return rc;
947}
948
4a8a4322 949static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY		 950{
951 int rc;
952 unsigned long flags;
953
954 spin_lock_irqsave(&priv->lock, flags);
5d49f498 955 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 956 if (rc) {
957 spin_unlock_irqrestore(&priv->lock, flags);
958 return rc;
959 }
960
5d49f498 961 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 962 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 963 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
964 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 965 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
966 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
967 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
968 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
969 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
970 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
971 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
972 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 973
974 /* fake read to flush all prev I/O */
5d49f498 975 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 976
5d49f498 977 iwl_release_nic_access(priv);
b481de9c
ZY		 978 spin_unlock_irqrestore(&priv->lock, flags);
979
980 return 0;
981}
982
4a8a4322 983static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c
ZY		 984{
985 int rc;
986 unsigned long flags;
987
988 spin_lock_irqsave(&priv->lock, flags);
5d49f498 989 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 990 if (rc) {
991 spin_unlock_irqrestore(&priv->lock, flags);
992 return rc;
993 }
994
995 /* bypass mode */
5d49f498 996 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 997
998 /* RA 0 is active */
5d49f498 999 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1000
1001 /* all 6 fifo are active */
5d49f498 1002 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1003
5d49f498
AK		 1004 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1005 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1006 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1007 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1008
5d49f498 1009 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 1010 priv->shared_phys);
b481de9c 1011
5d49f498 1012 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1013 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1014 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1015 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1016 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1017 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1018 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1019 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1020
5d49f498 1021 iwl_release_nic_access(priv);
b481de9c
ZY		 1022 spin_unlock_irqrestore(&priv->lock, flags);
1023
1024 return 0;
1025}
1026
1027/**
1028 * iwl3945_txq_ctx_reset - Reset TX queue context
1029 *
1030 * Destroys all DMA structures and initialize them again
1031 */
4a8a4322 1032static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1033{
1034 int rc;
1035 int txq_id, slots_num;
1036
bb8c093b 1037 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1038
1039 /* Tx CMD queue */
1040 rc = iwl3945_tx_reset(priv);
1041 if (rc)
1042 goto error;
1043
1044 /* Tx queue(s) */
1045 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1046 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1047 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 1048 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1049 txq_id);
b481de9c 1050 if (rc) {
15b1687c 1051 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1052 goto error;
1053 }
1054 }
1055
1056 return rc;
1057
1058 error:
bb8c093b 1059 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1060 return rc;
1061}
1062
01ec616d 1063static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1064{
01ec616d 1065 int ret = 0;
b481de9c 1066
bb8c093b 1067 iwl3945_power_init_handle(priv);
b481de9c 1068
5d49f498 1069 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1070 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1071
1072 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1073 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1074 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1075
01ec616d
KA		 1076 /* set "initialization complete" bit to move adapter
1077 * D0U* --> D0A* state */
5d49f498 1078 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d
KA		 1079
1080 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1081 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1082 if (ret < 0) {
b481de9c 1083 IWL_DEBUG_INFO("Failed to init the card\n");
01ec616d 1084 goto out;
b481de9c
ZY		 1085 }
1086
01ec616d
KA		 1087 ret = iwl_grab_nic_access(priv);
1088 if (ret)
1089 goto out;
1090
1091 /* enable DMA */
1092 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1093 APMG_CLK_VAL_BSM_CLK_RQT);
1094
b481de9c 1095 udelay(20);
01ec616d
KA		 1096
1097 /* disable L1-Active */
5d49f498 1098 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1099 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1100
5d49f498 1101 iwl_release_nic_access(priv);
01ec616d
KA		 1102out:
1103 return ret;
1104}
b481de9c 1105
01ec616d
KA		 1106static void iwl3945_nic_config(struct iwl_priv *priv)
1107{
e6148917 1108 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1109 unsigned long flags;
1110 u8 rev_id = 0;
b481de9c 1111
b481de9c
ZY		 1112 spin_lock_irqsave(&priv->lock, flags);
1113
1114 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1115 IWL_DEBUG_INFO("RTP type \n");
1116 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1117 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
5d49f498 1118 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1119 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1120 } else {
6f83eaa1 1121 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
5d49f498 1122 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1123 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1124 }
1125
e6148917 1126 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
b481de9c 1127 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
5d49f498 1128 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1129 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1130 } else
1131 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1132
e6148917 1133 if ((eeprom->board_revision & 0xF0) == 0xD0) {
b481de9c 1134 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
e6148917 1135 eeprom->board_revision);
5d49f498 1136 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1137 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1138 } else {
1139 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
e6148917 1140 eeprom->board_revision);
5d49f498 1141 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1142 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1143 }
1144
e6148917 1145 if (eeprom->almgor_m_version <= 1) {
5d49f498 1146 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1147 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c 1148 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
e6148917 1149 eeprom->almgor_m_version);
b481de9c
ZY		 1150 } else {
1151 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
e6148917 1152 eeprom->almgor_m_version);
5d49f498 1153 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1154 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1155 }
1156 spin_unlock_irqrestore(&priv->lock, flags);
1157
e6148917 1158 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 1159 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1160
e6148917 1161 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c 1162 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1163}
1164
1165int iwl3945_hw_nic_init(struct iwl_priv *priv)
1166{
1167 u8 rev_id;
1168 int rc;
1169 unsigned long flags;
1170 struct iwl_rx_queue *rxq = &priv->rxq;
1171
1172 spin_lock_irqsave(&priv->lock, flags);
1173 priv->cfg->ops->lib->apm_ops.init(priv);
1174 spin_unlock_irqrestore(&priv->lock, flags);
1175
1176 /* Determine HW type */
1177 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1178 if (rc)
1179 return rc;
1180 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1181
854682ed
KA		 1182 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1183 if(rc)
1184 return rc;
1185
01ec616d 1186 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1187
1188 /* Allocate the RX queue, or reset if it is already allocated */
1189 if (!rxq->bd) {
51af3d3f 1190 rc = iwl_rx_queue_alloc(priv);
b481de9c 1191 if (rc) {
15b1687c 1192 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1193 return -ENOMEM;
1194 }
1195 } else
51af3d3f 1196 iwl_rx_queue_reset(priv, rxq);
b481de9c 1197
bb8c093b 1198 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1199
1200 iwl3945_rx_init(priv, rxq);
1201
1202 spin_lock_irqsave(&priv->lock, flags);
1203
1204 /* Look at using this instead:
1205 rxq->need_update = 1;
141c43a3 1206 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1207 */
1208
5d49f498 1209 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1210 if (rc) {
1211 spin_unlock_irqrestore(&priv->lock, flags);
1212 return rc;
1213 }
5d49f498
AK		 1214 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1215 iwl_release_nic_access(priv);
b481de9c
ZY		 1216
1217 spin_unlock_irqrestore(&priv->lock, flags);
1218
1219 rc = iwl3945_txq_ctx_reset(priv);
1220 if (rc)
1221 return rc;
1222
1223 set_bit(STATUS_INIT, &priv->status);
1224
1225 return 0;
1226}
1227
1228/**
bb8c093b 1229 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1230 *
1231 * Destroy all TX DMA queues and structures
1232 */
4a8a4322 1233void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1234{
1235 int txq_id;
1236
1237 /* Tx queues */
1238 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
a8e74e27 1239 iwl_tx_queue_free(priv, txq_id);
b481de9c
ZY		 1240}
1241
4a8a4322 1242void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1243{
bddadf86 1244 int txq_id;
b481de9c
ZY		 1245 unsigned long flags;
1246
1247 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1248 if (iwl_grab_nic_access(priv)) {
b481de9c 1249 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1250 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1251 return;
1252 }
1253
1254 /* stop SCD */
5d49f498 1255 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1256
1257 /* reset TFD queues */
bddadf86 1258 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
5d49f498
AK		 1259 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1260 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1261 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1262 1000);
1263 }
1264
5d49f498 1265 iwl_release_nic_access(priv);
b481de9c
ZY		 1266 spin_unlock_irqrestore(&priv->lock, flags);
1267
bb8c093b 1268 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1269}
1270
01ec616d 1271static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1272{
01ec616d 1273 int ret = 0;
b481de9c
ZY		 1274 unsigned long flags;
1275
1276 spin_lock_irqsave(&priv->lock, flags);
1277
1278 /* set stop master bit */
5d49f498 1279 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1280
01ec616d
KA		 1281 iwl_poll_direct_bit(priv, CSR_RESET,
1282 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1283
01ec616d
KA		 1284 if (ret < 0)
1285 goto out;
b481de9c 1286
01ec616d 1287out:
b481de9c
ZY		 1288 spin_unlock_irqrestore(&priv->lock, flags);
1289 IWL_DEBUG_INFO("stop master\n");
1290
01ec616d
KA		 1291 return ret;
1292}
1293
1294static void iwl3945_apm_stop(struct iwl_priv *priv)
1295{
1296 unsigned long flags;
1297
1298 iwl3945_apm_stop_master(priv);
1299
1300 spin_lock_irqsave(&priv->lock, flags);
1301
1302 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1303
1304 udelay(10);
1305 /* clear "init complete" move adapter D0A* --> D0U state */
1306 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1307 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1308}
1309
e52119c5 1310static int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c
ZY		 1311{
1312 int rc;
1313 unsigned long flags;
1314
01ec616d 1315 iwl3945_apm_stop_master(priv);
b481de9c
ZY		 1316
1317 spin_lock_irqsave(&priv->lock, flags);
1318
5d49f498 1319 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
e9414b6b
AM		 1320 udelay(10);
1321
1322 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 1323
5d49f498 1324 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1325 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1326
5d49f498 1327 rc = iwl_grab_nic_access(priv);
b481de9c 1328 if (!rc) {
5d49f498 1329 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1330 APMG_CLK_VAL_BSM_CLK_RQT);
1331
5d49f498
AK		 1332 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1333 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1334 0xFFFFFFFF);
1335
1336 /* enable DMA */
5d49f498 1337 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1338 APMG_CLK_VAL_DMA_CLK_RQT |
1339 APMG_CLK_VAL_BSM_CLK_RQT);
1340 udelay(10);
1341
5d49f498 1342 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1343 APMG_PS_CTRL_VAL_RESET_REQ);
1344 udelay(5);
5d49f498 1345 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1346 APMG_PS_CTRL_VAL_RESET_REQ);
5d49f498 1347 iwl_release_nic_access(priv);
b481de9c
ZY		 1348 }
1349
1350 /* Clear the 'host command active' bit... */
1351 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1352
1353 wake_up_interruptible(&priv->wait_command_queue);
1354 spin_unlock_irqrestore(&priv->lock, flags);
1355
1356 return rc;
1357}
1358
1359/**
bb8c093b 1360 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1361 * return index delta into power gain settings table
1362*/
bb8c093b 1363static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1364{
1365 return (new_reading - old_reading) * (-11) / 100;
1366}
1367
1368/**
bb8c093b 1369 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1370 */
bb8c093b 1371static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1372{
3ac7f146 1373 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1374}
1375
4a8a4322 1376int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1377{
5d49f498 1378 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1379}
1380
1381/**
bb8c093b 1382 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1383 * get the current temperature by reading from NIC
1384*/
4a8a4322 1385static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1386{
e6148917 1387 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1388 int temperature;
1389
bb8c093b 1390 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1391
1392 /* driver's okay range is -260 to +25.
1393 * human readable okay range is 0 to +285 */
1394 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1395
1396 /* handle insane temp reading */
bb8c093b 1397 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1398 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1399
1400 /* if really really hot(?),
1401 * substitute the 3rd band/group's temp measured at factory */
1402 if (priv->last_temperature > 100)
e6148917 1403 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1404 else /* else use most recent "sane" value from driver */
1405 temperature = priv->last_temperature;
1406 }
1407
1408 return temperature; /* raw, not "human readable" */
1409}
1410
1411/* Adjust Txpower only if temperature variance is greater than threshold.
1412 *
1413 * Both are lower than older versions' 9 degrees */
1414#define IWL_TEMPERATURE_LIMIT_TIMER 6
1415
1416/**
1417 * is_temp_calib_needed - determines if new calibration is needed
1418 *
1419 * records new temperature in tx_mgr->temperature.
1420 * replaces tx_mgr->last_temperature *only* if calib needed
1421 * (assumes caller will actually do the calibration!). */
4a8a4322 1422static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1423{
1424 int temp_diff;
1425
bb8c093b 1426 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1427 temp_diff = priv->temperature - priv->last_temperature;
1428
1429 /* get absolute value */
1430 if (temp_diff < 0) {
1431 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1432 temp_diff = -temp_diff;
1433 } else if (temp_diff == 0)
1434 IWL_DEBUG_POWER("Same temp,\n");
1435 else
1436 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1437
1438 /* if we don't need calibration, *don't* update last_temperature */
1439 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1440 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1441 return 0;
1442 }
1443
1444 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1445
1446 /* assume that caller will actually do calib ...
1447 * update the "last temperature" value */
1448 priv->last_temperature = priv->temperature;
1449 return 1;
1450}
1451
1452#define IWL_MAX_GAIN_ENTRIES 78
1453#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1454#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1455
1456/* radio and DSP power table, each step is 1/2 dB.
1457 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1458static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1459 {
1460 {251, 127}, /* 2.4 GHz, highest power */
1461 {251, 127},
1462 {251, 127},
1463 {251, 127},
1464 {251, 125},
1465 {251, 110},
1466 {251, 105},
1467 {251, 98},
1468 {187, 125},
1469 {187, 115},
1470 {187, 108},
1471 {187, 99},
1472 {243, 119},
1473 {243, 111},
1474 {243, 105},
1475 {243, 97},
1476 {243, 92},
1477 {211, 106},
1478 {211, 100},
1479 {179, 120},
1480 {179, 113},
1481 {179, 107},
1482 {147, 125},
1483 {147, 119},
1484 {147, 112},
1485 {147, 106},
1486 {147, 101},
1487 {147, 97},
1488 {147, 91},
1489 {115, 107},
1490 {235, 121},
1491 {235, 115},
1492 {235, 109},
1493 {203, 127},
1494 {203, 121},
1495 {203, 115},
1496 {203, 108},
1497 {203, 102},
1498 {203, 96},
1499 {203, 92},
1500 {171, 110},
1501 {171, 104},
1502 {171, 98},
1503 {139, 116},
1504 {227, 125},
1505 {227, 119},
1506 {227, 113},
1507 {227, 107},
1508 {227, 101},
1509 {227, 96},
1510 {195, 113},
1511 {195, 106},
1512 {195, 102},
1513 {195, 95},
1514 {163, 113},
1515 {163, 106},
1516 {163, 102},
1517 {163, 95},
1518 {131, 113},
1519 {131, 106},
1520 {131, 102},
1521 {131, 95},
1522 {99, 113},
1523 {99, 106},
1524 {99, 102},
1525 {99, 95},
1526 {67, 113},
1527 {67, 106},
1528 {67, 102},
1529 {67, 95},
1530 {35, 113},
1531 {35, 106},
1532 {35, 102},
1533 {35, 95},
1534 {3, 113},
1535 {3, 106},
1536 {3, 102},
1537 {3, 95} }, /* 2.4 GHz, lowest power */
1538 {
1539 {251, 127}, /* 5.x GHz, highest power */
1540 {251, 120},
1541 {251, 114},
1542 {219, 119},
1543 {219, 101},
1544 {187, 113},
1545 {187, 102},
1546 {155, 114},
1547 {155, 103},
1548 {123, 117},
1549 {123, 107},
1550 {123, 99},
1551 {123, 92},
1552 {91, 108},
1553 {59, 125},
1554 {59, 118},
1555 {59, 109},
1556 {59, 102},
1557 {59, 96},
1558 {59, 90},
1559 {27, 104},
1560 {27, 98},
1561 {27, 92},
1562 {115, 118},
1563 {115, 111},
1564 {115, 104},
1565 {83, 126},
1566 {83, 121},
1567 {83, 113},
1568 {83, 105},
1569 {83, 99},
1570 {51, 118},
1571 {51, 111},
1572 {51, 104},
1573 {51, 98},
1574 {19, 116},
1575 {19, 109},
1576 {19, 102},
1577 {19, 98},
1578 {19, 93},
1579 {171, 113},
1580 {171, 107},
1581 {171, 99},
1582 {139, 120},
1583 {139, 113},
1584 {139, 107},
1585 {139, 99},
1586 {107, 120},
1587 {107, 113},
1588 {107, 107},
1589 {107, 99},
1590 {75, 120},
1591 {75, 113},
1592 {75, 107},
1593 {75, 99},
1594 {43, 120},
1595 {43, 113},
1596 {43, 107},
1597 {43, 99},
1598 {11, 120},
1599 {11, 113},
1600 {11, 107},
1601 {11, 99},
1602 {131, 107},
1603 {131, 99},
1604 {99, 120},
1605 {99, 113},
1606 {99, 107},
1607 {99, 99},
1608 {67, 120},
1609 {67, 113},
1610 {67, 107},
1611 {67, 99},
1612 {35, 120},
1613 {35, 113},
1614 {35, 107},
1615 {35, 99},
1616 {3, 120} } /* 5.x GHz, lowest power */
1617};
1618
bb8c093b 1619static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1620{
1621 if (index < 0)
1622 return 0;
1623 if (index >= IWL_MAX_GAIN_ENTRIES)
1624 return IWL_MAX_GAIN_ENTRIES - 1;
1625 return (u8) index;
1626}
1627
1628/* Kick off thermal recalibration check every 60 seconds */
1629#define REG_RECALIB_PERIOD (60)
1630
1631/**
bb8c093b 1632 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1633 *
1634 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1635 * or 6 Mbit (OFDM) rates.
1636 */
4a8a4322 1637static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1638 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1639 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1640 int band_index)
1641{
bb8c093b 1642 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1643 s8 power;
1644 u8 power_index;
1645
1646 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1647
1648 /* use this channel group's 6Mbit clipping/saturation pwr,
1649 * but cap at regulatory scan power restriction (set during init
1650 * based on eeprom channel data) for this channel. */
14577f23 1651 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1652
1653 /* further limit to user's max power preference.
1654 * FIXME: Other spectrum management power limitations do not
1655 * seem to apply?? */
62ea9c5b 1656 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1657 scan_power_info->requested_power = power;
1658
1659 /* find difference between new scan *power* and current "normal"
1660 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1661 * current "normal" temperature-compensated Tx power *index* for
1662 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1663 * *index*. */
1664 power_index = ch_info->power_info[rate_index].power_table_index
1665 - (power - ch_info->power_info
14577f23 1666 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1667
1668 /* store reference index that we use when adjusting *all* scan
1669 * powers. So we can accommodate user (all channel) or spectrum
1670 * management (single channel) power changes "between" temperature
1671 * feedback compensation procedures.
1672 * don't force fit this reference index into gain table; it may be a
1673 * negative number. This will help avoid errors when we're at
1674 * the lower bounds (highest gains, for warmest temperatures)
1675 * of the table. */
1676
1677 /* don't exceed table bounds for "real" setting */
bb8c093b 1678 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1679
1680 scan_power_info->power_table_index = power_index;
1681 scan_power_info->tpc.tx_gain =
1682 power_gain_table[band_index][power_index].tx_gain;
1683 scan_power_info->tpc.dsp_atten =
1684 power_gain_table[band_index][power_index].dsp_atten;
1685}
1686
1687/**
75bcfae9 1688 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1689 *
1690 * Configures power settings for all rates for the current channel,
1691 * using values from channel info struct, and send to NIC
1692 */
dfb39e82 1693static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1694{
14577f23 1695 int rate_idx, i;
d20b3c65 1696 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1697 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1698 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1699 };
1700
8318d78a 1701 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1702 ch_info = iwl_get_channel_info(priv,
8318d78a 1703 priv->band,
8ccde88a 1704 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1705 if (!ch_info) {
15b1687c
WT		 1706 IWL_ERR(priv,
1707 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1708 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1709 return -EINVAL;
1710 }
1711
1712 if (!is_channel_valid(ch_info)) {
1713 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1714 "non-Tx channel.\n");
1715 return 0;
1716 }
1717
1718 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1719 /* Fill OFDM rate */
1720 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1721 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1722
1723 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1724 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1725
1726 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1727 le16_to_cpu(txpower.channel),
1728 txpower.band,
14577f23
MA		 1729 txpower.power[i].tpc.tx_gain,
1730 txpower.power[i].tpc.dsp_atten,
1731 txpower.power[i].rate);
1732 }
1733 /* Fill CCK rates */
1734 for (rate_idx = IWL_FIRST_CCK_RATE;
1735 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1736 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1737 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1738
1739 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1740 le16_to_cpu(txpower.channel),
1741 txpower.band,
1742 txpower.power[i].tpc.tx_gain,
1743 txpower.power[i].tpc.dsp_atten,
1744 txpower.power[i].rate);
b481de9c
ZY		 1745 }
1746
518099a8
SO		 1747 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1748 sizeof(struct iwl3945_txpowertable_cmd),
1749 &txpower);
b481de9c
ZY		 1750
1751}
1752
1753/**
bb8c093b 1754 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1755 * @ch_info: Channel to update. Uses power_info.requested_power.
1756 *
1757 * Replace requested_power and base_power_index ch_info fields for
1758 * one channel.
1759 *
1760 * Called if user or spectrum management changes power preferences.
1761 * Takes into account h/w and modulation limitations (clip power).
1762 *
1763 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1764 *
1765 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1766 * properly fill out the scan powers, and actual h/w gain settings,
1767 * and send changes to NIC
1768 */
4a8a4322 1769static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1770 struct iwl_channel_info *ch_info)
b481de9c 1771{
bb8c093b 1772 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1773 int power_changed = 0;
1774 int i;
1775 const s8 *clip_pwrs;
1776 int power;
1777
1778 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1779 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1780
1781 /* Get this channel's rate-to-current-power settings table */
1782 power_info = ch_info->power_info;
1783
1784 /* update OFDM Txpower settings */
14577f23 1785 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1786 i++, ++power_info) {
1787 int delta_idx;
1788
1789 /* limit new power to be no more than h/w capability */
1790 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1791 if (power == power_info->requested_power)
1792 continue;
1793
1794 /* find difference between old and new requested powers,
1795 * update base (non-temp-compensated) power index */
1796 delta_idx = (power - power_info->requested_power) * 2;
1797 power_info->base_power_index -= delta_idx;
1798
1799 /* save new requested power value */
1800 power_info->requested_power = power;
1801
1802 power_changed = 1;
1803 }
1804
1805 /* update CCK Txpower settings, based on OFDM 12M setting ...
1806 * ... all CCK power settings for a given channel are the *same*. */
1807 if (power_changed) {
1808 power =
14577f23 1809 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1810 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1811
bb8c093b 1812 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1813 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1814 power_info->requested_power = power;
1815 power_info->base_power_index =
14577f23 1816 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1817 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1818 ++power_info;
1819 }
1820 }
1821
1822 return 0;
1823}
1824
1825/**
bb8c093b 1826 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1827 *
1828 * NOTE: Returned power limit may be less (but not more) than requested,
1829 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1830 * (no consideration for h/w clipping limitations).
1831 */
d20b3c65 1832static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1833{
1834 s8 max_power;
1835
1836#if 0
1837 /* if we're using TGd limits, use lower of TGd or EEPROM */
1838 if (ch_info->tgd_data.max_power != 0)
1839 max_power = min(ch_info->tgd_data.max_power,
1840 ch_info->eeprom.max_power_avg);
1841
1842 /* else just use EEPROM limits */
1843 else
1844#endif
1845 max_power = ch_info->eeprom.max_power_avg;
1846
1847 return min(max_power, ch_info->max_power_avg);
1848}
1849
1850/**
bb8c093b 1851 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1852 *
1853 * Compensate txpower settings of *all* channels for temperature.
1854 * This only accounts for the difference between current temperature
1855 * and the factory calibration temperatures, and bases the new settings
1856 * on the channel's base_power_index.
1857 *
1858 * If RxOn is "associated", this sends the new Txpower to NIC!
1859 */
4a8a4322 1860static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1861{
d20b3c65 1862 struct iwl_channel_info *ch_info = NULL;
e6148917 1863 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1864 int delta_index;
1865 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1866 u8 a_band;
1867 u8 rate_index;
1868 u8 scan_tbl_index;
1869 u8 i;
1870 int ref_temp;
1871 int temperature = priv->temperature;
1872
1873 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1874 for (i = 0; i < priv->channel_count; i++) {
1875 ch_info = &priv->channel_info[i];
1876 a_band = is_channel_a_band(ch_info);
1877
1878 /* Get this chnlgrp's factory calibration temperature */
e6148917 1879 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1880 temperature;
1881
a96a27f9 1882 /* get power index adjustment based on current and factory
b481de9c 1883 * temps */
bb8c093b 1884 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1885 ref_temp);
1886
1887 /* set tx power value for all rates, OFDM and CCK */
1888 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1889 rate_index++) {
1890 int power_idx =
1891 ch_info->power_info[rate_index].base_power_index;
1892
1893 /* temperature compensate */
1894 power_idx += delta_index;
1895
1896 /* stay within table range */
bb8c093b 1897 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1898 ch_info->power_info[rate_index].
1899 power_table_index = (u8) power_idx;
1900 ch_info->power_info[rate_index].tpc =
1901 power_gain_table[a_band][power_idx];
1902 }
1903
1904 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1905 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1906
1907 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1908 for (scan_tbl_index = 0;
1909 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1910 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1911 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1912 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1913 actual_index, clip_pwrs,
1914 ch_info, a_band);
1915 }
1916 }
1917
1918 /* send Txpower command for current channel to ucode */
75bcfae9 1919 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1920}
1921
4a8a4322 1922int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1923{
d20b3c65 1924 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1925 s8 max_power;
1926 u8 a_band;
1927 u8 i;
1928
62ea9c5b 1929 if (priv->tx_power_user_lmt == power) {
b481de9c
ZY		 1930 IWL_DEBUG_POWER("Requested Tx power same as current "
1931 "limit: %ddBm.\n", power);
1932 return 0;
1933 }
1934
1935 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1936 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1937
1938 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1939
1940 for (i = 0; i < priv->channel_count; i++) {
1941 ch_info = &priv->channel_info[i];
1942 a_band = is_channel_a_band(ch_info);
1943
1944 /* find minimum power of all user and regulatory constraints
1945 * (does not consider h/w clipping limitations) */
bb8c093b 1946 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1947 max_power = min(power, max_power);
1948 if (max_power != ch_info->curr_txpow) {
1949 ch_info->curr_txpow = max_power;
1950
1951 /* this considers the h/w clipping limitations */
bb8c093b 1952 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1953 }
1954 }
1955
1956 /* update txpower settings for all channels,
1957 * send to NIC if associated. */
1958 is_temp_calib_needed(priv);
bb8c093b 1959 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1960
1961 return 0;
1962}
1963
1964/* will add 3945 channel switch cmd handling later */
4a8a4322 1965int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1966{
1967 return 0;
1968}
1969
1970/**
1971 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1972 *
1973 * -- reset periodic timer
1974 * -- see if temp has changed enough to warrant re-calibration ... if so:
1975 * -- correct coeffs for temp (can reset temp timer)
1976 * -- save this temp as "last",
1977 * -- send new set of gain settings to NIC
1978 * NOTE: This should continue working, even when we're not associated,
1979 * so we can keep our internal table of scan powers current. */
4a8a4322 1980void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1981{
1982 /* This will kick in the "brute force"
bb8c093b 1983 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1984 if (!is_temp_calib_needed(priv))
1985 goto reschedule;
1986
1987 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1988 * This is based *only* on current temperature,
1989 * ignoring any previous power measurements */
bb8c093b 1990 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1991
1992 reschedule:
1993 queue_delayed_work(priv->workqueue,
1994 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1995}
1996
416e1438 1997static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1998{
4a8a4322 1999 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2000 thermal_periodic.work);
2001
2002 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2003 return;
2004
2005 mutex_lock(&priv->mutex);
2006 iwl3945_reg_txpower_periodic(priv);
2007 mutex_unlock(&priv->mutex);
2008}
2009
2010/**
bb8c093b 2011 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2012 * for the channel.
2013 *
2014 * This function is used when initializing channel-info structs.
2015 *
2016 * NOTE: These channel groups do *NOT* match the bands above!
2017 * These channel groups are based on factory-tested channels;
2018 * on A-band, EEPROM's "group frequency" entries represent the top
2019 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2020 */
4a8a4322 2021static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2022 const struct iwl_channel_info *ch_info)
b481de9c 2023{
e6148917
SO		 2024 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2025 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2026 u8 group;
2027 u16 group_index = 0; /* based on factory calib frequencies */
2028 u8 grp_channel;
2029
2030 /* Find the group index for the channel ... don't use index 1(?) */
2031 if (is_channel_a_band(ch_info)) {
2032 for (group = 1; group < 5; group++) {
2033 grp_channel = ch_grp[group].group_channel;
2034 if (ch_info->channel <= grp_channel) {
2035 group_index = group;
2036 break;
2037 }
2038 }
2039 /* group 4 has a few channels *above* its factory cal freq */
2040 if (group == 5)
2041 group_index = 4;
2042 } else
2043 group_index = 0; /* 2.4 GHz, group 0 */
2044
2045 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2046 group_index);
2047 return group_index;
2048}
2049
2050/**
bb8c093b 2051 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2052 *
2053 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2054 * into radio/DSP gain settings table for requested power.
2055 */
4a8a4322 2056static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2057 s8 requested_power,
2058 s32 setting_index, s32 *new_index)
2059{
bb8c093b 2060 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2061 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2062 s32 index0, index1;
2063 s32 power = 2 * requested_power;
2064 s32 i;
bb8c093b 2065 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2066 s32 gains0, gains1;
2067 s32 res;
2068 s32 denominator;
2069
e6148917 2070 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2071 samples = chnl_grp->samples;
2072 for (i = 0; i < 5; i++) {
2073 if (power == samples[i].power) {
2074 *new_index = samples[i].gain_index;
2075 return 0;
2076 }
2077 }
2078
2079 if (power > samples[1].power) {
2080 index0 = 0;
2081 index1 = 1;
2082 } else if (power > samples[2].power) {
2083 index0 = 1;
2084 index1 = 2;
2085 } else if (power > samples[3].power) {
2086 index0 = 2;
2087 index1 = 3;
2088 } else {
2089 index0 = 3;
2090 index1 = 4;
2091 }
2092
2093 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2094 if (denominator == 0)
2095 return -EINVAL;
2096 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2097 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2098 res = gains0 + (gains1 - gains0) *
2099 ((s32) power - (s32) samples[index0].power) / denominator +
2100 (1 << 18);
2101 *new_index = res >> 19;
2102 return 0;
2103}
2104
4a8a4322 2105static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2106{
2107 u32 i;
2108 s32 rate_index;
e6148917 2109 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2110 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2111
2112 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2113
2114 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2115 s8 *clip_pwrs; /* table of power levels for each rate */
2116 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2117 group = &eeprom->groups[i];
b481de9c
ZY		 2118
2119 /* sanity check on factory saturation power value */
2120 if (group->saturation_power < 40) {
39aadf8c 2121 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2122 "less than minimum expected 40\n",
2123 group->saturation_power);
2124 return;
2125 }
2126
2127 /*
2128 * Derive requested power levels for each rate, based on
2129 * hardware capabilities (saturation power for band).
2130 * Basic value is 3dB down from saturation, with further
2131 * power reductions for highest 3 data rates. These
2132 * backoffs provide headroom for high rate modulation
2133 * power peaks, without too much distortion (clipping).
2134 */
2135 /* we'll fill in this array with h/w max power levels */
f2c7e521 2136 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2137
2138 /* divide factory saturation power by 2 to find -3dB level */
2139 satur_pwr = (s8) (group->saturation_power >> 1);
2140
2141 /* fill in channel group's nominal powers for each rate */
2142 for (rate_index = 0;
2143 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2144 switch (rate_index) {
14577f23 2145 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2146 if (i == 0) /* B/G */
2147 *clip_pwrs = satur_pwr;
2148 else /* A */
2149 *clip_pwrs = satur_pwr - 5;
2150 break;
14577f23 2151 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2152 if (i == 0)
2153 *clip_pwrs = satur_pwr - 7;
2154 else
2155 *clip_pwrs = satur_pwr - 10;
2156 break;
14577f23 2157 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2158 if (i == 0)
2159 *clip_pwrs = satur_pwr - 9;
2160 else
2161 *clip_pwrs = satur_pwr - 12;
2162 break;
2163 default:
2164 *clip_pwrs = satur_pwr;
2165 break;
2166 }
2167 }
2168 }
2169}
2170
2171/**
2172 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2173 *
2174 * Second pass (during init) to set up priv->channel_info
2175 *
2176 * Set up Tx-power settings in our channel info database for each VALID
2177 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2178 * and current temperature.
2179 *
2180 * Since this is based on current temperature (at init time), these values may
2181 * not be valid for very long, but it gives us a starting/default point,
2182 * and allows us to active (i.e. using Tx) scan.
2183 *
2184 * This does *not* write values to NIC, just sets up our internal table.
2185 */
4a8a4322 2186int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2187{
d20b3c65 2188 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2189 struct iwl3945_channel_power_info *pwr_info;
e6148917 2190 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2191 int delta_index;
2192 u8 rate_index;
2193 u8 scan_tbl_index;
2194 const s8 *clip_pwrs; /* array of power levels for each rate */
2195 u8 gain, dsp_atten;
2196 s8 power;
2197 u8 pwr_index, base_pwr_index, a_band;
2198 u8 i;
2199 int temperature;
2200
2201 /* save temperature reference,
2202 * so we can determine next time to calibrate */
bb8c093b 2203 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2204 priv->last_temperature = temperature;
2205
bb8c093b 2206 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2207
2208 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2209 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2210 i++, ch_info++) {
2211 a_band = is_channel_a_band(ch_info);
2212 if (!is_channel_valid(ch_info))
2213 continue;
2214
2215 /* find this channel's channel group (*not* "band") index */
2216 ch_info->group_index =
bb8c093b 2217 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2218
2219 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2220 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2221
2222 /* calculate power index *adjustment* value according to
2223 * diff between current temperature and factory temperature */
bb8c093b 2224 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2225 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2226 temperature);
2227
2228 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2229 ch_info->channel, delta_index, temperature +
2230 IWL_TEMP_CONVERT);
2231
2232 /* set tx power value for all OFDM rates */
2233 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2234 rate_index++) {
25a4ccea 2235 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2236 int rc;
2237
2238 /* use channel group's clip-power table,
2239 * but don't exceed channel's max power */
2240 s8 pwr = min(ch_info->max_power_avg,
2241 clip_pwrs[rate_index]);
2242
2243 pwr_info = &ch_info->power_info[rate_index];
2244
2245 /* get base (i.e. at factory-measured temperature)
2246 * power table index for this rate's power */
bb8c093b 2247 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2248 ch_info->group_index,
2249 &power_idx);
2250 if (rc) {
15b1687c 2251 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2252 return rc;
2253 }
2254 pwr_info->base_power_index = (u8) power_idx;
2255
2256 /* temperature compensate */
2257 power_idx += delta_index;
2258
2259 /* stay within range of gain table */
bb8c093b 2260 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2261
bb8c093b 2262 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2263 pwr_info->requested_power = pwr;
2264 pwr_info->power_table_index = (u8) power_idx;
2265 pwr_info->tpc.tx_gain =
2266 power_gain_table[a_band][power_idx].tx_gain;
2267 pwr_info->tpc.dsp_atten =
2268 power_gain_table[a_band][power_idx].dsp_atten;
2269 }
2270
2271 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2272 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2273 power = pwr_info->requested_power +
2274 IWL_CCK_FROM_OFDM_POWER_DIFF;
2275 pwr_index = pwr_info->power_table_index +
2276 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2277 base_pwr_index = pwr_info->base_power_index +
2278 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2279
2280 /* stay within table range */
bb8c093b 2281 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2282 gain = power_gain_table[a_band][pwr_index].tx_gain;
2283 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2284
bb8c093b 2285 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2286 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2287 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2288 for (rate_index = 0;
2289 rate_index < IWL_CCK_RATES; rate_index++) {
2290 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2291 pwr_info->requested_power = power;
2292 pwr_info->power_table_index = pwr_index;
2293 pwr_info->base_power_index = base_pwr_index;
2294 pwr_info->tpc.tx_gain = gain;
2295 pwr_info->tpc.dsp_atten = dsp_atten;
2296 }
2297
2298 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2299 for (scan_tbl_index = 0;
2300 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2301 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2302 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2303 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2304 actual_index, clip_pwrs, ch_info, a_band);
2305 }
2306 }
2307
2308 return 0;
2309}
2310
4a8a4322 2311int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2312{
2313 int rc;
2314 unsigned long flags;
2315
2316 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2317 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2318 if (rc) {
2319 spin_unlock_irqrestore(&priv->lock, flags);
2320 return rc;
2321 }
2322
5d49f498
AK		 2323 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2324 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2325 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2326 if (rc < 0)
15b1687c 2327 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2328
5d49f498 2329 iwl_release_nic_access(priv);
b481de9c
ZY		 2330 spin_unlock_irqrestore(&priv->lock, flags);
2331
2332 return 0;
2333}
2334
188cf6c7 2335int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c
ZY		 2336{
2337 int rc;
2338 unsigned long flags;
2339 int txq_id = txq->q.id;
2340
3832ec9d 2341 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2342
2343 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2344
2345 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2346 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2347 if (rc) {
2348 spin_unlock_irqrestore(&priv->lock, flags);
2349 return rc;
2350 }
5d49f498
AK		 2351 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2352 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2353
5d49f498 2354 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2355 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2356 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2357 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2358 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2359 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
5d49f498 2360 iwl_release_nic_access(priv);
b481de9c
ZY		 2361
2362 /* fake read to flush all prev. writes */
5d49f498 2363 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2364 spin_unlock_irqrestore(&priv->lock, flags);
2365
2366 return 0;
2367}
2368
42427b4e
KA		 2369/*
2370 * HCMD utils
2371 */
2372static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2373{
2374 switch (cmd_id) {
2375 case REPLY_RXON:
2376 return (u16) sizeof(struct iwl3945_rxon_cmd);
2377 default:
2378 return len;
2379 }
2380}
2381
17f841cd
SO		 2382static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2383{
2384 u16 size = (u16)sizeof(struct iwl3945_addsta_cmd);
2385 memcpy(data, cmd, size);
2386 return size;
2387}
2388
b481de9c
ZY		 2389/**
2390 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2391 */
4a8a4322 2392int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2393{
14577f23 2394 int rc, i, index, prev_index;
bb8c093b 2395 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2396 .reserved = {0, 0, 0},
2397 };
bb8c093b 2398 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2399
bb8c093b
CH		 2400 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2401 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2402
2403 table[index].rate_n_flags =
bb8c093b 2404 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2405 table[index].try_cnt = priv->retry_rate;
bb8c093b 2406 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2407 table[index].next_rate_index =
2408 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2409 }
2410
8318d78a
JB		 2411 switch (priv->band) {
2412 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2413 IWL_DEBUG_RATE("Select A mode rate scale\n");
2414 /* If one of the following CCK rates is used,
2415 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2416 for (i = IWL_RATE_1M_INDEX_TABLE;
2417 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2418 table[i].next_rate_index =
2419 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2420
2421 /* Don't fall back to CCK rates */
7262796a
AM		 2422 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2423 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2424
2425 /* Don't drop out of OFDM rates */
14577f23 2426 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2427 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2428 break;
2429
8318d78a
JB		 2430 case IEEE80211_BAND_2GHZ:
2431 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2432 /* If an OFDM rate is used, have it fall back to the
2433 * 1M CCK rates */
b481de9c 2434
7262796a 2435 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2436 iwl_is_associated(priv)) {
7262796a
AM		 2437
2438 index = IWL_FIRST_CCK_RATE;
2439 for (i = IWL_RATE_6M_INDEX_TABLE;
2440 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2441 table[i].next_rate_index =
2442 iwl3945_rates[index].table_rs_index;
2443
2444 index = IWL_RATE_11M_INDEX_TABLE;
2445 /* CCK shouldn't fall back to OFDM... */
2446 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2447 }
b481de9c
ZY		 2448 break;
2449
2450 default:
8318d78a 2451 WARN_ON(1);
b481de9c
ZY		 2452 break;
2453 }
2454
2455 /* Update the rate scaling for control frame Tx */
2456 rate_cmd.table_id = 0;
518099a8 2457 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2458 &rate_cmd);
2459 if (rc)
2460 return rc;
2461
2462 /* Update the rate scaling for data frame Tx */
2463 rate_cmd.table_id = 1;
518099a8 2464 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2465 &rate_cmd);
2466}
2467
796083cb 2468/* Called when initializing driver */
4a8a4322 2469int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2470{
3832ec9d
AK		 2471 memset((void *)&priv->hw_params, 0,
2472 sizeof(struct iwl_hw_params));
b481de9c 2473
3832ec9d 2474 priv->shared_virt =
b481de9c 2475 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2476 sizeof(struct iwl3945_shared),
3832ec9d 2477 &priv->shared_phys);
b481de9c 2478
3832ec9d 2479 if (!priv->shared_virt) {
15b1687c 2480 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2481 mutex_unlock(&priv->mutex);
2482 return -ENOMEM;
2483 }
2484
a8e74e27 2485 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
1e33dc64 2486 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
3832ec9d
AK		 2487 priv->hw_params.max_pkt_size = 2342;
2488 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2489 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2490 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2491 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2492
141c43a3
WT		 2493 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2494
b481de9c
ZY		 2495 return 0;
2496}
2497
4a8a4322 2498unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2499 struct iwl3945_frame *frame, u8 rate)
b481de9c 2500{
bb8c093b 2501 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2502 unsigned int frame_size;
2503
bb8c093b 2504 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2505 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2506
3832ec9d 2507 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2508 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2509
bb8c093b 2510 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2511 tx_beacon_cmd->frame,
b481de9c
ZY		 2512 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2513
2514 BUG_ON(frame_size > MAX_MPDU_SIZE);
2515 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2516
2517 tx_beacon_cmd->tx.rate = rate;
2518 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2519 TX_CMD_FLG_TSF_MSK);
2520
14577f23
MA		 2521 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2522 tx_beacon_cmd->tx.supp_rates[0] =
2523 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2524
b481de9c 2525 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2526 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2527
3ac7f146 2528 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2529}
2530
4a8a4322 2531void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2532{
91c066f2 2533 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2534 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2535}
2536
4a8a4322 2537void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2538{
2539 INIT_DELAYED_WORK(&priv->thermal_periodic,
2540 iwl3945_bg_reg_txpower_periodic);
2541}
2542
4a8a4322 2543void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2544{
2545 cancel_delayed_work(&priv->thermal_periodic);
2546}
2547
0164b9b4
KA		 2548/* check contents of special bootstrap uCode SRAM */
2549static int iwl3945_verify_bsm(struct iwl_priv *priv)
2550 {
2551 __le32 *image = priv->ucode_boot.v_addr;
2552 u32 len = priv->ucode_boot.len;
2553 u32 reg;
2554 u32 val;
2555
2556 IWL_DEBUG_INFO("Begin verify bsm\n");
2557
2558 /* verify BSM SRAM contents */
2559 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2560 for (reg = BSM_SRAM_LOWER_BOUND;
2561 reg < BSM_SRAM_LOWER_BOUND + len;
2562 reg += sizeof(u32), image++) {
2563 val = iwl_read_prph(priv, reg);
2564 if (val != le32_to_cpu(*image)) {
2565 IWL_ERR(priv, "BSM uCode verification failed at "
2566 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2567 BSM_SRAM_LOWER_BOUND,
2568 reg - BSM_SRAM_LOWER_BOUND, len,
2569 val, le32_to_cpu(*image));
2570 return -EIO;
2571 }
2572 }
2573
2574 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2575
2576 return 0;
2577}
2578
e6148917
SO		 2579
2580/******************************************************************************
2581 *
2582 * EEPROM related functions
2583 *
2584 ******************************************************************************/
2585
2586/*
2587 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2588 * embedded controller) as EEPROM reader; each read is a series of pulses
2589 * to/from the EEPROM chip, not a single event, so even reads could conflict
2590 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2591 * simply claims ownership, which should be safe when this function is called
2592 * (i.e. before loading uCode!).
2593 */
2594static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2595{
2596 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2597 return 0;
2598}
2599
2600
2601static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2602{
2603 return;
2604}
2605
0164b9b4
KA		 2606 /**
2607 * iwl3945_load_bsm - Load bootstrap instructions
2608 *
2609 * BSM operation:
2610 *
2611 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2612 * in special SRAM that does not power down during RFKILL. When powering back
2613 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2614 * the bootstrap program into the on-board processor, and starts it.
2615 *
2616 * The bootstrap program loads (via DMA) instructions and data for a new
2617 * program from host DRAM locations indicated by the host driver in the
2618 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2619 * automatically.
2620 *
2621 * When initializing the NIC, the host driver points the BSM to the
2622 * "initialize" uCode image. This uCode sets up some internal data, then
2623 * notifies host via "initialize alive" that it is complete.
2624 *
2625 * The host then replaces the BSM_DRAM_* pointer values to point to the
2626 * normal runtime uCode instructions and a backup uCode data cache buffer
2627 * (filled initially with starting data values for the on-board processor),
2628 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2629 * which begins normal operation.
2630 *
2631 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2632 * the backup data cache in DRAM before SRAM is powered down.
2633 *
2634 * When powering back up, the BSM loads the bootstrap program. This reloads
2635 * the runtime uCode instructions and the backup data cache into SRAM,
2636 * and re-launches the runtime uCode from where it left off.
2637 */
2638static int iwl3945_load_bsm(struct iwl_priv *priv)
2639{
2640 __le32 *image = priv->ucode_boot.v_addr;
2641 u32 len = priv->ucode_boot.len;
2642 dma_addr_t pinst;
2643 dma_addr_t pdata;
2644 u32 inst_len;
2645 u32 data_len;
2646 int rc;
2647 int i;
2648 u32 done;
2649 u32 reg_offset;
2650
2651 IWL_DEBUG_INFO("Begin load bsm\n");
2652
2653 /* make sure bootstrap program is no larger than BSM's SRAM size */
2654 if (len > IWL39_MAX_BSM_SIZE)
2655 return -EINVAL;
2656
2657 /* Tell bootstrap uCode where to find the "Initialize" uCode
2658 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2659 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2660 * after the "initialize" uCode has run, to point to
2661 * runtime/protocol instructions and backup data cache. */
2662 pinst = priv->ucode_init.p_addr;
2663 pdata = priv->ucode_init_data.p_addr;
2664 inst_len = priv->ucode_init.len;
2665 data_len = priv->ucode_init_data.len;
2666
2667 rc = iwl_grab_nic_access(priv);
2668 if (rc)
2669 return rc;
2670
2671 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2672 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2673 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2674 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2675
2676 /* Fill BSM memory with bootstrap instructions */
2677 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2678 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2679 reg_offset += sizeof(u32), image++)
2680 _iwl_write_prph(priv, reg_offset,
2681 le32_to_cpu(*image));
2682
2683 rc = iwl3945_verify_bsm(priv);
2684 if (rc) {
2685 iwl_release_nic_access(priv);
2686 return rc;
2687 }
2688
2689 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2690 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2691 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2692 IWL39_RTC_INST_LOWER_BOUND);
2693 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2694
2695 /* Load bootstrap code into instruction SRAM now,
2696 * to prepare to load "initialize" uCode */
2697 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2698 BSM_WR_CTRL_REG_BIT_START);
2699
2700 /* Wait for load of bootstrap uCode to finish */
2701 for (i = 0; i < 100; i++) {
2702 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2703 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2704 break;
2705 udelay(10);
2706 }
2707 if (i < 100)
2708 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2709 else {
2710 IWL_ERR(priv, "BSM write did not complete!\n");
2711 return -EIO;
2712 }
2713
2714 /* Enable future boot loads whenever power management unit triggers it
2715 * (e.g. when powering back up after power-save shutdown) */
2716 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2717 BSM_WR_CTRL_REG_BIT_START_EN);
2718
2719 iwl_release_nic_access(priv);
2720
2721 return 0;
2722}
2723
2724static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2725 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2726 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2727 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2728 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2729 .apm_ops = {
2730 .init = iwl3945_apm_init,
2731 .reset = iwl3945_apm_reset,
2732 .stop = iwl3945_apm_stop,
2733 .config = iwl3945_nic_config,
854682ed 2734 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2735 },
e6148917
SO		 2736 .eeprom_ops = {
2737 .regulatory_bands = {
2738 EEPROM_REGULATORY_BAND_1_CHANNELS,
2739 EEPROM_REGULATORY_BAND_2_CHANNELS,
2740 EEPROM_REGULATORY_BAND_3_CHANNELS,
2741 EEPROM_REGULATORY_BAND_4_CHANNELS,
2742 EEPROM_REGULATORY_BAND_5_CHANNELS,
2743 IWL3945_EEPROM_IMG_SIZE,
2744 IWL3945_EEPROM_IMG_SIZE,
2745 },
2746 .verify_signature = iwlcore_eeprom_verify_signature,
2747 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2748 .release_semaphore = iwl3945_eeprom_release_semaphore,
2749 .query_addr = iwlcore_eeprom_query_addr,
2750 },
75bcfae9 2751 .send_tx_power = iwl3945_send_tx_power,
0164b9b4
KA		 2752};
2753
42427b4e
KA		 2754static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2755 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2756 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
42427b4e
KA		 2757};
2758
0164b9b4
KA		 2759static struct iwl_ops iwl3945_ops = {
2760 .lib = &iwl3945_lib,
42427b4e 2761 .utils = &iwl3945_hcmd_utils,
0164b9b4
KA		 2762};
2763
c0f20d91 2764static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2765 .name = "3945BG",
a0987a8d
RC		 2766 .fw_name_pre = IWL3945_FW_PRE,
2767 .ucode_api_max = IWL3945_UCODE_API_MAX,
2768 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2769 .sku = IWL_SKU_G,
e6148917
SO		 2770 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2771 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2772 .ops = &iwl3945_ops,
df878d8f 2773 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2774};
2775
c0f20d91 2776static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2777 .name = "3945ABG",
a0987a8d
RC		 2778 .fw_name_pre = IWL3945_FW_PRE,
2779 .ucode_api_max = IWL3945_UCODE_API_MAX,
2780 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2781 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2782 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2783 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2784 .ops = &iwl3945_ops,
df878d8f 2785 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2786};
2787
bb8c093b 2788struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2789 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2790 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2791 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2792 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2793 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2794 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2795 {0}
2796};
2797
bb8c093b 2798MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)