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iwlwifi: add thermal throttling support to 5150
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
17f841cd 44#include "iwl-sta.h"
b481de9c 45#include "iwl-3945.h"
e6148917 46#include "iwl-eeprom.h"
5d08cd1d 47#include "iwl-helpers.h"
5747d47f 48#include "iwl-core.h"
d9829a67 49#include "iwl-agn-rs.h"
b481de9c
ZY		 50
51#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
52 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 59 IWL_RATE_##np##M_INDEX, \
60 IWL_RATE_##r##M_INDEX_TABLE, \
61 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 62
63/*
64 * Parameter order:
65 * rate, prev rate, next rate, prev tgg rate, next tgg rate
66 *
67 * If there isn't a valid next or previous rate then INV is used which
68 * maps to IWL_RATE_INVALID
69 *
70 */
d9829a67 71const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 72 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
73 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
74 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
75 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 76 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
77 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
78 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
79 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
80 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
81 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
82 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
83 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 84};
85
bb8c093b 86/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 87#define IWL_EVT_DISABLE (0)
88#define IWL_EVT_DISABLE_SIZE (1532/32)
89
90/**
bb8c093b 91 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 92 *
93 * Disable an event by writing "1"s into "disable"
94 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
95 * Default values of 0 enable uCode events to be logged.
96 * Use for only special debugging. This function is just a placeholder as-is,
97 * you'll need to provide the special bits! ...
98 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 99void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 100{
b481de9c
ZY		 101 int i;
102 u32 base; /* SRAM address of event log header */
103 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
104 u32 array_size; /* # of u32 entries in array */
105 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
106 0x00000000, /* 31 - 0 Event id numbers */
107 0x00000000, /* 63 - 32 */
108 0x00000000, /* 95 - 64 */
109 0x00000000, /* 127 - 96 */
110 0x00000000, /* 159 - 128 */
111 0x00000000, /* 191 - 160 */
112 0x00000000, /* 223 - 192 */
113 0x00000000, /* 255 - 224 */
114 0x00000000, /* 287 - 256 */
115 0x00000000, /* 319 - 288 */
116 0x00000000, /* 351 - 320 */
117 0x00000000, /* 383 - 352 */
118 0x00000000, /* 415 - 384 */
119 0x00000000, /* 447 - 416 */
120 0x00000000, /* 479 - 448 */
121 0x00000000, /* 511 - 480 */
122 0x00000000, /* 543 - 512 */
123 0x00000000, /* 575 - 544 */
124 0x00000000, /* 607 - 576 */
125 0x00000000, /* 639 - 608 */
126 0x00000000, /* 671 - 640 */
127 0x00000000, /* 703 - 672 */
128 0x00000000, /* 735 - 704 */
129 0x00000000, /* 767 - 736 */
130 0x00000000, /* 799 - 768 */
131 0x00000000, /* 831 - 800 */
132 0x00000000, /* 863 - 832 */
133 0x00000000, /* 895 - 864 */
134 0x00000000, /* 927 - 896 */
135 0x00000000, /* 959 - 928 */
136 0x00000000, /* 991 - 960 */
137 0x00000000, /* 1023 - 992 */
138 0x00000000, /* 1055 - 1024 */
139 0x00000000, /* 1087 - 1056 */
140 0x00000000, /* 1119 - 1088 */
141 0x00000000, /* 1151 - 1120 */
142 0x00000000, /* 1183 - 1152 */
143 0x00000000, /* 1215 - 1184 */
144 0x00000000, /* 1247 - 1216 */
145 0x00000000, /* 1279 - 1248 */
146 0x00000000, /* 1311 - 1280 */
147 0x00000000, /* 1343 - 1312 */
148 0x00000000, /* 1375 - 1344 */
149 0x00000000, /* 1407 - 1376 */
150 0x00000000, /* 1439 - 1408 */
151 0x00000000, /* 1471 - 1440 */
152 0x00000000, /* 1503 - 1472 */
153 };
154
155 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 156 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 157 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 158 return;
159 }
160
5d49f498
AK		 161 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
162 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 163
164 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 165 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 166 disable_ptr);
b481de9c 167 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 168 iwl_write_targ_mem(priv,
af7cca2a
TW		 169 disable_ptr + (i * sizeof(u32)),
170 evt_disable[i]);
b481de9c 171
b481de9c 172 } else {
e1623446
TW		 173 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
174 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
175 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 176 disable_ptr, array_size);
177 }
178
179}
180
17744ff6
TW		 181static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
182{
183 int idx;
184
185 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
186 if (iwl3945_rates[idx].plcp == plcp)
187 return idx;
188 return -1;
189}
190
d08853a3 191#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 192#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
193
194static const char *iwl3945_get_tx_fail_reason(u32 status)
195{
196 switch (status & TX_STATUS_MSK) {
197 case TX_STATUS_SUCCESS:
198 return "SUCCESS";
199 TX_STATUS_ENTRY(SHORT_LIMIT);
200 TX_STATUS_ENTRY(LONG_LIMIT);
201 TX_STATUS_ENTRY(FIFO_UNDERRUN);
202 TX_STATUS_ENTRY(MGMNT_ABORT);
203 TX_STATUS_ENTRY(NEXT_FRAG);
204 TX_STATUS_ENTRY(LIFE_EXPIRE);
205 TX_STATUS_ENTRY(DEST_PS);
206 TX_STATUS_ENTRY(ABORTED);
207 TX_STATUS_ENTRY(BT_RETRY);
208 TX_STATUS_ENTRY(STA_INVALID);
209 TX_STATUS_ENTRY(FRAG_DROPPED);
210 TX_STATUS_ENTRY(TID_DISABLE);
211 TX_STATUS_ENTRY(FRAME_FLUSHED);
212 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
213 TX_STATUS_ENTRY(TX_LOCKED);
214 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
215 }
216
217 return "UNKNOWN";
218}
219#else
220static inline const char *iwl3945_get_tx_fail_reason(u32 status)
221{
222 return "";
223}
224#endif
225
e6a9854b
JB		 226/*
227 * get ieee prev rate from rate scale table.
228 * for A and B mode we need to overright prev
229 * value
230 */
4a8a4322 231int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 232{
233 int next_rate = iwl3945_get_prev_ieee_rate(rate);
234
235 switch (priv->band) {
236 case IEEE80211_BAND_5GHZ:
237 if (rate == IWL_RATE_12M_INDEX)
238 next_rate = IWL_RATE_9M_INDEX;
239 else if (rate == IWL_RATE_6M_INDEX)
240 next_rate = IWL_RATE_6M_INDEX;
241 break;
7262796a
AM		 242 case IEEE80211_BAND_2GHZ:
243 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 244 iwl_is_associated(priv)) {
7262796a
AM		 245 if (rate == IWL_RATE_11M_INDEX)
246 next_rate = IWL_RATE_5M_INDEX;
247 }
e6a9854b 248 break;
7262796a 249
e6a9854b
JB		 250 default:
251 break;
252 }
253
254 return next_rate;
255}
256
91c066f2
TW		 257
258/**
259 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
260 *
261 * When FW advances 'R' index, all entries between old and new 'R' index
262 * need to be reclaimed. As result, some free space forms. If there is
263 * enough free space (> low mark), wake the stack that feeds us.
264 */
4a8a4322 265static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 266 int txq_id, int index)
267{
188cf6c7 268 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 269 struct iwl_queue *q = &txq->q;
dbb6654c 270 struct iwl_tx_info *tx_info;
91c066f2
TW		 271
272 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
273
274 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
275 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
276
277 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 278 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 279 tx_info->skb[0] = NULL;
7aaa1d79 280 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 281 }
282
d20b3c65 283 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 284 (txq_id != IWL_CMD_QUEUE_NUM) &&
285 priv->mac80211_registered)
e4e72fb4 286 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 287}
288
289/**
290 * iwl3945_rx_reply_tx - Handle Tx response
291 */
4a8a4322 292static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 293 struct iwl_rx_mem_buffer *rxb)
91c066f2 294{
3d24a9f7 295 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 296 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
297 int txq_id = SEQ_TO_QUEUE(sequence);
298 int index = SEQ_TO_INDEX(sequence);
188cf6c7 299 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 300 struct ieee80211_tx_info *info;
91c066f2
TW		 301 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
302 u32 status = le32_to_cpu(tx_resp->status);
303 int rate_idx;
74221d07 304 int fail;
91c066f2 305
625a381a 306 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 307 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 308 "is out of range [0-%d] %d %d\n", txq_id,
309 index, txq->q.n_bd, txq->q.write_ptr,
310 txq->q.read_ptr);
311 return;
312 }
313
e039fa4a 314 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 315 ieee80211_tx_info_clear_status(info);
316
317 /* Fill the MRR chain with some info about on-chip retransmissions */
318 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
319 if (info->band == IEEE80211_BAND_5GHZ)
320 rate_idx -= IWL_FIRST_OFDM_RATE;
321
322 fail = tx_resp->failure_frame;
74221d07
AM		 323
324 info->status.rates[0].idx = rate_idx;
325 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 326
91c066f2 327 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 328 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
329 IEEE80211_TX_STAT_ACK : 0;
91c066f2 330
e1623446 331 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 332 txq_id, iwl3945_get_tx_fail_reason(status), status,
333 tx_resp->rate, tx_resp->failure_frame);
334
e1623446 335 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 336 iwl3945_tx_queue_reclaim(priv, txq_id, index);
337
338 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 339 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 340}
341
342
343
b481de9c
ZY		 344/*****************************************************************************
345 *
346 * Intel PRO/Wireless 3945ABG/BG Network Connection
347 *
348 * RX handler implementations
349 *
b481de9c
ZY		 350 *****************************************************************************/
351
4a8a4322 352void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 353{
3d24a9f7 354 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
e1623446 355 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 356 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 357 le32_to_cpu(pkt->len));
358
f2c7e521 359 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 360
ab53d8af
MA		 361 iwl3945_led_background(priv);
362
b481de9c
ZY		 363 priv->last_statistics_time = jiffies;
364}
365
17744ff6
TW		 366/******************************************************************************
367 *
368 * Misc. internal state and helper functions
369 *
370 ******************************************************************************/
d08853a3 371#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 372
373/**
374 * iwl3945_report_frame - dump frame to syslog during debug sessions
375 *
376 * You may hack this function to show different aspects of received frames,
377 * including selective frame dumps.
378 * group100 parameter selects whether to show 1 out of 100 good frames.
379 */
d08853a3 380static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 381 struct iwl_rx_packet *pkt,
17744ff6
TW		 382 struct ieee80211_hdr *header, int group100)
383{
384 u32 to_us;
385 u32 print_summary = 0;
386 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
387 u32 hundred = 0;
388 u32 dataframe = 0;
fd7c8a40 389 __le16 fc;
17744ff6
TW		 390 u16 seq_ctl;
391 u16 channel;
392 u16 phy_flags;
393 u16 length;
394 u16 status;
395 u16 bcn_tmr;
396 u32 tsf_low;
397 u64 tsf;
398 u8 rssi;
399 u8 agc;
400 u16 sig_avg;
401 u16 noise_diff;
402 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
403 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
404 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
405 u8 *data = IWL_RX_DATA(pkt);
406
407 /* MAC header */
fd7c8a40 408 fc = header->frame_control;
17744ff6
TW		 409 seq_ctl = le16_to_cpu(header->seq_ctrl);
410
411 /* metadata */
412 channel = le16_to_cpu(rx_hdr->channel);
413 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
414 length = le16_to_cpu(rx_hdr->len);
415
416 /* end-of-frame status and timestamp */
417 status = le32_to_cpu(rx_end->status);
418 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
419 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
420 tsf = le64_to_cpu(rx_end->timestamp);
421
422 /* signal statistics */
423 rssi = rx_stats->rssi;
424 agc = rx_stats->agc;
425 sig_avg = le16_to_cpu(rx_stats->sig_avg);
426 noise_diff = le16_to_cpu(rx_stats->noise_diff);
427
428 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
429
430 /* if data frame is to us and all is good,
431 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 432 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
433 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 434 dataframe = 1;
435 if (!group100)
436 print_summary = 1; /* print each frame */
437 else if (priv->framecnt_to_us < 100) {
438 priv->framecnt_to_us++;
439 print_summary = 0;
440 } else {
441 priv->framecnt_to_us = 0;
442 print_summary = 1;
443 hundred = 1;
444 }
445 } else {
446 /* print summary for all other frames */
447 print_summary = 1;
448 }
449
450 if (print_summary) {
451 char *title;
0ff1cca0 452 int rate;
17744ff6
TW		 453
454 if (hundred)
455 title = "100Frames";
fd7c8a40 456 else if (ieee80211_has_retry(fc))
17744ff6 457 title = "Retry";
fd7c8a40 458 else if (ieee80211_is_assoc_resp(fc))
17744ff6 459 title = "AscRsp";
fd7c8a40 460 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 461 title = "RasRsp";
fd7c8a40 462 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 463 title = "PrbRsp";
464 print_dump = 1; /* dump frame contents */
465 } else if (ieee80211_is_beacon(fc)) {
466 title = "Beacon";
467 print_dump = 1; /* dump frame contents */
468 } else if (ieee80211_is_atim(fc))
469 title = "ATIM";
470 else if (ieee80211_is_auth(fc))
471 title = "Auth";
472 else if (ieee80211_is_deauth(fc))
473 title = "DeAuth";
474 else if (ieee80211_is_disassoc(fc))
475 title = "DisAssoc";
476 else
477 title = "Frame";
478
479 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
480 if (rate == -1)
481 rate = 0;
482 else
483 rate = iwl3945_rates[rate].ieee / 2;
484
485 /* print frame summary.
486 * MAC addresses show just the last byte (for brevity),
487 * but you can hack it to show more, if you'd like to. */
488 if (dataframe)
e1623446 489 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 490 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 491 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 492 length, rssi, channel, rate);
493 else {
494 /* src/dst addresses assume managed mode */
e1623446 495 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 496 "src=0x%02x, rssi=%u, tim=%lu usec, "
497 "phy=0x%02x, chnl=%d\n",
fd7c8a40 498 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 499 header->addr3[5], rssi,
500 tsf_low - priv->scan_start_tsf,
501 phy_flags, channel);
502 }
503 }
504 if (print_dump)
3d816c77 505 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 506}
d08853a3
SO		 507
508static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
509 struct iwl_rx_packet *pkt,
510 struct ieee80211_hdr *header, int group100)
511{
3d816c77 512 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 513 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
514}
515
17744ff6 516#else
4a8a4322 517static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 518 struct iwl_rx_packet *pkt,
17744ff6
TW		 519 struct ieee80211_hdr *header, int group100)
520{
521}
522#endif
523
4bd9b4f3 524/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 525static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 526 struct ieee80211_hdr *header)
527{
528 /* Filter incoming packets to determine if they are targeted toward
529 * this network, discarding packets coming from ourselves */
530 switch (priv->iw_mode) {
05c914fe 531 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 532 /* packets to our IBSS update information */
533 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 534 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 535 /* packets to our IBSS update information */
536 return !compare_ether_addr(header->addr2, priv->bssid);
537 default:
538 return 1;
539 }
540}
17744ff6 541
4a8a4322 542static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 543 struct iwl_rx_mem_buffer *rxb,
12342c47 544 struct ieee80211_rx_status *stats)
b481de9c 545{
3d24a9f7 546 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
4bd9b4f3 547 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 548 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
549 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 550 short len = le16_to_cpu(rx_hdr->len);
551
552 /* We received data from the HW, so stop the watchdog */
3d24a9f7 553 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
e1623446 554 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 555 return;
556 }
557
558 /* We only process data packets if the interface is open */
559 if (unlikely(!priv->is_open)) {
e1623446
TW		 560 IWL_DEBUG_DROP_LIMIT(priv,
561 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 562 return;
563 }
b481de9c
ZY		 564
565 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
566 /* Set the size of the skb to the size of the frame */
567 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
568
9c74d9fb 569 if (!iwl3945_mod_params.sw_crypto)
8ccde88a
SO		 570 iwl_set_decrypted_flag(priv,
571 (struct ieee80211_hdr *)rxb->skb->data,
b481de9c
ZY		 572 le32_to_cpu(rx_end->status), stats);
573
5c8df2d5 574#ifdef CONFIG_IWLWIFI_LEDS
4bd9b4f3 575 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 576 priv->rxtxpackets += len;
577#endif
22fdf3c9
WYG		 578 iwl_update_stats(priv, false, hdr->frame_control, len);
579
f1d58c25
JB		 580 memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats));
581 ieee80211_rx_irqsafe(priv->hw, rxb->skb);
b481de9c
ZY		 582 rxb->skb = NULL;
583}
584
7878a5a4
MA		 585#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
586
4a8a4322 587static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 588 struct iwl_rx_mem_buffer *rxb)
b481de9c 589{
17744ff6
TW		 590 struct ieee80211_hdr *header;
591 struct ieee80211_rx_status rx_status;
3d24a9f7 592 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 593 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
594 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
595 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 596 int snr;
b481de9c
ZY		 597 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
598 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 599 u8 network_packet;
17744ff6 600
17744ff6
TW		 601 rx_status.flag = 0;
602 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 603 rx_status.freq =
c0186078 604 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 605 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
606 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
607
608 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 609 if (rx_status.band == IEEE80211_BAND_5GHZ)
610 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 611
6f0a2c4d
BR		 612 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
613 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
614
615 /* set the preamble flag if appropriate */
616 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
617 rx_status.flag |= RX_FLAG_SHORTPRE;
618
b481de9c 619 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 620 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
621 rx_stats->phy_count);
b481de9c
ZY		 622 return;
623 }
624
625 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
626 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 627 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 628 return;
629 }
630
56decd3c 631
b481de9c
ZY		 632
633 /* Convert 3945's rssi indicator to dBm */
250bdd21 634 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 635
636 /* Set default noise value to -127 */
637 if (priv->last_rx_noise == 0)
638 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
639
640 /* 3945 provides noise info for OFDM frames only.
641 * sig_avg and noise_diff are measured by the 3945's digital signal
642 * processor (DSP), and indicate linear levels of signal level and
643 * distortion/noise within the packet preamble after
644 * automatic gain control (AGC). sig_avg should stay fairly
645 * constant if the radio's AGC is working well.
646 * Since these values are linear (not dB or dBm), linear
647 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
648 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
649 * to obtain noise level in dBm.
17744ff6 650 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 651 if (rx_stats_noise_diff) {
652 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 653 rx_status.noise = rx_status.signal -
17744ff6 654 iwl3945_calc_db_from_ratio(snr);
566bfe5a 655 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 656 rx_status.noise);
b481de9c
ZY		 657
658 /* If noise info not available, calculate signal quality indicator (%)
659 * using just the dBm signal level. */
660 } else {
17744ff6 661 rx_status.noise = priv->last_rx_noise;
566bfe5a 662 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 663 }
664
665
e1623446 666 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 667 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 668 rx_stats_sig_avg, rx_stats_noise_diff);
669
b481de9c
ZY		 670 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
671
bb8c093b 672 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 673
e1623446 674 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
17744ff6
TW		 675 network_packet ? '*' : ' ',
676 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 677 rx_status.signal, rx_status.signal,
678 rx_status.noise, rx_status.rate_idx);
b481de9c 679
d08853a3
SO		 680 /* Set "1" to report good data frames in groups of 100 */
681 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 682 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 683
684 if (network_packet) {
685 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
686 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 687 priv->last_rx_rssi = rx_status.signal;
17744ff6 688 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 689 }
690
12e5e22d 691 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 692}
693
7aaa1d79
SO		 694int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
695 struct iwl_tx_queue *txq,
696 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 697{
698 int count;
7aaa1d79 699 struct iwl_queue *q;
59606ffa 700 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 701
702 q = &txq->q;
59606ffa
SO		 703 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
704 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 705
706 if (reset)
707 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 708
709 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 710
711 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 712 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 713 NUM_TFD_CHUNKS);
714 return -EINVAL;
715 }
716
dbb6654c
WT		 717 tfd->tbs[count].addr = cpu_to_le32(addr);
718 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 719
720 count++;
721
722 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
723 TFD_CTL_PAD_SET(pad));
724
725 return 0;
726}
727
728/**
bb8c093b 729 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 730 *
731 * Does NOT advance any indexes
732 */
7aaa1d79 733void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 734{
59606ffa 735 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 736 int index = txq->q.read_ptr;
737 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 738 struct pci_dev *dev = priv->pci_dev;
739 int i;
740 int counter;
741
b481de9c 742 /* sanity check */
dbb6654c 743 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 744 if (counter > NUM_TFD_CHUNKS) {
15b1687c 745 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 746 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 747 return;
b481de9c
ZY		 748 }
749
fd9377ee
RC		 750 /* Unmap tx_cmd */
751 if (counter)
752 pci_unmap_single(dev,
c2acea8e
JB		 753 pci_unmap_addr(&txq->meta[index], mapping),
754 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 755 PCI_DMA_TODEVICE);
756
b481de9c
ZY		 757 /* unmap chunks if any */
758
759 for (i = 1; i < counter; i++) {
dbb6654c
WT		 760 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
761 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 762 if (txq->txb[txq->q.read_ptr].skb[0]) {
763 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
764 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 765 /* Can be called from interrupt context */
766 dev_kfree_skb_any(skb);
fc4b6853 767 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 768 }
769 }
770 }
7aaa1d79 771 return ;
b481de9c
ZY		 772}
773
b481de9c 774/**
bb8c093b 775 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 776 *
777*/
c2acea8e
JB		 778void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
779 struct iwl_device_cmd *cmd,
780 struct ieee80211_tx_info *info,
781 struct ieee80211_hdr *hdr,
782 int sta_id, int tx_id)
b481de9c 783{
e039fa4a 784 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 785 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 786 u16 rate_mask;
787 int rate;
788 u8 rts_retry_limit;
789 u8 data_retry_limit;
790 __le32 tx_flags;
fd7c8a40 791 __le16 fc = hdr->frame_control;
c2d79b48 792 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 793
bb8c093b 794 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 795 tx_flags = tx->tx_flags;
b481de9c
ZY		 796
797 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 798 * in this running context */
b481de9c
ZY		 799 rate_mask = IWL_RATES_MASK;
800
b481de9c
ZY		 801 if (tx_id >= IWL_CMD_QUEUE_NUM)
802 rts_retry_limit = 3;
803 else
804 rts_retry_limit = 7;
805
fd7c8a40 806 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 807 data_retry_limit = 3;
808 if (data_retry_limit < rts_retry_limit)
809 rts_retry_limit = data_retry_limit;
810 } else
811 data_retry_limit = IWL_DEFAULT_TX_RETRY;
812
813 if (priv->data_retry_limit != -1)
814 data_retry_limit = priv->data_retry_limit;
815
fd7c8a40
HH		 816 if (ieee80211_is_mgmt(fc)) {
817 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
818 case cpu_to_le16(IEEE80211_STYPE_AUTH):
819 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
820 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
821 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 822 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
823 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
824 tx_flags |= TX_CMD_FLG_CTS_MSK;
825 }
826 break;
827 default:
828 break;
829 }
830 }
831
c2d79b48
WT		 832 tx->rts_retry_limit = rts_retry_limit;
833 tx->data_retry_limit = data_retry_limit;
834 tx->rate = rate;
835 tx->tx_flags = tx_flags;
b481de9c
ZY		 836
837 /* OFDM */
c2d79b48 838 tx->supp_rates[0] =
14577f23 839 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 840
841 /* CCK */
c2d79b48 842 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c 843
e1623446 844 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 845 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 846 tx->rate, le32_to_cpu(tx->tx_flags),
847 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 848}
849
4a8a4322 850u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 851{
852 unsigned long flags_spin;
c587de0b 853 struct iwl_station_entry *station;
b481de9c
ZY		 854
855 if (sta_id == IWL_INVALID_STATION)
856 return IWL_INVALID_STATION;
857
858 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 859 station = &priv->stations[sta_id];
b481de9c
ZY		 860
861 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
862 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 863 station->sta.mode = STA_CONTROL_MODIFY_MSK;
864
865 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
866
c587de0b 867 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 868 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 869 sta_id, tx_rate);
870 return sta_id;
871}
872
854682ed 873static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 874{
854682ed 875 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 876 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 877 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 878 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
879 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 880
5d49f498 881 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 882 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
883 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 884 }
b481de9c 885 } else {
5d49f498 886 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 887 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
888 ~APMG_PS_CTRL_MSK_PWR_SRC);
889
5d49f498 890 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 891 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
892 }
b481de9c 893
a8b50a0a 894 return 0;
b481de9c
ZY		 895}
896
4a8a4322 897static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 898{
5d49f498 899 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 900 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 901 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
902 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 903 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
904 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
905 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
906 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
907 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
908 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
909 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
910 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 911
912 /* fake read to flush all prev I/O */
5d49f498 913 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 914
b481de9c
ZY		 915 return 0;
916}
917
4a8a4322 918static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 919{
b481de9c
ZY		 920
921 /* bypass mode */
5d49f498 922 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 923
924 /* RA 0 is active */
5d49f498 925 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 926
927 /* all 6 fifo are active */
5d49f498 928 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 929
5d49f498
AK		 930 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
931 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
932 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
933 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 934
5d49f498 935 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 936 priv->shared_phys);
b481de9c 937
5d49f498 938 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 939 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
940 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
941 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
942 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
943 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
944 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
945 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 946
b481de9c
ZY		 947
948 return 0;
949}
950
951/**
952 * iwl3945_txq_ctx_reset - Reset TX queue context
953 *
954 * Destroys all DMA structures and initialize them again
955 */
4a8a4322 956static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 957{
958 int rc;
959 int txq_id, slots_num;
960
bb8c093b 961 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 962
963 /* Tx CMD queue */
964 rc = iwl3945_tx_reset(priv);
965 if (rc)
966 goto error;
967
968 /* Tx queue(s) */
5905a1aa 969 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 970 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
971 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 972 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
973 txq_id);
b481de9c 974 if (rc) {
15b1687c 975 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 976 goto error;
977 }
978 }
979
980 return rc;
981
982 error:
bb8c093b 983 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 984 return rc;
985}
986
01ec616d 987static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 988{
a8b50a0a 989 int ret;
b481de9c 990
d25aabb0 991 iwl_power_initialize(priv);
b481de9c 992
5d49f498 993 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 994 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
995
996 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
997 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
998 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 999
01ec616d
KA		 1000 /* set "initialization complete" bit to move adapter
1001 * D0U* --> D0A* state */
5d49f498 1002 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d 1003
ddcb5c78 1004 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
01ec616d
KA		 1005 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1006 if (ret < 0) {
e1623446 1007 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
01ec616d 1008 goto out;
b481de9c
ZY		 1009 }
1010
01ec616d
KA		 1011 /* enable DMA */
1012 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1013 APMG_CLK_VAL_BSM_CLK_RQT);
1014
b481de9c 1015 udelay(20);
01ec616d
KA		 1016
1017 /* disable L1-Active */
5d49f498 1018 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1019 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1020
01ec616d
KA		 1021out:
1022 return ret;
1023}
b481de9c 1024
01ec616d
KA		 1025static void iwl3945_nic_config(struct iwl_priv *priv)
1026{
e6148917 1027 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1028 unsigned long flags;
1029 u8 rev_id = 0;
b481de9c 1030
b481de9c
ZY		 1031 spin_lock_irqsave(&priv->lock, flags);
1032
43121432
AK		 1033 /* Determine HW type */
1034 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1035
1036 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1037
b481de9c 1038 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
e1623446 1039 IWL_DEBUG_INFO(priv, "RTP type \n");
b481de9c 1040 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1041 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1042 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1043 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1044 } else {
e1623446 1045 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1046 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1047 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1048 }
1049
e6148917 1050 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1051 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1052 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1053 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1054 } else
e1623446 1055 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1056
e6148917 1057 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1058 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1059 eeprom->board_revision);
5d49f498 1060 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1061 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1062 } else {
e1623446 1063 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1064 eeprom->board_revision);
5d49f498 1065 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1066 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1067 }
1068
e6148917 1069 if (eeprom->almgor_m_version <= 1) {
5d49f498 1070 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1071 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1072 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1073 eeprom->almgor_m_version);
b481de9c 1074 } else {
e1623446 1075 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1076 eeprom->almgor_m_version);
5d49f498 1077 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1078 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1079 }
1080 spin_unlock_irqrestore(&priv->lock, flags);
1081
e6148917 1082 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1083 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1084
e6148917 1085 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1086 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1087}
1088
1089int iwl3945_hw_nic_init(struct iwl_priv *priv)
1090{
01ec616d
KA		 1091 int rc;
1092 unsigned long flags;
1093 struct iwl_rx_queue *rxq = &priv->rxq;
1094
1095 spin_lock_irqsave(&priv->lock, flags);
1096 priv->cfg->ops->lib->apm_ops.init(priv);
1097 spin_unlock_irqrestore(&priv->lock, flags);
1098
854682ed 1099 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1100 if (rc)
854682ed
KA		 1101 return rc;
1102
01ec616d 1103 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1104
1105 /* Allocate the RX queue, or reset if it is already allocated */
1106 if (!rxq->bd) {
51af3d3f 1107 rc = iwl_rx_queue_alloc(priv);
b481de9c 1108 if (rc) {
15b1687c 1109 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1110 return -ENOMEM;
1111 }
1112 } else
df833b1d 1113 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1114
bb8c093b 1115 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1116
1117 iwl3945_rx_init(priv, rxq);
1118
b481de9c
ZY		 1119
1120 /* Look at using this instead:
1121 rxq->need_update = 1;
141c43a3 1122 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1123 */
1124
5d49f498 1125 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1126
1127 rc = iwl3945_txq_ctx_reset(priv);
1128 if (rc)
1129 return rc;
1130
1131 set_bit(STATUS_INIT, &priv->status);
1132
1133 return 0;
1134}
1135
1136/**
bb8c093b 1137 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1138 *
1139 * Destroy all TX DMA queues and structures
1140 */
4a8a4322 1141void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1142{
1143 int txq_id;
1144
1145 /* Tx queues */
5905a1aa 1146 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
3e5d238f
AK		 1147 if (txq_id == IWL_CMD_QUEUE_NUM)
1148 iwl_cmd_queue_free(priv);
1149 else
1150 iwl_tx_queue_free(priv, txq_id);
1151
b481de9c
ZY		 1152}
1153
4a8a4322 1154void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1155{
bddadf86 1156 int txq_id;
b481de9c
ZY		 1157
1158 /* stop SCD */
5d49f498 1159 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1160
1161 /* reset TFD queues */
5905a1aa 1162 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1163 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1164 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1165 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1166 1000);
1167 }
1168
bb8c093b 1169 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1170}
1171
01ec616d 1172static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1173{
01ec616d 1174 int ret = 0;
b481de9c
ZY		 1175 unsigned long flags;
1176
1177 spin_lock_irqsave(&priv->lock, flags);
1178
1179 /* set stop master bit */
5d49f498 1180 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1181
01ec616d
KA		 1182 iwl_poll_direct_bit(priv, CSR_RESET,
1183 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1184
01ec616d
KA		 1185 if (ret < 0)
1186 goto out;
b481de9c 1187
01ec616d 1188out:
b481de9c 1189 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 1190 IWL_DEBUG_INFO(priv, "stop master\n");
b481de9c 1191
01ec616d
KA		 1192 return ret;
1193}
1194
1195static void iwl3945_apm_stop(struct iwl_priv *priv)
1196{
1197 unsigned long flags;
1198
1199 iwl3945_apm_stop_master(priv);
1200
1201 spin_lock_irqsave(&priv->lock, flags);
1202
1203 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1204
1205 udelay(10);
1206 /* clear "init complete" move adapter D0A* --> D0U state */
1207 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1208 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1209}
1210
e52119c5 1211static int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c 1212{
01ec616d 1213 iwl3945_apm_stop_master(priv);
b481de9c 1214
b481de9c 1215
5d49f498 1216 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
e9414b6b
AM		 1217 udelay(10);
1218
1219 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 1220
5d49f498 1221 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1222 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1223
a8b50a0a
MA		 1224 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1225 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 1226
a8b50a0a
MA		 1227 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1228 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1229 0xFFFFFFFF);
1230
a8b50a0a
MA		 1231 /* enable DMA */
1232 iwl_write_prph(priv, APMG_CLK_EN_REG,
1233 APMG_CLK_VAL_DMA_CLK_RQT |
1234 APMG_CLK_VAL_BSM_CLK_RQT);
1235 udelay(10);
b481de9c 1236
a8b50a0a 1237 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1238 APMG_PS_CTRL_VAL_RESET_REQ);
a8b50a0a
MA		 1239 udelay(5);
1240 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1241 APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c
ZY		 1242
1243 /* Clear the 'host command active' bit... */
1244 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1245
1246 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1247
a8b50a0a 1248 return 0;
b481de9c
ZY		 1249}
1250
1251/**
bb8c093b 1252 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1253 * return index delta into power gain settings table
1254*/
bb8c093b 1255static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1256{
1257 return (new_reading - old_reading) * (-11) / 100;
1258}
1259
1260/**
bb8c093b 1261 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1262 */
bb8c093b 1263static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1264{
3ac7f146 1265 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1266}
1267
4a8a4322 1268int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1269{
5d49f498 1270 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1271}
1272
1273/**
bb8c093b 1274 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1275 * get the current temperature by reading from NIC
1276*/
4a8a4322 1277static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1278{
e6148917 1279 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1280 int temperature;
1281
bb8c093b 1282 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1283
1284 /* driver's okay range is -260 to +25.
1285 * human readable okay range is 0 to +285 */
e1623446 1286 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1287
1288 /* handle insane temp reading */
bb8c093b 1289 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1290 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1291
1292 /* if really really hot(?),
1293 * substitute the 3rd band/group's temp measured at factory */
1294 if (priv->last_temperature > 100)
e6148917 1295 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1296 else /* else use most recent "sane" value from driver */
1297 temperature = priv->last_temperature;
1298 }
1299
1300 return temperature; /* raw, not "human readable" */
1301}
1302
1303/* Adjust Txpower only if temperature variance is greater than threshold.
1304 *
1305 * Both are lower than older versions' 9 degrees */
1306#define IWL_TEMPERATURE_LIMIT_TIMER 6
1307
1308/**
1309 * is_temp_calib_needed - determines if new calibration is needed
1310 *
1311 * records new temperature in tx_mgr->temperature.
1312 * replaces tx_mgr->last_temperature *only* if calib needed
1313 * (assumes caller will actually do the calibration!). */
4a8a4322 1314static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1315{
1316 int temp_diff;
1317
bb8c093b 1318 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1319 temp_diff = priv->temperature - priv->last_temperature;
1320
1321 /* get absolute value */
1322 if (temp_diff < 0) {
e1623446 1323 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1324 temp_diff = -temp_diff;
1325 } else if (temp_diff == 0)
e1623446 1326 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1327 else
e1623446 1328 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1329
1330 /* if we don't need calibration, *don't* update last_temperature */
1331 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1332 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1333 return 0;
1334 }
1335
e1623446 1336 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1337
1338 /* assume that caller will actually do calib ...
1339 * update the "last temperature" value */
1340 priv->last_temperature = priv->temperature;
1341 return 1;
1342}
1343
1344#define IWL_MAX_GAIN_ENTRIES 78
1345#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1346#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1347
1348/* radio and DSP power table, each step is 1/2 dB.
1349 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1350static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1351 {
1352 {251, 127}, /* 2.4 GHz, highest power */
1353 {251, 127},
1354 {251, 127},
1355 {251, 127},
1356 {251, 125},
1357 {251, 110},
1358 {251, 105},
1359 {251, 98},
1360 {187, 125},
1361 {187, 115},
1362 {187, 108},
1363 {187, 99},
1364 {243, 119},
1365 {243, 111},
1366 {243, 105},
1367 {243, 97},
1368 {243, 92},
1369 {211, 106},
1370 {211, 100},
1371 {179, 120},
1372 {179, 113},
1373 {179, 107},
1374 {147, 125},
1375 {147, 119},
1376 {147, 112},
1377 {147, 106},
1378 {147, 101},
1379 {147, 97},
1380 {147, 91},
1381 {115, 107},
1382 {235, 121},
1383 {235, 115},
1384 {235, 109},
1385 {203, 127},
1386 {203, 121},
1387 {203, 115},
1388 {203, 108},
1389 {203, 102},
1390 {203, 96},
1391 {203, 92},
1392 {171, 110},
1393 {171, 104},
1394 {171, 98},
1395 {139, 116},
1396 {227, 125},
1397 {227, 119},
1398 {227, 113},
1399 {227, 107},
1400 {227, 101},
1401 {227, 96},
1402 {195, 113},
1403 {195, 106},
1404 {195, 102},
1405 {195, 95},
1406 {163, 113},
1407 {163, 106},
1408 {163, 102},
1409 {163, 95},
1410 {131, 113},
1411 {131, 106},
1412 {131, 102},
1413 {131, 95},
1414 {99, 113},
1415 {99, 106},
1416 {99, 102},
1417 {99, 95},
1418 {67, 113},
1419 {67, 106},
1420 {67, 102},
1421 {67, 95},
1422 {35, 113},
1423 {35, 106},
1424 {35, 102},
1425 {35, 95},
1426 {3, 113},
1427 {3, 106},
1428 {3, 102},
1429 {3, 95} }, /* 2.4 GHz, lowest power */
1430 {
1431 {251, 127}, /* 5.x GHz, highest power */
1432 {251, 120},
1433 {251, 114},
1434 {219, 119},
1435 {219, 101},
1436 {187, 113},
1437 {187, 102},
1438 {155, 114},
1439 {155, 103},
1440 {123, 117},
1441 {123, 107},
1442 {123, 99},
1443 {123, 92},
1444 {91, 108},
1445 {59, 125},
1446 {59, 118},
1447 {59, 109},
1448 {59, 102},
1449 {59, 96},
1450 {59, 90},
1451 {27, 104},
1452 {27, 98},
1453 {27, 92},
1454 {115, 118},
1455 {115, 111},
1456 {115, 104},
1457 {83, 126},
1458 {83, 121},
1459 {83, 113},
1460 {83, 105},
1461 {83, 99},
1462 {51, 118},
1463 {51, 111},
1464 {51, 104},
1465 {51, 98},
1466 {19, 116},
1467 {19, 109},
1468 {19, 102},
1469 {19, 98},
1470 {19, 93},
1471 {171, 113},
1472 {171, 107},
1473 {171, 99},
1474 {139, 120},
1475 {139, 113},
1476 {139, 107},
1477 {139, 99},
1478 {107, 120},
1479 {107, 113},
1480 {107, 107},
1481 {107, 99},
1482 {75, 120},
1483 {75, 113},
1484 {75, 107},
1485 {75, 99},
1486 {43, 120},
1487 {43, 113},
1488 {43, 107},
1489 {43, 99},
1490 {11, 120},
1491 {11, 113},
1492 {11, 107},
1493 {11, 99},
1494 {131, 107},
1495 {131, 99},
1496 {99, 120},
1497 {99, 113},
1498 {99, 107},
1499 {99, 99},
1500 {67, 120},
1501 {67, 113},
1502 {67, 107},
1503 {67, 99},
1504 {35, 120},
1505 {35, 113},
1506 {35, 107},
1507 {35, 99},
1508 {3, 120} } /* 5.x GHz, lowest power */
1509};
1510
bb8c093b 1511static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1512{
1513 if (index < 0)
1514 return 0;
1515 if (index >= IWL_MAX_GAIN_ENTRIES)
1516 return IWL_MAX_GAIN_ENTRIES - 1;
1517 return (u8) index;
1518}
1519
1520/* Kick off thermal recalibration check every 60 seconds */
1521#define REG_RECALIB_PERIOD (60)
1522
1523/**
bb8c093b 1524 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1525 *
1526 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1527 * or 6 Mbit (OFDM) rates.
1528 */
4a8a4322 1529static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1530 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1531 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1532 int band_index)
1533{
bb8c093b 1534 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1535 s8 power;
1536 u8 power_index;
1537
1538 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1539
1540 /* use this channel group's 6Mbit clipping/saturation pwr,
1541 * but cap at regulatory scan power restriction (set during init
1542 * based on eeprom channel data) for this channel. */
14577f23 1543 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1544
1545 /* further limit to user's max power preference.
1546 * FIXME: Other spectrum management power limitations do not
1547 * seem to apply?? */
62ea9c5b 1548 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1549 scan_power_info->requested_power = power;
1550
1551 /* find difference between new scan *power* and current "normal"
1552 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1553 * current "normal" temperature-compensated Tx power *index* for
1554 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1555 * *index*. */
1556 power_index = ch_info->power_info[rate_index].power_table_index
1557 - (power - ch_info->power_info
14577f23 1558 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1559
1560 /* store reference index that we use when adjusting *all* scan
1561 * powers. So we can accommodate user (all channel) or spectrum
1562 * management (single channel) power changes "between" temperature
1563 * feedback compensation procedures.
1564 * don't force fit this reference index into gain table; it may be a
1565 * negative number. This will help avoid errors when we're at
1566 * the lower bounds (highest gains, for warmest temperatures)
1567 * of the table. */
1568
1569 /* don't exceed table bounds for "real" setting */
bb8c093b 1570 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1571
1572 scan_power_info->power_table_index = power_index;
1573 scan_power_info->tpc.tx_gain =
1574 power_gain_table[band_index][power_index].tx_gain;
1575 scan_power_info->tpc.dsp_atten =
1576 power_gain_table[band_index][power_index].dsp_atten;
1577}
1578
1579/**
75bcfae9 1580 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1581 *
1582 * Configures power settings for all rates for the current channel,
1583 * using values from channel info struct, and send to NIC
1584 */
dfb39e82 1585static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1586{
14577f23 1587 int rate_idx, i;
d20b3c65 1588 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1589 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1590 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1591 };
1592
8318d78a 1593 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1594 ch_info = iwl_get_channel_info(priv,
8318d78a 1595 priv->band,
8ccde88a 1596 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1597 if (!ch_info) {
15b1687c
WT		 1598 IWL_ERR(priv,
1599 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1600 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1601 return -EINVAL;
1602 }
1603
1604 if (!is_channel_valid(ch_info)) {
e1623446 1605 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1606 "non-Tx channel.\n");
1607 return 0;
1608 }
1609
1610 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1611 /* Fill OFDM rate */
1612 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1613 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1614
1615 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1616 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1617
e1623446 1618 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1619 le16_to_cpu(txpower.channel),
1620 txpower.band,
14577f23
MA		 1621 txpower.power[i].tpc.tx_gain,
1622 txpower.power[i].tpc.dsp_atten,
1623 txpower.power[i].rate);
1624 }
1625 /* Fill CCK rates */
1626 for (rate_idx = IWL_FIRST_CCK_RATE;
1627 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1628 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1629 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1630
e1623446 1631 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1632 le16_to_cpu(txpower.channel),
1633 txpower.band,
1634 txpower.power[i].tpc.tx_gain,
1635 txpower.power[i].tpc.dsp_atten,
1636 txpower.power[i].rate);
b481de9c
ZY		 1637 }
1638
518099a8
SO		 1639 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1640 sizeof(struct iwl3945_txpowertable_cmd),
1641 &txpower);
b481de9c
ZY		 1642
1643}
1644
1645/**
bb8c093b 1646 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1647 * @ch_info: Channel to update. Uses power_info.requested_power.
1648 *
1649 * Replace requested_power and base_power_index ch_info fields for
1650 * one channel.
1651 *
1652 * Called if user or spectrum management changes power preferences.
1653 * Takes into account h/w and modulation limitations (clip power).
1654 *
1655 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1656 *
1657 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1658 * properly fill out the scan powers, and actual h/w gain settings,
1659 * and send changes to NIC
1660 */
4a8a4322 1661static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1662 struct iwl_channel_info *ch_info)
b481de9c 1663{
bb8c093b 1664 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1665 int power_changed = 0;
1666 int i;
1667 const s8 *clip_pwrs;
1668 int power;
1669
1670 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1671 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1672
1673 /* Get this channel's rate-to-current-power settings table */
1674 power_info = ch_info->power_info;
1675
1676 /* update OFDM Txpower settings */
14577f23 1677 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1678 i++, ++power_info) {
1679 int delta_idx;
1680
1681 /* limit new power to be no more than h/w capability */
1682 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1683 if (power == power_info->requested_power)
1684 continue;
1685
1686 /* find difference between old and new requested powers,
1687 * update base (non-temp-compensated) power index */
1688 delta_idx = (power - power_info->requested_power) * 2;
1689 power_info->base_power_index -= delta_idx;
1690
1691 /* save new requested power value */
1692 power_info->requested_power = power;
1693
1694 power_changed = 1;
1695 }
1696
1697 /* update CCK Txpower settings, based on OFDM 12M setting ...
1698 * ... all CCK power settings for a given channel are the *same*. */
1699 if (power_changed) {
1700 power =
14577f23 1701 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1702 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1703
bb8c093b 1704 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1705 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1706 power_info->requested_power = power;
1707 power_info->base_power_index =
14577f23 1708 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1709 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1710 ++power_info;
1711 }
1712 }
1713
1714 return 0;
1715}
1716
1717/**
bb8c093b 1718 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1719 *
1720 * NOTE: Returned power limit may be less (but not more) than requested,
1721 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1722 * (no consideration for h/w clipping limitations).
1723 */
d20b3c65 1724static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1725{
1726 s8 max_power;
1727
1728#if 0
1729 /* if we're using TGd limits, use lower of TGd or EEPROM */
1730 if (ch_info->tgd_data.max_power != 0)
1731 max_power = min(ch_info->tgd_data.max_power,
1732 ch_info->eeprom.max_power_avg);
1733
1734 /* else just use EEPROM limits */
1735 else
1736#endif
1737 max_power = ch_info->eeprom.max_power_avg;
1738
1739 return min(max_power, ch_info->max_power_avg);
1740}
1741
1742/**
bb8c093b 1743 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1744 *
1745 * Compensate txpower settings of *all* channels for temperature.
1746 * This only accounts for the difference between current temperature
1747 * and the factory calibration temperatures, and bases the new settings
1748 * on the channel's base_power_index.
1749 *
1750 * If RxOn is "associated", this sends the new Txpower to NIC!
1751 */
4a8a4322 1752static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1753{
d20b3c65 1754 struct iwl_channel_info *ch_info = NULL;
e6148917 1755 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1756 int delta_index;
1757 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1758 u8 a_band;
1759 u8 rate_index;
1760 u8 scan_tbl_index;
1761 u8 i;
1762 int ref_temp;
1763 int temperature = priv->temperature;
1764
1765 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1766 for (i = 0; i < priv->channel_count; i++) {
1767 ch_info = &priv->channel_info[i];
1768 a_band = is_channel_a_band(ch_info);
1769
1770 /* Get this chnlgrp's factory calibration temperature */
e6148917 1771 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1772 temperature;
1773
a96a27f9 1774 /* get power index adjustment based on current and factory
b481de9c 1775 * temps */
bb8c093b 1776 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1777 ref_temp);
1778
1779 /* set tx power value for all rates, OFDM and CCK */
1780 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1781 rate_index++) {
1782 int power_idx =
1783 ch_info->power_info[rate_index].base_power_index;
1784
1785 /* temperature compensate */
1786 power_idx += delta_index;
1787
1788 /* stay within table range */
bb8c093b 1789 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1790 ch_info->power_info[rate_index].
1791 power_table_index = (u8) power_idx;
1792 ch_info->power_info[rate_index].tpc =
1793 power_gain_table[a_band][power_idx];
1794 }
1795
1796 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1797 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1798
1799 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1800 for (scan_tbl_index = 0;
1801 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1802 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1803 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1804 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1805 actual_index, clip_pwrs,
1806 ch_info, a_band);
1807 }
1808 }
1809
1810 /* send Txpower command for current channel to ucode */
75bcfae9 1811 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1812}
1813
4a8a4322 1814int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1815{
d20b3c65 1816 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1817 s8 max_power;
1818 u8 a_band;
1819 u8 i;
1820
62ea9c5b 1821 if (priv->tx_power_user_lmt == power) {
e1623446 1822 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1823 "limit: %ddBm.\n", power);
1824 return 0;
1825 }
1826
e1623446 1827 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1828 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1829
1830 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1831
1832 for (i = 0; i < priv->channel_count; i++) {
1833 ch_info = &priv->channel_info[i];
1834 a_band = is_channel_a_band(ch_info);
1835
1836 /* find minimum power of all user and regulatory constraints
1837 * (does not consider h/w clipping limitations) */
bb8c093b 1838 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1839 max_power = min(power, max_power);
1840 if (max_power != ch_info->curr_txpow) {
1841 ch_info->curr_txpow = max_power;
1842
1843 /* this considers the h/w clipping limitations */
bb8c093b 1844 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1845 }
1846 }
1847
1848 /* update txpower settings for all channels,
1849 * send to NIC if associated. */
1850 is_temp_calib_needed(priv);
bb8c093b 1851 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1852
1853 return 0;
1854}
1855
5bbe233b
AK		 1856static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1857{
1858 int rc = 0;
1859 struct iwl_rx_packet *res = NULL;
1860 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1861 struct iwl_host_cmd cmd = {
1862 .id = REPLY_RXON_ASSOC,
1863 .len = sizeof(rxon_assoc),
c2acea8e 1864 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1865 .data = &rxon_assoc,
1866 };
1867 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1868 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1869
1870 if ((rxon1->flags == rxon2->flags) &&
1871 (rxon1->filter_flags == rxon2->filter_flags) &&
1872 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1873 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1874 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1875 return 0;
1876 }
1877
1878 rxon_assoc.flags = priv->staging_rxon.flags;
1879 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1880 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1881 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1882 rxon_assoc.reserved = 0;
1883
1884 rc = iwl_send_cmd_sync(priv, &cmd);
1885 if (rc)
1886 return rc;
1887
c2acea8e 1888 res = (struct iwl_rx_packet *)cmd.reply_skb->data;
5bbe233b
AK		 1889 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1890 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1891 rc = -EIO;
1892 }
1893
1894 priv->alloc_rxb_skb--;
c2acea8e 1895 dev_kfree_skb_any(cmd.reply_skb);
5bbe233b
AK		 1896
1897 return rc;
1898}
1899
e0158e61
AK		 1900/**
1901 * iwl3945_commit_rxon - commit staging_rxon to hardware
1902 *
1903 * The RXON command in staging_rxon is committed to the hardware and
1904 * the active_rxon structure is updated with the new data. This
1905 * function correctly transitions out of the RXON_ASSOC_MSK state if
1906 * a HW tune is required based on the RXON structure changes.
1907 */
1908static int iwl3945_commit_rxon(struct iwl_priv *priv)
1909{
1910 /* cast away the const for active_rxon in this function */
1911 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1912 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1913 int rc = 0;
1914 bool new_assoc =
1915 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1916
1917 if (!iwl_is_alive(priv))
1918 return -1;
1919
1920 /* always get timestamp with Rx frame */
1921 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1922
1923 /* select antenna */
1924 staging_rxon->flags &=
1925 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1926 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1927
1928 rc = iwl_check_rxon_cmd(priv);
1929 if (rc) {
1930 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1931 return -EINVAL;
1932 }
1933
1934 /* If we don't need to send a full RXON, we can use
1935 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1936 * and other flags for the current radio configuration. */
1937 if (!iwl_full_rxon_required(priv)) {
1938 rc = iwl_send_rxon_assoc(priv);
1939 if (rc) {
1940 IWL_ERR(priv, "Error setting RXON_ASSOC "
1941 "configuration (%d).\n", rc);
1942 return rc;
1943 }
1944
1945 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1946
1947 return 0;
1948 }
1949
1950 /* If we are currently associated and the new config requires
1951 * an RXON_ASSOC and the new config wants the associated mask enabled,
1952 * we must clear the associated from the active configuration
1953 * before we apply the new config */
1954 if (iwl_is_associated(priv) && new_assoc) {
1955 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1956 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1957
1958 /*
1959 * reserved4 and 5 could have been filled by the iwlcore code.
1960 * Let's clear them before pushing to the 3945.
1961 */
1962 active_rxon->reserved4 = 0;
1963 active_rxon->reserved5 = 0;
1964 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1965 sizeof(struct iwl3945_rxon_cmd),
1966 &priv->active_rxon);
1967
1968 /* If the mask clearing failed then we set
1969 * active_rxon back to what it was previously */
1970 if (rc) {
1971 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1972 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1973 "configuration (%d).\n", rc);
1974 return rc;
1975 }
1976 }
1977
1978 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1979 "* with%s RXON_FILTER_ASSOC_MSK\n"
1980 "* channel = %d\n"
1981 "* bssid = %pM\n",
1982 (new_assoc ? "" : "out"),
1983 le16_to_cpu(staging_rxon->channel),
1984 staging_rxon->bssid_addr);
1985
1986 /*
1987 * reserved4 and 5 could have been filled by the iwlcore code.
1988 * Let's clear them before pushing to the 3945.
1989 */
1990 staging_rxon->reserved4 = 0;
1991 staging_rxon->reserved5 = 0;
1992
90e8e424 1993 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1994
1995 /* Apply the new configuration */
1996 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1997 sizeof(struct iwl3945_rxon_cmd),
1998 staging_rxon);
1999 if (rc) {
2000 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
2001 return rc;
2002 }
2003
2004 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
2005
c587de0b 2006 iwl_clear_stations_table(priv);
e0158e61
AK		 2007
2008 /* If we issue a new RXON command which required a tune then we must
2009 * send a new TXPOWER command or we won't be able to Tx any frames */
2010 rc = priv->cfg->ops->lib->send_tx_power(priv);
2011 if (rc) {
2012 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
2013 return rc;
2014 }
2015
2016 /* Add the broadcast address so we can send broadcast frames */
c587de0b 2017 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
e0158e61
AK		 2018 IWL_INVALID_STATION) {
2019 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
2020 return -EIO;
2021 }
2022
2023 /* If we have set the ASSOC_MSK and we are in BSS mode then
2024 * add the IWL_AP_ID to the station rate table */
2025 if (iwl_is_associated(priv) &&
2026 (priv->iw_mode == NL80211_IFTYPE_STATION))
c587de0b
TW		 2027 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
2028 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
e0158e61
AK		 2029 IWL_ERR(priv, "Error adding AP address for transmit\n");
2030 return -EIO;
2031 }
2032
2033 /* Init the hardware's rate fallback order based on the band */
2034 rc = iwl3945_init_hw_rate_table(priv);
2035 if (rc) {
2036 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
2037 return -EIO;
2038 }
2039
2040 return 0;
2041}
2042
b481de9c 2043/* will add 3945 channel switch cmd handling later */
4a8a4322 2044int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2045{
2046 return 0;
2047}
2048
2049/**
2050 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
2051 *
2052 * -- reset periodic timer
2053 * -- see if temp has changed enough to warrant re-calibration ... if so:
2054 * -- correct coeffs for temp (can reset temp timer)
2055 * -- save this temp as "last",
2056 * -- send new set of gain settings to NIC
2057 * NOTE: This should continue working, even when we're not associated,
2058 * so we can keep our internal table of scan powers current. */
4a8a4322 2059void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 2060{
2061 /* This will kick in the "brute force"
bb8c093b 2062 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2063 if (!is_temp_calib_needed(priv))
2064 goto reschedule;
2065
2066 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2067 * This is based *only* on current temperature,
2068 * ignoring any previous power measurements */
bb8c093b 2069 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2070
2071 reschedule:
2072 queue_delayed_work(priv->workqueue,
2073 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2074}
2075
416e1438 2076static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2077{
4a8a4322 2078 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2079 thermal_periodic.work);
2080
2081 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2082 return;
2083
2084 mutex_lock(&priv->mutex);
2085 iwl3945_reg_txpower_periodic(priv);
2086 mutex_unlock(&priv->mutex);
2087}
2088
2089/**
bb8c093b 2090 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2091 * for the channel.
2092 *
2093 * This function is used when initializing channel-info structs.
2094 *
2095 * NOTE: These channel groups do *NOT* match the bands above!
2096 * These channel groups are based on factory-tested channels;
2097 * on A-band, EEPROM's "group frequency" entries represent the top
2098 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2099 */
4a8a4322 2100static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2101 const struct iwl_channel_info *ch_info)
b481de9c 2102{
e6148917
SO		 2103 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2104 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2105 u8 group;
2106 u16 group_index = 0; /* based on factory calib frequencies */
2107 u8 grp_channel;
2108
2109 /* Find the group index for the channel ... don't use index 1(?) */
2110 if (is_channel_a_band(ch_info)) {
2111 for (group = 1; group < 5; group++) {
2112 grp_channel = ch_grp[group].group_channel;
2113 if (ch_info->channel <= grp_channel) {
2114 group_index = group;
2115 break;
2116 }
2117 }
2118 /* group 4 has a few channels *above* its factory cal freq */
2119 if (group == 5)
2120 group_index = 4;
2121 } else
2122 group_index = 0; /* 2.4 GHz, group 0 */
2123
e1623446 2124 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2125 group_index);
2126 return group_index;
2127}
2128
2129/**
bb8c093b 2130 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2131 *
2132 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2133 * into radio/DSP gain settings table for requested power.
2134 */
4a8a4322 2135static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2136 s8 requested_power,
2137 s32 setting_index, s32 *new_index)
2138{
bb8c093b 2139 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2140 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2141 s32 index0, index1;
2142 s32 power = 2 * requested_power;
2143 s32 i;
bb8c093b 2144 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2145 s32 gains0, gains1;
2146 s32 res;
2147 s32 denominator;
2148
e6148917 2149 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2150 samples = chnl_grp->samples;
2151 for (i = 0; i < 5; i++) {
2152 if (power == samples[i].power) {
2153 *new_index = samples[i].gain_index;
2154 return 0;
2155 }
2156 }
2157
2158 if (power > samples[1].power) {
2159 index0 = 0;
2160 index1 = 1;
2161 } else if (power > samples[2].power) {
2162 index0 = 1;
2163 index1 = 2;
2164 } else if (power > samples[3].power) {
2165 index0 = 2;
2166 index1 = 3;
2167 } else {
2168 index0 = 3;
2169 index1 = 4;
2170 }
2171
2172 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2173 if (denominator == 0)
2174 return -EINVAL;
2175 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2176 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2177 res = gains0 + (gains1 - gains0) *
2178 ((s32) power - (s32) samples[index0].power) / denominator +
2179 (1 << 18);
2180 *new_index = res >> 19;
2181 return 0;
2182}
2183
4a8a4322 2184static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2185{
2186 u32 i;
2187 s32 rate_index;
e6148917 2188 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2189 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2190
e1623446 2191 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2192
2193 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2194 s8 *clip_pwrs; /* table of power levels for each rate */
2195 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2196 group = &eeprom->groups[i];
b481de9c
ZY		 2197
2198 /* sanity check on factory saturation power value */
2199 if (group->saturation_power < 40) {
39aadf8c 2200 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2201 "less than minimum expected 40\n",
2202 group->saturation_power);
2203 return;
2204 }
2205
2206 /*
2207 * Derive requested power levels for each rate, based on
2208 * hardware capabilities (saturation power for band).
2209 * Basic value is 3dB down from saturation, with further
2210 * power reductions for highest 3 data rates. These
2211 * backoffs provide headroom for high rate modulation
2212 * power peaks, without too much distortion (clipping).
2213 */
2214 /* we'll fill in this array with h/w max power levels */
f2c7e521 2215 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2216
2217 /* divide factory saturation power by 2 to find -3dB level */
2218 satur_pwr = (s8) (group->saturation_power >> 1);
2219
2220 /* fill in channel group's nominal powers for each rate */
2221 for (rate_index = 0;
2222 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2223 switch (rate_index) {
14577f23 2224 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2225 if (i == 0) /* B/G */
2226 *clip_pwrs = satur_pwr;
2227 else /* A */
2228 *clip_pwrs = satur_pwr - 5;
2229 break;
14577f23 2230 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2231 if (i == 0)
2232 *clip_pwrs = satur_pwr - 7;
2233 else
2234 *clip_pwrs = satur_pwr - 10;
2235 break;
14577f23 2236 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2237 if (i == 0)
2238 *clip_pwrs = satur_pwr - 9;
2239 else
2240 *clip_pwrs = satur_pwr - 12;
2241 break;
2242 default:
2243 *clip_pwrs = satur_pwr;
2244 break;
2245 }
2246 }
2247 }
2248}
2249
2250/**
2251 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2252 *
2253 * Second pass (during init) to set up priv->channel_info
2254 *
2255 * Set up Tx-power settings in our channel info database for each VALID
2256 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2257 * and current temperature.
2258 *
2259 * Since this is based on current temperature (at init time), these values may
2260 * not be valid for very long, but it gives us a starting/default point,
2261 * and allows us to active (i.e. using Tx) scan.
2262 *
2263 * This does *not* write values to NIC, just sets up our internal table.
2264 */
4a8a4322 2265int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2266{
d20b3c65 2267 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2268 struct iwl3945_channel_power_info *pwr_info;
e6148917 2269 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2270 int delta_index;
2271 u8 rate_index;
2272 u8 scan_tbl_index;
2273 const s8 *clip_pwrs; /* array of power levels for each rate */
2274 u8 gain, dsp_atten;
2275 s8 power;
2276 u8 pwr_index, base_pwr_index, a_band;
2277 u8 i;
2278 int temperature;
2279
2280 /* save temperature reference,
2281 * so we can determine next time to calibrate */
bb8c093b 2282 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2283 priv->last_temperature = temperature;
2284
bb8c093b 2285 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2286
2287 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2288 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2289 i++, ch_info++) {
2290 a_band = is_channel_a_band(ch_info);
2291 if (!is_channel_valid(ch_info))
2292 continue;
2293
2294 /* find this channel's channel group (*not* "band") index */
2295 ch_info->group_index =
bb8c093b 2296 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2297
2298 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2299 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2300
2301 /* calculate power index *adjustment* value according to
2302 * diff between current temperature and factory temperature */
bb8c093b 2303 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2304 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2305 temperature);
2306
e1623446 2307 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2308 ch_info->channel, delta_index, temperature +
2309 IWL_TEMP_CONVERT);
2310
2311 /* set tx power value for all OFDM rates */
2312 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2313 rate_index++) {
25a4ccea 2314 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2315 int rc;
2316
2317 /* use channel group's clip-power table,
2318 * but don't exceed channel's max power */
2319 s8 pwr = min(ch_info->max_power_avg,
2320 clip_pwrs[rate_index]);
2321
2322 pwr_info = &ch_info->power_info[rate_index];
2323
2324 /* get base (i.e. at factory-measured temperature)
2325 * power table index for this rate's power */
bb8c093b 2326 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2327 ch_info->group_index,
2328 &power_idx);
2329 if (rc) {
15b1687c 2330 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2331 return rc;
2332 }
2333 pwr_info->base_power_index = (u8) power_idx;
2334
2335 /* temperature compensate */
2336 power_idx += delta_index;
2337
2338 /* stay within range of gain table */
bb8c093b 2339 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2340
bb8c093b 2341 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2342 pwr_info->requested_power = pwr;
2343 pwr_info->power_table_index = (u8) power_idx;
2344 pwr_info->tpc.tx_gain =
2345 power_gain_table[a_band][power_idx].tx_gain;
2346 pwr_info->tpc.dsp_atten =
2347 power_gain_table[a_band][power_idx].dsp_atten;
2348 }
2349
2350 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2351 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2352 power = pwr_info->requested_power +
2353 IWL_CCK_FROM_OFDM_POWER_DIFF;
2354 pwr_index = pwr_info->power_table_index +
2355 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2356 base_pwr_index = pwr_info->base_power_index +
2357 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2358
2359 /* stay within table range */
bb8c093b 2360 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2361 gain = power_gain_table[a_band][pwr_index].tx_gain;
2362 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2363
bb8c093b 2364 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2365 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2366 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2367 for (rate_index = 0;
2368 rate_index < IWL_CCK_RATES; rate_index++) {
2369 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2370 pwr_info->requested_power = power;
2371 pwr_info->power_table_index = pwr_index;
2372 pwr_info->base_power_index = base_pwr_index;
2373 pwr_info->tpc.tx_gain = gain;
2374 pwr_info->tpc.dsp_atten = dsp_atten;
2375 }
2376
2377 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2378 for (scan_tbl_index = 0;
2379 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2380 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2381 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2382 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2383 actual_index, clip_pwrs, ch_info, a_band);
2384 }
2385 }
2386
2387 return 0;
2388}
2389
4a8a4322 2390int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2391{
2392 int rc;
b481de9c 2393
5d49f498
AK		 2394 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2395 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2396 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2397 if (rc < 0)
15b1687c 2398 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2399
b481de9c
ZY		 2400 return 0;
2401}
2402
188cf6c7 2403int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2404{
b481de9c
ZY		 2405 int txq_id = txq->q.id;
2406
3832ec9d 2407 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2408
2409 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2410
5d49f498
AK		 2411 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2412 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2413
5d49f498 2414 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2415 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2416 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2417 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2418 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2419 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2420
2421 /* fake read to flush all prev. writes */
5d49f498 2422 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2423
2424 return 0;
2425}
2426
42427b4e
KA		 2427/*
2428 * HCMD utils
2429 */
2430static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2431{
2432 switch (cmd_id) {
2433 case REPLY_RXON:
d25aabb0
WT		 2434 return sizeof(struct iwl3945_rxon_cmd);
2435 case POWER_TABLE_CMD:
2436 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2437 default:
2438 return len;
2439 }
2440}
2441
c587de0b 2442
17f841cd
SO		 2443static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2444{
c587de0b
TW		 2445 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2446 addsta->mode = cmd->mode;
2447 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2448 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2449 addsta->station_flags = cmd->station_flags;
2450 addsta->station_flags_msk = cmd->station_flags_msk;
2451 addsta->tid_disable_tx = cpu_to_le16(0);
2452 addsta->rate_n_flags = cmd->rate_n_flags;
2453 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2454 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2455 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2456
2457 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2458}
2459
c587de0b 2460
b481de9c
ZY		 2461/**
2462 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2463 */
4a8a4322 2464int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2465{
14577f23 2466 int rc, i, index, prev_index;
bb8c093b 2467 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2468 .reserved = {0, 0, 0},
2469 };
bb8c093b 2470 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2471
bb8c093b
CH		 2472 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2473 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2474
2475 table[index].rate_n_flags =
bb8c093b 2476 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2477 table[index].try_cnt = priv->retry_rate;
bb8c093b 2478 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2479 table[index].next_rate_index =
2480 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2481 }
2482
8318d78a
JB		 2483 switch (priv->band) {
2484 case IEEE80211_BAND_5GHZ:
e1623446 2485 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2486 /* If one of the following CCK rates is used,
2487 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2488 for (i = IWL_RATE_1M_INDEX_TABLE;
2489 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2490 table[i].next_rate_index =
2491 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2492
2493 /* Don't fall back to CCK rates */
7262796a
AM		 2494 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2495 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2496
2497 /* Don't drop out of OFDM rates */
14577f23 2498 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2499 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2500 break;
2501
8318d78a 2502 case IEEE80211_BAND_2GHZ:
e1623446 2503 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2504 /* If an OFDM rate is used, have it fall back to the
2505 * 1M CCK rates */
b481de9c 2506
7262796a 2507 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2508 iwl_is_associated(priv)) {
7262796a
AM		 2509
2510 index = IWL_FIRST_CCK_RATE;
2511 for (i = IWL_RATE_6M_INDEX_TABLE;
2512 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2513 table[i].next_rate_index =
2514 iwl3945_rates[index].table_rs_index;
2515
2516 index = IWL_RATE_11M_INDEX_TABLE;
2517 /* CCK shouldn't fall back to OFDM... */
2518 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2519 }
b481de9c
ZY		 2520 break;
2521
2522 default:
8318d78a 2523 WARN_ON(1);
b481de9c
ZY		 2524 break;
2525 }
2526
2527 /* Update the rate scaling for control frame Tx */
2528 rate_cmd.table_id = 0;
518099a8 2529 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2530 &rate_cmd);
2531 if (rc)
2532 return rc;
2533
2534 /* Update the rate scaling for data frame Tx */
2535 rate_cmd.table_id = 1;
518099a8 2536 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2537 &rate_cmd);
2538}
2539
796083cb 2540/* Called when initializing driver */
4a8a4322 2541int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2542{
3832ec9d
AK		 2543 memset((void *)&priv->hw_params, 0,
2544 sizeof(struct iwl_hw_params));
b481de9c 2545
3832ec9d 2546 priv->shared_virt =
b481de9c 2547 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2548 sizeof(struct iwl3945_shared),
3832ec9d 2549 &priv->shared_phys);
b481de9c 2550
3832ec9d 2551 if (!priv->shared_virt) {
15b1687c 2552 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2553 mutex_unlock(&priv->mutex);
2554 return -ENOMEM;
2555 }
2556
21c02a1a 2557 /* Assign number of Usable TX queues */
5905a1aa 2558 priv->hw_params.max_txq_num = IWL39_NUM_QUEUES;
21c02a1a 2559
a8e74e27 2560 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
1e33dc64 2561 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
3832ec9d
AK		 2562 priv->hw_params.max_pkt_size = 2342;
2563 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2564 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2565 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2566 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2567
141c43a3 2568 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2569 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2570
b481de9c
ZY		 2571 return 0;
2572}
2573
4a8a4322 2574unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2575 struct iwl3945_frame *frame, u8 rate)
b481de9c 2576{
bb8c093b 2577 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2578 unsigned int frame_size;
2579
bb8c093b 2580 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2581 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2582
3832ec9d 2583 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2584 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2585
bb8c093b 2586 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2587 tx_beacon_cmd->frame,
b481de9c
ZY		 2588 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2589
2590 BUG_ON(frame_size > MAX_MPDU_SIZE);
2591 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2592
2593 tx_beacon_cmd->tx.rate = rate;
2594 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2595 TX_CMD_FLG_TSF_MSK);
2596
14577f23
MA		 2597 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2598 tx_beacon_cmd->tx.supp_rates[0] =
2599 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2600
b481de9c 2601 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2602 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2603
3ac7f146 2604 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2605}
2606
4a8a4322 2607void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2608{
91c066f2 2609 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2610 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2611}
2612
4a8a4322 2613void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2614{
2615 INIT_DELAYED_WORK(&priv->thermal_periodic,
2616 iwl3945_bg_reg_txpower_periodic);
2617}
2618
4a8a4322 2619void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2620{
2621 cancel_delayed_work(&priv->thermal_periodic);
2622}
2623
0164b9b4
KA		 2624/* check contents of special bootstrap uCode SRAM */
2625static int iwl3945_verify_bsm(struct iwl_priv *priv)
2626 {
2627 __le32 *image = priv->ucode_boot.v_addr;
2628 u32 len = priv->ucode_boot.len;
2629 u32 reg;
2630 u32 val;
2631
e1623446 2632 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2633
2634 /* verify BSM SRAM contents */
2635 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2636 for (reg = BSM_SRAM_LOWER_BOUND;
2637 reg < BSM_SRAM_LOWER_BOUND + len;
2638 reg += sizeof(u32), image++) {
2639 val = iwl_read_prph(priv, reg);
2640 if (val != le32_to_cpu(*image)) {
2641 IWL_ERR(priv, "BSM uCode verification failed at "
2642 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2643 BSM_SRAM_LOWER_BOUND,
2644 reg - BSM_SRAM_LOWER_BOUND, len,
2645 val, le32_to_cpu(*image));
2646 return -EIO;
2647 }
2648 }
2649
e1623446 2650 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2651
2652 return 0;
2653}
2654
e6148917
SO		 2655
2656/******************************************************************************
2657 *
2658 * EEPROM related functions
2659 *
2660 ******************************************************************************/
2661
2662/*
2663 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2664 * embedded controller) as EEPROM reader; each read is a series of pulses
2665 * to/from the EEPROM chip, not a single event, so even reads could conflict
2666 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2667 * simply claims ownership, which should be safe when this function is called
2668 * (i.e. before loading uCode!).
2669 */
2670static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2671{
2672 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2673 return 0;
2674}
2675
2676
2677static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2678{
2679 return;
2680}
2681
0164b9b4
KA		 2682 /**
2683 * iwl3945_load_bsm - Load bootstrap instructions
2684 *
2685 * BSM operation:
2686 *
2687 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2688 * in special SRAM that does not power down during RFKILL. When powering back
2689 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2690 * the bootstrap program into the on-board processor, and starts it.
2691 *
2692 * The bootstrap program loads (via DMA) instructions and data for a new
2693 * program from host DRAM locations indicated by the host driver in the
2694 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2695 * automatically.
2696 *
2697 * When initializing the NIC, the host driver points the BSM to the
2698 * "initialize" uCode image. This uCode sets up some internal data, then
2699 * notifies host via "initialize alive" that it is complete.
2700 *
2701 * The host then replaces the BSM_DRAM_* pointer values to point to the
2702 * normal runtime uCode instructions and a backup uCode data cache buffer
2703 * (filled initially with starting data values for the on-board processor),
2704 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2705 * which begins normal operation.
2706 *
2707 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2708 * the backup data cache in DRAM before SRAM is powered down.
2709 *
2710 * When powering back up, the BSM loads the bootstrap program. This reloads
2711 * the runtime uCode instructions and the backup data cache into SRAM,
2712 * and re-launches the runtime uCode from where it left off.
2713 */
2714static int iwl3945_load_bsm(struct iwl_priv *priv)
2715{
2716 __le32 *image = priv->ucode_boot.v_addr;
2717 u32 len = priv->ucode_boot.len;
2718 dma_addr_t pinst;
2719 dma_addr_t pdata;
2720 u32 inst_len;
2721 u32 data_len;
2722 int rc;
2723 int i;
2724 u32 done;
2725 u32 reg_offset;
2726
e1623446 2727 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2728
2729 /* make sure bootstrap program is no larger than BSM's SRAM size */
2730 if (len > IWL39_MAX_BSM_SIZE)
2731 return -EINVAL;
2732
2733 /* Tell bootstrap uCode where to find the "Initialize" uCode
2734 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2735 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2736 * after the "initialize" uCode has run, to point to
2737 * runtime/protocol instructions and backup data cache. */
2738 pinst = priv->ucode_init.p_addr;
2739 pdata = priv->ucode_init_data.p_addr;
2740 inst_len = priv->ucode_init.len;
2741 data_len = priv->ucode_init_data.len;
2742
0164b9b4
KA		 2743 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2744 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2745 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2746 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2747
2748 /* Fill BSM memory with bootstrap instructions */
2749 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2750 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2751 reg_offset += sizeof(u32), image++)
2752 _iwl_write_prph(priv, reg_offset,
2753 le32_to_cpu(*image));
2754
2755 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2756 if (rc)
0164b9b4 2757 return rc;
0164b9b4
KA		 2758
2759 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2760 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2761 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2762 IWL39_RTC_INST_LOWER_BOUND);
2763 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2764
2765 /* Load bootstrap code into instruction SRAM now,
2766 * to prepare to load "initialize" uCode */
2767 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2768 BSM_WR_CTRL_REG_BIT_START);
2769
2770 /* Wait for load of bootstrap uCode to finish */
2771 for (i = 0; i < 100; i++) {
2772 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2773 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2774 break;
2775 udelay(10);
2776 }
2777 if (i < 100)
e1623446 2778 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2779 else {
2780 IWL_ERR(priv, "BSM write did not complete!\n");
2781 return -EIO;
2782 }
2783
2784 /* Enable future boot loads whenever power management unit triggers it
2785 * (e.g. when powering back up after power-save shutdown) */
2786 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2787 BSM_WR_CTRL_REG_BIT_START_EN);
2788
0164b9b4
KA		 2789 return 0;
2790}
2791
cc0f555d
JS		 2792#define IWL3945_UCODE_GET(item) \
2793static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2794 u32 api_ver) \
2795{ \
2796 return le32_to_cpu(ucode->u.v1.item); \
2797}
2798
2799static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2800{
2801 return UCODE_HEADER_SIZE(1);
2802}
2803static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2804 u32 api_ver)
2805{
2806 return 0;
2807}
2808static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2809 u32 api_ver)
2810{
2811 return (u8 *) ucode->u.v1.data;
2812}
2813
2814IWL3945_UCODE_GET(inst_size);
2815IWL3945_UCODE_GET(data_size);
2816IWL3945_UCODE_GET(init_size);
2817IWL3945_UCODE_GET(init_data_size);
2818IWL3945_UCODE_GET(boot_size);
2819
5bbe233b
AK		 2820static struct iwl_hcmd_ops iwl3945_hcmd = {
2821 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2822 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2823};
2824
cc0f555d
JS		 2825static struct iwl_ucode_ops iwl3945_ucode = {
2826 .get_header_size = iwl3945_ucode_get_header_size,
2827 .get_build = iwl3945_ucode_get_build,
2828 .get_inst_size = iwl3945_ucode_get_inst_size,
2829 .get_data_size = iwl3945_ucode_get_data_size,
2830 .get_init_size = iwl3945_ucode_get_init_size,
2831 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2832 .get_boot_size = iwl3945_ucode_get_boot_size,
2833 .get_data = iwl3945_ucode_get_data,
2834};
2835
0164b9b4 2836static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2837 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2838 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2839 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2840 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2841 .apm_ops = {
2842 .init = iwl3945_apm_init,
2843 .reset = iwl3945_apm_reset,
2844 .stop = iwl3945_apm_stop,
2845 .config = iwl3945_nic_config,
854682ed 2846 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2847 },
e6148917
SO		 2848 .eeprom_ops = {
2849 .regulatory_bands = {
2850 EEPROM_REGULATORY_BAND_1_CHANNELS,
2851 EEPROM_REGULATORY_BAND_2_CHANNELS,
2852 EEPROM_REGULATORY_BAND_3_CHANNELS,
2853 EEPROM_REGULATORY_BAND_4_CHANNELS,
2854 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2855 EEPROM_REGULATORY_BAND_NO_HT40,
2856 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2857 },
2858 .verify_signature = iwlcore_eeprom_verify_signature,
2859 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2860 .release_semaphore = iwl3945_eeprom_release_semaphore,
2861 .query_addr = iwlcore_eeprom_query_addr,
2862 },
75bcfae9 2863 .send_tx_power = iwl3945_send_tx_power,
c2436980 2864 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2865 .post_associate = iwl3945_post_associate,
ef850d7c 2866 .isr = iwl_isr_legacy,
60690a6a 2867 .config_ap = iwl3945_config_ap,
0164b9b4
KA		 2868};
2869
42427b4e
KA		 2870static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2871 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2872 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
42427b4e
KA		 2873};
2874
0164b9b4 2875static struct iwl_ops iwl3945_ops = {
cc0f555d 2876 .ucode = &iwl3945_ucode,
0164b9b4 2877 .lib = &iwl3945_lib,
5bbe233b 2878 .hcmd = &iwl3945_hcmd,
42427b4e 2879 .utils = &iwl3945_hcmd_utils,
0164b9b4
KA		 2880};
2881
c0f20d91 2882static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2883 .name = "3945BG",
a0987a8d
RC		 2884 .fw_name_pre = IWL3945_FW_PRE,
2885 .ucode_api_max = IWL3945_UCODE_API_MAX,
2886 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2887 .sku = IWL_SKU_G,
e6148917
SO		 2888 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2889 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2890 .ops = &iwl3945_ops,
ef850d7c 2891 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2892 .use_isr_legacy = true,
2893 .ht_greenfield_support = false,
82b9a121
TW		 2894};
2895
c0f20d91 2896static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2897 .name = "3945ABG",
a0987a8d
RC		 2898 .fw_name_pre = IWL3945_FW_PRE,
2899 .ucode_api_max = IWL3945_UCODE_API_MAX,
2900 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2901 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2902 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2903 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2904 .ops = &iwl3945_ops,
ef850d7c 2905 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2906 .use_isr_legacy = true,
2907 .ht_greenfield_support = false,
82b9a121
TW		 2908};
2909
bb8c093b 2910struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2911 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2912 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2913 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2914 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2915 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2916 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2917 {0}
2918};
2919
bb8c093b 2920MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)