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4bc85c13 | 1 | /****************************************************************************** |
4bc85c13 WYG |
2 | * |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
af038f40 | 5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
4bc85c13 WYG |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
4bc85c13 | 28 | *****************************************************************************/ |
af038f40 SG |
29 | |
30 | #ifndef __il_4965_h__ | |
31 | #define __il_4965_h__ | |
32 | ||
af038f40 SG |
33 | struct il_rx_queue; |
34 | struct il_rx_buf; | |
35 | struct il_rx_pkt; | |
36 | struct il_tx_queue; | |
37 | struct il_rxon_context; | |
38 | ||
39 | /* configuration for the _4965 devices */ | |
40 | extern struct il_cfg il4965_cfg; | |
c39ae9fd | 41 | extern const struct il_ops il4965_ops; |
af038f40 SG |
42 | |
43 | extern struct il_mod_params il4965_mod_params; | |
44 | ||
af038f40 | 45 | /* tx queue */ |
e7392364 SG |
46 | void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, |
47 | int freed); | |
af038f40 SG |
48 | |
49 | /* RXON */ | |
83007196 | 50 | void il4965_set_rxon_chain(struct il_priv *il); |
af038f40 SG |
51 | |
52 | /* uCode */ | |
53 | int il4965_verify_ucode(struct il_priv *il); | |
54 | ||
55 | /* lib */ | |
e7392364 | 56 | void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status); |
af038f40 SG |
57 | |
58 | void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq); | |
59 | int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq); | |
60 | int il4965_hw_nic_init(struct il_priv *il); | |
61 | int il4965_dump_fh(struct il_priv *il, char **buf, bool display); | |
62 | ||
f03ee2a8 SG |
63 | void il4965_nic_config(struct il_priv *il); |
64 | ||
af038f40 SG |
65 | /* rx */ |
66 | void il4965_rx_queue_restock(struct il_priv *il); | |
67 | void il4965_rx_replenish(struct il_priv *il); | |
68 | void il4965_rx_replenish_now(struct il_priv *il); | |
69 | void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq); | |
70 | int il4965_rxq_stop(struct il_priv *il); | |
71 | int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band); | |
af038f40 SG |
72 | void il4965_rx_handle(struct il_priv *il); |
73 | ||
74 | /* tx */ | |
75 | void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq); | |
e7392364 SG |
76 | int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, |
77 | dma_addr_t addr, u16 len, u8 reset, u8 pad); | |
78 | int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq); | |
af038f40 | 79 | void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags, |
e7392364 | 80 | struct ieee80211_tx_info *info); |
af038f40 SG |
81 | int il4965_tx_skb(struct il_priv *il, struct sk_buff *skb); |
82 | int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif, | |
e7392364 | 83 | struct ieee80211_sta *sta, u16 tid, u16 * ssn); |
af038f40 SG |
84 | int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif, |
85 | struct ieee80211_sta *sta, u16 tid); | |
e7392364 | 86 | int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id); |
af038f40 SG |
87 | int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx); |
88 | void il4965_hw_txq_ctx_free(struct il_priv *il); | |
89 | int il4965_txq_ctx_alloc(struct il_priv *il); | |
90 | void il4965_txq_ctx_reset(struct il_priv *il); | |
91 | void il4965_txq_ctx_stop(struct il_priv *il); | |
92 | void il4965_txq_set_sched(struct il_priv *il, u32 mask); | |
93 | ||
4bc85c13 | 94 | /* |
af038f40 | 95 | * Acquire il->lock before calling this function ! |
4bc85c13 | 96 | */ |
af038f40 SG |
97 | void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx); |
98 | /** | |
99 | * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue | |
100 | * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed | |
101 | * @scd_retry: (1) Indicates queue will be used in aggregation mode | |
102 | * | |
103 | * NOTE: Acquire il->lock before calling this function ! | |
104 | */ | |
e7392364 SG |
105 | void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq, |
106 | int tx_fifo_id, int scd_retry); | |
af038f40 | 107 | |
af038f40 SG |
108 | /* scan */ |
109 | int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif); | |
110 | ||
111 | /* station mgmt */ | |
e7392364 SG |
112 | int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, |
113 | bool add); | |
af038f40 SG |
114 | |
115 | /* hcmd */ | |
116 | int il4965_send_beacon_cmd(struct il_priv *il); | |
117 | ||
118 | #ifdef CONFIG_IWLEGACY_DEBUG | |
119 | const char *il4965_get_tx_fail_reason(u32 status); | |
120 | #else | |
121 | static inline const char * | |
e7392364 SG |
122 | il4965_get_tx_fail_reason(u32 status) |
123 | { | |
124 | return ""; | |
125 | } | |
af038f40 SG |
126 | #endif |
127 | ||
128 | /* station management */ | |
83007196 SG |
129 | int il4965_alloc_bcast_station(struct il_priv *il); |
130 | int il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r); | |
af038f40 | 131 | int il4965_remove_default_wep_key(struct il_priv *il, |
e7392364 | 132 | struct ieee80211_key_conf *key); |
83007196 | 133 | int il4965_set_default_wep_key(struct il_priv *il, |
af038f40 | 134 | struct ieee80211_key_conf *key); |
83007196 SG |
135 | int il4965_restore_default_wep_keys(struct il_priv *il); |
136 | int il4965_set_dynamic_key(struct il_priv *il, | |
e7392364 | 137 | struct ieee80211_key_conf *key, u8 sta_id); |
83007196 | 138 | int il4965_remove_dynamic_key(struct il_priv *il, |
e7392364 | 139 | struct ieee80211_key_conf *key, u8 sta_id); |
83007196 | 140 | void il4965_update_tkip_key(struct il_priv *il, |
e7392364 SG |
141 | struct ieee80211_key_conf *keyconf, |
142 | struct ieee80211_sta *sta, u32 iv32, | |
1722f8e1 | 143 | u16 *phase1key); |
e7392364 | 144 | int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid); |
af038f40 | 145 | int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, |
e7392364 | 146 | int tid, u16 ssn); |
af038f40 | 147 | int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, |
e7392364 SG |
148 | int tid); |
149 | void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt); | |
af038f40 SG |
150 | int il4965_update_bcast_stations(struct il_priv *il); |
151 | ||
152 | /* rate */ | |
e7392364 SG |
153 | static inline u8 |
154 | il4965_hw_get_rate(__le32 rate_n_flags) | |
af038f40 SG |
155 | { |
156 | return le32_to_cpu(rate_n_flags) & 0xFF; | |
157 | } | |
4bc85c13 | 158 | |
af038f40 | 159 | /* eeprom */ |
e7392364 | 160 | void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac); |
af038f40 SG |
161 | int il4965_eeprom_acquire_semaphore(struct il_priv *il); |
162 | void il4965_eeprom_release_semaphore(struct il_priv *il); | |
e7392364 | 163 | int il4965_eeprom_check_version(struct il_priv *il); |
af038f40 SG |
164 | |
165 | /* mac80211 handlers (for 4965) */ | |
166 | void il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb); | |
167 | int il4965_mac_start(struct ieee80211_hw *hw); | |
168 | void il4965_mac_stop(struct ieee80211_hw *hw); | |
169 | void il4965_configure_filter(struct ieee80211_hw *hw, | |
170 | unsigned int changed_flags, | |
e7392364 | 171 | unsigned int *total_flags, u64 multicast); |
af038f40 SG |
172 | int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
173 | struct ieee80211_vif *vif, struct ieee80211_sta *sta, | |
174 | struct ieee80211_key_conf *key); | |
175 | void il4965_mac_update_tkip_key(struct ieee80211_hw *hw, | |
176 | struct ieee80211_vif *vif, | |
177 | struct ieee80211_key_conf *keyconf, | |
e7392364 | 178 | struct ieee80211_sta *sta, u32 iv32, |
1722f8e1 | 179 | u16 *phase1key); |
e7392364 | 180 | int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
af038f40 | 181 | enum ieee80211_ampdu_mlme_action action, |
e7392364 | 182 | struct ieee80211_sta *sta, u16 tid, u16 * ssn, |
af038f40 | 183 | u8 buf_size); |
e7392364 | 184 | int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
af038f40 SG |
185 | struct ieee80211_sta *sta); |
186 | void il4965_mac_channel_switch(struct ieee80211_hw *hw, | |
187 | struct ieee80211_channel_switch *ch_switch); | |
188 | ||
189 | void il4965_led_enable(struct il_priv *il); | |
4bc85c13 | 190 | |
4bc85c13 | 191 | /* EEPROM */ |
d3175167 | 192 | #define IL4965_EEPROM_IMG_SIZE 1024 |
4bc85c13 WYG |
193 | |
194 | /* | |
195 | * uCode queue management definitions ... | |
196 | * The first queue used for block-ack aggregation is #7 (4965 only). | |
197 | * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7. | |
198 | */ | |
d3175167 | 199 | #define IL49_FIRST_AMPDU_QUEUE 7 |
4bc85c13 WYG |
200 | |
201 | /* Sizes and addresses for instruction and data memory (SRAM) in | |
202 | * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ | |
d3175167 SG |
203 | #define IL49_RTC_INST_LOWER_BOUND (0x000000) |
204 | #define IL49_RTC_INST_UPPER_BOUND (0x018000) | |
4bc85c13 | 205 | |
d3175167 SG |
206 | #define IL49_RTC_DATA_LOWER_BOUND (0x800000) |
207 | #define IL49_RTC_DATA_UPPER_BOUND (0x80A000) | |
4bc85c13 | 208 | |
d3175167 SG |
209 | #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \ |
210 | IL49_RTC_INST_LOWER_BOUND) | |
211 | #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \ | |
212 | IL49_RTC_DATA_LOWER_BOUND) | |
4bc85c13 | 213 | |
d3175167 SG |
214 | #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE |
215 | #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE | |
4bc85c13 WYG |
216 | |
217 | /* Size of uCode instruction memory in bootstrap state machine */ | |
d3175167 | 218 | #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE |
4bc85c13 | 219 | |
e7392364 SG |
220 | static inline int |
221 | il4965_hw_valid_rtc_data_addr(u32 addr) | |
4bc85c13 | 222 | { |
d3175167 SG |
223 | return (addr >= IL49_RTC_DATA_LOWER_BOUND && |
224 | addr < IL49_RTC_DATA_UPPER_BOUND); | |
4bc85c13 WYG |
225 | } |
226 | ||
227 | /********************* START TEMPERATURE *************************************/ | |
228 | ||
229 | /** | |
230 | * 4965 temperature calculation. | |
231 | * | |
232 | * The driver must calculate the device temperature before calculating | |
233 | * a txpower setting (amplifier gain is temperature dependent). The | |
234 | * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration | |
235 | * values used for the life of the driver, and one of which (R4) is the | |
236 | * real-time temperature indicator. | |
237 | * | |
238 | * uCode provides all 4 values to the driver via the "initialize alive" | |
e2ebc833 | 239 | * notification (see struct il4965_init_alive_resp). After the runtime uCode |
ebf0d90d | 240 | * image loads, uCode updates the R4 value via stats notifications |
4d69c752 SG |
241 | * (see N_STATS), which occur after each received beacon |
242 | * when associated, or can be requested via C_STATS. | |
4bc85c13 WYG |
243 | * |
244 | * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver | |
245 | * must sign-extend to 32 bits before applying formula below. | |
246 | * | |
247 | * Formula: | |
248 | * | |
249 | * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 | |
250 | * | |
251 | * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is | |
252 | * an additional correction, which should be centered around 0 degrees | |
253 | * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for | |
254 | * centering the 97/100 correction around 0 degrees K. | |
255 | * | |
256 | * Add 273 to Kelvin value to find degrees Celsius, for comparing current | |
257 | * temperature with factory-measured temperatures when calculating txpower | |
258 | * settings. | |
259 | */ | |
260 | #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 | |
261 | #define TEMPERATURE_CALIB_A_VAL 259 | |
262 | ||
263 | /* Limit range of calculated temperature to be between these Kelvin values */ | |
e2ebc833 SG |
264 | #define IL_TX_POWER_TEMPERATURE_MIN (263) |
265 | #define IL_TX_POWER_TEMPERATURE_MAX (410) | |
4bc85c13 | 266 | |
e2ebc833 | 267 | #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ |
232913b5 SG |
268 | ((t) < IL_TX_POWER_TEMPERATURE_MIN || \ |
269 | (t) > IL_TX_POWER_TEMPERATURE_MAX) | |
4bc85c13 | 270 | |
527901d0 | 271 | extern void il4965_temperature_calib(struct il_priv *il); |
4bc85c13 WYG |
272 | /********************* END TEMPERATURE ***************************************/ |
273 | ||
274 | /********************* START TXPOWER *****************************************/ | |
275 | ||
276 | /** | |
277 | * 4965 txpower calculations rely on information from three sources: | |
278 | * | |
279 | * 1) EEPROM | |
280 | * 2) "initialize" alive notification | |
ebf0d90d | 281 | * 3) stats notifications |
4bc85c13 WYG |
282 | * |
283 | * EEPROM data consists of: | |
284 | * | |
285 | * 1) Regulatory information (max txpower and channel usage flags) is provided | |
286 | * separately for each channel that can possibly supported by 4965. | |
287 | * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz | |
288 | * (legacy) channels. | |
289 | * | |
e2ebc833 | 290 | * See struct il4965_eeprom_channel for format, and struct il4965_eeprom |
4bc85c13 WYG |
291 | * for locations in EEPROM. |
292 | * | |
293 | * 2) Factory txpower calibration information is provided separately for | |
294 | * sub-bands of contiguous channels. 2.4GHz has just one sub-band, | |
295 | * but 5 GHz has several sub-bands. | |
296 | * | |
297 | * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided. | |
298 | * | |
e2ebc833 SG |
299 | * See struct il4965_eeprom_calib_info (and the tree of structures |
300 | * contained within it) for format, and struct il4965_eeprom for | |
4bc85c13 WYG |
301 | * locations in EEPROM. |
302 | * | |
e2ebc833 | 303 | * "Initialization alive" notification (see struct il4965_init_alive_resp) |
4bc85c13 WYG |
304 | * consists of: |
305 | * | |
306 | * 1) Temperature calculation parameters. | |
307 | * | |
308 | * 2) Power supply voltage measurement. | |
309 | * | |
310 | * 3) Tx gain compensation to balance 2 transmitters for MIMO use. | |
311 | * | |
312 | * Statistics notifications deliver: | |
313 | * | |
314 | * 1) Current values for temperature param R4. | |
315 | */ | |
316 | ||
317 | /** | |
318 | * To calculate a txpower setting for a given desired target txpower, channel, | |
319 | * modulation bit rate, and transmitter chain (4965 has 2 transmitters to | |
320 | * support MIMO and transmit diversity), driver must do the following: | |
321 | * | |
322 | * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel. | |
323 | * Do not exceed regulatory limit; reduce target txpower if necessary. | |
324 | * | |
0c2c8852 | 325 | * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31), |
4bc85c13 WYG |
326 | * 2 transmitters will be used simultaneously; driver must reduce the |
327 | * regulatory limit by 3 dB (half-power) for each transmitter, so the | |
328 | * combined total output of the 2 transmitters is within regulatory limits. | |
329 | * | |
330 | * | |
331 | * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by | |
332 | * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]); | |
333 | * reduce target txpower if necessary. | |
334 | * | |
335 | * Backoff values below are in 1/2 dB units (equivalent to steps in | |
336 | * txpower gain tables): | |
337 | * | |
338 | * OFDM 6 - 36 MBit: 10 steps (5 dB) | |
339 | * OFDM 48 MBit: 15 steps (7.5 dB) | |
340 | * OFDM 54 MBit: 17 steps (8.5 dB) | |
341 | * OFDM 60 MBit: 20 steps (10 dB) | |
342 | * CCK all rates: 10 steps (5 dB) | |
343 | * | |
344 | * Backoff values apply to saturation txpower on a per-transmitter basis; | |
345 | * when using MIMO (2 transmitters), each transmitter uses the same | |
346 | * saturation level provided in EEPROM, and the same backoff values; | |
347 | * no reduction (such as with regulatory txpower limits) is required. | |
348 | * | |
349 | * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel | |
350 | * widths and 40 Mhz (.11n HT40) channel widths; there is no separate | |
351 | * factory measurement for ht40 channels. | |
352 | * | |
353 | * The result of this step is the final target txpower. The rest of | |
354 | * the steps figure out the proper settings for the device to achieve | |
355 | * that target txpower. | |
356 | * | |
357 | * | |
358 | * 3) Determine (EEPROM) calibration sub band for the target channel, by | |
359 | * comparing against first and last channels in each sub band | |
e2ebc833 | 360 | * (see struct il4965_eeprom_calib_subband_info). |
4bc85c13 WYG |
361 | * |
362 | * | |
363 | * 4) Linearly interpolate (EEPROM) factory calibration measurement sets, | |
364 | * referencing the 2 factory-measured (sample) channels within the sub band. | |
365 | * | |
366 | * Interpolation is based on difference between target channel's frequency | |
367 | * and the sample channels' frequencies. Since channel numbers are based | |
368 | * on frequency (5 MHz between each channel number), this is equivalent | |
369 | * to interpolating based on channel number differences. | |
370 | * | |
371 | * Note that the sample channels may or may not be the channels at the | |
372 | * edges of the sub band. The target channel may be "outside" of the | |
373 | * span of the sampled channels. | |
374 | * | |
375 | * Driver may choose the pair (for 2 Tx chains) of measurements (see | |
e2ebc833 | 376 | * struct il4965_eeprom_calib_ch_info) for which the actual measured |
4bc85c13 WYG |
377 | * txpower comes closest to the desired txpower. Usually, though, |
378 | * the middle set of measurements is closest to the regulatory limits, | |
379 | * and is therefore a good choice for all txpower calculations (this | |
380 | * assumes that high accuracy is needed for maximizing legal txpower, | |
381 | * while lower txpower configurations do not need as much accuracy). | |
382 | * | |
383 | * Driver should interpolate both members of the chosen measurement pair, | |
384 | * i.e. for both Tx chains (radio transmitters), unless the driver knows | |
385 | * that only one of the chains will be used (e.g. only one tx antenna | |
386 | * connected, but this should be unusual). The rate scaling algorithm | |
387 | * switches antennas to find best performance, so both Tx chains will | |
388 | * be used (although only one at a time) even for non-MIMO transmissions. | |
389 | * | |
390 | * Driver should interpolate factory values for temperature, gain table | |
0c2c8852 | 391 | * idx, and actual power. The power amplifier detector values are |
4bc85c13 WYG |
392 | * not used by the driver. |
393 | * | |
394 | * Sanity check: If the target channel happens to be one of the sample | |
395 | * channels, the results should agree with the sample channel's | |
396 | * measurements! | |
397 | * | |
398 | * | |
399 | * 5) Find difference between desired txpower and (interpolated) | |
0c2c8852 SG |
400 | * factory-measured txpower. Using (interpolated) factory gain table idx |
401 | * (shown elsewhere) as a starting point, adjust this idx lower to | |
4bc85c13 WYG |
402 | * increase txpower, or higher to decrease txpower, until the target |
403 | * txpower is reached. Each step in the gain table is 1/2 dB. | |
404 | * | |
405 | * For example, if factory measured txpower is 16 dBm, and target txpower | |
0c2c8852 | 406 | * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower |
4bc85c13 WYG |
407 | * by 3 dB. |
408 | * | |
409 | * | |
410 | * 6) Find difference between current device temperature and (interpolated) | |
411 | * factory-measured temperature for sub-band. Factory values are in | |
412 | * degrees Celsius. To calculate current temperature, see comments for | |
413 | * "4965 temperature calculation". | |
414 | * | |
415 | * If current temperature is higher than factory temperature, driver must | |
0c2c8852 | 416 | * increase gain (lower gain table idx), and vice verse. |
4bc85c13 WYG |
417 | * |
418 | * Temperature affects gain differently for different channels: | |
419 | * | |
420 | * 2.4 GHz all channels: 3.5 degrees per half-dB step | |
421 | * 5 GHz channels 34-43: 4.5 degrees per half-dB step | |
422 | * 5 GHz channels >= 44: 4.0 degrees per half-dB step | |
423 | * | |
424 | * NOTE: Temperature can increase rapidly when transmitting, especially | |
425 | * with heavy traffic at high txpowers. Driver should update | |
426 | * temperature calculations often under these conditions to | |
427 | * maintain strong txpower in the face of rising temperature. | |
428 | * | |
429 | * | |
430 | * 7) Find difference between current power supply voltage indicator | |
431 | * (from "initialize alive") and factory-measured power supply voltage | |
432 | * indicator (EEPROM). | |
433 | * | |
434 | * If the current voltage is higher (indicator is lower) than factory | |
0c2c8852 | 435 | * voltage, gain should be reduced (gain table idx increased) by: |
4bc85c13 WYG |
436 | * |
437 | * (eeprom - current) / 7 | |
438 | * | |
439 | * If the current voltage is lower (indicator is higher) than factory | |
0c2c8852 | 440 | * voltage, gain should be increased (gain table idx decreased) by: |
4bc85c13 WYG |
441 | * |
442 | * 2 * (current - eeprom) / 7 | |
443 | * | |
0c2c8852 | 444 | * If number of idx steps in either direction turns out to be > 2, |
4bc85c13 WYG |
445 | * something is wrong ... just use 0. |
446 | * | |
447 | * NOTE: Voltage compensation is independent of band/channel. | |
448 | * | |
449 | * NOTE: "Initialize" uCode measures current voltage, which is assumed | |
450 | * to be constant after this initial measurement. Voltage | |
451 | * compensation for txpower (number of steps in gain table) | |
452 | * may be calculated once and used until the next uCode bootload. | |
453 | * | |
454 | * | |
0c2c8852 | 455 | * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31), |
4bc85c13 WYG |
456 | * adjust txpower for each transmitter chain, so txpower is balanced |
457 | * between the two chains. There are 5 pairs of tx_atten[group][chain] | |
458 | * values in "initialize alive", one pair for each of 5 channel ranges: | |
459 | * | |
460 | * Group 0: 5 GHz channel 34-43 | |
461 | * Group 1: 5 GHz channel 44-70 | |
462 | * Group 2: 5 GHz channel 71-124 | |
463 | * Group 3: 5 GHz channel 125-200 | |
464 | * Group 4: 2.4 GHz all channels | |
465 | * | |
0c2c8852 | 466 | * Add the tx_atten[group][chain] value to the idx for the target chain. |
4bc85c13 WYG |
467 | * The values are signed, but are in pairs of 0 and a non-negative number, |
468 | * so as to reduce gain (if necessary) of the "hotter" channel. This | |
469 | * avoids any need to double-check for regulatory compliance after | |
470 | * this step. | |
471 | * | |
472 | * | |
473 | * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation | |
0c2c8852 | 474 | * value to the idx: |
4bc85c13 WYG |
475 | * |
476 | * Hardware rev B: 9 steps (4.5 dB) | |
477 | * Hardware rev C: 5 steps (2.5 dB) | |
478 | * | |
479 | * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, | |
480 | * bits [3:2], 1 = B, 2 = C. | |
481 | * | |
482 | * NOTE: This compensation is in addition to any saturation backoff that | |
483 | * might have been applied in an earlier step. | |
484 | * | |
485 | * | |
486 | * 10) Select the gain table, based on band (2.4 vs 5 GHz). | |
487 | * | |
0c2c8852 | 488 | * Limit the adjusted idx to stay within the table! |
4bc85c13 WYG |
489 | * |
490 | * | |
491 | * 11) Read gain table entries for DSP and radio gain, place into appropriate | |
e2ebc833 | 492 | * location(s) in command (struct il4965_txpowertable_cmd). |
4bc85c13 WYG |
493 | */ |
494 | ||
495 | /** | |
496 | * When MIMO is used (2 transmitters operating simultaneously), driver should | |
497 | * limit each transmitter to deliver a max of 3 dB below the regulatory limit | |
498 | * for the device. That is, use half power for each transmitter, so total | |
499 | * txpower is within regulatory limits. | |
500 | * | |
501 | * The value "6" represents number of steps in gain table to reduce power 3 dB. | |
502 | * Each step is 1/2 dB. | |
503 | */ | |
e2ebc833 | 504 | #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) |
4bc85c13 WYG |
505 | |
506 | /** | |
507 | * CCK gain compensation. | |
508 | * | |
509 | * When calculating txpowers for CCK, after making sure that the target power | |
510 | * is within regulatory and saturation limits, driver must additionally | |
0c2c8852 | 511 | * back off gain by adding these values to the gain table idx. |
4bc85c13 WYG |
512 | * |
513 | * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, | |
514 | * bits [3:2], 1 = B, 2 = C. | |
515 | */ | |
e2ebc833 SG |
516 | #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9) |
517 | #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5) | |
4bc85c13 WYG |
518 | |
519 | /* | |
520 | * 4965 power supply voltage compensation for txpower | |
521 | */ | |
e2ebc833 | 522 | #define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7) |
4bc85c13 WYG |
523 | |
524 | /** | |
525 | * Gain tables. | |
526 | * | |
527 | * The following tables contain pair of values for setting txpower, i.e. | |
528 | * gain settings for the output of the device's digital signal processor (DSP), | |
529 | * and for the analog gain structure of the transmitter. | |
530 | * | |
531 | * Each entry in the gain tables represents a step of 1/2 dB. Note that these | |
532 | * are *relative* steps, not indications of absolute output power. Output | |
533 | * power varies with temperature, voltage, and channel frequency, and also | |
534 | * requires consideration of average power (to satisfy regulatory constraints), | |
535 | * and peak power (to avoid distortion of the output signal). | |
536 | * | |
537 | * Each entry contains two values: | |
538 | * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained | |
539 | * linear value that multiplies the output of the digital signal processor, | |
540 | * before being sent to the analog radio. | |
541 | * 2) Radio gain. This sets the analog gain of the radio Tx path. | |
542 | * It is a coarser setting, and behaves in a logarithmic (dB) fashion. | |
543 | * | |
544 | * EEPROM contains factory calibration data for txpower. This maps actual | |
545 | * measured txpower levels to gain settings in the "well known" tables | |
546 | * below ("well-known" means here that both factory calibration *and* the | |
547 | * driver work with the same table). | |
548 | * | |
549 | * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table | |
0c2c8852 | 550 | * has an extension (into negative idxes), in case the driver needs to |
4bc85c13 | 551 | * boost power setting for high device temperatures (higher than would be |
0c2c8852 | 552 | * present during factory calibration). A 5 Ghz EEPROM idx of "40" |
4bc85c13 WYG |
553 | * corresponds to the 49th entry in the table used by the driver. |
554 | */ | |
e7392364 SG |
555 | #define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */ |
556 | #define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */ | |
4bc85c13 WYG |
557 | |
558 | /** | |
559 | * 2.4 GHz gain table | |
560 | * | |
561 | * Index Dsp gain Radio gain | |
562 | * 0 110 0x3f (highest gain) | |
563 | * 1 104 0x3f | |
564 | * 2 98 0x3f | |
565 | * 3 110 0x3e | |
566 | * 4 104 0x3e | |
567 | * 5 98 0x3e | |
568 | * 6 110 0x3d | |
569 | * 7 104 0x3d | |
570 | * 8 98 0x3d | |
571 | * 9 110 0x3c | |
572 | * 10 104 0x3c | |
573 | * 11 98 0x3c | |
574 | * 12 110 0x3b | |
575 | * 13 104 0x3b | |
576 | * 14 98 0x3b | |
577 | * 15 110 0x3a | |
578 | * 16 104 0x3a | |
579 | * 17 98 0x3a | |
580 | * 18 110 0x39 | |
581 | * 19 104 0x39 | |
582 | * 20 98 0x39 | |
583 | * 21 110 0x38 | |
584 | * 22 104 0x38 | |
585 | * 23 98 0x38 | |
586 | * 24 110 0x37 | |
587 | * 25 104 0x37 | |
588 | * 26 98 0x37 | |
589 | * 27 110 0x36 | |
590 | * 28 104 0x36 | |
591 | * 29 98 0x36 | |
592 | * 30 110 0x35 | |
593 | * 31 104 0x35 | |
594 | * 32 98 0x35 | |
595 | * 33 110 0x34 | |
596 | * 34 104 0x34 | |
597 | * 35 98 0x34 | |
598 | * 36 110 0x33 | |
599 | * 37 104 0x33 | |
600 | * 38 98 0x33 | |
601 | * 39 110 0x32 | |
602 | * 40 104 0x32 | |
603 | * 41 98 0x32 | |
604 | * 42 110 0x31 | |
605 | * 43 104 0x31 | |
606 | * 44 98 0x31 | |
607 | * 45 110 0x30 | |
608 | * 46 104 0x30 | |
609 | * 47 98 0x30 | |
610 | * 48 110 0x6 | |
611 | * 49 104 0x6 | |
612 | * 50 98 0x6 | |
613 | * 51 110 0x5 | |
614 | * 52 104 0x5 | |
615 | * 53 98 0x5 | |
616 | * 54 110 0x4 | |
617 | * 55 104 0x4 | |
618 | * 56 98 0x4 | |
619 | * 57 110 0x3 | |
620 | * 58 104 0x3 | |
621 | * 59 98 0x3 | |
622 | * 60 110 0x2 | |
623 | * 61 104 0x2 | |
624 | * 62 98 0x2 | |
625 | * 63 110 0x1 | |
626 | * 64 104 0x1 | |
627 | * 65 98 0x1 | |
628 | * 66 110 0x0 | |
629 | * 67 104 0x0 | |
630 | * 68 98 0x0 | |
631 | * 69 97 0 | |
632 | * 70 96 0 | |
633 | * 71 95 0 | |
634 | * 72 94 0 | |
635 | * 73 93 0 | |
636 | * 74 92 0 | |
637 | * 75 91 0 | |
638 | * 76 90 0 | |
639 | * 77 89 0 | |
640 | * 78 88 0 | |
641 | * 79 87 0 | |
642 | * 80 86 0 | |
643 | * 81 85 0 | |
644 | * 82 84 0 | |
645 | * 83 83 0 | |
646 | * 84 82 0 | |
647 | * 85 81 0 | |
648 | * 86 80 0 | |
649 | * 87 79 0 | |
650 | * 88 78 0 | |
651 | * 89 77 0 | |
652 | * 90 76 0 | |
653 | * 91 75 0 | |
654 | * 92 74 0 | |
655 | * 93 73 0 | |
656 | * 94 72 0 | |
657 | * 95 71 0 | |
658 | * 96 70 0 | |
659 | * 97 69 0 | |
660 | * 98 68 0 | |
661 | */ | |
662 | ||
663 | /** | |
664 | * 5 GHz gain table | |
665 | * | |
666 | * Index Dsp gain Radio gain | |
667 | * -9 123 0x3F (highest gain) | |
668 | * -8 117 0x3F | |
669 | * -7 110 0x3F | |
670 | * -6 104 0x3F | |
671 | * -5 98 0x3F | |
672 | * -4 110 0x3E | |
673 | * -3 104 0x3E | |
674 | * -2 98 0x3E | |
675 | * -1 110 0x3D | |
676 | * 0 104 0x3D | |
677 | * 1 98 0x3D | |
678 | * 2 110 0x3C | |
679 | * 3 104 0x3C | |
680 | * 4 98 0x3C | |
681 | * 5 110 0x3B | |
682 | * 6 104 0x3B | |
683 | * 7 98 0x3B | |
684 | * 8 110 0x3A | |
685 | * 9 104 0x3A | |
686 | * 10 98 0x3A | |
687 | * 11 110 0x39 | |
688 | * 12 104 0x39 | |
689 | * 13 98 0x39 | |
690 | * 14 110 0x38 | |
691 | * 15 104 0x38 | |
692 | * 16 98 0x38 | |
693 | * 17 110 0x37 | |
694 | * 18 104 0x37 | |
695 | * 19 98 0x37 | |
696 | * 20 110 0x36 | |
697 | * 21 104 0x36 | |
698 | * 22 98 0x36 | |
699 | * 23 110 0x35 | |
700 | * 24 104 0x35 | |
701 | * 25 98 0x35 | |
702 | * 26 110 0x34 | |
703 | * 27 104 0x34 | |
704 | * 28 98 0x34 | |
705 | * 29 110 0x33 | |
706 | * 30 104 0x33 | |
707 | * 31 98 0x33 | |
708 | * 32 110 0x32 | |
709 | * 33 104 0x32 | |
710 | * 34 98 0x32 | |
711 | * 35 110 0x31 | |
712 | * 36 104 0x31 | |
713 | * 37 98 0x31 | |
714 | * 38 110 0x30 | |
715 | * 39 104 0x30 | |
716 | * 40 98 0x30 | |
717 | * 41 110 0x25 | |
718 | * 42 104 0x25 | |
719 | * 43 98 0x25 | |
720 | * 44 110 0x24 | |
721 | * 45 104 0x24 | |
722 | * 46 98 0x24 | |
723 | * 47 110 0x23 | |
724 | * 48 104 0x23 | |
725 | * 49 98 0x23 | |
726 | * 50 110 0x22 | |
727 | * 51 104 0x18 | |
728 | * 52 98 0x18 | |
729 | * 53 110 0x17 | |
730 | * 54 104 0x17 | |
731 | * 55 98 0x17 | |
732 | * 56 110 0x16 | |
733 | * 57 104 0x16 | |
734 | * 58 98 0x16 | |
735 | * 59 110 0x15 | |
736 | * 60 104 0x15 | |
737 | * 61 98 0x15 | |
738 | * 62 110 0x14 | |
739 | * 63 104 0x14 | |
740 | * 64 98 0x14 | |
741 | * 65 110 0x13 | |
742 | * 66 104 0x13 | |
743 | * 67 98 0x13 | |
744 | * 68 110 0x12 | |
745 | * 69 104 0x08 | |
746 | * 70 98 0x08 | |
747 | * 71 110 0x07 | |
748 | * 72 104 0x07 | |
749 | * 73 98 0x07 | |
750 | * 74 110 0x06 | |
751 | * 75 104 0x06 | |
752 | * 76 98 0x06 | |
753 | * 77 110 0x05 | |
754 | * 78 104 0x05 | |
755 | * 79 98 0x05 | |
756 | * 80 110 0x04 | |
757 | * 81 104 0x04 | |
758 | * 82 98 0x04 | |
759 | * 83 110 0x03 | |
760 | * 84 104 0x03 | |
761 | * 85 98 0x03 | |
762 | * 86 110 0x02 | |
763 | * 87 104 0x02 | |
764 | * 88 98 0x02 | |
765 | * 89 110 0x01 | |
766 | * 90 104 0x01 | |
767 | * 91 98 0x01 | |
768 | * 92 110 0x00 | |
769 | * 93 104 0x00 | |
770 | * 94 98 0x00 | |
771 | * 95 93 0x00 | |
772 | * 96 88 0x00 | |
773 | * 97 83 0x00 | |
774 | * 98 78 0x00 | |
775 | */ | |
776 | ||
4bc85c13 WYG |
777 | /** |
778 | * Sanity checks and default values for EEPROM regulatory levels. | |
779 | * If EEPROM values fall outside MIN/MAX range, use default values. | |
780 | * | |
781 | * Regulatory limits refer to the maximum average txpower allowed by | |
782 | * regulatory agencies in the geographies in which the device is meant | |
783 | * to be operated. These limits are SKU-specific (i.e. geography-specific), | |
784 | * and channel-specific; each channel has an individual regulatory limit | |
785 | * listed in the EEPROM. | |
786 | * | |
787 | * Units are in half-dBm (i.e. "34" means 17 dBm). | |
788 | */ | |
e2ebc833 SG |
789 | #define IL_TX_POWER_DEFAULT_REGULATORY_24 (34) |
790 | #define IL_TX_POWER_DEFAULT_REGULATORY_52 (34) | |
791 | #define IL_TX_POWER_REGULATORY_MIN (0) | |
792 | #define IL_TX_POWER_REGULATORY_MAX (34) | |
4bc85c13 WYG |
793 | |
794 | /** | |
795 | * Sanity checks and default values for EEPROM saturation levels. | |
796 | * If EEPROM values fall outside MIN/MAX range, use default values. | |
797 | * | |
798 | * Saturation is the highest level that the output power amplifier can produce | |
799 | * without significant clipping distortion. This is a "peak" power level. | |
800 | * Different types of modulation (i.e. various "rates", and OFDM vs. CCK) | |
801 | * require differing amounts of backoff, relative to their average power output, | |
802 | * in order to avoid clipping distortion. | |
803 | * | |
804 | * Driver must make sure that it is violating neither the saturation limit, | |
805 | * nor the regulatory limit, when calculating Tx power settings for various | |
806 | * rates. | |
807 | * | |
808 | * Units are in half-dBm (i.e. "38" means 19 dBm). | |
809 | */ | |
e2ebc833 SG |
810 | #define IL_TX_POWER_DEFAULT_SATURATION_24 (38) |
811 | #define IL_TX_POWER_DEFAULT_SATURATION_52 (38) | |
812 | #define IL_TX_POWER_SATURATION_MIN (20) | |
813 | #define IL_TX_POWER_SATURATION_MAX (50) | |
4bc85c13 WYG |
814 | |
815 | /** | |
816 | * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance) | |
817 | * and thermal Txpower calibration. | |
818 | * | |
819 | * When calculating txpower, driver must compensate for current device | |
820 | * temperature; higher temperature requires higher gain. Driver must calculate | |
821 | * current temperature (see "4965 temperature calculation"), then compare vs. | |
822 | * factory calibration temperature in EEPROM; if current temperature is higher | |
823 | * than factory temperature, driver must *increase* gain by proportions shown | |
824 | * in table below. If current temperature is lower than factory, driver must | |
825 | * *decrease* gain. | |
826 | * | |
827 | * Different frequency ranges require different compensation, as shown below. | |
828 | */ | |
829 | /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */ | |
e2ebc833 SG |
830 | #define CALIB_IL_TX_ATTEN_GR1_FCH 34 |
831 | #define CALIB_IL_TX_ATTEN_GR1_LCH 43 | |
4bc85c13 WYG |
832 | |
833 | /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */ | |
e2ebc833 SG |
834 | #define CALIB_IL_TX_ATTEN_GR2_FCH 44 |
835 | #define CALIB_IL_TX_ATTEN_GR2_LCH 70 | |
4bc85c13 WYG |
836 | |
837 | /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */ | |
e2ebc833 SG |
838 | #define CALIB_IL_TX_ATTEN_GR3_FCH 71 |
839 | #define CALIB_IL_TX_ATTEN_GR3_LCH 124 | |
4bc85c13 WYG |
840 | |
841 | /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */ | |
e2ebc833 SG |
842 | #define CALIB_IL_TX_ATTEN_GR4_FCH 125 |
843 | #define CALIB_IL_TX_ATTEN_GR4_LCH 200 | |
4bc85c13 WYG |
844 | |
845 | /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */ | |
e2ebc833 SG |
846 | #define CALIB_IL_TX_ATTEN_GR5_FCH 1 |
847 | #define CALIB_IL_TX_ATTEN_GR5_LCH 20 | |
4bc85c13 WYG |
848 | |
849 | enum { | |
850 | CALIB_CH_GROUP_1 = 0, | |
851 | CALIB_CH_GROUP_2 = 1, | |
852 | CALIB_CH_GROUP_3 = 2, | |
853 | CALIB_CH_GROUP_4 = 3, | |
854 | CALIB_CH_GROUP_5 = 4, | |
855 | CALIB_CH_GROUP_MAX | |
856 | }; | |
857 | ||
858 | /********************* END TXPOWER *****************************************/ | |
859 | ||
4bc85c13 WYG |
860 | /** |
861 | * Tx/Rx Queues | |
862 | * | |
863 | * Most communication between driver and 4965 is via queues of data buffers. | |
864 | * For example, all commands that the driver issues to device's embedded | |
865 | * controller (uCode) are via the command queue (one of the Tx queues). All | |
866 | * uCode command responses/replies/notifications, including Rx frames, are | |
867 | * conveyed from uCode to driver via the Rx queue. | |
868 | * | |
869 | * Most support for these queues, including handshake support, resides in | |
870 | * structures in host DRAM, shared between the driver and the device. When | |
871 | * allocating this memory, the driver must make sure that data written by | |
872 | * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's | |
873 | * cache memory), so DRAM and cache are consistent, and the device can | |
874 | * immediately see changes made by the driver. | |
875 | * | |
876 | * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via | |
877 | * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array | |
878 | * in DRAM containing 256 Transmit Frame Descriptors (TFDs). | |
879 | */ | |
d3175167 SG |
880 | #define IL49_NUM_FIFOS 7 |
881 | #define IL49_CMD_FIFO_NUM 4 | |
882 | #define IL49_NUM_QUEUES 16 | |
883 | #define IL49_NUM_AMPDU_QUEUES 8 | |
4bc85c13 | 884 | |
4bc85c13 | 885 | /** |
e2ebc833 | 886 | * struct il4965_schedq_bc_tbl |
4bc85c13 WYG |
887 | * |
888 | * Byte Count table | |
889 | * | |
890 | * Each Tx queue uses a byte-count table containing 320 entries: | |
891 | * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that | |
6ce1dc45 SG |
892 | * duplicate the first 64 entries (to avoid wrap-around within a Tx win; |
893 | * max Tx win is 64 TFDs). | |
4bc85c13 WYG |
894 | * |
895 | * When driver sets up a new TFD, it must also enter the total byte count | |
896 | * of the frame to be transmitted into the corresponding entry in the byte | |
0c2c8852 SG |
897 | * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver |
898 | * must duplicate the byte count entry in corresponding idx 256-319. | |
4bc85c13 WYG |
899 | * |
900 | * padding puts each byte count table on a 1024-byte boundary; | |
901 | * 4965 assumes tables are separated by 1024 bytes. | |
902 | */ | |
e2ebc833 | 903 | struct il4965_scd_bc_tbl { |
4bc85c13 WYG |
904 | __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; |
905 | u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)]; | |
906 | } __packed; | |
907 | ||
d3175167 | 908 | #define IL4965_RTC_INST_LOWER_BOUND (0x000000) |
be663ab6 WYG |
909 | |
910 | /* RSSI to dBm */ | |
d3175167 | 911 | #define IL4965_RSSI_OFFSET 44 |
be663ab6 WYG |
912 | |
913 | /* PCI registers */ | |
914 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
915 | ||
916 | /* PCI register values */ | |
917 | #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01 | |
918 | #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02 | |
919 | ||
d3175167 | 920 | #define IL4965_DEFAULT_TX_RETRY 15 |
be663ab6 | 921 | |
be663ab6 | 922 | /* EEPROM */ |
d3175167 | 923 | #define IL4965_FIRST_AMPDU_QUEUE 10 |
be663ab6 | 924 | |
af038f40 SG |
925 | /* Calibration */ |
926 | void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp); | |
927 | void il4965_sensitivity_calibration(struct il_priv *il, void *resp); | |
928 | void il4965_init_sensitivity(struct il_priv *il); | |
929 | void il4965_reset_run_time_calib(struct il_priv *il); | |
af038f40 SG |
930 | |
931 | /* Debug */ | |
932 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
93b7654e | 933 | extern const struct il_debugfs_ops il4965_debugfs_ops; |
af038f40 | 934 | #endif |
be663ab6 | 935 | |
eac3b212 SG |
936 | /****************************/ |
937 | /* Flow Handler Definitions */ | |
938 | /****************************/ | |
939 | ||
940 | /** | |
941 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) | |
942 | * Addresses are offsets from device's PCI hardware base address. | |
943 | */ | |
944 | #define FH49_MEM_LOWER_BOUND (0x1000) | |
945 | #define FH49_MEM_UPPER_BOUND (0x2000) | |
946 | ||
947 | /** | |
948 | * Keep-Warm (KW) buffer base address. | |
949 | * | |
950 | * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the | |
951 | * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency | |
952 | * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host | |
953 | * from going into a power-savings mode that would cause higher DRAM latency, | |
954 | * and possible data over/under-runs, before all Tx/Rx is complete. | |
955 | * | |
956 | * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4) | |
957 | * of the buffer, which must be 4K aligned. Once this is set up, the 4965 | |
958 | * automatically invokes keep-warm accesses when normal accesses might not | |
959 | * be sufficient to maintain fast DRAM response. | |
960 | * | |
961 | * Bit fields: | |
962 | * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned | |
963 | */ | |
964 | #define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C) | |
965 | ||
eac3b212 SG |
966 | /** |
967 | * TFD Circular Buffers Base (CBBC) addresses | |
968 | * | |
969 | * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident | |
970 | * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) | |
971 | * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04 | |
972 | * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte | |
973 | * aligned (address bits 0-7 must be 0). | |
974 | * | |
975 | * Bit fields in each pointer register: | |
976 | * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned | |
977 | */ | |
978 | #define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0) | |
979 | #define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10) | |
980 | ||
981 | /* Find TFD CB base pointer for given queue (range 0-15). */ | |
982 | #define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4) | |
983 | ||
eac3b212 SG |
984 | /** |
985 | * Rx SRAM Control and Status Registers (RSCSR) | |
986 | * | |
987 | * These registers provide handshake between driver and 4965 for the Rx queue | |
988 | * (this queue handles *all* command responses, notifications, Rx data, etc. | |
989 | * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx | |
990 | * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can | |
991 | * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer | |
992 | * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 | |
993 | * mapping between RBDs and RBs. | |
994 | * | |
995 | * Driver must allocate host DRAM memory for the following, and set the | |
996 | * physical address of each into 4965 registers: | |
997 | * | |
998 | * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 | |
999 | * entries (although any power of 2, up to 4096, is selectable by driver). | |
1000 | * Each entry (1 dword) points to a receive buffer (RB) of consistent size | |
1001 | * (typically 4K, although 8K or 16K are also selectable by driver). | |
1002 | * Driver sets up RB size and number of RBDs in the CB via Rx config | |
1003 | * register FH49_MEM_RCSR_CHNL0_CONFIG_REG. | |
1004 | * | |
1005 | * Bit fields within one RBD: | |
1006 | * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned | |
1007 | * | |
1008 | * Driver sets physical address [35:8] of base of RBD circular buffer | |
1009 | * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. | |
1010 | * | |
1011 | * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers | |
1012 | * (RBs) have been filled, via a "write pointer", actually the idx of | |
1013 | * the RB's corresponding RBD within the circular buffer. Driver sets | |
1014 | * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. | |
1015 | * | |
1016 | * Bit fields in lower dword of Rx status buffer (upper dword not used | |
1017 | * by driver; see struct il4965_shared, val0): | |
1018 | * 31-12: Not used by driver | |
1019 | * 11- 0: Index of last filled Rx buffer descriptor | |
1020 | * (4965 writes, driver reads this value) | |
1021 | * | |
1022 | * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must | |
1023 | * enter pointers to these RBs into contiguous RBD circular buffer entries, | |
1024 | * and update the 4965's "write" idx register, | |
1025 | * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG. | |
1026 | * | |
1027 | * This "write" idx corresponds to the *next* RBD that the driver will make | |
1028 | * available, i.e. one RBD past the tail of the ready-to-fill RBDs within | |
1029 | * the circular buffer. This value should initially be 0 (before preparing any | |
1030 | * RBs), should be 8 after preparing the first 8 RBs (for example), and must | |
1031 | * wrap back to 0 at the end of the circular buffer (but don't wrap before | |
1032 | * "read" idx has advanced past 1! See below). | |
1033 | * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8. | |
1034 | * | |
1035 | * As the 4965 fills RBs (referenced from contiguous RBDs within the circular | |
1036 | * buffer), it updates the Rx status buffer in host DRAM, 2) described above, | |
1037 | * to tell the driver the idx of the latest filled RBD. The driver must | |
1038 | * read this "read" idx from DRAM after receiving an Rx interrupt from 4965. | |
1039 | * | |
1040 | * The driver must also internally keep track of a third idx, which is the | |
1041 | * next RBD to process. When receiving an Rx interrupt, driver should process | |
1042 | * all filled but unprocessed RBs up to, but not including, the RB | |
1043 | * corresponding to the "read" idx. For example, if "read" idx becomes "1", | |
1044 | * driver may process the RB pointed to by RBD 0. Depending on volume of | |
1045 | * traffic, there may be many RBs to process. | |
1046 | * | |
1047 | * If read idx == write idx, 4965 thinks there is no room to put new data. | |
1048 | * Due to this, the maximum number of filled RBs is 255, instead of 256. To | |
1049 | * be safe, make sure that there is a gap of at least 2 RBDs between "write" | |
1050 | * and "read" idxes; that is, make sure that there are no more than 254 | |
1051 | * buffers waiting to be filled. | |
1052 | */ | |
1053 | #define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0) | |
1054 | #define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00) | |
1055 | #define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND) | |
1056 | ||
1057 | /** | |
1058 | * Physical base address of 8-byte Rx Status buffer. | |
1059 | * Bit fields: | |
1060 | * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. | |
1061 | */ | |
1062 | #define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0) | |
1063 | ||
1064 | /** | |
1065 | * Physical base address of Rx Buffer Descriptor Circular Buffer. | |
1066 | * Bit fields: | |
1067 | * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. | |
1068 | */ | |
1069 | #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004) | |
1070 | ||
1071 | /** | |
1072 | * Rx write pointer (idx, really!). | |
1073 | * Bit fields: | |
1074 | * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. | |
1075 | * NOTE: For 256-entry circular buffer, use only bits [7:0]. | |
1076 | */ | |
1077 | #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008) | |
1078 | #define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG) | |
1079 | ||
eac3b212 SG |
1080 | /** |
1081 | * Rx Config/Status Registers (RCSR) | |
1082 | * Rx Config Reg for channel 0 (only channel used) | |
1083 | * | |
1084 | * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for | |
1085 | * normal operation (see bit fields). | |
1086 | * | |
1087 | * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. | |
1088 | * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for | |
1089 | * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. | |
1090 | * | |
1091 | * Bit fields: | |
1092 | * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
1093 | * '10' operate normally | |
1094 | * 29-24: reserved | |
1095 | * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), | |
1096 | * min "5" for 32 RBDs, max "12" for 4096 RBDs. | |
1097 | * 19-18: reserved | |
1098 | * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, | |
1099 | * '10' 12K, '11' 16K. | |
1100 | * 15-14: reserved | |
1101 | * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) | |
1102 | * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) | |
1103 | * typical value 0x10 (about 1/2 msec) | |
1104 | * 3- 0: reserved | |
1105 | */ | |
1106 | #define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00) | |
1107 | #define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0) | |
1108 | #define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND) | |
1109 | ||
1110 | #define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0) | |
1111 | ||
e7392364 SG |
1112 | #define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ |
1113 | #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ | |
1114 | #define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ | |
1115 | #define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ | |
1116 | #define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ | |
1117 | #define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */ | |
eac3b212 SG |
1118 | |
1119 | #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) | |
1120 | #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) | |
1121 | #define RX_RB_TIMEOUT (0x10) | |
1122 | ||
1123 | #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) | |
1124 | #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) | |
1125 | #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) | |
1126 | ||
1127 | #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) | |
1128 | #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) | |
1129 | #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) | |
1130 | #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) | |
1131 | ||
1132 | #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) | |
1133 | #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) | |
1134 | #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) | |
1135 | ||
1136 | /** | |
1137 | * Rx Shared Status Registers (RSSR) | |
1138 | * | |
1139 | * After stopping Rx DMA channel (writing 0 to | |
1140 | * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll | |
1141 | * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. | |
1142 | * | |
1143 | * Bit fields: | |
1144 | * 24: 1 = Channel 0 is idle | |
1145 | * | |
1146 | * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV | |
1147 | * contain default values that should not be altered by the driver. | |
1148 | */ | |
1149 | #define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40) | |
1150 | #define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00) | |
1151 | ||
1152 | #define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND) | |
1153 | #define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004) | |
1154 | #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ | |
1155 | (FH49_MEM_RSSR_LOWER_BOUND + 0x008) | |
1156 | ||
1157 | #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) | |
1158 | ||
1159 | #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 | |
1160 | ||
1161 | /* TFDB Area - TFDs buffer table */ | |
1162 | #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) | |
1163 | #define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900) | |
1164 | #define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958) | |
1165 | #define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) | |
1166 | #define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) | |
1167 | ||
1168 | /** | |
1169 | * Transmit DMA Channel Control/Status Registers (TCSR) | |
1170 | * | |
1171 | * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels | |
1172 | * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, | |
1173 | * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. | |
1174 | * | |
1175 | * To use a Tx DMA channel, driver must initialize its | |
1176 | * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with: | |
1177 | * | |
1178 | * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
1179 | * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | |
1180 | * | |
1181 | * All other bits should be 0. | |
1182 | * | |
1183 | * Bit fields: | |
1184 | * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
1185 | * '10' operate normally | |
1186 | * 29- 4: Reserved, set to "0" | |
1187 | * 3: Enable internal DMA requests (1, normal operation), disable (0) | |
1188 | * 2- 0: Reserved, set to "0" | |
1189 | */ | |
1190 | #define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00) | |
1191 | #define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60) | |
1192 | ||
1193 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ | |
1194 | #define FH49_TCSR_CHNL_NUM (7) | |
1195 | #define FH50_TCSR_CHNL_NUM (8) | |
1196 | ||
1197 | /* TCSR: tx_config register values */ | |
1198 | #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ | |
1199 | (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl)) | |
1200 | #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ | |
1201 | (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) | |
1202 | #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ | |
1203 | (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) | |
1204 | ||
1205 | #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) | |
1206 | #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) | |
1207 | ||
1208 | #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) | |
1209 | #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) | |
1210 | ||
1211 | #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) | |
1212 | #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) | |
1213 | #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) | |
1214 | ||
1215 | #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) | |
1216 | #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) | |
1217 | #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) | |
1218 | ||
1219 | #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) | |
1220 | #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) | |
1221 | #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
1222 | ||
1223 | #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) | |
1224 | #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) | |
1225 | #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) | |
1226 | ||
1227 | #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) | |
1228 | #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) | |
1229 | ||
1230 | /** | |
1231 | * Tx Shared Status Registers (TSSR) | |
1232 | * | |
1233 | * After stopping Tx DMA channel (writing 0 to | |
1234 | * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll | |
1235 | * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle | |
1236 | * (channel's buffers empty | no pending requests). | |
1237 | * | |
1238 | * Bit fields: | |
1239 | * 31-24: 1 = Channel buffers empty (channel 7:0) | |
1240 | * 23-16: 1 = No pending requests (channel 7:0) | |
1241 | */ | |
1242 | #define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0) | |
1243 | #define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0) | |
1244 | ||
1245 | #define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010) | |
1246 | ||
1247 | /** | |
1248 | * Bit fields for TSSR(Tx Shared Status & Control) error status register: | |
1249 | * 31: Indicates an address error when accessed to internal memory | |
1250 | * uCode/driver must write "1" in order to clear this flag | |
1251 | * 30: Indicates that Host did not send the expected number of dwords to FH | |
1252 | * uCode/driver must write "1" in order to clear this flag | |
1253 | * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA | |
1254 | * command was received from the scheduler while the TRB was already full | |
1255 | * with previous command | |
1256 | * uCode/driver must write "1" in order to clear this flag | |
1257 | * 7-0: Each status bit indicates a channel's TxCredit error. When an error | |
1258 | * bit is set, it indicates that the FH has received a full indication | |
1259 | * from the RTC TxFIFO and the current value of the TxCredit counter was | |
1260 | * not equal to zero. This mean that the credit mechanism was not | |
1261 | * synchronized to the TxFIFO status | |
1262 | * uCode/driver must write "1" in order to clear this flag | |
1263 | */ | |
1264 | #define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018) | |
1265 | ||
1266 | #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) | |
1267 | ||
1268 | /* Tx service channels */ | |
1269 | #define FH49_SRVC_CHNL (9) | |
1270 | #define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8) | |
1271 | #define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0) | |
1272 | #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ | |
1273 | (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) | |
1274 | ||
1275 | #define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98) | |
1276 | /* Instruct FH to increment the retry count of a packet when | |
1277 | * it is brought from the memory to TX-FIFO | |
1278 | */ | |
1279 | #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) | |
1280 | ||
1281 | /* Keep Warm Size */ | |
1282 | #define IL_KW_SIZE 0x1000 /* 4k */ | |
1283 | ||
af038f40 | 1284 | #endif /* __il_4965_h__ */ |