Commit | Line | Data |
---|---|---|
6bbb1370 SG |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Linux Wireless <ilw@linux.intel.com> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | *****************************************************************************/ | |
26 | ||
27 | #ifndef __il_3945_h__ | |
28 | #define __il_3945_h__ | |
29 | ||
e7392364 | 30 | #include <linux/pci.h> /* for struct pci_device_id */ |
6bbb1370 SG |
31 | #include <linux/kernel.h> |
32 | #include <net/ieee80211_radiotap.h> | |
33 | ||
34 | /* Hardware specific file defines the PCI IDs table for that hardware module */ | |
35 | extern const struct pci_device_id il3945_hw_card_ids[]; | |
36 | ||
e94a4099 | 37 | #include "common.h" |
6bbb1370 | 38 | |
c39ae9fd SG |
39 | extern const struct il_ops il3945_ops; |
40 | ||
6bbb1370 SG |
41 | /* Highest firmware API version supported */ |
42 | #define IL3945_UCODE_API_MAX 2 | |
43 | ||
44 | /* Lowest firmware API version supported */ | |
45 | #define IL3945_UCODE_API_MIN 1 | |
46 | ||
47 | #define IL3945_FW_PRE "iwlwifi-3945-" | |
48 | #define _IL3945_MODULE_FIRMWARE(api) IL3945_FW_PRE #api ".ucode" | |
49 | #define IL3945_MODULE_FIRMWARE(api) _IL3945_MODULE_FIRMWARE(api) | |
50 | ||
51 | /* Default noise level to report when noise measurement is not available. | |
52 | * This may be because we're: | |
53 | * 1) Not associated (4965, no beacon stats being sent to driver) | |
54 | * 2) Scanning (noise measurement does not apply to associated channel) | |
55 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
56 | * Use default noise value of -127 ... this is below the range of measurable | |
57 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
58 | * Also, -127 works better than 0 when averaging frames with/without | |
59 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
60 | * always negative ... using a negative value as the default keeps all | |
61 | * averages within an s8's (used in some apps) range of negative values. */ | |
62 | #define IL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
63 | ||
64 | /* Module parameters accessible from iwl-*.c */ | |
65 | extern struct il_mod_params il3945_mod_params; | |
66 | ||
67 | struct il3945_rate_scale_data { | |
68 | u64 data; | |
69 | s32 success_counter; | |
70 | s32 success_ratio; | |
71 | s32 counter; | |
72 | s32 average_tpt; | |
73 | unsigned long stamp; | |
74 | }; | |
75 | ||
76 | struct il3945_rs_sta { | |
77 | spinlock_t lock; | |
78 | struct il_priv *il; | |
79 | s32 *expected_tpt; | |
80 | unsigned long last_partial_flush; | |
81 | unsigned long last_flush; | |
82 | u32 flush_time; | |
83 | u32 last_tx_packets; | |
84 | u32 tx_packets; | |
85 | u8 tgg; | |
86 | u8 flush_pending; | |
87 | u8 start_rate; | |
88 | struct timer_list rate_scale_flush; | |
89 | struct il3945_rate_scale_data win[RATE_COUNT_3945]; | |
90 | #ifdef CONFIG_MAC80211_DEBUGFS | |
91 | struct dentry *rs_sta_dbgfs_stats_table_file; | |
92 | #endif | |
93 | ||
94 | /* used to be in sta_info */ | |
95 | int last_txrate_idx; | |
96 | }; | |
97 | ||
6bbb1370 SG |
98 | /* |
99 | * The common struct MUST be first because it is shared between | |
100 | * 3945 and 4965! | |
101 | */ | |
102 | struct il3945_sta_priv { | |
103 | struct il_station_priv_common common; | |
104 | struct il3945_rs_sta rs_sta; | |
105 | }; | |
106 | ||
107 | enum il3945_antenna { | |
108 | IL_ANTENNA_DIVERSITY, | |
109 | IL_ANTENNA_MAIN, | |
110 | IL_ANTENNA_AUX | |
111 | }; | |
112 | ||
113 | /* | |
114 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
115 | * Per spec: | |
116 | * a value of 0 means RTS on all data/management packets | |
117 | * a value > max MSDU size means no RTS | |
118 | * else RTS for data/management frames where MPDU is larger | |
119 | * than RTS value. | |
120 | */ | |
121 | #define DEFAULT_RTS_THRESHOLD 2347U | |
122 | #define MIN_RTS_THRESHOLD 0U | |
123 | #define MAX_RTS_THRESHOLD 2347U | |
124 | #define MAX_MSDU_SIZE 2304U | |
125 | #define MAX_MPDU_SIZE 2346U | |
126 | #define DEFAULT_BEACON_INTERVAL 100U | |
127 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
128 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
129 | ||
130 | #define IL_TX_FIFO_AC0 0 | |
131 | #define IL_TX_FIFO_AC1 1 | |
132 | #define IL_TX_FIFO_AC2 2 | |
133 | #define IL_TX_FIFO_AC3 3 | |
134 | #define IL_TX_FIFO_HCCA_1 5 | |
135 | #define IL_TX_FIFO_HCCA_2 6 | |
136 | #define IL_TX_FIFO_NONE 7 | |
137 | ||
138 | #define IEEE80211_DATA_LEN 2304 | |
139 | #define IEEE80211_4ADDR_LEN 30 | |
140 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
141 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
142 | ||
143 | struct il3945_frame { | |
144 | union { | |
145 | struct ieee80211_hdr frame; | |
146 | struct il3945_tx_beacon_cmd beacon; | |
147 | u8 raw[IEEE80211_FRAME_LEN]; | |
148 | u8 cmd[360]; | |
149 | } u; | |
150 | struct list_head list; | |
151 | }; | |
152 | ||
6bbb1370 SG |
153 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 |
154 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
155 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
156 | ||
157 | #define IL_SUPPORTED_RATES_IE_LEN 8 | |
158 | ||
159 | #define SCAN_INTERVAL 100 | |
160 | ||
161 | #define MAX_TID_COUNT 9 | |
162 | ||
163 | #define IL_INVALID_RATE 0xFF | |
164 | #define IL_INVALID_VALUE -1 | |
165 | ||
166 | #define STA_PS_STATUS_WAKE 0 | |
167 | #define STA_PS_STATUS_SLEEP 1 | |
168 | ||
169 | struct il3945_ibss_seq { | |
170 | u8 mac[ETH_ALEN]; | |
171 | u16 seq_num; | |
172 | u16 frag_num; | |
173 | unsigned long packet_time; | |
174 | struct list_head list; | |
175 | }; | |
176 | ||
177 | #define IL_RX_HDR(x) ((struct il3945_rx_frame_hdr *)(\ | |
178 | x->u.rx_frame.stats.payload + \ | |
179 | x->u.rx_frame.stats.phy_count)) | |
180 | #define IL_RX_END(x) ((struct il3945_rx_frame_end *)(\ | |
181 | IL_RX_HDR(x)->payload + \ | |
182 | le16_to_cpu(IL_RX_HDR(x)->len))) | |
183 | #define IL_RX_STATS(x) (&x->u.rx_frame.stats) | |
184 | #define IL_RX_DATA(x) (IL_RX_HDR(x)->payload) | |
185 | ||
6bbb1370 SG |
186 | /****************************************************************************** |
187 | * | |
188 | * Functions implemented in iwl3945-base.c which are forward declared here | |
189 | * for use by iwl-*.c | |
190 | * | |
191 | *****************************************************************************/ | |
192 | extern int il3945_calc_db_from_ratio(int sig_ratio); | |
193 | extern void il3945_rx_replenish(void *data); | |
194 | extern void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq); | |
195 | extern unsigned int il3945_fill_beacon_frame(struct il_priv *il, | |
e7392364 SG |
196 | struct ieee80211_hdr *hdr, |
197 | int left); | |
6bbb1370 | 198 | extern int il3945_dump_nic_event_log(struct il_priv *il, bool full_log, |
e7392364 | 199 | char **buf, bool display); |
6bbb1370 SG |
200 | extern void il3945_dump_nic_error_log(struct il_priv *il); |
201 | ||
202 | /****************************************************************************** | |
203 | * | |
204 | * Functions implemented in iwl-[34]*.c which are forward declared here | |
205 | * for use by iwl3945-base.c | |
206 | * | |
207 | * NOTE: The implementation of these functions are hardware specific | |
208 | * which is why they are in the hardware specific files (vs. iwl-base.c) | |
209 | * | |
210 | * Naming convention -- | |
211 | * il3945_ <-- Its part of iwlwifi (should be changed to il3945_) | |
212 | * il3945_hw_ <-- Hardware specific (implemented in iwl-XXXX.c by all HW) | |
213 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) | |
214 | * il3945_bg_ <-- Called from work queue context | |
215 | * il3945_mac_ <-- mac80211 callback | |
216 | * | |
217 | ****************************************************************************/ | |
d0c72347 | 218 | extern void il3945_hw_handler_setup(struct il_priv *il); |
6bbb1370 SG |
219 | extern void il3945_hw_setup_deferred_work(struct il_priv *il); |
220 | extern void il3945_hw_cancel_deferred_work(struct il_priv *il); | |
221 | extern int il3945_hw_rxq_stop(struct il_priv *il); | |
222 | extern int il3945_hw_set_hw_params(struct il_priv *il); | |
223 | extern int il3945_hw_nic_init(struct il_priv *il); | |
224 | extern int il3945_hw_nic_stop_master(struct il_priv *il); | |
225 | extern void il3945_hw_txq_ctx_free(struct il_priv *il); | |
226 | extern void il3945_hw_txq_ctx_stop(struct il_priv *il); | |
227 | extern int il3945_hw_nic_reset(struct il_priv *il); | |
228 | extern int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, | |
e7392364 SG |
229 | struct il_tx_queue *txq, |
230 | dma_addr_t addr, u16 len, u8 reset, | |
231 | u8 pad); | |
232 | extern void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq); | |
6bbb1370 | 233 | extern int il3945_hw_get_temperature(struct il_priv *il); |
e7392364 | 234 | extern int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq); |
6bbb1370 | 235 | extern unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il, |
e7392364 SG |
236 | struct il3945_frame *frame, |
237 | u8 rate); | |
238 | void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd, | |
239 | struct ieee80211_tx_info *info, | |
81fb4613 | 240 | struct ieee80211_hdr *hdr, int sta_id); |
6bbb1370 SG |
241 | extern int il3945_hw_reg_send_txpower(struct il_priv *il); |
242 | extern int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power); | |
e7392364 SG |
243 | extern void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb); |
244 | void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb); | |
6bbb1370 SG |
245 | extern void il3945_disable_events(struct il_priv *il); |
246 | extern int il4965_get_temperature(const struct il_priv *il); | |
247 | extern void il3945_post_associate(struct il_priv *il); | |
248 | extern void il3945_config_ap(struct il_priv *il); | |
249 | ||
83007196 | 250 | extern int il3945_commit_rxon(struct il_priv *il); |
6bbb1370 SG |
251 | |
252 | /** | |
253 | * il3945_hw_find_station - Find station id for a given BSSID | |
254 | * @bssid: MAC address of station ID to find | |
255 | * | |
256 | * NOTE: This should not be hardware specific but the code has | |
257 | * not yet been merged into a single common layer for managing the | |
258 | * station tables. | |
259 | */ | |
e7392364 | 260 | extern u8 il3945_hw_find_station(struct il_priv *il, const u8 * bssid); |
6bbb1370 | 261 | |
6bbb1370 SG |
262 | extern __le32 il3945_get_antenna_flags(const struct il_priv *il); |
263 | extern int il3945_init_hw_rate_table(struct il_priv *il); | |
264 | extern void il3945_reg_txpower_periodic(struct il_priv *il); | |
265 | extern int il3945_txpower_set_from_eeprom(struct il_priv *il); | |
266 | ||
6bbb1370 SG |
267 | extern int il3945_rs_next_rate(struct il_priv *il, int rate); |
268 | ||
269 | /* scanning */ | |
270 | int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif); | |
271 | void il3945_post_scan(struct il_priv *il); | |
272 | ||
273 | /* rates */ | |
274 | extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945]; | |
275 | ||
6bbb1370 SG |
276 | /* RSSI to dBm */ |
277 | #define IL39_RSSI_OFFSET 95 | |
278 | ||
279 | /* | |
280 | * EEPROM related constants, enums, and structures. | |
281 | */ | |
282 | #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) | |
283 | ||
284 | /* | |
285 | * Mapping of a Tx power level, at factory calibration temperature, | |
286 | * to a radio/DSP gain table idx. | |
287 | * One for each of 5 "sample" power levels in each band. | |
288 | * v_det is measured at the factory, using the 3945's built-in power amplifier | |
289 | * (PA) output voltage detector. This same detector is used during Tx of | |
290 | * long packets in normal operation to provide feedback as to proper output | |
291 | * level. | |
292 | * Data copied from EEPROM. | |
293 | * DO NOT ALTER THIS STRUCTURE!!! | |
294 | */ | |
295 | struct il3945_eeprom_txpower_sample { | |
296 | u8 gain_idx; /* idx into power (gain) setup table ... */ | |
297 | s8 power; /* ... for this pwr level for this chnl group */ | |
298 | u16 v_det; /* PA output voltage */ | |
299 | } __packed; | |
300 | ||
301 | /* | |
302 | * Mappings of Tx power levels -> nominal radio/DSP gain table idxes. | |
303 | * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). | |
304 | * Tx power setup code interpolates between the 5 "sample" power levels | |
305 | * to determine the nominal setup for a requested power level. | |
306 | * Data copied from EEPROM. | |
307 | * DO NOT ALTER THIS STRUCTURE!!! | |
308 | */ | |
309 | struct il3945_eeprom_txpower_group { | |
e7392364 | 310 | struct il3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ |
6bbb1370 SG |
311 | s32 a, b, c, d, e; /* coefficients for voltage->power |
312 | * formula (signed) */ | |
313 | s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on | |
314 | * frequency (signed) */ | |
315 | s8 saturation_power; /* highest power possible by h/w in this | |
316 | * band */ | |
317 | u8 group_channel; /* "representative" channel # in this band */ | |
318 | s16 temperature; /* h/w temperature at factory calib this band | |
319 | * (signed) */ | |
320 | } __packed; | |
321 | ||
322 | /* | |
323 | * Temperature-based Tx-power compensation data, not band-specific. | |
324 | * These coefficients are use to modify a/b/c/d/e coeffs based on | |
325 | * difference between current temperature and factory calib temperature. | |
326 | * Data copied from EEPROM. | |
327 | */ | |
328 | struct il3945_eeprom_temperature_corr { | |
329 | u32 Ta; | |
330 | u32 Tb; | |
331 | u32 Tc; | |
332 | u32 Td; | |
333 | u32 Te; | |
334 | } __packed; | |
335 | ||
336 | /* | |
337 | * EEPROM map | |
338 | */ | |
339 | struct il3945_eeprom { | |
340 | u8 reserved0[16]; | |
e7392364 | 341 | u16 device_id; /* abs.ofs: 16 */ |
6bbb1370 SG |
342 | u8 reserved1[2]; |
343 | u16 pmc; /* abs.ofs: 20 */ | |
344 | u8 reserved2[20]; | |
345 | u8 mac_address[6]; /* abs.ofs: 42 */ | |
346 | u8 reserved3[58]; | |
347 | u16 board_revision; /* abs.ofs: 106 */ | |
348 | u8 reserved4[11]; | |
349 | u8 board_pba_number[9]; /* abs.ofs: 119 */ | |
350 | u8 reserved5[8]; | |
351 | u16 version; /* abs.ofs: 136 */ | |
352 | u8 sku_cap; /* abs.ofs: 138 */ | |
353 | u8 leds_mode; /* abs.ofs: 139 */ | |
354 | u16 oem_mode; | |
355 | u16 wowlan_mode; /* abs.ofs: 142 */ | |
356 | u16 leds_time_interval; /* abs.ofs: 144 */ | |
357 | u8 leds_off_time; /* abs.ofs: 146 */ | |
358 | u8 leds_on_time; /* abs.ofs: 147 */ | |
359 | u8 almgor_m_version; /* abs.ofs: 148 */ | |
360 | u8 antenna_switch_type; /* abs.ofs: 149 */ | |
361 | u8 reserved6[42]; | |
362 | u8 sku_id[4]; /* abs.ofs: 192 */ | |
363 | ||
364 | /* | |
365 | * Per-channel regulatory data. | |
366 | * | |
367 | * Each channel that *might* be supported by 3945 has a fixed location | |
368 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory | |
369 | * txpower (MSB). | |
370 | * | |
371 | * Entries immediately below are for 20 MHz channel width. | |
372 | * | |
373 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
374 | */ | |
375 | u16 band_1_count; /* abs.ofs: 196 */ | |
e7392364 | 376 | struct il_eeprom_channel band_1_channels[14]; /* abs.ofs: 198 */ |
6bbb1370 SG |
377 | |
378 | /* | |
379 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, | |
380 | * 5.0 GHz channels 7, 8, 11, 12, 16 | |
381 | * (4915-5080MHz) (none of these is ever supported) | |
382 | */ | |
383 | u16 band_2_count; /* abs.ofs: 226 */ | |
e7392364 | 384 | struct il_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ |
6bbb1370 SG |
385 | |
386 | /* | |
387 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
388 | * (5170-5320MHz) | |
389 | */ | |
390 | u16 band_3_count; /* abs.ofs: 254 */ | |
e7392364 | 391 | struct il_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ |
6bbb1370 SG |
392 | |
393 | /* | |
394 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
395 | * (5500-5700MHz) | |
396 | */ | |
397 | u16 band_4_count; /* abs.ofs: 280 */ | |
e7392364 | 398 | struct il_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ |
6bbb1370 SG |
399 | |
400 | /* | |
401 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 | |
402 | * (5725-5825MHz) | |
403 | */ | |
404 | u16 band_5_count; /* abs.ofs: 304 */ | |
e7392364 | 405 | struct il_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ |
6bbb1370 SG |
406 | |
407 | u8 reserved9[194]; | |
408 | ||
409 | /* | |
410 | * 3945 Txpower calibration data. | |
411 | */ | |
412 | #define IL_NUM_TX_CALIB_GROUPS 5 | |
413 | struct il3945_eeprom_txpower_group groups[IL_NUM_TX_CALIB_GROUPS]; | |
414 | /* abs.ofs: 512 */ | |
e7392364 | 415 | struct il3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ |
6bbb1370 SG |
416 | u8 reserved16[172]; /* fill out to full 1024 byte block */ |
417 | } __packed; | |
418 | ||
419 | #define IL3945_EEPROM_IMG_SIZE 1024 | |
420 | ||
421 | /* End of EEPROM */ | |
422 | ||
423 | #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ | |
424 | #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ | |
425 | ||
426 | /* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */ | |
427 | #define IL39_NUM_QUEUES 5 | |
428 | #define IL39_CMD_QUEUE_NUM 4 | |
429 | ||
430 | #define IL_DEFAULT_TX_RETRY 15 | |
431 | ||
432 | /*********************************************/ | |
433 | ||
434 | #define RFD_SIZE 4 | |
435 | #define NUM_TFD_CHUNKS 4 | |
436 | ||
6bbb1370 SG |
437 | #define TFD_CTL_COUNT_SET(n) (n << 24) |
438 | #define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7) | |
439 | #define TFD_CTL_PAD_SET(n) (n << 28) | |
440 | #define TFD_CTL_PAD_GET(ctl) (ctl >> 28) | |
441 | ||
442 | /* Sizes and addresses for instruction and data memory (SRAM) in | |
443 | * 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ | |
444 | #define IL39_RTC_INST_LOWER_BOUND (0x000000) | |
445 | #define IL39_RTC_INST_UPPER_BOUND (0x014000) | |
446 | ||
447 | #define IL39_RTC_DATA_LOWER_BOUND (0x800000) | |
448 | #define IL39_RTC_DATA_UPPER_BOUND (0x808000) | |
449 | ||
450 | #define IL39_RTC_INST_SIZE (IL39_RTC_INST_UPPER_BOUND - \ | |
451 | IL39_RTC_INST_LOWER_BOUND) | |
452 | #define IL39_RTC_DATA_SIZE (IL39_RTC_DATA_UPPER_BOUND - \ | |
453 | IL39_RTC_DATA_LOWER_BOUND) | |
454 | ||
455 | #define IL39_MAX_INST_SIZE IL39_RTC_INST_SIZE | |
456 | #define IL39_MAX_DATA_SIZE IL39_RTC_DATA_SIZE | |
457 | ||
458 | /* Size of uCode instruction memory in bootstrap state machine */ | |
459 | #define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE | |
460 | ||
e7392364 SG |
461 | static inline int |
462 | il3945_hw_valid_rtc_data_addr(u32 addr) | |
6bbb1370 SG |
463 | { |
464 | return (addr >= IL39_RTC_DATA_LOWER_BOUND && | |
465 | addr < IL39_RTC_DATA_UPPER_BOUND); | |
466 | } | |
467 | ||
53143a18 SG |
468 | /* Base physical address of il3945_shared is provided to FH39_TSSR_CBB_BASE |
469 | * and &il3945_shared.rx_read_ptr[0] is provided to FH39_RCSR_RPTR_ADDR(0) */ | |
6bbb1370 SG |
470 | struct il3945_shared { |
471 | __le32 tx_base_ptr[8]; | |
472 | } __packed; | |
473 | ||
6bbb1370 SG |
474 | /************************************/ |
475 | /* iwl3945 Flow Handler Definitions */ | |
476 | /************************************/ | |
477 | ||
478 | /** | |
479 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) | |
480 | * Addresses are offsets from device's PCI hardware base address. | |
481 | */ | |
482 | #define FH39_MEM_LOWER_BOUND (0x0800) | |
483 | #define FH39_MEM_UPPER_BOUND (0x1000) | |
484 | ||
485 | #define FH39_CBCC_TBL (FH39_MEM_LOWER_BOUND + 0x140) | |
486 | #define FH39_TFDB_TBL (FH39_MEM_LOWER_BOUND + 0x180) | |
487 | #define FH39_RCSR_TBL (FH39_MEM_LOWER_BOUND + 0x400) | |
488 | #define FH39_RSSR_TBL (FH39_MEM_LOWER_BOUND + 0x4c0) | |
489 | #define FH39_TCSR_TBL (FH39_MEM_LOWER_BOUND + 0x500) | |
490 | #define FH39_TSSR_TBL (FH39_MEM_LOWER_BOUND + 0x680) | |
491 | ||
492 | /* TFDB (Transmit Frame Buffer Descriptor) */ | |
493 | #define FH39_TFDB(_ch, buf) (FH39_TFDB_TBL + \ | |
494 | ((_ch) * 2 + (buf)) * 0x28) | |
495 | #define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TBL + 0x50 * (_ch)) | |
496 | ||
497 | /* CBCC channel is [0,2] */ | |
498 | #define FH39_CBCC(_ch) (FH39_CBCC_TBL + (_ch) * 0x8) | |
499 | #define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00) | |
500 | #define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04) | |
501 | ||
502 | /* RCSR channel is [0,2] */ | |
503 | #define FH39_RCSR(_ch) (FH39_RCSR_TBL + (_ch) * 0x40) | |
504 | #define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00) | |
505 | #define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04) | |
506 | #define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20) | |
507 | #define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24) | |
508 | ||
509 | #define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0)) | |
510 | ||
511 | /* RSSR */ | |
512 | #define FH39_RSSR_CTRL (FH39_RSSR_TBL + 0x000) | |
513 | #define FH39_RSSR_STATUS (FH39_RSSR_TBL + 0x004) | |
514 | ||
515 | /* TCSR */ | |
516 | #define FH39_TCSR(_ch) (FH39_TCSR_TBL + (_ch) * 0x20) | |
517 | #define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00) | |
518 | #define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04) | |
519 | #define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08) | |
520 | ||
521 | /* TSSR */ | |
522 | #define FH39_TSSR_CBB_BASE (FH39_TSSR_TBL + 0x000) | |
523 | #define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TBL + 0x008) | |
524 | #define FH39_TSSR_TX_STATUS (FH39_TSSR_TBL + 0x010) | |
525 | ||
6bbb1370 SG |
526 | /* DBM */ |
527 | ||
528 | #define FH39_SRVC_CHNL (6) | |
529 | ||
530 | #define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) | |
531 | #define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) | |
532 | ||
533 | #define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) | |
534 | ||
535 | #define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) | |
536 | ||
537 | #define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) | |
538 | ||
539 | #define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) | |
540 | ||
541 | #define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) | |
542 | ||
543 | #define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) | |
544 | ||
545 | #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) | |
546 | #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) | |
547 | ||
548 | #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) | |
549 | #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) | |
550 | ||
551 | #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) | |
552 | ||
553 | #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) | |
554 | ||
555 | #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) | |
556 | #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
557 | ||
558 | #define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) | |
559 | ||
560 | #define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) | |
561 | ||
562 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) | |
563 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) | |
564 | ||
565 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) | |
566 | ||
567 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) | |
568 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) | |
569 | ||
570 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) | |
571 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) | |
572 | ||
573 | #define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24) | |
574 | #define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16) | |
575 | ||
576 | #define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \ | |
577 | (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \ | |
578 | FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch)) | |
579 | ||
580 | #define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) | |
581 | ||
582 | struct il3945_tfd_tb { | |
583 | __le32 addr; | |
584 | __le32 len; | |
585 | } __packed; | |
586 | ||
587 | struct il3945_tfd { | |
588 | __le32 control_flags; | |
589 | struct il3945_tfd_tb tbs[4]; | |
590 | u8 __pad[28]; | |
591 | } __packed; | |
592 | ||
593 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
93b7654e | 594 | extern const struct il_debugfs_ops il3945_debugfs_ops; |
6bbb1370 SG |
595 | #endif |
596 | ||
6bbb1370 | 597 | #endif |