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iwlegacy: remove struct il_tx_info
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlegacy / 3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
be663ab6 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c 29#include <linux/init.h>
5a0e3ad6 30#include <linux/slab.h>
b481de9c
ZY		 31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
d43c36dc 34#include <linux/sched.h>
b481de9c
ZY		 35#include <linux/skbuff.h>
36#include <linux/netdevice.h>
b481de9c 37#include <linux/firmware.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47
ZY		 39#include <asm/unaligned.h>
40#include <net/mac80211.h>
b481de9c 41
e94a4099 42#include "common.h"
6bbb1370 43#include "3945.h"
b481de9c 44
ecce1f09 45/* Send led command */
e7392364
SG		 46static int
47il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd)
ecce1f09
SG		 48{
49 struct il_host_cmd cmd = {
4d69c752 50 .id = C_LEDS,
ecce1f09
SG		 51 .len = sizeof(struct il_led_cmd),
52 .data = led_cmd,
53 .flags = CMD_ASYNC,
54 .callback = NULL,
55 };
56
57 return il_send_cmd(il, &cmd);
58}
59
60const struct il_led_ops il3945_led_ops = {
61 .cmd = il3945_send_led_cmd,
62};
63
e2ebc833 64#define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
2d09b062 65 [RATE_##r##M_IDX] = { RATE_##r##M_PLCP, \
2eb05816 66 RATE_##r##M_IEEE, \
2d09b062
SG		 67 RATE_##ip##M_IDX, \
68 RATE_##in##M_IDX, \
69 RATE_##rp##M_IDX, \
70 RATE_##rn##M_IDX, \
71 RATE_##pp##M_IDX, \
72 RATE_##np##M_IDX, \
3b98c7f4
SG		 73 RATE_##r##M_IDX_TBL, \
74 RATE_##ip##M_IDX_TBL }
b481de9c
ZY		 75
76/*
77 * Parameter order:
78 * rate, prev rate, next rate, prev tgg rate, next tgg rate
79 *
80 * If there isn't a valid next or previous rate then INV is used which
2eb05816 81 * maps to RATE_INVALID
b481de9c
ZY		 82 *
83 */
2eb05816 84const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = {
e7392364
SG		 85 IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
86 IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
87 IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
88 IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
89 IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
90 IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
91 IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
92 IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
93 IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
94 IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
95 IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
96 IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV), /* 54mbps */
b481de9c
ZY		 97};
98
e7392364
SG		 99static inline u8
100il3945_get_prev_ieee_rate(u8 rate_idx)
635b85b4 101{
0c2c8852 102 u8 rate = il3945_rates[rate_idx].prev_ieee;
635b85b4 103
2eb05816 104 if (rate == RATE_INVALID)
0c2c8852 105 rate = rate_idx;
635b85b4
JB		 106 return rate;
107}
108
e2ebc833
SG		 109/* 1 = enable the il3945_disable_events() function */
110#define IL_EVT_DISABLE (0)
111#define IL_EVT_DISABLE_SIZE (1532/32)
b481de9c
ZY		 112
113/**
e2ebc833 114 * il3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 115 *
116 * Disable an event by writing "1"s into "disable"
117 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
118 * Default values of 0 enable uCode events to be logged.
119 * Use for only special debugging. This function is just a placeholder as-is,
120 * you'll need to provide the special bits! ...
e2ebc833 121 * ... and set IL_EVT_DISABLE to 1. */
e7392364
SG		 122void
123il3945_disable_events(struct il_priv *il)
b481de9c 124{
b481de9c
ZY		 125 int i;
126 u32 base; /* SRAM address of event log header */
127 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
128 u32 array_size; /* # of u32 entries in array */
e2ebc833 129 static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = {
b481de9c
ZY		 130 0x00000000, /* 31 - 0 Event id numbers */
131 0x00000000, /* 63 - 32 */
132 0x00000000, /* 95 - 64 */
133 0x00000000, /* 127 - 96 */
134 0x00000000, /* 159 - 128 */
135 0x00000000, /* 191 - 160 */
136 0x00000000, /* 223 - 192 */
137 0x00000000, /* 255 - 224 */
138 0x00000000, /* 287 - 256 */
139 0x00000000, /* 319 - 288 */
140 0x00000000, /* 351 - 320 */
141 0x00000000, /* 383 - 352 */
142 0x00000000, /* 415 - 384 */
143 0x00000000, /* 447 - 416 */
144 0x00000000, /* 479 - 448 */
145 0x00000000, /* 511 - 480 */
146 0x00000000, /* 543 - 512 */
147 0x00000000, /* 575 - 544 */
148 0x00000000, /* 607 - 576 */
149 0x00000000, /* 639 - 608 */
150 0x00000000, /* 671 - 640 */
151 0x00000000, /* 703 - 672 */
152 0x00000000, /* 735 - 704 */
153 0x00000000, /* 767 - 736 */
154 0x00000000, /* 799 - 768 */
155 0x00000000, /* 831 - 800 */
156 0x00000000, /* 863 - 832 */
157 0x00000000, /* 895 - 864 */
158 0x00000000, /* 927 - 896 */
159 0x00000000, /* 959 - 928 */
160 0x00000000, /* 991 - 960 */
161 0x00000000, /* 1023 - 992 */
162 0x00000000, /* 1055 - 1024 */
163 0x00000000, /* 1087 - 1056 */
164 0x00000000, /* 1119 - 1088 */
165 0x00000000, /* 1151 - 1120 */
166 0x00000000, /* 1183 - 1152 */
167 0x00000000, /* 1215 - 1184 */
168 0x00000000, /* 1247 - 1216 */
169 0x00000000, /* 1279 - 1248 */
170 0x00000000, /* 1311 - 1280 */
171 0x00000000, /* 1343 - 1312 */
172 0x00000000, /* 1375 - 1344 */
173 0x00000000, /* 1407 - 1376 */
174 0x00000000, /* 1439 - 1408 */
175 0x00000000, /* 1471 - 1440 */
176 0x00000000, /* 1503 - 1472 */
177 };
178
46bc8d4b 179 base = le32_to_cpu(il->card_alive.log_event_table_ptr);
e2ebc833 180 if (!il3945_hw_valid_rtc_data_addr(base)) {
9406f797 181 IL_ERR("Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 182 return;
183 }
184
46bc8d4b
SG		 185 disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32)));
186 array_size = il_read_targ_mem(il, base + (5 * sizeof(u32)));
b481de9c 187
232913b5 188 if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) {
58de00a4 189 D_INFO("Disabling selected uCode log events at 0x%x\n",
e7392364 190 disable_ptr);
e2ebc833 191 for (i = 0; i < IL_EVT_DISABLE_SIZE; i++)
e7392364
SG		 192 il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)),
193 evt_disable[i]);
b481de9c 194
b481de9c 195 } else {
58de00a4
SG		 196 D_INFO("Selected uCode log events may be disabled\n");
197 D_INFO(" by writing \"1\"s into disable bitmap\n");
e7392364
SG		 198 D_INFO(" in SRAM at 0x%x, size %d u32s\n", disable_ptr,
199 array_size);
b481de9c
ZY		 200 }
201
202}
203
e7392364
SG		 204static int
205il3945_hwrate_to_plcp_idx(u8 plcp)
17744ff6
TW		 206{
207 int idx;
208
2eb05816 209 for (idx = 0; idx < RATE_COUNT_3945; idx++)
e2ebc833 210 if (il3945_rates[idx].plcp == plcp)
17744ff6
TW		 211 return idx;
212 return -1;
213}
214
d3175167 215#ifdef CONFIG_IWLEGACY_DEBUG
04569cbe 216#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
91c066f2 217
e7392364
SG		 218static const char *
219il3945_get_tx_fail_reason(u32 status)
91c066f2
TW		 220{
221 switch (status & TX_STATUS_MSK) {
04569cbe 222 case TX_3945_STATUS_SUCCESS:
91c066f2
TW		 223 return "SUCCESS";
224 TX_STATUS_ENTRY(SHORT_LIMIT);
225 TX_STATUS_ENTRY(LONG_LIMIT);
226 TX_STATUS_ENTRY(FIFO_UNDERRUN);
227 TX_STATUS_ENTRY(MGMNT_ABORT);
228 TX_STATUS_ENTRY(NEXT_FRAG);
229 TX_STATUS_ENTRY(LIFE_EXPIRE);
230 TX_STATUS_ENTRY(DEST_PS);
231 TX_STATUS_ENTRY(ABORTED);
232 TX_STATUS_ENTRY(BT_RETRY);
233 TX_STATUS_ENTRY(STA_INVALID);
234 TX_STATUS_ENTRY(FRAG_DROPPED);
235 TX_STATUS_ENTRY(TID_DISABLE);
236 TX_STATUS_ENTRY(FRAME_FLUSHED);
237 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
238 TX_STATUS_ENTRY(TX_LOCKED);
239 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
240 }
241
242 return "UNKNOWN";
243}
244#else
e7392364
SG		 245static inline const char *
246il3945_get_tx_fail_reason(u32 status)
91c066f2
TW		 247{
248 return "";
249}
250#endif
251
e6a9854b
JB		 252/*
253 * get ieee prev rate from rate scale table.
254 * for A and B mode we need to overright prev
255 * value
256 */
e7392364
SG		 257int
258il3945_rs_next_rate(struct il_priv *il, int rate)
e6a9854b 259{
e2ebc833 260 int next_rate = il3945_get_prev_ieee_rate(rate);
e6a9854b 261
46bc8d4b 262 switch (il->band) {
e6a9854b 263 case IEEE80211_BAND_5GHZ:
2d09b062
SG		 264 if (rate == RATE_12M_IDX)
265 next_rate = RATE_9M_IDX;
266 else if (rate == RATE_6M_IDX)
267 next_rate = RATE_6M_IDX;
e6a9854b 268 break;
7262796a 269 case IEEE80211_BAND_2GHZ:
46bc8d4b 270 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
7c2cde2e 271 il_is_associated(il)) {
2d09b062
SG		 272 if (rate == RATE_11M_IDX)
273 next_rate = RATE_5M_IDX;
7262796a 274 }
e6a9854b 275 break;
7262796a 276
e6a9854b
JB		 277 default:
278 break;
279 }
280
281 return next_rate;
282}
283
91c066f2 284/**
e2ebc833 285 * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
91c066f2 286 *
0c2c8852 287 * When FW advances 'R' idx, all entries between old and new 'R' idx
91c066f2
TW		 288 * need to be reclaimed. As result, some free space forms. If there is
289 * enough free space (> low mark), wake the stack that feeds us.
290 */
e7392364
SG		 291static void
292il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
91c066f2 293{
46bc8d4b 294 struct il_tx_queue *txq = &il->txq[txq_id];
e2ebc833 295 struct il_queue *q = &txq->q;
00ea99e1 296 struct sk_buff *skb;
91c066f2 297
d3175167 298 BUG_ON(txq_id == IL39_CMD_QUEUE_NUM);
91c066f2 299
e7392364
SG		 300 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
301 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
91c066f2 302
00ea99e1
SG		 303 skb = txq->skbs[txq->q.read_ptr];
304 ieee80211_tx_status_irqsafe(il->hw, skb);
305 txq->skbs[txq->q.read_ptr] = NULL;
c39ae9fd 306 il->ops->lib->txq_free_tfd(il, txq);
91c066f2
TW		 307 }
308
232913b5 309 if (il_queue_space(q) > q->low_mark && txq_id >= 0 &&
d3175167 310 txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
46bc8d4b 311 il_wake_queue(il, txq);
91c066f2
TW		 312}
313
314/**
6e9848b4 315 * il3945_hdl_tx - Handle Tx response
91c066f2 316 */
e7392364
SG		 317static void
318il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
91c066f2 319{
dcae1c64 320 struct il_rx_pkt *pkt = rxb_addr(rxb);
91c066f2
TW		 321 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
322 int txq_id = SEQ_TO_QUEUE(sequence);
0c2c8852 323 int idx = SEQ_TO_IDX(sequence);
46bc8d4b 324 struct il_tx_queue *txq = &il->txq[txq_id];
e039fa4a 325 struct ieee80211_tx_info *info;
e2ebc833 326 struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
e7392364 327 u32 status = le32_to_cpu(tx_resp->status);
91c066f2 328 int rate_idx;
74221d07 329 int fail;
91c066f2 330
0c2c8852
SG		 331 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
332 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
e7392364
SG		 333 "is out of range [0-%d] %d %d\n", txq_id, idx,
334 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
91c066f2
TW		 335 return;
336 }
337
22de94de 338 txq->time_stamp = jiffies;
00ea99e1 339 info = IEEE80211_SKB_CB(txq->skbs[txq->q.read_ptr]);
e6a9854b
JB		 340 ieee80211_tx_info_clear_status(info);
341
342 /* Fill the MRR chain with some info about on-chip retransmissions */
e2ebc833 343 rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate);
e6a9854b 344 if (info->band == IEEE80211_BAND_5GHZ)
e2ebc833 345 rate_idx -= IL_FIRST_OFDM_RATE;
e6a9854b
JB		 346
347 fail = tx_resp->failure_frame;
74221d07
AM		 348
349 info->status.rates[0].idx = rate_idx;
e7392364 350 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 351
91c066f2 352 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e7392364
SG		 353 info->flags |=
354 ((status & TX_STATUS_MSK) ==
355 TX_STATUS_SUCCESS) ? IEEE80211_TX_STAT_ACK : 0;
91c066f2 356
e7392364
SG		 357 D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id,
358 il3945_get_tx_fail_reason(status), status, tx_resp->rate,
359 tx_resp->failure_frame);
91c066f2 360
0c2c8852
SG		 361 D_TX_REPLY("Tx queue reclaim %d\n", idx);
362 il3945_tx_queue_reclaim(il, txq_id, idx);
91c066f2 363
a313f383 364 if (status & TX_ABORT_REQUIRED_MSK)
9406f797 365 IL_ERR("TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 366}
367
b481de9c
ZY		 368/*****************************************************************************
369 *
370 * Intel PRO/Wireless 3945ABG/BG Network Connection
371 *
372 * RX handler implementations
373 *
b481de9c 374 *****************************************************************************/
d3175167 375#ifdef CONFIG_IWLEGACY_DEBUGFS
e7392364
SG		 376static void
377il3945_accumulative_stats(struct il_priv *il, __le32 * stats)
17f36fc6
AK		 378{
379 int i;
380 __le32 *prev_stats;
381 u32 *accum_stats;
382 u32 *delta, *max_delta;
383
1722f8e1
SG		 384 prev_stats = (__le32 *) &il->_3945.stats;
385 accum_stats = (u32 *) &il->_3945.accum_stats;
386 delta = (u32 *) &il->_3945.delta_stats;
387 max_delta = (u32 *) &il->_3945.max_delta;
17f36fc6 388
ebf0d90d 389 for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats);
e7392364
SG		 390 i +=
391 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
392 accum_stats++) {
17f36fc6 393 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
e7392364
SG		 394 *delta =
395 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
17f36fc6
AK		 396 *accum_stats += *delta;
397 if (*delta > *max_delta)
398 *max_delta = *delta;
399 }
400 }
401
ebf0d90d
SG		 402 /* reset accumulative stats for "no-counter" type stats */
403 il->_3945.accum_stats.general.temperature =
e7392364 404 il->_3945.stats.general.temperature;
ebf0d90d 405 il->_3945.accum_stats.general.ttl_timestamp =
e7392364 406 il->_3945.stats.general.ttl_timestamp;
17f36fc6
AK		 407}
408#endif
b481de9c 409
e7392364
SG		 410void
411il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
b481de9c 412{
dcae1c64 413 struct il_rx_pkt *pkt = rxb_addr(rxb);
17f36fc6 414
58de00a4 415 D_RX("Statistics notification received (%d vs %d).\n",
e7392364
SG		 416 (int)sizeof(struct il3945_notif_stats),
417 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
d3175167 418#ifdef CONFIG_IWLEGACY_DEBUGFS
1722f8e1 419 il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw);
17f36fc6 420#endif
b481de9c 421
ebf0d90d 422 memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats));
b481de9c
ZY		 423}
424
e7392364
SG		 425void
426il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
17f36fc6 427{
dcae1c64 428 struct il_rx_pkt *pkt = rxb_addr(rxb);
1722f8e1 429 __le32 *flag = (__le32 *) &pkt->u.raw;
17f36fc6 430
db7746f7 431 if (le32_to_cpu(*flag) & UCODE_STATS_CLEAR_MSK) {
d3175167 432#ifdef CONFIG_IWLEGACY_DEBUGFS
ebf0d90d 433 memset(&il->_3945.accum_stats, 0,
e7392364 434 sizeof(struct il3945_notif_stats));
ebf0d90d 435 memset(&il->_3945.delta_stats, 0,
e7392364 436 sizeof(struct il3945_notif_stats));
46bc8d4b 437 memset(&il->_3945.max_delta, 0,
e7392364 438 sizeof(struct il3945_notif_stats));
17f36fc6 439#endif
58de00a4 440 D_RX("Statistics have been cleared\n");
17f36fc6 441 }
d2dfb33e 442 il3945_hdl_stats(il, rxb);
17f36fc6
AK		 443}
444
17744ff6
TW		 445/******************************************************************************
446 *
447 * Misc. internal state and helper functions
448 *
449 ******************************************************************************/
17744ff6 450
ebf0d90d 451/* This is necessary only for a number of stats, see the caller. */
e7392364
SG		 452static int
453il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header)
4bd9b4f3
AG		 454{
455 /* Filter incoming packets to determine if they are targeted toward
456 * this network, discarding packets coming from ourselves */
46bc8d4b 457 switch (il->iw_mode) {
e7392364 458 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3 459 /* packets to our IBSS update information */
46bc8d4b 460 return !compare_ether_addr(header->addr3, il->bssid);
e7392364 461 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3 462 /* packets to our IBSS update information */
46bc8d4b 463 return !compare_ether_addr(header->addr2, il->bssid);
4bd9b4f3
AG		 464 default:
465 return 1;
466 }
467}
17744ff6 468
e7392364
SG		 469static void
470il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb,
471 struct ieee80211_rx_status *stats)
b481de9c 472{
dcae1c64 473 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833
SG		 474 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
475 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
476 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
2f301227
ZY		 477 u16 len = le16_to_cpu(rx_hdr->len);
478 struct sk_buff *skb;
29b1b268 479 __le16 fc = hdr->frame_control;
b481de9c
ZY		 480
481 /* We received data from the HW, so stop the watchdog */
e7392364
SG		 482 if (unlikely
483 (len + IL39_RX_FRAME_SIZE >
484 PAGE_SIZE << il->hw_params.rx_page_order)) {
58de00a4 485 D_DROP("Corruption detected!\n");
b481de9c
ZY		 486 return;
487 }
488
489 /* We only process data packets if the interface is open */
46bc8d4b 490 if (unlikely(!il->is_open)) {
e7392364 491 D_DROP("Dropping packet while interface is not open.\n");
b481de9c
ZY		 492 return;
493 }
b481de9c 494
ecdf94b8 495 skb = dev_alloc_skb(128);
2f301227 496 if (!skb) {
9406f797 497 IL_ERR("dev_alloc_skb failed\n");
2f301227
ZY		 498 return;
499 }
b481de9c 500
e2ebc833 501 if (!il3945_mod_params.sw_crypto)
e7392364
SG		 502 il_set_decrypted_flag(il, (struct ieee80211_hdr *)rxb_addr(rxb),
503 le32_to_cpu(rx_end->status), stats);
b481de9c 504
2f301227
ZY		 505 skb_add_rx_frag(skb, 0, rxb->page,
506 (void *)rx_hdr->payload - (void *)pkt, len);
507
46bc8d4b 508 il_update_stats(il, false, fc, len);
2f301227 509 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
2f301227 510
46bc8d4b
SG		 511 ieee80211_rx(il->hw, skb);
512 il->alloc_rxb_page--;
2f301227 513 rxb->page = NULL;
b481de9c
ZY		 514}
515
e2ebc833 516#define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
7878a5a4 517
e7392364
SG		 518static void
519il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
b481de9c 520{
17744ff6
TW		 521 struct ieee80211_hdr *header;
522 struct ieee80211_rx_status rx_status;
dcae1c64 523 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833
SG		 524 struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt);
525 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
526 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
f875f518 527 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
e7392364
SG		 528 u16 rx_stats_noise_diff __maybe_unused =
529 le16_to_cpu(rx_stats->noise_diff);
b481de9c 530 u8 network_packet;
17744ff6 531
17744ff6
TW		 532 rx_status.flag = 0;
533 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
e7392364
SG		 534 rx_status.band =
535 (rx_hdr->
536 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
537 IEEE80211_BAND_5GHZ;
59eb21a6 538 rx_status.freq =
e7392364
SG		 539 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
540 rx_status.band);
17744ff6 541
e2ebc833 542 rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6 543 if (rx_status.band == IEEE80211_BAND_5GHZ)
e2ebc833 544 rx_status.rate_idx -= IL_FIRST_OFDM_RATE;
b481de9c 545
e7392364
SG		 546 rx_status.antenna =
547 (le16_to_cpu(rx_hdr->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
548 4;
6f0a2c4d
BR		 549
550 /* set the preamble flag if appropriate */
551 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
552 rx_status.flag |= RX_FLAG_SHORTPRE;
553
b481de9c 554 if ((unlikely(rx_stats->phy_count > 20))) {
58de00a4 555 D_DROP("dsp size out of range [0,20]: %d/n",
e7392364 556 rx_stats->phy_count);
b481de9c
ZY		 557 return;
558 }
559
232913b5
SG		 560 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) ||
561 !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
58de00a4 562 D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 563 return;
564 }
565
b481de9c 566 /* Convert 3945's rssi indicator to dBm */
d3175167 567 rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET;
b481de9c 568
e7392364
SG		 569 D_STATS("Rssi %d sig_avg %d noise_diff %d\n", rx_status.signal,
570 rx_stats_sig_avg, rx_stats_noise_diff);
b481de9c 571
e2ebc833 572 header = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
b481de9c 573
46bc8d4b 574 network_packet = il3945_is_network_packet(il, header);
b481de9c 575
58de00a4 576 D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
e7392364
SG		 577 network_packet ? '*' : ' ', le16_to_cpu(rx_hdr->channel),
578 rx_status.signal, rx_status.signal, rx_status.rate_idx);
b481de9c 579
e7392364 580 il_dbg_log_rx_data_frame(il, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 581
582 if (network_packet) {
46bc8d4b 583 il->_3945.last_beacon_time =
e7392364 584 le32_to_cpu(rx_end->beacon_timestamp);
46bc8d4b
SG		 585 il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
586 il->_3945.last_rx_rssi = rx_status.signal;
b481de9c
ZY		 587 }
588
46bc8d4b 589 il3945_pass_packet_to_mac80211(il, rxb, &rx_status);
b481de9c
ZY		 590}
591
e7392364
SG		 592int
593il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
594 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 595{
596 int count;
e2ebc833
SG		 597 struct il_queue *q;
598 struct il3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 599
600 q = &txq->q;
e2ebc833 601 tfd_tmp = (struct il3945_tfd *)txq->tfds;
59606ffa 602 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 603
604 if (reset)
605 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 606
607 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 608
232913b5 609 if (count >= NUM_TFD_CHUNKS || count < 0) {
9406f797 610 IL_ERR("Error can not send more than %d chunks\n",
e7392364 611 NUM_TFD_CHUNKS);
b481de9c
ZY		 612 return -EINVAL;
613 }
614
dbb6654c
WT		 615 tfd->tbs[count].addr = cpu_to_le32(addr);
616 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 617
618 count++;
619
e7392364
SG		 620 tfd->control_flags =
621 cpu_to_le32(TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad));
b481de9c
ZY		 622
623 return 0;
624}
625
626/**
0c2c8852 627 * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr]
b481de9c 628 *
0c2c8852 629 * Does NOT advance any idxes
b481de9c 630 */
e7392364
SG		 631void
632il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
b481de9c 633{
e2ebc833 634 struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds;
0c2c8852
SG		 635 int idx = txq->q.read_ptr;
636 struct il3945_tfd *tfd = &tfd_tmp[idx];
46bc8d4b 637 struct pci_dev *dev = il->pci_dev;
b481de9c
ZY		 638 int i;
639 int counter;
640
b481de9c 641 /* sanity check */
dbb6654c 642 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 643 if (counter > NUM_TFD_CHUNKS) {
9406f797 644 IL_ERR("Too many chunks: %i\n", counter);
b481de9c 645 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 646 return;
b481de9c
ZY		 647 }
648
fd9377ee
RC		 649 /* Unmap tx_cmd */
650 if (counter)
e7392364
SG		 651 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
652 dma_unmap_len(&txq->meta[idx], len),
653 PCI_DMA_TODEVICE);
fd9377ee 654
b481de9c
ZY		 655 /* unmap chunks if any */
656
ff0d91c3 657 for (i = 1; i < counter; i++)
dbb6654c 658 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
e7392364
SG		 659 le32_to_cpu(tfd->tbs[i].len),
660 PCI_DMA_TODEVICE);
4f5fa237 661
ff0d91c3 662 /* free SKB */
00ea99e1
SG		 663 if (txq->skbs) {
664 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
ff0d91c3
JB		 665
666 /* can be called from irqs-disabled context */
667 if (skb) {
668 dev_kfree_skb_any(skb);
00ea99e1 669 txq->skbs[txq->q.read_ptr] = NULL;
b481de9c
ZY		 670 }
671 }
b481de9c
ZY		 672}
673
b481de9c 674/**
e2ebc833 675 * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 676 *
677*/
e7392364
SG		 678void
679il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
680 struct ieee80211_tx_info *info,
81fb4613 681 struct ieee80211_hdr *hdr, int sta_id)
b481de9c 682{
46bc8d4b 683 u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value;
d71be937 684 u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945 - 1);
b481de9c
ZY		 685 u16 rate_mask;
686 int rate;
81fb4613 687 const u8 rts_retry_limit = 7;
b481de9c
ZY		 688 u8 data_retry_limit;
689 __le32 tx_flags;
fd7c8a40 690 __le16 fc = hdr->frame_control;
e2ebc833 691 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
b481de9c 692
0c2c8852 693 rate = il3945_rates[rate_idx].plcp;
9744c91f 694 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 695
696 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 697 * in this running context */
2eb05816 698 rate_mask = RATES_MASK_3945;
768db982 699
e7392364 700 /* Set retry limit on DATA packets and Probe Responses */
768db982
AK		 701 if (ieee80211_is_probe_resp(fc))
702 data_retry_limit = 3;
703 else
e2ebc833 704 data_retry_limit = IL_DEFAULT_TX_RETRY;
768db982 705 tx_cmd->data_retry_limit = data_retry_limit;
81fb4613
SG		 706 /* Set retry limit on RTS packets */
707 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
b481de9c 708
9744c91f
AK		 709 tx_cmd->rate = rate;
710 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 711
712 /* OFDM */
9744c91f 713 tx_cmd->supp_rates[0] =
e7392364 714 ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 715
716 /* CCK */
9744c91f 717 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 718
58de00a4 719 D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
e7392364
SG		 720 "cck/ofdm mask: 0x%x/0x%x\n", sta_id, tx_cmd->rate,
721 le32_to_cpu(tx_cmd->tx_flags), tx_cmd->supp_rates[1],
722 tx_cmd->supp_rates[0]);
b481de9c
ZY		 723}
724
e7392364
SG		 725static u8
726il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate)
b481de9c
ZY		 727{
728 unsigned long flags_spin;
e2ebc833 729 struct il_station_entry *station;
b481de9c 730
e2ebc833
SG		 731 if (sta_id == IL_INVALID_STATION)
732 return IL_INVALID_STATION;
b481de9c 733
46bc8d4b
SG		 734 spin_lock_irqsave(&il->sta_lock, flags_spin);
735 station = &il->stations[sta_id];
b481de9c
ZY		 736
737 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
738 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c 739 station->sta.mode = STA_CONTROL_MODIFY_MSK;
46bc8d4b
SG		 740 il_send_add_sta(il, &station->sta, CMD_ASYNC);
741 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
b481de9c 742
e7392364 743 D_RATE("SCALE sync station %d to rate %d\n", sta_id, tx_rate);
b481de9c
ZY		 744 return sta_id;
745}
746
e7392364
SG		 747static void
748il3945_set_pwr_vmain(struct il_priv *il)
b481de9c 749{
9597ebac
JB		 750/*
751 * (for documentation purposes)
752 * to set power to V_AUX, do
753
46bc8d4b
SG		 754 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) {
755 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
b481de9c
ZY		 756 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
757 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 758
142b343f 759 _il_poll_bit(il, CSR_GPIO_IN,
b481de9c
ZY		 760 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
761 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 762 }
9597ebac 763 */
b481de9c 764
46bc8d4b 765 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
e7392364
SG		 766 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
767 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 768
1722f8e1
SG		 769 _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
770 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
b481de9c
ZY		 771}
772
e7392364
SG		 773static int
774il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
b481de9c 775{
0c1a94e2 776 il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
e7392364 777 il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
0c1a94e2
SG		 778 il_wr(il, FH39_RCSR_WPTR(0), 0);
779 il_wr(il, FH39_RCSR_CONFIG(0),
e7392364
SG		 780 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
781 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
782 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
783 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | (RX_QUEUE_SIZE_LOG
784 <<
785 FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE)
786 | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | (1 <<
787 FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH)
788 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 789
790 /* fake read to flush all prev I/O */
0c1a94e2 791 il_rd(il, FH39_RSSR_CTRL);
b481de9c 792
b481de9c
ZY		 793 return 0;
794}
795
e7392364
SG		 796static int
797il3945_tx_reset(struct il_priv *il)
b481de9c 798{
b481de9c
ZY		 799
800 /* bypass mode */
db54eb57 801 il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 802
803 /* RA 0 is active */
db54eb57 804 il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 805
806 /* all 6 fifo are active */
db54eb57 807 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 808
db54eb57
SG		 809 il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
810 il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
811 il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
812 il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 813
e7392364 814 il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys);
b481de9c 815
0c1a94e2 816 il_wr(il, FH39_TSSR_MSG_CONFIG,
e7392364
SG		 817 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
818 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
819 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
820 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
821 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
822 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
823 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c
ZY		 824
825 return 0;
826}
827
828/**
e2ebc833 829 * il3945_txq_ctx_reset - Reset TX queue context
b481de9c
ZY		 830 *
831 * Destroys all DMA structures and initialize them again
832 */
e7392364
SG		 833static int
834il3945_txq_ctx_reset(struct il_priv *il)
b481de9c
ZY		 835{
836 int rc;
837 int txq_id, slots_num;
838
46bc8d4b 839 il3945_hw_txq_ctx_free(il);
b481de9c 840
88804e2b 841 /* allocate tx queue structure */
46bc8d4b 842 rc = il_alloc_txq_mem(il);
88804e2b
WYG		 843 if (rc)
844 return rc;
845
b481de9c 846 /* Tx CMD queue */
46bc8d4b 847 rc = il3945_tx_reset(il);
b481de9c
ZY		 848 if (rc)
849 goto error;
850
851 /* Tx queue(s) */
46bc8d4b 852 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
e7392364
SG		 853 slots_num =
854 (txq_id ==
855 IL39_CMD_QUEUE_NUM) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
856 rc = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id);
b481de9c 857 if (rc) {
9406f797 858 IL_ERR("Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 859 goto error;
860 }
861 }
862
863 return rc;
864
e7392364 865error:
46bc8d4b 866 il3945_hw_txq_ctx_free(il);
b481de9c
ZY		 867 return rc;
868}
869
f33269b8 870/*
fadb3582 871 * Start up 3945's basic functionality after it has been reset
e2ebc833 872 * (e.g. after platform boot, or shutdown via il_apm_stop())
f33269b8
BC		 873 * NOTE: This does not load uCode nor start the embedded processor
874 */
e7392364
SG		 875static int
876il3945_apm_init(struct il_priv *il)
b481de9c 877{
46bc8d4b 878 int ret = il_apm_init(il);
01ec616d 879
f33269b8 880 /* Clear APMG (NIC's internal power management) interrupts */
db54eb57
SG		 881 il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
882 il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
f33269b8
BC		 883
884 /* Reset radio chip */
e7392364 885 il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
f33269b8 886 udelay(5);
e7392364 887 il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
f33269b8 888
01ec616d
KA		 889 return ret;
890}
b481de9c 891
e7392364
SG		 892static void
893il3945_nic_config(struct il_priv *il)
01ec616d 894{
46bc8d4b 895 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
01ec616d 896 unsigned long flags;
46bc8d4b 897 u8 rev_id = il->pci_dev->revision;
b481de9c 898
46bc8d4b 899 spin_lock_irqsave(&il->lock, flags);
b481de9c 900
43121432 901 /* Determine HW type */
58de00a4 902 D_INFO("HW Revision ID = 0x%X\n", rev_id);
43121432 903
b481de9c 904 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
58de00a4 905 D_INFO("RTP type\n");
b481de9c 906 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
58de00a4 907 D_INFO("3945 RADIO-MB type\n");
46bc8d4b 908 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 909 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 910 } else {
58de00a4 911 D_INFO("3945 RADIO-MM type\n");
46bc8d4b 912 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 913 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 914 }
915
e6148917 916 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
58de00a4 917 D_INFO("SKU OP mode is mrc\n");
46bc8d4b 918 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 919 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 920 } else
58de00a4 921 D_INFO("SKU OP mode is basic\n");
b481de9c 922
e6148917 923 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e7392364 924 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
46bc8d4b 925 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 926 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 927 } else {
e7392364 928 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
46bc8d4b 929 il_clear_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 930 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 931 }
932
e6148917 933 if (eeprom->almgor_m_version <= 1) {
46bc8d4b 934 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 935 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
58de00a4 936 D_INFO("Card M type A version is 0x%X\n",
e7392364 937 eeprom->almgor_m_version);
b481de9c 938 } else {
58de00a4 939 D_INFO("Card M type B version is 0x%X\n",
e7392364 940 eeprom->almgor_m_version);
46bc8d4b 941 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 942 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c 943 }
46bc8d4b 944 spin_unlock_irqrestore(&il->lock, flags);
b481de9c 945
e6148917 946 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
58de00a4 947 D_RF_KILL("SW RF KILL supported in EEPROM.\n");
b481de9c 948
e6148917 949 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
58de00a4 950 D_RF_KILL("HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 951}
952
e7392364
SG		 953int
954il3945_hw_nic_init(struct il_priv *il)
01ec616d 955{
01ec616d
KA		 956 int rc;
957 unsigned long flags;
46bc8d4b 958 struct il_rx_queue *rxq = &il->rxq;
01ec616d 959
46bc8d4b 960 spin_lock_irqsave(&il->lock, flags);
c39ae9fd 961 il->ops->lib->apm_ops.init(il);
46bc8d4b 962 spin_unlock_irqrestore(&il->lock, flags);
01ec616d 963
46bc8d4b 964 il3945_set_pwr_vmain(il);
854682ed 965
c39ae9fd 966 il->ops->lib->apm_ops.config(il);
b481de9c
ZY		 967
968 /* Allocate the RX queue, or reset if it is already allocated */
969 if (!rxq->bd) {
46bc8d4b 970 rc = il_rx_queue_alloc(il);
b481de9c 971 if (rc) {
9406f797 972 IL_ERR("Unable to initialize Rx queue\n");
b481de9c
ZY		 973 return -ENOMEM;
974 }
975 } else
46bc8d4b 976 il3945_rx_queue_reset(il, rxq);
b481de9c 977
46bc8d4b 978 il3945_rx_replenish(il);
b481de9c 979
46bc8d4b 980 il3945_rx_init(il, rxq);
b481de9c 981
b481de9c 982 /* Look at using this instead:
e7392364
SG		 983 rxq->need_update = 1;
984 il_rx_queue_update_write_ptr(il, rxq);
985 */
b481de9c 986
0c1a94e2 987 il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c 988
46bc8d4b 989 rc = il3945_txq_ctx_reset(il);
b481de9c
ZY		 990 if (rc)
991 return rc;
992
a6766ccd 993 set_bit(S_INIT, &il->status);
b481de9c
ZY		 994
995 return 0;
996}
997
998/**
e2ebc833 999 * il3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1000 *
1001 * Destroy all TX DMA queues and structures
1002 */
e7392364
SG		 1003void
1004il3945_hw_txq_ctx_free(struct il_priv *il)
b481de9c
ZY		 1005{
1006 int txq_id;
1007
1008 /* Tx queues */
46bc8d4b 1009 if (il->txq)
e7392364 1010 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
d3175167 1011 if (txq_id == IL39_CMD_QUEUE_NUM)
46bc8d4b 1012 il_cmd_queue_free(il);
88804e2b 1013 else
46bc8d4b 1014 il_tx_queue_free(il, txq_id);
3e5d238f 1015
88804e2b 1016 /* free tx queue structure */
46bc8d4b 1017 il_txq_mem(il);
b481de9c
ZY		 1018}
1019
e7392364
SG		 1020void
1021il3945_hw_txq_ctx_stop(struct il_priv *il)
b481de9c 1022{
bddadf86 1023 int txq_id;
b481de9c
ZY		 1024
1025 /* stop SCD */
db54eb57
SG		 1026 il_wr_prph(il, ALM_SCD_MODE_REG, 0);
1027 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1028
1029 /* reset TFD queues */
46bc8d4b 1030 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
0c1a94e2
SG		 1031 il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
1032 il_poll_bit(il, FH39_TSSR_TX_STATUS,
e7392364
SG		 1033 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1034 1000);
b481de9c
ZY		 1035 }
1036
46bc8d4b 1037 il3945_hw_txq_ctx_free(il);
b481de9c
ZY		 1038}
1039
b481de9c 1040/**
e2ebc833 1041 * il3945_hw_reg_adjust_power_by_temp
0c2c8852 1042 * return idx delta into power gain settings table
bbc5807b 1043*/
e7392364
SG		 1044static int
1045il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1046{
1047 return (new_reading - old_reading) * (-11) / 100;
1048}
1049
1050/**
e2ebc833 1051 * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1052 */
e7392364
SG		 1053static inline int
1054il3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1055{
232913b5 1056 return (temperature < -260 || temperature > 25) ? 1 : 0;
b481de9c
ZY		 1057}
1058
e7392364
SG		 1059int
1060il3945_hw_get_temperature(struct il_priv *il)
b481de9c 1061{
841b2cca 1062 return _il_rd(il, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1063}
1064
1065/**
e2ebc833 1066 * il3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1067 * get the current temperature by reading from NIC
1068*/
e7392364
SG		 1069static int
1070il3945_hw_reg_txpower_get_temperature(struct il_priv *il)
b481de9c 1071{
46bc8d4b 1072 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
b481de9c
ZY		 1073 int temperature;
1074
46bc8d4b 1075 temperature = il3945_hw_get_temperature(il);
b481de9c
ZY		 1076
1077 /* driver's okay range is -260 to +25.
1078 * human readable okay range is 0 to +285 */
58de00a4 1079 D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT);
b481de9c
ZY		 1080
1081 /* handle insane temp reading */
e2ebc833 1082 if (il3945_hw_reg_temp_out_of_range(temperature)) {
9406f797 1083 IL_ERR("Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1084
1085 /* if really really hot(?),
1086 * substitute the 3rd band/group's temp measured at factory */
46bc8d4b 1087 if (il->last_temperature > 100)
e6148917 1088 temperature = eeprom->groups[2].temperature;
e7392364 1089 else /* else use most recent "sane" value from driver */
46bc8d4b 1090 temperature = il->last_temperature;
b481de9c
ZY		 1091 }
1092
1093 return temperature; /* raw, not "human readable" */
1094}
1095
1096/* Adjust Txpower only if temperature variance is greater than threshold.
1097 *
1098 * Both are lower than older versions' 9 degrees */
e2ebc833 1099#define IL_TEMPERATURE_LIMIT_TIMER 6
b481de9c
ZY		 1100
1101/**
e2ebc833 1102 * il3945_is_temp_calib_needed - determines if new calibration is needed
b481de9c
ZY		 1103 *
1104 * records new temperature in tx_mgr->temperature.
1105 * replaces tx_mgr->last_temperature *only* if calib needed
1106 * (assumes caller will actually do the calibration!). */
e7392364
SG		 1107static int
1108il3945_is_temp_calib_needed(struct il_priv *il)
b481de9c
ZY		 1109{
1110 int temp_diff;
1111
46bc8d4b
SG		 1112 il->temperature = il3945_hw_reg_txpower_get_temperature(il);
1113 temp_diff = il->temperature - il->last_temperature;
b481de9c
ZY		 1114
1115 /* get absolute value */
1116 if (temp_diff < 0) {
58de00a4 1117 D_POWER("Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1118 temp_diff = -temp_diff;
1119 } else if (temp_diff == 0)
58de00a4 1120 D_POWER("Same temp,\n");
b481de9c 1121 else
58de00a4 1122 D_POWER("Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1123
1124 /* if we don't need calibration, *don't* update last_temperature */
e2ebc833 1125 if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) {
58de00a4 1126 D_POWER("Timed thermal calib not needed\n");
b481de9c
ZY		 1127 return 0;
1128 }
1129
58de00a4 1130 D_POWER("Timed thermal calib needed\n");
b481de9c
ZY		 1131
1132 /* assume that caller will actually do calib ...
1133 * update the "last temperature" value */
46bc8d4b 1134 il->last_temperature = il->temperature;
b481de9c
ZY		 1135 return 1;
1136}
1137
e2ebc833
SG		 1138#define IL_MAX_GAIN_ENTRIES 78
1139#define IL_CCK_FROM_OFDM_POWER_DIFF -5
2d09b062 1140#define IL_CCK_FROM_OFDM_IDX_DIFF (10)
b481de9c
ZY		 1141
1142/* radio and DSP power table, each step is 1/2 dB.
1143 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
e2ebc833 1144static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1145 {
1146 {251, 127}, /* 2.4 GHz, highest power */
1147 {251, 127},
1148 {251, 127},
1149 {251, 127},
1150 {251, 125},
1151 {251, 110},
1152 {251, 105},
1153 {251, 98},
1154 {187, 125},
1155 {187, 115},
1156 {187, 108},
1157 {187, 99},
1158 {243, 119},
1159 {243, 111},
1160 {243, 105},
1161 {243, 97},
1162 {243, 92},
1163 {211, 106},
1164 {211, 100},
1165 {179, 120},
1166 {179, 113},
1167 {179, 107},
1168 {147, 125},
1169 {147, 119},
1170 {147, 112},
1171 {147, 106},
1172 {147, 101},
1173 {147, 97},
1174 {147, 91},
1175 {115, 107},
1176 {235, 121},
1177 {235, 115},
1178 {235, 109},
1179 {203, 127},
1180 {203, 121},
1181 {203, 115},
1182 {203, 108},
1183 {203, 102},
1184 {203, 96},
1185 {203, 92},
1186 {171, 110},
1187 {171, 104},
1188 {171, 98},
1189 {139, 116},
1190 {227, 125},
1191 {227, 119},
1192 {227, 113},
1193 {227, 107},
1194 {227, 101},
1195 {227, 96},
1196 {195, 113},
1197 {195, 106},
1198 {195, 102},
1199 {195, 95},
1200 {163, 113},
1201 {163, 106},
1202 {163, 102},
1203 {163, 95},
1204 {131, 113},
1205 {131, 106},
1206 {131, 102},
1207 {131, 95},
1208 {99, 113},
1209 {99, 106},
1210 {99, 102},
1211 {99, 95},
1212 {67, 113},
1213 {67, 106},
1214 {67, 102},
1215 {67, 95},
1216 {35, 113},
1217 {35, 106},
1218 {35, 102},
1219 {35, 95},
1220 {3, 113},
1221 {3, 106},
1222 {3, 102},
1722f8e1
SG		 1223 {3, 95} /* 2.4 GHz, lowest power */
1224 },
b481de9c
ZY		 1225 {
1226 {251, 127}, /* 5.x GHz, highest power */
1227 {251, 120},
1228 {251, 114},
1229 {219, 119},
1230 {219, 101},
1231 {187, 113},
1232 {187, 102},
1233 {155, 114},
1234 {155, 103},
1235 {123, 117},
1236 {123, 107},
1237 {123, 99},
1238 {123, 92},
1239 {91, 108},
1240 {59, 125},
1241 {59, 118},
1242 {59, 109},
1243 {59, 102},
1244 {59, 96},
1245 {59, 90},
1246 {27, 104},
1247 {27, 98},
1248 {27, 92},
1249 {115, 118},
1250 {115, 111},
1251 {115, 104},
1252 {83, 126},
1253 {83, 121},
1254 {83, 113},
1255 {83, 105},
1256 {83, 99},
1257 {51, 118},
1258 {51, 111},
1259 {51, 104},
1260 {51, 98},
1261 {19, 116},
1262 {19, 109},
1263 {19, 102},
1264 {19, 98},
1265 {19, 93},
1266 {171, 113},
1267 {171, 107},
1268 {171, 99},
1269 {139, 120},
1270 {139, 113},
1271 {139, 107},
1272 {139, 99},
1273 {107, 120},
1274 {107, 113},
1275 {107, 107},
1276 {107, 99},
1277 {75, 120},
1278 {75, 113},
1279 {75, 107},
1280 {75, 99},
1281 {43, 120},
1282 {43, 113},
1283 {43, 107},
1284 {43, 99},
1285 {11, 120},
1286 {11, 113},
1287 {11, 107},
1288 {11, 99},
1289 {131, 107},
1290 {131, 99},
1291 {99, 120},
1292 {99, 113},
1293 {99, 107},
1294 {99, 99},
1295 {67, 120},
1296 {67, 113},
1297 {67, 107},
1298 {67, 99},
1299 {35, 120},
1300 {35, 113},
1301 {35, 107},
1302 {35, 99},
1722f8e1
SG		 1303 {3, 120} /* 5.x GHz, lowest power */
1304 }
b481de9c
ZY		 1305};
1306
e7392364
SG		 1307static inline u8
1308il3945_hw_reg_fix_power_idx(int idx)
b481de9c 1309{
0c2c8852 1310 if (idx < 0)
b481de9c 1311 return 0;
0c2c8852 1312 if (idx >= IL_MAX_GAIN_ENTRIES)
e2ebc833 1313 return IL_MAX_GAIN_ENTRIES - 1;
0c2c8852 1314 return (u8) idx;
b481de9c
ZY		 1315}
1316
1317/* Kick off thermal recalibration check every 60 seconds */
1318#define REG_RECALIB_PERIOD (60)
1319
1320/**
e2ebc833 1321 * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1322 *
1323 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1324 * or 6 Mbit (OFDM) rates.
1325 */
e7392364
SG		 1326static void
1327il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx,
1722f8e1 1328 const s8 *clip_pwrs,
e7392364 1329 struct il_channel_info *ch_info, int band_idx)
b481de9c 1330{
e2ebc833 1331 struct il3945_scan_power_info *scan_power_info;
b481de9c 1332 s8 power;
0c2c8852 1333 u8 power_idx;
b481de9c 1334
0c2c8852 1335 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx];
b481de9c
ZY		 1336
1337 /* use this channel group's 6Mbit clipping/saturation pwr,
1338 * but cap at regulatory scan power restriction (set during init
1339 * based on eeprom channel data) for this channel. */
3b98c7f4 1340 power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]);
b481de9c 1341
46bc8d4b 1342 power = min(power, il->tx_power_user_lmt);
b481de9c
ZY		 1343 scan_power_info->requested_power = power;
1344
1345 /* find difference between new scan *power* and current "normal"
1346 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
0c2c8852 1347 * current "normal" temperature-compensated Tx power *idx* for
b481de9c 1348 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
0c2c8852 1349 * *idx*. */
e7392364
SG		 1350 power_idx =
1351 ch_info->power_info[rate_idx].power_table_idx - (power -
1352 ch_info->
1353 power_info
1354 [RATE_6M_IDX_TBL].
1355 requested_power) *
1356 2;
b481de9c 1357
0c2c8852 1358 /* store reference idx that we use when adjusting *all* scan
b481de9c
ZY		 1359 * powers. So we can accommodate user (all channel) or spectrum
1360 * management (single channel) power changes "between" temperature
1361 * feedback compensation procedures.
0c2c8852 1362 * don't force fit this reference idx into gain table; it may be a
b481de9c
ZY		 1363 * negative number. This will help avoid errors when we're at
1364 * the lower bounds (highest gains, for warmest temperatures)
1365 * of the table. */
1366
1367 /* don't exceed table bounds for "real" setting */
0c2c8852 1368 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
b481de9c 1369
0c2c8852 1370 scan_power_info->power_table_idx = power_idx;
b481de9c 1371 scan_power_info->tpc.tx_gain =
0c2c8852 1372 power_gain_table[band_idx][power_idx].tx_gain;
b481de9c 1373 scan_power_info->tpc.dsp_atten =
0c2c8852 1374 power_gain_table[band_idx][power_idx].dsp_atten;
b481de9c
ZY		 1375}
1376
1377/**
e2ebc833 1378 * il3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1379 *
1380 * Configures power settings for all rates for the current channel,
1381 * using values from channel info struct, and send to NIC
1382 */
e7392364
SG		 1383static int
1384il3945_send_tx_power(struct il_priv *il)
b481de9c 1385{
14577f23 1386 int rate_idx, i;
e2ebc833
SG		 1387 const struct il_channel_info *ch_info = NULL;
1388 struct il3945_txpowertable_cmd txpower = {
c8b03958 1389 .channel = il->active.channel,
b481de9c 1390 };
246ed355
JB		 1391 u16 chan;
1392
e7392364
SG		 1393 if (WARN_ONCE
1394 (test_bit(S_SCAN_HW, &il->status),
1395 "TX Power requested while scanning!\n"))
4beeba7d
SG		 1396 return -EAGAIN;
1397
c8b03958 1398 chan = le16_to_cpu(il->active.channel);
b481de9c 1399
46bc8d4b
SG		 1400 txpower.band = (il->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1401 ch_info = il_get_channel_info(il, il->band, chan);
b481de9c 1402 if (!ch_info) {
e7392364
SG		 1403 IL_ERR("Failed to get channel info for channel %d [%d]\n", chan,
1404 il->band);
b481de9c
ZY		 1405 return -EINVAL;
1406 }
1407
e2ebc833 1408 if (!il_is_channel_valid(ch_info)) {
e7392364 1409 D_POWER("Not calling TX_PWR_TBL_CMD on " "non-Tx channel.\n");
b481de9c
ZY		 1410 return 0;
1411 }
1412
1413 /* fill cmd with power settings for all rates for current channel */
14577f23 1414 /* Fill OFDM rate */
e2ebc833 1415 for (rate_idx = IL_FIRST_OFDM_RATE, i = 0;
d3175167 1416 rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1417
1418 txpower.power[i].tpc = ch_info->power_info[i].tpc;
e2ebc833 1419 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
b481de9c 1420
58de00a4 1421 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
e7392364
SG		 1422 le16_to_cpu(txpower.channel), txpower.band,
1423 txpower.power[i].tpc.tx_gain,
1424 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
14577f23
MA		 1425 }
1426 /* Fill CCK rates */
e7392364
SG		 1427 for (rate_idx = IL_FIRST_CCK_RATE; rate_idx <= IL_LAST_CCK_RATE;
1428 rate_idx++, i++) {
14577f23 1429 txpower.power[i].tpc = ch_info->power_info[i].tpc;
e2ebc833 1430 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
14577f23 1431
58de00a4 1432 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
e7392364
SG		 1433 le16_to_cpu(txpower.channel), txpower.band,
1434 txpower.power[i].tpc.tx_gain,
1435 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
b481de9c
ZY		 1436 }
1437
4d69c752 1438 return il_send_cmd_pdu(il, C_TX_PWR_TBL,
e7392364
SG		 1439 sizeof(struct il3945_txpowertable_cmd),
1440 &txpower);
b481de9c
ZY		 1441
1442}
1443
1444/**
e2ebc833 1445 * il3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1446 * @ch_info: Channel to update. Uses power_info.requested_power.
1447 *
0c2c8852 1448 * Replace requested_power and base_power_idx ch_info fields for
b481de9c
ZY		 1449 * one channel.
1450 *
1451 * Called if user or spectrum management changes power preferences.
1452 * Takes into account h/w and modulation limitations (clip power).
1453 *
1454 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1455 *
1456 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1457 * properly fill out the scan powers, and actual h/w gain settings,
1458 * and send changes to NIC
1459 */
e7392364
SG		 1460static int
1461il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info)
b481de9c 1462{
e2ebc833 1463 struct il3945_channel_power_info *power_info;
b481de9c
ZY		 1464 int power_changed = 0;
1465 int i;
1466 const s8 *clip_pwrs;
1467 int power;
1468
1469 /* Get this chnlgrp's rate-to-max/clip-powers table */
0c2c8852 1470 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
b481de9c
ZY		 1471
1472 /* Get this channel's rate-to-current-power settings table */
1473 power_info = ch_info->power_info;
1474
1475 /* update OFDM Txpower settings */
e7392364 1476 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++, ++power_info) {
b481de9c
ZY		 1477 int delta_idx;
1478
1479 /* limit new power to be no more than h/w capability */
1480 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1481 if (power == power_info->requested_power)
1482 continue;
1483
1484 /* find difference between old and new requested powers,
0c2c8852 1485 * update base (non-temp-compensated) power idx */
b481de9c 1486 delta_idx = (power - power_info->requested_power) * 2;
0c2c8852 1487 power_info->base_power_idx -= delta_idx;
b481de9c
ZY		 1488
1489 /* save new requested power value */
1490 power_info->requested_power = power;
1491
1492 power_changed = 1;
1493 }
1494
1495 /* update CCK Txpower settings, based on OFDM 12M setting ...
1496 * ... all CCK power settings for a given channel are the *same*. */
1497 if (power_changed) {
1498 power =
e7392364
SG		 1499 ch_info->power_info[RATE_12M_IDX_TBL].requested_power +
1500 IL_CCK_FROM_OFDM_POWER_DIFF;
b481de9c 1501
e2ebc833 1502 /* do all CCK rates' il3945_channel_power_info structures */
3b98c7f4 1503 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) {
b481de9c 1504 power_info->requested_power = power;
0c2c8852 1505 power_info->base_power_idx =
3b98c7f4 1506 ch_info->power_info[RATE_12M_IDX_TBL].
0c2c8852 1507 base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
b481de9c
ZY		 1508 ++power_info;
1509 }
1510 }
1511
1512 return 0;
1513}
1514
1515/**
e2ebc833 1516 * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1517 *
1518 * NOTE: Returned power limit may be less (but not more) than requested,
1519 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1520 * (no consideration for h/w clipping limitations).
1521 */
e7392364
SG		 1522static int
1523il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info)
b481de9c
ZY		 1524{
1525 s8 max_power;
1526
1527#if 0
1528 /* if we're using TGd limits, use lower of TGd or EEPROM */
1529 if (ch_info->tgd_data.max_power != 0)
e7392364
SG		 1530 max_power =
1531 min(ch_info->tgd_data.max_power,
1532 ch_info->eeprom.max_power_avg);
b481de9c
ZY		 1533
1534 /* else just use EEPROM limits */
1535 else
1536#endif
1537 max_power = ch_info->eeprom.max_power_avg;
1538
1539 return min(max_power, ch_info->max_power_avg);
1540}
1541
1542/**
e2ebc833 1543 * il3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1544 *
1545 * Compensate txpower settings of *all* channels for temperature.
1546 * This only accounts for the difference between current temperature
1547 * and the factory calibration temperatures, and bases the new settings
0c2c8852 1548 * on the channel's base_power_idx.
b481de9c
ZY		 1549 *
1550 * If RxOn is "associated", this sends the new Txpower to NIC!
1551 */
e7392364
SG		 1552static int
1553il3945_hw_reg_comp_txpower_temp(struct il_priv *il)
b481de9c 1554{
e2ebc833 1555 struct il_channel_info *ch_info = NULL;
46bc8d4b 1556 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
0c2c8852 1557 int delta_idx;
e7392364 1558 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
b481de9c 1559 u8 a_band;
0c2c8852
SG		 1560 u8 rate_idx;
1561 u8 scan_tbl_idx;
b481de9c
ZY		 1562 u8 i;
1563 int ref_temp;
46bc8d4b 1564 int temperature = il->temperature;
b481de9c 1565
e7392364 1566 if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) {
4e7033ef
WYG		 1567 /* do not perform tx power calibration */
1568 return 0;
1569 }
b481de9c 1570 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
46bc8d4b
SG		 1571 for (i = 0; i < il->channel_count; i++) {
1572 ch_info = &il->channel_info[i];
e2ebc833 1573 a_band = il_is_channel_a_band(ch_info);
b481de9c
ZY		 1574
1575 /* Get this chnlgrp's factory calibration temperature */
e7392364 1576 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature;
b481de9c 1577
0c2c8852 1578 /* get power idx adjustment based on current and factory
b481de9c 1579 * temps */
e7392364
SG		 1580 delta_idx =
1581 il3945_hw_reg_adjust_power_by_temp(temperature, ref_temp);
b481de9c
ZY		 1582
1583 /* set tx power value for all rates, OFDM and CCK */
e7392364 1584 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; rate_idx++) {
b481de9c 1585 int power_idx =
0c2c8852 1586 ch_info->power_info[rate_idx].base_power_idx;
b481de9c
ZY		 1587
1588 /* temperature compensate */
0c2c8852 1589 power_idx += delta_idx;
b481de9c
ZY		 1590
1591 /* stay within table range */
0c2c8852 1592 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
e7392364
SG		 1593 ch_info->power_info[rate_idx].power_table_idx =
1594 (u8) power_idx;
0c2c8852 1595 ch_info->power_info[rate_idx].tpc =
b481de9c
ZY		 1596 power_gain_table[a_band][power_idx];
1597 }
1598
1599 /* Get this chnlgrp's rate-to-max/clip-powers table */
e7392364
SG		 1600 clip_pwrs =
1601 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
b481de9c
ZY		 1602
1603 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
e7392364
SG		 1604 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
1605 scan_tbl_idx++) {
1606 s32 actual_idx =
1607 (scan_tbl_idx ==
1608 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
0c2c8852 1609 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
e7392364
SG		 1610 actual_idx, clip_pwrs,
1611 ch_info, a_band);
b481de9c
ZY		 1612 }
1613 }
1614
1615 /* send Txpower command for current channel to ucode */
c39ae9fd 1616 return il->ops->lib->send_tx_power(il);
b481de9c
ZY		 1617}
1618
e7392364
SG		 1619int
1620il3945_hw_reg_set_txpower(struct il_priv *il, s8 power)
b481de9c 1621{
e2ebc833 1622 struct il_channel_info *ch_info;
b481de9c
ZY		 1623 s8 max_power;
1624 u8 a_band;
1625 u8 i;
1626
46bc8d4b 1627 if (il->tx_power_user_lmt == power) {
e7392364
SG		 1628 D_POWER("Requested Tx power same as current " "limit: %ddBm.\n",
1629 power);
b481de9c
ZY		 1630 return 0;
1631 }
1632
58de00a4 1633 D_POWER("Setting upper limit clamp to %ddBm.\n", power);
46bc8d4b 1634 il->tx_power_user_lmt = power;
b481de9c
ZY		 1635
1636 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1637
46bc8d4b
SG		 1638 for (i = 0; i < il->channel_count; i++) {
1639 ch_info = &il->channel_info[i];
e2ebc833 1640 a_band = il_is_channel_a_band(ch_info);
b481de9c
ZY		 1641
1642 /* find minimum power of all user and regulatory constraints
1643 * (does not consider h/w clipping limitations) */
e2ebc833 1644 max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1645 max_power = min(power, max_power);
1646 if (max_power != ch_info->curr_txpow) {
1647 ch_info->curr_txpow = max_power;
1648
1649 /* this considers the h/w clipping limitations */
46bc8d4b 1650 il3945_hw_reg_set_new_power(il, ch_info);
b481de9c
ZY		 1651 }
1652 }
1653
1654 /* update txpower settings for all channels,
1655 * send to NIC if associated. */
46bc8d4b
SG		 1656 il3945_is_temp_calib_needed(il);
1657 il3945_hw_reg_comp_txpower_temp(il);
b481de9c
ZY		 1658
1659 return 0;
1660}
1661
e7392364 1662static int
83007196 1663il3945_send_rxon_assoc(struct il_priv *il)
5bbe233b
AK		 1664{
1665 int rc = 0;
dcae1c64 1666 struct il_rx_pkt *pkt;
e2ebc833
SG		 1667 struct il3945_rxon_assoc_cmd rxon_assoc;
1668 struct il_host_cmd cmd = {
4d69c752 1669 .id = C_RXON_ASSOC,
5bbe233b 1670 .len = sizeof(rxon_assoc),
c2acea8e 1671 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1672 .data = &rxon_assoc,
1673 };
c8b03958
SG		 1674 const struct il_rxon_cmd *rxon1 = &il->staging;
1675 const struct il_rxon_cmd *rxon2 = &il->active;
5bbe233b 1676
232913b5
SG		 1677 if (rxon1->flags == rxon2->flags &&
1678 rxon1->filter_flags == rxon2->filter_flags &&
1679 rxon1->cck_basic_rates == rxon2->cck_basic_rates &&
1680 rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) {
58de00a4 1681 D_INFO("Using current RXON_ASSOC. Not resending.\n");
5bbe233b
AK		 1682 return 0;
1683 }
1684
c8b03958
SG		 1685 rxon_assoc.flags = il->staging.flags;
1686 rxon_assoc.filter_flags = il->staging.filter_flags;
1687 rxon_assoc.ofdm_basic_rates = il->staging.ofdm_basic_rates;
1688 rxon_assoc.cck_basic_rates = il->staging.cck_basic_rates;
5bbe233b
AK		 1689 rxon_assoc.reserved = 0;
1690
46bc8d4b 1691 rc = il_send_cmd_sync(il, &cmd);
5bbe233b
AK		 1692 if (rc)
1693 return rc;
1694
dcae1c64 1695 pkt = (struct il_rx_pkt *)cmd.reply_page;
e2ebc833 1696 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
4d69c752 1697 IL_ERR("Bad return from C_RXON_ASSOC command\n");
5bbe233b
AK		 1698 rc = -EIO;
1699 }
1700
46bc8d4b 1701 il_free_pages(il, cmd.reply_page);
5bbe233b
AK		 1702
1703 return rc;
1704}
1705
e0158e61 1706/**
e2ebc833 1707 * il3945_commit_rxon - commit staging_rxon to hardware
e0158e61
AK		 1708 *
1709 * The RXON command in staging_rxon is committed to the hardware and
1710 * the active_rxon structure is updated with the new data. This
1711 * function correctly transitions out of the RXON_ASSOC_MSK state if
1712 * a HW tune is required based on the RXON structure changes.
1713 */
e7392364 1714int
83007196 1715il3945_commit_rxon(struct il_priv *il)
e0158e61
AK		 1716{
1717 /* cast away the const for active_rxon in this function */
c8b03958
SG		 1718 struct il3945_rxon_cmd *active_rxon = (void *)&il->active;
1719 struct il3945_rxon_cmd *staging_rxon = (void *)&il->staging;
e0158e61 1720 int rc = 0;
246ed355 1721 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
e0158e61 1722
a6766ccd 1723 if (test_bit(S_EXIT_PENDING, &il->status))
adb90a00
WYG		 1724 return -EINVAL;
1725
46bc8d4b 1726 if (!il_is_alive(il))
e0158e61
AK		 1727 return -1;
1728
1729 /* always get timestamp with Rx frame */
1730 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1731
1732 /* select antenna */
e7392364 1733 staging_rxon->flags &= ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
46bc8d4b 1734 staging_rxon->flags |= il3945_get_antenna_flags(il);
e0158e61 1735
83007196 1736 rc = il_check_rxon_cmd(il);
e0158e61 1737 if (rc) {
9406f797 1738 IL_ERR("Invalid RXON configuration. Not committing.\n");
e0158e61
AK		 1739 return -EINVAL;
1740 }
1741
1742 /* If we don't need to send a full RXON, we can use
e2ebc833 1743 * il3945_rxon_assoc_cmd which is used to reconfigure filter
e0158e61 1744 * and other flags for the current radio configuration. */
83007196
SG		 1745 if (!il_full_rxon_required(il)) {
1746 rc = il_send_rxon_assoc(il);
e0158e61 1747 if (rc) {
9406f797 1748 IL_ERR("Error setting RXON_ASSOC "
e7392364 1749 "configuration (%d).\n", rc);
e0158e61
AK		 1750 return rc;
1751 }
1752
1753 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
17e859a8
SG		 1754 /*
1755 * We do not commit tx power settings while channel changing,
1756 * do it now if tx power changed.
1757 */
46bc8d4b 1758 il_set_tx_power(il, il->tx_power_next, false);
e0158e61
AK		 1759 return 0;
1760 }
1761
1762 /* If we are currently associated and the new config requires
1763 * an RXON_ASSOC and the new config wants the associated mask enabled,
1764 * we must clear the associated from the active configuration
1765 * before we apply the new config */
7c2cde2e 1766 if (il_is_associated(il) && new_assoc) {
58de00a4 1767 D_INFO("Toggling associated bit on current RXON\n");
e0158e61
AK		 1768 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1769
1770 /*
1771 * reserved4 and 5 could have been filled by the iwlcore code.
1772 * Let's clear them before pushing to the 3945.
1773 */
1774 active_rxon->reserved4 = 0;
1775 active_rxon->reserved5 = 0;
e7392364 1776 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
c8b03958 1777 &il->active);
e0158e61
AK		 1778
1779 /* If the mask clearing failed then we set
1780 * active_rxon back to what it was previously */
1781 if (rc) {
1782 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
9406f797 1783 IL_ERR("Error clearing ASSOC_MSK on current "
e7392364 1784 "configuration (%d).\n", rc);
e0158e61
AK		 1785 return rc;
1786 }
83007196
SG		 1787 il_clear_ucode_stations(il);
1788 il_restore_stations(il);
e0158e61
AK		 1789 }
1790
e7392364
SG		 1791 D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n"
1792 "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"),
1793 le16_to_cpu(staging_rxon->channel), staging_rxon->bssid_addr);
e0158e61
AK		 1794
1795 /*
1796 * reserved4 and 5 could have been filled by the iwlcore code.
1797 * Let's clear them before pushing to the 3945.
1798 */
1799 staging_rxon->reserved4 = 0;
1800 staging_rxon->reserved5 = 0;
1801
83007196 1802 il_set_rxon_hwcrypto(il, !il3945_mod_params.sw_crypto);
e0158e61
AK		 1803
1804 /* Apply the new configuration */
e7392364
SG		 1805 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1806 staging_rxon);
e0158e61 1807 if (rc) {
9406f797 1808 IL_ERR("Error setting new configuration (%d).\n", rc);
e0158e61
AK		 1809 return rc;
1810 }
1811
1812 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1813
7e246191 1814 if (!new_assoc) {
83007196
SG		 1815 il_clear_ucode_stations(il);
1816 il_restore_stations(il);
7e246191 1817 }
e0158e61
AK		 1818
1819 /* If we issue a new RXON command which required a tune then we must
1820 * send a new TXPOWER command or we won't be able to Tx any frames */
46bc8d4b 1821 rc = il_set_tx_power(il, il->tx_power_next, true);
e0158e61 1822 if (rc) {
9406f797 1823 IL_ERR("Error setting Tx power (%d).\n", rc);
e0158e61
AK		 1824 return rc;
1825 }
1826
e0158e61 1827 /* Init the hardware's rate fallback order based on the band */
46bc8d4b 1828 rc = il3945_init_hw_rate_table(il);
e0158e61 1829 if (rc) {
9406f797 1830 IL_ERR("Error setting HW rate table: %02X\n", rc);
e0158e61
AK		 1831 return -EIO;
1832 }
1833
1834 return 0;
1835}
1836
b481de9c 1837/**
e2ebc833 1838 * il3945_reg_txpower_periodic - called when time to check our temperature.
b481de9c
ZY		 1839 *
1840 * -- reset periodic timer
1841 * -- see if temp has changed enough to warrant re-calibration ... if so:
1842 * -- correct coeffs for temp (can reset temp timer)
1843 * -- save this temp as "last",
1844 * -- send new set of gain settings to NIC
1845 * NOTE: This should continue working, even when we're not associated,
1846 * so we can keep our internal table of scan powers current. */
e7392364
SG		 1847void
1848il3945_reg_txpower_periodic(struct il_priv *il)
b481de9c
ZY		 1849{
1850 /* This will kick in the "brute force"
e2ebc833 1851 * il3945_hw_reg_comp_txpower_temp() below */
46bc8d4b 1852 if (!il3945_is_temp_calib_needed(il))
b481de9c
ZY		 1853 goto reschedule;
1854
1855 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1856 * This is based *only* on current temperature,
1857 * ignoring any previous power measurements */
46bc8d4b 1858 il3945_hw_reg_comp_txpower_temp(il);
b481de9c 1859
e7392364
SG		 1860reschedule:
1861 queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic,
1862 REG_RECALIB_PERIOD * HZ);
b481de9c
ZY		 1863}
1864
e7392364
SG		 1865static void
1866il3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1867{
46bc8d4b 1868 struct il_priv *il = container_of(work, struct il_priv,
e7392364 1869 _3945.thermal_periodic.work);
b481de9c 1870
a6766ccd 1871 if (test_bit(S_EXIT_PENDING, &il->status))
b481de9c
ZY		 1872 return;
1873
46bc8d4b
SG		 1874 mutex_lock(&il->mutex);
1875 il3945_reg_txpower_periodic(il);
1876 mutex_unlock(&il->mutex);
b481de9c
ZY		 1877}
1878
1879/**
1722f8e1 1880 * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4) for channel.
b481de9c
ZY		 1881 *
1882 * This function is used when initializing channel-info structs.
1883 *
1884 * NOTE: These channel groups do *NOT* match the bands above!
1885 * These channel groups are based on factory-tested channels;
1886 * on A-band, EEPROM's "group frequency" entries represent the top
1887 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1888 */
e7392364
SG		 1889static u16
1890il3945_hw_reg_get_ch_grp_idx(struct il_priv *il,
1891 const struct il_channel_info *ch_info)
b481de9c 1892{
46bc8d4b 1893 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
e2ebc833 1894 struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c 1895 u8 group;
0c2c8852 1896 u16 group_idx = 0; /* based on factory calib frequencies */
b481de9c
ZY		 1897 u8 grp_channel;
1898
0c2c8852 1899 /* Find the group idx for the channel ... don't use idx 1(?) */
e2ebc833 1900 if (il_is_channel_a_band(ch_info)) {
b481de9c
ZY		 1901 for (group = 1; group < 5; group++) {
1902 grp_channel = ch_grp[group].group_channel;
1903 if (ch_info->channel <= grp_channel) {
0c2c8852 1904 group_idx = group;
b481de9c
ZY		 1905 break;
1906 }
1907 }
1908 /* group 4 has a few channels *above* its factory cal freq */
1909 if (group == 5)
0c2c8852 1910 group_idx = 4;
b481de9c 1911 } else
0c2c8852 1912 group_idx = 0; /* 2.4 GHz, group 0 */
b481de9c 1913
e7392364 1914 D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx);
0c2c8852 1915 return group_idx;
b481de9c
ZY		 1916}
1917
1918/**
0c2c8852 1919 * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx
b481de9c 1920 *
0c2c8852 1921 * Interpolate to get nominal (i.e. at factory calibration temperature) idx
b481de9c
ZY		 1922 * into radio/DSP gain settings table for requested power.
1923 */
e7392364
SG		 1924static int
1925il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power,
1722f8e1 1926 s32 setting_idx, s32 *new_idx)
b481de9c 1927{
e2ebc833 1928 const struct il3945_eeprom_txpower_group *chnl_grp = NULL;
46bc8d4b 1929 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
0c2c8852 1930 s32 idx0, idx1;
b481de9c
ZY		 1931 s32 power = 2 * requested_power;
1932 s32 i;
e2ebc833 1933 const struct il3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 1934 s32 gains0, gains1;
1935 s32 res;
1936 s32 denominator;
1937
0c2c8852 1938 chnl_grp = &eeprom->groups[setting_idx];
b481de9c
ZY		 1939 samples = chnl_grp->samples;
1940 for (i = 0; i < 5; i++) {
1941 if (power == samples[i].power) {
0c2c8852 1942 *new_idx = samples[i].gain_idx;
b481de9c
ZY		 1943 return 0;
1944 }
1945 }
1946
1947 if (power > samples[1].power) {
0c2c8852
SG		 1948 idx0 = 0;
1949 idx1 = 1;
b481de9c 1950 } else if (power > samples[2].power) {
0c2c8852
SG		 1951 idx0 = 1;
1952 idx1 = 2;
b481de9c 1953 } else if (power > samples[3].power) {
0c2c8852
SG		 1954 idx0 = 2;
1955 idx1 = 3;
b481de9c 1956 } else {
0c2c8852
SG		 1957 idx0 = 3;
1958 idx1 = 4;
b481de9c
ZY		 1959 }
1960
0c2c8852 1961 denominator = (s32) samples[idx1].power - (s32) samples[idx0].power;
b481de9c
ZY		 1962 if (denominator == 0)
1963 return -EINVAL;
0c2c8852
SG		 1964 gains0 = (s32) samples[idx0].gain_idx * (1 << 19);
1965 gains1 = (s32) samples[idx1].gain_idx * (1 << 19);
e7392364
SG		 1966 res =
1967 gains0 + (gains1 - gains0) * ((s32) power -
1968 (s32) samples[idx0].power) /
1969 denominator + (1 << 18);
0c2c8852 1970 *new_idx = res >> 19;
b481de9c
ZY		 1971 return 0;
1972}
1973
e7392364
SG		 1974static void
1975il3945_hw_reg_init_channel_groups(struct il_priv *il)
b481de9c
ZY		 1976{
1977 u32 i;
0c2c8852 1978 s32 rate_idx;
46bc8d4b 1979 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
e2ebc833 1980 const struct il3945_eeprom_txpower_group *group;
b481de9c 1981
58de00a4 1982 D_POWER("Initializing factory calib info from EEPROM\n");
b481de9c 1983
e2ebc833 1984 for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) {
b481de9c
ZY		 1985 s8 *clip_pwrs; /* table of power levels for each rate */
1986 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 1987 group = &eeprom->groups[i];
b481de9c
ZY		 1988
1989 /* sanity check on factory saturation power value */
1990 if (group->saturation_power < 40) {
9406f797 1991 IL_WARN("Error: saturation power is %d, "
e7392364
SG		 1992 "less than minimum expected 40\n",
1993 group->saturation_power);
b481de9c
ZY		 1994 return;
1995 }
1996
1997 /*
1998 * Derive requested power levels for each rate, based on
1999 * hardware capabilities (saturation power for band).
2000 * Basic value is 3dB down from saturation, with further
2001 * power reductions for highest 3 data rates. These
2002 * backoffs provide headroom for high rate modulation
2003 * power peaks, without too much distortion (clipping).
2004 */
2005 /* we'll fill in this array with h/w max power levels */
46bc8d4b 2006 clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers;
b481de9c
ZY		 2007
2008 /* divide factory saturation power by 2 to find -3dB level */
2009 satur_pwr = (s8) (group->saturation_power >> 1);
2010
2011 /* fill in channel group's nominal powers for each rate */
e7392364
SG		 2012 for (rate_idx = 0; rate_idx < RATE_COUNT_3945;
2013 rate_idx++, clip_pwrs++) {
0c2c8852 2014 switch (rate_idx) {
3b98c7f4 2015 case RATE_36M_IDX_TBL:
b481de9c
ZY		 2016 if (i == 0) /* B/G */
2017 *clip_pwrs = satur_pwr;
2018 else /* A */
2019 *clip_pwrs = satur_pwr - 5;
2020 break;
3b98c7f4 2021 case RATE_48M_IDX_TBL:
b481de9c
ZY		 2022 if (i == 0)
2023 *clip_pwrs = satur_pwr - 7;
2024 else
2025 *clip_pwrs = satur_pwr - 10;
2026 break;
3b98c7f4 2027 case RATE_54M_IDX_TBL:
b481de9c
ZY		 2028 if (i == 0)
2029 *clip_pwrs = satur_pwr - 9;
2030 else
2031 *clip_pwrs = satur_pwr - 12;
2032 break;
2033 default:
2034 *clip_pwrs = satur_pwr;
2035 break;
2036 }
2037 }
2038 }
2039}
2040
2041/**
e2ebc833 2042 * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
b481de9c 2043 *
46bc8d4b 2044 * Second pass (during init) to set up il->channel_info
b481de9c
ZY		 2045 *
2046 * Set up Tx-power settings in our channel info database for each VALID
2047 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2048 * and current temperature.
2049 *
2050 * Since this is based on current temperature (at init time), these values may
2051 * not be valid for very long, but it gives us a starting/default point,
2052 * and allows us to active (i.e. using Tx) scan.
2053 *
2054 * This does *not* write values to NIC, just sets up our internal table.
2055 */
e7392364
SG		 2056int
2057il3945_txpower_set_from_eeprom(struct il_priv *il)
b481de9c 2058{
e2ebc833
SG		 2059 struct il_channel_info *ch_info = NULL;
2060 struct il3945_channel_power_info *pwr_info;
46bc8d4b 2061 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
0c2c8852
SG		 2062 int delta_idx;
2063 u8 rate_idx;
2064 u8 scan_tbl_idx;
b481de9c
ZY		 2065 const s8 *clip_pwrs; /* array of power levels for each rate */
2066 u8 gain, dsp_atten;
2067 s8 power;
0c2c8852 2068 u8 pwr_idx, base_pwr_idx, a_band;
b481de9c
ZY		 2069 u8 i;
2070 int temperature;
2071
2072 /* save temperature reference,
2073 * so we can determine next time to calibrate */
46bc8d4b
SG		 2074 temperature = il3945_hw_reg_txpower_get_temperature(il);
2075 il->last_temperature = temperature;
b481de9c 2076
46bc8d4b 2077 il3945_hw_reg_init_channel_groups(il);
b481de9c
ZY		 2078
2079 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
46bc8d4b 2080 for (i = 0, ch_info = il->channel_info; i < il->channel_count;
b481de9c 2081 i++, ch_info++) {
e2ebc833
SG		 2082 a_band = il_is_channel_a_band(ch_info);
2083 if (!il_is_channel_valid(ch_info))
b481de9c
ZY		 2084 continue;
2085
0c2c8852 2086 /* find this channel's channel group (*not* "band") idx */
e7392364 2087 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info);
b481de9c
ZY		 2088
2089 /* Get this chnlgrp's rate->max/clip-powers table */
e7392364
SG		 2090 clip_pwrs =
2091 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
b481de9c 2092
0c2c8852 2093 /* calculate power idx *adjustment* value according to
b481de9c 2094 * diff between current temperature and factory temperature */
e7392364
SG		 2095 delta_idx =
2096 il3945_hw_reg_adjust_power_by_temp(temperature,
2097 eeprom->groups[ch_info->
2098 group_idx].
2099 temperature);
b481de9c 2100
e7392364
SG		 2101 D_POWER("Delta idx for channel %d: %d [%d]\n", ch_info->channel,
2102 delta_idx, temperature + IL_TEMP_CONVERT);
b481de9c
ZY		 2103
2104 /* set tx power value for all OFDM rates */
e7392364 2105 for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) {
25a4ccea 2106 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2107 int rc;
2108
2109 /* use channel group's clip-power table,
2110 * but don't exceed channel's max power */
2111 s8 pwr = min(ch_info->max_power_avg,
0c2c8852 2112 clip_pwrs[rate_idx]);
b481de9c 2113
0c2c8852 2114 pwr_info = &ch_info->power_info[rate_idx];
b481de9c
ZY		 2115
2116 /* get base (i.e. at factory-measured temperature)
0c2c8852
SG		 2117 * power table idx for this rate's power */
2118 rc = il3945_hw_reg_get_matched_power_idx(il, pwr,
e7392364
SG		 2119 ch_info->
2120 group_idx,
2121 &power_idx);
b481de9c 2122 if (rc) {
0c2c8852 2123 IL_ERR("Invalid power idx\n");
b481de9c
ZY		 2124 return rc;
2125 }
0c2c8852 2126 pwr_info->base_power_idx = (u8) power_idx;
b481de9c
ZY		 2127
2128 /* temperature compensate */
0c2c8852 2129 power_idx += delta_idx;
b481de9c
ZY		 2130
2131 /* stay within range of gain table */
0c2c8852 2132 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
b481de9c 2133
e2ebc833 2134 /* fill 1 OFDM rate's il3945_channel_power_info struct */
b481de9c 2135 pwr_info->requested_power = pwr;
0c2c8852 2136 pwr_info->power_table_idx = (u8) power_idx;
b481de9c
ZY		 2137 pwr_info->tpc.tx_gain =
2138 power_gain_table[a_band][power_idx].tx_gain;
2139 pwr_info->tpc.dsp_atten =
2140 power_gain_table[a_band][power_idx].dsp_atten;
2141 }
2142
e7392364 2143 /* set tx power for CCK rates, based on OFDM 12 Mbit settings */
3b98c7f4 2144 pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL];
e7392364
SG		 2145 power = pwr_info->requested_power + IL_CCK_FROM_OFDM_POWER_DIFF;
2146 pwr_idx = pwr_info->power_table_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2147 base_pwr_idx =
2148 pwr_info->base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
b481de9c
ZY		 2149
2150 /* stay within table range */
0c2c8852
SG		 2151 pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx);
2152 gain = power_gain_table[a_band][pwr_idx].tx_gain;
2153 dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten;
b481de9c 2154
e2ebc833 2155 /* fill each CCK rate's il3945_channel_power_info structure
b481de9c
ZY		 2156 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2157 * NOTE: CCK rates start at end of OFDM rates! */
e7392364
SG		 2158 for (rate_idx = 0; rate_idx < IL_CCK_RATES; rate_idx++) {
2159 pwr_info =
2160 &ch_info->power_info[rate_idx + IL_OFDM_RATES];
b481de9c 2161 pwr_info->requested_power = power;
0c2c8852
SG		 2162 pwr_info->power_table_idx = pwr_idx;
2163 pwr_info->base_power_idx = base_pwr_idx;
b481de9c
ZY		 2164 pwr_info->tpc.tx_gain = gain;
2165 pwr_info->tpc.dsp_atten = dsp_atten;
2166 }
2167
2168 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
e7392364
SG		 2169 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
2170 scan_tbl_idx++) {
2171 s32 actual_idx =
2172 (scan_tbl_idx ==
2173 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
0c2c8852 2174 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
e7392364
SG		 2175 actual_idx, clip_pwrs,
2176 ch_info, a_band);
b481de9c
ZY		 2177 }
2178 }
2179
2180 return 0;
2181}
2182
e7392364
SG		 2183int
2184il3945_hw_rxq_stop(struct il_priv *il)
b481de9c
ZY		 2185{
2186 int rc;
b481de9c 2187
0c1a94e2
SG		 2188 il_wr(il, FH39_RCSR_CONFIG(0), 0);
2189 rc = il_poll_bit(il, FH39_RSSR_STATUS,
e7392364 2190 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2191 if (rc < 0)
9406f797 2192 IL_ERR("Can't stop Rx DMA.\n");
b481de9c 2193
b481de9c
ZY		 2194 return 0;
2195}
2196
e7392364
SG		 2197int
2198il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
b481de9c 2199{
b481de9c
ZY		 2200 int txq_id = txq->q.id;
2201
46bc8d4b 2202 struct il3945_shared *shared_data = il->_3945.shared_virt;
b481de9c 2203
e7392364 2204 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr);
b481de9c 2205
0c1a94e2
SG		 2206 il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
2207 il_wr(il, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2208
0c1a94e2 2209 il_wr(il, FH39_TCSR_CONFIG(txq_id),
e7392364
SG		 2210 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2211 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2212 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2213 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2214 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2215
2216 /* fake read to flush all prev. writes */
841b2cca 2217 _il_rd(il, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2218
2219 return 0;
2220}
2221
42427b4e
KA		 2222/*
2223 * HCMD utils
2224 */
e7392364
SG		 2225static u16
2226il3945_get_hcmd_size(u8 cmd_id, u16 len)
42427b4e
KA		 2227{
2228 switch (cmd_id) {
4d69c752 2229 case C_RXON:
e2ebc833 2230 return sizeof(struct il3945_rxon_cmd);
4d69c752 2231 case C_POWER_TBL:
e2ebc833 2232 return sizeof(struct il3945_powertable_cmd);
42427b4e
KA		 2233 default:
2234 return len;
2235 }
2236}
2237
e7392364
SG		 2238static u16
2239il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data)
17f841cd 2240{
e2ebc833 2241 struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data;
c587de0b
TW		 2242 addsta->mode = cmd->mode;
2243 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
e2ebc833 2244 memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo));
c587de0b
TW		 2245 addsta->station_flags = cmd->station_flags;
2246 addsta->station_flags_msk = cmd->station_flags_msk;
2247 addsta->tid_disable_tx = cpu_to_le16(0);
2248 addsta->rate_n_flags = cmd->rate_n_flags;
2249 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2250 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2251 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2252
e7392364 2253 return (u16) sizeof(struct il3945_addsta_cmd);
17f841cd
SO		 2254}
2255
e7392364
SG		 2256static int
2257il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r)
a30e3112 2258{
a30e3112
JB		 2259 int ret;
2260 u8 sta_id;
2261 unsigned long flags;
2262
2263 if (sta_id_r)
e2ebc833 2264 *sta_id_r = IL_INVALID_STATION;
a30e3112 2265
83007196 2266 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
a30e3112 2267 if (ret) {
9406f797 2268 IL_ERR("Unable to add station %pM\n", addr);
a30e3112
JB		 2269 return ret;
2270 }
2271
2272 if (sta_id_r)
2273 *sta_id_r = sta_id;
2274
46bc8d4b
SG		 2275 spin_lock_irqsave(&il->sta_lock, flags);
2276 il->stations[sta_id].used |= IL_STA_LOCAL;
2277 spin_unlock_irqrestore(&il->sta_lock, flags);
a30e3112
JB		 2278
2279 return 0;
2280}
e7392364
SG		 2281
2282static int
2283il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
2284 bool add)
1fa61b2e 2285{
e2ebc833 2286 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1fa61b2e
JB		 2287 int ret;
2288
1fa61b2e 2289 if (add) {
e7392364
SG		 2290 ret =
2291 il3945_add_bssid_station(il, vif->bss_conf.bssid,
2292 &vif_priv->ibss_bssid_sta_id);
1fa61b2e
JB		 2293 if (ret)
2294 return ret;
2295
46bc8d4b 2296 il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id,
e7392364
SG		 2297 (il->band ==
2298 IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP :
2299 RATE_1M_PLCP);
46bc8d4b 2300 il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id);
1fa61b2e
JB		 2301
2302 return 0;
2303 }
2304
46bc8d4b 2305 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
e7392364 2306 vif->bss_conf.bssid);
1fa61b2e 2307}
c587de0b 2308
b481de9c 2309/**
e2ebc833 2310 * il3945_init_hw_rate_table - Initialize the hardware rate fallback table
b481de9c 2311 */
e7392364
SG		 2312int
2313il3945_init_hw_rate_table(struct il_priv *il)
b481de9c 2314{
0c2c8852 2315 int rc, i, idx, prev_idx;
e2ebc833 2316 struct il3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2317 .reserved = {0, 0, 0},
2318 };
e2ebc833 2319 struct il3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2320
e2ebc833 2321 for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) {
0c2c8852 2322 idx = il3945_rates[i].table_rs_idx;
14577f23 2323
280ade5e 2324 table[idx].rate_n_flags = cpu_to_le16(il3945_rates[i].plcp);
0c2c8852
SG		 2325 table[idx].try_cnt = il->retry_rate;
2326 prev_idx = il3945_get_prev_ieee_rate(i);
e7392364 2327 table[idx].next_rate_idx = il3945_rates[prev_idx].table_rs_idx;
b481de9c
ZY		 2328 }
2329
46bc8d4b 2330 switch (il->band) {
8318d78a 2331 case IEEE80211_BAND_5GHZ:
58de00a4 2332 D_RATE("Select A mode rate scale\n");
b481de9c
ZY		 2333 /* If one of the following CCK rates is used,
2334 * have it fall back to the 6M OFDM rate */
e7392364 2335 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++)
0c2c8852 2336 table[i].next_rate_idx =
e7392364 2337 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
b481de9c
ZY		 2338
2339 /* Don't fall back to CCK rates */
e7392364 2340 table[RATE_12M_IDX_TBL].next_rate_idx = RATE_9M_IDX_TBL;
b481de9c
ZY		 2341
2342 /* Don't drop out of OFDM rates */
3b98c7f4 2343 table[RATE_6M_IDX_TBL].next_rate_idx =
0c2c8852 2344 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
b481de9c
ZY		 2345 break;
2346
8318d78a 2347 case IEEE80211_BAND_2GHZ:
58de00a4 2348 D_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2349 /* If an OFDM rate is used, have it fall back to the
2350 * 1M CCK rates */
b481de9c 2351
46bc8d4b 2352 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
7c2cde2e 2353 il_is_associated(il)) {
7262796a 2354
0c2c8852 2355 idx = IL_FIRST_CCK_RATE;
e7392364 2356 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++)
0c2c8852 2357 table[i].next_rate_idx =
e7392364 2358 il3945_rates[idx].table_rs_idx;
7262796a 2359
3b98c7f4 2360 idx = RATE_11M_IDX_TBL;
7262796a 2361 /* CCK shouldn't fall back to OFDM... */
3b98c7f4 2362 table[idx].next_rate_idx = RATE_5M_IDX_TBL;
7262796a 2363 }
b481de9c
ZY		 2364 break;
2365
2366 default:
8318d78a 2367 WARN_ON(1);
b481de9c
ZY		 2368 break;
2369 }
2370
2371 /* Update the rate scaling for control frame Tx */
2372 rate_cmd.table_id = 0;
e7392364 2373 rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
b481de9c
ZY		 2374 if (rc)
2375 return rc;
2376
2377 /* Update the rate scaling for data frame Tx */
2378 rate_cmd.table_id = 1;
e7392364 2379 return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
b481de9c
ZY		 2380}
2381
796083cb 2382/* Called when initializing driver */
e7392364
SG		 2383int
2384il3945_hw_set_hw_params(struct il_priv *il)
b481de9c 2385{
e7392364 2386 memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params));
b481de9c 2387
46bc8d4b 2388 il->_3945.shared_virt =
e7392364
SG		 2389 dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared),
2390 &il->_3945.shared_phys, GFP_KERNEL);
46bc8d4b 2391 if (!il->_3945.shared_virt) {
9406f797 2392 IL_ERR("failed to allocate pci memory\n");
b481de9c
ZY		 2393 return -ENOMEM;
2394 }
2395
b16db50a
SG		 2396 il->hw_params.bcast_id = IL3945_BROADCAST_ID;
2397
21c02a1a 2398 /* Assign number of Usable TX queues */
89ef1ed2 2399 il->hw_params.max_txq_num = il->cfg->num_of_queues;
21c02a1a 2400
46bc8d4b
SG		 2401 il->hw_params.tfd_size = sizeof(struct il3945_tfd);
2402 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K);
2403 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2404 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
d3175167 2405 il->hw_params.max_stations = IL3945_STATION_COUNT;
3e82a822 2406
46bc8d4b 2407 il->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 2408
46bc8d4b 2409 il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
d3175167
SG		 2410 il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL;
2411 il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS;
141c43a3 2412
b481de9c
ZY		 2413 return 0;
2414}
2415
e7392364
SG		 2416unsigned int
2417il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame,
2418 u8 rate)
b481de9c 2419{
e2ebc833 2420 struct il3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2421 unsigned int frame_size;
2422
e2ebc833 2423 tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2424 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2425
b16db50a 2426 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
b481de9c
ZY		 2427 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2428
e7392364
SG		 2429 frame_size =
2430 il3945_fill_beacon_frame(il, tx_beacon_cmd->frame,
2431 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
b481de9c
ZY		 2432
2433 BUG_ON(frame_size > MAX_MPDU_SIZE);
e7392364 2434 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
b481de9c
ZY		 2435
2436 tx_beacon_cmd->tx.rate = rate;
e7392364
SG		 2437 tx_beacon_cmd->tx.tx_flags =
2438 (TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK);
b481de9c 2439
e7392364 2440 /* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE */
14577f23 2441 tx_beacon_cmd->tx.supp_rates[0] =
e7392364 2442 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
14577f23 2443
e7392364 2444 tx_beacon_cmd->tx.supp_rates[1] = (IL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2445
e2ebc833 2446 return sizeof(struct il3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2447}
2448
e7392364
SG		 2449void
2450il3945_hw_handler_setup(struct il_priv *il)
b481de9c 2451{
6e9848b4
SG		 2452 il->handlers[C_TX] = il3945_hdl_tx;
2453 il->handlers[N_3945_RX] = il3945_hdl_rx;
b481de9c
ZY		 2454}
2455
e7392364
SG		 2456void
2457il3945_hw_setup_deferred_work(struct il_priv *il)
b481de9c 2458{
46bc8d4b 2459 INIT_DELAYED_WORK(&il->_3945.thermal_periodic,
e2ebc833 2460 il3945_bg_reg_txpower_periodic);
b481de9c
ZY		 2461}
2462
e7392364
SG		 2463void
2464il3945_hw_cancel_deferred_work(struct il_priv *il)
b481de9c 2465{
46bc8d4b 2466 cancel_delayed_work(&il->_3945.thermal_periodic);
b481de9c
ZY		 2467}
2468
0164b9b4 2469/* check contents of special bootstrap uCode SRAM */
e7392364
SG		 2470static int
2471il3945_verify_bsm(struct il_priv *il)
2472{
46bc8d4b
SG		 2473 __le32 *image = il->ucode_boot.v_addr;
2474 u32 len = il->ucode_boot.len;
0164b9b4
KA		 2475 u32 reg;
2476 u32 val;
2477
58de00a4 2478 D_INFO("Begin verify bsm\n");
0164b9b4
KA		 2479
2480 /* verify BSM SRAM contents */
db54eb57 2481 val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
e7392364 2482 for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len;
0164b9b4 2483 reg += sizeof(u32), image++) {
db54eb57 2484 val = il_rd_prph(il, reg);
0164b9b4 2485 if (val != le32_to_cpu(*image)) {
9406f797 2486 IL_ERR("BSM uCode verification failed at "
e7392364
SG		 2487 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2488 BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND,
2489 len, val, le32_to_cpu(*image));
0164b9b4
KA		 2490 return -EIO;
2491 }
2492 }
2493
58de00a4 2494 D_INFO("BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2495
2496 return 0;
2497}
2498
e6148917
SO		 2499/******************************************************************************
2500 *
2501 * EEPROM related functions
2502 *
2503 ******************************************************************************/
2504
2505/*
2506 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2507 * embedded controller) as EEPROM reader; each read is a series of pulses
2508 * to/from the EEPROM chip, not a single event, so even reads could conflict
2509 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2510 * simply claims ownership, which should be safe when this function is called
2511 * (i.e. before loading uCode!).
2512 */
e7392364
SG		 2513static int
2514il3945_eeprom_acquire_semaphore(struct il_priv *il)
e6148917 2515{
46bc8d4b 2516 _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
e6148917
SO		 2517 return 0;
2518}
2519
e7392364
SG		 2520static void
2521il3945_eeprom_release_semaphore(struct il_priv *il)
e6148917
SO		 2522{
2523 return;
2524}
2525
0164b9b4 2526 /**
e2ebc833 2527 * il3945_load_bsm - Load bootstrap instructions
0164b9b4
KA		 2528 *
2529 * BSM operation:
2530 *
2531 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2532 * in special SRAM that does not power down during RFKILL. When powering back
2533 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2534 * the bootstrap program into the on-board processor, and starts it.
2535 *
2536 * The bootstrap program loads (via DMA) instructions and data for a new
2537 * program from host DRAM locations indicated by the host driver in the
2538 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2539 * automatically.
2540 *
2541 * When initializing the NIC, the host driver points the BSM to the
2542 * "initialize" uCode image. This uCode sets up some internal data, then
2543 * notifies host via "initialize alive" that it is complete.
2544 *
2545 * The host then replaces the BSM_DRAM_* pointer values to point to the
2546 * normal runtime uCode instructions and a backup uCode data cache buffer
2547 * (filled initially with starting data values for the on-board processor),
2548 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2549 * which begins normal operation.
2550 *
2551 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2552 * the backup data cache in DRAM before SRAM is powered down.
2553 *
2554 * When powering back up, the BSM loads the bootstrap program. This reloads
2555 * the runtime uCode instructions and the backup data cache into SRAM,
2556 * and re-launches the runtime uCode from where it left off.
2557 */
e7392364
SG		 2558static int
2559il3945_load_bsm(struct il_priv *il)
0164b9b4 2560{
46bc8d4b
SG		 2561 __le32 *image = il->ucode_boot.v_addr;
2562 u32 len = il->ucode_boot.len;
0164b9b4
KA		 2563 dma_addr_t pinst;
2564 dma_addr_t pdata;
2565 u32 inst_len;
2566 u32 data_len;
2567 int rc;
2568 int i;
2569 u32 done;
2570 u32 reg_offset;
2571
58de00a4 2572 D_INFO("Begin load bsm\n");
0164b9b4
KA		 2573
2574 /* make sure bootstrap program is no larger than BSM's SRAM size */
d3175167 2575 if (len > IL39_MAX_BSM_SIZE)
0164b9b4
KA		 2576 return -EINVAL;
2577
2578 /* Tell bootstrap uCode where to find the "Initialize" uCode
e7392364
SG		 2579 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2580 * NOTE: il3945_initialize_alive_start() will replace these values,
2581 * after the "initialize" uCode has run, to point to
2582 * runtime/protocol instructions and backup data cache. */
46bc8d4b
SG		 2583 pinst = il->ucode_init.p_addr;
2584 pdata = il->ucode_init_data.p_addr;
2585 inst_len = il->ucode_init.len;
2586 data_len = il->ucode_init_data.len;
0164b9b4 2587
db54eb57
SG		 2588 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2589 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2590 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2591 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
0164b9b4
KA		 2592
2593 /* Fill BSM memory with bootstrap instructions */
2594 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2595 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2596 reg_offset += sizeof(u32), image++)
e7392364 2597 _il_wr_prph(il, reg_offset, le32_to_cpu(*image));
0164b9b4 2598
46bc8d4b 2599 rc = il3945_verify_bsm(il);
a8b50a0a 2600 if (rc)
0164b9b4 2601 return rc;
0164b9b4
KA		 2602
2603 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
db54eb57 2604 il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
e7392364 2605 il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND);
db54eb57 2606 il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
0164b9b4
KA		 2607
2608 /* Load bootstrap code into instruction SRAM now,
2609 * to prepare to load "initialize" uCode */
e7392364 2610 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
0164b9b4
KA		 2611
2612 /* Wait for load of bootstrap uCode to finish */
2613 for (i = 0; i < 100; i++) {
db54eb57 2614 done = il_rd_prph(il, BSM_WR_CTRL_REG);
0164b9b4
KA		 2615 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2616 break;
2617 udelay(10);
2618 }
2619 if (i < 100)
58de00a4 2620 D_INFO("BSM write complete, poll %d iterations\n", i);
0164b9b4 2621 else {
9406f797 2622 IL_ERR("BSM write did not complete!\n");
0164b9b4
KA		 2623 return -EIO;
2624 }
2625
2626 /* Enable future boot loads whenever power management unit triggers it
2627 * (e.g. when powering back up after power-save shutdown) */
e7392364 2628 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
0164b9b4 2629
0164b9b4
KA		 2630 return 0;
2631}
2632
e2ebc833
SG		 2633static struct il_hcmd_ops il3945_hcmd = {
2634 .rxon_assoc = il3945_send_rxon_assoc,
2635 .commit_rxon = il3945_commit_rxon,
5bbe233b
AK		 2636};
2637
e2ebc833
SG		 2638static struct il_lib_ops il3945_lib = {
2639 .txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd,
2640 .txq_free_tfd = il3945_hw_txq_free_tfd,
2641 .txq_init = il3945_hw_tx_queue_init,
2642 .load_ucode = il3945_load_bsm,
2643 .dump_nic_error_log = il3945_dump_nic_error_log,
01ec616d 2644 .apm_ops = {
e7392364
SG		 2645 .init = il3945_apm_init,
2646 .config = il3945_nic_config,
2647 },
e6148917 2648 .eeprom_ops = {
e7392364
SG		 2649 .regulatory_bands = {
2650 EEPROM_REGULATORY_BAND_1_CHANNELS,
2651 EEPROM_REGULATORY_BAND_2_CHANNELS,
2652 EEPROM_REGULATORY_BAND_3_CHANNELS,
2653 EEPROM_REGULATORY_BAND_4_CHANNELS,
2654 EEPROM_REGULATORY_BAND_5_CHANNELS,
2655 EEPROM_REGULATORY_BAND_NO_HT40,
2656 EEPROM_REGULATORY_BAND_NO_HT40,
2657 },
2658 .acquire_semaphore = il3945_eeprom_acquire_semaphore,
2659 .release_semaphore = il3945_eeprom_release_semaphore,
2660 },
2661 .send_tx_power = il3945_send_tx_power,
e2ebc833 2662 .is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr,
17f36fc6 2663
9b5e2f46 2664#ifdef CONFIG_IWLEGACY_DEBUGFS
17f36fc6 2665 .debugfs_ops = {
e7392364
SG		 2666 .rx_stats_read = il3945_ucode_rx_stats_read,
2667 .tx_stats_read = il3945_ucode_tx_stats_read,
2668 .general_stats_read = il3945_ucode_general_stats_read,
2669 },
9b5e2f46 2670#endif
0164b9b4
KA		 2671};
2672
e2ebc833
SG		 2673static const struct il_legacy_ops il3945_legacy_ops = {
2674 .post_associate = il3945_post_associate,
2675 .config_ap = il3945_config_ap,
2676 .manage_ibss_station = il3945_manage_ibss_station,
2295c66b
JB		 2677};
2678
e2ebc833
SG		 2679static struct il_hcmd_utils_ops il3945_hcmd_utils = {
2680 .get_hcmd_size = il3945_get_hcmd_size,
2681 .build_addsta_hcmd = il3945_build_addsta_hcmd,
2682 .request_scan = il3945_request_scan,
2683 .post_scan = il3945_post_scan,
42427b4e
KA		 2684};
2685
c39ae9fd 2686const struct il_ops il3945_ops = {
e2ebc833
SG		 2687 .lib = &il3945_lib,
2688 .hcmd = &il3945_hcmd,
2689 .utils = &il3945_hcmd_utils,
2690 .led = &il3945_led_ops,
2691 .legacy = &il3945_legacy_ops,
0164b9b4
KA		 2692};
2693
e2ebc833 2694static struct il_cfg il3945_bg_cfg = {
7cb1b088 2695 .name = "3945BG",
d3175167
SG		 2696 .fw_name_pre = IL3945_FW_PRE,
2697 .ucode_api_max = IL3945_UCODE_API_MAX,
2698 .ucode_api_min = IL3945_UCODE_API_MIN,
e2ebc833 2699 .sku = IL_SKU_G,
7cb1b088 2700 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
e2ebc833 2701 .mod_params = &il3945_mod_params,
e2ebc833 2702 .led_mode = IL_LED_BLINK,
89ef1ed2
SG		 2703
2704 .eeprom_size = IL3945_EEPROM_IMG_SIZE,
2705 .num_of_queues = IL39_NUM_QUEUES,
2706 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2707 .set_l0s = false,
2708 .use_bsm = true,
2709 .led_compensation = 64,
2710 .wd_timeout = IL_DEF_WD_TIMEOUT
7cb1b088
WYG		 2711};
2712
e2ebc833 2713static struct il_cfg il3945_abg_cfg = {
82b9a121 2714 .name = "3945ABG",
d3175167
SG		 2715 .fw_name_pre = IL3945_FW_PRE,
2716 .ucode_api_max = IL3945_UCODE_API_MAX,
2717 .ucode_api_min = IL3945_UCODE_API_MIN,
e7392364 2718 .sku = IL_SKU_A | IL_SKU_G,
e6148917 2719 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
e2ebc833 2720 .mod_params = &il3945_mod_params,
e2ebc833 2721 .led_mode = IL_LED_BLINK,
89ef1ed2
SG		 2722
2723 .eeprom_size = IL3945_EEPROM_IMG_SIZE,
2724 .num_of_queues = IL39_NUM_QUEUES,
2725 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2726 .set_l0s = false,
2727 .use_bsm = true,
2728 .led_compensation = 64,
2729 .wd_timeout = IL_DEF_WD_TIMEOUT
82b9a121
TW		 2730};
2731
e2ebc833 2732DEFINE_PCI_DEVICE_TABLE(il3945_hw_card_ids) = {
1722f8e1
SG		 2733 {IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)},
2734 {IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)},
2735 {IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)},
2736 {IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)},
2737 {IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)},
2738 {IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)},
2739 {0}
b481de9c
ZY		 2740};
2741
e2ebc833 2742MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)