iwlegacy: remove struct il_tx_info
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlegacy / 3945-mac.c
CommitLineData
4bc85c13
WYG
1/******************************************************************************
2 *
be663ab6 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4bc85c13
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
4bc85c13
WYG
43#include <linux/firmware.h>
44#include <linux/etherdevice.h>
45#include <linux/if_arp.h>
46
47#include <net/ieee80211_radiotap.h>
48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
52#define DRV_NAME "iwl3945"
53
d4459a99 54#include "commands.h"
98613be0 55#include "common.h"
e94a4099 56#include "3945.h"
4bc85c13 57#include "iwl-spectrum.h"
4bc85c13
WYG
58
59/*
60 * module name, copyright, version, etc.
61 */
62
63#define DRV_DESCRIPTION \
64"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
65
d3175167 66#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
67#define VD "d"
68#else
69#define VD
70#endif
71
72/*
73 * add "s" to indicate spectrum measurement included.
74 * we add it here to be consistent with previous releases in which
75 * this was configurable.
76 */
77#define DRV_VERSION IWLWIFI_VERSION VD "s"
be663ab6 78#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
4bc85c13
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79#define DRV_AUTHOR "<ilw@linux.intel.com>"
80
81MODULE_DESCRIPTION(DRV_DESCRIPTION);
82MODULE_VERSION(DRV_VERSION);
83MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
84MODULE_LICENSE("GPL");
85
86 /* module parameters */
e2ebc833 87struct il_mod_params il3945_mod_params = {
4bc85c13
WYG
88 .sw_crypto = 1,
89 .restart_fw = 1,
0263aa45 90 .disable_hw_scan = 1,
4bc85c13
WYG
91 /* the rest are 0 by default */
92};
93
94/**
e2ebc833 95 * il3945_get_antenna_flags - Get antenna flags for RXON command
46bc8d4b 96 * @il: eeprom and antenna fields are used to determine antenna flags
4bc85c13 97 *
46bc8d4b 98 * il->eeprom39 is used to determine if antenna AUX/MAIN are reversed
e2ebc833 99 * il3945_mod_params.antenna specifies the antenna diversity mode:
4bc85c13 100 *
e2ebc833
SG
101 * IL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
102 * IL_ANTENNA_MAIN - Force MAIN antenna
103 * IL_ANTENNA_AUX - Force AUX antenna
4bc85c13 104 */
e7392364
SG
105__le32
106il3945_get_antenna_flags(const struct il_priv *il)
4bc85c13 107{
46bc8d4b 108 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
4bc85c13 109
e2ebc833
SG
110 switch (il3945_mod_params.antenna) {
111 case IL_ANTENNA_DIVERSITY:
4bc85c13
WYG
112 return 0;
113
e2ebc833 114 case IL_ANTENNA_MAIN:
4bc85c13
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115 if (eeprom->antenna_switch_type)
116 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
118
e2ebc833 119 case IL_ANTENNA_AUX:
4bc85c13
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120 if (eeprom->antenna_switch_type)
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
123 }
124
125 /* bad antenna selector value */
9406f797 126 IL_ERR("Bad antenna selector value (0x%x)\n",
e7392364 127 il3945_mod_params.antenna);
4bc85c13
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128
129 return 0; /* "diversity" is default if error */
130}
131
e7392364
SG
132static int
133il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
134 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
135{
136 unsigned long flags;
137 __le16 key_flags = 0;
138 int ret;
139
140 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
141 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
142
b16db50a 143 if (sta_id == il->hw_params.bcast_id)
4bc85c13
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144 key_flags |= STA_KEY_MULTICAST_MSK;
145
146 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
147 keyconf->hw_key_idx = keyconf->keyidx;
148 key_flags &= ~STA_KEY_FLG_INVALID;
149
46bc8d4b
SG
150 spin_lock_irqsave(&il->sta_lock, flags);
151 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
152 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
e7392364 153 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
4bc85c13 154
e7392364 155 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
4bc85c13 156
e7392364
SG
157 if ((il->stations[sta_id].sta.key.
158 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
46bc8d4b 159 il->stations[sta_id].sta.key.key_offset =
e7392364 160 il_get_free_ucode_key_idx(il);
4bc85c13 161 /* else, we are overriding an existing key => no need to allocated room
e7392364 162 * in uCode. */
4bc85c13 163
46bc8d4b 164 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
e7392364 165 "no space for a new key");
4bc85c13 166
46bc8d4b
SG
167 il->stations[sta_id].sta.key.key_flags = key_flags;
168 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
169 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4bc85c13 170
58de00a4 171 D_INFO("hwcrypto: modify ucode station key info\n");
4bc85c13 172
e7392364 173 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
4bc85c13 174
46bc8d4b 175 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
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176
177 return ret;
178}
179
e7392364
SG
180static int
181il3945_set_tkip_dynamic_key_info(struct il_priv *il,
182 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
183{
184 return -EOPNOTSUPP;
185}
186
e7392364
SG
187static int
188il3945_set_wep_dynamic_key_info(struct il_priv *il,
189 struct ieee80211_key_conf *keyconf, u8 sta_id)
4bc85c13
WYG
190{
191 return -EOPNOTSUPP;
192}
193
e7392364
SG
194static int
195il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
4bc85c13
WYG
196{
197 unsigned long flags;
e2ebc833 198 struct il_addsta_cmd sta_cmd;
4bc85c13 199
46bc8d4b
SG
200 spin_lock_irqsave(&il->sta_lock, flags);
201 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
e7392364 202 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
46bc8d4b
SG
203 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
204 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
205 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
e7392364
SG
206 memcpy(&sta_cmd, &il->stations[sta_id].sta,
207 sizeof(struct il_addsta_cmd));
46bc8d4b 208 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13 209
58de00a4 210 D_INFO("hwcrypto: clear ucode station key info\n");
46bc8d4b 211 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
4bc85c13
WYG
212}
213
e7392364
SG
214static int
215il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
216 u8 sta_id)
4bc85c13
WYG
217{
218 int ret = 0;
219
220 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
221
222 switch (keyconf->cipher) {
223 case WLAN_CIPHER_SUITE_CCMP:
46bc8d4b 224 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
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225 break;
226 case WLAN_CIPHER_SUITE_TKIP:
46bc8d4b 227 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
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228 break;
229 case WLAN_CIPHER_SUITE_WEP40:
230 case WLAN_CIPHER_SUITE_WEP104:
46bc8d4b 231 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
4bc85c13
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232 break;
233 default:
e7392364 234 IL_ERR("Unknown alg: %s alg=%x\n", __func__, keyconf->cipher);
4bc85c13
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235 ret = -EINVAL;
236 }
237
58de00a4 238 D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
e7392364 239 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
4bc85c13
WYG
240
241 return ret;
242}
243
e7392364
SG
244static int
245il3945_remove_static_key(struct il_priv *il)
4bc85c13
WYG
246{
247 int ret = -EOPNOTSUPP;
248
249 return ret;
250}
251
e7392364
SG
252static int
253il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
4bc85c13
WYG
254{
255 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
256 key->cipher == WLAN_CIPHER_SUITE_WEP104)
257 return -EOPNOTSUPP;
258
9406f797 259 IL_ERR("Static key invalid: cipher %x\n", key->cipher);
4bc85c13
WYG
260 return -EINVAL;
261}
262
e7392364
SG
263static void
264il3945_clear_free_frames(struct il_priv *il)
4bc85c13
WYG
265{
266 struct list_head *element;
267
e7392364 268 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
4bc85c13 269
46bc8d4b
SG
270 while (!list_empty(&il->free_frames)) {
271 element = il->free_frames.next;
4bc85c13 272 list_del(element);
e2ebc833 273 kfree(list_entry(element, struct il3945_frame, list));
46bc8d4b 274 il->frames_count--;
4bc85c13
WYG
275 }
276
46bc8d4b 277 if (il->frames_count) {
9406f797 278 IL_WARN("%d frames still in use. Did we lose one?\n",
e7392364 279 il->frames_count);
46bc8d4b 280 il->frames_count = 0;
4bc85c13
WYG
281 }
282}
283
e7392364
SG
284static struct il3945_frame *
285il3945_get_free_frame(struct il_priv *il)
4bc85c13 286{
e2ebc833 287 struct il3945_frame *frame;
4bc85c13 288 struct list_head *element;
46bc8d4b 289 if (list_empty(&il->free_frames)) {
4bc85c13
WYG
290 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
291 if (!frame) {
9406f797 292 IL_ERR("Could not allocate frame!\n");
4bc85c13
WYG
293 return NULL;
294 }
295
46bc8d4b 296 il->frames_count++;
4bc85c13
WYG
297 return frame;
298 }
299
46bc8d4b 300 element = il->free_frames.next;
4bc85c13 301 list_del(element);
e2ebc833 302 return list_entry(element, struct il3945_frame, list);
4bc85c13
WYG
303}
304
e7392364
SG
305static void
306il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
4bc85c13
WYG
307{
308 memset(frame, 0, sizeof(*frame));
46bc8d4b 309 list_add(&frame->list, &il->free_frames);
4bc85c13
WYG
310}
311
e7392364
SG
312unsigned int
313il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
314 int left)
4bc85c13
WYG
315{
316
7c2cde2e 317 if (!il_is_associated(il) || !il->beacon_skb)
4bc85c13
WYG
318 return 0;
319
46bc8d4b 320 if (il->beacon_skb->len > left)
4bc85c13
WYG
321 return 0;
322
46bc8d4b 323 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
4bc85c13 324
46bc8d4b 325 return il->beacon_skb->len;
4bc85c13
WYG
326}
327
e7392364
SG
328static int
329il3945_send_beacon_cmd(struct il_priv *il)
4bc85c13 330{
e2ebc833 331 struct il3945_frame *frame;
4bc85c13
WYG
332 unsigned int frame_size;
333 int rc;
334 u8 rate;
335
46bc8d4b 336 frame = il3945_get_free_frame(il);
4bc85c13
WYG
337
338 if (!frame) {
9406f797 339 IL_ERR("Could not obtain free frame buffer for beacon "
e7392364 340 "command.\n");
4bc85c13
WYG
341 return -ENOMEM;
342 }
343
83007196 344 rate = il_get_lowest_plcp(il);
4bc85c13 345
46bc8d4b 346 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
4bc85c13 347
e7392364 348 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
4bc85c13 349
46bc8d4b 350 il3945_free_frame(il, frame);
4bc85c13
WYG
351
352 return rc;
353}
354
e7392364
SG
355static void
356il3945_unset_hw_params(struct il_priv *il)
4bc85c13 357{
46bc8d4b
SG
358 if (il->_3945.shared_virt)
359 dma_free_coherent(&il->pci_dev->dev,
e2ebc833 360 sizeof(struct il3945_shared),
e7392364 361 il->_3945.shared_virt, il->_3945.shared_phys);
4bc85c13
WYG
362}
363
e7392364
SG
364static void
365il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
366 struct il_device_cmd *cmd,
367 struct sk_buff *skb_frag, int sta_id)
4bc85c13 368{
e2ebc833 369 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
46bc8d4b 370 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
4bc85c13
WYG
371
372 tx_cmd->sec_ctl = 0;
373
374 switch (keyinfo->cipher) {
375 case WLAN_CIPHER_SUITE_CCMP:
376 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
377 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
58de00a4 378 D_TX("tx_cmd with AES hwcrypto\n");
4bc85c13
WYG
379 break;
380
381 case WLAN_CIPHER_SUITE_TKIP:
382 break;
383
384 case WLAN_CIPHER_SUITE_WEP104:
385 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
386 /* fall through */
387 case WLAN_CIPHER_SUITE_WEP40:
e7392364
SG
388 tx_cmd->sec_ctl |=
389 TX_CMD_SEC_WEP | (info->control.hw_key->
390 hw_key_idx & TX_CMD_SEC_MSK) <<
391 TX_CMD_SEC_SHIFT;
4bc85c13
WYG
392
393 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
394
e7392364
SG
395 D_TX("Configuring packet for WEP encryption " "with key %d\n",
396 info->control.hw_key->hw_key_idx);
4bc85c13
WYG
397 break;
398
399 default:
9406f797 400 IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
4bc85c13
WYG
401 break;
402 }
403}
404
405/*
4d69c752 406 * handle build C_TX command notification.
4bc85c13 407 */
e7392364
SG
408static void
409il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
410 struct ieee80211_tx_info *info,
411 struct ieee80211_hdr *hdr, u8 std_id)
4bc85c13 412{
e2ebc833 413 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
4bc85c13
WYG
414 __le32 tx_flags = tx_cmd->tx_flags;
415 __le16 fc = hdr->frame_control;
416
417 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
418 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
419 tx_flags |= TX_CMD_FLG_ACK_MSK;
420 if (ieee80211_is_mgmt(fc))
421 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
422 if (ieee80211_is_probe_resp(fc) &&
423 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
424 tx_flags |= TX_CMD_FLG_TSF_MSK;
425 } else {
426 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
427 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
428 }
429
430 tx_cmd->sta_id = std_id;
431 if (ieee80211_has_morefrags(fc))
432 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
433
434 if (ieee80211_is_data_qos(fc)) {
435 u8 *qc = ieee80211_get_qos_ctl(hdr);
436 tx_cmd->tid_tspec = qc[0] & 0xf;
437 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
438 } else {
439 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
440 }
441
46bc8d4b 442 il_tx_cmd_protection(il, info, fc, &tx_flags);
4bc85c13
WYG
443
444 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
445 if (ieee80211_is_mgmt(fc)) {
446 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
447 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
448 else
449 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
450 } else {
451 tx_cmd->timeout.pm_frame_timeout = 0;
452 }
453
454 tx_cmd->driver_txop = 0;
455 tx_cmd->tx_flags = tx_flags;
456 tx_cmd->next_frame_len = 0;
457}
458
459/*
4d69c752 460 * start C_TX command process
4bc85c13 461 */
e7392364
SG
462static int
463il3945_tx_skb(struct il_priv *il, struct sk_buff *skb)
4bc85c13
WYG
464{
465 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
466 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e2ebc833
SG
467 struct il3945_tx_cmd *tx_cmd;
468 struct il_tx_queue *txq = NULL;
469 struct il_queue *q = NULL;
470 struct il_device_cmd *out_cmd;
471 struct il_cmd_meta *out_meta;
4bc85c13
WYG
472 dma_addr_t phys_addr;
473 dma_addr_t txcmd_phys;
474 int txq_id = skb_get_queue_mapping(skb);
475 u16 len, idx, hdr_len;
476 u8 id;
477 u8 unicast;
478 u8 sta_id;
479 u8 tid = 0;
480 __le16 fc;
481 u8 wait_write_ptr = 0;
482 unsigned long flags;
483
46bc8d4b
SG
484 spin_lock_irqsave(&il->lock, flags);
485 if (il_is_rfkill(il)) {
58de00a4 486 D_DROP("Dropping - RF KILL\n");
4bc85c13
WYG
487 goto drop_unlock;
488 }
489
e7392364
SG
490 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
491 IL_INVALID_RATE) {
9406f797 492 IL_ERR("ERROR: No TX rate available.\n");
4bc85c13
WYG
493 goto drop_unlock;
494 }
495
496 unicast = !is_multicast_ether_addr(hdr->addr1);
497 id = 0;
498
499 fc = hdr->frame_control;
500
d3175167 501#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13 502 if (ieee80211_is_auth(fc))
58de00a4 503 D_TX("Sending AUTH frame\n");
4bc85c13 504 else if (ieee80211_is_assoc_req(fc))
58de00a4 505 D_TX("Sending ASSOC frame\n");
4bc85c13 506 else if (ieee80211_is_reassoc_req(fc))
58de00a4 507 D_TX("Sending REASSOC frame\n");
4bc85c13
WYG
508#endif
509
46bc8d4b 510 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
511
512 hdr_len = ieee80211_hdrlen(fc);
513
0c2c8852 514 /* Find idx into station table for destination station */
83007196 515 sta_id = il_sta_id_or_broadcast(il, info->control.sta);
e2ebc833 516 if (sta_id == IL_INVALID_STATION) {
e7392364 517 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
4bc85c13
WYG
518 goto drop;
519 }
520
58de00a4 521 D_RATE("station Id %d\n", sta_id);
4bc85c13
WYG
522
523 if (ieee80211_is_data_qos(fc)) {
524 u8 *qc = ieee80211_get_qos_ctl(hdr);
525 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
526 if (unlikely(tid >= MAX_TID_COUNT))
527 goto drop;
528 }
529
530 /* Descriptor for chosen Tx queue */
46bc8d4b 531 txq = &il->txq[txq_id];
4bc85c13
WYG
532 q = &txq->q;
533
e2ebc833 534 if ((il_queue_space(q) < q->high_mark))
4bc85c13
WYG
535 goto drop;
536
46bc8d4b 537 spin_lock_irqsave(&il->lock, flags);
4bc85c13 538
0c2c8852 539 idx = il_get_cmd_idx(q, q->write_ptr, 0);
4bc85c13 540
00ea99e1 541 txq->skbs[q->write_ptr] = skb;
4bc85c13
WYG
542
543 /* Init first empty entry in queue's array of Tx/cmd buffers */
544 out_cmd = txq->cmd[idx];
545 out_meta = &txq->meta[idx];
e2ebc833 546 tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
4bc85c13
WYG
547 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
548 memset(tx_cmd, 0, sizeof(*tx_cmd));
549
550 /*
551 * Set up the Tx-command (not MAC!) header.
0c2c8852 552 * Store the chosen Tx queue and TFD idx within the sequence field;
4bc85c13
WYG
553 * after Tx, uCode's Tx response will return this value so driver can
554 * locate the frame within the tx queue and do post-tx processing.
555 */
4d69c752 556 out_cmd->hdr.cmd = C_TX;
e7392364
SG
557 out_cmd->hdr.sequence =
558 cpu_to_le16((u16)
559 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
4bc85c13
WYG
560
561 /* Copy MAC header from skb into command buffer */
562 memcpy(tx_cmd->hdr, hdr, hdr_len);
563
4bc85c13 564 if (info->control.hw_key)
46bc8d4b 565 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
4bc85c13
WYG
566
567 /* TODO need this for burst mode later on */
46bc8d4b 568 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
4bc85c13 569
81fb4613 570 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
4bc85c13
WYG
571
572 /* Total # bytes to be transmitted */
e7392364 573 len = (u16) skb->len;
4bc85c13
WYG
574 tx_cmd->len = cpu_to_le16(len);
575
46bc8d4b
SG
576 il_dbg_log_tx_data_frame(il, len, hdr);
577 il_update_stats(il, true, fc, len);
4bc85c13
WYG
578 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
579 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
580
581 if (!ieee80211_has_morefrags(hdr->frame_control)) {
582 txq->need_update = 1;
583 } else {
584 wait_write_ptr = 1;
585 txq->need_update = 0;
586 }
587
e7392364 588 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
58de00a4 589 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
46bc8d4b 590 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
e7392364
SG
591 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
592 ieee80211_hdrlen(fc));
4bc85c13
WYG
593
594 /*
595 * Use the first empty entry in this queue's command buffer array
596 * to contain the Tx command and MAC header concatenated together
597 * (payload data will be in another buffer).
598 * Size of this varies, due to varying MAC header length.
599 * If end is not dword aligned, we'll have 2 extra bytes at the end
600 * of the MAC header (device reads on dword boundaries).
601 * We'll tell device about this padding later.
602 */
e7392364
SG
603 len =
604 sizeof(struct il3945_tx_cmd) + sizeof(struct il_cmd_header) +
605 hdr_len;
4bc85c13
WYG
606 len = (len + 3) & ~3;
607
608 /* Physical address of this Tx command's header (not MAC header!),
609 * within command buffer array. */
e7392364
SG
610 txcmd_phys =
611 pci_map_single(il->pci_dev, &out_cmd->hdr, len, PCI_DMA_TODEVICE);
4bc85c13
WYG
612 /* we do not map meta data ... so we can safely access address to
613 * provide to unmap command*/
614 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
615 dma_unmap_len_set(out_meta, len, len);
616
617 /* Add buffer containing Tx command and MAC(!) header to TFD's
618 * first entry */
c39ae9fd 619 il->ops->lib->txq_attach_buf_to_tfd(il, txq, txcmd_phys, len, 1, 0);
4bc85c13
WYG
620
621 /* Set up TFD's 2nd entry to point directly to remainder of skb,
622 * if any (802.11 null frames have no payload). */
623 len = skb->len - hdr_len;
624 if (len) {
e7392364
SG
625 phys_addr =
626 pci_map_single(il->pci_dev, skb->data + hdr_len, len,
627 PCI_DMA_TODEVICE);
c39ae9fd
SG
628 il->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr, len, 0,
629 U32_PAD(len));
4bc85c13
WYG
630 }
631
0c2c8852 632 /* Tell device the write idx *just past* this latest filled TFD */
e2ebc833 633 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
46bc8d4b
SG
634 il_txq_update_write_ptr(il, txq);
635 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 636
e7392364 637 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
4bc85c13 638 if (wait_write_ptr) {
46bc8d4b 639 spin_lock_irqsave(&il->lock, flags);
4bc85c13 640 txq->need_update = 1;
46bc8d4b
SG
641 il_txq_update_write_ptr(il, txq);
642 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
643 }
644
46bc8d4b 645 il_stop_queue(il, txq);
4bc85c13
WYG
646 }
647
648 return 0;
649
650drop_unlock:
46bc8d4b 651 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
652drop:
653 return -1;
654}
655
e7392364
SG
656static int
657il3945_get_measurement(struct il_priv *il,
658 struct ieee80211_measurement_params *params, u8 type)
4bc85c13 659{
e2ebc833 660 struct il_spectrum_cmd spectrum;
dcae1c64 661 struct il_rx_pkt *pkt;
e2ebc833 662 struct il_host_cmd cmd = {
4d69c752 663 .id = C_SPECTRUM_MEASUREMENT,
4bc85c13
WYG
664 .data = (void *)&spectrum,
665 .flags = CMD_WANT_SKB,
666 };
667 u32 add_time = le64_to_cpu(params->start_time);
668 int rc;
669 int spectrum_resp_status;
670 int duration = le16_to_cpu(params->duration);
4bc85c13 671
7c2cde2e 672 if (il_is_associated(il))
e7392364
SG
673 add_time =
674 il_usecs_to_beacons(il,
675 le64_to_cpu(params->start_time) -
676 il->_3945.last_tsf,
c8b03958 677 le16_to_cpu(il->timing.beacon_interval));
4bc85c13
WYG
678
679 memset(&spectrum, 0, sizeof(spectrum));
680
681 spectrum.channel_count = cpu_to_le16(1);
682 spectrum.flags =
683 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
684 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
685 cmd.len = sizeof(spectrum);
686 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
687
7c2cde2e 688 if (il_is_associated(il))
4bc85c13 689 spectrum.start_time =
e7392364 690 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
c8b03958 691 le16_to_cpu(il->timing.beacon_interval));
4bc85c13
WYG
692 else
693 spectrum.start_time = 0;
694
695 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
696 spectrum.channels[0].channel = params->channel;
697 spectrum.channels[0].type = type;
c8b03958 698 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
e7392364
SG
699 spectrum.flags |=
700 RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
701 RXON_FLG_TGG_PROTECT_MSK;
4bc85c13 702
46bc8d4b 703 rc = il_send_cmd_sync(il, &cmd);
4bc85c13
WYG
704 if (rc)
705 return rc;
706
dcae1c64 707 pkt = (struct il_rx_pkt *)cmd.reply_page;
e2ebc833 708 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
4d69c752 709 IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
4bc85c13
WYG
710 rc = -EIO;
711 }
712
713 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
714 switch (spectrum_resp_status) {
715 case 0: /* Command will be handled */
716 if (pkt->u.spectrum.id != 0xff) {
58de00a4 717 D_INFO("Replaced existing measurement: %d\n",
e7392364 718 pkt->u.spectrum.id);
46bc8d4b 719 il->measurement_status &= ~MEASUREMENT_READY;
4bc85c13 720 }
46bc8d4b 721 il->measurement_status |= MEASUREMENT_ACTIVE;
4bc85c13
WYG
722 rc = 0;
723 break;
724
725 case 1: /* Command will not be handled */
726 rc = -EAGAIN;
727 break;
728 }
729
46bc8d4b 730 il_free_pages(il, cmd.reply_page);
4bc85c13
WYG
731
732 return rc;
733}
734
e7392364
SG
735static void
736il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 737{
dcae1c64 738 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 739 struct il_alive_resp *palive;
4bc85c13
WYG
740 struct delayed_work *pwork;
741
742 palive = &pkt->u.alive_frame;
743
e7392364
SG
744 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
745 palive->is_valid, palive->ver_type, palive->ver_subtype);
4bc85c13
WYG
746
747 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
58de00a4 748 D_INFO("Initialization Alive received.\n");
46bc8d4b 749 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
e2ebc833 750 sizeof(struct il_alive_resp));
46bc8d4b 751 pwork = &il->init_alive_start;
4bc85c13 752 } else {
58de00a4 753 D_INFO("Runtime Alive received.\n");
46bc8d4b 754 memcpy(&il->card_alive, &pkt->u.alive_frame,
e2ebc833 755 sizeof(struct il_alive_resp));
46bc8d4b
SG
756 pwork = &il->alive_start;
757 il3945_disable_events(il);
4bc85c13
WYG
758 }
759
760 /* We delay the ALIVE response by 5ms to
761 * give the HW RF Kill time to activate... */
762 if (palive->is_valid == UCODE_VALID_OK)
e7392364 763 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
4bc85c13 764 else
9406f797 765 IL_WARN("uCode did not respond OK.\n");
4bc85c13
WYG
766}
767
e7392364
SG
768static void
769il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 770{
d3175167 771#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 772 struct il_rx_pkt *pkt = rxb_addr(rxb);
4bc85c13
WYG
773#endif
774
4d69c752 775 D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
4bc85c13
WYG
776}
777
e7392364
SG
778static void
779il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 780{
dcae1c64 781 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 782 struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
d3175167 783#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
784 u8 rate = beacon->beacon_notify_hdr.rate;
785
e7392364
SG
786 D_RX("beacon status %x retries %d iss %d " "tsf %d %d rate %d\n",
787 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
788 beacon->beacon_notify_hdr.failure_frame,
789 le32_to_cpu(beacon->ibss_mgr_status),
790 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
4bc85c13
WYG
791#endif
792
46bc8d4b 793 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
4bc85c13 794
4bc85c13
WYG
795}
796
797/* Handle notification from uCode that card's power state is changing
798 * due to software, hardware, or critical temperature RFKILL */
e7392364
SG
799static void
800il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
4bc85c13 801{
dcae1c64 802 struct il_rx_pkt *pkt = rxb_addr(rxb);
4bc85c13 803 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
46bc8d4b 804 unsigned long status = il->status;
4bc85c13 805
9406f797 806 IL_WARN("Card state received: HW:%s SW:%s\n",
e7392364
SG
807 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
808 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
4bc85c13 809
e7392364 810 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4bc85c13
WYG
811
812 if (flags & HW_CARD_DISABLED)
a6766ccd 813 set_bit(S_RF_KILL_HW, &il->status);
4bc85c13 814 else
a6766ccd 815 clear_bit(S_RF_KILL_HW, &il->status);
4bc85c13 816
46bc8d4b 817 il_scan_cancel(il);
4bc85c13 818
a6766ccd
SG
819 if ((test_bit(S_RF_KILL_HW, &status) !=
820 test_bit(S_RF_KILL_HW, &il->status)))
46bc8d4b 821 wiphy_rfkill_set_hw_state(il->hw->wiphy,
e7392364 822 test_bit(S_RF_KILL_HW, &il->status));
4bc85c13 823 else
46bc8d4b 824 wake_up(&il->wait_command_queue);
4bc85c13
WYG
825}
826
827/**
d0c72347 828 * il3945_setup_handlers - Initialize Rx handler callbacks
4bc85c13
WYG
829 *
830 * Setup the RX handlers for each of the reply types sent from the uCode
831 * to the host.
832 *
833 * This function chains into the hardware specific files for them to setup
834 * any hardware specific handlers as well.
835 */
e7392364
SG
836static void
837il3945_setup_handlers(struct il_priv *il)
4bc85c13 838{
6e9848b4
SG
839 il->handlers[N_ALIVE] = il3945_hdl_alive;
840 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
841 il->handlers[N_ERROR] = il_hdl_error;
d2dfb33e 842 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
e7392364 843 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
d2dfb33e 844 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
e7392364 845 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
d2dfb33e 846 il->handlers[N_BEACON] = il3945_hdl_beacon;
4bc85c13
WYG
847
848 /*
849 * The same handler is used for both the REPLY to a discrete
ebf0d90d
SG
850 * stats request from the host as well as for the periodic
851 * stats notifications (after received beacons) from the uCode.
4bc85c13 852 */
d2dfb33e
SG
853 il->handlers[C_STATS] = il3945_hdl_c_stats;
854 il->handlers[N_STATS] = il3945_hdl_stats;
4bc85c13 855
46bc8d4b 856 il_setup_rx_scan_handlers(il);
d2dfb33e 857 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
4bc85c13
WYG
858
859 /* Set up hardware specific Rx handlers */
d0c72347 860 il3945_hw_handler_setup(il);
4bc85c13
WYG
861}
862
863/************************** RX-FUNCTIONS ****************************/
864/*
865 * Rx theory of operation
866 *
867 * The host allocates 32 DMA target addresses and passes the host address
3b98c7f4 868 * to the firmware at register IL_RFDS_TBL_LOWER + N * RFD_SIZE where N is
4bc85c13
WYG
869 * 0 to 31
870 *
871 * Rx Queue Indexes
0c2c8852 872 * The host/firmware share two idx registers for managing the Rx buffers.
4bc85c13 873 *
0c2c8852 874 * The READ idx maps to the first position that the firmware may be writing
4bc85c13
WYG
875 * to -- the driver can read up to (but not including) this position and get
876 * good data.
0c2c8852 877 * The READ idx is managed by the firmware once the card is enabled.
4bc85c13 878 *
0c2c8852 879 * The WRITE idx maps to the last position the driver has read from -- the
4bc85c13
WYG
880 * position preceding WRITE is the last slot the firmware can place a packet.
881 *
882 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
883 * WRITE = READ.
884 *
885 * During initialization, the host sets up the READ queue position to the first
2d09b062 886 * IDX position, and WRITE to the last (READ - 1 wrapped)
4bc85c13 887 *
0c2c8852
SG
888 * When the firmware places a packet in a buffer, it will advance the READ idx
889 * and fire the RX interrupt. The driver can then query the READ idx and
890 * process as many packets as possible, moving the WRITE idx forward as it
4bc85c13
WYG
891 * resets the Rx queue buffers with new memory.
892 *
893 * The management in the driver is as follows:
894 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
895 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
896 * to replenish the iwl->rxq->rx_free.
e2ebc833 897 * + In il3945_rx_replenish (scheduled) if 'processed' != 'read' then the
2d09b062 898 * iwl->rxq is replenished and the READ IDX is updated (updating the
0c2c8852 899 * 'processed' and 'read' driver idxes as well)
4bc85c13 900 * + A received packet is processed and handed to the kernel network stack,
0c2c8852 901 * detached from the iwl->rxq. The driver 'processed' idx is updated.
4bc85c13
WYG
902 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
903 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2d09b062 904 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
4bc85c13
WYG
905 * were enough free buffers and RX_STALLED is set it is cleared.
906 *
907 *
908 * Driver sequence:
909 *
e2ebc833
SG
910 * il3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
911 * il3945_rx_queue_restock
912 * il3945_rx_queue_restock() Moves available buffers from rx_free into Rx
4bc85c13 913 * queue, updates firmware pointers, and updates
0c2c8852 914 * the WRITE idx. If insufficient rx_free buffers
e2ebc833 915 * are available, schedules il3945_rx_replenish
4bc85c13
WYG
916 *
917 * -- enable interrupts --
b73bb5f1 918 * ISR - il3945_rx() Detach il_rx_bufs from pool up to the
2d09b062 919 * READ IDX, detaching the SKB from the pool.
4bc85c13 920 * Moves the packet buffer from queue to rx_used.
e2ebc833 921 * Calls il3945_rx_queue_restock to refill any empty
4bc85c13
WYG
922 * slots.
923 * ...
924 *
925 */
926
927/**
e2ebc833 928 * il3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
4bc85c13 929 */
e7392364
SG
930static inline __le32
931il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
4bc85c13 932{
e7392364 933 return cpu_to_le32((u32) dma_addr);
4bc85c13
WYG
934}
935
936/**
e2ebc833 937 * il3945_rx_queue_restock - refill RX queue from pre-allocated pool
4bc85c13
WYG
938 *
939 * If there are slots in the RX queue that need to be restocked,
940 * and we have free pre-allocated buffers, fill the ranks as much
941 * as we can, pulling from rx_free.
942 *
0c2c8852 943 * This moves the 'write' idx forward to catch up with 'processed', and
4bc85c13
WYG
944 * also updates the memory address in the firmware to reference the new
945 * target buffer.
946 */
e7392364
SG
947static void
948il3945_rx_queue_restock(struct il_priv *il)
4bc85c13 949{
46bc8d4b 950 struct il_rx_queue *rxq = &il->rxq;
4bc85c13 951 struct list_head *element;
b73bb5f1 952 struct il_rx_buf *rxb;
4bc85c13
WYG
953 unsigned long flags;
954 int write;
955
956 spin_lock_irqsave(&rxq->lock, flags);
957 write = rxq->write & ~0x7;
232913b5 958 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
4bc85c13
WYG
959 /* Get next free Rx buffer, remove from free list */
960 element = rxq->rx_free.next;
b73bb5f1 961 rxb = list_entry(element, struct il_rx_buf, list);
4bc85c13
WYG
962 list_del(element);
963
964 /* Point to Rx buffer via next RBD in circular buffer */
e7392364
SG
965 rxq->bd[rxq->write] =
966 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
4bc85c13
WYG
967 rxq->queue[rxq->write] = rxb;
968 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
969 rxq->free_count--;
970 }
971 spin_unlock_irqrestore(&rxq->lock, flags);
972 /* If the pre-allocated buffer pool is dropping low, schedule to
973 * refill it */
974 if (rxq->free_count <= RX_LOW_WATERMARK)
46bc8d4b 975 queue_work(il->workqueue, &il->rx_replenish);
4bc85c13 976
4bc85c13
WYG
977 /* If we've added more space for the firmware to place data, tell it.
978 * Increment device's write pointer in multiples of 8. */
232913b5
SG
979 if (rxq->write_actual != (rxq->write & ~0x7) ||
980 abs(rxq->write - rxq->read) > 7) {
4bc85c13
WYG
981 spin_lock_irqsave(&rxq->lock, flags);
982 rxq->need_update = 1;
983 spin_unlock_irqrestore(&rxq->lock, flags);
46bc8d4b 984 il_rx_queue_update_write_ptr(il, rxq);
4bc85c13
WYG
985 }
986}
987
988/**
e2ebc833 989 * il3945_rx_replenish - Move all used packet from rx_used to rx_free
4bc85c13
WYG
990 *
991 * When moving to rx_free an SKB is allocated for the slot.
992 *
e2ebc833 993 * Also restock the Rx queue via il3945_rx_queue_restock.
4bc85c13
WYG
994 * This is called as a scheduled work item (except for during initialization)
995 */
e7392364
SG
996static void
997il3945_rx_allocate(struct il_priv *il, gfp_t priority)
4bc85c13 998{
46bc8d4b 999 struct il_rx_queue *rxq = &il->rxq;
4bc85c13 1000 struct list_head *element;
b73bb5f1 1001 struct il_rx_buf *rxb;
4bc85c13
WYG
1002 struct page *page;
1003 unsigned long flags;
1004 gfp_t gfp_mask = priority;
1005
1006 while (1) {
1007 spin_lock_irqsave(&rxq->lock, flags);
1008
1009 if (list_empty(&rxq->rx_used)) {
1010 spin_unlock_irqrestore(&rxq->lock, flags);
1011 return;
1012 }
1013 spin_unlock_irqrestore(&rxq->lock, flags);
1014
1015 if (rxq->free_count > RX_LOW_WATERMARK)
1016 gfp_mask |= __GFP_NOWARN;
1017
46bc8d4b 1018 if (il->hw_params.rx_page_order > 0)
4bc85c13
WYG
1019 gfp_mask |= __GFP_COMP;
1020
1021 /* Alloc a new receive buffer */
46bc8d4b 1022 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
4bc85c13
WYG
1023 if (!page) {
1024 if (net_ratelimit())
58de00a4 1025 D_INFO("Failed to allocate SKB buffer.\n");
232913b5 1026 if (rxq->free_count <= RX_LOW_WATERMARK &&
4bc85c13 1027 net_ratelimit())
1722f8e1
SG
1028 IL_ERR("Failed to allocate SKB buffer with %0x."
1029 "Only %u free buffers remaining.\n",
1030 priority, rxq->free_count);
4bc85c13
WYG
1031 /* We don't reschedule replenish work here -- we will
1032 * call the restock method and if it still needs
1033 * more buffers it will schedule replenish */
1034 break;
1035 }
1036
1037 spin_lock_irqsave(&rxq->lock, flags);
1038 if (list_empty(&rxq->rx_used)) {
1039 spin_unlock_irqrestore(&rxq->lock, flags);
46bc8d4b 1040 __free_pages(page, il->hw_params.rx_page_order);
4bc85c13
WYG
1041 return;
1042 }
1043 element = rxq->rx_used.next;
b73bb5f1 1044 rxb = list_entry(element, struct il_rx_buf, list);
4bc85c13
WYG
1045 list_del(element);
1046 spin_unlock_irqrestore(&rxq->lock, flags);
1047
1048 rxb->page = page;
1049 /* Get physical address of RB/SKB */
e7392364
SG
1050 rxb->page_dma =
1051 pci_map_page(il->pci_dev, page, 0,
1052 PAGE_SIZE << il->hw_params.rx_page_order,
1053 PCI_DMA_FROMDEVICE);
4bc85c13
WYG
1054
1055 spin_lock_irqsave(&rxq->lock, flags);
1056
1057 list_add_tail(&rxb->list, &rxq->rx_free);
1058 rxq->free_count++;
46bc8d4b 1059 il->alloc_rxb_page++;
4bc85c13
WYG
1060
1061 spin_unlock_irqrestore(&rxq->lock, flags);
1062 }
1063}
1064
e7392364
SG
1065void
1066il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
4bc85c13
WYG
1067{
1068 unsigned long flags;
1069 int i;
1070 spin_lock_irqsave(&rxq->lock, flags);
1071 INIT_LIST_HEAD(&rxq->rx_free);
1072 INIT_LIST_HEAD(&rxq->rx_used);
1073 /* Fill the rx_used queue with _all_ of the Rx buffers */
1074 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1075 /* In the reset function, these buffers may have been allocated
1076 * to an SKB, so we need to unmap and free potential storage */
1077 if (rxq->pool[i].page != NULL) {
46bc8d4b 1078 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG
1079 PAGE_SIZE << il->hw_params.rx_page_order,
1080 PCI_DMA_FROMDEVICE);
46bc8d4b 1081 __il_free_pages(il, rxq->pool[i].page);
4bc85c13
WYG
1082 rxq->pool[i].page = NULL;
1083 }
1084 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1085 }
1086
1087 /* Set us so that we have processed and used all buffers, but have
1088 * not restocked the Rx queue with fresh buffers */
1089 rxq->read = rxq->write = 0;
1090 rxq->write_actual = 0;
1091 rxq->free_count = 0;
1092 spin_unlock_irqrestore(&rxq->lock, flags);
1093}
1094
e7392364
SG
1095void
1096il3945_rx_replenish(void *data)
4bc85c13 1097{
46bc8d4b 1098 struct il_priv *il = data;
4bc85c13
WYG
1099 unsigned long flags;
1100
46bc8d4b 1101 il3945_rx_allocate(il, GFP_KERNEL);
4bc85c13 1102
46bc8d4b
SG
1103 spin_lock_irqsave(&il->lock, flags);
1104 il3945_rx_queue_restock(il);
1105 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
1106}
1107
e7392364
SG
1108static void
1109il3945_rx_replenish_now(struct il_priv *il)
4bc85c13 1110{
46bc8d4b 1111 il3945_rx_allocate(il, GFP_ATOMIC);
4bc85c13 1112
46bc8d4b 1113 il3945_rx_queue_restock(il);
4bc85c13
WYG
1114}
1115
4bc85c13
WYG
1116/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1117 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1118 * This free routine walks the list of POOL entries and if SKB is set to
1119 * non NULL it is unmapped and freed
1120 */
e7392364
SG
1121static void
1122il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
4bc85c13
WYG
1123{
1124 int i;
1125 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1126 if (rxq->pool[i].page != NULL) {
46bc8d4b 1127 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
e7392364
SG
1128 PAGE_SIZE << il->hw_params.rx_page_order,
1129 PCI_DMA_FROMDEVICE);
46bc8d4b 1130 __il_free_pages(il, rxq->pool[i].page);
4bc85c13
WYG
1131 rxq->pool[i].page = NULL;
1132 }
1133 }
1134
46bc8d4b 1135 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
4bc85c13 1136 rxq->bd_dma);
46bc8d4b 1137 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
4bc85c13
WYG
1138 rxq->rb_stts, rxq->rb_stts_dma);
1139 rxq->bd = NULL;
e7392364 1140 rxq->rb_stts = NULL;
4bc85c13
WYG
1141}
1142
4bc85c13
WYG
1143/* Convert linear signal-to-noise ratio into dB */
1144static u8 ratio2dB[100] = {
1145/* 0 1 2 3 4 5 6 7 8 9 */
e7392364
SG
1146 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1147 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1148 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1149 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1150 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1151 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1152 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1153 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1154 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1155 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
4bc85c13
WYG
1156};
1157
1158/* Calculates a relative dB value from a ratio of linear
1159 * (i.e. not dB) signal levels.
1160 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
e7392364
SG
1161int
1162il3945_calc_db_from_ratio(int sig_ratio)
4bc85c13
WYG
1163{
1164 /* 1000:1 or higher just report as 60 dB */
1165 if (sig_ratio >= 1000)
1166 return 60;
1167
1168 /* 100:1 or higher, divide by 10 and use table,
1169 * add 20 dB to make up for divide by 10 */
1170 if (sig_ratio >= 100)
e7392364 1171 return 20 + (int)ratio2dB[sig_ratio / 10];
4bc85c13
WYG
1172
1173 /* We shouldn't see this */
1174 if (sig_ratio < 1)
1175 return 0;
1176
1177 /* Use table for ratios 1:1 - 99:1 */
1178 return (int)ratio2dB[sig_ratio];
1179}
1180
1181/**
e2ebc833 1182 * il3945_rx_handle - Main entry function for receiving responses from uCode
4bc85c13 1183 *
d0c72347 1184 * Uses the il->handlers callback function array to invoke
4bc85c13
WYG
1185 * the appropriate handlers, including command responses,
1186 * frame-received notifications, and other notifications.
1187 */
e7392364
SG
1188static void
1189il3945_rx_handle(struct il_priv *il)
4bc85c13 1190{
b73bb5f1 1191 struct il_rx_buf *rxb;
dcae1c64 1192 struct il_rx_pkt *pkt;
46bc8d4b 1193 struct il_rx_queue *rxq = &il->rxq;
4bc85c13
WYG
1194 u32 r, i;
1195 int reclaim;
1196 unsigned long flags;
1197 u8 fill_rx = 0;
1198 u32 count = 8;
1199 int total_empty = 0;
1200
0c2c8852 1201 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
4bc85c13 1202 * buffer that the driver may process (last buffer filled by ucode). */
e7392364 1203 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
4bc85c13
WYG
1204 i = rxq->read;
1205
1206 /* calculate total frames need to be restock after handling RX */
1207 total_empty = r - rxq->write_actual;
1208 if (total_empty < 0)
1209 total_empty += RX_QUEUE_SIZE;
1210
1211 if (total_empty > (RX_QUEUE_SIZE / 2))
1212 fill_rx = 1;
1213 /* Rx interrupt, but nothing sent from uCode */
1214 if (i == r)
58de00a4 1215 D_RX("r = %d, i = %d\n", r, i);
4bc85c13
WYG
1216
1217 while (i != r) {
1218 int len;
1219
1220 rxb = rxq->queue[i];
1221
1222 /* If an RXB doesn't have a Rx queue slot associated with it,
1223 * then a bug has been introduced in the queue refilling
1224 * routines -- catch it here */
1225 BUG_ON(rxb == NULL);
1226
1227 rxq->queue[i] = NULL;
1228
46bc8d4b
SG
1229 pci_unmap_page(il->pci_dev, rxb->page_dma,
1230 PAGE_SIZE << il->hw_params.rx_page_order,
4bc85c13
WYG
1231 PCI_DMA_FROMDEVICE);
1232 pkt = rxb_addr(rxb);
1233
e94a4099 1234 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364 1235 len += sizeof(u32); /* account for status word */
4bc85c13
WYG
1236
1237 /* Reclaim a command buffer only if this packet is a response
1238 * to a (driver-originated) command.
1239 * If the packet (e.g. Rx frame) originated from uCode,
1240 * there is no command buffer to reclaim.
1241 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1242 * but apparently a few don't get set; catch them here. */
1243 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
e7392364 1244 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX;
4bc85c13
WYG
1245
1246 /* Based on type of command response or notification,
1247 * handle those that need handling via function in
d0c72347
SG
1248 * handlers table. See il3945_setup_handlers() */
1249 if (il->handlers[pkt->hdr.cmd]) {
58de00a4 1250 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
e7392364 1251 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
d0c72347
SG
1252 il->isr_stats.handlers[pkt->hdr.cmd]++;
1253 il->handlers[pkt->hdr.cmd] (il, rxb);
4bc85c13
WYG
1254 } else {
1255 /* No handling needed */
e7392364
SG
1256 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
1257 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4bc85c13
WYG
1258 }
1259
1260 /*
1261 * XXX: After here, we should always check rxb->page
1262 * against NULL before touching it or its virtual
d0c72347 1263 * memory (pkt). Because some handler might have
4bc85c13
WYG
1264 * already taken or freed the pages.
1265 */
1266
1267 if (reclaim) {
1268 /* Invoke any callbacks, transfer the buffer to caller,
e2ebc833 1269 * and fire off the (possibly) blocking il_send_cmd()
4bc85c13
WYG
1270 * as we reclaim the driver command queue */
1271 if (rxb->page)
46bc8d4b 1272 il_tx_cmd_complete(il, rxb);
4bc85c13 1273 else
9406f797 1274 IL_WARN("Claim null rxb?\n");
4bc85c13
WYG
1275 }
1276
1277 /* Reuse the page if possible. For notification packets and
1278 * SKBs that fail to Rx correctly, add them back into the
1279 * rx_free list for reuse later. */
1280 spin_lock_irqsave(&rxq->lock, flags);
1281 if (rxb->page != NULL) {
e7392364
SG
1282 rxb->page_dma =
1283 pci_map_page(il->pci_dev, rxb->page, 0,
1284 PAGE_SIZE << il->hw_params.
1285 rx_page_order, PCI_DMA_FROMDEVICE);
4bc85c13
WYG
1286 list_add_tail(&rxb->list, &rxq->rx_free);
1287 rxq->free_count++;
1288 } else
1289 list_add_tail(&rxb->list, &rxq->rx_used);
1290
1291 spin_unlock_irqrestore(&rxq->lock, flags);
1292
1293 i = (i + 1) & RX_QUEUE_MASK;
1294 /* If there are a lot of unused frames,
1295 * restock the Rx queue so ucode won't assert. */
1296 if (fill_rx) {
1297 count++;
1298 if (count >= 8) {
1299 rxq->read = i;
46bc8d4b 1300 il3945_rx_replenish_now(il);
4bc85c13
WYG
1301 count = 0;
1302 }
1303 }
1304 }
1305
1306 /* Backtrack one entry */
1307 rxq->read = i;
1308 if (fill_rx)
46bc8d4b 1309 il3945_rx_replenish_now(il);
4bc85c13 1310 else
46bc8d4b 1311 il3945_rx_queue_restock(il);
4bc85c13
WYG
1312}
1313
1314/* call this function to flush any scheduled tasklet */
e7392364
SG
1315static inline void
1316il3945_synchronize_irq(struct il_priv *il)
4bc85c13 1317{
e7392364 1318 /* wait to make sure we flush pending tasklet */
46bc8d4b
SG
1319 synchronize_irq(il->pci_dev->irq);
1320 tasklet_kill(&il->irq_tasklet);
4bc85c13
WYG
1321}
1322
e7392364
SG
1323static const char *
1324il3945_desc_lookup(int i)
4bc85c13
WYG
1325{
1326 switch (i) {
1327 case 1:
1328 return "FAIL";
1329 case 2:
1330 return "BAD_PARAM";
1331 case 3:
1332 return "BAD_CHECKSUM";
1333 case 4:
1334 return "NMI_INTERRUPT";
1335 case 5:
1336 return "SYSASSERT";
1337 case 6:
1338 return "FATAL_ERROR";
1339 }
1340
1341 return "UNKNOWN";
1342}
1343
1344#define ERROR_START_OFFSET (1 * sizeof(u32))
1345#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1346
e7392364
SG
1347void
1348il3945_dump_nic_error_log(struct il_priv *il)
4bc85c13
WYG
1349{
1350 u32 i;
1351 u32 desc, time, count, base, data1;
1352 u32 blink1, blink2, ilink1, ilink2;
1353
46bc8d4b 1354 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
4bc85c13 1355
e2ebc833 1356 if (!il3945_hw_valid_rtc_data_addr(base)) {
9406f797 1357 IL_ERR("Not valid error log pointer 0x%08X\n", base);
4bc85c13
WYG
1358 return;
1359 }
1360
46bc8d4b 1361 count = il_read_targ_mem(il, base);
4bc85c13
WYG
1362
1363 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
9406f797 1364 IL_ERR("Start IWL Error Log Dump:\n");
e7392364 1365 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
4bc85c13
WYG
1366 }
1367
9406f797 1368 IL_ERR("Desc Time asrtPC blink2 "
e7392364 1369 "ilink1 nmiPC Line\n");
4bc85c13
WYG
1370 for (i = ERROR_START_OFFSET;
1371 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1372 i += ERROR_ELEM_SIZE) {
46bc8d4b 1373 desc = il_read_targ_mem(il, base + i);
e7392364
SG
1374 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1375 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1376 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1377 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1378 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1379 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
4bc85c13 1380
e7392364
SG
1381 IL_ERR("%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1382 il3945_desc_lookup(desc), desc, time, blink1, blink2,
1383 ilink1, ilink2, data1);
4bc85c13
WYG
1384 }
1385}
1386
e7392364
SG
1387static void
1388il3945_irq_tasklet(struct il_priv *il)
4bc85c13
WYG
1389{
1390 u32 inta, handled = 0;
1391 u32 inta_fh;
1392 unsigned long flags;
d3175167 1393#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
1394 u32 inta_mask;
1395#endif
1396
46bc8d4b 1397 spin_lock_irqsave(&il->lock, flags);
4bc85c13
WYG
1398
1399 /* Ack/clear/reset pending uCode interrupts.
1400 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1401 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
841b2cca
SG
1402 inta = _il_rd(il, CSR_INT);
1403 _il_wr(il, CSR_INT, inta);
4bc85c13
WYG
1404
1405 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1406 * Any new interrupts that happen after this, either while we're
1407 * in this tasklet, or later, will show up in next ISR/tasklet. */
841b2cca
SG
1408 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1409 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4bc85c13 1410
d3175167 1411#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1412 if (il_get_debug_level(il) & IL_DL_ISR) {
4bc85c13 1413 /* just for debug */
841b2cca 1414 inta_mask = _il_rd(il, CSR_INT_MASK);
e7392364
SG
1415 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
1416 inta_mask, inta_fh);
4bc85c13
WYG
1417 }
1418#endif
1419
46bc8d4b 1420 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
1421
1422 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1423 * atomic, make sure that inta covers all the interrupts that
1424 * we've discovered, even if FH interrupt came in just after
1425 * reading CSR_INT. */
1426 if (inta_fh & CSR39_FH_INT_RX_MASK)
1427 inta |= CSR_INT_BIT_FH_RX;
1428 if (inta_fh & CSR39_FH_INT_TX_MASK)
1429 inta |= CSR_INT_BIT_FH_TX;
1430
1431 /* Now service all interrupt bits discovered above. */
1432 if (inta & CSR_INT_BIT_HW_ERR) {
9406f797 1433 IL_ERR("Hardware error detected. Restarting.\n");
4bc85c13
WYG
1434
1435 /* Tell the device to stop sending interrupts */
46bc8d4b 1436 il_disable_interrupts(il);
4bc85c13 1437
46bc8d4b
SG
1438 il->isr_stats.hw++;
1439 il_irq_handle_error(il);
4bc85c13
WYG
1440
1441 handled |= CSR_INT_BIT_HW_ERR;
1442
1443 return;
1444 }
d3175167 1445#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1446 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4bc85c13
WYG
1447 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1448 if (inta & CSR_INT_BIT_SCD) {
58de00a4 1449 D_ISR("Scheduler finished to transmit "
e7392364 1450 "the frame/frames.\n");
46bc8d4b 1451 il->isr_stats.sch++;
4bc85c13
WYG
1452 }
1453
1454 /* Alive notification via Rx interrupt will do the real work */
1455 if (inta & CSR_INT_BIT_ALIVE) {
58de00a4 1456 D_ISR("Alive interrupt\n");
46bc8d4b 1457 il->isr_stats.alive++;
4bc85c13
WYG
1458 }
1459 }
1460#endif
1461 /* Safely ignore these bits for debug checks below */
1462 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1463
1464 /* Error detected by uCode */
1465 if (inta & CSR_INT_BIT_SW_ERR) {
e7392364
SG
1466 IL_ERR("Microcode SW error detected. " "Restarting 0x%X.\n",
1467 inta);
46bc8d4b
SG
1468 il->isr_stats.sw++;
1469 il_irq_handle_error(il);
4bc85c13
WYG
1470 handled |= CSR_INT_BIT_SW_ERR;
1471 }
1472
1473 /* uCode wakes up after power-down sleep */
1474 if (inta & CSR_INT_BIT_WAKEUP) {
58de00a4 1475 D_ISR("Wakeup interrupt\n");
46bc8d4b
SG
1476 il_rx_queue_update_write_ptr(il, &il->rxq);
1477 il_txq_update_write_ptr(il, &il->txq[0]);
1478 il_txq_update_write_ptr(il, &il->txq[1]);
1479 il_txq_update_write_ptr(il, &il->txq[2]);
1480 il_txq_update_write_ptr(il, &il->txq[3]);
1481 il_txq_update_write_ptr(il, &il->txq[4]);
1482 il_txq_update_write_ptr(il, &il->txq[5]);
1483
1484 il->isr_stats.wakeup++;
4bc85c13
WYG
1485 handled |= CSR_INT_BIT_WAKEUP;
1486 }
1487
1488 /* All uCode command responses, including Tx command responses,
1489 * Rx "responses" (frame-received notification), and other
1490 * notifications from uCode come through here*/
1491 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
46bc8d4b
SG
1492 il3945_rx_handle(il);
1493 il->isr_stats.rx++;
4bc85c13
WYG
1494 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1495 }
1496
1497 if (inta & CSR_INT_BIT_FH_TX) {
58de00a4 1498 D_ISR("Tx interrupt\n");
46bc8d4b 1499 il->isr_stats.tx++;
4bc85c13 1500
841b2cca 1501 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
e7392364 1502 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
4bc85c13
WYG
1503 handled |= CSR_INT_BIT_FH_TX;
1504 }
1505
1506 if (inta & ~handled) {
9406f797 1507 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
46bc8d4b 1508 il->isr_stats.unhandled++;
4bc85c13
WYG
1509 }
1510
46bc8d4b 1511 if (inta & ~il->inta_mask) {
9406f797 1512 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
e7392364 1513 inta & ~il->inta_mask);
53143a18 1514 IL_WARN(" with inta_fh = 0x%08x\n", inta_fh);
4bc85c13
WYG
1515 }
1516
1517 /* Re-enable all interrupts */
1518 /* only Re-enable if disabled by irq */
a6766ccd 1519 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b 1520 il_enable_interrupts(il);
4bc85c13 1521
d3175167 1522#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 1523 if (il_get_debug_level(il) & (IL_DL_ISR)) {
841b2cca
SG
1524 inta = _il_rd(il, CSR_INT);
1525 inta_mask = _il_rd(il, CSR_INT_MASK);
1526 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
58de00a4 1527 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
e7392364 1528 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4bc85c13
WYG
1529 }
1530#endif
1531}
1532
e7392364
SG
1533static int
1534il3945_get_channels_for_scan(struct il_priv *il, enum ieee80211_band band,
1535 u8 is_active, u8 n_probes,
1536 struct il3945_scan_channel *scan_ch,
1537 struct ieee80211_vif *vif)
4bc85c13
WYG
1538{
1539 struct ieee80211_channel *chan;
1540 const struct ieee80211_supported_band *sband;
e2ebc833 1541 const struct il_channel_info *ch_info;
4bc85c13
WYG
1542 u16 passive_dwell = 0;
1543 u16 active_dwell = 0;
1544 int added, i;
1545
46bc8d4b 1546 sband = il_get_hw_mode(il, band);
4bc85c13
WYG
1547 if (!sband)
1548 return 0;
1549
46bc8d4b
SG
1550 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1551 passive_dwell = il_get_passive_dwell_time(il, band, vif);
4bc85c13
WYG
1552
1553 if (passive_dwell <= active_dwell)
1554 passive_dwell = active_dwell + 1;
1555
46bc8d4b
SG
1556 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1557 chan = il->scan_request->channels[i];
4bc85c13
WYG
1558
1559 if (chan->band != band)
1560 continue;
1561
1562 scan_ch->channel = chan->hw_value;
1563
e7392364 1564 ch_info = il_get_channel_info(il, band, scan_ch->channel);
e2ebc833 1565 if (!il_is_channel_valid(ch_info)) {
e7392364 1566 D_SCAN("Channel %d is INVALID for this band.\n",
be663ab6 1567 scan_ch->channel);
4bc85c13
WYG
1568 continue;
1569 }
1570
1571 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1572 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1573 /* If passive , set up for auto-switch
1574 * and use long active_dwell time.
1575 */
e2ebc833 1576 if (!is_active || il_is_channel_passive(ch_info) ||
4bc85c13
WYG
1577 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
1578 scan_ch->type = 0; /* passive */
46bc8d4b 1579 if (IL_UCODE_API(il->ucode_ver) == 1)
e7392364
SG
1580 scan_ch->active_dwell =
1581 cpu_to_le16(passive_dwell - 1);
4bc85c13
WYG
1582 } else {
1583 scan_ch->type = 1; /* active */
1584 }
1585
1586 /* Set direct probe bits. These may be used both for active
1587 * scan channels (probes gets sent right away),
1588 * or for passive channels (probes get se sent only after
1589 * hearing clear Rx packet).*/
46bc8d4b 1590 if (IL_UCODE_API(il->ucode_ver) >= 2) {
4bc85c13 1591 if (n_probes)
d3175167 1592 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
4bc85c13
WYG
1593 } else {
1594 /* uCode v1 does not allow setting direct probe bits on
1595 * passive channel. */
1596 if ((scan_ch->type & 1) && n_probes)
d3175167 1597 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
4bc85c13
WYG
1598 }
1599
1600 /* Set txpower levels to defaults */
1601 scan_ch->tpc.dsp_atten = 110;
1602 /* scan_pwr_info->tpc.dsp_atten; */
1603
1604 /*scan_pwr_info->tpc.tx_gain; */
1605 if (band == IEEE80211_BAND_5GHZ)
1606 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1607 else {
1608 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1609 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1610 * power level:
1611 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
1612 */
1613 }
1614
e7392364
SG
1615 D_SCAN("Scanning %d [%s %d]\n", scan_ch->channel,
1616 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1617 (scan_ch->type & 1) ? active_dwell : passive_dwell);
4bc85c13
WYG
1618
1619 scan_ch++;
1620 added++;
1621 }
1622
58de00a4 1623 D_SCAN("total channels to scan %d\n", added);
4bc85c13
WYG
1624 return added;
1625}
1626
e7392364
SG
1627static void
1628il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
4bc85c13
WYG
1629{
1630 int i;
1631
2eb05816 1632 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
e2ebc833 1633 rates[i].bitrate = il3945_rates[i].ieee * 5;
e7392364 1634 rates[i].hw_value = i; /* Rate scaling will work on idxes */
4bc85c13
WYG
1635 rates[i].hw_value_short = i;
1636 rates[i].flags = 0;
d3175167 1637 if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
4bc85c13
WYG
1638 /*
1639 * If CCK != 1M then set short preamble rate flag.
1640 */
e7392364
SG
1641 rates[i].flags |=
1642 (il3945_rates[i].plcp ==
1643 10) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4bc85c13
WYG
1644 }
1645 }
1646}
1647
1648/******************************************************************************
1649 *
1650 * uCode download functions
1651 *
1652 ******************************************************************************/
1653
e7392364
SG
1654static void
1655il3945_dealloc_ucode_pci(struct il_priv *il)
4bc85c13 1656{
46bc8d4b
SG
1657 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1658 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1659 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1660 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1661 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1662 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4bc85c13
WYG
1663}
1664
1665/**
e2ebc833 1666 * il3945_verify_inst_full - verify runtime uCode image in card vs. host,
4bc85c13
WYG
1667 * looking at all data.
1668 */
e7392364
SG
1669static int
1670il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
4bc85c13
WYG
1671{
1672 u32 val;
1673 u32 save_len = len;
1674 int rc = 0;
1675 u32 errcnt;
1676
58de00a4 1677 D_INFO("ucode inst image size is %u\n", len);
4bc85c13 1678
e7392364 1679 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
4bc85c13
WYG
1680
1681 errcnt = 0;
1682 for (; len > 0; len -= sizeof(u32), image++) {
1683 /* read data comes through single port, auto-incr addr */
1684 /* NOTE: Use the debugless read so we don't flood kernel log
e2ebc833 1685 * if IL_DL_IO is set */
1c8cae57 1686 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
4bc85c13 1687 if (val != le32_to_cpu(*image)) {
9406f797 1688 IL_ERR("uCode INST section is invalid at "
e7392364
SG
1689 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1690 save_len - len, val, le32_to_cpu(*image));
4bc85c13
WYG
1691 rc = -EIO;
1692 errcnt++;
1693 if (errcnt >= 20)
1694 break;
1695 }
1696 }
1697
4bc85c13 1698 if (!errcnt)
e7392364 1699 D_INFO("ucode image in INSTRUCTION memory is good\n");
4bc85c13
WYG
1700
1701 return rc;
1702}
1703
4bc85c13 1704/**
e2ebc833 1705 * il3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
4bc85c13
WYG
1706 * using sample data 100 bytes apart. If these sample points are good,
1707 * it's a pretty good bet that everything between them is good, too.
1708 */
e7392364
SG
1709static int
1710il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
4bc85c13
WYG
1711{
1712 u32 val;
1713 int rc = 0;
1714 u32 errcnt = 0;
1715 u32 i;
1716
58de00a4 1717 D_INFO("ucode inst image size is %u\n", len);
4bc85c13 1718
e7392364 1719 for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) {
4bc85c13
WYG
1720 /* read data comes through single port, auto-incr addr */
1721 /* NOTE: Use the debugless read so we don't flood kernel log
e2ebc833 1722 * if IL_DL_IO is set */
e7392364 1723 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1c8cae57 1724 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
4bc85c13 1725 if (val != le32_to_cpu(*image)) {
e7392364 1726#if 0 /* Enable this if you want to see details */
9406f797 1727 IL_ERR("uCode INST section is invalid at "
e7392364
SG
1728 "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val,
1729 *image);
4bc85c13
WYG
1730#endif
1731 rc = -EIO;
1732 errcnt++;
1733 if (errcnt >= 3)
1734 break;
1735 }
1736 }
1737
1738 return rc;
1739}
1740
4bc85c13 1741/**
e2ebc833 1742 * il3945_verify_ucode - determine which instruction image is in SRAM,
4bc85c13
WYG
1743 * and verify its contents
1744 */
e7392364
SG
1745static int
1746il3945_verify_ucode(struct il_priv *il)
4bc85c13
WYG
1747{
1748 __le32 *image;
1749 u32 len;
1750 int rc = 0;
1751
1752 /* Try bootstrap */
e7392364 1753 image = (__le32 *) il->ucode_boot.v_addr;
46bc8d4b
SG
1754 len = il->ucode_boot.len;
1755 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1756 if (rc == 0) {
58de00a4 1757 D_INFO("Bootstrap uCode is good in inst SRAM\n");
4bc85c13
WYG
1758 return 0;
1759 }
1760
1761 /* Try initialize */
e7392364 1762 image = (__le32 *) il->ucode_init.v_addr;
46bc8d4b
SG
1763 len = il->ucode_init.len;
1764 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1765 if (rc == 0) {
58de00a4 1766 D_INFO("Initialize uCode is good in inst SRAM\n");
4bc85c13
WYG
1767 return 0;
1768 }
1769
1770 /* Try runtime/protocol */
e7392364 1771 image = (__le32 *) il->ucode_code.v_addr;
46bc8d4b
SG
1772 len = il->ucode_code.len;
1773 rc = il3945_verify_inst_sparse(il, image, len);
4bc85c13 1774 if (rc == 0) {
58de00a4 1775 D_INFO("Runtime uCode is good in inst SRAM\n");
4bc85c13
WYG
1776 return 0;
1777 }
1778
9406f797 1779 IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
4bc85c13
WYG
1780
1781 /* Since nothing seems to match, show first several data entries in
1782 * instruction SRAM, so maybe visual inspection will give a clue.
1783 * Selection of bootstrap image (vs. other images) is arbitrary. */
e7392364 1784 image = (__le32 *) il->ucode_boot.v_addr;
46bc8d4b
SG
1785 len = il->ucode_boot.len;
1786 rc = il3945_verify_inst_full(il, image, len);
4bc85c13
WYG
1787
1788 return rc;
1789}
1790
e7392364
SG
1791static void
1792il3945_nic_start(struct il_priv *il)
4bc85c13
WYG
1793{
1794 /* Remove all resets to allow NIC to operate */
841b2cca 1795 _il_wr(il, CSR_RESET, 0);
4bc85c13
WYG
1796}
1797
d3175167 1798#define IL3945_UCODE_GET(item) \
e2ebc833 1799static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
4bc85c13 1800{ \
be663ab6 1801 return le32_to_cpu(ucode->v1.item); \
4bc85c13
WYG
1802}
1803
e7392364
SG
1804static u32
1805il3945_ucode_get_header_size(u32 api_ver)
4bc85c13
WYG
1806{
1807 return 24;
1808}
1809
e7392364
SG
1810static u8 *
1811il3945_ucode_get_data(const struct il_ucode_header *ucode)
4bc85c13 1812{
be663ab6 1813 return (u8 *) ucode->v1.data;
4bc85c13
WYG
1814}
1815
d3175167
SG
1816IL3945_UCODE_GET(inst_size);
1817IL3945_UCODE_GET(data_size);
1818IL3945_UCODE_GET(init_size);
1819IL3945_UCODE_GET(init_data_size);
1820IL3945_UCODE_GET(boot_size);
4bc85c13
WYG
1821
1822/**
e2ebc833 1823 * il3945_read_ucode - Read uCode images from disk file.
4bc85c13
WYG
1824 *
1825 * Copy into buffers for card to fetch via bus-mastering
1826 */
e7392364
SG
1827static int
1828il3945_read_ucode(struct il_priv *il)
4bc85c13 1829{
e2ebc833 1830 const struct il_ucode_header *ucode;
0c2c8852 1831 int ret = -EINVAL, idx;
4bc85c13
WYG
1832 const struct firmware *ucode_raw;
1833 /* firmware file name contains uCode/driver compatibility version */
46bc8d4b
SG
1834 const char *name_pre = il->cfg->fw_name_pre;
1835 const unsigned int api_max = il->cfg->ucode_api_max;
1836 const unsigned int api_min = il->cfg->ucode_api_min;
4bc85c13
WYG
1837 char buf[25];
1838 u8 *src;
1839 size_t len;
1840 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1841
1842 /* Ask kernel firmware_class module to get the boot firmware off disk.
1843 * request_firmware() is synchronous, file is in memory on return. */
0c2c8852
SG
1844 for (idx = api_max; idx >= api_min; idx--) {
1845 sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
46bc8d4b 1846 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
4bc85c13 1847 if (ret < 0) {
e7392364 1848 IL_ERR("%s firmware file req failed: %d\n", buf, ret);
4bc85c13
WYG
1849 if (ret == -ENOENT)
1850 continue;
1851 else
1852 goto error;
1853 } else {
0c2c8852 1854 if (idx < api_max)
9406f797 1855 IL_ERR("Loaded firmware %s, "
e7392364
SG
1856 "which is deprecated. "
1857 " Please use API v%u instead.\n", buf,
1858 api_max);
58de00a4 1859 D_INFO("Got firmware '%s' file "
e7392364 1860 "(%zd bytes) from disk\n", buf, ucode_raw->size);
4bc85c13
WYG
1861 break;
1862 }
1863 }
1864
1865 if (ret < 0)
1866 goto error;
1867
1868 /* Make sure that we got at least our header! */
e7392364 1869 if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
9406f797 1870 IL_ERR("File size way too small!\n");
4bc85c13
WYG
1871 ret = -EINVAL;
1872 goto err_release;
1873 }
1874
1875 /* Data from ucode file: header followed by uCode images */
e2ebc833 1876 ucode = (struct il_ucode_header *)ucode_raw->data;
4bc85c13 1877
46bc8d4b
SG
1878 il->ucode_ver = le32_to_cpu(ucode->ver);
1879 api_ver = IL_UCODE_API(il->ucode_ver);
e2ebc833
SG
1880 inst_size = il3945_ucode_get_inst_size(ucode);
1881 data_size = il3945_ucode_get_data_size(ucode);
1882 init_size = il3945_ucode_get_init_size(ucode);
1883 init_data_size = il3945_ucode_get_init_data_size(ucode);
1884 boot_size = il3945_ucode_get_boot_size(ucode);
1885 src = il3945_ucode_get_data(ucode);
4bc85c13
WYG
1886
1887 /* api_ver should match the api version forming part of the
1888 * firmware filename ... but we don't check for that and only rely
1889 * on the API version read from firmware header from here on forward */
1890
1891 if (api_ver < api_min || api_ver > api_max) {
9406f797 1892 IL_ERR("Driver unable to support your firmware API. "
e7392364
SG
1893 "Driver supports v%u, firmware is v%u.\n", api_max,
1894 api_ver);
46bc8d4b 1895 il->ucode_ver = 0;
4bc85c13
WYG
1896 ret = -EINVAL;
1897 goto err_release;
1898 }
1899 if (api_ver != api_max)
9406f797 1900 IL_ERR("Firmware has old API version. Expected %u, "
e7392364
SG
1901 "got %u. New firmware can be obtained "
1902 "from http://www.intellinuxwireless.org.\n", api_max,
1903 api_ver);
4bc85c13 1904
9406f797 1905 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
e7392364
SG
1906 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1907 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
46bc8d4b 1908
e7392364
SG
1909 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1910 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1911 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1912 IL_UCODE_SERIAL(il->ucode_ver));
4bc85c13 1913
e7392364
SG
1914 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1915 D_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
1916 D_INFO("f/w package hdr runtime data size = %u\n", data_size);
1917 D_INFO("f/w package hdr init inst size = %u\n", init_size);
1918 D_INFO("f/w package hdr init data size = %u\n", init_data_size);
1919 D_INFO("f/w package hdr boot inst size = %u\n", boot_size);
4bc85c13
WYG
1920
1921 /* Verify size of file vs. image size info in file's header */
e7392364
SG
1922 if (ucode_raw->size !=
1923 il3945_ucode_get_header_size(api_ver) + inst_size + data_size +
1924 init_size + init_data_size + boot_size) {
4bc85c13 1925
e7392364
SG
1926 D_INFO("uCode file size %zd does not match expected size\n",
1927 ucode_raw->size);
4bc85c13
WYG
1928 ret = -EINVAL;
1929 goto err_release;
1930 }
1931
1932 /* Verify that uCode images will fit in card's SRAM */
d3175167 1933 if (inst_size > IL39_MAX_INST_SIZE) {
e7392364 1934 D_INFO("uCode instr len %d too large to fit in\n", inst_size);
4bc85c13
WYG
1935 ret = -EINVAL;
1936 goto err_release;
1937 }
1938
d3175167 1939 if (data_size > IL39_MAX_DATA_SIZE) {
e7392364 1940 D_INFO("uCode data len %d too large to fit in\n", data_size);
4bc85c13
WYG
1941 ret = -EINVAL;
1942 goto err_release;
1943 }
d3175167 1944 if (init_size > IL39_MAX_INST_SIZE) {
e7392364
SG
1945 D_INFO("uCode init instr len %d too large to fit in\n",
1946 init_size);
4bc85c13
WYG
1947 ret = -EINVAL;
1948 goto err_release;
1949 }
d3175167 1950 if (init_data_size > IL39_MAX_DATA_SIZE) {
e7392364
SG
1951 D_INFO("uCode init data len %d too large to fit in\n",
1952 init_data_size);
4bc85c13
WYG
1953 ret = -EINVAL;
1954 goto err_release;
1955 }
d3175167 1956 if (boot_size > IL39_MAX_BSM_SIZE) {
e7392364
SG
1957 D_INFO("uCode boot instr len %d too large to fit in\n",
1958 boot_size);
4bc85c13
WYG
1959 ret = -EINVAL;
1960 goto err_release;
1961 }
1962
1963 /* Allocate ucode buffers for card's bus-master loading ... */
1964
1965 /* Runtime instructions and 2 copies of data:
1966 * 1) unmodified from disk
1967 * 2) backup cache for save/restore during power-downs */
46bc8d4b
SG
1968 il->ucode_code.len = inst_size;
1969 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4bc85c13 1970
46bc8d4b
SG
1971 il->ucode_data.len = data_size;
1972 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4bc85c13 1973
46bc8d4b
SG
1974 il->ucode_data_backup.len = data_size;
1975 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4bc85c13 1976
46bc8d4b
SG
1977 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1978 !il->ucode_data_backup.v_addr)
4bc85c13
WYG
1979 goto err_pci_alloc;
1980
1981 /* Initialization instructions and data */
1982 if (init_size && init_data_size) {
46bc8d4b
SG
1983 il->ucode_init.len = init_size;
1984 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4bc85c13 1985
46bc8d4b
SG
1986 il->ucode_init_data.len = init_data_size;
1987 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4bc85c13 1988
46bc8d4b 1989 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4bc85c13
WYG
1990 goto err_pci_alloc;
1991 }
1992
1993 /* Bootstrap (instructions only, no data) */
1994 if (boot_size) {
46bc8d4b
SG
1995 il->ucode_boot.len = boot_size;
1996 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4bc85c13 1997
46bc8d4b 1998 if (!il->ucode_boot.v_addr)
4bc85c13
WYG
1999 goto err_pci_alloc;
2000 }
2001
2002 /* Copy images into buffers for card's bus-master reads ... */
2003
2004 /* Runtime instructions (first block of data in file) */
2005 len = inst_size;
e7392364 2006 D_INFO("Copying (but not loading) uCode instr len %zd\n", len);
46bc8d4b 2007 memcpy(il->ucode_code.v_addr, src, len);
4bc85c13
WYG
2008 src += len;
2009
58de00a4 2010 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
e7392364 2011 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
4bc85c13
WYG
2012
2013 /* Runtime data (2nd block)
e2ebc833 2014 * NOTE: Copy into backup buffer will be done in il3945_up() */
4bc85c13 2015 len = data_size;
e7392364 2016 D_INFO("Copying (but not loading) uCode data len %zd\n", len);
46bc8d4b
SG
2017 memcpy(il->ucode_data.v_addr, src, len);
2018 memcpy(il->ucode_data_backup.v_addr, src, len);
4bc85c13
WYG
2019 src += len;
2020
2021 /* Initialization instructions (3rd block) */
2022 if (init_size) {
2023 len = init_size;
e7392364 2024 D_INFO("Copying (but not loading) init instr len %zd\n", len);
46bc8d4b 2025 memcpy(il->ucode_init.v_addr, src, len);
4bc85c13
WYG
2026 src += len;
2027 }
2028
2029 /* Initialization data (4th block) */
2030 if (init_data_size) {
2031 len = init_data_size;
e7392364 2032 D_INFO("Copying (but not loading) init data len %zd\n", len);
46bc8d4b 2033 memcpy(il->ucode_init_data.v_addr, src, len);
4bc85c13
WYG
2034 src += len;
2035 }
2036
2037 /* Bootstrap instructions (5th block) */
2038 len = boot_size;
e7392364 2039 D_INFO("Copying (but not loading) boot instr len %zd\n", len);
46bc8d4b 2040 memcpy(il->ucode_boot.v_addr, src, len);
4bc85c13
WYG
2041
2042 /* We have our copies now, allow OS release its copies */
2043 release_firmware(ucode_raw);
2044 return 0;
2045
e7392364 2046err_pci_alloc:
9406f797 2047 IL_ERR("failed to allocate pci memory\n");
4bc85c13 2048 ret = -ENOMEM;
46bc8d4b 2049 il3945_dealloc_ucode_pci(il);
4bc85c13 2050
e7392364 2051err_release:
4bc85c13
WYG
2052 release_firmware(ucode_raw);
2053
e7392364 2054error:
4bc85c13
WYG
2055 return ret;
2056}
2057
4bc85c13 2058/**
e2ebc833 2059 * il3945_set_ucode_ptrs - Set uCode address location
4bc85c13
WYG
2060 *
2061 * Tell initialization uCode where to find runtime uCode.
2062 *
2063 * BSM registers initially contain pointers to initialization uCode.
2064 * We need to replace them to load runtime uCode inst and data,
2065 * and to save runtime data when powering down.
2066 */
e7392364
SG
2067static int
2068il3945_set_ucode_ptrs(struct il_priv *il)
4bc85c13
WYG
2069{
2070 dma_addr_t pinst;
2071 dma_addr_t pdata;
2072
2073 /* bits 31:0 for 3945 */
46bc8d4b
SG
2074 pinst = il->ucode_code.p_addr;
2075 pdata = il->ucode_data_backup.p_addr;
4bc85c13
WYG
2076
2077 /* Tell bootstrap uCode where to find image to load */
db54eb57
SG
2078 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2079 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
e7392364 2080 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
4bc85c13
WYG
2081
2082 /* Inst byte count must be last to set up, bit 31 signals uCode
2083 * that all new ptr/size info is in place */
db54eb57 2084 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
e7392364 2085 il->ucode_code.len | BSM_DRAM_INST_LOAD);
4bc85c13 2086
58de00a4 2087 D_INFO("Runtime uCode pointers are set.\n");
4bc85c13
WYG
2088
2089 return 0;
2090}
2091
2092/**
4d69c752 2093 * il3945_init_alive_start - Called after N_ALIVE notification received
4bc85c13 2094 *
4d69c752 2095 * Called after N_ALIVE notification received from "initialize" uCode.
4bc85c13
WYG
2096 *
2097 * Tell "initialize" uCode to go ahead and load the runtime uCode.
2098 */
e7392364
SG
2099static void
2100il3945_init_alive_start(struct il_priv *il)
4bc85c13
WYG
2101{
2102 /* Check alive response for "valid" sign from uCode */
46bc8d4b 2103 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
4bc85c13
WYG
2104 /* We had an error bringing up the hardware, so take it
2105 * all the way back down so we can try again */
58de00a4 2106 D_INFO("Initialize Alive failed.\n");
4bc85c13
WYG
2107 goto restart;
2108 }
2109
2110 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2111 * This is a paranoid check, because we would not have gotten the
2112 * "initialize" alive if code weren't properly loaded. */
46bc8d4b 2113 if (il3945_verify_ucode(il)) {
4bc85c13
WYG
2114 /* Runtime instruction load was bad;
2115 * take it all the way back down so we can try again */
58de00a4 2116 D_INFO("Bad \"initialize\" uCode load.\n");
4bc85c13
WYG
2117 goto restart;
2118 }
2119
2120 /* Send pointers to protocol/runtime uCode image ... init code will
2121 * load and launch runtime uCode, which will send us another "Alive"
2122 * notification. */
58de00a4 2123 D_INFO("Initialization Alive received.\n");
46bc8d4b 2124 if (il3945_set_ucode_ptrs(il)) {
4bc85c13
WYG
2125 /* Runtime instruction load won't happen;
2126 * take it all the way back down so we can try again */
58de00a4 2127 D_INFO("Couldn't set up uCode pointers.\n");
4bc85c13
WYG
2128 goto restart;
2129 }
2130 return;
2131
e7392364 2132restart:
46bc8d4b 2133 queue_work(il->workqueue, &il->restart);
4bc85c13
WYG
2134}
2135
2136/**
4d69c752 2137 * il3945_alive_start - called after N_ALIVE notification received
4bc85c13 2138 * from protocol/runtime uCode (initialization uCode's
e2ebc833 2139 * Alive gets handled by il3945_init_alive_start()).
4bc85c13 2140 */
e7392364
SG
2141static void
2142il3945_alive_start(struct il_priv *il)
4bc85c13
WYG
2143{
2144 int thermal_spin = 0;
2145 u32 rfkill;
4bc85c13 2146
58de00a4 2147 D_INFO("Runtime Alive received.\n");
4bc85c13 2148
46bc8d4b 2149 if (il->card_alive.is_valid != UCODE_VALID_OK) {
4bc85c13
WYG
2150 /* We had an error bringing up the hardware, so take it
2151 * all the way back down so we can try again */
58de00a4 2152 D_INFO("Alive failed.\n");
4bc85c13
WYG
2153 goto restart;
2154 }
2155
2156 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2157 * This is a paranoid check, because we would not have gotten the
2158 * "runtime" alive if code weren't properly loaded. */
46bc8d4b 2159 if (il3945_verify_ucode(il)) {
4bc85c13
WYG
2160 /* Runtime instruction load was bad;
2161 * take it all the way back down so we can try again */
58de00a4 2162 D_INFO("Bad runtime uCode load.\n");
4bc85c13
WYG
2163 goto restart;
2164 }
2165
db54eb57 2166 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
58de00a4 2167 D_INFO("RFKILL status: 0x%x\n", rfkill);
4bc85c13
WYG
2168
2169 if (rfkill & 0x1) {
a6766ccd 2170 clear_bit(S_RF_KILL_HW, &il->status);
4bc85c13
WYG
2171 /* if RFKILL is not on, then wait for thermal
2172 * sensor in adapter to kick in */
46bc8d4b 2173 while (il3945_hw_get_temperature(il) == 0) {
4bc85c13
WYG
2174 thermal_spin++;
2175 udelay(10);
2176 }
2177
2178 if (thermal_spin)
58de00a4 2179 D_INFO("Thermal calibration took %dus\n",
e7392364 2180 thermal_spin * 10);
4bc85c13 2181 } else
a6766ccd 2182 set_bit(S_RF_KILL_HW, &il->status);
4bc85c13
WYG
2183
2184 /* After the ALIVE response, we can send commands to 3945 uCode */
a6766ccd 2185 set_bit(S_ALIVE, &il->status);
4bc85c13
WYG
2186
2187 /* Enable watchdog to monitor the driver tx queues */
46bc8d4b 2188 il_setup_watchdog(il);
4bc85c13 2189
46bc8d4b 2190 if (il_is_rfkill(il))
4bc85c13
WYG
2191 return;
2192
46bc8d4b 2193 ieee80211_wake_queues(il->hw);
4bc85c13 2194
2eb05816 2195 il->active_rate = RATES_MASK_3945;
4bc85c13 2196
46bc8d4b 2197 il_power_update_mode(il, true);
4bc85c13 2198
7c2cde2e 2199 if (il_is_associated(il)) {
e2ebc833 2200 struct il3945_rxon_cmd *active_rxon =
c8b03958 2201 (struct il3945_rxon_cmd *)(&il->active);
4bc85c13 2202
c8b03958 2203 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
4bc85c13
WYG
2204 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2205 } else {
2206 /* Initialize our rx_config data */
83007196 2207 il_connection_init_rx_config(il);
4bc85c13
WYG
2208 }
2209
2210 /* Configure Bluetooth device coexistence support */
46bc8d4b 2211 il_send_bt_config(il);
4bc85c13 2212
a6766ccd 2213 set_bit(S_READY, &il->status);
4bc85c13
WYG
2214
2215 /* Configure the adapter for unassociated operation */
83007196 2216 il3945_commit_rxon(il);
4bc85c13 2217
46bc8d4b 2218 il3945_reg_txpower_periodic(il);
4bc85c13 2219
58de00a4 2220 D_INFO("ALIVE processing complete.\n");
46bc8d4b 2221 wake_up(&il->wait_command_queue);
4bc85c13
WYG
2222
2223 return;
2224
e7392364 2225restart:
46bc8d4b 2226 queue_work(il->workqueue, &il->restart);
4bc85c13
WYG
2227}
2228
46bc8d4b 2229static void il3945_cancel_deferred_work(struct il_priv *il);
4bc85c13 2230
e7392364
SG
2231static void
2232__il3945_down(struct il_priv *il)
4bc85c13
WYG
2233{
2234 unsigned long flags;
2235 int exit_pending;
2236
58de00a4 2237 D_INFO(DRV_NAME " is going down\n");
4bc85c13 2238
46bc8d4b 2239 il_scan_cancel_timeout(il, 200);
4bc85c13 2240
a6766ccd 2241 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
4bc85c13 2242
a6766ccd 2243 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
4bc85c13 2244 * to prevent rearm timer */
46bc8d4b 2245 del_timer_sync(&il->watchdog);
4bc85c13
WYG
2246
2247 /* Station information will now be cleared in device */
83007196 2248 il_clear_ucode_stations(il);
46bc8d4b
SG
2249 il_dealloc_bcast_stations(il);
2250 il_clear_driver_stations(il);
4bc85c13
WYG
2251
2252 /* Unblock any waiting calls */
46bc8d4b 2253 wake_up_all(&il->wait_command_queue);
4bc85c13
WYG
2254
2255 /* Wipe out the EXIT_PENDING status bit if we are not actually
2256 * exiting the module */
2257 if (!exit_pending)
a6766ccd 2258 clear_bit(S_EXIT_PENDING, &il->status);
4bc85c13
WYG
2259
2260 /* stop and reset the on-board processor */
841b2cca 2261 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4bc85c13
WYG
2262
2263 /* tell the device to stop sending interrupts */
46bc8d4b
SG
2264 spin_lock_irqsave(&il->lock, flags);
2265 il_disable_interrupts(il);
2266 spin_unlock_irqrestore(&il->lock, flags);
2267 il3945_synchronize_irq(il);
4bc85c13 2268
46bc8d4b
SG
2269 if (il->mac80211_registered)
2270 ieee80211_stop_queues(il->hw);
4bc85c13 2271
e2ebc833 2272 /* If we have not previously called il3945_init() then
4bc85c13 2273 * clear all bits but the RF Kill bits and return */
46bc8d4b 2274 if (!il_is_init(il)) {
e7392364
SG
2275 il->status =
2276 test_bit(S_RF_KILL_HW,
2277 &il->
2278 status) << S_RF_KILL_HW |
2279 test_bit(S_GEO_CONFIGURED,
2280 &il->
2281 status) << S_GEO_CONFIGURED |
2282 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
4bc85c13
WYG
2283 goto exit;
2284 }
2285
2286 /* ...otherwise clear out all the status bits but the RF Kill
2287 * bit and continue taking the NIC down. */
e7392364
SG
2288 il->status &=
2289 test_bit(S_RF_KILL_HW,
2290 &il->status) << S_RF_KILL_HW | test_bit(S_GEO_CONFIGURED,
2291 &il->
2292 status) <<
2293 S_GEO_CONFIGURED | test_bit(S_FW_ERROR,
2294 &il->
2295 status) << S_FW_ERROR |
2296 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
4bc85c13 2297
46bc8d4b
SG
2298 il3945_hw_txq_ctx_stop(il);
2299 il3945_hw_rxq_stop(il);
4bc85c13
WYG
2300
2301 /* Power-down device's busmaster DMA clocks */
db54eb57 2302 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
4bc85c13
WYG
2303 udelay(5);
2304
2305 /* Stop the device, and put it in low power state */
46bc8d4b 2306 il_apm_stop(il);
4bc85c13 2307
e7392364 2308exit:
46bc8d4b 2309 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
4bc85c13 2310
46bc8d4b
SG
2311 if (il->beacon_skb)
2312 dev_kfree_skb(il->beacon_skb);
2313 il->beacon_skb = NULL;
4bc85c13
WYG
2314
2315 /* clear out any free frames */
46bc8d4b 2316 il3945_clear_free_frames(il);
4bc85c13
WYG
2317}
2318
e7392364
SG
2319static void
2320il3945_down(struct il_priv *il)
4bc85c13 2321{
46bc8d4b
SG
2322 mutex_lock(&il->mutex);
2323 __il3945_down(il);
2324 mutex_unlock(&il->mutex);
4bc85c13 2325
46bc8d4b 2326 il3945_cancel_deferred_work(il);
4bc85c13
WYG
2327}
2328
2329#define MAX_HW_RESTARTS 5
2330
e7392364
SG
2331static int
2332il3945_alloc_bcast_station(struct il_priv *il)
4bc85c13 2333{
4bc85c13
WYG
2334 unsigned long flags;
2335 u8 sta_id;
2336
46bc8d4b 2337 spin_lock_irqsave(&il->sta_lock, flags);
83007196 2338 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
e2ebc833 2339 if (sta_id == IL_INVALID_STATION) {
9406f797 2340 IL_ERR("Unable to prepare broadcast station\n");
46bc8d4b 2341 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
2342
2343 return -EINVAL;
2344 }
2345
46bc8d4b
SG
2346 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2347 il->stations[sta_id].used |= IL_STA_BCAST;
2348 spin_unlock_irqrestore(&il->sta_lock, flags);
4bc85c13
WYG
2349
2350 return 0;
2351}
2352
e7392364
SG
2353static int
2354__il3945_up(struct il_priv *il)
4bc85c13
WYG
2355{
2356 int rc, i;
2357
46bc8d4b 2358 rc = il3945_alloc_bcast_station(il);
4bc85c13
WYG
2359 if (rc)
2360 return rc;
2361
a6766ccd 2362 if (test_bit(S_EXIT_PENDING, &il->status)) {
9406f797 2363 IL_WARN("Exit pending; will not bring the NIC up\n");
4bc85c13
WYG
2364 return -EIO;
2365 }
2366
46bc8d4b 2367 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
9406f797 2368 IL_ERR("ucode not available for device bring up\n");
4bc85c13
WYG
2369 return -EIO;
2370 }
2371
2372 /* If platform's RF_KILL switch is NOT set to KILL */
e7392364 2373 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
a6766ccd 2374 clear_bit(S_RF_KILL_HW, &il->status);
4bc85c13 2375 else {
a6766ccd 2376 set_bit(S_RF_KILL_HW, &il->status);
9406f797 2377 IL_WARN("Radio disabled by HW RF Kill switch\n");
4bc85c13
WYG
2378 return -ENODEV;
2379 }
2380
841b2cca 2381 _il_wr(il, CSR_INT, 0xFFFFFFFF);
4bc85c13 2382
46bc8d4b 2383 rc = il3945_hw_nic_init(il);
4bc85c13 2384 if (rc) {
9406f797 2385 IL_ERR("Unable to int nic\n");
4bc85c13
WYG
2386 return rc;
2387 }
2388
2389 /* make sure rfkill handshake bits are cleared */
841b2cca 2390 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
e7392364 2391 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4bc85c13
WYG
2392
2393 /* clear (again), then enable host interrupts */
841b2cca 2394 _il_wr(il, CSR_INT, 0xFFFFFFFF);
46bc8d4b 2395 il_enable_interrupts(il);
4bc85c13
WYG
2396
2397 /* really make sure rfkill handshake bits are cleared */
841b2cca
SG
2398 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2399 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4bc85c13
WYG
2400
2401 /* Copy original ucode data image from disk into backup cache.
2402 * This will be used to initialize the on-board processor's
2403 * data SRAM for a clean start when the runtime program first loads. */
46bc8d4b
SG
2404 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2405 il->ucode_data.len);
4bc85c13
WYG
2406
2407 /* We return success when we resume from suspend and rf_kill is on. */
a6766ccd 2408 if (test_bit(S_RF_KILL_HW, &il->status))
4bc85c13
WYG
2409 return 0;
2410
2411 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2412
2413 /* load bootstrap state machine,
2414 * load bootstrap program into processor's memory,
2415 * prepare to load the "initialize" uCode */
c39ae9fd 2416 rc = il->ops->lib->load_ucode(il);
4bc85c13
WYG
2417
2418 if (rc) {
e7392364 2419 IL_ERR("Unable to set up bootstrap uCode: %d\n", rc);
4bc85c13
WYG
2420 continue;
2421 }
2422
2423 /* start card; "initialize" will load runtime ucode */
46bc8d4b 2424 il3945_nic_start(il);
4bc85c13 2425
58de00a4 2426 D_INFO(DRV_NAME " is coming up\n");
4bc85c13
WYG
2427
2428 return 0;
2429 }
2430
a6766ccd 2431 set_bit(S_EXIT_PENDING, &il->status);
46bc8d4b 2432 __il3945_down(il);
a6766ccd 2433 clear_bit(S_EXIT_PENDING, &il->status);
4bc85c13
WYG
2434
2435 /* tried to restart and config the device for as long as our
2436 * patience could withstand */
9406f797 2437 IL_ERR("Unable to initialize device after %d attempts.\n", i);
4bc85c13
WYG
2438 return -EIO;
2439}
2440
4bc85c13
WYG
2441/*****************************************************************************
2442 *
2443 * Workqueue callbacks
2444 *
2445 *****************************************************************************/
2446
e7392364
SG
2447static void
2448il3945_bg_init_alive_start(struct work_struct *data)
4bc85c13 2449{
46bc8d4b 2450 struct il_priv *il =
e2ebc833 2451 container_of(data, struct il_priv, init_alive_start.work);
4bc85c13 2452
46bc8d4b 2453 mutex_lock(&il->mutex);
a6766ccd 2454 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 2455 goto out;
4bc85c13 2456
46bc8d4b 2457 il3945_init_alive_start(il);
28a6e577 2458out:
46bc8d4b 2459 mutex_unlock(&il->mutex);
4bc85c13
WYG
2460}
2461
e7392364
SG
2462static void
2463il3945_bg_alive_start(struct work_struct *data)
4bc85c13 2464{
46bc8d4b 2465 struct il_priv *il =
e2ebc833 2466 container_of(data, struct il_priv, alive_start.work);
4bc85c13 2467
46bc8d4b 2468 mutex_lock(&il->mutex);
a6766ccd 2469 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 2470 goto out;
4bc85c13 2471
46bc8d4b 2472 il3945_alive_start(il);
28a6e577 2473out:
46bc8d4b 2474 mutex_unlock(&il->mutex);
4bc85c13
WYG
2475}
2476
2477/*
2478 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2479 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2480 * *is* readable even when device has been SW_RESET into low power mode
2481 * (e.g. during RF KILL).
2482 */
e7392364
SG
2483static void
2484il3945_rfkill_poll(struct work_struct *data)
4bc85c13 2485{
46bc8d4b 2486 struct il_priv *il =
e2ebc833 2487 container_of(data, struct il_priv, _3945.rfkill_poll.work);
a6766ccd 2488 bool old_rfkill = test_bit(S_RF_KILL_HW, &il->status);
e7392364
SG
2489 bool new_rfkill =
2490 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
4bc85c13
WYG
2491
2492 if (new_rfkill != old_rfkill) {
2493 if (new_rfkill)
a6766ccd 2494 set_bit(S_RF_KILL_HW, &il->status);
4bc85c13 2495 else
a6766ccd 2496 clear_bit(S_RF_KILL_HW, &il->status);
4bc85c13 2497
46bc8d4b 2498 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
4bc85c13 2499
58de00a4 2500 D_RF_KILL("RF_KILL bit toggled to %s.\n",
e7392364 2501 new_rfkill ? "disable radio" : "enable radio");
4bc85c13
WYG
2502 }
2503
2504 /* Keep this running, even if radio now enabled. This will be
2505 * cancelled in mac_start() if system decides to start again */
46bc8d4b 2506 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
2507 round_jiffies_relative(2 * HZ));
2508
2509}
2510
e7392364
SG
2511int
2512il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
4bc85c13 2513{
e2ebc833 2514 struct il_host_cmd cmd = {
4d69c752 2515 .id = C_SCAN,
e2ebc833 2516 .len = sizeof(struct il3945_scan_cmd),
4bc85c13
WYG
2517 .flags = CMD_SIZE_HUGE,
2518 };
e2ebc833 2519 struct il3945_scan_cmd *scan;
4bc85c13
WYG
2520 u8 n_probes = 0;
2521 enum ieee80211_band band;
2522 bool is_active = false;
2523 int ret;
dd6d2a8a 2524 u16 len;
4bc85c13 2525
46bc8d4b 2526 lockdep_assert_held(&il->mutex);
4bc85c13 2527
46bc8d4b 2528 if (!il->scan_cmd) {
e7392364
SG
2529 il->scan_cmd =
2530 kmalloc(sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE,
2531 GFP_KERNEL);
46bc8d4b 2532 if (!il->scan_cmd) {
58de00a4 2533 D_SCAN("Fail to allocate scan memory\n");
4bc85c13
WYG
2534 return -ENOMEM;
2535 }
2536 }
46bc8d4b 2537 scan = il->scan_cmd;
e2ebc833 2538 memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
4bc85c13 2539
e2ebc833
SG
2540 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2541 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
4bc85c13 2542
7c2cde2e 2543 if (il_is_associated(il)) {
dd6d2a8a 2544 u16 interval;
4bc85c13
WYG
2545 u32 extra;
2546 u32 suspend_time = 100;
2547 u32 scan_suspend_time = 100;
2548
58de00a4 2549 D_INFO("Scanning while associated...\n");
4bc85c13 2550
dd6d2a8a 2551 interval = vif->bss_conf.beacon_int;
4bc85c13
WYG
2552
2553 scan->suspend_time = 0;
2554 scan->max_out_time = cpu_to_le32(200 * 1024);
2555 if (!interval)
2556 interval = suspend_time;
2557 /*
2558 * suspend time format:
2559 * 0-19: beacon interval in usec (time before exec.)
2560 * 20-23: 0
2561 * 24-31: number of beacons (suspend between channels)
2562 */
2563
2564 extra = (suspend_time / interval) << 24;
e7392364
SG
2565 scan_suspend_time =
2566 0xFF0FFFFF & (extra | ((suspend_time % interval) * 1024));
4bc85c13
WYG
2567
2568 scan->suspend_time = cpu_to_le32(scan_suspend_time);
58de00a4 2569 D_SCAN("suspend_time 0x%X beacon interval %d\n",
e7392364 2570 scan_suspend_time, interval);
4bc85c13
WYG
2571 }
2572
46bc8d4b 2573 if (il->scan_request->n_ssids) {
4bc85c13 2574 int i, p = 0;
58de00a4 2575 D_SCAN("Kicking off active scan\n");
46bc8d4b 2576 for (i = 0; i < il->scan_request->n_ssids; i++) {
4bc85c13 2577 /* always does wildcard anyway */
46bc8d4b 2578 if (!il->scan_request->ssids[i].ssid_len)
4bc85c13
WYG
2579 continue;
2580 scan->direct_scan[p].id = WLAN_EID_SSID;
2581 scan->direct_scan[p].len =
e7392364 2582 il->scan_request->ssids[i].ssid_len;
4bc85c13 2583 memcpy(scan->direct_scan[p].ssid,
46bc8d4b
SG
2584 il->scan_request->ssids[i].ssid,
2585 il->scan_request->ssids[i].ssid_len);
4bc85c13
WYG
2586 n_probes++;
2587 p++;
2588 }
2589 is_active = true;
2590 } else
58de00a4 2591 D_SCAN("Kicking off passive scan.\n");
4bc85c13
WYG
2592
2593 /* We don't build a direct scan probe request; the uCode will do
2594 * that based on the direct_mask added to each channel entry */
2595 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
b16db50a 2596 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
4bc85c13
WYG
2597 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2598
2599 /* flags + rate selection */
2600
46bc8d4b 2601 switch (il->scan_band) {
4bc85c13
WYG
2602 case IEEE80211_BAND_2GHZ:
2603 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2eb05816 2604 scan->tx_cmd.rate = RATE_1M_PLCP;
4bc85c13
WYG
2605 band = IEEE80211_BAND_2GHZ;
2606 break;
2607 case IEEE80211_BAND_5GHZ:
2eb05816 2608 scan->tx_cmd.rate = RATE_6M_PLCP;
4bc85c13
WYG
2609 band = IEEE80211_BAND_5GHZ;
2610 break;
2611 default:
9406f797 2612 IL_WARN("Invalid scan band\n");
4bc85c13
WYG
2613 return -EIO;
2614 }
2615
2616 /*
68acc4af
SG
2617 * If active scaning is requested but a certain channel is marked
2618 * passive, we can do active scanning if we detect transmissions. For
2619 * passive only scanning disable switching to active on any channel.
4bc85c13 2620 */
e7392364 2621 scan->good_CRC_th =
68acc4af 2622 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
e7392364
SG
2623
2624 len =
2625 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2626 vif->addr, il->scan_request->ie,
2627 il->scan_request->ie_len,
2628 IL_MAX_SCAN_SIZE - sizeof(*scan));
dd6d2a8a
SG
2629 scan->tx_cmd.len = cpu_to_le16(len);
2630
4bc85c13 2631 /* select Rx antennas */
46bc8d4b 2632 scan->flags |= il3945_get_antenna_flags(il);
4bc85c13 2633
e7392364
SG
2634 scan->channel_count =
2635 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2636 (void *)&scan->data[len], vif);
4bc85c13 2637 if (scan->channel_count == 0) {
58de00a4 2638 D_SCAN("channel count %d\n", scan->channel_count);
4bc85c13
WYG
2639 return -EIO;
2640 }
2641
e7392364
SG
2642 cmd.len +=
2643 le16_to_cpu(scan->tx_cmd.len) +
e2ebc833 2644 scan->channel_count * sizeof(struct il3945_scan_channel);
4bc85c13
WYG
2645 cmd.data = scan;
2646 scan->len = cpu_to_le16(cmd.len);
2647
a6766ccd 2648 set_bit(S_SCAN_HW, &il->status);
46bc8d4b 2649 ret = il_send_cmd_sync(il, &cmd);
4bc85c13 2650 if (ret)
a6766ccd 2651 clear_bit(S_SCAN_HW, &il->status);
4bc85c13
WYG
2652 return ret;
2653}
2654
e7392364
SG
2655void
2656il3945_post_scan(struct il_priv *il)
4bc85c13 2657{
4bc85c13
WYG
2658 /*
2659 * Since setting the RXON may have been deferred while
2660 * performing the scan, fire one off if needed
2661 */
c8b03958 2662 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
83007196 2663 il3945_commit_rxon(il);
4bc85c13
WYG
2664}
2665
e7392364
SG
2666static void
2667il3945_bg_restart(struct work_struct *data)
4bc85c13 2668{
46bc8d4b 2669 struct il_priv *il = container_of(data, struct il_priv, restart);
4bc85c13 2670
a6766ccd 2671 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2672 return;
2673
a6766ccd 2674 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
46bc8d4b 2675 mutex_lock(&il->mutex);
83007196
SG
2676 /* FIXME: vif can be dereferenced */
2677 il->vif = NULL;
46bc8d4b
SG
2678 il->is_open = 0;
2679 mutex_unlock(&il->mutex);
2680 il3945_down(il);
2681 ieee80211_restart_hw(il->hw);
4bc85c13 2682 } else {
46bc8d4b 2683 il3945_down(il);
4bc85c13 2684
46bc8d4b 2685 mutex_lock(&il->mutex);
a6766ccd 2686 if (test_bit(S_EXIT_PENDING, &il->status)) {
46bc8d4b 2687 mutex_unlock(&il->mutex);
4bc85c13 2688 return;
28a6e577 2689 }
4bc85c13 2690
46bc8d4b
SG
2691 __il3945_up(il);
2692 mutex_unlock(&il->mutex);
4bc85c13
WYG
2693 }
2694}
2695
e7392364
SG
2696static void
2697il3945_bg_rx_replenish(struct work_struct *data)
4bc85c13 2698{
e7392364 2699 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
4bc85c13 2700
46bc8d4b 2701 mutex_lock(&il->mutex);
a6766ccd 2702 if (test_bit(S_EXIT_PENDING, &il->status))
28a6e577 2703 goto out;
4bc85c13 2704
46bc8d4b 2705 il3945_rx_replenish(il);
28a6e577 2706out:
46bc8d4b 2707 mutex_unlock(&il->mutex);
4bc85c13
WYG
2708}
2709
e7392364
SG
2710void
2711il3945_post_associate(struct il_priv *il)
4bc85c13
WYG
2712{
2713 int rc = 0;
2714 struct ieee80211_conf *conf = NULL;
4bc85c13 2715
83007196 2716 if (!il->vif || !il->is_open)
4bc85c13
WYG
2717 return;
2718
83007196 2719 D_ASSOC("Associated as %d to: %pM\n", il->vif->bss_conf.aid,
c8b03958 2720 il->active.bssid_addr);
4bc85c13 2721
a6766ccd 2722 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2723 return;
2724
46bc8d4b 2725 il_scan_cancel_timeout(il, 200);
4bc85c13 2726
6278ddab 2727 conf = &il->hw->conf;
4bc85c13 2728
c8b03958 2729 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 2730 il3945_commit_rxon(il);
4bc85c13 2731
83007196 2732 rc = il_send_rxon_timing(il);
4bc85c13 2733 if (rc)
e7392364 2734 IL_WARN("C_RXON_TIMING failed - " "Attempting to continue.\n");
4bc85c13 2735
c8b03958 2736 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
4bc85c13 2737
83007196 2738 il->staging.assoc_id = cpu_to_le16(il->vif->bss_conf.aid);
4bc85c13 2739
83007196
SG
2740 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->bss_conf.aid,
2741 il->vif->bss_conf.beacon_int);
4bc85c13 2742
83007196 2743 if (il->vif->bss_conf.use_short_preamble)
c8b03958 2744 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2745 else
c8b03958 2746 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2747
c8b03958 2748 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
83007196 2749 if (il->vif->bss_conf.use_short_slot)
c8b03958 2750 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
4bc85c13 2751 else
c8b03958 2752 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
4bc85c13
WYG
2753 }
2754
83007196 2755 il3945_commit_rxon(il);
4bc85c13 2756
83007196 2757 switch (il->vif->type) {
4bc85c13 2758 case NL80211_IFTYPE_STATION:
46bc8d4b 2759 il3945_rate_scale_init(il->hw, IL_AP_ID);
4bc85c13
WYG
2760 break;
2761 case NL80211_IFTYPE_ADHOC:
46bc8d4b 2762 il3945_send_beacon_cmd(il);
4bc85c13
WYG
2763 break;
2764 default:
e7392364 2765 IL_ERR("%s Should not be called in %d mode\n", __func__,
83007196 2766 il->vif->type);
4bc85c13
WYG
2767 break;
2768 }
2769}
2770
2771/*****************************************************************************
2772 *
2773 * mac80211 entry point functions
2774 *
2775 *****************************************************************************/
2776
2777#define UCODE_READY_TIMEOUT (2 * HZ)
2778
e7392364
SG
2779static int
2780il3945_mac_start(struct ieee80211_hw *hw)
4bc85c13 2781{
46bc8d4b 2782 struct il_priv *il = hw->priv;
4bc85c13
WYG
2783 int ret;
2784
58de00a4 2785 D_MAC80211("enter\n");
4bc85c13
WYG
2786
2787 /* we should be verifying the device is ready to be opened */
46bc8d4b 2788 mutex_lock(&il->mutex);
4bc85c13
WYG
2789
2790 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2791 * ucode filename and max sizes are card-specific. */
2792
46bc8d4b
SG
2793 if (!il->ucode_code.len) {
2794 ret = il3945_read_ucode(il);
4bc85c13 2795 if (ret) {
9406f797 2796 IL_ERR("Could not read microcode: %d\n", ret);
46bc8d4b 2797 mutex_unlock(&il->mutex);
4bc85c13
WYG
2798 goto out_release_irq;
2799 }
2800 }
2801
46bc8d4b 2802 ret = __il3945_up(il);
4bc85c13 2803
46bc8d4b 2804 mutex_unlock(&il->mutex);
4bc85c13
WYG
2805
2806 if (ret)
2807 goto out_release_irq;
2808
58de00a4 2809 D_INFO("Start UP work.\n");
4bc85c13
WYG
2810
2811 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
2812 * mac80211 will not be run successfully. */
46bc8d4b 2813 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG
2814 test_bit(S_READY, &il->status),
2815 UCODE_READY_TIMEOUT);
4bc85c13 2816 if (!ret) {
a6766ccd 2817 if (!test_bit(S_READY, &il->status)) {
e7392364
SG
2818 IL_ERR("Wait for START_ALIVE timeout after %dms.\n",
2819 jiffies_to_msecs(UCODE_READY_TIMEOUT));
4bc85c13
WYG
2820 ret = -ETIMEDOUT;
2821 goto out_release_irq;
2822 }
2823 }
2824
2825 /* ucode is running and will send rfkill notifications,
2826 * no need to poll the killswitch state anymore */
46bc8d4b 2827 cancel_delayed_work(&il->_3945.rfkill_poll);
4bc85c13 2828
46bc8d4b 2829 il->is_open = 1;
58de00a4 2830 D_MAC80211("leave\n");
4bc85c13
WYG
2831 return 0;
2832
2833out_release_irq:
46bc8d4b 2834 il->is_open = 0;
58de00a4 2835 D_MAC80211("leave - failed\n");
4bc85c13
WYG
2836 return ret;
2837}
2838
e7392364
SG
2839static void
2840il3945_mac_stop(struct ieee80211_hw *hw)
4bc85c13 2841{
46bc8d4b 2842 struct il_priv *il = hw->priv;
4bc85c13 2843
58de00a4 2844 D_MAC80211("enter\n");
4bc85c13 2845
46bc8d4b 2846 if (!il->is_open) {
58de00a4 2847 D_MAC80211("leave - skip\n");
4bc85c13
WYG
2848 return;
2849 }
2850
46bc8d4b 2851 il->is_open = 0;
4bc85c13 2852
46bc8d4b 2853 il3945_down(il);
4bc85c13 2854
46bc8d4b 2855 flush_workqueue(il->workqueue);
4bc85c13
WYG
2856
2857 /* start polling the killswitch state again */
46bc8d4b 2858 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
4bc85c13
WYG
2859 round_jiffies_relative(2 * HZ));
2860
58de00a4 2861 D_MAC80211("leave\n");
4bc85c13
WYG
2862}
2863
e7392364
SG
2864static void
2865il3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
4bc85c13 2866{
46bc8d4b 2867 struct il_priv *il = hw->priv;
4bc85c13 2868
58de00a4 2869 D_MAC80211("enter\n");
4bc85c13 2870
58de00a4 2871 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e7392364 2872 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
4bc85c13 2873
46bc8d4b 2874 if (il3945_tx_skb(il, skb))
4bc85c13
WYG
2875 dev_kfree_skb_any(skb);
2876
58de00a4 2877 D_MAC80211("leave\n");
4bc85c13
WYG
2878}
2879
e7392364
SG
2880void
2881il3945_config_ap(struct il_priv *il)
4bc85c13 2882{
83007196 2883 struct ieee80211_vif *vif = il->vif;
4bc85c13
WYG
2884 int rc = 0;
2885
a6766ccd 2886 if (test_bit(S_EXIT_PENDING, &il->status))
4bc85c13
WYG
2887 return;
2888
2889 /* The following should be done only at AP bring up */
7c2cde2e 2890 if (!(il_is_associated(il))) {
4bc85c13
WYG
2891
2892 /* RXON - unassoc (to set timing command) */
c8b03958 2893 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 2894 il3945_commit_rxon(il);
4bc85c13
WYG
2895
2896 /* RXON Timing */
83007196 2897 rc = il_send_rxon_timing(il);
4bc85c13 2898 if (rc)
4d69c752 2899 IL_WARN("C_RXON_TIMING failed - "
e7392364 2900 "Attempting to continue.\n");
4bc85c13 2901
c8b03958 2902 il->staging.assoc_id = 0;
4bc85c13
WYG
2903
2904 if (vif->bss_conf.use_short_preamble)
c8b03958 2905 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2906 else
c8b03958 2907 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
4bc85c13 2908
c8b03958 2909 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
4bc85c13 2910 if (vif->bss_conf.use_short_slot)
c8b03958 2911 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
4bc85c13 2912 else
c8b03958 2913 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
4bc85c13
WYG
2914 }
2915 /* restore RXON assoc */
c8b03958 2916 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
83007196 2917 il3945_commit_rxon(il);
4bc85c13 2918 }
46bc8d4b 2919 il3945_send_beacon_cmd(il);
4bc85c13
WYG
2920}
2921
e7392364
SG
2922static int
2923il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2924 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2925 struct ieee80211_key_conf *key)
4bc85c13 2926{
46bc8d4b 2927 struct il_priv *il = hw->priv;
4bc85c13 2928 int ret = 0;
e2ebc833 2929 u8 sta_id = IL_INVALID_STATION;
4bc85c13
WYG
2930 u8 static_key;
2931
58de00a4 2932 D_MAC80211("enter\n");
4bc85c13 2933
e2ebc833 2934 if (il3945_mod_params.sw_crypto) {
58de00a4 2935 D_MAC80211("leave - hwcrypto disabled\n");
4bc85c13
WYG
2936 return -EOPNOTSUPP;
2937 }
2938
2939 /*
2940 * To support IBSS RSN, don't program group keys in IBSS, the
2941 * hardware will then not attempt to decrypt the frames.
2942 */
2943 if (vif->type == NL80211_IFTYPE_ADHOC &&
2944 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2945 return -EOPNOTSUPP;
2946
7c2cde2e 2947 static_key = !il_is_associated(il);
4bc85c13
WYG
2948
2949 if (!static_key) {
83007196 2950 sta_id = il_sta_id_or_broadcast(il, sta);
e2ebc833 2951 if (sta_id == IL_INVALID_STATION)
4bc85c13
WYG
2952 return -EINVAL;
2953 }
2954
46bc8d4b
SG
2955 mutex_lock(&il->mutex);
2956 il_scan_cancel_timeout(il, 100);
4bc85c13
WYG
2957
2958 switch (cmd) {
2959 case SET_KEY:
2960 if (static_key)
46bc8d4b 2961 ret = il3945_set_static_key(il, key);
4bc85c13 2962 else
46bc8d4b 2963 ret = il3945_set_dynamic_key(il, key, sta_id);
58de00a4 2964 D_MAC80211("enable hwcrypto key\n");
4bc85c13
WYG
2965 break;
2966 case DISABLE_KEY:
2967 if (static_key)
46bc8d4b 2968 ret = il3945_remove_static_key(il);
4bc85c13 2969 else
46bc8d4b 2970 ret = il3945_clear_sta_key_info(il, sta_id);
58de00a4 2971 D_MAC80211("disable hwcrypto key\n");
4bc85c13
WYG
2972 break;
2973 default:
2974 ret = -EINVAL;
2975 }
2976
46bc8d4b 2977 mutex_unlock(&il->mutex);
58de00a4 2978 D_MAC80211("leave\n");
4bc85c13
WYG
2979
2980 return ret;
2981}
2982
e7392364
SG
2983static int
2984il3945_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2985 struct ieee80211_sta *sta)
4bc85c13 2986{
46bc8d4b 2987 struct il_priv *il = hw->priv;
e2ebc833 2988 struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
4bc85c13
WYG
2989 int ret;
2990 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
2991 u8 sta_id;
2992
e7392364 2993 D_INFO("received request to add station %pM\n", sta->addr);
46bc8d4b 2994 mutex_lock(&il->mutex);
e7392364 2995 D_INFO("proceeding to add station %pM\n", sta->addr);
e2ebc833 2996 sta_priv->common.sta_id = IL_INVALID_STATION;
4bc85c13 2997
83007196 2998 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
4bc85c13 2999 if (ret) {
e7392364 3000 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
4bc85c13 3001 /* Should we return success if return code is EEXIST ? */
46bc8d4b 3002 mutex_unlock(&il->mutex);
4bc85c13
WYG
3003 return ret;
3004 }
3005
3006 sta_priv->common.sta_id = sta_id;
3007
3008 /* Initialize rate scaling */
e7392364 3009 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
46bc8d4b
SG
3010 il3945_rs_rate_init(il, sta, sta_id);
3011 mutex_unlock(&il->mutex);
4bc85c13
WYG
3012
3013 return 0;
3014}
3015
e7392364
SG
3016static void
3017il3945_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
3018 unsigned int *total_flags, u64 multicast)
4bc85c13 3019{
46bc8d4b 3020 struct il_priv *il = hw->priv;
4bc85c13 3021 __le32 filter_or = 0, filter_nand = 0;
4bc85c13
WYG
3022
3023#define CHK(test, flag) do { \
3024 if (*total_flags & (test)) \
3025 filter_or |= (flag); \
3026 else \
3027 filter_nand |= (flag); \
3028 } while (0)
3029
e7392364
SG
3030 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
3031 *total_flags);
4bc85c13
WYG
3032
3033 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3034 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3035 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3036
3037#undef CHK
3038
46bc8d4b 3039 mutex_lock(&il->mutex);
4bc85c13 3040
c8b03958
SG
3041 il->staging.filter_flags &= ~filter_nand;
3042 il->staging.filter_flags |= filter_or;
4bc85c13
WYG
3043
3044 /*
3045 * Not committing directly because hardware can perform a scan,
3046 * but even if hw is ready, committing here breaks for some reason,
3047 * we'll eventually commit the filter flags change anyway.
3048 */
3049
46bc8d4b 3050 mutex_unlock(&il->mutex);
4bc85c13
WYG
3051
3052 /*
3053 * Receiving all multicast frames is always enabled by the
e2ebc833 3054 * default flags setup in il_connection_init_rx_config()
4bc85c13
WYG
3055 * since we currently do not support programming multicast
3056 * filters into the device.
3057 */
e7392364
SG
3058 *total_flags &=
3059 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3060 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4bc85c13
WYG
3061}
3062
4bc85c13
WYG
3063/*****************************************************************************
3064 *
3065 * sysfs attributes
3066 *
3067 *****************************************************************************/
3068
d3175167 3069#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
3070
3071/*
3072 * The following adds a new attribute to the sysfs representation
3073 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3074 * used for controlling the debug level.
3075 *
3076 * See the level definitions in iwl for details.
3077 *
3078 * The debug_level being managed using sysfs below is a per device debug
3079 * level that is used instead of the global debug level if it (the per
3080 * device debug level) is set.
3081 */
e7392364
SG
3082static ssize_t
3083il3945_show_debug_level(struct device *d, struct device_attribute *attr,
3084 char *buf)
4bc85c13 3085{
46bc8d4b
SG
3086 struct il_priv *il = dev_get_drvdata(d);
3087 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4bc85c13 3088}
e7392364
SG
3089
3090static ssize_t
3091il3945_store_debug_level(struct device *d, struct device_attribute *attr,
3092 const char *buf, size_t count)
4bc85c13 3093{
46bc8d4b 3094 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3095 unsigned long val;
3096 int ret;
3097
3098 ret = strict_strtoul(buf, 0, &val);
3099 if (ret)
9406f797 3100 IL_INFO("%s is not in hex or decimal form.\n", buf);
4bc85c13 3101 else {
46bc8d4b
SG
3102 il->debug_level = val;
3103 if (il_alloc_traffic_mem(il))
e7392364 3104 IL_ERR("Not enough memory to generate traffic log\n");
4bc85c13
WYG
3105 }
3106 return strnlen(buf, count);
3107}
3108
e7392364
SG
3109static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il3945_show_debug_level,
3110 il3945_store_debug_level);
4bc85c13 3111
d3175167 3112#endif /* CONFIG_IWLEGACY_DEBUG */
4bc85c13 3113
e7392364
SG
3114static ssize_t
3115il3945_show_temperature(struct device *d, struct device_attribute *attr,
3116 char *buf)
4bc85c13 3117{
46bc8d4b 3118 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3119
46bc8d4b 3120 if (!il_is_alive(il))
4bc85c13
WYG
3121 return -EAGAIN;
3122
46bc8d4b 3123 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
4bc85c13
WYG
3124}
3125
e2ebc833 3126static DEVICE_ATTR(temperature, S_IRUGO, il3945_show_temperature, NULL);
4bc85c13 3127
e7392364
SG
3128static ssize_t
3129il3945_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3130{
46bc8d4b
SG
3131 struct il_priv *il = dev_get_drvdata(d);
3132 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4bc85c13
WYG
3133}
3134
e7392364
SG
3135static ssize_t
3136il3945_store_tx_power(struct device *d, struct device_attribute *attr,
3137 const char *buf, size_t count)
4bc85c13 3138{
46bc8d4b 3139 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3140 char *p = (char *)buf;
3141 u32 val;
3142
3143 val = simple_strtoul(p, &p, 10);
3144 if (p == buf)
9406f797 3145 IL_INFO(": %s is not in decimal form.\n", buf);
4bc85c13 3146 else
46bc8d4b 3147 il3945_hw_reg_set_txpower(il, val);
4bc85c13
WYG
3148
3149 return count;
3150}
3151
e7392364
SG
3152static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il3945_show_tx_power,
3153 il3945_store_tx_power);
4bc85c13 3154
e7392364
SG
3155static ssize_t
3156il3945_show_flags(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3157{
46bc8d4b 3158 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3159
c8b03958 3160 return sprintf(buf, "0x%04X\n", il->active.flags);
4bc85c13
WYG
3161}
3162
e7392364
SG
3163static ssize_t
3164il3945_store_flags(struct device *d, struct device_attribute *attr,
3165 const char *buf, size_t count)
4bc85c13 3166{
46bc8d4b 3167 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3168 u32 flags = simple_strtoul(buf, NULL, 0);
4bc85c13 3169
46bc8d4b 3170 mutex_lock(&il->mutex);
c8b03958 3171 if (le32_to_cpu(il->staging.flags) != flags) {
4bc85c13 3172 /* Cancel any currently running scans... */
46bc8d4b 3173 if (il_scan_cancel_timeout(il, 100))
9406f797 3174 IL_WARN("Could not cancel scan.\n");
4bc85c13 3175 else {
e7392364 3176 D_INFO("Committing rxon.flags = 0x%04X\n", flags);
c8b03958 3177 il->staging.flags = cpu_to_le32(flags);
83007196 3178 il3945_commit_rxon(il);
4bc85c13
WYG
3179 }
3180 }
46bc8d4b 3181 mutex_unlock(&il->mutex);
4bc85c13
WYG
3182
3183 return count;
3184}
3185
e7392364
SG
3186static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, il3945_show_flags,
3187 il3945_store_flags);
4bc85c13 3188
e7392364
SG
3189static ssize_t
3190il3945_show_filter_flags(struct device *d, struct device_attribute *attr,
3191 char *buf)
4bc85c13 3192{
46bc8d4b 3193 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3194
c8b03958 3195 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
4bc85c13
WYG
3196}
3197
e7392364
SG
3198static ssize_t
3199il3945_store_filter_flags(struct device *d, struct device_attribute *attr,
3200 const char *buf, size_t count)
4bc85c13 3201{
46bc8d4b 3202 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3203 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3204
46bc8d4b 3205 mutex_lock(&il->mutex);
c8b03958 3206 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
4bc85c13 3207 /* Cancel any currently running scans... */
46bc8d4b 3208 if (il_scan_cancel_timeout(il, 100))
9406f797 3209 IL_WARN("Could not cancel scan.\n");
4bc85c13 3210 else {
e7392364
SG
3211 D_INFO("Committing rxon.filter_flags = " "0x%04X\n",
3212 filter_flags);
c8b03958 3213 il->staging.filter_flags = cpu_to_le32(filter_flags);
83007196 3214 il3945_commit_rxon(il);
4bc85c13
WYG
3215 }
3216 }
46bc8d4b 3217 mutex_unlock(&il->mutex);
4bc85c13
WYG
3218
3219 return count;
3220}
3221
e2ebc833
SG
3222static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, il3945_show_filter_flags,
3223 il3945_store_filter_flags);
4bc85c13 3224
e7392364
SG
3225static ssize_t
3226il3945_show_measurement(struct device *d, struct device_attribute *attr,
3227 char *buf)
4bc85c13 3228{
46bc8d4b 3229 struct il_priv *il = dev_get_drvdata(d);
e2ebc833 3230 struct il_spectrum_notification measure_report;
4bc85c13 3231 u32 size = sizeof(measure_report), len = 0, ofs = 0;
1722f8e1 3232 u8 *data = (u8 *) &measure_report;
4bc85c13
WYG
3233 unsigned long flags;
3234
46bc8d4b
SG
3235 spin_lock_irqsave(&il->lock, flags);
3236 if (!(il->measurement_status & MEASUREMENT_READY)) {
3237 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13
WYG
3238 return 0;
3239 }
46bc8d4b
SG
3240 memcpy(&measure_report, &il->measure_report, size);
3241 il->measurement_status = 0;
3242 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3243
232913b5 3244 while (size && PAGE_SIZE - len) {
4bc85c13
WYG
3245 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3246 PAGE_SIZE - len, 1);
3247 len = strlen(buf);
3248 if (PAGE_SIZE - len)
3249 buf[len++] = '\n';
3250
3251 ofs += 16;
3252 size -= min(size, 16U);
3253 }
3254
3255 return len;
3256}
3257
e7392364
SG
3258static ssize_t
3259il3945_store_measurement(struct device *d, struct device_attribute *attr,
3260 const char *buf, size_t count)
4bc85c13 3261{
46bc8d4b 3262 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3263 struct ieee80211_measurement_params params = {
c8b03958 3264 .channel = le16_to_cpu(il->active.channel),
46bc8d4b 3265 .start_time = cpu_to_le64(il->_3945.last_tsf),
4bc85c13
WYG
3266 .duration = cpu_to_le16(1),
3267 };
e2ebc833 3268 u8 type = IL_MEASURE_BASIC;
4bc85c13
WYG
3269 u8 buffer[32];
3270 u8 channel;
3271
3272 if (count) {
3273 char *p = buffer;
3274 strncpy(buffer, buf, min(sizeof(buffer), count));
3275 channel = simple_strtoul(p, NULL, 0);
3276 if (channel)
3277 params.channel = channel;
3278
3279 p = buffer;
3280 while (*p && *p != ' ')
3281 p++;
3282 if (*p)
3283 type = simple_strtoul(p + 1, NULL, 0);
3284 }
3285
e7392364
SG
3286 D_INFO("Invoking measurement of type %d on " "channel %d (for '%s')\n",
3287 type, params.channel, buf);
46bc8d4b 3288 il3945_get_measurement(il, &params, type);
4bc85c13
WYG
3289
3290 return count;
3291}
3292
e7392364
SG
3293static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, il3945_show_measurement,
3294 il3945_store_measurement);
4bc85c13 3295
e7392364
SG
3296static ssize_t
3297il3945_store_retry_rate(struct device *d, struct device_attribute *attr,
3298 const char *buf, size_t count)
4bc85c13 3299{
46bc8d4b 3300 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3301
46bc8d4b
SG
3302 il->retry_rate = simple_strtoul(buf, NULL, 0);
3303 if (il->retry_rate <= 0)
3304 il->retry_rate = 1;
4bc85c13
WYG
3305
3306 return count;
3307}
3308
e7392364
SG
3309static ssize_t
3310il3945_show_retry_rate(struct device *d, struct device_attribute *attr,
3311 char *buf)
4bc85c13 3312{
46bc8d4b
SG
3313 struct il_priv *il = dev_get_drvdata(d);
3314 return sprintf(buf, "%d", il->retry_rate);
4bc85c13
WYG
3315}
3316
e2ebc833
SG
3317static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, il3945_show_retry_rate,
3318 il3945_store_retry_rate);
4bc85c13 3319
e7392364
SG
3320static ssize_t
3321il3945_show_channels(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13
WYG
3322{
3323 /* all this shit doesn't belong into sysfs anyway */
3324 return 0;
3325}
3326
e2ebc833 3327static DEVICE_ATTR(channels, S_IRUSR, il3945_show_channels, NULL);
4bc85c13 3328
e7392364
SG
3329static ssize_t
3330il3945_show_antenna(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3331{
46bc8d4b 3332 struct il_priv *il = dev_get_drvdata(d);
4bc85c13 3333
46bc8d4b 3334 if (!il_is_alive(il))
4bc85c13
WYG
3335 return -EAGAIN;
3336
e2ebc833 3337 return sprintf(buf, "%d\n", il3945_mod_params.antenna);
4bc85c13
WYG
3338}
3339
e7392364
SG
3340static ssize_t
3341il3945_store_antenna(struct device *d, struct device_attribute *attr,
3342 const char *buf, size_t count)
4bc85c13 3343{
46bc8d4b 3344 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
4bc85c13
WYG
3345 int ant;
3346
3347 if (count == 0)
3348 return 0;
3349
3350 if (sscanf(buf, "%1i", &ant) != 1) {
58de00a4 3351 D_INFO("not in hex or decimal form.\n");
4bc85c13
WYG
3352 return count;
3353 }
3354
232913b5 3355 if (ant >= 0 && ant <= 2) {
58de00a4 3356 D_INFO("Setting antenna select to %d.\n", ant);
e2ebc833 3357 il3945_mod_params.antenna = (enum il3945_antenna)ant;
4bc85c13 3358 } else
58de00a4 3359 D_INFO("Bad antenna select value %d.\n", ant);
4bc85c13 3360
4bc85c13
WYG
3361 return count;
3362}
3363
e7392364
SG
3364static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, il3945_show_antenna,
3365 il3945_store_antenna);
4bc85c13 3366
e7392364
SG
3367static ssize_t
3368il3945_show_status(struct device *d, struct device_attribute *attr, char *buf)
4bc85c13 3369{
46bc8d4b
SG
3370 struct il_priv *il = dev_get_drvdata(d);
3371 if (!il_is_alive(il))
4bc85c13 3372 return -EAGAIN;
46bc8d4b 3373 return sprintf(buf, "0x%08x\n", (int)il->status);
4bc85c13
WYG
3374}
3375
e2ebc833 3376static DEVICE_ATTR(status, S_IRUGO, il3945_show_status, NULL);
4bc85c13 3377
e7392364
SG
3378static ssize_t
3379il3945_dump_error_log(struct device *d, struct device_attribute *attr,
3380 const char *buf, size_t count)
4bc85c13 3381{
46bc8d4b 3382 struct il_priv *il = dev_get_drvdata(d);
4bc85c13
WYG
3383 char *p = (char *)buf;
3384
3385 if (p[0] == '1')
46bc8d4b 3386 il3945_dump_nic_error_log(il);
4bc85c13
WYG
3387
3388 return strnlen(buf, count);
3389}
3390
e2ebc833 3391static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, il3945_dump_error_log);
4bc85c13
WYG
3392
3393/*****************************************************************************
3394 *
3395 * driver setup and tear down
3396 *
3397 *****************************************************************************/
3398
e7392364
SG
3399static void
3400il3945_setup_deferred_work(struct il_priv *il)
4bc85c13 3401{
46bc8d4b 3402 il->workqueue = create_singlethread_workqueue(DRV_NAME);
4bc85c13 3403
46bc8d4b 3404 init_waitqueue_head(&il->wait_command_queue);
4bc85c13 3405
46bc8d4b
SG
3406 INIT_WORK(&il->restart, il3945_bg_restart);
3407 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3408 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3409 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3410 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
4bc85c13 3411
46bc8d4b 3412 il_setup_scan_deferred_work(il);
4bc85c13 3413
46bc8d4b 3414 il3945_hw_setup_deferred_work(il);
4bc85c13 3415
46bc8d4b
SG
3416 init_timer(&il->watchdog);
3417 il->watchdog.data = (unsigned long)il;
3418 il->watchdog.function = il_bg_watchdog;
4bc85c13 3419
e7392364
SG
3420 tasklet_init(&il->irq_tasklet,
3421 (void (*)(unsigned long))il3945_irq_tasklet,
3422 (unsigned long)il);
4bc85c13
WYG
3423}
3424
e7392364
SG
3425static void
3426il3945_cancel_deferred_work(struct il_priv *il)
4bc85c13 3427{
46bc8d4b 3428 il3945_hw_cancel_deferred_work(il);
4bc85c13 3429
46bc8d4b
SG
3430 cancel_delayed_work_sync(&il->init_alive_start);
3431 cancel_delayed_work(&il->alive_start);
4bc85c13 3432
46bc8d4b 3433 il_cancel_scan_deferred_work(il);
4bc85c13
WYG
3434}
3435
e2ebc833 3436static struct attribute *il3945_sysfs_entries[] = {
4bc85c13
WYG
3437 &dev_attr_antenna.attr,
3438 &dev_attr_channels.attr,
3439 &dev_attr_dump_errors.attr,
3440 &dev_attr_flags.attr,
3441 &dev_attr_filter_flags.attr,
3442 &dev_attr_measurement.attr,
3443 &dev_attr_retry_rate.attr,
3444 &dev_attr_status.attr,
3445 &dev_attr_temperature.attr,
3446 &dev_attr_tx_power.attr,
d3175167 3447#ifdef CONFIG_IWLEGACY_DEBUG
4bc85c13
WYG
3448 &dev_attr_debug_level.attr,
3449#endif
3450 NULL
3451};
3452
e2ebc833 3453static struct attribute_group il3945_attribute_group = {
4bc85c13 3454 .name = NULL, /* put in device directory */
e2ebc833 3455 .attrs = il3945_sysfs_entries,
4bc85c13
WYG
3456};
3457
c39ae9fd 3458struct ieee80211_ops il3945_mac_ops = {
e2ebc833
SG
3459 .tx = il3945_mac_tx,
3460 .start = il3945_mac_start,
3461 .stop = il3945_mac_stop,
3462 .add_interface = il_mac_add_interface,
3463 .remove_interface = il_mac_remove_interface,
3464 .change_interface = il_mac_change_interface,
3465 .config = il_mac_config,
3466 .configure_filter = il3945_configure_filter,
3467 .set_key = il3945_mac_set_key,
3468 .conf_tx = il_mac_conf_tx,
3469 .reset_tsf = il_mac_reset_tsf,
3470 .bss_info_changed = il_mac_bss_info_changed,
3471 .hw_scan = il_mac_hw_scan,
3472 .sta_add = il3945_mac_sta_add,
3473 .sta_remove = il_mac_sta_remove,
3474 .tx_last_beacon = il_mac_tx_last_beacon,
4bc85c13
WYG
3475};
3476
e7392364
SG
3477static int
3478il3945_init_drv(struct il_priv *il)
4bc85c13
WYG
3479{
3480 int ret;
46bc8d4b 3481 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
4bc85c13 3482
46bc8d4b
SG
3483 il->retry_rate = 1;
3484 il->beacon_skb = NULL;
4bc85c13 3485
46bc8d4b
SG
3486 spin_lock_init(&il->sta_lock);
3487 spin_lock_init(&il->hcmd_lock);
4bc85c13 3488
46bc8d4b 3489 INIT_LIST_HEAD(&il->free_frames);
4bc85c13 3490
46bc8d4b 3491 mutex_init(&il->mutex);
4bc85c13 3492
46bc8d4b
SG
3493 il->ieee_channels = NULL;
3494 il->ieee_rates = NULL;
3495 il->band = IEEE80211_BAND_2GHZ;
4bc85c13 3496
46bc8d4b
SG
3497 il->iw_mode = NL80211_IFTYPE_STATION;
3498 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
4bc85c13
WYG
3499
3500 /* initialize force reset */
46bc8d4b 3501 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
4bc85c13 3502
4bc85c13 3503 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
9406f797 3504 IL_WARN("Unsupported EEPROM version: 0x%04X\n",
e7392364 3505 eeprom->version);
4bc85c13
WYG
3506 ret = -EINVAL;
3507 goto err;
3508 }
46bc8d4b 3509 ret = il_init_channel_map(il);
4bc85c13 3510 if (ret) {
9406f797 3511 IL_ERR("initializing regulatory failed: %d\n", ret);
4bc85c13
WYG
3512 goto err;
3513 }
3514
3515 /* Set up txpower settings in driver for all channels */
46bc8d4b 3516 if (il3945_txpower_set_from_eeprom(il)) {
4bc85c13
WYG
3517 ret = -EIO;
3518 goto err_free_channel_map;
3519 }
3520
46bc8d4b 3521 ret = il_init_geos(il);
4bc85c13 3522 if (ret) {
9406f797 3523 IL_ERR("initializing geos failed: %d\n", ret);
4bc85c13
WYG
3524 goto err_free_channel_map;
3525 }
46bc8d4b 3526 il3945_init_hw_rates(il, il->ieee_rates);
4bc85c13
WYG
3527
3528 return 0;
3529
3530err_free_channel_map:
46bc8d4b 3531 il_free_channel_map(il);
4bc85c13
WYG
3532err:
3533 return ret;
3534}
3535
d3175167 3536#define IL3945_MAX_PROBE_REQUEST 200
4bc85c13 3537
e7392364
SG
3538static int
3539il3945_setup_mac(struct il_priv *il)
4bc85c13
WYG
3540{
3541 int ret;
46bc8d4b 3542 struct ieee80211_hw *hw = il->hw;
4bc85c13
WYG
3543
3544 hw->rate_control_algorithm = "iwl-3945-rs";
e2ebc833
SG
3545 hw->sta_data_size = sizeof(struct il3945_sta_priv);
3546 hw->vif_data_size = sizeof(struct il_vif_priv);
4bc85c13
WYG
3547
3548 /* Tell mac80211 our characteristics */
e7392364 3549 hw->flags = IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_SPECTRUM_MGMT;
4bc85c13 3550
8c9c48d5
SG
3551 hw->wiphy->interface_modes =
3552 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
4bc85c13 3553
e7392364
SG
3554 hw->wiphy->flags |=
3555 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS |
3556 WIPHY_FLAG_IBSS_RSN;
4bc85c13
WYG
3557
3558 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3559 /* we create the 802.11 header and a zero-length SSID element */
d3175167 3560 hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
4bc85c13
WYG
3561
3562 /* Default value; 4 EDCA QOS priorities */
3563 hw->queues = 4;
3564
46bc8d4b
SG
3565 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
3566 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
e7392364 3567 &il->bands[IEEE80211_BAND_2GHZ];
4bc85c13 3568
46bc8d4b
SG
3569 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
3570 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
e7392364 3571 &il->bands[IEEE80211_BAND_5GHZ];
4bc85c13 3572
46bc8d4b 3573 il_leds_init(il);
4bc85c13 3574
46bc8d4b 3575 ret = ieee80211_register_hw(il->hw);
4bc85c13 3576 if (ret) {
9406f797 3577 IL_ERR("Failed to register hw (error %d)\n", ret);
4bc85c13
WYG
3578 return ret;
3579 }
46bc8d4b 3580 il->mac80211_registered = 1;
4bc85c13
WYG
3581
3582 return 0;
3583}
3584
e7392364
SG
3585static int
3586il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4bc85c13 3587{
7c2cde2e 3588 int err = 0;
46bc8d4b 3589 struct il_priv *il;
4bc85c13 3590 struct ieee80211_hw *hw;
e2ebc833
SG
3591 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3592 struct il3945_eeprom *eeprom;
4bc85c13
WYG
3593 unsigned long flags;
3594
3595 /***********************
3596 * 1. Allocating HW data
3597 * ********************/
3598
c39ae9fd
SG
3599 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il3945_mac_ops);
3600 if (!hw) {
4bc85c13
WYG
3601 err = -ENOMEM;
3602 goto out;
3603 }
46bc8d4b 3604 il = hw->priv;
c39ae9fd 3605 il->hw = hw;
4bc85c13
WYG
3606 SET_IEEE80211_DEV(hw, &pdev->dev);
3607
d3175167 3608 il->cmd_queue = IL39_CMD_QUEUE_NUM;
4bc85c13 3609
4bc85c13
WYG
3610 /*
3611 * Disabling hardware scan means that mac80211 will perform scans
3612 * "the hard way", rather than using device's scan.
3613 */
e2ebc833 3614 if (il3945_mod_params.disable_hw_scan) {
58de00a4 3615 D_INFO("Disabling hw_scan\n");
c39ae9fd 3616 il3945_mac_ops.hw_scan = NULL;
4bc85c13
WYG
3617 }
3618
58de00a4 3619 D_INFO("*** LOAD DRIVER ***\n");
46bc8d4b 3620 il->cfg = cfg;
c39ae9fd 3621 il->ops = &il3945_ops;
46bc8d4b
SG
3622 il->pci_dev = pdev;
3623 il->inta_mask = CSR_INI_SET_MASK;
4bc85c13 3624
46bc8d4b 3625 if (il_alloc_traffic_mem(il))
9406f797 3626 IL_ERR("Not enough memory to generate traffic log\n");
4bc85c13
WYG
3627
3628 /***************************
3629 * 2. Initializing PCI bus
3630 * *************************/
e7392364
SG
3631 pci_disable_link_state(pdev,
3632 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3633 PCIE_LINK_STATE_CLKPM);
4bc85c13
WYG
3634
3635 if (pci_enable_device(pdev)) {
3636 err = -ENODEV;
3637 goto out_ieee80211_free_hw;
3638 }
3639
3640 pci_set_master(pdev);
3641
3642 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3643 if (!err)
3644 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3645 if (err) {
9406f797 3646 IL_WARN("No suitable DMA available.\n");
4bc85c13
WYG
3647 goto out_pci_disable_device;
3648 }
3649
46bc8d4b 3650 pci_set_drvdata(pdev, il);
4bc85c13
WYG
3651 err = pci_request_regions(pdev, DRV_NAME);
3652 if (err)
3653 goto out_pci_disable_device;
3654
3655 /***********************
3656 * 3. Read REV Register
3657 * ********************/
46bc8d4b
SG
3658 il->hw_base = pci_iomap(pdev, 0, 0);
3659 if (!il->hw_base) {
4bc85c13
WYG
3660 err = -ENODEV;
3661 goto out_pci_release_regions;
3662 }
3663
58de00a4 3664 D_INFO("pci_resource_len = 0x%08llx\n",
e7392364 3665 (unsigned long long)pci_resource_len(pdev, 0));
58de00a4 3666 D_INFO("pci_resource_base = %p\n", il->hw_base);
4bc85c13
WYG
3667
3668 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3669 * PCI Tx retries from interfering with C3 CPU state */
3670 pci_write_config_byte(pdev, 0x41, 0x00);
3671
3672 /* these spin locks will be used in apm_ops.init and EEPROM access
3673 * we should init now
3674 */
46bc8d4b
SG
3675 spin_lock_init(&il->reg_lock);
3676 spin_lock_init(&il->lock);
4bc85c13
WYG
3677
3678 /*
3679 * stop and reset the on-board processor just in case it is in a
3680 * strange state ... like being left stranded by a primary kernel
3681 * and this is now the kdump kernel trying to start up
3682 */
841b2cca 3683 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4bc85c13
WYG
3684
3685 /***********************
3686 * 4. Read EEPROM
3687 * ********************/
3688
3689 /* Read the EEPROM */
46bc8d4b 3690 err = il_eeprom_init(il);
4bc85c13 3691 if (err) {
9406f797 3692 IL_ERR("Unable to init EEPROM\n");
4bc85c13
WYG
3693 goto out_iounmap;
3694 }
3695 /* MAC Address location in EEPROM same for 3945/4965 */
46bc8d4b 3696 eeprom = (struct il3945_eeprom *)il->eeprom;
58de00a4 3697 D_INFO("MAC address: %pM\n", eeprom->mac_address);
46bc8d4b 3698 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
4bc85c13
WYG
3699
3700 /***********************
3701 * 5. Setup HW Constants
3702 * ********************/
3703 /* Device-specific setup */
46bc8d4b 3704 if (il3945_hw_set_hw_params(il)) {
9406f797 3705 IL_ERR("failed to set hw settings\n");
4bc85c13
WYG
3706 goto out_eeprom_free;
3707 }
3708
3709 /***********************
46bc8d4b 3710 * 6. Setup il
4bc85c13
WYG
3711 * ********************/
3712
46bc8d4b 3713 err = il3945_init_drv(il);
4bc85c13 3714 if (err) {
9406f797 3715 IL_ERR("initializing driver failed\n");
4bc85c13
WYG
3716 goto out_unset_hw_params;
3717 }
3718
e7392364 3719 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
4bc85c13
WYG
3720
3721 /***********************
3722 * 7. Setup Services
3723 * ********************/
3724
46bc8d4b
SG
3725 spin_lock_irqsave(&il->lock, flags);
3726 il_disable_interrupts(il);
3727 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3728
46bc8d4b 3729 pci_enable_msi(il->pci_dev);
4bc85c13 3730
e7392364 3731 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
4bc85c13 3732 if (err) {
9406f797 3733 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
4bc85c13
WYG
3734 goto out_disable_msi;
3735 }
3736
e2ebc833 3737 err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3738 if (err) {
9406f797 3739 IL_ERR("failed to create sysfs device attributes\n");
4bc85c13
WYG
3740 goto out_release_irq;
3741 }
3742
83007196 3743 il_set_rxon_channel(il, &il->bands[IEEE80211_BAND_2GHZ].channels[5]);
46bc8d4b 3744 il3945_setup_deferred_work(il);
d0c72347 3745 il3945_setup_handlers(il);
46bc8d4b 3746 il_power_initialize(il);
4bc85c13
WYG
3747
3748 /*********************************
3749 * 8. Setup and Register mac80211
3750 * *******************************/
3751
46bc8d4b 3752 il_enable_interrupts(il);
4bc85c13 3753
46bc8d4b 3754 err = il3945_setup_mac(il);
4bc85c13 3755 if (err)
e7392364 3756 goto out_remove_sysfs;
4bc85c13 3757
46bc8d4b 3758 err = il_dbgfs_register(il, DRV_NAME);
4bc85c13 3759 if (err)
e7392364
SG
3760 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
3761 err);
4bc85c13
WYG
3762
3763 /* Start monitoring the killswitch */
e7392364 3764 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
4bc85c13
WYG
3765
3766 return 0;
3767
e7392364 3768out_remove_sysfs:
46bc8d4b
SG
3769 destroy_workqueue(il->workqueue);
3770 il->workqueue = NULL;
e2ebc833 3771 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
e7392364 3772out_release_irq:
46bc8d4b 3773 free_irq(il->pci_dev->irq, il);
e7392364 3774out_disable_msi:
46bc8d4b
SG
3775 pci_disable_msi(il->pci_dev);
3776 il_free_geos(il);
3777 il_free_channel_map(il);
e7392364 3778out_unset_hw_params:
46bc8d4b 3779 il3945_unset_hw_params(il);
e7392364 3780out_eeprom_free:
46bc8d4b 3781 il_eeprom_free(il);
e7392364 3782out_iounmap:
46bc8d4b 3783 pci_iounmap(pdev, il->hw_base);
e7392364 3784out_pci_release_regions:
4bc85c13 3785 pci_release_regions(pdev);
e7392364 3786out_pci_disable_device:
4bc85c13
WYG
3787 pci_set_drvdata(pdev, NULL);
3788 pci_disable_device(pdev);
e7392364 3789out_ieee80211_free_hw:
46bc8d4b
SG
3790 il_free_traffic_mem(il);
3791 ieee80211_free_hw(il->hw);
e7392364 3792out:
4bc85c13
WYG
3793 return err;
3794}
3795
e7392364
SG
3796static void __devexit
3797il3945_pci_remove(struct pci_dev *pdev)
4bc85c13 3798{
46bc8d4b 3799 struct il_priv *il = pci_get_drvdata(pdev);
4bc85c13
WYG
3800 unsigned long flags;
3801
46bc8d4b 3802 if (!il)
4bc85c13
WYG
3803 return;
3804
58de00a4 3805 D_INFO("*** UNLOAD DRIVER ***\n");
4bc85c13 3806
46bc8d4b 3807 il_dbgfs_unregister(il);
4bc85c13 3808
a6766ccd 3809 set_bit(S_EXIT_PENDING, &il->status);
4bc85c13 3810
46bc8d4b 3811 il_leds_exit(il);
4bc85c13 3812
46bc8d4b
SG
3813 if (il->mac80211_registered) {
3814 ieee80211_unregister_hw(il->hw);
3815 il->mac80211_registered = 0;
4bc85c13 3816 } else {
46bc8d4b 3817 il3945_down(il);
4bc85c13
WYG
3818 }
3819
3820 /*
3821 * Make sure device is reset to low power before unloading driver.
e2ebc833
SG
3822 * This may be redundant with il_down(), but there are paths to
3823 * run il_down() without calling apm_ops.stop(), and there are
3824 * paths to avoid running il_down() at all before leaving driver.
4bc85c13
WYG
3825 * This (inexpensive) call *makes sure* device is reset.
3826 */
46bc8d4b 3827 il_apm_stop(il);
4bc85c13
WYG
3828
3829 /* make sure we flush any pending irq or
3830 * tasklet for the driver
3831 */
46bc8d4b
SG
3832 spin_lock_irqsave(&il->lock, flags);
3833 il_disable_interrupts(il);
3834 spin_unlock_irqrestore(&il->lock, flags);
4bc85c13 3835
46bc8d4b 3836 il3945_synchronize_irq(il);
4bc85c13 3837
e2ebc833 3838 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
4bc85c13 3839
46bc8d4b 3840 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
4bc85c13 3841
46bc8d4b 3842 il3945_dealloc_ucode_pci(il);
4bc85c13 3843
46bc8d4b
SG
3844 if (il->rxq.bd)
3845 il3945_rx_queue_free(il, &il->rxq);
3846 il3945_hw_txq_ctx_free(il);
4bc85c13 3847
46bc8d4b 3848 il3945_unset_hw_params(il);
4bc85c13
WYG
3849
3850 /*netif_stop_queue(dev); */
46bc8d4b 3851 flush_workqueue(il->workqueue);
4bc85c13 3852
e2ebc833 3853 /* ieee80211_unregister_hw calls il3945_mac_stop, which flushes
46bc8d4b 3854 * il->workqueue... so we can't take down the workqueue
4bc85c13 3855 * until now... */
46bc8d4b
SG
3856 destroy_workqueue(il->workqueue);
3857 il->workqueue = NULL;
3858 il_free_traffic_mem(il);
4bc85c13 3859
46bc8d4b 3860 free_irq(pdev->irq, il);
4bc85c13
WYG
3861 pci_disable_msi(pdev);
3862
46bc8d4b 3863 pci_iounmap(pdev, il->hw_base);
4bc85c13
WYG
3864 pci_release_regions(pdev);
3865 pci_disable_device(pdev);
3866 pci_set_drvdata(pdev, NULL);
3867
46bc8d4b
SG
3868 il_free_channel_map(il);
3869 il_free_geos(il);
3870 kfree(il->scan_cmd);
3871 if (il->beacon_skb)
3872 dev_kfree_skb(il->beacon_skb);
4bc85c13 3873
46bc8d4b 3874 ieee80211_free_hw(il->hw);
4bc85c13
WYG
3875}
3876
4bc85c13
WYG
3877/*****************************************************************************
3878 *
3879 * driver and module entry point
3880 *
3881 *****************************************************************************/
3882
e2ebc833 3883static struct pci_driver il3945_driver = {
4bc85c13 3884 .name = DRV_NAME,
e2ebc833
SG
3885 .id_table = il3945_hw_card_ids,
3886 .probe = il3945_pci_probe,
3887 .remove = __devexit_p(il3945_pci_remove),
3888 .driver.pm = IL_LEGACY_PM_OPS,
4bc85c13
WYG
3889};
3890
e7392364
SG
3891static int __init
3892il3945_init(void)
4bc85c13
WYG
3893{
3894
3895 int ret;
3896 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3897 pr_info(DRV_COPYRIGHT "\n");
3898
e2ebc833 3899 ret = il3945_rate_control_register();
4bc85c13
WYG
3900 if (ret) {
3901 pr_err("Unable to register rate control algorithm: %d\n", ret);
3902 return ret;
3903 }
3904
e2ebc833 3905 ret = pci_register_driver(&il3945_driver);
4bc85c13
WYG
3906 if (ret) {
3907 pr_err("Unable to initialize PCI module\n");
3908 goto error_register;
3909 }
3910
3911 return ret;
3912
3913error_register:
e2ebc833 3914 il3945_rate_control_unregister();
4bc85c13
WYG
3915 return ret;
3916}
3917
e7392364
SG
3918static void __exit
3919il3945_exit(void)
4bc85c13 3920{
e2ebc833
SG
3921 pci_unregister_driver(&il3945_driver);
3922 il3945_rate_control_unregister();
4bc85c13
WYG
3923}
3924
d3175167 3925MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
4bc85c13 3926
e2ebc833 3927module_param_named(antenna, il3945_mod_params.antenna, int, S_IRUGO);
4bc85c13 3928MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
e2ebc833 3929module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, S_IRUGO);
e7392364
SG
3930MODULE_PARM_DESC(swcrypto, "using software crypto (default 1 [software])");
3931module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, int,
3932 S_IRUGO);
0263aa45 3933MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
d3175167 3934#ifdef CONFIG_IWLEGACY_DEBUG
d2ddf621 3935module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
4bc85c13
WYG
3936MODULE_PARM_DESC(debug, "debug output mask");
3937#endif
e2ebc833 3938module_param_named(fw_restart, il3945_mod_params.restart_fw, int, S_IRUGO);
be663ab6 3939MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4bc85c13 3940
e2ebc833
SG
3941module_exit(il3945_exit);
3942module_init(il3945_init);