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[PATCH] bcm43xx: fix nrssi_threshold calculation.
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / wireless / bcm43xx / bcm43xx_main.c
CommitLineData
f222313a
JL		 1/*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
36#include <linux/version.h>
37#include <linux/firmware.h>
38#include <linux/wireless.h>
39#include <linux/workqueue.h>
40#include <linux/skbuff.h>
41#include <net/iw_handler.h>
42
43#include "bcm43xx.h"
44#include "bcm43xx_main.h"
45#include "bcm43xx_debugfs.h"
46#include "bcm43xx_radio.h"
47#include "bcm43xx_phy.h"
48#include "bcm43xx_dma.h"
49#include "bcm43xx_pio.h"
50#include "bcm43xx_power.h"
51#include "bcm43xx_wx.h"
6465ce1b 52#include "bcm43xx_ethtool.h"
f398f02d 53#include "bcm43xx_xmit.h"
f222313a
JL		 54
55
56MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
57MODULE_AUTHOR("Martin Langer");
58MODULE_AUTHOR("Stefano Brivio");
59MODULE_AUTHOR("Michael Buesch");
60MODULE_LICENSE("GPL");
61
62#ifdef CONFIG_BCM947XX
63extern char *nvram_get(char *name);
64#endif
65
77db31ea 66#if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
f222313a
JL		 67static int modparam_pio;
68module_param_named(pio, modparam_pio, int, 0444);
69MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
77db31ea
MB		 70#elif defined(CONFIG_BCM43XX_DMA)
71# define modparam_pio 0
72#elif defined(CONFIG_BCM43XX_PIO)
73# define modparam_pio 1
74#endif
f222313a
JL		 75
76static int modparam_bad_frames_preempt;
77module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
78MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
79
80static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
81module_param_named(short_retry, modparam_short_retry, int, 0444);
82MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
83
84static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
85module_param_named(long_retry, modparam_long_retry, int, 0444);
86MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
87
88static int modparam_locale = -1;
89module_param_named(locale, modparam_locale, int, 0444);
90MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
91
f222313a
JL		 92static int modparam_noleds;
93module_param_named(noleds, modparam_noleds, int, 0444);
94MODULE_PARM_DESC(noleds, "Turn off all LED activity");
95
96#ifdef CONFIG_BCM43XX_DEBUG
97static char modparam_fwpostfix[64];
98module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
99MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
100#else
101# define modparam_fwpostfix ""
102#endif /* CONFIG_BCM43XX_DEBUG*/
103
104
105/* If you want to debug with just a single device, enable this,
106 * where the string is the pci device ID (as given by the kernel's
107 * pci_name function) of the device to be used.
108 */
109//#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
110
111/* If you want to enable printing of each MMIO access, enable this. */
112//#define DEBUG_ENABLE_MMIO_PRINT
113
114/* If you want to enable printing of MMIO access within
115 * ucode/pcm upload, initvals write, enable this.
116 */
117//#define DEBUG_ENABLE_UCODE_MMIO_PRINT
118
119/* If you want to enable printing of PCI Config Space access, enable this */
120//#define DEBUG_ENABLE_PCILOG
121
122
489423c8
MB		 123/* Detailed list maintained at:
124 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
125 */
126 static struct pci_device_id bcm43xx_pci_tbl[] = {
f222313a
JL		 127 /* Broadcom 4303 802.11b */
128 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
489423c8 129 /* Broadcom 4307 802.11b */
f222313a 130 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
489423c8 131 /* Broadcom 4318 802.11b/g */
f222313a 132 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f222313a
JL		 133 /* Broadcom 4306 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
489423c8 135 /* Broadcom 4306 802.11a */
f222313a 136// { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f222313a
JL		 137 /* Broadcom 4309 802.11a/b/g */
138 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f222313a
JL		 139 /* Broadcom 43XG 802.11b/g */
140 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
489423c8
MB		 141#ifdef CONFIG_BCM947XX
142 /* SB bus on BCM947xx */
143 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144#endif
145 { 0 },
f222313a
JL		 146};
147MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
148
149static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
150{
151 u32 status;
152
153 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
154 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
155 val = swab32(val);
156
157 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
73733847 158 mmiowb();
f222313a
JL		 159 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
160}
161
162static inline
163void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
164 u16 routing, u16 offset)
165{
166 u32 control;
167
168 /* "offset" is the WORD offset. */
169
170 control = routing;
171 control <<= 16;
172 control |= offset;
173 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
174}
175
176u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
177 u16 routing, u16 offset)
178{
179 u32 ret;
180
181 if (routing == BCM43xx_SHM_SHARED) {
182 if (offset & 0x0003) {
183 /* Unaligned access */
184 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
185 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
186 ret <<= 16;
187 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
188 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
189
190 return ret;
191 }
192 offset >>= 2;
193 }
194 bcm43xx_shm_control_word(bcm, routing, offset);
195 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
196
197 return ret;
198}
199
200u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
201 u16 routing, u16 offset)
202{
203 u16 ret;
204
205 if (routing == BCM43xx_SHM_SHARED) {
206 if (offset & 0x0003) {
207 /* Unaligned access */
208 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
209 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
210
211 return ret;
212 }
213 offset >>= 2;
214 }
215 bcm43xx_shm_control_word(bcm, routing, offset);
216 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
217
218 return ret;
219}
220
221void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
222 u16 routing, u16 offset,
223 u32 value)
224{
225 if (routing == BCM43xx_SHM_SHARED) {
226 if (offset & 0x0003) {
227 /* Unaligned access */
228 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
73733847 229 mmiowb();
f222313a
JL		 230 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
231 (value >> 16) & 0xffff);
73733847 232 mmiowb();
f222313a 233 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
73733847 234 mmiowb();
f222313a
JL		 235 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
236 value & 0xffff);
237 return;
238 }
239 offset >>= 2;
240 }
241 bcm43xx_shm_control_word(bcm, routing, offset);
73733847 242 mmiowb();
f222313a
JL		 243 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
244}
245
246void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
247 u16 routing, u16 offset,
248 u16 value)
249{
250 if (routing == BCM43xx_SHM_SHARED) {
251 if (offset & 0x0003) {
252 /* Unaligned access */
253 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
73733847 254 mmiowb();
f222313a
JL		 255 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
256 value);
257 return;
258 }
259 offset >>= 2;
260 }
261 bcm43xx_shm_control_word(bcm, routing, offset);
73733847 262 mmiowb();
f222313a
JL		 263 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
264}
265
266void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
267{
268 /* We need to be careful. As we read the TSF from multiple
269 * registers, we should take care of register overflows.
270 * In theory, the whole tsf read process should be atomic.
271 * We try to be atomic here, by restaring the read process,
272 * if any of the high registers changed (overflew).
273 */
274 if (bcm->current_core->rev >= 3) {
275 u32 low, high, high2;
276
277 do {
278 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
279 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
280 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
281 } while (unlikely(high != high2));
282
283 *tsf = high;
284 *tsf <<= 32;
285 *tsf |= low;
286 } else {
287 u64 tmp;
288 u16 v0, v1, v2, v3;
289 u16 test1, test2, test3;
290
291 do {
292 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
293 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
294 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
295 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
296
297 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
298 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
299 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
300 } while (v3 != test3 || v2 != test2 || v1 != test1);
301
302 *tsf = v3;
303 *tsf <<= 48;
304 tmp = v2;
305 tmp <<= 32;
306 *tsf |= tmp;
307 tmp = v1;
308 tmp <<= 16;
309 *tsf |= tmp;
310 *tsf |= v0;
311 }
312}
313
314void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
315{
316 u32 status;
317
318 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
319 status |= BCM43xx_SBF_TIME_UPDATE;
320 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
73733847 321 mmiowb();
f222313a
JL		 322
323 /* Be careful with the in-progress timer.
324 * First zero out the low register, so we have a full
325 * register-overflow duration to complete the operation.
326 */
327 if (bcm->current_core->rev >= 3) {
328 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
329 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
330
f222313a 331 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
73733847 332 mmiowb();
f222313a 333 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
73733847 334 mmiowb();
f222313a
JL		 335 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
336 } else {
337 u16 v0 = (tsf & 0x000000000000FFFFULL);
338 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
339 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
340 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
341
f222313a 342 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
73733847 343 mmiowb();
f222313a 344 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
73733847 345 mmiowb();
f222313a 346 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
73733847 347 mmiowb();
f222313a 348 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
73733847 349 mmiowb();
f222313a
JL		 350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
351 }
352
353 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
354 status &= ~BCM43xx_SBF_TIME_UPDATE;
355 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
356}
357
f222313a
JL		 358static
359void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
360 u16 offset,
361 const u8 *mac)
362{
363 u16 data;
364
365 offset |= 0x0020;
366 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
367
368 data = mac[0];
369 data |= mac[1] << 8;
370 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
371 data = mac[2];
372 data |= mac[3] << 8;
373 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
374 data = mac[4];
375 data |= mac[5] << 8;
376 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
377}
378
489423c8
MB		 379static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
380 u16 offset)
f222313a
JL		 381{
382 const u8 zero_addr[ETH_ALEN] = { 0 };
383
384 bcm43xx_macfilter_set(bcm, offset, zero_addr);
385}
386
387static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
388{
389 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
390 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
391 u8 mac_bssid[ETH_ALEN * 2];
392 int i;
393
394 memcpy(mac_bssid, mac, ETH_ALEN);
395 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
396
397 /* Write our MAC address and BSSID to template ram */
398 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
399 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
400 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
401 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
402 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
403 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
404}
405
489423c8 406static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
f222313a
JL		 407{
408 /* slot_time is in usec. */
e9357c05 409 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
f222313a
JL		 410 return;
411 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
412 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
413}
414
489423c8 415static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
f222313a
JL		 416{
417 bcm43xx_set_slot_time(bcm, 9);
418}
419
489423c8 420static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
f222313a
JL		 421{
422 bcm43xx_set_slot_time(bcm, 20);
423}
424
425//FIXME: rename this func?
426static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
427{
428 bcm43xx_mac_suspend(bcm);
429 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
430
431 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
432 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
433 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
434 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
435 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
436 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
437
438 if (bcm->current_core->rev < 3) {
439 bcm43xx_write16(bcm, 0x0610, 0x8000);
440 bcm43xx_write16(bcm, 0x060E, 0x0000);
441 } else
442 bcm43xx_write32(bcm, 0x0188, 0x80000000);
443
444 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
445
e9357c05 446 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
f222313a
JL		 447 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
448 bcm43xx_short_slot_timing_enable(bcm);
449
450 bcm43xx_mac_enable(bcm);
451}
452
453//FIXME: rename this func?
454static void bcm43xx_associate(struct bcm43xx_private *bcm,
455 const u8 *mac)
456{
457 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
458
459 bcm43xx_mac_suspend(bcm);
460 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
461 bcm43xx_write_mac_bssid_templates(bcm);
462 bcm43xx_mac_enable(bcm);
463}
464
465/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
466 * Returns the _previously_ enabled IRQ mask.
467 */
468static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
469{
470 u32 old_mask;
471
472 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
473 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
474
475 return old_mask;
476}
477
478/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
479 * Returns the _previously_ enabled IRQ mask.
480 */
481static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
482{
483 u32 old_mask;
484
485 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
486 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
487
488 return old_mask;
489}
490
491/* Make sure we don't receive more data from the device. */
492static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm, u32 *oldstate)
493{
494 u32 old;
495 unsigned long flags;
496
efccb647 497 bcm43xx_lock_mmio(bcm, flags);
f222313a 498 if (bcm43xx_is_initializing(bcm) || bcm->shutting_down) {
efccb647 499 bcm43xx_unlock_mmio(bcm, flags);
f222313a
JL		 500 return -EBUSY;
501 }
502 old = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
503 tasklet_disable(&bcm->isr_tasklet);
efccb647 504 bcm43xx_unlock_mmio(bcm, flags);
f222313a
JL		 505 if (oldstate)
506 *oldstate = old;
507
508 return 0;
509}
510
511static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
512{
e9357c05
MB		 513 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
514 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a
JL		 515 u32 radio_id;
516 u16 manufact;
517 u16 version;
518 u8 revision;
519 s8 i;
520
521 if (bcm->chip_id == 0x4317) {
522 if (bcm->chip_rev == 0x00)
523 radio_id = 0x3205017F;
524 else if (bcm->chip_rev == 0x01)
525 radio_id = 0x4205017F;
526 else
527 radio_id = 0x5205017F;
528 } else {
529 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
530 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
531 radio_id <<= 16;
532 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
533 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
534 }
535
536 manufact = (radio_id & 0x00000FFF);
537 version = (radio_id & 0x0FFFF000) >> 12;
538 revision = (radio_id & 0xF0000000) >> 28;
539
489423c8 540 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
f222313a
JL		 541 radio_id, manufact, version, revision);
542
489423c8 543 switch (phy->type) {
f222313a
JL		 544 case BCM43xx_PHYTYPE_A:
545 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
546 goto err_unsupported_radio;
547 break;
548 case BCM43xx_PHYTYPE_B:
549 if ((version & 0xFFF0) != 0x2050)
550 goto err_unsupported_radio;
551 break;
552 case BCM43xx_PHYTYPE_G:
553 if (version != 0x2050)
554 goto err_unsupported_radio;
555 break;
556 }
557
489423c8
MB		 558 radio->manufact = manufact;
559 radio->version = version;
560 radio->revision = revision;
f222313a
JL		 561
562 /* Set default attenuation values. */
6ecb2690
MB		 563 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
564 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
565 radio->txctl1 = bcm43xx_default_txctl1(bcm);
e9357c05 566 if (phy->type == BCM43xx_PHYTYPE_A)
489423c8 567 radio->txpower_desired = bcm->sprom.maxpower_aphy;
393344f6 568 else
e9357c05 569 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
f222313a
JL		 570
571 /* Initialize the in-memory nrssi Lookup Table. */
572 for (i = 0; i < 64; i++)
489423c8 573 radio->nrssi_lt[i] = i;
f222313a
JL		 574
575 return 0;
576
577err_unsupported_radio:
578 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
579 return -ENODEV;
580}
581
582static const char * bcm43xx_locale_iso(u8 locale)
583{
584 /* ISO 3166-1 country codes.
585 * Note that there aren't ISO 3166-1 codes for
586 * all or locales. (Not all locales are countries)
587 */
588 switch (locale) {
589 case BCM43xx_LOCALE_WORLD:
590 case BCM43xx_LOCALE_ALL:
591 return "XX";
592 case BCM43xx_LOCALE_THAILAND:
593 return "TH";
594 case BCM43xx_LOCALE_ISRAEL:
595 return "IL";
596 case BCM43xx_LOCALE_JORDAN:
597 return "JO";
598 case BCM43xx_LOCALE_CHINA:
599 return "CN";
600 case BCM43xx_LOCALE_JAPAN:
601 case BCM43xx_LOCALE_JAPAN_HIGH:
602 return "JP";
603 case BCM43xx_LOCALE_USA_CANADA_ANZ:
604 case BCM43xx_LOCALE_USA_LOW:
605 return "US";
606 case BCM43xx_LOCALE_EUROPE:
607 return "EU";
608 case BCM43xx_LOCALE_NONE:
609 return " ";
610 }
611 assert(0);
612 return " ";
613}
614
615static const char * bcm43xx_locale_string(u8 locale)
616{
617 switch (locale) {
618 case BCM43xx_LOCALE_WORLD:
619 return "World";
620 case BCM43xx_LOCALE_THAILAND:
621 return "Thailand";
622 case BCM43xx_LOCALE_ISRAEL:
623 return "Israel";
624 case BCM43xx_LOCALE_JORDAN:
625 return "Jordan";
626 case BCM43xx_LOCALE_CHINA:
627 return "China";
628 case BCM43xx_LOCALE_JAPAN:
629 return "Japan";
630 case BCM43xx_LOCALE_USA_CANADA_ANZ:
631 return "USA/Canada/ANZ";
632 case BCM43xx_LOCALE_EUROPE:
633 return "Europe";
634 case BCM43xx_LOCALE_USA_LOW:
635 return "USAlow";
636 case BCM43xx_LOCALE_JAPAN_HIGH:
637 return "JapanHigh";
638 case BCM43xx_LOCALE_ALL:
639 return "All";
640 case BCM43xx_LOCALE_NONE:
641 return "None";
642 }
643 assert(0);
644 return "";
645}
646
647static inline u8 bcm43xx_crc8(u8 crc, u8 data)
648{
649 static const u8 t[] = {
650 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
651 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
652 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
653 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
654 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
655 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
656 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
657 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
658 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
659 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
660 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
661 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
662 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
663 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
664 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
665 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
666 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
667 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
668 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
669 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
670 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
671 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
672 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
673 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
674 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
675 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
676 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
677 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
678 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
679 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
680 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
681 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
682 };
683 return t[crc ^ data];
684}
685
ad3f086c 686static u8 bcm43xx_sprom_crc(const u16 *sprom)
f222313a
JL		 687{
688 int word;
689 u8 crc = 0xFF;
690
691 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
692 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
693 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
694 }
695 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
696 crc ^= 0xFF;
697
698 return crc;
699}
700
ea0922b0 701int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
f222313a
JL		 702{
703 int i;
ea0922b0
MB		 704 u8 crc, expected_crc;
705
706 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
707 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
708 /* CRC-8 check. */
709 crc = bcm43xx_sprom_crc(sprom);
710 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
711 if (crc != expected_crc) {
712 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
713 "(0x%02X, expected: 0x%02X)\n",
714 crc, expected_crc);
715 return -EINVAL;
716 }
717
718 return 0;
719}
720
721int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
722{
723 int i, err;
724 u8 crc, expected_crc;
725 u32 spromctl;
726
727 /* CRC-8 validation of the input data. */
728 crc = bcm43xx_sprom_crc(sprom);
729 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
730 if (crc != expected_crc) {
731 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
732 return -EINVAL;
733 }
734
735 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
736 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
737 if (err)
738 goto err_ctlreg;
739 spromctl |= 0x10; /* SPROM WRITE enable. */
740 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
741 if (err)
742 goto err_ctlreg;
743 /* We must burn lots of CPU cycles here, but that does not
744 * really matter as one does not write the SPROM every other minute...
745 */
746 printk(KERN_INFO PFX "[ 0%%");
747 mdelay(500);
748 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
749 if (i == 16)
750 printk("25%%");
751 else if (i == 32)
752 printk("50%%");
753 else if (i == 48)
754 printk("75%%");
755 else if (i % 2)
756 printk(".");
757 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
efccb647 758 mmiowb();
ea0922b0
MB		 759 mdelay(20);
760 }
761 spromctl &= ~0x10; /* SPROM WRITE enable. */
762 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
763 if (err)
764 goto err_ctlreg;
765 mdelay(500);
766 printk("100%% ]\n");
767 printk(KERN_INFO PFX "SPROM written.\n");
768 bcm43xx_controller_restart(bcm, "SPROM update");
769
770 return 0;
771err_ctlreg:
772 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
773 return -ENODEV;
774}
775
776static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
777{
f222313a
JL		 778 u16 value;
779 u16 *sprom;
f222313a
JL		 780#ifdef CONFIG_BCM947XX
781 char *c;
782#endif
783
784 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
785 GFP_KERNEL);
786 if (!sprom) {
ea0922b0 787 printk(KERN_ERR PFX "sprom_extract OOM\n");
f222313a
JL		 788 return -ENOMEM;
789 }
790#ifdef CONFIG_BCM947XX
791 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
792 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
793
794 if ((c = nvram_get("il0macaddr")) != NULL)
795 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
796
797 if ((c = nvram_get("et1macaddr")) != NULL)
798 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
799
800 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
801 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
802 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
803
804 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
805 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
806 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
807
808 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
809#else
ea0922b0 810 bcm43xx_sprom_read(bcm, sprom);
f222313a
JL		 811#endif
812
813 /* boardflags2 */
814 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
815 bcm->sprom.boardflags2 = value;
816
817 /* il0macaddr */
818 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
819 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
820 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
821 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
822 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
823 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
824
825 /* et0macaddr */
826 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
827 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
828 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
829 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
830 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
831 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
832
833 /* et1macaddr */
834 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
835 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
836 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
837 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
838 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
839 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
840
841 /* ethernet phy settings */
842 value = sprom[BCM43xx_SPROM_ETHPHY];
843 bcm->sprom.et0phyaddr = (value & 0x001F);
844 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
845 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
846 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
847
848 /* boardrev, antennas, locale */
849 value = sprom[BCM43xx_SPROM_BOARDREV];
850 bcm->sprom.boardrev = (value & 0x00FF);
851 bcm->sprom.locale = (value & 0x0F00) >> 8;
852 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
853 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
854 if (modparam_locale != -1) {
855 if (modparam_locale >= 0 && modparam_locale <= 11) {
856 bcm->sprom.locale = modparam_locale;
857 printk(KERN_WARNING PFX "Operating with modified "
858 "LocaleCode %u (%s)\n",
859 bcm->sprom.locale,
860 bcm43xx_locale_string(bcm->sprom.locale));
861 } else {
862 printk(KERN_WARNING PFX "Module parameter \"locale\" "
863 "invalid value. (0 - 11)\n");
864 }
865 }
866
867 /* pa0b* */
868 value = sprom[BCM43xx_SPROM_PA0B0];
869 bcm->sprom.pa0b0 = value;
870 value = sprom[BCM43xx_SPROM_PA0B1];
871 bcm->sprom.pa0b1 = value;
872 value = sprom[BCM43xx_SPROM_PA0B2];
873 bcm->sprom.pa0b2 = value;
874
875 /* wl0gpio* */
876 value = sprom[BCM43xx_SPROM_WL0GPIO0];
877 if (value == 0x0000)
878 value = 0xFFFF;
879 bcm->sprom.wl0gpio0 = value & 0x00FF;
880 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
881 value = sprom[BCM43xx_SPROM_WL0GPIO2];
882 if (value == 0x0000)
883 value = 0xFFFF;
884 bcm->sprom.wl0gpio2 = value & 0x00FF;
885 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
886
887 /* maxpower */
888 value = sprom[BCM43xx_SPROM_MAXPWR];
889 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
890 bcm->sprom.maxpower_bgphy = value & 0x00FF;
891
892 /* pa1b* */
893 value = sprom[BCM43xx_SPROM_PA1B0];
894 bcm->sprom.pa1b0 = value;
895 value = sprom[BCM43xx_SPROM_PA1B1];
896 bcm->sprom.pa1b1 = value;
897 value = sprom[BCM43xx_SPROM_PA1B2];
898 bcm->sprom.pa1b2 = value;
899
900 /* idle tssi target */
901 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
902 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
903 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
904
905 /* boardflags */
906 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
907 if (value == 0xFFFF)
908 value = 0x0000;
909 bcm->sprom.boardflags = value;
b3db5e55
MB		 910 /* boardflags workarounds */
911 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
912 bcm->chip_id == 0x4301 &&
913 bcm->board_revision == 0x74)
914 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
915 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
916 bcm->board_type == 0x4E &&
917 bcm->board_revision > 0x40)
918 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
f222313a
JL		 919
920 /* antenna gain */
921 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
922 if (value == 0x0000 || value == 0xFFFF)
923 value = 0x0202;
924 /* convert values to Q5.2 */
925 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
926 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
927
928 kfree(sprom);
929
930 return 0;
931}
932
f222313a
JL		 933static void bcm43xx_geo_init(struct bcm43xx_private *bcm)
934{
935 struct ieee80211_geo geo;
936 struct ieee80211_channel *chan;
937 int have_a = 0, have_bg = 0;
e9357c05 938 int i;
9e4a375b 939 u8 channel;
f222313a
JL		 940 struct bcm43xx_phyinfo *phy;
941 const char *iso_country;
942
943 memset(&geo, 0, sizeof(geo));
e9357c05
MB		 944 for (i = 0; i < bcm->nr_80211_available; i++) {
945 phy = &(bcm->core_80211_ext[i].phy);
f222313a
JL		 946 switch (phy->type) {
947 case BCM43xx_PHYTYPE_B:
948 case BCM43xx_PHYTYPE_G:
949 have_bg = 1;
950 break;
951 case BCM43xx_PHYTYPE_A:
952 have_a = 1;
953 break;
954 default:
955 assert(0);
956 }
957 }
958 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
959
960 if (have_a) {
961 for (i = 0, channel = 0; channel < 201; channel++) {
f222313a 962 chan = &geo.a[i++];
10d8dd88 963 chan->freq = bcm43xx_channel_to_freq_a(channel);
f222313a 964 chan->channel = channel;
f222313a
JL		 965 }
966 geo.a_channels = i;
967 }
968 if (have_bg) {
969 for (i = 0, channel = 1; channel < 15; channel++) {
f222313a 970 chan = &geo.bg[i++];
10d8dd88 971 chan->freq = bcm43xx_channel_to_freq_bg(channel);
f222313a 972 chan->channel = channel;
f222313a
JL		 973 }
974 geo.bg_channels = i;
975 }
976 memcpy(geo.name, iso_country, 2);
977 if (0 /*TODO: Outdoor use only */)
978 geo.name[2] = 'O';
979 else if (0 /*TODO: Indoor use only */)
980 geo.name[2] = 'I';
981 else
982 geo.name[2] = ' ';
983 geo.name[3] = '\0';
984
985 ieee80211_set_geo(bcm->ieee, &geo);
986}
987
988/* DummyTransmission function, as documented on
989 * http://bcm-specs.sipsolutions.net/DummyTransmission
990 */
991void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
992{
e9357c05
MB		 993 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
994 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
f222313a
JL		 995 unsigned int i, max_loop;
996 u16 value = 0;
997 u32 buffer[5] = {
998 0x00000000,
999 0x0000D400,
1000 0x00000000,
1001 0x00000001,
1002 0x00000000,
1003 };
1004
489423c8 1005 switch (phy->type) {
f222313a
JL		 1006 case BCM43xx_PHYTYPE_A:
1007 max_loop = 0x1E;
1008 buffer[0] = 0xCC010200;
1009 break;
1010 case BCM43xx_PHYTYPE_B:
1011 case BCM43xx_PHYTYPE_G:
1012 max_loop = 0xFA;
1013 buffer[0] = 0x6E840B00;
1014 break;
1015 default:
1016 assert(0);
1017 return;
1018 }
1019
1020 for (i = 0; i < 5; i++)
1021 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1022
1023 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1024
1025 bcm43xx_write16(bcm, 0x0568, 0x0000);
1026 bcm43xx_write16(bcm, 0x07C0, 0x0000);
489423c8 1027 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
f222313a
JL		 1028 bcm43xx_write16(bcm, 0x0508, 0x0000);
1029 bcm43xx_write16(bcm, 0x050A, 0x0000);
1030 bcm43xx_write16(bcm, 0x054C, 0x0000);
1031 bcm43xx_write16(bcm, 0x056A, 0x0014);
1032 bcm43xx_write16(bcm, 0x0568, 0x0826);
1033 bcm43xx_write16(bcm, 0x0500, 0x0000);
1034 bcm43xx_write16(bcm, 0x0502, 0x0030);
1035
73733847
MB		 1036 if (radio->version == 0x2050 && radio->revision <= 0x5)
1037 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
f222313a
JL		 1038 for (i = 0x00; i < max_loop; i++) {
1039 value = bcm43xx_read16(bcm, 0x050E);
73733847 1040 if (value & 0x0080)
f222313a
JL		 1041 break;
1042 udelay(10);
1043 }
1044 for (i = 0x00; i < 0x0A; i++) {
1045 value = bcm43xx_read16(bcm, 0x050E);
73733847 1046 if (value & 0x0400)
f222313a
JL		 1047 break;
1048 udelay(10);
1049 }
1050 for (i = 0x00; i < 0x0A; i++) {
1051 value = bcm43xx_read16(bcm, 0x0690);
73733847 1052 if (!(value & 0x0100))
f222313a
JL		 1053 break;
1054 udelay(10);
1055 }
73733847
MB		 1056 if (radio->version == 0x2050 && radio->revision <= 0x5)
1057 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
f222313a
JL		 1058}
1059
1060static void key_write(struct bcm43xx_private *bcm,
1061 u8 index, u8 algorithm, const u16 *key)
1062{
1063 unsigned int i, basic_wep = 0;
1064 u32 offset;
1065 u16 value;
1066
1067 /* Write associated key information */
1068 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1069 ((index << 4) | (algorithm & 0x0F)));
1070
1071 /* The first 4 WEP keys need extra love */
1072 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1073 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1074 basic_wep = 1;
1075
1076 /* Write key payload, 8 little endian words */
1077 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1078 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1079 value = cpu_to_le16(key[i]);
1080 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1081 offset + (i * 2), value);
1082
1083 if (!basic_wep)
1084 continue;
1085
1086 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1087 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1088 value);
1089 }
1090}
1091
1092static void keymac_write(struct bcm43xx_private *bcm,
1093 u8 index, const u32 *addr)
1094{
1095 /* for keys 0-3 there is no associated mac address */
1096 if (index < 4)
1097 return;
1098
1099 index -= 4;
1100 if (bcm->current_core->rev >= 5) {
1101 bcm43xx_shm_write32(bcm,
1102 BCM43xx_SHM_HWMAC,
1103 index * 2,
1104 cpu_to_be32(*addr));
1105 bcm43xx_shm_write16(bcm,
1106 BCM43xx_SHM_HWMAC,
1107 (index * 2) + 1,
1108 cpu_to_be16(*((u16 *)(addr + 1))));
1109 } else {
1110 if (index < 8) {
1111 TODO(); /* Put them in the macaddress filter */
1112 } else {
1113 TODO();
1114 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1115 Keep in mind to update the count of keymacs in 0x003E as well! */
1116 }
1117 }
1118}
1119
1120static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1121 u8 index, u8 algorithm,
1122 const u8 *_key, int key_len,
1123 const u8 *mac_addr)
1124{
1125 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1126
1127 if (index >= ARRAY_SIZE(bcm->key))
1128 return -EINVAL;
1129 if (key_len > ARRAY_SIZE(key))
1130 return -EINVAL;
1131 if (algorithm < 1 || algorithm > 5)
1132 return -EINVAL;
1133
1134 memcpy(key, _key, key_len);
1135 key_write(bcm, index, algorithm, (const u16 *)key);
1136 keymac_write(bcm, index, (const u32 *)mac_addr);
1137
1138 bcm->key[index].algorithm = algorithm;
1139
1140 return 0;
1141}
1142
1143static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1144{
1145 static const u32 zero_mac[2] = { 0 };
1146 unsigned int i,j, nr_keys = 54;
1147 u16 offset;
1148
1149 if (bcm->current_core->rev < 5)
1150 nr_keys = 16;
1151 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1152
1153 for (i = 0; i < nr_keys; i++) {
1154 bcm->key[i].enabled = 0;
1155 /* returns for i < 4 immediately */
1156 keymac_write(bcm, i, zero_mac);
1157 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1158 0x100 + (i * 2), 0x0000);
1159 for (j = 0; j < 8; j++) {
1160 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1161 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1162 offset, 0x0000);
1163 }
1164 }
1165 dprintk(KERN_INFO PFX "Keys cleared\n");
1166}
1167
f222313a
JL		 1168/* Lowlevel core-switch function. This is only to be used in
1169 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1170 */
1171static int _switch_core(struct bcm43xx_private *bcm, int core)
1172{
1173 int err;
1174 int attempts = 0;
489423c8 1175 u32 current_core;
f222313a
JL		 1176
1177 assert(core >= 0);
489423c8
MB		 1178 while (1) {
1179 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
f222313a 1180 (core * 0x1000) + 0x18000000);
489423c8
MB		 1181 if (unlikely(err))
1182 goto error;
1183 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1184 &current_core);
1185 if (unlikely(err))
1186 goto error;
1187 current_core = (current_core - 0x18000000) / 0x1000;
1188 if (current_core == core)
1189 break;
1190
1191 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1192 goto error;
1193 udelay(10);
1194 }
f222313a 1195#ifdef CONFIG_BCM947XX
489423c8
MB		 1196 if (bcm->pci_dev->bus->number == 0)
1197 bcm->current_core_offset = 0x1000 * core;
1198 else
1199 bcm->current_core_offset = 0;
f222313a 1200#endif
f222313a 1201
489423c8
MB		 1202 return 0;
1203error:
1204 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1205 return -ENODEV;
f222313a
JL		 1206}
1207
1208int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1209{
1210 int err;
1211
489423c8 1212 if (unlikely(!new_core))
f222313a 1213 return 0;
e9357c05 1214 if (!new_core->available)
f222313a
JL		 1215 return -ENODEV;
1216 if (bcm->current_core == new_core)
1217 return 0;
1218 err = _switch_core(bcm, new_core->index);
e9357c05
MB		 1219 if (unlikely(err))
1220 goto out;
f222313a 1221
e9357c05
MB		 1222 bcm->current_core = new_core;
1223 bcm->current_80211_core_idx = -1;
1224 if (new_core->id == BCM43xx_COREID_80211)
1225 bcm->current_80211_core_idx = (int)(new_core - &(bcm->core_80211[0]));
1226
1227out:
f222313a
JL		 1228 return err;
1229}
1230
489423c8 1231static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
f222313a
JL		 1232{
1233 u32 value;
1234
1235 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1236 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1237 | BCM43xx_SBTMSTATELOW_REJECT;
1238
1239 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1240}
1241
1242/* disable current core */
1243static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1244{
1245 u32 sbtmstatelow;
1246 u32 sbtmstatehigh;
1247 int i;
1248
1249 /* fetch sbtmstatelow from core information registers */
1250 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1251
1252 /* core is already in reset */
1253 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1254 goto out;
1255
1256 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1257 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1258 BCM43xx_SBTMSTATELOW_REJECT;
1259 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1260
1261 for (i = 0; i < 1000; i++) {
1262 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1263 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1264 i = -1;
1265 break;
1266 }
1267 udelay(10);
1268 }
1269 if (i != -1) {
1270 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1271 return -EBUSY;
1272 }
1273
1274 for (i = 0; i < 1000; i++) {
1275 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1276 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1277 i = -1;
1278 break;
1279 }
1280 udelay(10);
1281 }
1282 if (i != -1) {
1283 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1284 return -EBUSY;
1285 }
1286
1287 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1288 BCM43xx_SBTMSTATELOW_REJECT |
1289 BCM43xx_SBTMSTATELOW_RESET |
1290 BCM43xx_SBTMSTATELOW_CLOCK |
1291 core_flags;
1292 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1293 udelay(10);
1294 }
1295
1296 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1297 BCM43xx_SBTMSTATELOW_REJECT |
1298 core_flags;
1299 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1300
1301out:
e9357c05
MB		 1302 bcm->current_core->enabled = 0;
1303
f222313a
JL		 1304 return 0;
1305}
1306
1307/* enable (reset) current core */
1308static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1309{
1310 u32 sbtmstatelow;
1311 u32 sbtmstatehigh;
1312 u32 sbimstate;
1313 int err;
1314
1315 err = bcm43xx_core_disable(bcm, core_flags);
1316 if (err)
1317 goto out;
1318
1319 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1320 BCM43xx_SBTMSTATELOW_RESET |
1321 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1322 core_flags;
1323 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1324 udelay(1);
1325
1326 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1327 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1328 sbtmstatehigh = 0x00000000;
1329 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1330 }
1331
1332 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1333 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1334 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1335 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1336 }
1337
1338 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1339 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1340 core_flags;
1341 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1342 udelay(1);
1343
1344 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1345 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1346 udelay(1);
1347
e9357c05 1348 bcm->current_core->enabled = 1;
f222313a
JL		 1349 assert(err == 0);
1350out:
1351 return err;
1352}
1353
1354/* http://bcm-specs.sipsolutions.net/80211CoreReset */
1355void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1356{
1357 u32 flags = 0x00040000;
1358
77db31ea
MB		 1359 if ((bcm43xx_core_enabled(bcm)) &&
1360 !bcm43xx_using_pio(bcm)) {
f222313a
JL		 1361//FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1362#ifndef CONFIG_BCM947XX
1363 /* reset all used DMA controllers. */
1364 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1365 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1366 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1367 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1368 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1369 if (bcm->current_core->rev < 5)
1370 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1371#endif
1372 }
1373 if (bcm->shutting_down) {
1374 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1375 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1376 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1377 } else {
1378 if (connect_phy)
1379 flags |= 0x20000000;
1380 bcm43xx_phy_connect(bcm, connect_phy);
1381 bcm43xx_core_enable(bcm, flags);
1382 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1383 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1384 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1385 | BCM43xx_SBF_400);
1386 }
1387}
1388
1389static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1390{
1391 bcm43xx_radio_turn_off(bcm);
1392 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1393 bcm43xx_core_disable(bcm, 0);
1394}
1395
1396/* Mark the current 80211 core inactive.
1397 * "active_80211_core" is the other 80211 core, which is used.
1398 */
1399static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm,
1400 struct bcm43xx_coreinfo *active_80211_core)
1401{
1402 u32 sbtmstatelow;
1403 struct bcm43xx_coreinfo *old_core;
1404 int err = 0;
1405
1406 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1407 bcm43xx_radio_turn_off(bcm);
1408 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1409 sbtmstatelow &= ~0x200a0000;
1410 sbtmstatelow |= 0xa0000;
1411 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1412 udelay(1);
1413 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1414 sbtmstatelow &= ~0xa0000;
1415 sbtmstatelow |= 0x80000;
1416 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1417 udelay(1);
1418
e9357c05 1419 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
f222313a
JL		 1420 old_core = bcm->current_core;
1421 err = bcm43xx_switch_core(bcm, active_80211_core);
1422 if (err)
1423 goto out;
1424 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1425 sbtmstatelow &= ~0x20000000;
1426 sbtmstatelow |= 0x20000000;
1427 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1428 err = bcm43xx_switch_core(bcm, old_core);
1429 }
1430
1431out:
1432 return err;
1433}
1434
489423c8 1435static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
f222313a
JL		 1436{
1437 u32 v0, v1;
1438 u16 tmp;
1439 struct bcm43xx_xmitstatus stat;
1440
f222313a
JL		 1441 while (1) {
1442 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1443 if (!v0)
1444 break;
1445 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1446
1447 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1448 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1449 stat.flags = tmp & 0xFF;
1450 stat.cnt1 = (tmp & 0x0F00) >> 8;
1451 stat.cnt2 = (tmp & 0xF000) >> 12;
1452 stat.seq = (u16)(v1 & 0xFFFF);
1453 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1454
1455 bcm43xx_debugfs_log_txstat(bcm, &stat);
1456
1457 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1458 continue;
1459 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1460 //TODO: packet was not acked (was lost)
1461 }
1462 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1463
77db31ea 1464 if (bcm43xx_using_pio(bcm))
f222313a
JL		 1465 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1466 else
1467 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1468 }
1469}
1470
489423c8 1471static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
f222313a
JL		 1472{
1473 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1474 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1475 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1476 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1477 assert(bcm->noisecalc.core_at_start == bcm->current_core);
e9357c05 1478 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
f222313a
JL		 1479}
1480
1481static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1482{
1483 /* Top half of Link Quality calculation. */
1484
1485 if (bcm->noisecalc.calculation_running)
1486 return;
1487 bcm->noisecalc.core_at_start = bcm->current_core;
e9357c05 1488 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
f222313a
JL		 1489 bcm->noisecalc.calculation_running = 1;
1490 bcm->noisecalc.nr_samples = 0;
1491
1492 bcm43xx_generate_noise_sample(bcm);
1493}
1494
489423c8 1495static void handle_irq_noise(struct bcm43xx_private *bcm)
f222313a 1496{
e9357c05 1497 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
f222313a
JL		 1498 u16 tmp;
1499 u8 noise[4];
1500 u8 i, j;
1501 s32 average;
1502
1503 /* Bottom half of Link Quality calculation. */
1504
1505 assert(bcm->noisecalc.calculation_running);
1506 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1507 bcm->noisecalc.channel_at_start != radio->channel)
1508 goto drop_calculation;
1509 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1510 noise[0] = (tmp & 0x00FF);
1511 noise[1] = (tmp & 0xFF00) >> 8;
1512 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1513 noise[2] = (tmp & 0x00FF);
1514 noise[3] = (tmp & 0xFF00) >> 8;
1515 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1516 noise[2] == 0x7F || noise[3] == 0x7F)
1517 goto generate_new;
1518
1519 /* Get the noise samples. */
1520 assert(bcm->noisecalc.nr_samples <= 8);
1521 i = bcm->noisecalc.nr_samples;
1522 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1523 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1524 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1525 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1526 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1527 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1528 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1529 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1530 bcm->noisecalc.nr_samples++;
1531 if (bcm->noisecalc.nr_samples == 8) {
1532 /* Calculate the Link Quality by the noise samples. */
1533 average = 0;
1534 for (i = 0; i < 8; i++) {
1535 for (j = 0; j < 4; j++)
1536 average += bcm->noisecalc.samples[i][j];
1537 }
1538 average /= (8 * 4);
1539 average *= 125;
1540 average += 64;
1541 average /= 128;
1542 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1543 tmp = (tmp / 128) & 0x1F;
1544 if (tmp >= 8)
1545 average += 2;
1546 else
1547 average -= 25;
1548 if (tmp == 8)
1549 average -= 72;
1550 else
1551 average -= 48;
1552
1553 if (average > -65)
1554 bcm->stats.link_quality = 0;
1555 else if (average > -75)
1556 bcm->stats.link_quality = 1;
1557 else if (average > -85)
1558 bcm->stats.link_quality = 2;
1559 else
1560 bcm->stats.link_quality = 3;
1561// dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
1562drop_calculation:
1563 bcm->noisecalc.calculation_running = 0;
1564 return;
1565 }
1566generate_new:
1567 bcm43xx_generate_noise_sample(bcm);
1568}
1569
489423c8 1570static void handle_irq_ps(struct bcm43xx_private *bcm)
f222313a
JL		 1571{
1572 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1573 ///TODO: PS TBTT
1574 } else {
1575 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1576 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1577 }
1578 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1579 bcm->reg124_set_0x4 = 1;
1580 //FIXME else set to false?
1581}
1582
489423c8 1583static void handle_irq_reg124(struct bcm43xx_private *bcm)
f222313a
JL		 1584{
1585 if (!bcm->reg124_set_0x4)
1586 return;
1587 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1588 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1589 | 0x4);
1590 //FIXME: reset reg124_set_0x4 to false?
1591}
1592
489423c8 1593static void handle_irq_pmq(struct bcm43xx_private *bcm)
f222313a
JL		 1594{
1595 u32 tmp;
1596
1597 //TODO: AP mode.
1598
1599 while (1) {
1600 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1601 if (!(tmp & 0x00000008))
1602 break;
1603 }
1604 /* 16bit write is odd, but correct. */
1605 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1606}
1607
1608static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1609 u16 ram_offset, u16 shm_size_offset)
1610{
1611 u32 value;
1612 u16 size = 0;
1613
1614 /* Timestamp. */
1615 //FIXME: assumption: The chip sets the timestamp
1616 value = 0;
1617 bcm43xx_ram_write(bcm, ram_offset++, value);
1618 bcm43xx_ram_write(bcm, ram_offset++, value);
1619 size += 8;
1620
1621 /* Beacon Interval / Capability Information */
1622 value = 0x0000;//FIXME: Which interval?
1623 value |= (1 << 0) << 16; /* ESS */
1624 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1625 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1626 if (!bcm->ieee->open_wep)
1627 value |= (1 << 4) << 16; /* Privacy */
1628 bcm43xx_ram_write(bcm, ram_offset++, value);
1629 size += 4;
1630
1631 /* SSID */
1632 //TODO
1633
1634 /* FH Parameter Set */
1635 //TODO
1636
1637 /* DS Parameter Set */
1638 //TODO
1639
1640 /* CF Parameter Set */
1641 //TODO
1642
1643 /* TIM */
1644 //TODO
1645
1646 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1647}
1648
489423c8 1649static void handle_irq_beacon(struct bcm43xx_private *bcm)
f222313a
JL		 1650{
1651 u32 status;
1652
1653 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1654 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1655
1656 if ((status & 0x1) && (status & 0x2)) {
1657 /* ACK beacon IRQ. */
1658 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1659 BCM43xx_IRQ_BEACON);
1660 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1661 return;
1662 }
1663 if (!(status & 0x1)) {
1664 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1665 status |= 0x1;
1666 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1667 }
1668 if (!(status & 0x2)) {
1669 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1670 status |= 0x2;
1671 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1672 }
1673}
1674
f222313a
JL		 1675/* Interrupt handler bottom-half */
1676static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1677{
1678 u32 reason;
1679 u32 dma_reason[4];
1680 int activity = 0;
1681 unsigned long flags;
1682
1683#ifdef CONFIG_BCM43XX_DEBUG
1684 u32 _handled = 0x00000000;
1685# define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1686#else
1687# define bcmirq_handled(irq) do { /* nothing */ } while (0)
1688#endif /* CONFIG_BCM43XX_DEBUG*/
1689
efccb647 1690 bcm43xx_lock_mmio(bcm, flags);
f222313a
JL		 1691 reason = bcm->irq_reason;
1692 dma_reason[0] = bcm->dma_reason[0];
1693 dma_reason[1] = bcm->dma_reason[1];
1694 dma_reason[2] = bcm->dma_reason[2];
1695 dma_reason[3] = bcm->dma_reason[3];
1696
1697 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1698 /* TX error. We get this when Template Ram is written in wrong endianess
1699 * in dummy_tx(). We also get this if something is wrong with the TX header
1700 * on DMA or PIO queues.
1701 * Maybe we get this in other error conditions, too.
1702 */
73733847 1703 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
f222313a
JL		 1704 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1705 }
73733847
MB		 1706 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |
1707 (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |
1708 (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |
1709 (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {
1710 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1711 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1712 dma_reason[0], dma_reason[1],
1713 dma_reason[2], dma_reason[3]);
1714 bcm43xx_controller_restart(bcm, "DMA error");
1715 bcm43xx_unlock_mmio(bcm, flags);
1716 return;
1717 }
1718 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |
1719 (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |
1720 (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |
1721 (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {
1722 printkl(KERN_ERR PFX "DMA error: "
1723 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1724 dma_reason[0], dma_reason[1],
1725 dma_reason[2], dma_reason[3]);
1726 }
f222313a
JL		 1727
1728 if (reason & BCM43xx_IRQ_PS) {
1729 handle_irq_ps(bcm);
1730 bcmirq_handled(BCM43xx_IRQ_PS);
1731 }
1732
1733 if (reason & BCM43xx_IRQ_REG124) {
1734 handle_irq_reg124(bcm);
1735 bcmirq_handled(BCM43xx_IRQ_REG124);
1736 }
1737
1738 if (reason & BCM43xx_IRQ_BEACON) {
1739 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1740 handle_irq_beacon(bcm);
1741 bcmirq_handled(BCM43xx_IRQ_BEACON);
1742 }
1743
1744 if (reason & BCM43xx_IRQ_PMQ) {
1745 handle_irq_pmq(bcm);
1746 bcmirq_handled(BCM43xx_IRQ_PMQ);
1747 }
1748
1749 if (reason & BCM43xx_IRQ_SCAN) {
1750 /*TODO*/
1751 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1752 }
1753
1754 if (reason & BCM43xx_IRQ_NOISE) {
1755 handle_irq_noise(bcm);
1756 bcmirq_handled(BCM43xx_IRQ_NOISE);
1757 }
1758
1759 /* Check the DMA reason registers for received data. */
1760 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1761 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1762 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
77db31ea 1763 if (bcm43xx_using_pio(bcm))
e9357c05 1764 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
f222313a 1765 else
e9357c05 1766 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
dcfd720b 1767 /* We intentionally don't set "activity" to 1, here. */
f222313a
JL		 1768 }
1769 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
e1b1b581 1770 if (bcm43xx_using_pio(bcm))
e9357c05 1771 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
e1b1b581 1772 else
e9357c05 1773 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);
e1b1b581 1774 activity = 1;
f222313a
JL		 1775 }
1776 bcmirq_handled(BCM43xx_IRQ_RX);
1777
1778 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
e1b1b581
MB		 1779 handle_irq_transmit_status(bcm);
1780 activity = 1;
f222313a
JL		 1781 //TODO: In AP mode, this also causes sending of powersave responses.
1782 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1783 }
1784
f222313a
JL		 1785 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1786 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1787#ifdef CONFIG_BCM43XX_DEBUG
1788 if (unlikely(reason & ~_handled)) {
1789 printkl(KERN_WARNING PFX
1790 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1791 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1792 reason, (reason & ~_handled),
1793 dma_reason[0], dma_reason[1],
1794 dma_reason[2], dma_reason[3]);
1795 }
1796#endif
1797#undef bcmirq_handled
1798
1799 if (!modparam_noleds)
1800 bcm43xx_leds_update(bcm, activity);
1801 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
efccb647 1802 bcm43xx_unlock_mmio(bcm, flags);
f222313a
JL		 1803}
1804
0ac59dae
MB		 1805static void pio_irq_workaround(struct bcm43xx_private *bcm,
1806 u16 base, int queueidx)
f222313a 1807{
0ac59dae
MB		 1808 u16 rxctl;
1809
1810 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1811 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1812 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1813 else
1814 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1815}
f222313a 1816
0ac59dae
MB		 1817static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1818{
77db31ea 1819 if (bcm43xx_using_pio(bcm) &&
f222313a
JL		 1820 (bcm->current_core->rev < 3) &&
1821 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1822 /* Apply a PIO specific workaround to the dma_reasons */
0ac59dae
MB		 1823 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1824 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1825 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1826 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
f222313a
JL		 1827 }
1828
0ac59dae 1829 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
f222313a
JL		 1830
1831 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1832 bcm->dma_reason[0]);
1833 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1834 bcm->dma_reason[1]);
1835 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1836 bcm->dma_reason[2]);
1837 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1838 bcm->dma_reason[3]);
1839}
1840
1841/* Interrupt handler top-half */
1842static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1843{
efccb647 1844 irqreturn_t ret = IRQ_HANDLED;
f222313a 1845 struct bcm43xx_private *bcm = dev_id;
0ac59dae 1846 u32 reason;
f222313a
JL		 1847
1848 if (!bcm)
1849 return IRQ_NONE;
1850
efccb647 1851 spin_lock(&bcm->_lock);
f222313a
JL		 1852
1853 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1854 if (reason == 0xffffffff) {
1855 /* irq not for us (shared irq) */
efccb647
MB		 1856 ret = IRQ_NONE;
1857 goto out;
f222313a 1858 }
0ac59dae
MB		 1859 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1860 if (!reason)
efccb647 1861 goto out;
f222313a 1862
0ac59dae
MB		 1863 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1864 & 0x0001dc00;
1865 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1866 & 0x0000dc00;
1867 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1868 & 0x0000dc00;
1869 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1870 & 0x0001dc00;
1871
1872 bcm43xx_interrupt_ack(bcm, reason);
f222313a 1873
bf7b8760
MB		 1874 /* Only accept IRQs, if we are initialized properly.
1875 * This avoids an RX race while initializing.
1876 * We should probably not enable IRQs before we are initialized
1877 * completely, but some careful work is needed to fix this. I think it
1878 * is best to stay with this cheap workaround for now... .
1879 */
1880 if (likely(bcm->initialized)) {
1881 /* disable all IRQs. They are enabled again in the bottom half. */
1882 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1883 /* save the reason code and call our bottom half. */
1884 bcm->irq_reason = reason;
1885 tasklet_schedule(&bcm->isr_tasklet);
1886 }
f222313a 1887
efccb647
MB		 1888out:
1889 mmiowb();
1890 spin_unlock(&bcm->_lock);
f222313a 1891
efccb647 1892 return ret;
f222313a
JL		 1893}
1894
a4a600d3 1895static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
f222313a 1896{
a4a600d3 1897 if (bcm->firmware_norelease && !force)
f222313a
JL		 1898 return; /* Suspending or controller reset. */
1899 release_firmware(bcm->ucode);
1900 bcm->ucode = NULL;
1901 release_firmware(bcm->pcm);
1902 bcm->pcm = NULL;
1903 release_firmware(bcm->initvals0);
1904 bcm->initvals0 = NULL;
1905 release_firmware(bcm->initvals1);
1906 bcm->initvals1 = NULL;
1907}
1908
1909static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1910{
e9357c05 1911 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a
JL		 1912 u8 rev = bcm->current_core->rev;
1913 int err = 0;
1914 int nr;
1915 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1916
1917 if (!bcm->ucode) {
1918 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1919 (rev >= 5 ? 5 : rev),
1920 modparam_fwpostfix);
1921 err = request_firmware(&bcm->ucode, buf, &bcm->pci_dev->dev);
1922 if (err) {
1923 printk(KERN_ERR PFX
1924 "Error: Microcode \"%s\" not available or load failed.\n",
1925 buf);
1926 goto error;
1927 }
1928 }
1929
1930 if (!bcm->pcm) {
1931 snprintf(buf, ARRAY_SIZE(buf),
1932 "bcm43xx_pcm%d%s.fw",
1933 (rev < 5 ? 4 : 5),
1934 modparam_fwpostfix);
1935 err = request_firmware(&bcm->pcm, buf, &bcm->pci_dev->dev);
1936 if (err) {
1937 printk(KERN_ERR PFX
1938 "Error: PCM \"%s\" not available or load failed.\n",
1939 buf);
1940 goto error;
1941 }
1942 }
1943
1944 if (!bcm->initvals0) {
1945 if (rev == 2 || rev == 4) {
1946 switch (phy->type) {
1947 case BCM43xx_PHYTYPE_A:
1948 nr = 3;
1949 break;
1950 case BCM43xx_PHYTYPE_B:
1951 case BCM43xx_PHYTYPE_G:
1952 nr = 1;
1953 break;
1954 default:
1955 goto err_noinitval;
1956 }
1957
1958 } else if (rev >= 5) {
1959 switch (phy->type) {
1960 case BCM43xx_PHYTYPE_A:
1961 nr = 7;
1962 break;
1963 case BCM43xx_PHYTYPE_B:
1964 case BCM43xx_PHYTYPE_G:
1965 nr = 5;
1966 break;
1967 default:
1968 goto err_noinitval;
1969 }
1970 } else
1971 goto err_noinitval;
1972 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1973 nr, modparam_fwpostfix);
1974
1975 err = request_firmware(&bcm->initvals0, buf, &bcm->pci_dev->dev);
1976 if (err) {
1977 printk(KERN_ERR PFX
1978 "Error: InitVals \"%s\" not available or load failed.\n",
1979 buf);
1980 goto error;
1981 }
1982 if (bcm->initvals0->size % sizeof(struct bcm43xx_initval)) {
1983 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1984 goto error;
1985 }
1986 }
1987
1988 if (!bcm->initvals1) {
1989 if (rev >= 5) {
1990 u32 sbtmstatehigh;
1991
1992 switch (phy->type) {
1993 case BCM43xx_PHYTYPE_A:
1994 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1995 if (sbtmstatehigh & 0x00010000)
1996 nr = 9;
1997 else
1998 nr = 10;
1999 break;
2000 case BCM43xx_PHYTYPE_B:
2001 case BCM43xx_PHYTYPE_G:
2002 nr = 6;
2003 break;
2004 default:
2005 goto err_noinitval;
2006 }
2007 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2008 nr, modparam_fwpostfix);
2009
2010 err = request_firmware(&bcm->initvals1, buf, &bcm->pci_dev->dev);
2011 if (err) {
2012 printk(KERN_ERR PFX
2013 "Error: InitVals \"%s\" not available or load failed.\n",
2014 buf);
2015 goto error;
2016 }
2017 if (bcm->initvals1->size % sizeof(struct bcm43xx_initval)) {
2018 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2019 goto error;
2020 }
2021 }
2022 }
2023
2024out:
2025 return err;
2026error:
a4a600d3 2027 bcm43xx_release_firmware(bcm, 1);
f222313a
JL		 2028 goto out;
2029err_noinitval:
2030 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2031 err = -ENOENT;
2032 goto error;
2033}
2034
2035static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2036{
2037 const u32 *data;
2038 unsigned int i, len;
2039
f222313a
JL		 2040 /* Upload Microcode. */
2041 data = (u32 *)(bcm->ucode->data);
2042 len = bcm->ucode->size / sizeof(u32);
2043 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2044 for (i = 0; i < len; i++) {
2045 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2046 be32_to_cpu(data[i]));
2047 udelay(10);
2048 }
2049
2050 /* Upload PCM data. */
2051 data = (u32 *)(bcm->pcm->data);
2052 len = bcm->pcm->size / sizeof(u32);
2053 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2054 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2055 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2056 for (i = 0; i < len; i++) {
2057 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2058 be32_to_cpu(data[i]));
2059 udelay(10);
2060 }
f222313a
JL		 2061}
2062
a4a600d3
MB		 2063static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2064 const struct bcm43xx_initval *data,
2065 const unsigned int len)
f222313a
JL		 2066{
2067 u16 offset, size;
2068 u32 value;
2069 unsigned int i;
2070
2071 for (i = 0; i < len; i++) {
2072 offset = be16_to_cpu(data[i].offset);
2073 size = be16_to_cpu(data[i].size);
2074 value = be32_to_cpu(data[i].value);
2075
a4a600d3
MB		 2076 if (unlikely(offset >= 0x1000))
2077 goto err_format;
2078 if (size == 2) {
2079 if (unlikely(value & 0xFFFF0000))
2080 goto err_format;
2081 bcm43xx_write16(bcm, offset, (u16)value);
2082 } else if (size == 4) {
f222313a 2083 bcm43xx_write32(bcm, offset, value);
a4a600d3
MB		 2084 } else
2085 goto err_format;
f222313a 2086 }
a4a600d3
MB		 2087
2088 return 0;
2089
2090err_format:
2091 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2092 "Please fix your bcm43xx firmware files.\n");
2093 return -EPROTO;
f222313a
JL		 2094}
2095
a4a600d3 2096static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
f222313a 2097{
a4a600d3
MB		 2098 int err;
2099
a4a600d3
MB		 2100 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals0->data,
2101 bcm->initvals0->size / sizeof(struct bcm43xx_initval));
2102 if (err)
2103 goto out;
f222313a 2104 if (bcm->initvals1) {
a4a600d3
MB		 2105 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals1->data,
2106 bcm->initvals1->size / sizeof(struct bcm43xx_initval));
2107 if (err)
2108 goto out;
f222313a 2109 }
a4a600d3 2110out:
a4a600d3 2111 return err;
f222313a
JL		 2112}
2113
2114static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2115{
2116 int res;
2117 unsigned int i;
2118 u32 data;
2119
2120 bcm->irq = bcm->pci_dev->irq;
2121#ifdef CONFIG_BCM947XX
2122 if (bcm->pci_dev->bus->number == 0) {
2123 struct pci_dev *d = NULL;
2124 /* FIXME: we will probably need more device IDs here... */
2125 d = pci_find_device(PCI_VENDOR_ID_BROADCOM, 0x4324, NULL);
2126 if (d != NULL) {
2127 bcm->irq = d->irq;
2128 }
2129 }
2130#endif
2131 res = request_irq(bcm->irq, bcm43xx_interrupt_handler,
65f3f191 2132 SA_SHIRQ, KBUILD_MODNAME, bcm);
f222313a
JL		 2133 if (res) {
2134 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
489423c8 2135 return -ENODEV;
f222313a
JL		 2136 }
2137 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xffffffff);
2138 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2139 i = 0;
2140 while (1) {
2141 data = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2142 if (data == BCM43xx_IRQ_READY)
2143 break;
2144 i++;
2145 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2146 printk(KERN_ERR PFX "Card IRQ register not responding. "
2147 "Giving up.\n");
2148 free_irq(bcm->irq, bcm);
2149 return -ENODEV;
2150 }
2151 udelay(10);
2152 }
2153 // dummy read
2154 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2155
2156 return 0;
2157}
2158
2159/* Switch to the core used to write the GPIO register.
2160 * This is either the ChipCommon, or the PCI core.
2161 */
489423c8 2162static int switch_to_gpio_core(struct bcm43xx_private *bcm)
f222313a
JL		 2163{
2164 int err;
2165
2166 /* Where to find the GPIO register depends on the chipset.
2167 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2168 * control register. Otherwise the register at offset 0x6c in the
2169 * PCI core is the GPIO control register.
2170 */
2171 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2172 if (err == -ENODEV) {
2173 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
489423c8 2174 if (unlikely(err == -ENODEV)) {
f222313a
JL		 2175 printk(KERN_ERR PFX "gpio error: "
2176 "Neither ChipCommon nor PCI core available!\n");
714eece7
MB		 2177 }
2178 }
f222313a 2179
714eece7 2180 return err;
f222313a
JL		 2181}
2182
2183/* Initialize the GPIOs
2184 * http://bcm-specs.sipsolutions.net/GPIO
2185 */
2186static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2187{
2188 struct bcm43xx_coreinfo *old_core;
2189 int err;
714eece7 2190 u32 mask, set;
f222313a 2191
714eece7
MB		 2192 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2193 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2194 & 0xFFFF3FFF);
f222313a 2195
714eece7 2196 bcm43xx_leds_switch_all(bcm, 0);
f222313a
JL		 2197 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2198 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2199
714eece7
MB		 2200 mask = 0x0000001F;
2201 set = 0x0000000F;
f222313a 2202 if (bcm->chip_id == 0x4301) {
714eece7
MB		 2203 mask |= 0x0060;
2204 set |= 0x0060;
2205 }
2206 if (0 /* FIXME: conditional unknown */) {
2207 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2208 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2209 | 0x0100);
2210 mask |= 0x0180;
2211 set |= 0x0180;
f222313a
JL		 2212 }
2213 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
714eece7
MB		 2214 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2215 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2216 | 0x0200);
2217 mask |= 0x0200;
2218 set |= 0x0200;
f222313a 2219 }
714eece7
MB		 2220 if (bcm->current_core->rev >= 2)
2221 mask |= 0x0010; /* FIXME: This is redundant. */
f222313a 2222
714eece7
MB		 2223 old_core = bcm->current_core;
2224 err = switch_to_gpio_core(bcm);
2225 if (err)
2226 goto out;
f222313a 2227 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
714eece7 2228 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
f222313a 2229 err = bcm43xx_switch_core(bcm, old_core);
714eece7
MB		 2230out:
2231 return err;
f222313a
JL		 2232}
2233
2234/* Turn off all GPIO stuff. Call this on module unload, for example. */
2235static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2236{
2237 struct bcm43xx_coreinfo *old_core;
2238 int err;
2239
2240 old_core = bcm->current_core;
2241 err = switch_to_gpio_core(bcm);
2242 if (err)
2243 return err;
2244 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2245 err = bcm43xx_switch_core(bcm, old_core);
2246 assert(err == 0);
2247
2248 return 0;
2249}
2250
2251/* http://bcm-specs.sipsolutions.net/EnableMac */
2252void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2253{
2254 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2255 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2256 | BCM43xx_SBF_MAC_ENABLED);
2257 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2258 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2259 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2260 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2261}
2262
2263/* http://bcm-specs.sipsolutions.net/SuspendMAC */
2264void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2265{
2266 int i;
2267 u32 tmp;
2268
2269 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2270 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2271 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2272 & ~BCM43xx_SBF_MAC_ENABLED);
2273 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
921e485f 2274 for (i = 100000; i; i--) {
f222313a 2275 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
921e485f
MB		 2276 if (tmp & BCM43xx_IRQ_READY)
2277 return;
f222313a
JL		 2278 udelay(10);
2279 }
921e485f 2280 printkl(KERN_ERR PFX "MAC suspend failed\n");
f222313a
JL		 2281}
2282
2283void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2284 int iw_mode)
2285{
2286 unsigned long flags;
6ab5b8e6 2287 struct net_device *net_dev = bcm->net_dev;
f222313a 2288 u32 status;
6ab5b8e6 2289 u16 value;
f222313a
JL		 2290
2291 spin_lock_irqsave(&bcm->ieee->lock, flags);
2292 bcm->ieee->iw_mode = iw_mode;
2293 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2294 if (iw_mode == IW_MODE_MONITOR)
6ab5b8e6 2295 net_dev->type = ARPHRD_IEEE80211;
f222313a 2296 else
6ab5b8e6 2297 net_dev->type = ARPHRD_ETHER;
f222313a 2298
f222313a
JL		 2299 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2300 /* Reset status to infrastructured mode */
2301 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
6ab5b8e6
MB		 2302 status &= ~BCM43xx_SBF_MODE_PROMISC;
2303 status |= BCM43xx_SBF_MODE_NOTADHOC;
2304
2305/* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2306status |= BCM43xx_SBF_MODE_PROMISC;
f222313a
JL		 2307
2308 switch (iw_mode) {
2309 case IW_MODE_MONITOR:
6ab5b8e6
MB		 2310 status |= BCM43xx_SBF_MODE_MONITOR;
2311 status |= BCM43xx_SBF_MODE_PROMISC;
f222313a
JL		 2312 break;
2313 case IW_MODE_ADHOC:
2314 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2315 break;
2316 case IW_MODE_MASTER:
6ab5b8e6
MB		 2317 status |= BCM43xx_SBF_MODE_AP;
2318 break;
f222313a
JL		 2319 case IW_MODE_SECOND:
2320 case IW_MODE_REPEAT:
6ab5b8e6 2321 TODO(); /* TODO */
f222313a
JL		 2322 break;
2323 case IW_MODE_INFRA:
2324 /* nothing to be done here... */
2325 break;
2326 default:
6ab5b8e6 2327 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
f222313a 2328 }
6ab5b8e6
MB		 2329 if (net_dev->flags & IFF_PROMISC)
2330 status |= BCM43xx_SBF_MODE_PROMISC;
f222313a 2331 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
6ab5b8e6
MB		 2332
2333 value = 0x0002;
2334 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2335 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2336 value = 0x0064;
2337 else
2338 value = 0x0032;
2339 }
2340 bcm43xx_write16(bcm, 0x0612, value);
f222313a
JL		 2341}
2342
2343/* This is the opposite of bcm43xx_chip_init() */
2344static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2345{
2346 bcm43xx_radio_turn_off(bcm);
2347 if (!modparam_noleds)
2348 bcm43xx_leds_exit(bcm);
2349 bcm43xx_gpio_cleanup(bcm);
2350 free_irq(bcm->irq, bcm);
a4a600d3 2351 bcm43xx_release_firmware(bcm, 0);
f222313a
JL		 2352}
2353
2354/* Initialize the chip
2355 * http://bcm-specs.sipsolutions.net/ChipInit
2356 */
2357static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2358{
e9357c05
MB		 2359 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2360 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a 2361 int err;
f222313a
JL		 2362 int tmp;
2363 u32 value32;
2364 u16 value16;
2365
2366 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2367 BCM43xx_SBF_CORE_READY
2368 | BCM43xx_SBF_400);
2369
2370 err = bcm43xx_request_firmware(bcm);
2371 if (err)
2372 goto out;
2373 bcm43xx_upload_microcode(bcm);
2374
2375 err = bcm43xx_initialize_irq(bcm);
2376 if (err)
a4a600d3 2377 goto err_release_fw;
f222313a
JL		 2378
2379 err = bcm43xx_gpio_init(bcm);
2380 if (err)
2381 goto err_free_irq;
2382
a4a600d3
MB		 2383 err = bcm43xx_upload_initvals(bcm);
2384 if (err)
2385 goto err_gpio_cleanup;
f222313a
JL		 2386 bcm43xx_radio_turn_on(bcm);
2387
f222313a
JL		 2388 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2389 err = bcm43xx_phy_init(bcm);
2390 if (err)
2391 goto err_radio_off;
2392
2393 /* Select initial Interference Mitigation. */
e9357c05
MB		 2394 tmp = radio->interfmode;
2395 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
f222313a
JL		 2396 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2397
2398 bcm43xx_phy_set_antenna_diversity(bcm);
2399 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
e9357c05 2400 if (phy->type == BCM43xx_PHYTYPE_B) {
f222313a
JL		 2401 value16 = bcm43xx_read16(bcm, 0x005E);
2402 value16 |= 0x0004;
2403 bcm43xx_write16(bcm, 0x005E, value16);
2404 }
2405 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2406 if (bcm->current_core->rev < 5)
2407 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2408
2409 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2410 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2411 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2412 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2413 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2414 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
f222313a 2415
f222313a 2416 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
6ab5b8e6 2417 value32 |= 0x100000;
f222313a
JL		 2418 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2419
77db31ea 2420 if (bcm43xx_using_pio(bcm)) {
f222313a
JL		 2421 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2422 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2423 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2424 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2425 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2426 }
2427
2428 /* Probe Response Timeout value */
2429 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2430 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2431
6ab5b8e6
MB		 2432 /* Initially set the wireless operation mode. */
2433 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
f222313a
JL		 2434
2435 if (bcm->current_core->rev < 3) {
2436 bcm43xx_write16(bcm, 0x060E, 0x0000);
2437 bcm43xx_write16(bcm, 0x0610, 0x8000);
2438 bcm43xx_write16(bcm, 0x0604, 0x0000);
2439 bcm43xx_write16(bcm, 0x0606, 0x0200);
2440 } else {
2441 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2442 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2443 }
2444 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2445 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);
2446 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2447 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);
2448 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);
2449
2450 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2451 value32 |= 0x00100000;
2452 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2453
2454 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2455
2456 assert(err == 0);
2457 dprintk(KERN_INFO PFX "Chip initialized\n");
2458out:
2459 return err;
2460
2461err_radio_off:
2462 bcm43xx_radio_turn_off(bcm);
a4a600d3 2463err_gpio_cleanup:
f222313a
JL		 2464 bcm43xx_gpio_cleanup(bcm);
2465err_free_irq:
2466 free_irq(bcm->irq, bcm);
a4a600d3
MB		 2467err_release_fw:
2468 bcm43xx_release_firmware(bcm, 1);
f222313a
JL		 2469 goto out;
2470}
2471
2472/* Validate chip access
2473 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2474static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2475{
f222313a
JL		 2476 u32 value;
2477 u32 shm_backup;
2478
2479 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2480 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
489423c8
MB		 2481 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2482 goto error;
f222313a 2483 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
489423c8
MB		 2484 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2485 goto error;
f222313a
JL		 2486 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2487
2488 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
489423c8
MB		 2489 if ((value | 0x80000000) != 0x80000400)
2490 goto error;
f222313a
JL		 2491
2492 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
489423c8
MB		 2493 if (value != 0x00000000)
2494 goto error;
f222313a 2495
489423c8
MB		 2496 return 0;
2497error:
2498 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2499 return -ENODEV;
f222313a
JL		 2500}
2501
e9357c05
MB		 2502void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2503{
2504 /* Initialize a "phyinfo" structure. The structure is already
2505 * zeroed out.
2506 */
2507 phy->antenna_diversity = 0xFFFF;
2508 phy->savedpctlreg = 0xFFFF;
2509 phy->minlowsig[0] = 0xFFFF;
2510 phy->minlowsig[1] = 0xFFFF;
2511 spin_lock_init(&phy->lock);
2512}
2513
2514void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2515{
2516 /* Initialize a "radioinfo" structure. The structure is already
2517 * zeroed out.
2518 */
2519 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2520 radio->channel = 0xFF;
2521 radio->initial_channel = 0xFF;
2522 radio->lofcal = 0xFFFF;
2523 radio->initval = 0xFFFF;
2524 radio->nrssi[0] = -1000;
2525 radio->nrssi[1] = -1000;
2526}
2527
f222313a
JL		 2528static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2529{
2530 int err, i;
2531 int current_core;
2532 u32 core_vendor, core_id, core_rev;
2533 u32 sb_id_hi, chip_id_32 = 0;
2534 u16 pci_device, chip_id_16;
2535 u8 core_count;
2536
2537 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2538 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
f222313a
JL		 2539 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2540 * BCM43xx_MAX_80211_CORES);
e9357c05
MB		 2541 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2542 * BCM43xx_MAX_80211_CORES);
2543 bcm->current_80211_core_idx = -1;
2544 bcm->nr_80211_available = 0;
2545 bcm->current_core = NULL;
2546 bcm->active_80211_core = NULL;
f222313a
JL		 2547
2548 /* map core 0 */
2549 err = _switch_core(bcm, 0);
2550 if (err)
2551 goto out;
2552
2553 /* fetch sb_id_hi from core information registers */
2554 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2555
2556 core_id = (sb_id_hi & 0xFFF0) >> 4;
2557 core_rev = (sb_id_hi & 0xF);
2558 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2559
2560 /* if present, chipcommon is always core 0; read the chipid from it */
2561 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2562 chip_id_32 = bcm43xx_read32(bcm, 0);
2563 chip_id_16 = chip_id_32 & 0xFFFF;
e9357c05 2564 bcm->core_chipcommon.available = 1;
f222313a
JL		 2565 bcm->core_chipcommon.id = core_id;
2566 bcm->core_chipcommon.rev = core_rev;
2567 bcm->core_chipcommon.index = 0;
2568 /* While we are at it, also read the capabilities. */
2569 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2570 } else {
2571 /* without a chipCommon, use a hard coded table. */
2572 pci_device = bcm->pci_dev->device;
2573 if (pci_device == 0x4301)
2574 chip_id_16 = 0x4301;
2575 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2576 chip_id_16 = 0x4307;
2577 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2578 chip_id_16 = 0x4402;
2579 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2580 chip_id_16 = 0x4610;
2581 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2582 chip_id_16 = 0x4710;
2583#ifdef CONFIG_BCM947XX
2584 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2585 chip_id_16 = 0x4309;
2586#endif
2587 else {
2588 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2589 return -ENODEV;
2590 }
2591 }
2592
2593 /* ChipCommon with Core Rev >=4 encodes number of cores,
2594 * otherwise consult hardcoded table */
2595 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2596 core_count = (chip_id_32 & 0x0F000000) >> 24;
2597 } else {
2598 switch (chip_id_16) {
2599 case 0x4610:
2600 case 0x4704:
2601 case 0x4710:
2602 core_count = 9;
2603 break;
2604 case 0x4310:
2605 core_count = 8;
2606 break;
2607 case 0x5365:
2608 core_count = 7;
2609 break;
2610 case 0x4306:
2611 core_count = 6;
2612 break;
2613 case 0x4301:
2614 case 0x4307:
2615 core_count = 5;
2616 break;
2617 case 0x4402:
2618 core_count = 3;
2619 break;
2620 default:
2621 /* SOL if we get here */
2622 assert(0);
2623 core_count = 1;
2624 }
2625 }
2626
2627 bcm->chip_id = chip_id_16;
2628 bcm->chip_rev = (chip_id_32 & 0x000f0000) >> 16;
2629
2630 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2631 bcm->chip_id, bcm->chip_rev);
2632 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
e9357c05 2633 if (bcm->core_chipcommon.available) {
f222313a
JL		 2634 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2635 core_id, core_rev, core_vendor,
2636 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2637 }
2638
e9357c05 2639 if (bcm->core_chipcommon.available)
f222313a
JL		 2640 current_core = 1;
2641 else
2642 current_core = 0;
2643 for ( ; current_core < core_count; current_core++) {
2644 struct bcm43xx_coreinfo *core;
e9357c05 2645 struct bcm43xx_coreinfo_80211 *ext_80211;
f222313a
JL		 2646
2647 err = _switch_core(bcm, current_core);
2648 if (err)
2649 goto out;
2650 /* Gather information */
2651 /* fetch sb_id_hi from core information registers */
2652 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2653
2654 /* extract core_id, core_rev, core_vendor */
2655 core_id = (sb_id_hi & 0xFFF0) >> 4;
2656 core_rev = (sb_id_hi & 0xF);
2657 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2658
2659 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2660 current_core, core_id, core_rev, core_vendor,
2661 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2662
2663 core = NULL;
2664 switch (core_id) {
2665 case BCM43xx_COREID_PCI:
2666 core = &bcm->core_pci;
e9357c05 2667 if (core->available) {
f222313a
JL		 2668 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2669 continue;
2670 }
2671 break;
f222313a
JL		 2672 case BCM43xx_COREID_80211:
2673 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2674 core = &(bcm->core_80211[i]);
e9357c05
MB		 2675 ext_80211 = &(bcm->core_80211_ext[i]);
2676 if (!core->available)
f222313a
JL		 2677 break;
2678 core = NULL;
2679 }
2680 if (!core) {
2681 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2682 BCM43xx_MAX_80211_CORES);
2683 continue;
2684 }
2685 if (i != 0) {
2686 /* More than one 80211 core is only supported
2687 * by special chips.
2688 * There are chips with two 80211 cores, but with
2689 * dangling pins on the second core. Be careful
2690 * and ignore these cores here.
2691 */
2692 if (bcm->pci_dev->device != 0x4324) {
2693 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2694 continue;
2695 }
2696 }
2697 switch (core_rev) {
2698 case 2:
2699 case 4:
2700 case 5:
2701 case 6:
2702 case 7:
2703 case 9:
2704 break;
2705 default:
2706 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2707 core_rev);
2708 err = -ENODEV;
2709 goto out;
2710 }
e9357c05
MB		 2711 bcm->nr_80211_available++;
2712 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2713 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
f222313a
JL		 2714 break;
2715 case BCM43xx_COREID_CHIPCOMMON:
2716 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2717 break;
f222313a
JL		 2718 }
2719 if (core) {
e9357c05 2720 core->available = 1;
f222313a
JL		 2721 core->id = core_id;
2722 core->rev = core_rev;
2723 core->index = current_core;
2724 }
2725 }
2726
e9357c05 2727 if (!bcm->core_80211[0].available) {
f222313a
JL		 2728 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2729 err = -ENODEV;
2730 goto out;
2731 }
2732
2733 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2734
2735 assert(err == 0);
2736out:
2737 return err;
2738}
2739
2740static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2741{
2742 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2743 u8 *bssid = bcm->ieee->bssid;
2744
2745 switch (bcm->ieee->iw_mode) {
2746 case IW_MODE_ADHOC:
2747 random_ether_addr(bssid);
2748 break;
2749 case IW_MODE_MASTER:
2750 case IW_MODE_INFRA:
2751 case IW_MODE_REPEAT:
2752 case IW_MODE_SECOND:
2753 case IW_MODE_MONITOR:
2754 memcpy(bssid, mac, ETH_ALEN);
2755 break;
2756 default:
2757 assert(0);
2758 }
2759}
2760
2761static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2762 u16 rate,
2763 int is_ofdm)
2764{
2765 u16 offset;
2766
2767 if (is_ofdm) {
2768 offset = 0x480;
2769 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2770 }
2771 else {
2772 offset = 0x4C0;
2773 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2774 }
2775 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2776 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2777}
2778
2779static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2780{
e9357c05 2781 switch (bcm43xx_current_phy(bcm)->type) {
f222313a
JL		 2782 case BCM43xx_PHYTYPE_A:
2783 case BCM43xx_PHYTYPE_G:
2784 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2785 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2786 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2787 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2788 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2789 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2790 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2791 case BCM43xx_PHYTYPE_B:
2792 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2793 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2794 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2795 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2796 break;
2797 default:
2798 assert(0);
2799 }
2800}
2801
2802static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2803{
2804 bcm43xx_chip_cleanup(bcm);
2805 bcm43xx_pio_free(bcm);
2806 bcm43xx_dma_free(bcm);
2807
e9357c05 2808 bcm->current_core->initialized = 0;
f222313a
JL		 2809}
2810
2811/* http://bcm-specs.sipsolutions.net/80211Init */
2812static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm)
2813{
e9357c05
MB		 2814 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2815 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
f222313a
JL		 2816 u32 ucodeflags;
2817 int err;
2818 u32 sbimconfiglow;
2819 u8 limit;
2820
2821 if (bcm->chip_rev < 5) {
2822 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2823 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2824 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2825 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2826 sbimconfiglow |= 0x32;
2827 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2828 sbimconfiglow |= 0x53;
2829 else
2830 assert(0);
2831 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2832 }
2833
2834 bcm43xx_phy_calibrate(bcm);
2835 err = bcm43xx_chip_init(bcm);
2836 if (err)
2837 goto out;
2838
2839 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2840 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2841
2842 if (0 /*FIXME: which condition has to be used here? */)
2843 ucodeflags |= 0x00000010;
2844
2845 /* HW decryption needs to be set now */
2846 ucodeflags |= 0x40000000;
2847
e9357c05 2848 if (phy->type == BCM43xx_PHYTYPE_G) {
f222313a 2849 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
e9357c05 2850 if (phy->rev == 1)
f222313a
JL		 2851 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2852 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2853 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
e9357c05 2854 } else if (phy->type == BCM43xx_PHYTYPE_B) {
f222313a 2855 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
e9357c05 2856 if (phy->rev >= 2 && radio->version == 0x2050)
f222313a
JL		 2857 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2858 }
2859
2860 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2861 BCM43xx_UCODEFLAGS_OFFSET)) {
2862 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2863 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2864 }
2865
2866 /* Short/Long Retry Limit.
2867 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2868 * the chip-internal counter.
2869 */
2870 limit = limit_value(modparam_short_retry, 0, 0xF);
2871 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2872 limit = limit_value(modparam_long_retry, 0, 0xF);
2873 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2874
2875 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2876 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2877
2878 bcm43xx_rate_memory_init(bcm);
2879
2880 /* Minimum Contention Window */
e9357c05 2881 if (phy->type == BCM43xx_PHYTYPE_B)
f222313a
JL		 2882 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2883 else
2884 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2885 /* Maximum Contention Window */
2886 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2887
2888 bcm43xx_gen_bssid(bcm);
2889 bcm43xx_write_mac_bssid_templates(bcm);
2890
2891 if (bcm->current_core->rev >= 5)
2892 bcm43xx_write16(bcm, 0x043C, 0x000C);
2893
77db31ea 2894 if (bcm43xx_using_pio(bcm))
f222313a 2895 err = bcm43xx_pio_init(bcm);
77db31ea
MB		 2896 else
2897 err = bcm43xx_dma_init(bcm);
2898 if (err)
2899 goto err_chip_cleanup;
f222313a
JL		 2900 bcm43xx_write16(bcm, 0x0612, 0x0050);
2901 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2902 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2903
2904 bcm43xx_mac_enable(bcm);
2905 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
2906
e9357c05 2907 bcm->current_core->initialized = 1;
f222313a
JL		 2908out:
2909 return err;
2910
2911err_chip_cleanup:
2912 bcm43xx_chip_cleanup(bcm);
2913 goto out;
2914}
2915
2916static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2917{
2918 int err;
2919 u16 pci_status;
2920
2921 err = bcm43xx_pctl_set_crystal(bcm, 1);
2922 if (err)
2923 goto out;
2924 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2925 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2926
2927out:
2928 return err;
2929}
2930
2931static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2932{
2933 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2934 bcm43xx_pctl_set_crystal(bcm, 0);
2935}
2936
489423c8
MB		 2937static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2938 u32 address,
2939 u32 data)
f222313a
JL		 2940{
2941 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2942 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2943}
2944
2945static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2946{
2947 int err;
2948 struct bcm43xx_coreinfo *old_core;
2949
2950 old_core = bcm->current_core;
2951 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2952 if (err)
2953 goto out;
2954
2955 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2956
2957 bcm43xx_switch_core(bcm, old_core);
2958 assert(err == 0);
2959out:
2960 return err;
2961}
2962
2963/* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
2964 * To enable core 0, pass a core_mask of 1<<0
2965 */
2966static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
2967 u32 core_mask)
2968{
2969 u32 backplane_flag_nr;
2970 u32 value;
2971 struct bcm43xx_coreinfo *old_core;
2972 int err = 0;
2973
2974 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
2975 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
2976
2977 old_core = bcm->current_core;
2978 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2979 if (err)
2980 goto out;
2981
2982 if (bcm->core_pci.rev < 6) {
2983 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
2984 value |= (1 << backplane_flag_nr);
2985 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
2986 } else {
2987 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
2988 if (err) {
2989 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
2990 goto out_switch_back;
2991 }
2992 value |= core_mask << 8;
2993 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
2994 if (err) {
2995 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
2996 goto out_switch_back;
2997 }
2998 }
2999
3000 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3001 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3002 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3003
3004 if (bcm->core_pci.rev < 5) {
3005 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3006 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3007 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3008 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3009 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3010 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3011 err = bcm43xx_pcicore_commit_settings(bcm);
3012 assert(err == 0);
3013 }
3014
3015out_switch_back:
3016 err = bcm43xx_switch_core(bcm, old_core);
3017out:
3018 return err;
3019}
3020
3021static void bcm43xx_softmac_init(struct bcm43xx_private *bcm)
3022{
3023 ieee80211softmac_start(bcm->net_dev);
3024}
3025
ab4977f8 3026static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
f222313a 3027{
e9357c05 3028 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a 3029
ab4977f8
MB		 3030 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3031 return;
f222313a 3032
ab4977f8
MB		 3033 bcm43xx_mac_suspend(bcm);
3034 bcm43xx_phy_lo_g_measure(bcm);
3035 bcm43xx_mac_enable(bcm);
f222313a
JL		 3036}
3037
ab4977f8 3038static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
f222313a 3039{
f222313a
JL		 3040 bcm43xx_phy_lo_mark_all_unused(bcm);
3041 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3042 bcm43xx_mac_suspend(bcm);
3043 bcm43xx_calc_nrssi_slope(bcm);
3044 bcm43xx_mac_enable(bcm);
3045 }
f222313a
JL		 3046}
3047
ab4977f8 3048static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
f222313a 3049{
ab4977f8
MB		 3050 /* Update device statistics. */
3051 bcm43xx_calculate_link_quality(bcm);
3052}
f222313a 3053
ab4977f8
MB		 3054static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3055{
e9357c05
MB		 3056 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3057 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
f222313a 3058
ab4977f8
MB		 3059 if (phy->type == BCM43xx_PHYTYPE_G) {
3060 //TODO: update_aci_moving_average
3061 if (radio->aci_enable && radio->aci_wlan_automatic) {
3062 bcm43xx_mac_suspend(bcm);
3063 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3064 if (0 /*TODO: bunch of conditions*/) {
3065 bcm43xx_radio_set_interference_mitigation(bcm,
3066 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3067 }
3068 } else if (1/*TODO*/) {
3069 /*
3070 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3071 bcm43xx_radio_set_interference_mitigation(bcm,
3072 BCM43xx_RADIO_INTERFMODE_NONE);
3073 }
3074 */
3075 }
3076 bcm43xx_mac_enable(bcm);
3077 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3078 phy->rev == 1) {
3079 //TODO: implement rev1 workaround
3080 }
f222313a 3081 }
ab4977f8
MB		 3082 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3083 //TODO for APHY (temperature?)
f222313a
JL		 3084}
3085
ab4977f8 3086static void bcm43xx_periodic_task_handler(unsigned long d)
f222313a 3087{
ab4977f8 3088 struct bcm43xx_private *bcm = (struct bcm43xx_private *)d;
f222313a 3089 unsigned long flags;
ab4977f8 3090 unsigned int state;
f222313a 3091
efccb647 3092 bcm43xx_lock_mmio(bcm, flags);
f222313a 3093
ab4977f8
MB		 3094 assert(bcm->initialized);
3095 state = bcm->periodic_state;
3096 if (state % 8 == 0)
3097 bcm43xx_periodic_every120sec(bcm);
3098 if (state % 4 == 0)
3099 bcm43xx_periodic_every60sec(bcm);
3100 if (state % 2 == 0)
3101 bcm43xx_periodic_every30sec(bcm);
3102 bcm43xx_periodic_every15sec(bcm);
3103 bcm->periodic_state = state + 1;
3104
3105 mod_timer(&bcm->periodic_tasks, jiffies + (HZ * 15));
f222313a 3106
efccb647 3107 bcm43xx_unlock_mmio(bcm, flags);
f222313a
JL		 3108}
3109
f222313a
JL		 3110static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3111{
ab4977f8 3112 del_timer_sync(&bcm->periodic_tasks);
f222313a
JL		 3113}
3114
f222313a
JL		 3115static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3116{
ab4977f8 3117 struct timer_list *timer = &(bcm->periodic_tasks);
f222313a 3118
1d1a73cc 3119 assert(bcm->initialized);
ab4977f8
MB		 3120 setup_timer(timer,
3121 bcm43xx_periodic_task_handler,
3122 (unsigned long)bcm);
3123 timer->expires = jiffies;
3124 add_timer(timer);
f222313a
JL		 3125}
3126
3127static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3128{
3129 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3130 0x0056) * 2;
3131 bcm43xx_clear_keys(bcm);
3132}
3133
3134/* This is the opposite of bcm43xx_init_board() */
3135static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3136{
3137 int i, err;
3138 unsigned long flags;
3139
367f899a
MB		 3140 bcm43xx_sysfs_unregister(bcm);
3141
ab4977f8
MB		 3142 bcm43xx_periodic_tasks_delete(bcm);
3143
efccb647 3144 bcm43xx_lock(bcm, flags);
f222313a
JL		 3145 bcm->initialized = 0;
3146 bcm->shutting_down = 1;
efccb647 3147 bcm43xx_unlock(bcm, flags);
f222313a 3148
f222313a 3149 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
e9357c05 3150 if (!bcm->core_80211[i].available)
f222313a 3151 continue;
e9357c05 3152 if (!bcm->core_80211[i].initialized)
f222313a
JL		 3153 continue;
3154
3155 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3156 assert(err == 0);
3157 bcm43xx_wireless_core_cleanup(bcm);
3158 }
3159
3160 bcm43xx_pctl_set_crystal(bcm, 0);
3161
efccb647 3162 bcm43xx_lock(bcm, flags);
f222313a 3163 bcm->shutting_down = 0;
efccb647 3164 bcm43xx_unlock(bcm, flags);
f222313a
JL		 3165}
3166
3167static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3168{
3169 int i, err;
f222313a
JL		 3170 int connect_phy;
3171 unsigned long flags;
3172
3173 might_sleep();
3174
efccb647 3175 bcm43xx_lock(bcm, flags);
f222313a
JL		 3176 bcm->initialized = 0;
3177 bcm->shutting_down = 0;
efccb647 3178 bcm43xx_unlock(bcm, flags);
f222313a
JL		 3179
3180 err = bcm43xx_pctl_set_crystal(bcm, 1);
3181 if (err)
3182 goto out;
3183 err = bcm43xx_pctl_init(bcm);
3184 if (err)
3185 goto err_crystal_off;
3186 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3187 if (err)
3188 goto err_crystal_off;
3189
3190 tasklet_enable(&bcm->isr_tasklet);
e9357c05 3191 for (i = 0; i < bcm->nr_80211_available; i++) {
f222313a
JL		 3192 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3193 assert(err != -ENODEV);
3194 if (err)
3195 goto err_80211_unwind;
3196
3197 /* Enable the selected wireless core.
3198 * Connect PHY only on the first core.
3199 */
3200 if (!bcm43xx_core_enabled(bcm)) {
e9357c05
MB		 3201 if (bcm->nr_80211_available == 1) {
3202 connect_phy = bcm43xx_current_phy(bcm)->connected;
f222313a
JL		 3203 } else {
3204 if (i == 0)
3205 connect_phy = 1;
3206 else
3207 connect_phy = 0;
3208 }
3209 bcm43xx_wireless_core_reset(bcm, connect_phy);
3210 }
3211
3212 if (i != 0)
3213 bcm43xx_wireless_core_mark_inactive(bcm, &bcm->core_80211[0]);
3214
3215 err = bcm43xx_wireless_core_init(bcm);
3216 if (err)
3217 goto err_80211_unwind;
3218
3219 if (i != 0) {
3220 bcm43xx_mac_suspend(bcm);
3221 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3222 bcm43xx_radio_turn_off(bcm);
3223 }
3224 }
3225 bcm->active_80211_core = &bcm->core_80211[0];
e9357c05 3226 if (bcm->nr_80211_available >= 2) {
f222313a
JL		 3227 bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
3228 bcm43xx_mac_enable(bcm);
3229 }
3230 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3231 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3232 dprintk(KERN_INFO PFX "80211 cores initialized\n");
3233 bcm43xx_security_init(bcm);
3234 bcm43xx_softmac_init(bcm);
3235
3236 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3237
e9357c05 3238 if (bcm43xx_current_radio(bcm)->initial_channel != 0xFF) {
f222313a 3239 bcm43xx_mac_suspend(bcm);
e9357c05 3240 bcm43xx_radio_selectchannel(bcm, bcm43xx_current_radio(bcm)->initial_channel, 0);
f222313a
JL		 3241 bcm43xx_mac_enable(bcm);
3242 }
cad2b31a
MB		 3243
3244 /* Initialization of the board is done. Flag it as such. */
efccb647 3245 bcm43xx_lock(bcm, flags);
cad2b31a 3246 bcm->initialized = 1;
efccb647 3247 bcm43xx_unlock(bcm, flags);
cad2b31a 3248
f222313a 3249 bcm43xx_periodic_tasks_setup(bcm);
367f899a
MB		 3250 bcm43xx_sysfs_register(bcm);
3251 //FIXME: check for bcm43xx_sysfs_register failure. This function is a bit messy regarding unwinding, though...
f222313a
JL		 3252
3253 assert(err == 0);
3254out:
3255 return err;
3256
3257err_80211_unwind:
3258 tasklet_disable(&bcm->isr_tasklet);
3259 /* unwind all 80211 initialization */
e9357c05
MB		 3260 for (i = 0; i < bcm->nr_80211_available; i++) {
3261 if (!bcm->core_80211[i].initialized)
f222313a
JL		 3262 continue;
3263 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3264 bcm43xx_wireless_core_cleanup(bcm);
3265 }
3266err_crystal_off:
3267 bcm43xx_pctl_set_crystal(bcm, 0);
3268 goto out;
3269}
3270
3271static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3272{
3273 struct pci_dev *pci_dev = bcm->pci_dev;
3274 int i;
3275
3276 bcm43xx_chipset_detach(bcm);
3277 /* Do _not_ access the chip, after it is detached. */
3278 iounmap(bcm->mmio_addr);
3279
3280 pci_release_regions(pci_dev);
3281 pci_disable_device(pci_dev);
3282
3283 /* Free allocated structures/fields */
3284 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
e9357c05
MB		 3285 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3286 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3287 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
f222313a
JL		 3288 }
3289}
3290
3291static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3292{
e9357c05 3293 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
f222313a
JL		 3294 u16 value;
3295 u8 phy_version;
3296 u8 phy_type;
3297 u8 phy_rev;
3298 int phy_rev_ok = 1;
3299 void *p;
3300
3301 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3302
3303 phy_version = (value & 0xF000) >> 12;
3304 phy_type = (value & 0x0F00) >> 8;
3305 phy_rev = (value & 0x000F);
3306
3307 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3308 phy_version, phy_type, phy_rev);
3309
3310 switch (phy_type) {
3311 case BCM43xx_PHYTYPE_A:
3312 if (phy_rev >= 4)
3313 phy_rev_ok = 0;
3314 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3315 * if we switch 80211 cores after init is done.
3316 * As we do not implement on the fly switching between
3317 * wireless cores, I will leave this as a future task.
3318 */
3319 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3320 bcm->ieee->mode = IEEE_A;
3321 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3322 IEEE80211_24GHZ_BAND;
3323 break;
3324 case BCM43xx_PHYTYPE_B:
3325 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3326 phy_rev_ok = 0;
3327 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3328 bcm->ieee->mode = IEEE_B;
3329 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3330 break;
3331 case BCM43xx_PHYTYPE_G:
3332 if (phy_rev > 7)
3333 phy_rev_ok = 0;
3334 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3335 IEEE80211_CCK_MODULATION;
3336 bcm->ieee->mode = IEEE_G;
3337 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3338 break;
3339 default:
3340 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3341 phy_type);
3342 return -ENODEV;
3343 };
3344 if (!phy_rev_ok) {
3345 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3346 phy_rev);
3347 }
3348
489423c8
MB		 3349 phy->version = phy_version;
3350 phy->type = phy_type;
3351 phy->rev = phy_rev;
f222313a
JL		 3352 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3353 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3354 GFP_KERNEL);
3355 if (!p)
3356 return -ENOMEM;
489423c8 3357 phy->_lo_pairs = p;
f222313a
JL		 3358 }
3359
3360 return 0;
3361}
3362
3363static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3364{
3365 struct pci_dev *pci_dev = bcm->pci_dev;
3366 struct net_device *net_dev = bcm->net_dev;
3367 int err;
3368 int i;
4a1821e4 3369 unsigned long mmio_start, mmio_flags, mmio_len;
f222313a
JL		 3370 u32 coremask;
3371
3372 err = pci_enable_device(pci_dev);
3373 if (err) {
3374 printk(KERN_ERR PFX "unable to wake up pci device (%i)\n", err);
f222313a
JL		 3375 goto out;
3376 }
f222313a 3377 mmio_start = pci_resource_start(pci_dev, 0);
f222313a
JL		 3378 mmio_flags = pci_resource_flags(pci_dev, 0);
3379 mmio_len = pci_resource_len(pci_dev, 0);
f222313a
JL		 3380 if (!(mmio_flags & IORESOURCE_MEM)) {
3381 printk(KERN_ERR PFX
3382 "%s, region #0 not an MMIO resource, aborting\n",
3383 pci_name(pci_dev));
3384 err = -ENODEV;
3385 goto err_pci_disable;
3386 }
65f3f191 3387 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
f222313a
JL		 3388 if (err) {
3389 printk(KERN_ERR PFX
3390 "could not access PCI resources (%i)\n", err);
3391 goto err_pci_disable;
3392 }
f222313a
JL		 3393 /* enable PCI bus-mastering */
3394 pci_set_master(pci_dev);
4a1821e4
MB		 3395 bcm->mmio_addr = ioremap(mmio_start, mmio_len);
3396 if (!bcm->mmio_addr) {
f222313a
JL		 3397 printk(KERN_ERR PFX "%s: cannot remap MMIO, aborting\n",
3398 pci_name(pci_dev));
3399 err = -EIO;
3400 goto err_pci_release;
3401 }
f222313a 3402 bcm->mmio_len = mmio_len;
4a1821e4 3403 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
f222313a
JL		 3404
3405 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3406 &bcm->board_vendor);
3407 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3408 &bcm->board_type);
3409 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3410 &bcm->board_revision);
3411
3412 err = bcm43xx_chipset_attach(bcm);
3413 if (err)
3414 goto err_iounmap;
3415 err = bcm43xx_pctl_init(bcm);
3416 if (err)
3417 goto err_chipset_detach;
3418 err = bcm43xx_probe_cores(bcm);
3419 if (err)
3420 goto err_chipset_detach;
3421
f222313a
JL		 3422 /* Attach all IO cores to the backplane. */
3423 coremask = 0;
e9357c05 3424 for (i = 0; i < bcm->nr_80211_available; i++)
f222313a
JL		 3425 coremask |= (1 << bcm->core_80211[i].index);
3426 //FIXME: Also attach some non80211 cores?
3427 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3428 if (err) {
3429 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3430 goto err_chipset_detach;
3431 }
3432
ea0922b0 3433 err = bcm43xx_sprom_extract(bcm);
f222313a
JL		 3434 if (err)
3435 goto err_chipset_detach;
3436 err = bcm43xx_leds_init(bcm);
3437 if (err)
3438 goto err_chipset_detach;
3439
e9357c05 3440 for (i = 0; i < bcm->nr_80211_available; i++) {
f222313a
JL		 3441 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3442 assert(err != -ENODEV);
3443 if (err)
3444 goto err_80211_unwind;
3445
3446 /* Enable the selected wireless core.
3447 * Connect PHY only on the first core.
3448 */
3449 bcm43xx_wireless_core_reset(bcm, (i == 0));
3450
3451 err = bcm43xx_read_phyinfo(bcm);
3452 if (err && (i == 0))
3453 goto err_80211_unwind;
3454
3455 err = bcm43xx_read_radioinfo(bcm);
3456 if (err && (i == 0))
3457 goto err_80211_unwind;
3458
3459 err = bcm43xx_validate_chip(bcm);
3460 if (err && (i == 0))
3461 goto err_80211_unwind;
3462
3463 bcm43xx_radio_turn_off(bcm);
3464 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3465 if (err)
3466 goto err_80211_unwind;
3467 bcm43xx_wireless_core_disable(bcm);
3468 }
3469 bcm43xx_pctl_set_crystal(bcm, 0);
3470
3471 /* Set the MAC address in the networking subsystem */
e9357c05 3472 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
f222313a
JL		 3473 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3474 else
3475 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3476
3477 bcm43xx_geo_init(bcm);
3478
3479 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3480 "Broadcom %04X", bcm->chip_id);
3481
3482 assert(err == 0);
3483out:
3484 return err;
3485
3486err_80211_unwind:
3487 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
e9357c05
MB		 3488 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3489 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3490 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
f222313a
JL		 3491 }
3492err_chipset_detach:
3493 bcm43xx_chipset_detach(bcm);
3494err_iounmap:
3495 iounmap(bcm->mmio_addr);
3496err_pci_release:
3497 pci_release_regions(pci_dev);
3498err_pci_disable:
3499 pci_disable_device(pci_dev);
3500 goto out;
3501}
3502
f222313a
JL		 3503/* Do the Hardware IO operations to send the txb */
3504static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3505 struct ieee80211_txb *txb)
3506{
3507 int err = -ENODEV;
3508
77db31ea
MB		 3509 if (bcm43xx_using_pio(bcm))
3510 err = bcm43xx_pio_tx(bcm, txb);
f222313a 3511 else
ea72ab22 3512 err = bcm43xx_dma_tx(bcm, txb);
f222313a
JL		 3513
3514 return err;
3515}
3516
3517static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3518 u8 channel)
3519{
3520 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3521 unsigned long flags;
3522
efccb647 3523 bcm43xx_lock_mmio(bcm, flags);
f222313a
JL		 3524 bcm43xx_mac_suspend(bcm);
3525 bcm43xx_radio_selectchannel(bcm, channel, 0);
3526 bcm43xx_mac_enable(bcm);
efccb647 3527 bcm43xx_unlock_mmio(bcm, flags);
f222313a
JL		 3528}
3529
3530/* set_security() callback in struct ieee80211_device */
3531static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3532 struct ieee80211_security *sec)
3533{
3534 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3535 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3536 unsigned long flags;
3537 int keyidx;
3538
3539 dprintk(KERN_INFO PFX "set security called\n");
efccb647
MB		 3540
3541 bcm43xx_lock_mmio(bcm, flags);
3542
f222313a
JL		 3543 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3544 if (sec->flags & (1<<keyidx)) {
3545 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3546 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3547 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3548 }
3549
3550 if (sec->flags & SEC_ACTIVE_KEY) {
3551 secinfo->active_key = sec->active_key;
3552 dprintk(KERN_INFO PFX " .active_key = %d\n", sec->active_key);
3553 }
3554 if (sec->flags & SEC_UNICAST_GROUP) {
3555 secinfo->unicast_uses_group = sec->unicast_uses_group;
3556 dprintk(KERN_INFO PFX " .unicast_uses_group = %d\n", sec->unicast_uses_group);
3557 }
3558 if (sec->flags & SEC_LEVEL) {
3559 secinfo->level = sec->level;
3560 dprintk(KERN_INFO PFX " .level = %d\n", sec->level);
3561 }
3562 if (sec->flags & SEC_ENABLED) {
3563 secinfo->enabled = sec->enabled;
3564 dprintk(KERN_INFO PFX " .enabled = %d\n", sec->enabled);
3565 }
3566 if (sec->flags & SEC_ENCRYPT) {
3567 secinfo->encrypt = sec->encrypt;
3568 dprintk(KERN_INFO PFX " .encrypt = %d\n", sec->encrypt);
3569 }
3570 if (bcm->initialized && !bcm->ieee->host_encrypt) {
3571 if (secinfo->enabled) {
3572 /* upload WEP keys to hardware */
3573 char null_address[6] = { 0 };
3574 u8 algorithm = 0;
3575 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3576 if (!(sec->flags & (1<<keyidx)))
3577 continue;
3578 switch (sec->encode_alg[keyidx]) {
3579 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3580 case SEC_ALG_WEP:
3581 algorithm = BCM43xx_SEC_ALGO_WEP;
3582 if (secinfo->key_sizes[keyidx] == 13)
3583 algorithm = BCM43xx_SEC_ALGO_WEP104;
3584 break;
3585 case SEC_ALG_TKIP:
3586 FIXME();
3587 algorithm = BCM43xx_SEC_ALGO_TKIP;
3588 break;
3589 case SEC_ALG_CCMP:
3590 FIXME();
3591 algorithm = BCM43xx_SEC_ALGO_AES;
3592 break;
3593 default:
3594 assert(0);
3595 break;
3596 }
3597 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3598 bcm->key[keyidx].enabled = 1;
3599 bcm->key[keyidx].algorithm = algorithm;
3600 }
3601 } else
3602 bcm43xx_clear_keys(bcm);
3603 }
efccb647 3604 bcm43xx_unlock_mmio(bcm, flags);
f222313a
JL		 3605}
3606
3607/* hard_start_xmit() callback in struct ieee80211_device */
3608static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3609 struct net_device *net_dev,
3610 int pri)
3611{
3612 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3613 int err = -ENODEV;
3614 unsigned long flags;
3615
efccb647 3616 bcm43xx_lock_mmio(bcm, flags);
f222313a
JL		 3617 if (likely(bcm->initialized))
3618 err = bcm43xx_tx(bcm, txb);
efccb647 3619 bcm43xx_unlock_mmio(bcm, flags);
f222313a
JL		 3620
3621 return err;
3622}
3623
3624static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3625{
3626 return &(bcm43xx_priv(net_dev)->ieee->stats);
3627}
3628
3629static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3630{
3631 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
efccb647 3632 unsigned long flags;
f222313a 3633
efccb647 3634 bcm43xx_lock_mmio(bcm, flags);
f222313a 3635 bcm43xx_controller_restart(bcm, "TX timeout");
efccb647 3636 bcm43xx_unlock_mmio(bcm, flags);
f222313a
JL		 3637}
3638
3639#ifdef CONFIG_NET_POLL_CONTROLLER
3640static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3641{
3642 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3643 unsigned long flags;
3644
3645 local_irq_save(flags);
3646 bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3647 local_irq_restore(flags);
3648}
3649#endif /* CONFIG_NET_POLL_CONTROLLER */
3650
3651static int bcm43xx_net_open(struct net_device *net_dev)
3652{
3653 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3654
3655 return bcm43xx_init_board(bcm);
3656}
3657
3658static int bcm43xx_net_stop(struct net_device *net_dev)
3659{
3660 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3661
3662 ieee80211softmac_stop(net_dev);
3663 bcm43xx_disable_interrupts_sync(bcm, NULL);
3664 bcm43xx_free_board(bcm);
3665
3666 return 0;
3667}
3668
77db31ea
MB		 3669static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3670 struct net_device *net_dev,
ab4977f8 3671 struct pci_dev *pci_dev)
f222313a 3672{
4d5a9e0e
MB		 3673 int err;
3674
f222313a
JL		 3675 bcm->ieee = netdev_priv(net_dev);
3676 bcm->softmac = ieee80211_priv(net_dev);
3677 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
f222313a 3678
f222313a
JL		 3679 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3680 bcm->pci_dev = pci_dev;
3681 bcm->net_dev = net_dev;
4d5a9e0e 3682 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
efccb647 3683 spin_lock_init(&bcm->_lock);
f222313a
JL		 3684 tasklet_init(&bcm->isr_tasklet,
3685 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3686 (unsigned long)bcm);
3687 tasklet_disable_nosync(&bcm->isr_tasklet);
3688 if (modparam_pio) {
77db31ea 3689 bcm->__using_pio = 1;
f222313a 3690 } else {
4d5a9e0e
MB		 3691 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
3692 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
3693 if (err) {
77db31ea 3694#ifdef CONFIG_BCM43XX_PIO
f222313a 3695 printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
77db31ea
MB		 3696 bcm->__using_pio = 1;
3697#else
3698 printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
3699 "Recompile the driver with PIO support, please.\n");
3700 return -ENODEV;
3701#endif /* CONFIG_BCM43XX_PIO */
f222313a
JL		 3702 }
3703 }
3704 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
3705
3706 /* default to sw encryption for now */
3707 bcm->ieee->host_build_iv = 0;
3708 bcm->ieee->host_encrypt = 1;
3709 bcm->ieee->host_decrypt = 1;
3710
3711 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
3712 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
3713 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
3714 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
77db31ea
MB		 3715
3716 return 0;
f222313a
JL		 3717}
3718
3719static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
3720 const struct pci_device_id *ent)
3721{
3722 struct net_device *net_dev;
3723 struct bcm43xx_private *bcm;
f222313a
JL		 3724 int err;
3725
3726#ifdef CONFIG_BCM947XX
3727 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
3728 return -ENODEV;
3729#endif
3730
3731#ifdef DEBUG_SINGLE_DEVICE_ONLY
3732 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
3733 return -ENODEV;
3734#endif
3735
3736 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
3737 if (!net_dev) {
3738 printk(KERN_ERR PFX
3739 "could not allocate ieee80211 device %s\n",
3740 pci_name(pdev));
3741 err = -ENOMEM;
3742 goto out;
3743 }
3744 /* initialize the net_device struct */
3745 SET_MODULE_OWNER(net_dev);
3746 SET_NETDEV_DEV(net_dev, &pdev->dev);
3747
3748 net_dev->open = bcm43xx_net_open;
3749 net_dev->stop = bcm43xx_net_stop;
3750 net_dev->get_stats = bcm43xx_net_get_stats;
3751 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
3752#ifdef CONFIG_NET_POLL_CONTROLLER
3753 net_dev->poll_controller = bcm43xx_net_poll_controller;
3754#endif
3755 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
3756 net_dev->irq = pdev->irq;
6465ce1b 3757 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
f222313a
JL		 3758
3759 /* initialize the bcm43xx_private struct */
3760 bcm = bcm43xx_priv(net_dev);
3761 memset(bcm, 0, sizeof(*bcm));
ab4977f8 3762 err = bcm43xx_init_private(bcm, net_dev, pdev);
77db31ea 3763 if (err)
ab4977f8 3764 goto err_free_netdev;
f222313a
JL		 3765
3766 pci_set_drvdata(pdev, net_dev);
3767
3768 err = bcm43xx_attach_board(bcm);
3769 if (err)
ab4977f8 3770 goto err_free_netdev;
f222313a
JL		 3771
3772 err = register_netdev(net_dev);
3773 if (err) {
3774 printk(KERN_ERR PFX "Cannot register net device, "
3775 "aborting.\n");
3776 err = -ENOMEM;
3777 goto err_detach_board;
3778 }
3779
3780 bcm43xx_debugfs_add_device(bcm);
3781
3782 assert(err == 0);
3783out:
3784 return err;
3785
3786err_detach_board:
3787 bcm43xx_detach_board(bcm);
f222313a
JL		 3788err_free_netdev:
3789 free_ieee80211softmac(net_dev);
3790 goto out;
3791}
3792
3793static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
3794{
3795 struct net_device *net_dev = pci_get_drvdata(pdev);
3796 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3797
3798 bcm43xx_debugfs_remove_device(bcm);
3799 unregister_netdev(net_dev);
3800 bcm43xx_detach_board(bcm);
3801 assert(bcm->ucode == NULL);
f222313a
JL		 3802 free_ieee80211softmac(net_dev);
3803}
3804
3805/* Hard-reset the chip. Do not call this directly.
3806 * Use bcm43xx_controller_restart()
3807 */
3808static void bcm43xx_chip_reset(void *_bcm)
3809{
3810 struct bcm43xx_private *bcm = _bcm;
3811 struct net_device *net_dev = bcm->net_dev;
3812 struct pci_dev *pci_dev = bcm->pci_dev;
f222313a
JL		 3813 int err;
3814 int was_initialized = bcm->initialized;
3815
3816 netif_stop_queue(bcm->net_dev);
3817 tasklet_disable(&bcm->isr_tasklet);
3818
3819 bcm->firmware_norelease = 1;
3820 if (was_initialized)
3821 bcm43xx_free_board(bcm);
3822 bcm->firmware_norelease = 0;
3823 bcm43xx_detach_board(bcm);
ab4977f8 3824 err = bcm43xx_init_private(bcm, net_dev, pci_dev);
77db31ea
MB		 3825 if (err)
3826 goto failure;
f222313a
JL		 3827 err = bcm43xx_attach_board(bcm);
3828 if (err)
3829 goto failure;
3830 if (was_initialized) {
3831 err = bcm43xx_init_board(bcm);
3832 if (err)
3833 goto failure;
3834 }
3835 netif_wake_queue(bcm->net_dev);
3836 printk(KERN_INFO PFX "Controller restarted\n");
3837
3838 return;
3839failure:
3840 printk(KERN_ERR PFX "Controller restart failed\n");
3841}
3842
3843/* Hard-reset the chip.
3844 * This can be called from interrupt or process context.
3845 * Make sure to _not_ re-enable device interrupts after this has been called.
3846*/
3847void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
3848{
3849 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
73733847 3850 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
f222313a
JL		 3851 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
3852 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
ab4977f8 3853 schedule_work(&bcm->restart_work);
f222313a
JL		 3854}
3855
3856#ifdef CONFIG_PM
3857
3858static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
3859{
3860 struct net_device *net_dev = pci_get_drvdata(pdev);
3861 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3862 unsigned long flags;
3863 int try_to_shutdown = 0, err;
3864
3865 dprintk(KERN_INFO PFX "Suspending...\n");
3866
efccb647 3867 bcm43xx_lock(bcm, flags);
f222313a
JL		 3868 bcm->was_initialized = bcm->initialized;
3869 if (bcm->initialized)
3870 try_to_shutdown = 1;
efccb647 3871 bcm43xx_unlock(bcm, flags);
f222313a
JL		 3872
3873 netif_device_detach(net_dev);
3874 if (try_to_shutdown) {
3875 ieee80211softmac_stop(net_dev);
3876 err = bcm43xx_disable_interrupts_sync(bcm, &bcm->irq_savedstate);
3877 if (unlikely(err)) {
3878 dprintk(KERN_ERR PFX "Suspend failed.\n");
3879 return -EAGAIN;
3880 }
3881 bcm->firmware_norelease = 1;
3882 bcm43xx_free_board(bcm);
3883 bcm->firmware_norelease = 0;
3884 }
3885 bcm43xx_chipset_detach(bcm);
3886
3887 pci_save_state(pdev);
3888 pci_disable_device(pdev);
3889 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3890
3891 dprintk(KERN_INFO PFX "Device suspended.\n");
3892
3893 return 0;
3894}
3895
3896static int bcm43xx_resume(struct pci_dev *pdev)
3897{
3898 struct net_device *net_dev = pci_get_drvdata(pdev);
3899 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3900 int err = 0;
3901
3902 dprintk(KERN_INFO PFX "Resuming...\n");
3903
3904 pci_set_power_state(pdev, 0);
3905 pci_enable_device(pdev);
3906 pci_restore_state(pdev);
3907
3908 bcm43xx_chipset_attach(bcm);
3909 if (bcm->was_initialized) {
3910 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3911 err = bcm43xx_init_board(bcm);
3912 }
3913 if (err) {
3914 printk(KERN_ERR PFX "Resume failed!\n");
3915 return err;
3916 }
3917
3918 netif_device_attach(net_dev);
3919
3920 /*FIXME: This should be handled by softmac instead. */
3921 schedule_work(&bcm->softmac->associnfo.work);
3922
3923 dprintk(KERN_INFO PFX "Device resumed.\n");
3924
3925 return 0;
3926}
3927
3928#endif /* CONFIG_PM */
3929
3930static struct pci_driver bcm43xx_pci_driver = {
65f3f191 3931 .name = KBUILD_MODNAME,
f222313a
JL		 3932 .id_table = bcm43xx_pci_tbl,
3933 .probe = bcm43xx_init_one,
3934 .remove = __devexit_p(bcm43xx_remove_one),
3935#ifdef CONFIG_PM
3936 .suspend = bcm43xx_suspend,
3937 .resume = bcm43xx_resume,
3938#endif /* CONFIG_PM */
3939};
3940
3941static int __init bcm43xx_init(void)
3942{
65f3f191 3943 printk(KERN_INFO KBUILD_MODNAME " driver\n");
f222313a
JL		 3944 bcm43xx_debugfs_init();
3945 return pci_register_driver(&bcm43xx_pci_driver);
3946}
3947
3948static void __exit bcm43xx_exit(void)
3949{
3950 pci_unregister_driver(&bcm43xx_pci_driver);
3951 bcm43xx_debugfs_exit();
3952}
3953
3954module_init(bcm43xx_init)
3955module_exit(bcm43xx_exit)
3956
3957/* vim: set ts=8 sw=8 sts=8: */