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cfg80211 API for channels/bitrates, mac80211 and driver conversion
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / net / wireless / b43legacy / main.c
CommitLineData
75388acd
LF		 1/*
2 *
3 * Broadcom B43legacy wireless driver
4 *
5 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6fff1c64 6 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
75388acd
LF		 7 * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11 *
12 * Some parts of the code in this file are derived from the ipw2200
13 * driver Copyright(c) 2003 - 2004 Intel Corporation.
14
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING. If not, write to
27 * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28 * Boston, MA 02110-1301, USA.
29 *
30 */
31
32#include <linux/delay.h>
33#include <linux/init.h>
34#include <linux/moduleparam.h>
35#include <linux/if_arp.h>
36#include <linux/etherdevice.h>
37#include <linux/version.h>
38#include <linux/firmware.h>
39#include <linux/wireless.h>
40#include <linux/workqueue.h>
41#include <linux/skbuff.h>
42#include <linux/dma-mapping.h>
43#include <net/dst.h>
44#include <asm/unaligned.h>
45
46#include "b43legacy.h"
47#include "main.h"
48#include "debugfs.h"
49#include "phy.h"
50#include "dma.h"
51#include "pio.h"
52#include "sysfs.h"
53#include "xmit.h"
54#include "radio.h"
55
56
57MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
1a1c360d
SB		 63MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
64
75388acd
LF		 65#if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
66static int modparam_pio;
67module_param_named(pio, modparam_pio, int, 0444);
68MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
69#elif defined(CONFIG_B43LEGACY_DMA)
70# define modparam_pio 0
71#elif defined(CONFIG_B43LEGACY_PIO)
72# define modparam_pio 1
73#endif
74
75static int modparam_bad_frames_preempt;
76module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
77MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
78 " Preemption");
79
75388acd
LF		 80static char modparam_fwpostfix[16];
81module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
82MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
83
75388acd
LF		 84/* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
85static const struct ssb_device_id b43legacy_ssb_tbl[] = {
86 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
87 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
88 SSB_DEVTABLE_END
89};
90MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
91
92
93/* Channel and ratetables are shared for all devices.
94 * They can't be const, because ieee80211 puts some precalculated
95 * data in there. This data is the same for all devices, so we don't
96 * get concurrency issues */
97#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 98 { \
99 .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
100 .hw_value = (_rateid), \
101 .flags = (_flags), \
75388acd 102 }
8318d78a
JB		 103/*
104 * NOTE: When changing this, sync with xmit.c's
105 * b43legacy_plcp_get_bitrate_idx_* functions!
106 */
75388acd 107static struct ieee80211_rate __b43legacy_ratetable[] = {
8318d78a
JB		 108 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
109 RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
110 RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
111 RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
112 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
113 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
114 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
115 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
116 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
117 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
118 RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
119 RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
75388acd 120};
75388acd
LF		 121#define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
122#define b43legacy_b_ratetable_size 4
123#define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
124#define b43legacy_g_ratetable_size 12
125
126#define CHANTAB_ENT(_chanid, _freq) \
127 { \
8318d78a
JB		 128 .center_freq = (_freq), \
129 .hw_value = (_chanid), \
75388acd
LF		 130 }
131static struct ieee80211_channel b43legacy_bg_chantable[] = {
132 CHANTAB_ENT(1, 2412),
133 CHANTAB_ENT(2, 2417),
134 CHANTAB_ENT(3, 2422),
135 CHANTAB_ENT(4, 2427),
136 CHANTAB_ENT(5, 2432),
137 CHANTAB_ENT(6, 2437),
138 CHANTAB_ENT(7, 2442),
139 CHANTAB_ENT(8, 2447),
140 CHANTAB_ENT(9, 2452),
141 CHANTAB_ENT(10, 2457),
142 CHANTAB_ENT(11, 2462),
143 CHANTAB_ENT(12, 2467),
144 CHANTAB_ENT(13, 2472),
145 CHANTAB_ENT(14, 2484),
146};
8318d78a
JB		 147
148static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
149 .channels = b43legacy_bg_chantable,
150 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
151 .bitrates = b43legacy_b_ratetable,
152 .n_bitrates = b43legacy_b_ratetable_size,
153};
154
155static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
156 .channels = b43legacy_bg_chantable,
157 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
158 .bitrates = b43legacy_g_ratetable,
159 .n_bitrates = b43legacy_g_ratetable_size,
160};
75388acd
LF		 161
162static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
163static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
164static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
165static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
166
167
168static int b43legacy_ratelimit(struct b43legacy_wl *wl)
169{
170 if (!wl || !wl->current_dev)
171 return 1;
172 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
173 return 1;
174 /* We are up and running.
175 * Ratelimit the messages to avoid DoS over the net. */
176 return net_ratelimit();
177}
178
179void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
180{
181 va_list args;
182
183 if (!b43legacy_ratelimit(wl))
184 return;
185 va_start(args, fmt);
186 printk(KERN_INFO "b43legacy-%s: ",
187 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
188 vprintk(fmt, args);
189 va_end(args);
190}
191
192void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
193{
194 va_list args;
195
196 if (!b43legacy_ratelimit(wl))
197 return;
198 va_start(args, fmt);
199 printk(KERN_ERR "b43legacy-%s ERROR: ",
200 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
201 vprintk(fmt, args);
202 va_end(args);
203}
204
205void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
206{
207 va_list args;
208
209 if (!b43legacy_ratelimit(wl))
210 return;
211 va_start(args, fmt);
212 printk(KERN_WARNING "b43legacy-%s warning: ",
213 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
214 vprintk(fmt, args);
215 va_end(args);
216}
217
218#if B43legacy_DEBUG
219void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
220{
221 va_list args;
222
223 va_start(args, fmt);
224 printk(KERN_DEBUG "b43legacy-%s debug: ",
225 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
226 vprintk(fmt, args);
227 va_end(args);
228}
229#endif /* DEBUG */
230
231static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
232 u32 val)
233{
234 u32 status;
235
236 B43legacy_WARN_ON(offset % 4 != 0);
237
e78c9d28
SB		 238 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
239 if (status & B43legacy_MACCTL_BE)
75388acd
LF		 240 val = swab32(val);
241
242 b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
243 mmiowb();
244 b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
245}
246
247static inline
248void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
249 u16 routing, u16 offset)
250{
251 u32 control;
252
253 /* "offset" is the WORD offset. */
254
255 control = routing;
256 control <<= 16;
257 control |= offset;
258 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
259}
260
261u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
262 u16 routing, u16 offset)
263{
264 u32 ret;
265
266 if (routing == B43legacy_SHM_SHARED) {
267 B43legacy_WARN_ON((offset & 0x0001) != 0);
268 if (offset & 0x0003) {
269 /* Unaligned access */
270 b43legacy_shm_control_word(dev, routing, offset >> 2);
271 ret = b43legacy_read16(dev,
272 B43legacy_MMIO_SHM_DATA_UNALIGNED);
273 ret <<= 16;
274 b43legacy_shm_control_word(dev, routing,
275 (offset >> 2) + 1);
276 ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
277
278 return ret;
279 }
280 offset >>= 2;
281 }
282 b43legacy_shm_control_word(dev, routing, offset);
283 ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
284
285 return ret;
286}
287
288u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
289 u16 routing, u16 offset)
290{
291 u16 ret;
292
293 if (routing == B43legacy_SHM_SHARED) {
294 B43legacy_WARN_ON((offset & 0x0001) != 0);
295 if (offset & 0x0003) {
296 /* Unaligned access */
297 b43legacy_shm_control_word(dev, routing, offset >> 2);
298 ret = b43legacy_read16(dev,
299 B43legacy_MMIO_SHM_DATA_UNALIGNED);
300
301 return ret;
302 }
303 offset >>= 2;
304 }
305 b43legacy_shm_control_word(dev, routing, offset);
306 ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
307
308 return ret;
309}
310
311void b43legacy_shm_write32(struct b43legacy_wldev *dev,
312 u16 routing, u16 offset,
313 u32 value)
314{
315 if (routing == B43legacy_SHM_SHARED) {
316 B43legacy_WARN_ON((offset & 0x0001) != 0);
317 if (offset & 0x0003) {
318 /* Unaligned access */
319 b43legacy_shm_control_word(dev, routing, offset >> 2);
320 mmiowb();
321 b43legacy_write16(dev,
322 B43legacy_MMIO_SHM_DATA_UNALIGNED,
323 (value >> 16) & 0xffff);
324 mmiowb();
325 b43legacy_shm_control_word(dev, routing,
326 (offset >> 2) + 1);
327 mmiowb();
328 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
329 value & 0xffff);
330 return;
331 }
332 offset >>= 2;
333 }
334 b43legacy_shm_control_word(dev, routing, offset);
335 mmiowb();
336 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
337}
338
339void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
340 u16 value)
341{
342 if (routing == B43legacy_SHM_SHARED) {
343 B43legacy_WARN_ON((offset & 0x0001) != 0);
344 if (offset & 0x0003) {
345 /* Unaligned access */
346 b43legacy_shm_control_word(dev, routing, offset >> 2);
347 mmiowb();
348 b43legacy_write16(dev,
349 B43legacy_MMIO_SHM_DATA_UNALIGNED,
350 value);
351 return;
352 }
353 offset >>= 2;
354 }
355 b43legacy_shm_control_word(dev, routing, offset);
356 mmiowb();
357 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
358}
359
360/* Read HostFlags */
361u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
362{
363 u32 ret;
364
365 ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
366 B43legacy_SHM_SH_HOSTFHI);
367 ret <<= 16;
368 ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
369 B43legacy_SHM_SH_HOSTFLO);
370
371 return ret;
372}
373
374/* Write HostFlags */
375void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
376{
377 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
378 B43legacy_SHM_SH_HOSTFLO,
379 (value & 0x0000FFFF));
380 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
381 B43legacy_SHM_SH_HOSTFHI,
382 ((value & 0xFFFF0000) >> 16));
383}
384
385void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
386{
387 /* We need to be careful. As we read the TSF from multiple
388 * registers, we should take care of register overflows.
389 * In theory, the whole tsf read process should be atomic.
390 * We try to be atomic here, by restaring the read process,
391 * if any of the high registers changed (overflew).
392 */
393 if (dev->dev->id.revision >= 3) {
394 u32 low;
395 u32 high;
396 u32 high2;
397
398 do {
399 high = b43legacy_read32(dev,
400 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
401 low = b43legacy_read32(dev,
402 B43legacy_MMIO_REV3PLUS_TSF_LOW);
403 high2 = b43legacy_read32(dev,
404 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
405 } while (unlikely(high != high2));
406
407 *tsf = high;
408 *tsf <<= 32;
409 *tsf |= low;
410 } else {
411 u64 tmp;
412 u16 v0;
413 u16 v1;
414 u16 v2;
415 u16 v3;
416 u16 test1;
417 u16 test2;
418 u16 test3;
419
420 do {
421 v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
422 v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
423 v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
424 v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
425
426 test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
427 test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
428 test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
429 } while (v3 != test3 || v2 != test2 || v1 != test1);
430
431 *tsf = v3;
432 *tsf <<= 48;
433 tmp = v2;
434 tmp <<= 32;
435 *tsf |= tmp;
436 tmp = v1;
437 tmp <<= 16;
438 *tsf |= tmp;
439 *tsf |= v0;
440 }
441}
442
443static void b43legacy_time_lock(struct b43legacy_wldev *dev)
444{
445 u32 status;
446
e78c9d28
SB		 447 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
448 status |= B43legacy_MACCTL_TBTTHOLD;
449 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 450 mmiowb();
451}
452
453static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
454{
455 u32 status;
456
e78c9d28
SB		 457 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
458 status &= ~B43legacy_MACCTL_TBTTHOLD;
459 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
75388acd
LF		 460}
461
462static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
463{
464 /* Be careful with the in-progress timer.
465 * First zero out the low register, so we have a full
466 * register-overflow duration to complete the operation.
467 */
468 if (dev->dev->id.revision >= 3) {
469 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
470 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
471
472 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
473 mmiowb();
474 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
475 hi);
476 mmiowb();
477 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
478 lo);
479 } else {
480 u16 v0 = (tsf & 0x000000000000FFFFULL);
481 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
482 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
483 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
484
485 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
486 mmiowb();
487 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
488 mmiowb();
489 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
490 mmiowb();
491 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
492 mmiowb();
493 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
494 }
495}
496
497void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
498{
499 b43legacy_time_lock(dev);
500 b43legacy_tsf_write_locked(dev, tsf);
501 b43legacy_time_unlock(dev);
502}
503
504static
505void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
506 u16 offset, const u8 *mac)
507{
508 static const u8 zero_addr[ETH_ALEN] = { 0 };
509 u16 data;
510
511 if (!mac)
512 mac = zero_addr;
513
514 offset |= 0x0020;
515 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
516
517 data = mac[0];
518 data |= mac[1] << 8;
519 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
520 data = mac[2];
521 data |= mac[3] << 8;
522 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
523 data = mac[4];
524 data |= mac[5] << 8;
525 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
526}
527
528static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
529{
530 static const u8 zero_addr[ETH_ALEN] = { 0 };
531 const u8 *mac = dev->wl->mac_addr;
532 const u8 *bssid = dev->wl->bssid;
533 u8 mac_bssid[ETH_ALEN * 2];
534 int i;
535 u32 tmp;
536
537 if (!bssid)
538 bssid = zero_addr;
539 if (!mac)
540 mac = zero_addr;
541
542 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
543
544 memcpy(mac_bssid, mac, ETH_ALEN);
545 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
546
547 /* Write our MAC address and BSSID to template ram */
548 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
549 tmp = (u32)(mac_bssid[i + 0]);
550 tmp |= (u32)(mac_bssid[i + 1]) << 8;
551 tmp |= (u32)(mac_bssid[i + 2]) << 16;
552 tmp |= (u32)(mac_bssid[i + 3]) << 24;
553 b43legacy_ram_write(dev, 0x20 + i, tmp);
554 b43legacy_ram_write(dev, 0x78 + i, tmp);
555 b43legacy_ram_write(dev, 0x478 + i, tmp);
556 }
557}
558
4150c572 559static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
75388acd 560{
75388acd 561 b43legacy_write_mac_bssid_templates(dev);
4150c572
JB		 562 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
563 dev->wl->mac_addr);
75388acd
LF		 564}
565
566static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
567 u16 slot_time)
568{
569 /* slot_time is in usec. */
570 if (dev->phy.type != B43legacy_PHYTYPE_G)
571 return;
572 b43legacy_write16(dev, 0x684, 510 + slot_time);
573 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
574 slot_time);
575}
576
577static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
578{
579 b43legacy_set_slot_time(dev, 9);
580 dev->short_slot = 1;
581}
582
583static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
584{
585 b43legacy_set_slot_time(dev, 20);
586 dev->short_slot = 0;
587}
588
589/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
590 * Returns the _previously_ enabled IRQ mask.
591 */
592static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
593 u32 mask)
594{
595 u32 old_mask;
596
597 old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
598 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
599 mask);
600
601 return old_mask;
602}
603
604/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
605 * Returns the _previously_ enabled IRQ mask.
606 */
607static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
608 u32 mask)
609{
610 u32 old_mask;
611
612 old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
613 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
614
615 return old_mask;
616}
617
618/* Synchronize IRQ top- and bottom-half.
619 * IRQs must be masked before calling this.
620 * This must not be called with the irq_lock held.
621 */
622static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
623{
624 synchronize_irq(dev->dev->irq);
625 tasklet_kill(&dev->isr_tasklet);
626}
627
628/* DummyTransmission function, as documented on
629 * http://bcm-specs.sipsolutions.net/DummyTransmission
630 */
631void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
632{
633 struct b43legacy_phy *phy = &dev->phy;
634 unsigned int i;
635 unsigned int max_loop;
636 u16 value;
637 u32 buffer[5] = {
638 0x00000000,
639 0x00D40000,
640 0x00000000,
641 0x01000000,
642 0x00000000,
643 };
644
645 switch (phy->type) {
646 case B43legacy_PHYTYPE_B:
647 case B43legacy_PHYTYPE_G:
648 max_loop = 0xFA;
649 buffer[0] = 0x000B846E;
650 break;
651 default:
652 B43legacy_BUG_ON(1);
653 return;
654 }
655
656 for (i = 0; i < 5; i++)
657 b43legacy_ram_write(dev, i * 4, buffer[i]);
658
659 /* dummy read follows */
e78c9d28 660 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 661
662 b43legacy_write16(dev, 0x0568, 0x0000);
663 b43legacy_write16(dev, 0x07C0, 0x0000);
664 b43legacy_write16(dev, 0x050C, 0x0000);
665 b43legacy_write16(dev, 0x0508, 0x0000);
666 b43legacy_write16(dev, 0x050A, 0x0000);
667 b43legacy_write16(dev, 0x054C, 0x0000);
668 b43legacy_write16(dev, 0x056A, 0x0014);
669 b43legacy_write16(dev, 0x0568, 0x0826);
670 b43legacy_write16(dev, 0x0500, 0x0000);
671 b43legacy_write16(dev, 0x0502, 0x0030);
672
673 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
674 b43legacy_radio_write16(dev, 0x0051, 0x0017);
675 for (i = 0x00; i < max_loop; i++) {
676 value = b43legacy_read16(dev, 0x050E);
677 if (value & 0x0080)
678 break;
679 udelay(10);
680 }
681 for (i = 0x00; i < 0x0A; i++) {
682 value = b43legacy_read16(dev, 0x050E);
683 if (value & 0x0400)
684 break;
685 udelay(10);
686 }
687 for (i = 0x00; i < 0x0A; i++) {
688 value = b43legacy_read16(dev, 0x0690);
689 if (!(value & 0x0100))
690 break;
691 udelay(10);
692 }
693 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
694 b43legacy_radio_write16(dev, 0x0051, 0x0037);
695}
696
697/* Turn the Analog ON/OFF */
698static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
699{
700 b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
701}
702
703void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
704{
705 u32 tmslow;
706 u32 macctl;
707
708 flags |= B43legacy_TMSLOW_PHYCLKEN;
709 flags |= B43legacy_TMSLOW_PHYRESET;
710 ssb_device_enable(dev->dev, flags);
711 msleep(2); /* Wait for the PLL to turn on. */
712
713 /* Now take the PHY out of Reset again */
714 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
715 tmslow |= SSB_TMSLOW_FGC;
716 tmslow &= ~B43legacy_TMSLOW_PHYRESET;
717 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
718 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
719 msleep(1);
720 tmslow &= ~SSB_TMSLOW_FGC;
721 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
722 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
723 msleep(1);
724
725 /* Turn Analog ON */
726 b43legacy_switch_analog(dev, 1);
727
728 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
729 macctl &= ~B43legacy_MACCTL_GMODE;
730 if (flags & B43legacy_TMSLOW_GMODE) {
731 macctl |= B43legacy_MACCTL_GMODE;
732 dev->phy.gmode = 1;
733 } else
734 dev->phy.gmode = 0;
735 macctl |= B43legacy_MACCTL_IHR_ENABLED;
736 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
737}
738
739static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
740{
741 u32 v0;
742 u32 v1;
743 u16 tmp;
744 struct b43legacy_txstatus stat;
745
746 while (1) {
747 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
748 if (!(v0 & 0x00000001))
749 break;
750 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
751
752 stat.cookie = (v0 >> 16);
753 stat.seq = (v1 & 0x0000FFFF);
754 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
755 tmp = (v0 & 0x0000FFFF);
756 stat.frame_count = ((tmp & 0xF000) >> 12);
757 stat.rts_count = ((tmp & 0x0F00) >> 8);
758 stat.supp_reason = ((tmp & 0x001C) >> 2);
759 stat.pm_indicated = !!(tmp & 0x0080);
760 stat.intermediate = !!(tmp & 0x0040);
761 stat.for_ampdu = !!(tmp & 0x0020);
762 stat.acked = !!(tmp & 0x0002);
763
764 b43legacy_handle_txstatus(dev, &stat);
765 }
766}
767
768static void drain_txstatus_queue(struct b43legacy_wldev *dev)
769{
770 u32 dummy;
771
772 if (dev->dev->id.revision < 5)
773 return;
774 /* Read all entries from the microcode TXstatus FIFO
775 * and throw them away.
776 */
777 while (1) {
778 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
779 if (!(dummy & 0x00000001))
780 break;
781 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
782 }
783}
784
785static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
786{
787 u32 val = 0;
788
789 val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
790 val <<= 16;
791 val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
792
793 return val;
794}
795
796static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
797{
798 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
799 (jssi & 0x0000FFFF));
800 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
801 (jssi & 0xFFFF0000) >> 16);
802}
803
804static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
805{
806 b43legacy_jssi_write(dev, 0x7F7F7F7F);
e78c9d28 807 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
75388acd 808 b43legacy_read32(dev,
e78c9d28 809 B43legacy_MMIO_MACCMD)
75388acd
LF		 810 | (1 << 4));
811 B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
812 dev->phy.channel);
813}
814
815static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
816{
817 /* Top half of Link Quality calculation. */
818
819 if (dev->noisecalc.calculation_running)
820 return;
821 dev->noisecalc.channel_at_start = dev->phy.channel;
822 dev->noisecalc.calculation_running = 1;
823 dev->noisecalc.nr_samples = 0;
824
825 b43legacy_generate_noise_sample(dev);
826}
827
828static void handle_irq_noise(struct b43legacy_wldev *dev)
829{
830 struct b43legacy_phy *phy = &dev->phy;
831 u16 tmp;
832 u8 noise[4];
833 u8 i;
834 u8 j;
835 s32 average;
836
837 /* Bottom half of Link Quality calculation. */
838
839 B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
840 if (dev->noisecalc.channel_at_start != phy->channel)
841 goto drop_calculation;
842 *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
843 if (noise[0] == 0x7F || noise[1] == 0x7F ||
844 noise[2] == 0x7F || noise[3] == 0x7F)
845 goto generate_new;
846
847 /* Get the noise samples. */
848 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
849 i = dev->noisecalc.nr_samples;
850 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
851 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
852 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
853 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
854 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
855 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
856 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
857 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
858 dev->noisecalc.nr_samples++;
859 if (dev->noisecalc.nr_samples == 8) {
860 /* Calculate the Link Quality by the noise samples. */
861 average = 0;
862 for (i = 0; i < 8; i++) {
863 for (j = 0; j < 4; j++)
864 average += dev->noisecalc.samples[i][j];
865 }
866 average /= (8 * 4);
867 average *= 125;
868 average += 64;
869 average /= 128;
870 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
871 0x40C);
872 tmp = (tmp / 128) & 0x1F;
873 if (tmp >= 8)
874 average += 2;
875 else
876 average -= 25;
877 if (tmp == 8)
878 average -= 72;
879 else
880 average -= 48;
881
882 dev->stats.link_noise = average;
883drop_calculation:
884 dev->noisecalc.calculation_running = 0;
885 return;
886 }
887generate_new:
888 b43legacy_generate_noise_sample(dev);
889}
890
891static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
892{
893 if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
894 /* TODO: PS TBTT */
895 } else {
896 if (1/*FIXME: the last PSpoll frame was sent successfully */)
897 b43legacy_power_saving_ctl_bits(dev, -1, -1);
898 }
899 dev->reg124_set_0x4 = 0;
900 if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
901 dev->reg124_set_0x4 = 1;
902}
903
904static void handle_irq_atim_end(struct b43legacy_wldev *dev)
905{
906 if (!dev->reg124_set_0x4) /*FIXME rename this variable*/
907 return;
e78c9d28
SB		 908 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
909 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
75388acd
LF		 910 | 0x4);
911}
912
913static void handle_irq_pmq(struct b43legacy_wldev *dev)
914{
915 u32 tmp;
916
917 /* TODO: AP mode. */
918
919 while (1) {
920 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
921 if (!(tmp & 0x00000008))
922 break;
923 }
924 /* 16bit write is odd, but correct. */
925 b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
926}
927
928static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
929 const u8 *data, u16 size,
930 u16 ram_offset,
931 u16 shm_size_offset, u8 rate)
932{
933 u32 i;
934 u32 tmp;
935 struct b43legacy_plcp_hdr4 plcp;
936
937 plcp.data = 0;
938 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
939 b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
940 ram_offset += sizeof(u32);
941 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
942 * So leave the first two bytes of the next write blank.
943 */
944 tmp = (u32)(data[0]) << 16;
945 tmp |= (u32)(data[1]) << 24;
946 b43legacy_ram_write(dev, ram_offset, tmp);
947 ram_offset += sizeof(u32);
948 for (i = 2; i < size; i += sizeof(u32)) {
949 tmp = (u32)(data[i + 0]);
950 if (i + 1 < size)
951 tmp |= (u32)(data[i + 1]) << 8;
952 if (i + 2 < size)
953 tmp |= (u32)(data[i + 2]) << 16;
954 if (i + 3 < size)
955 tmp |= (u32)(data[i + 3]) << 24;
956 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
957 }
958 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
959 size + sizeof(struct b43legacy_plcp_hdr6));
960}
961
962static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
963 u16 ram_offset,
964 u16 shm_size_offset, u8 rate)
965{
966 int len;
967 const u8 *data;
968
969 B43legacy_WARN_ON(!dev->cached_beacon);
970 len = min((size_t)dev->cached_beacon->len,
971 0x200 - sizeof(struct b43legacy_plcp_hdr6));
972 data = (const u8 *)(dev->cached_beacon->data);
973 b43legacy_write_template_common(dev, data,
974 len, ram_offset,
975 shm_size_offset, rate);
976}
977
978static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
979 u16 shm_offset, u16 size,
8318d78a 980 struct ieee80211_rate *rate)
75388acd
LF		 981{
982 struct b43legacy_plcp_hdr4 plcp;
983 u32 tmp;
984 __le16 dur;
985
986 plcp.data = 0;
8318d78a 987 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->bitrate);
75388acd 988 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 989 dev->wl->vif,
75388acd 990 size,
8318d78a 991 rate);
75388acd
LF		 992 /* Write PLCP in two parts and timing for packet transfer */
993 tmp = le32_to_cpu(plcp.data);
994 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
995 tmp & 0xFFFF);
996 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
997 tmp >> 16);
998 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
999 le16_to_cpu(dur));
1000}
1001
1002/* Instead of using custom probe response template, this function
1003 * just patches custom beacon template by:
1004 * 1) Changing packet type
1005 * 2) Patching duration field
1006 * 3) Stripping TIM
1007 */
1008static u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
8318d78a
JB		 1009 u16 *dest_size,
1010 struct ieee80211_rate *rate)
75388acd
LF		 1011{
1012 const u8 *src_data;
1013 u8 *dest_data;
1014 u16 src_size;
1015 u16 elem_size;
1016 u16 src_pos;
1017 u16 dest_pos;
1018 __le16 dur;
1019 struct ieee80211_hdr *hdr;
1020
1021 B43legacy_WARN_ON(!dev->cached_beacon);
1022 src_size = dev->cached_beacon->len;
1023 src_data = (const u8 *)dev->cached_beacon->data;
1024
1025 if (unlikely(src_size < 0x24)) {
1026 b43legacydbg(dev->wl, "b43legacy_generate_probe_resp: "
1027 "invalid beacon\n");
1028 return NULL;
1029 }
1030
1031 dest_data = kmalloc(src_size, GFP_ATOMIC);
1032 if (unlikely(!dest_data))
1033 return NULL;
1034
1035 /* 0x24 is offset of first variable-len Information-Element
1036 * in beacon frame.
1037 */
1038 memcpy(dest_data, src_data, 0x24);
1039 src_pos = 0x24;
1040 dest_pos = 0x24;
1041 for (; src_pos < src_size - 2; src_pos += elem_size) {
1042 elem_size = src_data[src_pos + 1] + 2;
1043 if (src_data[src_pos] != 0x05) { /* TIM */
1044 memcpy(dest_data + dest_pos, src_data + src_pos,
1045 elem_size);
1046 dest_pos += elem_size;
1047 }
1048 }
1049 *dest_size = dest_pos;
1050 hdr = (struct ieee80211_hdr *)dest_data;
1051
1052 /* Set the frame control. */
1053 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1054 IEEE80211_STYPE_PROBE_RESP);
1055 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1056 dev->wl->vif,
75388acd 1057 *dest_size,
8318d78a 1058 rate);
75388acd
LF		 1059 hdr->duration_id = dur;
1060
1061 return dest_data;
1062}
1063
1064static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1065 u16 ram_offset,
8318d78a
JB		 1066 u16 shm_size_offset,
1067 struct ieee80211_rate *rate)
75388acd
LF		 1068{
1069 u8 *probe_resp_data;
1070 u16 size;
1071
1072 B43legacy_WARN_ON(!dev->cached_beacon);
1073 size = dev->cached_beacon->len;
1074 probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1075 if (unlikely(!probe_resp_data))
1076 return;
1077
1078 /* Looks like PLCP headers plus packet timings are stored for
1079 * all possible basic rates
1080 */
1081 b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
8318d78a 1082 &b43legacy_b_ratetable[0]);
75388acd 1083 b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
8318d78a 1084 &b43legacy_b_ratetable[1]);
75388acd 1085 b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
8318d78a 1086 &b43legacy_b_ratetable[2]);
75388acd 1087 b43legacy_write_probe_resp_plcp(dev, 0x350, size,
8318d78a 1088 &b43legacy_b_ratetable[3]);
75388acd
LF		 1089
1090 size = min((size_t)size,
1091 0x200 - sizeof(struct b43legacy_plcp_hdr6));
1092 b43legacy_write_template_common(dev, probe_resp_data,
1093 size, ram_offset,
8318d78a 1094 shm_size_offset, rate->bitrate);
75388acd
LF		 1095 kfree(probe_resp_data);
1096}
1097
1098static int b43legacy_refresh_cached_beacon(struct b43legacy_wldev *dev,
1099 struct sk_buff *beacon)
1100{
1101 if (dev->cached_beacon)
1102 kfree_skb(dev->cached_beacon);
1103 dev->cached_beacon = beacon;
1104
1105 return 0;
1106}
1107
1108static void b43legacy_update_templates(struct b43legacy_wldev *dev)
1109{
1110 u32 status;
1111
1112 B43legacy_WARN_ON(!dev->cached_beacon);
1113
1114 b43legacy_write_beacon_template(dev, 0x68, 0x18,
1115 B43legacy_CCK_RATE_1MB);
1116 b43legacy_write_beacon_template(dev, 0x468, 0x1A,
1117 B43legacy_CCK_RATE_1MB);
1118 b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
8318d78a 1119 &b43legacy_b_ratetable[0]);
75388acd 1120
e78c9d28 1121 status = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
75388acd 1122 status |= 0x03;
e78c9d28 1123 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, status);
75388acd
LF		 1124}
1125
1126static void b43legacy_refresh_templates(struct b43legacy_wldev *dev,
1127 struct sk_buff *beacon)
1128{
1129 int err;
1130
1131 err = b43legacy_refresh_cached_beacon(dev, beacon);
1132 if (unlikely(err))
1133 return;
1134 b43legacy_update_templates(dev);
1135}
1136
1137static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
1138 const u8 *ssid, u8 ssid_len)
1139{
1140 u32 tmp;
1141 u16 i;
1142 u16 len;
1143
1144 len = min((u16)ssid_len, (u16)0x100);
1145 for (i = 0; i < len; i += sizeof(u32)) {
1146 tmp = (u32)(ssid[i + 0]);
1147 if (i + 1 < len)
1148 tmp |= (u32)(ssid[i + 1]) << 8;
1149 if (i + 2 < len)
1150 tmp |= (u32)(ssid[i + 2]) << 16;
1151 if (i + 3 < len)
1152 tmp |= (u32)(ssid[i + 3]) << 24;
1153 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
1154 0x380 + i, tmp);
1155 }
1156 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1157 0x48, len);
1158}
1159
1160static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1161 u16 beacon_int)
1162{
1163 b43legacy_time_lock(dev);
1164 if (dev->dev->id.revision >= 3)
1165 b43legacy_write32(dev, 0x188, (beacon_int << 16));
1166 else {
1167 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1168 b43legacy_write16(dev, 0x610, beacon_int);
1169 }
1170 b43legacy_time_unlock(dev);
1171}
1172
1173static void handle_irq_beacon(struct b43legacy_wldev *dev)
1174{
1175 u32 status;
1176
1177 if (!b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1178 return;
1179
1180 dev->irq_savedstate &= ~B43legacy_IRQ_BEACON;
e78c9d28 1181 status = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
75388acd
LF		 1182
1183 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1184 /* ACK beacon IRQ. */
1185 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1186 B43legacy_IRQ_BEACON);
1187 dev->irq_savedstate |= B43legacy_IRQ_BEACON;
1188 if (dev->cached_beacon)
1189 kfree_skb(dev->cached_beacon);
1190 dev->cached_beacon = NULL;
1191 return;
1192 }
1193 if (!(status & 0x1)) {
1194 b43legacy_write_beacon_template(dev, 0x68, 0x18,
1195 B43legacy_CCK_RATE_1MB);
1196 status |= 0x1;
e78c9d28 1197 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
75388acd
LF		 1198 status);
1199 }
1200 if (!(status & 0x2)) {
1201 b43legacy_write_beacon_template(dev, 0x468, 0x1A,
1202 B43legacy_CCK_RATE_1MB);
1203 status |= 0x2;
e78c9d28 1204 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
75388acd
LF		 1205 status);
1206 }
1207}
1208
1209static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1210{
1211}
1212
1213/* Interrupt handler bottom-half */
1214static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1215{
1216 u32 reason;
1217 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1218 u32 merged_dma_reason = 0;
1219 int i;
75388acd
LF		 1220 unsigned long flags;
1221
1222 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1223
1224 B43legacy_WARN_ON(b43legacy_status(dev) <
1225 B43legacy_STAT_INITIALIZED);
1226
1227 reason = dev->irq_reason;
1228 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1229 dma_reason[i] = dev->dma_reason[i];
1230 merged_dma_reason |= dma_reason[i];
1231 }
1232
1233 if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1234 b43legacyerr(dev->wl, "MAC transmission error\n");
1235
a293ee99 1236 if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
75388acd 1237 b43legacyerr(dev->wl, "PHY transmission error\n");
a293ee99
SB		 1238 rmb();
1239 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1240 b43legacyerr(dev->wl, "Too many PHY TX errors, "
1241 "restarting the controller\n");
1242 b43legacy_controller_restart(dev, "PHY TX errors");
1243 }
1244 }
75388acd
LF		 1245
1246 if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1247 B43legacy_DMAIRQ_NONFATALMASK))) {
1248 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1249 b43legacyerr(dev->wl, "Fatal DMA error: "
1250 "0x%08X, 0x%08X, 0x%08X, "
1251 "0x%08X, 0x%08X, 0x%08X\n",
1252 dma_reason[0], dma_reason[1],
1253 dma_reason[2], dma_reason[3],
1254 dma_reason[4], dma_reason[5]);
1255 b43legacy_controller_restart(dev, "DMA error");
1256 mmiowb();
1257 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1258 return;
1259 }
1260 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1261 b43legacyerr(dev->wl, "DMA error: "
1262 "0x%08X, 0x%08X, 0x%08X, "
1263 "0x%08X, 0x%08X, 0x%08X\n",
1264 dma_reason[0], dma_reason[1],
1265 dma_reason[2], dma_reason[3],
1266 dma_reason[4], dma_reason[5]);
1267 }
1268
1269 if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1270 handle_irq_ucode_debug(dev);
1271 if (reason & B43legacy_IRQ_TBTT_INDI)
1272 handle_irq_tbtt_indication(dev);
1273 if (reason & B43legacy_IRQ_ATIM_END)
1274 handle_irq_atim_end(dev);
1275 if (reason & B43legacy_IRQ_BEACON)
1276 handle_irq_beacon(dev);
1277 if (reason & B43legacy_IRQ_PMQ)
1278 handle_irq_pmq(dev);
1279 if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1280 ;/*TODO*/
1281 if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1282 handle_irq_noise(dev);
1283
1284 /* Check the DMA reason registers for received data. */
1285 if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1286 if (b43legacy_using_pio(dev))
1287 b43legacy_pio_rx(dev->pio.queue0);
1288 else
1289 b43legacy_dma_rx(dev->dma.rx_ring0);
75388acd
LF		 1290 }
1291 B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1292 B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1293 if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1294 if (b43legacy_using_pio(dev))
1295 b43legacy_pio_rx(dev->pio.queue3);
1296 else
1297 b43legacy_dma_rx(dev->dma.rx_ring3);
75388acd
LF		 1298 }
1299 B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1300 B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1301
ba48f7bb 1302 if (reason & B43legacy_IRQ_TX_OK)
75388acd 1303 handle_irq_transmit_status(dev);
75388acd 1304
75388acd
LF		 1305 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1306 mmiowb();
1307 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1308}
1309
1310static void pio_irq_workaround(struct b43legacy_wldev *dev,
1311 u16 base, int queueidx)
1312{
1313 u16 rxctl;
1314
1315 rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1316 if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1317 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1318 else
1319 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1320}
1321
1322static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1323{
1324 if (b43legacy_using_pio(dev) &&
1325 (dev->dev->id.revision < 3) &&
1326 (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1327 /* Apply a PIO specific workaround to the dma_reasons */
1328 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1329 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1330 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1331 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1332 }
1333
1334 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1335
1336 b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1337 dev->dma_reason[0]);
1338 b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1339 dev->dma_reason[1]);
1340 b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1341 dev->dma_reason[2]);
1342 b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1343 dev->dma_reason[3]);
1344 b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1345 dev->dma_reason[4]);
1346 b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1347 dev->dma_reason[5]);
1348}
1349
1350/* Interrupt handler top-half */
1351static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1352{
1353 irqreturn_t ret = IRQ_NONE;
1354 struct b43legacy_wldev *dev = dev_id;
1355 u32 reason;
1356
1357 if (!dev)
1358 return IRQ_NONE;
1359
1360 spin_lock(&dev->wl->irq_lock);
1361
1362 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
1363 goto out;
1364 reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1365 if (reason == 0xffffffff) /* shared IRQ */
1366 goto out;
1367 ret = IRQ_HANDLED;
1368 reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
1369 if (!reason)
1370 goto out;
1371
1372 dev->dma_reason[0] = b43legacy_read32(dev,
1373 B43legacy_MMIO_DMA0_REASON)
1374 & 0x0001DC00;
1375 dev->dma_reason[1] = b43legacy_read32(dev,
1376 B43legacy_MMIO_DMA1_REASON)
1377 & 0x0000DC00;
1378 dev->dma_reason[2] = b43legacy_read32(dev,
1379 B43legacy_MMIO_DMA2_REASON)
1380 & 0x0000DC00;
1381 dev->dma_reason[3] = b43legacy_read32(dev,
1382 B43legacy_MMIO_DMA3_REASON)
1383 & 0x0001DC00;
1384 dev->dma_reason[4] = b43legacy_read32(dev,
1385 B43legacy_MMIO_DMA4_REASON)
1386 & 0x0000DC00;
1387 dev->dma_reason[5] = b43legacy_read32(dev,
1388 B43legacy_MMIO_DMA5_REASON)
1389 & 0x0000DC00;
1390
1391 b43legacy_interrupt_ack(dev, reason);
1392 /* disable all IRQs. They are enabled again in the bottom half. */
1393 dev->irq_savedstate = b43legacy_interrupt_disable(dev,
1394 B43legacy_IRQ_ALL);
1395 /* save the reason code and call our bottom half. */
1396 dev->irq_reason = reason;
1397 tasklet_schedule(&dev->isr_tasklet);
1398out:
1399 mmiowb();
1400 spin_unlock(&dev->wl->irq_lock);
1401
1402 return ret;
1403}
1404
1405static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1406{
1407 release_firmware(dev->fw.ucode);
1408 dev->fw.ucode = NULL;
1409 release_firmware(dev->fw.pcm);
1410 dev->fw.pcm = NULL;
1411 release_firmware(dev->fw.initvals);
1412 dev->fw.initvals = NULL;
1413 release_firmware(dev->fw.initvals_band);
1414 dev->fw.initvals_band = NULL;
1415}
1416
1417static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1418{
1419 b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
354807e0 1420 "Drivers/b43#devicefirmware "
75388acd
LF		 1421 "and download the correct firmware (version 3).\n");
1422}
1423
1424static int do_request_fw(struct b43legacy_wldev *dev,
1425 const char *name,
1426 const struct firmware **fw)
1427{
1428 char path[sizeof(modparam_fwpostfix) + 32];
1429 struct b43legacy_fw_header *hdr;
1430 u32 size;
1431 int err;
1432
1433 if (!name)
1434 return 0;
1435
1436 snprintf(path, ARRAY_SIZE(path),
1437 "b43legacy%s/%s.fw",
1438 modparam_fwpostfix, name);
1439 err = request_firmware(fw, path, dev->dev->dev);
1440 if (err) {
1441 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1442 "or load failed.\n", path);
1443 return err;
1444 }
1445 if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1446 goto err_format;
1447 hdr = (struct b43legacy_fw_header *)((*fw)->data);
1448 switch (hdr->type) {
1449 case B43legacy_FW_TYPE_UCODE:
1450 case B43legacy_FW_TYPE_PCM:
1451 size = be32_to_cpu(hdr->size);
1452 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1453 goto err_format;
1454 /* fallthrough */
1455 case B43legacy_FW_TYPE_IV:
1456 if (hdr->ver != 1)
1457 goto err_format;
1458 break;
1459 default:
1460 goto err_format;
1461 }
1462
1463 return err;
1464
1465err_format:
1466 b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1467 return -EPROTO;
1468}
1469
1470static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1471{
1472 struct b43legacy_firmware *fw = &dev->fw;
1473 const u8 rev = dev->dev->id.revision;
1474 const char *filename;
1475 u32 tmshigh;
1476 int err;
1477
1478 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1479 if (!fw->ucode) {
1480 if (rev == 2)
1481 filename = "ucode2";
1482 else if (rev == 4)
1483 filename = "ucode4";
1484 else
1485 filename = "ucode5";
1486 err = do_request_fw(dev, filename, &fw->ucode);
1487 if (err)
1488 goto err_load;
1489 }
1490 if (!fw->pcm) {
1491 if (rev < 5)
1492 filename = "pcm4";
1493 else
1494 filename = "pcm5";
1495 err = do_request_fw(dev, filename, &fw->pcm);
1496 if (err)
1497 goto err_load;
1498 }
1499 if (!fw->initvals) {
1500 switch (dev->phy.type) {
1501 case B43legacy_PHYTYPE_G:
1502 if ((rev >= 5) && (rev <= 10))
1503 filename = "b0g0initvals5";
1504 else if (rev == 2 || rev == 4)
1505 filename = "b0g0initvals2";
1506 else
1507 goto err_no_initvals;
1508 break;
1509 default:
1510 goto err_no_initvals;
1511 }
1512 err = do_request_fw(dev, filename, &fw->initvals);
1513 if (err)
1514 goto err_load;
1515 }
1516 if (!fw->initvals_band) {
1517 switch (dev->phy.type) {
1518 case B43legacy_PHYTYPE_G:
1519 if ((rev >= 5) && (rev <= 10))
1520 filename = "b0g0bsinitvals5";
1521 else if (rev >= 11)
1522 filename = NULL;
1523 else if (rev == 2 || rev == 4)
1524 filename = NULL;
1525 else
1526 goto err_no_initvals;
1527 break;
1528 default:
1529 goto err_no_initvals;
1530 }
1531 err = do_request_fw(dev, filename, &fw->initvals_band);
1532 if (err)
1533 goto err_load;
1534 }
1535
1536 return 0;
1537
1538err_load:
1539 b43legacy_print_fw_helptext(dev->wl);
1540 goto error;
1541
1542err_no_initvals:
1543 err = -ENODEV;
1544 b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1545 "core rev %u\n", dev->phy.type, rev);
1546 goto error;
1547
1548error:
1549 b43legacy_release_firmware(dev);
1550 return err;
1551}
1552
1553static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1554{
1555 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1556 const __be32 *data;
1557 unsigned int i;
1558 unsigned int len;
1559 u16 fwrev;
1560 u16 fwpatch;
1561 u16 fwdate;
1562 u16 fwtime;
e78c9d28 1563 u32 tmp, macctl;
75388acd
LF		 1564 int err = 0;
1565
e78c9d28
SB		 1566 /* Jump the microcode PSM to offset 0 */
1567 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1568 B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1569 macctl |= B43legacy_MACCTL_PSM_JMP0;
1570 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1571 /* Zero out all microcode PSM registers and shared memory. */
1572 for (i = 0; i < 64; i++)
1573 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1574 for (i = 0; i < 4096; i += 2)
1575 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1576
75388acd
LF		 1577 /* Upload Microcode. */
1578 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1579 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1580 b43legacy_shm_control_word(dev,
1581 B43legacy_SHM_UCODE |
1582 B43legacy_SHM_AUTOINC_W,
1583 0x0000);
1584 for (i = 0; i < len; i++) {
1585 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1586 be32_to_cpu(data[i]));
1587 udelay(10);
1588 }
1589
1590 if (dev->fw.pcm) {
1591 /* Upload PCM data. */
1592 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1593 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1594 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1595 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1596 /* No need for autoinc bit in SHM_HW */
1597 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1598 for (i = 0; i < len; i++) {
1599 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1600 be32_to_cpu(data[i]));
1601 udelay(10);
1602 }
1603 }
1604
1605 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1606 B43legacy_IRQ_ALL);
e78c9d28
SB		 1607
1608 /* Start the microcode PSM */
1609 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1610 macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1611 macctl |= B43legacy_MACCTL_PSM_RUN;
1612 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 1613
1614 /* Wait for the microcode to load and respond */
1615 i = 0;
1616 while (1) {
1617 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1618 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1619 break;
1620 i++;
1621 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1622 b43legacyerr(dev->wl, "Microcode not responding\n");
1623 b43legacy_print_fw_helptext(dev->wl);
1624 err = -ENODEV;
e78c9d28
SB		 1625 goto error;
1626 }
1627 msleep_interruptible(50);
1628 if (signal_pending(current)) {
1629 err = -EINTR;
1630 goto error;
75388acd 1631 }
75388acd
LF		 1632 }
1633 /* dummy read follows */
1634 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1635
1636 /* Get and check the revisions. */
1637 fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1638 B43legacy_SHM_SH_UCODEREV);
1639 fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1640 B43legacy_SHM_SH_UCODEPATCH);
1641 fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1642 B43legacy_SHM_SH_UCODEDATE);
1643 fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1644 B43legacy_SHM_SH_UCODETIME);
1645
1646 if (fwrev > 0x128) {
1647 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1648 " Only firmware from binary drivers version 3.x"
1649 " is supported. You must change your firmware"
1650 " files.\n");
1651 b43legacy_print_fw_helptext(dev->wl);
75388acd 1652 err = -EOPNOTSUPP;
e78c9d28 1653 goto error;
75388acd 1654 }
cfbc35b6
SB		 1655 b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1656 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1657 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1658 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1659 fwtime & 0x1F);
75388acd
LF		 1660
1661 dev->fw.rev = fwrev;
1662 dev->fw.patch = fwpatch;
1663
e78c9d28
SB		 1664 return 0;
1665
1666error:
1667 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1668 macctl &= ~B43legacy_MACCTL_PSM_RUN;
1669 macctl |= B43legacy_MACCTL_PSM_JMP0;
1670 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1671
75388acd
LF		 1672 return err;
1673}
1674
1675static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1676 const struct b43legacy_iv *ivals,
1677 size_t count,
1678 size_t array_size)
1679{
1680 const struct b43legacy_iv *iv;
1681 u16 offset;
1682 size_t i;
1683 bool bit32;
1684
1685 BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1686 iv = ivals;
1687 for (i = 0; i < count; i++) {
1688 if (array_size < sizeof(iv->offset_size))
1689 goto err_format;
1690 array_size -= sizeof(iv->offset_size);
1691 offset = be16_to_cpu(iv->offset_size);
1692 bit32 = !!(offset & B43legacy_IV_32BIT);
1693 offset &= B43legacy_IV_OFFSET_MASK;
1694 if (offset >= 0x1000)
1695 goto err_format;
1696 if (bit32) {
1697 u32 value;
1698
1699 if (array_size < sizeof(iv->data.d32))
1700 goto err_format;
1701 array_size -= sizeof(iv->data.d32);
1702
1703 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1704 b43legacy_write32(dev, offset, value);
1705
1706 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1707 sizeof(__be16) +
1708 sizeof(__be32));
1709 } else {
1710 u16 value;
1711
1712 if (array_size < sizeof(iv->data.d16))
1713 goto err_format;
1714 array_size -= sizeof(iv->data.d16);
1715
1716 value = be16_to_cpu(iv->data.d16);
1717 b43legacy_write16(dev, offset, value);
1718
1719 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1720 sizeof(__be16) +
1721 sizeof(__be16));
1722 }
1723 }
1724 if (array_size)
1725 goto err_format;
1726
1727 return 0;
1728
1729err_format:
1730 b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1731 b43legacy_print_fw_helptext(dev->wl);
1732
1733 return -EPROTO;
1734}
1735
1736static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1737{
1738 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1739 const struct b43legacy_fw_header *hdr;
1740 struct b43legacy_firmware *fw = &dev->fw;
1741 const struct b43legacy_iv *ivals;
1742 size_t count;
1743 int err;
1744
1745 hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1746 ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1747 count = be32_to_cpu(hdr->size);
1748 err = b43legacy_write_initvals(dev, ivals, count,
1749 fw->initvals->size - hdr_len);
1750 if (err)
1751 goto out;
1752 if (fw->initvals_band) {
1753 hdr = (const struct b43legacy_fw_header *)
1754 (fw->initvals_band->data);
1755 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1756 + hdr_len);
1757 count = be32_to_cpu(hdr->size);
1758 err = b43legacy_write_initvals(dev, ivals, count,
1759 fw->initvals_band->size - hdr_len);
1760 if (err)
1761 goto out;
1762 }
1763out:
1764
1765 return err;
1766}
1767
1768/* Initialize the GPIOs
1769 * http://bcm-specs.sipsolutions.net/GPIO
1770 */
1771static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1772{
1773 struct ssb_bus *bus = dev->dev->bus;
1774 struct ssb_device *gpiodev, *pcidev = NULL;
1775 u32 mask;
1776 u32 set;
1777
e78c9d28 1778 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1779 b43legacy_read32(dev,
e78c9d28 1780 B43legacy_MMIO_MACCTL)
75388acd
LF		 1781 & 0xFFFF3FFF);
1782
75388acd
LF		 1783 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1784 b43legacy_read16(dev,
1785 B43legacy_MMIO_GPIO_MASK)
1786 | 0x000F);
1787
1788 mask = 0x0000001F;
1789 set = 0x0000000F;
1790 if (dev->dev->bus->chip_id == 0x4301) {
1791 mask |= 0x0060;
1792 set |= 0x0060;
1793 }
7797aa38 1794 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
75388acd
LF		 1795 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1796 b43legacy_read16(dev,
1797 B43legacy_MMIO_GPIO_MASK)
1798 | 0x0200);
1799 mask |= 0x0200;
1800 set |= 0x0200;
1801 }
1802 if (dev->dev->id.revision >= 2)
1803 mask |= 0x0010; /* FIXME: This is redundant. */
1804
1805#ifdef CONFIG_SSB_DRIVER_PCICORE
1806 pcidev = bus->pcicore.dev;
1807#endif
1808 gpiodev = bus->chipco.dev ? : pcidev;
1809 if (!gpiodev)
1810 return 0;
1811 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1812 (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1813 & mask) | set);
1814
1815 return 0;
1816}
1817
1818/* Turn off all GPIO stuff. Call this on module unload, for example. */
1819static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1820{
1821 struct ssb_bus *bus = dev->dev->bus;
1822 struct ssb_device *gpiodev, *pcidev = NULL;
1823
1824#ifdef CONFIG_SSB_DRIVER_PCICORE
1825 pcidev = bus->pcicore.dev;
1826#endif
1827 gpiodev = bus->chipco.dev ? : pcidev;
1828 if (!gpiodev)
1829 return;
1830 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1831}
1832
1833/* http://bcm-specs.sipsolutions.net/EnableMac */
1834void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1835{
1836 dev->mac_suspended--;
1837 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1838 B43legacy_WARN_ON(irqs_disabled());
75388acd 1839 if (dev->mac_suspended == 0) {
e78c9d28 1840 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1841 b43legacy_read32(dev,
e78c9d28
SB		 1842 B43legacy_MMIO_MACCTL)
1843 | B43legacy_MACCTL_ENABLED);
75388acd
LF		 1844 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1845 B43legacy_IRQ_MAC_SUSPENDED);
1846 /* the next two are dummy reads */
e78c9d28 1847 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
75388acd
LF		 1848 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1849 b43legacy_power_saving_ctl_bits(dev, -1, -1);
f34eb692
LF		 1850
1851 /* Re-enable IRQs. */
1852 spin_lock_irq(&dev->wl->irq_lock);
1853 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1854 spin_unlock_irq(&dev->wl->irq_lock);
75388acd
LF		 1855 }
1856}
1857
1858/* http://bcm-specs.sipsolutions.net/SuspendMAC */
1859void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1860{
1861 int i;
1862 u32 tmp;
1863
f34eb692
LF		 1864 might_sleep();
1865 B43legacy_WARN_ON(irqs_disabled());
75388acd 1866 B43legacy_WARN_ON(dev->mac_suspended < 0);
f34eb692 1867
75388acd 1868 if (dev->mac_suspended == 0) {
f34eb692
LF		 1869 /* Mask IRQs before suspending MAC. Otherwise
1870 * the MAC stays busy and won't suspend. */
1871 spin_lock_irq(&dev->wl->irq_lock);
1872 tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
1873 spin_unlock_irq(&dev->wl->irq_lock);
1874 b43legacy_synchronize_irq(dev);
1875 dev->irq_savedstate = tmp;
1876
75388acd 1877 b43legacy_power_saving_ctl_bits(dev, -1, 1);
e78c9d28 1878 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
75388acd 1879 b43legacy_read32(dev,
e78c9d28
SB		 1880 B43legacy_MMIO_MACCTL)
1881 & ~B43legacy_MACCTL_ENABLED);
75388acd 1882 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
f34eb692 1883 for (i = 40; i; i--) {
75388acd
LF		 1884 tmp = b43legacy_read32(dev,
1885 B43legacy_MMIO_GEN_IRQ_REASON);
1886 if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1887 goto out;
f34eb692 1888 msleep(1);
75388acd
LF		 1889 }
1890 b43legacyerr(dev->wl, "MAC suspend failed\n");
1891 }
1892out:
1893 dev->mac_suspended++;
1894}
1895
1896static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1897{
1898 struct b43legacy_wl *wl = dev->wl;
1899 u32 ctl;
1900 u16 cfp_pretbtt;
1901
1902 ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1903 /* Reset status to STA infrastructure mode. */
1904 ctl &= ~B43legacy_MACCTL_AP;
1905 ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1906 ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1907 ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1908 ctl &= ~B43legacy_MACCTL_PROMISC;
4150c572 1909 ctl &= ~B43legacy_MACCTL_BEACPROMISC;
75388acd
LF		 1910 ctl |= B43legacy_MACCTL_INFRA;
1911
4150c572
JB		 1912 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
1913 ctl |= B43legacy_MACCTL_AP;
1914 else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
1915 ctl &= ~B43legacy_MACCTL_INFRA;
1916
1917 if (wl->filter_flags & FIF_CONTROL)
75388acd 1918 ctl |= B43legacy_MACCTL_KEEP_CTL;
4150c572
JB		 1919 if (wl->filter_flags & FIF_FCSFAIL)
1920 ctl |= B43legacy_MACCTL_KEEP_BAD;
1921 if (wl->filter_flags & FIF_PLCPFAIL)
1922 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1923 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
75388acd 1924 ctl |= B43legacy_MACCTL_PROMISC;
4150c572
JB		 1925 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1926 ctl |= B43legacy_MACCTL_BEACPROMISC;
1927
75388acd
LF		 1928 /* Workaround: On old hardware the HW-MAC-address-filter
1929 * doesn't work properly, so always run promisc in filter
1930 * it in software. */
1931 if (dev->dev->id.revision <= 4)
1932 ctl |= B43legacy_MACCTL_PROMISC;
1933
1934 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
1935
1936 cfp_pretbtt = 2;
1937 if ((ctl & B43legacy_MACCTL_INFRA) &&
1938 !(ctl & B43legacy_MACCTL_AP)) {
1939 if (dev->dev->bus->chip_id == 0x4306 &&
1940 dev->dev->bus->chip_rev == 3)
1941 cfp_pretbtt = 100;
1942 else
1943 cfp_pretbtt = 50;
1944 }
1945 b43legacy_write16(dev, 0x612, cfp_pretbtt);
1946}
1947
1948static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
1949 u16 rate,
1950 int is_ofdm)
1951{
1952 u16 offset;
1953
1954 if (is_ofdm) {
1955 offset = 0x480;
1956 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
1957 } else {
1958 offset = 0x4C0;
1959 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
1960 }
1961 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
1962 b43legacy_shm_read16(dev,
1963 B43legacy_SHM_SHARED, offset));
1964}
1965
1966static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
1967{
1968 switch (dev->phy.type) {
1969 case B43legacy_PHYTYPE_G:
1970 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
1971 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
1972 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
1973 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
1974 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
1975 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
1976 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
1977 /* fallthrough */
1978 case B43legacy_PHYTYPE_B:
1979 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
1980 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
1981 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
1982 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
1983 break;
1984 default:
1985 B43legacy_BUG_ON(1);
1986 }
1987}
1988
1989/* Set the TX-Antenna for management frames sent by firmware. */
1990static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
1991 int antenna)
1992{
1993 u16 ant = 0;
1994 u16 tmp;
1995
1996 switch (antenna) {
1997 case B43legacy_ANTENNA0:
1998 ant |= B43legacy_TX4_PHY_ANT0;
1999 break;
2000 case B43legacy_ANTENNA1:
2001 ant |= B43legacy_TX4_PHY_ANT1;
2002 break;
2003 case B43legacy_ANTENNA_AUTO:
2004 ant |= B43legacy_TX4_PHY_ANTLAST;
2005 break;
2006 default:
2007 B43legacy_BUG_ON(1);
2008 }
2009
2010 /* FIXME We also need to set the other flags of the PHY control
2011 * field somewhere. */
2012
2013 /* For Beacons */
2014 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2015 B43legacy_SHM_SH_BEACPHYCTL);
2016 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2017 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2018 B43legacy_SHM_SH_BEACPHYCTL, tmp);
2019 /* For ACK/CTS */
2020 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2021 B43legacy_SHM_SH_ACKCTSPHYCTL);
2022 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2023 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2024 B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2025 /* For Probe Resposes */
2026 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2027 B43legacy_SHM_SH_PRPHYCTL);
2028 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2029 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2030 B43legacy_SHM_SH_PRPHYCTL, tmp);
2031}
2032
2033/* This is the opposite of b43legacy_chip_init() */
2034static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2035{
93bb7f3a 2036 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 2037 b43legacy_gpio_cleanup(dev);
2038 /* firmware is released later */
2039}
2040
2041/* Initialize the chip
2042 * http://bcm-specs.sipsolutions.net/ChipInit
2043 */
2044static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2045{
2046 struct b43legacy_phy *phy = &dev->phy;
2047 int err;
2048 int tmp;
e78c9d28 2049 u32 value32, macctl;
75388acd
LF		 2050 u16 value16;
2051
e78c9d28
SB		 2052 /* Initialize the MAC control */
2053 macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2054 if (dev->phy.gmode)
2055 macctl |= B43legacy_MACCTL_GMODE;
2056 macctl |= B43legacy_MACCTL_INFRA;
2057 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
75388acd
LF		 2058
2059 err = b43legacy_request_firmware(dev);
2060 if (err)
2061 goto out;
2062 err = b43legacy_upload_microcode(dev);
2063 if (err)
2064 goto out; /* firmware is released later */
2065
2066 err = b43legacy_gpio_init(dev);
2067 if (err)
2068 goto out; /* firmware is released later */
ba48f7bb 2069
75388acd
LF		 2070 err = b43legacy_upload_initvals(dev);
2071 if (err)
4ad36d78 2072 goto err_gpio_clean;
75388acd 2073 b43legacy_radio_turn_on(dev);
75388acd
LF		 2074
2075 b43legacy_write16(dev, 0x03E6, 0x0000);
2076 err = b43legacy_phy_init(dev);
2077 if (err)
2078 goto err_radio_off;
2079
2080 /* Select initial Interference Mitigation. */
2081 tmp = phy->interfmode;
2082 phy->interfmode = B43legacy_INTERFMODE_NONE;
2083 b43legacy_radio_set_interference_mitigation(dev, tmp);
2084
2085 b43legacy_phy_set_antenna_diversity(dev);
2086 b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2087
2088 if (phy->type == B43legacy_PHYTYPE_B) {
2089 value16 = b43legacy_read16(dev, 0x005E);
2090 value16 |= 0x0004;
2091 b43legacy_write16(dev, 0x005E, value16);
2092 }
2093 b43legacy_write32(dev, 0x0100, 0x01000000);
2094 if (dev->dev->id.revision < 5)
2095 b43legacy_write32(dev, 0x010C, 0x01000000);
2096
e78c9d28
SB		 2097 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2098 value32 &= ~B43legacy_MACCTL_INFRA;
2099 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2100 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2101 value32 |= B43legacy_MACCTL_INFRA;
2102 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
75388acd 2103
75388acd
LF		 2104 if (b43legacy_using_pio(dev)) {
2105 b43legacy_write32(dev, 0x0210, 0x00000100);
2106 b43legacy_write32(dev, 0x0230, 0x00000100);
2107 b43legacy_write32(dev, 0x0250, 0x00000100);
2108 b43legacy_write32(dev, 0x0270, 0x00000100);
2109 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2110 0x0000);
2111 }
2112
2113 /* Probe Response Timeout value */
2114 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2115 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2116
2117 /* Initially set the wireless operation mode. */
2118 b43legacy_adjust_opmode(dev);
2119
2120 if (dev->dev->id.revision < 3) {
2121 b43legacy_write16(dev, 0x060E, 0x0000);
2122 b43legacy_write16(dev, 0x0610, 0x8000);
2123 b43legacy_write16(dev, 0x0604, 0x0000);
2124 b43legacy_write16(dev, 0x0606, 0x0200);
2125 } else {
2126 b43legacy_write32(dev, 0x0188, 0x80000000);
2127 b43legacy_write32(dev, 0x018C, 0x02000000);
2128 }
2129 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2130 b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2131 b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2132 b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2133 b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2134 b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2135 b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2136
2137 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2138 value32 |= 0x00100000;
2139 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2140
2141 b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2142 dev->dev->bus->chipco.fast_pwrup_delay);
2143
a293ee99
SB		 2144 /* PHY TX errors counter. */
2145 atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2146
75388acd
LF		 2147 B43legacy_WARN_ON(err != 0);
2148 b43legacydbg(dev->wl, "Chip initialized\n");
2149out:
2150 return err;
2151
2152err_radio_off:
93bb7f3a 2153 b43legacy_radio_turn_off(dev, 1);
4ad36d78 2154err_gpio_clean:
75388acd
LF		 2155 b43legacy_gpio_cleanup(dev);
2156 goto out;
2157}
2158
2159static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2160{
2161 struct b43legacy_phy *phy = &dev->phy;
2162
2163 if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2164 return;
2165
2166 b43legacy_mac_suspend(dev);
2167 b43legacy_phy_lo_g_measure(dev);
2168 b43legacy_mac_enable(dev);
2169}
2170
2171static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2172{
2173 b43legacy_phy_lo_mark_all_unused(dev);
7797aa38 2174 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
75388acd
LF		 2175 b43legacy_mac_suspend(dev);
2176 b43legacy_calc_nrssi_slope(dev);
2177 b43legacy_mac_enable(dev);
2178 }
2179}
2180
2181static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2182{
2183 /* Update device statistics. */
2184 b43legacy_calculate_link_quality(dev);
2185}
2186
2187static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2188{
2189 b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
a293ee99
SB		 2190
2191 atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2192 wmb();
75388acd
LF		 2193}
2194
75388acd
LF		 2195static void do_periodic_work(struct b43legacy_wldev *dev)
2196{
2197 unsigned int state;
2198
2199 state = dev->periodic_state;
6be50837 2200 if (state % 8 == 0)
75388acd 2201 b43legacy_periodic_every120sec(dev);
6be50837 2202 if (state % 4 == 0)
75388acd 2203 b43legacy_periodic_every60sec(dev);
6be50837 2204 if (state % 2 == 0)
75388acd 2205 b43legacy_periodic_every30sec(dev);
6be50837 2206 b43legacy_periodic_every15sec(dev);
75388acd
LF		 2207}
2208
f34eb692
LF		 2209/* Periodic work locking policy:
2210 * The whole periodic work handler is protected by
2211 * wl->mutex. If another lock is needed somewhere in the
2212 * pwork callchain, it's aquired in-place, where it's needed.
75388acd 2213 */
75388acd
LF		 2214static void b43legacy_periodic_work_handler(struct work_struct *work)
2215{
f34eb692
LF		 2216 struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2217 periodic_work.work);
2218 struct b43legacy_wl *wl = dev->wl;
75388acd 2219 unsigned long delay;
75388acd 2220
f34eb692 2221 mutex_lock(&wl->mutex);
75388acd
LF		 2222
2223 if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2224 goto out;
2225 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2226 goto out_requeue;
2227
f34eb692 2228 do_periodic_work(dev);
75388acd 2229
75388acd
LF		 2230 dev->periodic_state++;
2231out_requeue:
2232 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2233 delay = msecs_to_jiffies(50);
2234 else
6be50837 2235 delay = round_jiffies_relative(HZ * 15);
f34eb692 2236 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
75388acd 2237out:
f34eb692 2238 mutex_unlock(&wl->mutex);
75388acd
LF		 2239}
2240
2241static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2242{
2243 struct delayed_work *work = &dev->periodic_work;
2244
2245 dev->periodic_state = 0;
2246 INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2247 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2248}
2249
2250/* Validate access to the chip (SHM) */
2251static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2252{
2253 u32 value;
2254 u32 shm_backup;
2255
2256 shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2257 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2258 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2259 0xAA5555AA)
2260 goto error;
2261 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2262 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2263 0x55AAAA55)
2264 goto error;
2265 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2266
2267 value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2268 if ((value | B43legacy_MACCTL_GMODE) !=
2269 (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2270 goto error;
2271
2272 value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2273 if (value)
2274 goto error;
2275
2276 return 0;
2277error:
2278 b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2279 return -ENODEV;
2280}
2281
2282static void b43legacy_security_init(struct b43legacy_wldev *dev)
2283{
2284 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2285 B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2286 dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2287 0x0056);
2288 /* KTP is a word address, but we address SHM bytewise.
2289 * So multiply by two.
2290 */
2291 dev->ktp *= 2;
2292 if (dev->dev->id.revision >= 5)
2293 /* Number of RCMTA address slots */
2294 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2295 dev->max_nr_keys - 8);
2296}
2297
2298static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2299{
2300 struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2301 unsigned long flags;
2302
2303 /* Don't take wl->mutex here, as it could deadlock with
2304 * hwrng internal locking. It's not needed to take
2305 * wl->mutex here, anyway. */
2306
2307 spin_lock_irqsave(&wl->irq_lock, flags);
2308 *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2309 spin_unlock_irqrestore(&wl->irq_lock, flags);
2310
2311 return (sizeof(u16));
2312}
2313
2314static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2315{
2316 if (wl->rng_initialized)
2317 hwrng_unregister(&wl->rng);
2318}
2319
2320static int b43legacy_rng_init(struct b43legacy_wl *wl)
2321{
2322 int err;
2323
2324 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2325 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2326 wl->rng.name = wl->rng_name;
2327 wl->rng.data_read = b43legacy_rng_read;
2328 wl->rng.priv = (unsigned long)wl;
2329 wl->rng_initialized = 1;
2330 err = hwrng_register(&wl->rng);
2331 if (err) {
2332 wl->rng_initialized = 0;
2333 b43legacyerr(wl, "Failed to register the random "
2334 "number generator (%d)\n", err);
2335 }
2336
2337 return err;
2338}
2339
33a3dc93
SB		 2340static int b43legacy_op_tx(struct ieee80211_hw *hw,
2341 struct sk_buff *skb,
2342 struct ieee80211_tx_control *ctl)
75388acd
LF		 2343{
2344 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2345 struct b43legacy_wldev *dev = wl->current_dev;
2346 int err = -ENODEV;
2347 unsigned long flags;
2348
2349 if (unlikely(!dev))
2350 goto out;
2351 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2352 goto out;
2353 /* DMA-TX is done without a global lock. */
2354 if (b43legacy_using_pio(dev)) {
2355 spin_lock_irqsave(&wl->irq_lock, flags);
2356 err = b43legacy_pio_tx(dev, skb, ctl);
2357 spin_unlock_irqrestore(&wl->irq_lock, flags);
2358 } else
2359 err = b43legacy_dma_tx(dev, skb, ctl);
2360out:
2361 if (unlikely(err))
2362 return NETDEV_TX_BUSY;
2363 return NETDEV_TX_OK;
2364}
2365
33a3dc93
SB		 2366static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
2367 int queue,
2368 const struct ieee80211_tx_queue_params *params)
75388acd
LF		 2369{
2370 return 0;
2371}
2372
33a3dc93
SB		 2373static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
2374 struct ieee80211_tx_queue_stats *stats)
75388acd
LF		 2375{
2376 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2377 struct b43legacy_wldev *dev = wl->current_dev;
2378 unsigned long flags;
2379 int err = -ENODEV;
2380
2381 if (!dev)
2382 goto out;
2383 spin_lock_irqsave(&wl->irq_lock, flags);
2384 if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
2385 if (b43legacy_using_pio(dev))
2386 b43legacy_pio_get_tx_stats(dev, stats);
2387 else
2388 b43legacy_dma_get_tx_stats(dev, stats);
2389 err = 0;
2390 }
2391 spin_unlock_irqrestore(&wl->irq_lock, flags);
2392out:
2393 return err;
2394}
2395
33a3dc93
SB		 2396static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2397 struct ieee80211_low_level_stats *stats)
75388acd
LF		 2398{
2399 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2400 unsigned long flags;
2401
2402 spin_lock_irqsave(&wl->irq_lock, flags);
2403 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2404 spin_unlock_irqrestore(&wl->irq_lock, flags);
2405
2406 return 0;
2407}
2408
2409static const char *phymode_to_string(unsigned int phymode)
2410{
2411 switch (phymode) {
2412 case B43legacy_PHYMODE_B:
2413 return "B";
2414 case B43legacy_PHYMODE_G:
2415 return "G";
2416 default:
2417 B43legacy_BUG_ON(1);
2418 }
2419 return "";
2420}
2421
2422static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2423 unsigned int phymode,
2424 struct b43legacy_wldev **dev,
2425 bool *gmode)
2426{
2427 struct b43legacy_wldev *d;
2428
2429 list_for_each_entry(d, &wl->devlist, list) {
2430 if (d->phy.possible_phymodes & phymode) {
2431 /* Ok, this device supports the PHY-mode.
2432 * Set the gmode bit. */
2433 *gmode = 1;
2434 *dev = d;
2435
2436 return 0;
2437 }
2438 }
2439
2440 return -ESRCH;
2441}
2442
2443static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2444{
2445 struct ssb_device *sdev = dev->dev;
2446 u32 tmslow;
2447
2448 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2449 tmslow &= ~B43legacy_TMSLOW_GMODE;
2450 tmslow |= B43legacy_TMSLOW_PHYRESET;
2451 tmslow |= SSB_TMSLOW_FGC;
2452 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2453 msleep(1);
2454
2455 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2456 tmslow &= ~SSB_TMSLOW_FGC;
2457 tmslow |= B43legacy_TMSLOW_PHYRESET;
2458 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2459 msleep(1);
2460}
2461
2462/* Expects wl->mutex locked */
2463static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2464 unsigned int new_mode)
2465{
2466 struct b43legacy_wldev *up_dev;
2467 struct b43legacy_wldev *down_dev;
2468 int err;
2469 bool gmode = 0;
2470 int prev_status;
2471
2472 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2473 if (err) {
2474 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2475 phymode_to_string(new_mode));
2476 return err;
2477 }
2478 if ((up_dev == wl->current_dev) &&
2479 (!!wl->current_dev->phy.gmode == !!gmode))
2480 /* This device is already running. */
2481 return 0;
2482 b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2483 phymode_to_string(new_mode));
2484 down_dev = wl->current_dev;
2485
2486 prev_status = b43legacy_status(down_dev);
2487 /* Shutdown the currently running core. */
2488 if (prev_status >= B43legacy_STAT_STARTED)
2489 b43legacy_wireless_core_stop(down_dev);
2490 if (prev_status >= B43legacy_STAT_INITIALIZED)
2491 b43legacy_wireless_core_exit(down_dev);
2492
2493 if (down_dev != up_dev)
2494 /* We switch to a different core, so we put PHY into
2495 * RESET on the old core. */
2496 b43legacy_put_phy_into_reset(down_dev);
2497
2498 /* Now start the new core. */
2499 up_dev->phy.gmode = gmode;
2500 if (prev_status >= B43legacy_STAT_INITIALIZED) {
2501 err = b43legacy_wireless_core_init(up_dev);
2502 if (err) {
2503 b43legacyerr(wl, "Fatal: Could not initialize device"
2504 " for newly selected %s-PHY mode\n",
2505 phymode_to_string(new_mode));
2506 goto init_failure;
2507 }
2508 }
2509 if (prev_status >= B43legacy_STAT_STARTED) {
2510 err = b43legacy_wireless_core_start(up_dev);
2511 if (err) {
2512 b43legacyerr(wl, "Fatal: Coult not start device for "
2513 "newly selected %s-PHY mode\n",
2514 phymode_to_string(new_mode));
2515 b43legacy_wireless_core_exit(up_dev);
2516 goto init_failure;
2517 }
2518 }
2519 B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2520
2521 b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2522
2523 wl->current_dev = up_dev;
2524
2525 return 0;
2526init_failure:
2527 /* Whoops, failed to init the new core. No core is operating now. */
2528 wl->current_dev = NULL;
2529 return err;
2530}
2531
2532static int b43legacy_antenna_from_ieee80211(u8 antenna)
2533{
2534 switch (antenna) {
2535 case 0: /* default/diversity */
2536 return B43legacy_ANTENNA_DEFAULT;
2537 case 1: /* Antenna 0 */
2538 return B43legacy_ANTENNA0;
2539 case 2: /* Antenna 1 */
2540 return B43legacy_ANTENNA1;
2541 default:
2542 return B43legacy_ANTENNA_DEFAULT;
2543 }
2544}
2545
33a3dc93
SB		 2546static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2547 struct ieee80211_conf *conf)
75388acd
LF		 2548{
2549 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2550 struct b43legacy_wldev *dev;
2551 struct b43legacy_phy *phy;
2552 unsigned long flags;
2553 unsigned int new_phymode = 0xFFFF;
2554 int antenna_tx;
2555 int antenna_rx;
2556 int err = 0;
2557 u32 savedirqs;
2558
2559 antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
2560 antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
2561
2562 mutex_lock(&wl->mutex);
8318d78a
JB		 2563 dev = wl->current_dev;
2564 phy = &dev->phy;
75388acd
LF		 2565
2566 /* Switch the PHY mode (if necessary). */
8318d78a
JB		 2567 switch (conf->channel->band) {
2568 case IEEE80211_BAND_2GHZ:
2569 if (phy->type == B43legacy_PHYTYPE_B)
2570 new_phymode = B43legacy_PHYMODE_B;
2571 else
2572 new_phymode = B43legacy_PHYMODE_G;
75388acd
LF		 2573 break;
2574 default:
2575 B43legacy_WARN_ON(1);
2576 }
2577 err = b43legacy_switch_phymode(wl, new_phymode);
2578 if (err)
2579 goto out_unlock_mutex;
75388acd
LF		 2580
2581 /* Disable IRQs while reconfiguring the device.
2582 * This makes it possible to drop the spinlock throughout
2583 * the reconfiguration process. */
2584 spin_lock_irqsave(&wl->irq_lock, flags);
2585 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2586 spin_unlock_irqrestore(&wl->irq_lock, flags);
2587 goto out_unlock_mutex;
2588 }
2589 savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
2590 spin_unlock_irqrestore(&wl->irq_lock, flags);
2591 b43legacy_synchronize_irq(dev);
2592
2593 /* Switch to the requested channel.
2594 * The firmware takes care of races with the TX handler. */
8318d78a
JB		 2595 if (conf->channel->hw_value != phy->channel)
2596 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
75388acd
LF		 2597
2598 /* Enable/Disable ShortSlot timing. */
2599 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
2600 != dev->short_slot) {
2601 B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
2602 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2603 b43legacy_short_slot_timing_enable(dev);
2604 else
2605 b43legacy_short_slot_timing_disable(dev);
2606 }
2607
5be3bda8
JB		 2608 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2609
75388acd
LF		 2610 /* Adjust the desired TX power level. */
2611 if (conf->power_level != 0) {
2612 if (conf->power_level != phy->power_level) {
2613 phy->power_level = conf->power_level;
2614 b43legacy_phy_xmitpower(dev);
2615 }
2616 }
2617
2618 /* Antennas for RX and management frame TX. */
2619 b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2620
2621 /* Update templates for AP mode. */
2622 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
2623 b43legacy_set_beacon_int(dev, conf->beacon_int);
2624
2625
42a9174f
LF		 2626 if (!!conf->radio_enabled != phy->radio_on) {
2627 if (conf->radio_enabled) {
2628 b43legacy_radio_turn_on(dev);
2629 b43legacyinfo(dev->wl, "Radio turned on by software\n");
2630 if (!dev->radio_hw_enable)
2631 b43legacyinfo(dev->wl, "The hardware RF-kill"
2632 " button still turns the radio"
2633 " physically off. Press the"
2634 " button to turn it on.\n");
2635 } else {
93bb7f3a 2636 b43legacy_radio_turn_off(dev, 0);
42a9174f
LF		 2637 b43legacyinfo(dev->wl, "Radio turned off by"
2638 " software\n");
2639 }
2640 }
2641
75388acd
LF		 2642 spin_lock_irqsave(&wl->irq_lock, flags);
2643 b43legacy_interrupt_enable(dev, savedirqs);
2644 mmiowb();
2645 spin_unlock_irqrestore(&wl->irq_lock, flags);
2646out_unlock_mutex:
2647 mutex_unlock(&wl->mutex);
2648
2649 return err;
2650}
2651
33a3dc93
SB		 2652static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2653 unsigned int changed,
2654 unsigned int *fflags,
2655 int mc_count,
2656 struct dev_addr_list *mc_list)
75388acd
LF		 2657{
2658 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2659 struct b43legacy_wldev *dev = wl->current_dev;
2660 unsigned long flags;
2661
4150c572
JB		 2662 if (!dev) {
2663 *fflags = 0;
75388acd 2664 return;
75388acd 2665 }
4150c572
JB		 2666
2667 spin_lock_irqsave(&wl->irq_lock, flags);
2668 *fflags &= FIF_PROMISC_IN_BSS |
2669 FIF_ALLMULTI |
2670 FIF_FCSFAIL |
2671 FIF_PLCPFAIL |
2672 FIF_CONTROL |
2673 FIF_OTHER_BSS |
2674 FIF_BCN_PRBRESP_PROMISC;
2675
2676 changed &= FIF_PROMISC_IN_BSS |
2677 FIF_ALLMULTI |
2678 FIF_FCSFAIL |
2679 FIF_PLCPFAIL |
2680 FIF_CONTROL |
2681 FIF_OTHER_BSS |
2682 FIF_BCN_PRBRESP_PROMISC;
2683
2684 wl->filter_flags = *fflags;
2685
2686 if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2687 b43legacy_adjust_opmode(dev);
75388acd
LF		 2688 spin_unlock_irqrestore(&wl->irq_lock, flags);
2689}
2690
33a3dc93 2691static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 2692 struct ieee80211_vif *vif,
33a3dc93 2693 struct ieee80211_if_conf *conf)
75388acd
LF		 2694{
2695 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2696 struct b43legacy_wldev *dev = wl->current_dev;
2697 unsigned long flags;
2698
2699 if (!dev)
2700 return -ENODEV;
2701 mutex_lock(&wl->mutex);
2702 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 2703 B43legacy_WARN_ON(wl->vif != vif);
4150c572
JB		 2704 if (conf->bssid)
2705 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2706 else
2707 memset(wl->bssid, 0, ETH_ALEN);
2708 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2709 if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2710 B43legacy_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2711 b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
2712 if (conf->beacon)
2713 b43legacy_refresh_templates(dev, conf->beacon);
75388acd 2714 }
4150c572 2715 b43legacy_write_mac_bssid_templates(dev);
75388acd
LF		 2716 }
2717 spin_unlock_irqrestore(&wl->irq_lock, flags);
2718 mutex_unlock(&wl->mutex);
2719
2720 return 0;
2721}
2722
2723/* Locking: wl->mutex */
2724static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2725{
2726 struct b43legacy_wl *wl = dev->wl;
2727 unsigned long flags;
2728
2729 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2730 return;
440cb58a
SB		 2731
2732 /* Disable and sync interrupts. We must do this before than
2733 * setting the status to INITIALIZED, as the interrupt handler
2734 * won't care about IRQs then. */
2735 spin_lock_irqsave(&wl->irq_lock, flags);
2736 dev->irq_savedstate = b43legacy_interrupt_disable(dev,
2737 B43legacy_IRQ_ALL);
2738 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2739 spin_unlock_irqrestore(&wl->irq_lock, flags);
2740 b43legacy_synchronize_irq(dev);
2741
75388acd
LF		 2742 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2743
2744 mutex_unlock(&wl->mutex);
2745 /* Must unlock as it would otherwise deadlock. No races here.
2746 * Cancel the possibly running self-rearming periodic work. */
2747 cancel_delayed_work_sync(&dev->periodic_work);
2748 mutex_lock(&wl->mutex);
2749
2750 ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2751
75388acd
LF		 2752 b43legacy_mac_suspend(dev);
2753 free_irq(dev->dev->irq, dev);
2754 b43legacydbg(wl, "Wireless interface stopped\n");
2755}
2756
2757/* Locking: wl->mutex */
2758static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2759{
2760 int err;
2761
2762 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2763
2764 drain_txstatus_queue(dev);
2765 err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2766 IRQF_SHARED, KBUILD_MODNAME, dev);
2767 if (err) {
2768 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2769 dev->dev->irq);
2770 goto out;
2771 }
2772 /* We are ready to run. */
2773 b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2774
2775 /* Start data flow (TX/RX) */
2776 b43legacy_mac_enable(dev);
2777 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
2778 ieee80211_start_queues(dev->wl->hw);
2779
2780 /* Start maintenance work */
2781 b43legacy_periodic_tasks_setup(dev);
2782
2783 b43legacydbg(dev->wl, "Wireless interface started\n");
2784out:
2785 return err;
2786}
2787
2788/* Get PHY and RADIO versioning numbers */
2789static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2790{
2791 struct b43legacy_phy *phy = &dev->phy;
2792 u32 tmp;
2793 u8 analog_type;
2794 u8 phy_type;
2795 u8 phy_rev;
2796 u16 radio_manuf;
2797 u16 radio_ver;
2798 u16 radio_rev;
2799 int unsupported = 0;
2800
2801 /* Get PHY versioning */
2802 tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2803 analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2804 >> B43legacy_PHYVER_ANALOG_SHIFT;
2805 phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2806 phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2807 switch (phy_type) {
2808 case B43legacy_PHYTYPE_B:
2809 if (phy_rev != 2 && phy_rev != 4
2810 && phy_rev != 6 && phy_rev != 7)
2811 unsupported = 1;
2812 break;
2813 case B43legacy_PHYTYPE_G:
2814 if (phy_rev > 8)
2815 unsupported = 1;
2816 break;
2817 default:
2818 unsupported = 1;
2819 };
2820 if (unsupported) {
2821 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2822 "(Analog %u, Type %u, Revision %u)\n",
2823 analog_type, phy_type, phy_rev);
2824 return -EOPNOTSUPP;
2825 }
2826 b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2827 analog_type, phy_type, phy_rev);
2828
2829
2830 /* Get RADIO versioning */
2831 if (dev->dev->bus->chip_id == 0x4317) {
2832 if (dev->dev->bus->chip_rev == 0)
2833 tmp = 0x3205017F;
2834 else if (dev->dev->bus->chip_rev == 1)
2835 tmp = 0x4205017F;
2836 else
2837 tmp = 0x5205017F;
2838 } else {
2839 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2840 B43legacy_RADIOCTL_ID);
2841 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2842 tmp <<= 16;
2843 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2844 B43legacy_RADIOCTL_ID);
2845 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2846 }
2847 radio_manuf = (tmp & 0x00000FFF);
2848 radio_ver = (tmp & 0x0FFFF000) >> 12;
2849 radio_rev = (tmp & 0xF0000000) >> 28;
2850 switch (phy_type) {
2851 case B43legacy_PHYTYPE_B:
2852 if ((radio_ver & 0xFFF0) != 0x2050)
2853 unsupported = 1;
2854 break;
2855 case B43legacy_PHYTYPE_G:
2856 if (radio_ver != 0x2050)
2857 unsupported = 1;
2858 break;
2859 default:
2860 B43legacy_BUG_ON(1);
2861 }
2862 if (unsupported) {
2863 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
2864 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
2865 radio_manuf, radio_ver, radio_rev);
2866 return -EOPNOTSUPP;
2867 }
2868 b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
2869 " Revision %u\n", radio_manuf, radio_ver, radio_rev);
2870
2871
2872 phy->radio_manuf = radio_manuf;
2873 phy->radio_ver = radio_ver;
2874 phy->radio_rev = radio_rev;
2875
2876 phy->analog = analog_type;
2877 phy->type = phy_type;
2878 phy->rev = phy_rev;
2879
2880 return 0;
2881}
2882
2883static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
2884 struct b43legacy_phy *phy)
2885{
2886 struct b43legacy_lopair *lo;
2887 int i;
2888
2889 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
2890 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
2891
1065de15
LF		 2892 /* Assume the radio is enabled. If it's not enabled, the state will
2893 * immediately get fixed on the first periodic work run. */
2894 dev->radio_hw_enable = 1;
75388acd
LF		 2895
2896 phy->savedpctlreg = 0xFFFF;
2897 phy->aci_enable = 0;
2898 phy->aci_wlan_automatic = 0;
2899 phy->aci_hw_rssi = 0;
2900
2901 lo = phy->_lo_pairs;
2902 if (lo)
2903 memset(lo, 0, sizeof(struct b43legacy_lopair) *
2904 B43legacy_LO_COUNT);
2905 phy->max_lb_gain = 0;
2906 phy->trsw_rx_gain = 0;
2907
2908 /* Set default attenuation values. */
2909 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
2910 phy->rfatt = b43legacy_default_radio_attenuation(dev);
2911 phy->txctl1 = b43legacy_default_txctl1(dev);
2912 phy->txpwr_offset = 0;
2913
2914 /* NRSSI */
2915 phy->nrssislope = 0;
2916 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
2917 phy->nrssi[i] = -1000;
2918 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
2919 phy->nrssi_lt[i] = i;
2920
2921 phy->lofcal = 0xFFFF;
2922 phy->initval = 0xFFFF;
2923
75388acd
LF		 2924 phy->interfmode = B43legacy_INTERFMODE_NONE;
2925 phy->channel = 0xFF;
2926}
2927
2928static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
2929{
2930 /* Flags */
2931 dev->reg124_set_0x4 = 0;
2932
2933 /* Stats */
2934 memset(&dev->stats, 0, sizeof(dev->stats));
2935
2936 setup_struct_phy_for_init(dev, &dev->phy);
2937
2938 /* IRQ related flags */
2939 dev->irq_reason = 0;
2940 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
2941 dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
2942
2943 dev->mac_suspended = 1;
2944
2945 /* Noise calculation context */
2946 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
2947}
2948
2949static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
2950{
2951#ifdef CONFIG_SSB_DRIVER_PCICORE
2952 struct ssb_bus *bus = dev->dev->bus;
2953 u32 tmp;
2954
2955 if (bus->pcicore.dev &&
2956 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
2957 bus->pcicore.dev->id.revision <= 5) {
2958 /* IMCFGLO timeouts workaround. */
2959 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
2960 tmp &= ~SSB_IMCFGLO_REQTO;
2961 tmp &= ~SSB_IMCFGLO_SERTO;
2962 switch (bus->bustype) {
2963 case SSB_BUSTYPE_PCI:
2964 case SSB_BUSTYPE_PCMCIA:
2965 tmp |= 0x32;
2966 break;
2967 case SSB_BUSTYPE_SSB:
2968 tmp |= 0x53;
2969 break;
2970 }
2971 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
2972 }
2973#endif /* CONFIG_SSB_DRIVER_PCICORE */
2974}
2975
0a6e1bee
SB		 2976/* Write the short and long frame retry limit values. */
2977static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2978 unsigned int short_retry,
2979 unsigned int long_retry)
2980{
2981 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2982 * the chip-internal counter. */
2983 short_retry = min(short_retry, (unsigned int)0xF);
2984 long_retry = min(long_retry, (unsigned int)0xF);
2985
2986 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2987 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2988}
2989
75388acd
LF		 2990/* Shutdown a wireless core */
2991/* Locking: wl->mutex */
2992static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
2993{
2994 struct b43legacy_wl *wl = dev->wl;
2995 struct b43legacy_phy *phy = &dev->phy;
e78c9d28 2996 u32 macctl;
75388acd
LF		 2997
2998 B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
2999 if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3000 return;
3001 b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3002
e78c9d28
SB		 3003 /* Stop the microcode PSM. */
3004 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3005 macctl &= ~B43legacy_MACCTL_PSM_RUN;
3006 macctl |= B43legacy_MACCTL_PSM_JMP0;
3007 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3008
75388acd
LF		 3009 mutex_unlock(&wl->mutex);
3010 /* Must unlock as it would otherwise deadlock. No races here.
3011 * Cancel possibly pending workqueues. */
3012 cancel_work_sync(&dev->restart_work);
3013 mutex_lock(&wl->mutex);
3014
4ad36d78 3015 b43legacy_leds_exit(dev);
75388acd
LF		 3016 b43legacy_rng_exit(dev->wl);
3017 b43legacy_pio_free(dev);
3018 b43legacy_dma_free(dev);
3019 b43legacy_chip_exit(dev);
93bb7f3a 3020 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3021 b43legacy_switch_analog(dev, 0);
3022 if (phy->dyn_tssi_tbl)
3023 kfree(phy->tssi2dbm);
3024 kfree(phy->lo_control);
3025 phy->lo_control = NULL;
3026 ssb_device_disable(dev->dev, 0);
3027 ssb_bus_may_powerdown(dev->dev->bus);
3028}
3029
3030static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3031{
3032 struct b43legacy_phy *phy = &dev->phy;
3033 int i;
3034
3035 /* Set default attenuation values. */
3036 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3037 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3038 phy->txctl1 = b43legacy_default_txctl1(dev);
3039 phy->txctl2 = 0xFFFF;
3040 phy->txpwr_offset = 0;
3041
3042 /* NRSSI */
3043 phy->nrssislope = 0;
3044 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3045 phy->nrssi[i] = -1000;
3046 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3047 phy->nrssi_lt[i] = i;
3048
3049 phy->lofcal = 0xFFFF;
3050 phy->initval = 0xFFFF;
3051
3052 phy->aci_enable = 0;
3053 phy->aci_wlan_automatic = 0;
3054 phy->aci_hw_rssi = 0;
3055
3056 phy->antenna_diversity = 0xFFFF;
3057 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3058 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3059
3060 /* Flags */
3061 phy->calibrated = 0;
75388acd
LF		 3062
3063 if (phy->_lo_pairs)
3064 memset(phy->_lo_pairs, 0,
3065 sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3066 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3067}
3068
3069/* Initialize a wireless core */
3070static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3071{
3072 struct b43legacy_wl *wl = dev->wl;
3073 struct ssb_bus *bus = dev->dev->bus;
3074 struct b43legacy_phy *phy = &dev->phy;
3075 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3076 int err;
3077 u32 hf;
3078 u32 tmp;
3079
3080 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3081
3082 err = ssb_bus_powerup(bus, 0);
3083 if (err)
3084 goto out;
3085 if (!ssb_device_is_enabled(dev->dev)) {
3086 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3087 b43legacy_wireless_core_reset(dev, tmp);
3088 }
3089
3090 if ((phy->type == B43legacy_PHYTYPE_B) ||
3091 (phy->type == B43legacy_PHYTYPE_G)) {
3092 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3093 * B43legacy_LO_COUNT,
3094 GFP_KERNEL);
3095 if (!phy->_lo_pairs)
3096 return -ENOMEM;
3097 }
3098 setup_struct_wldev_for_init(dev);
3099
3100 err = b43legacy_phy_init_tssi2dbm_table(dev);
3101 if (err)
3102 goto err_kfree_lo_control;
3103
3104 /* Enable IRQ routing to this device. */
3105 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3106
3107 b43legacy_imcfglo_timeouts_workaround(dev);
3108 prepare_phy_data_for_init(dev);
3109 b43legacy_phy_calibrate(dev);
3110 err = b43legacy_chip_init(dev);
3111 if (err)
3112 goto err_kfree_tssitbl;
3113 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3114 B43legacy_SHM_SH_WLCOREREV,
3115 dev->dev->id.revision);
3116 hf = b43legacy_hf_read(dev);
3117 if (phy->type == B43legacy_PHYTYPE_G) {
3118 hf |= B43legacy_HF_SYMW;
3119 if (phy->rev == 1)
3120 hf |= B43legacy_HF_GDCW;
7797aa38 3121 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
75388acd
LF		 3122 hf |= B43legacy_HF_OFDMPABOOST;
3123 } else if (phy->type == B43legacy_PHYTYPE_B) {
3124 hf |= B43legacy_HF_SYMW;
3125 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3126 hf &= ~B43legacy_HF_GDCW;
3127 }
3128 b43legacy_hf_write(dev, hf);
3129
0a6e1bee
SB		 3130 b43legacy_set_retry_limits(dev,
3131 B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3132 B43legacy_DEFAULT_LONG_RETRY_LIMIT);
75388acd
LF		 3133
3134 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3135 0x0044, 3);
3136 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3137 0x0046, 2);
3138
3139 /* Disable sending probe responses from firmware.
3140 * Setting the MaxTime to one usec will always trigger
3141 * a timeout, so we never send any probe resp.
3142 * A timeout of zero is infinite. */
3143 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3144 B43legacy_SHM_SH_PRMAXTIME, 1);
3145
3146 b43legacy_rate_memory_init(dev);
3147
3148 /* Minimum Contention Window */
3149 if (phy->type == B43legacy_PHYTYPE_B)
3150 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3151 0x0003, 31);
3152 else
3153 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3154 0x0003, 15);
3155 /* Maximum Contention Window */
3156 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3157 0x0004, 1023);
3158
3159 do {
3160 if (b43legacy_using_pio(dev))
3161 err = b43legacy_pio_init(dev);
3162 else {
3163 err = b43legacy_dma_init(dev);
3164 if (!err)
3165 b43legacy_qos_init(dev);
3166 }
3167 } while (err == -EAGAIN);
3168 if (err)
3169 goto err_chip_exit;
3170
3171 b43legacy_write16(dev, 0x0612, 0x0050);
3172 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0416, 0x0050);
3173 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0414, 0x01F4);
3174
3175 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 3176 b43legacy_upload_card_macaddress(dev);
75388acd
LF		 3177 b43legacy_security_init(dev);
3178 b43legacy_rng_init(wl);
3179
3180 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3181
4ad36d78 3182 b43legacy_leds_init(dev);
75388acd
LF		 3183out:
3184 return err;
3185
3186err_chip_exit:
3187 b43legacy_chip_exit(dev);
3188err_kfree_tssitbl:
3189 if (phy->dyn_tssi_tbl)
3190 kfree(phy->tssi2dbm);
3191err_kfree_lo_control:
3192 kfree(phy->lo_control);
3193 phy->lo_control = NULL;
3194 ssb_bus_may_powerdown(bus);
3195 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3196 return err;
3197}
3198
33a3dc93
SB		 3199static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3200 struct ieee80211_if_init_conf *conf)
75388acd
LF		 3201{
3202 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3203 struct b43legacy_wldev *dev;
3204 unsigned long flags;
3205 int err = -EOPNOTSUPP;
4150c572
JB		 3206
3207 /* TODO: allow WDS/AP devices to coexist */
3208
3209 if (conf->type != IEEE80211_IF_TYPE_AP &&
3210 conf->type != IEEE80211_IF_TYPE_STA &&
3211 conf->type != IEEE80211_IF_TYPE_WDS &&
3212 conf->type != IEEE80211_IF_TYPE_IBSS)
3213 return -EOPNOTSUPP;
75388acd
LF		 3214
3215 mutex_lock(&wl->mutex);
4150c572 3216 if (wl->operating)
75388acd
LF		 3217 goto out_mutex_unlock;
3218
3219 b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
3220
3221 dev = wl->current_dev;
4150c572 3222 wl->operating = 1;
32bfd35d 3223 wl->vif = conf->vif;
4150c572
JB		 3224 wl->if_type = conf->type;
3225 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3226
3227 spin_lock_irqsave(&wl->irq_lock, flags);
3228 b43legacy_adjust_opmode(dev);
3229 b43legacy_upload_card_macaddress(dev);
3230 spin_unlock_irqrestore(&wl->irq_lock, flags);
3231
3232 err = 0;
3233 out_mutex_unlock:
3234 mutex_unlock(&wl->mutex);
3235
3236 return err;
3237}
3238
33a3dc93
SB		 3239static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3240 struct ieee80211_if_init_conf *conf)
4150c572
JB		 3241{
3242 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3243 struct b43legacy_wldev *dev = wl->current_dev;
3244 unsigned long flags;
3245
3246 b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
3247
3248 mutex_lock(&wl->mutex);
3249
3250 B43legacy_WARN_ON(!wl->operating);
32bfd35d
JB		 3251 B43legacy_WARN_ON(wl->vif != conf->vif);
3252 wl->vif = NULL;
4150c572
JB		 3253
3254 wl->operating = 0;
3255
3256 spin_lock_irqsave(&wl->irq_lock, flags);
3257 b43legacy_adjust_opmode(dev);
3258 memset(wl->mac_addr, 0, ETH_ALEN);
3259 b43legacy_upload_card_macaddress(dev);
3260 spin_unlock_irqrestore(&wl->irq_lock, flags);
3261
3262 mutex_unlock(&wl->mutex);
3263}
3264
33a3dc93 3265static int b43legacy_op_start(struct ieee80211_hw *hw)
4150c572
JB		 3266{
3267 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3268 struct b43legacy_wldev *dev = wl->current_dev;
3269 int did_init = 0;
208eec88 3270 int err = 0;
8712f276 3271 bool do_rfkill_exit = 0;
4150c572 3272
4ad36d78
LF		 3273 /* First register RFkill.
3274 * LEDs that are registered later depend on it. */
3275 b43legacy_rfkill_init(dev);
3276
ada50731
SB		 3277 /* Kill all old instance specific information to make sure
3278 * the card won't use it in the short timeframe between start
3279 * and mac80211 reconfiguring it. */
3280 memset(wl->bssid, 0, ETH_ALEN);
3281 memset(wl->mac_addr, 0, ETH_ALEN);
3282 wl->filter_flags = 0;
3283
4150c572
JB		 3284 mutex_lock(&wl->mutex);
3285
75388acd
LF		 3286 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3287 err = b43legacy_wireless_core_init(dev);
8712f276
MB		 3288 if (err) {
3289 do_rfkill_exit = 1;
75388acd 3290 goto out_mutex_unlock;
8712f276 3291 }
75388acd
LF		 3292 did_init = 1;
3293 }
4150c572 3294
75388acd
LF		 3295 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3296 err = b43legacy_wireless_core_start(dev);
3297 if (err) {
3298 if (did_init)
3299 b43legacy_wireless_core_exit(dev);
8712f276 3300 do_rfkill_exit = 1;
75388acd
LF		 3301 goto out_mutex_unlock;
3302 }
3303 }
3304
75388acd
LF		 3305out_mutex_unlock:
3306 mutex_unlock(&wl->mutex);
3307
8712f276
MB		 3308 if (do_rfkill_exit)
3309 b43legacy_rfkill_exit(dev);
3310
75388acd
LF		 3311 return err;
3312}
3313
33a3dc93 3314static void b43legacy_op_stop(struct ieee80211_hw *hw)
75388acd
LF		 3315{
3316 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
4150c572 3317 struct b43legacy_wldev *dev = wl->current_dev;
75388acd 3318
4ad36d78
LF		 3319 b43legacy_rfkill_exit(dev);
3320
75388acd 3321 mutex_lock(&wl->mutex);
4150c572
JB		 3322 if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3323 b43legacy_wireless_core_stop(dev);
3324 b43legacy_wireless_core_exit(dev);
75388acd
LF		 3325 mutex_unlock(&wl->mutex);
3326}
3327
0a6e1bee
SB		 3328static int b43legacy_op_set_retry_limit(struct ieee80211_hw *hw,
3329 u32 short_retry_limit,
3330 u32 long_retry_limit)
3331{
3332 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3333 struct b43legacy_wldev *dev;
3334 int err = 0;
3335
3336 mutex_lock(&wl->mutex);
3337 dev = wl->current_dev;
3338 if (unlikely(!dev ||
3339 (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED))) {
3340 err = -ENODEV;
3341 goto out_unlock;
3342 }
3343 b43legacy_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3344out_unlock:
3345 mutex_unlock(&wl->mutex);
3346
3347 return err;
3348}
75388acd
LF		 3349
3350static const struct ieee80211_ops b43legacy_hw_ops = {
33a3dc93
SB		 3351 .tx = b43legacy_op_tx,
3352 .conf_tx = b43legacy_op_conf_tx,
3353 .add_interface = b43legacy_op_add_interface,
3354 .remove_interface = b43legacy_op_remove_interface,
3355 .config = b43legacy_op_dev_config,
3356 .config_interface = b43legacy_op_config_interface,
3357 .configure_filter = b43legacy_op_configure_filter,
3358 .get_stats = b43legacy_op_get_stats,
3359 .get_tx_stats = b43legacy_op_get_tx_stats,
3360 .start = b43legacy_op_start,
3361 .stop = b43legacy_op_stop,
0a6e1bee 3362 .set_retry_limit = b43legacy_op_set_retry_limit,
75388acd
LF		 3363};
3364
3365/* Hard-reset the chip. Do not call this directly.
3366 * Use b43legacy_controller_restart()
3367 */
3368static void b43legacy_chip_reset(struct work_struct *work)
3369{
3370 struct b43legacy_wldev *dev =
3371 container_of(work, struct b43legacy_wldev, restart_work);
3372 struct b43legacy_wl *wl = dev->wl;
3373 int err = 0;
3374 int prev_status;
3375
3376 mutex_lock(&wl->mutex);
3377
3378 prev_status = b43legacy_status(dev);
3379 /* Bring the device down... */
3380 if (prev_status >= B43legacy_STAT_STARTED)
3381 b43legacy_wireless_core_stop(dev);
3382 if (prev_status >= B43legacy_STAT_INITIALIZED)
3383 b43legacy_wireless_core_exit(dev);
3384
3385 /* ...and up again. */
3386 if (prev_status >= B43legacy_STAT_INITIALIZED) {
3387 err = b43legacy_wireless_core_init(dev);
3388 if (err)
3389 goto out;
3390 }
3391 if (prev_status >= B43legacy_STAT_STARTED) {
3392 err = b43legacy_wireless_core_start(dev);
3393 if (err) {
3394 b43legacy_wireless_core_exit(dev);
3395 goto out;
3396 }
3397 }
3398out:
3399 mutex_unlock(&wl->mutex);
3400 if (err)
3401 b43legacyerr(wl, "Controller restart FAILED\n");
3402 else
3403 b43legacyinfo(wl, "Controller restarted\n");
3404}
3405
3406static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3407 int have_bphy,
3408 int have_gphy)
3409{
3410 struct ieee80211_hw *hw = dev->wl->hw;
75388acd 3411 struct b43legacy_phy *phy = &dev->phy;
75388acd
LF		 3412
3413 phy->possible_phymodes = 0;
8318d78a
JB		 3414 if (have_bphy) {
3415 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3416 &b43legacy_band_2GHz_BPHY;
3417 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3418 }
3419
3420 if (have_gphy) {
3421 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3422 &b43legacy_band_2GHz_GPHY;
3423 phy->possible_phymodes |= B43legacy_PHYMODE_G;
75388acd
LF		 3424 }
3425
3426 return 0;
3427}
3428
3429static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3430{
3431 /* We release firmware that late to not be required to re-request
3432 * is all the time when we reinit the core. */
3433 b43legacy_release_firmware(dev);
3434}
3435
3436static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3437{
3438 struct b43legacy_wl *wl = dev->wl;
3439 struct ssb_bus *bus = dev->dev->bus;
3440 struct pci_dev *pdev = bus->host_pci;
3441 int err;
3442 int have_bphy = 0;
3443 int have_gphy = 0;
3444 u32 tmp;
3445
3446 /* Do NOT do any device initialization here.
3447 * Do it in wireless_core_init() instead.
3448 * This function is for gathering basic information about the HW, only.
3449 * Also some structs may be set up here. But most likely you want to
3450 * have that in core_init(), too.
3451 */
3452
3453 err = ssb_bus_powerup(bus, 0);
3454 if (err) {
3455 b43legacyerr(wl, "Bus powerup failed\n");
3456 goto out;
3457 }
3458 /* Get the PHY type. */
3459 if (dev->dev->id.revision >= 5) {
3460 u32 tmshigh;
3461
3462 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3463 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3464 if (!have_gphy)
3465 have_bphy = 1;
3466 } else if (dev->dev->id.revision == 4)
3467 have_gphy = 1;
3468 else
3469 have_bphy = 1;
3470
75388acd
LF		 3471 dev->phy.gmode = (have_gphy || have_bphy);
3472 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3473 b43legacy_wireless_core_reset(dev, tmp);
3474
3475 err = b43legacy_phy_versioning(dev);
3476 if (err)
ba48f7bb 3477 goto err_powerdown;
75388acd
LF		 3478 /* Check if this device supports multiband. */
3479 if (!pdev ||
3480 (pdev->device != 0x4312 &&
3481 pdev->device != 0x4319 &&
3482 pdev->device != 0x4324)) {
3483 /* No multiband support. */
3484 have_bphy = 0;
3485 have_gphy = 0;
3486 switch (dev->phy.type) {
3487 case B43legacy_PHYTYPE_B:
3488 have_bphy = 1;
3489 break;
3490 case B43legacy_PHYTYPE_G:
3491 have_gphy = 1;
3492 break;
3493 default:
3494 B43legacy_BUG_ON(1);
3495 }
3496 }
3497 dev->phy.gmode = (have_gphy || have_bphy);
3498 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3499 b43legacy_wireless_core_reset(dev, tmp);
3500
3501 err = b43legacy_validate_chipaccess(dev);
3502 if (err)
ba48f7bb 3503 goto err_powerdown;
75388acd
LF		 3504 err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3505 if (err)
ba48f7bb 3506 goto err_powerdown;
75388acd
LF		 3507
3508 /* Now set some default "current_dev" */
3509 if (!wl->current_dev)
3510 wl->current_dev = dev;
3511 INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3512
93bb7f3a 3513 b43legacy_radio_turn_off(dev, 1);
75388acd
LF		 3514 b43legacy_switch_analog(dev, 0);
3515 ssb_device_disable(dev->dev, 0);
3516 ssb_bus_may_powerdown(bus);
3517
3518out:
3519 return err;
3520
75388acd
LF		 3521err_powerdown:
3522 ssb_bus_may_powerdown(bus);
3523 return err;
3524}
3525
3526static void b43legacy_one_core_detach(struct ssb_device *dev)
3527{
3528 struct b43legacy_wldev *wldev;
3529 struct b43legacy_wl *wl;
3530
3531 wldev = ssb_get_drvdata(dev);
3532 wl = wldev->wl;
3533 cancel_work_sync(&wldev->restart_work);
3534 b43legacy_debugfs_remove_device(wldev);
3535 b43legacy_wireless_core_detach(wldev);
3536 list_del(&wldev->list);
3537 wl->nr_devs--;
3538 ssb_set_drvdata(dev, NULL);
3539 kfree(wldev);
3540}
3541
3542static int b43legacy_one_core_attach(struct ssb_device *dev,
3543 struct b43legacy_wl *wl)
3544{
3545 struct b43legacy_wldev *wldev;
3546 struct pci_dev *pdev;
3547 int err = -ENOMEM;
3548
3549 if (!list_empty(&wl->devlist)) {
3550 /* We are not the first core on this chip. */
3551 pdev = dev->bus->host_pci;
3552 /* Only special chips support more than one wireless
3553 * core, although some of the other chips have more than
3554 * one wireless core as well. Check for this and
3555 * bail out early.
3556 */
3557 if (!pdev ||
3558 ((pdev->device != 0x4321) &&
3559 (pdev->device != 0x4313) &&
3560 (pdev->device != 0x431A))) {
3561 b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
3562 return -ENODEV;
3563 }
3564 }
3565
3566 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3567 if (!wldev)
3568 goto out;
3569
3570 wldev->dev = dev;
3571 wldev->wl = wl;
3572 b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3573 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3574 tasklet_init(&wldev->isr_tasklet,
3575 (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3576 (unsigned long)wldev);
3577 if (modparam_pio)
3578 wldev->__using_pio = 1;
3579 INIT_LIST_HEAD(&wldev->list);
3580
3581 err = b43legacy_wireless_core_attach(wldev);
3582 if (err)
3583 goto err_kfree_wldev;
3584
3585 list_add(&wldev->list, &wl->devlist);
3586 wl->nr_devs++;
3587 ssb_set_drvdata(dev, wldev);
3588 b43legacy_debugfs_add_device(wldev);
3589out:
3590 return err;
3591
3592err_kfree_wldev:
3593 kfree(wldev);
3594 return err;
3595}
3596
3597static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3598{
3599 /* boardflags workarounds */
3600 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3601 bus->boardinfo.type == 0x4E &&
3602 bus->boardinfo.rev > 0x40)
7797aa38 3603 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
75388acd
LF		 3604}
3605
3606static void b43legacy_wireless_exit(struct ssb_device *dev,
3607 struct b43legacy_wl *wl)
3608{
3609 struct ieee80211_hw *hw = wl->hw;
3610
3611 ssb_set_devtypedata(dev, NULL);
3612 ieee80211_free_hw(hw);
3613}
3614
3615static int b43legacy_wireless_init(struct ssb_device *dev)
3616{
3617 struct ssb_sprom *sprom = &dev->bus->sprom;
3618 struct ieee80211_hw *hw;
3619 struct b43legacy_wl *wl;
3620 int err = -ENOMEM;
3621
3622 b43legacy_sprom_fixup(dev->bus);
3623
3624 hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3625 if (!hw) {
3626 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3627 goto out;
3628 }
3629
3630 /* fill hw info */
3631 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3632 IEEE80211_HW_RX_INCLUDES_FCS;
3633 hw->max_signal = 100;
3634 hw->max_rssi = -110;
3635 hw->max_noise = -110;
3636 hw->queues = 1; /* FIXME: hardware has more queues */
3637 SET_IEEE80211_DEV(hw, dev->dev);
7797aa38
LF		 3638 if (is_valid_ether_addr(sprom->et1mac))
3639 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
75388acd 3640 else
7797aa38 3641 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
75388acd
LF		 3642
3643 /* Get and initialize struct b43legacy_wl */
3644 wl = hw_to_b43legacy_wl(hw);
3645 memset(wl, 0, sizeof(*wl));
3646 wl->hw = hw;
3647 spin_lock_init(&wl->irq_lock);
3648 spin_lock_init(&wl->leds_lock);
3649 mutex_init(&wl->mutex);
3650 INIT_LIST_HEAD(&wl->devlist);
3651
3652 ssb_set_devtypedata(dev, wl);
3653 b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3654 err = 0;
3655out:
3656 return err;
3657}
3658
3659static int b43legacy_probe(struct ssb_device *dev,
3660 const struct ssb_device_id *id)
3661{
3662 struct b43legacy_wl *wl;
3663 int err;
3664 int first = 0;
3665
3666 wl = ssb_get_devtypedata(dev);
3667 if (!wl) {
3668 /* Probing the first core - setup common struct b43legacy_wl */
3669 first = 1;
3670 err = b43legacy_wireless_init(dev);
3671 if (err)
3672 goto out;
3673 wl = ssb_get_devtypedata(dev);
3674 B43legacy_WARN_ON(!wl);
3675 }
3676 err = b43legacy_one_core_attach(dev, wl);
3677 if (err)
3678 goto err_wireless_exit;
3679
3680 if (first) {
3681 err = ieee80211_register_hw(wl->hw);
3682 if (err)
3683 goto err_one_core_detach;
3684 }
3685
3686out:
3687 return err;
3688
3689err_one_core_detach:
3690 b43legacy_one_core_detach(dev);
3691err_wireless_exit:
3692 if (first)
3693 b43legacy_wireless_exit(dev, wl);
3694 return err;
3695}
3696
3697static void b43legacy_remove(struct ssb_device *dev)
3698{
3699 struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3700 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3701
3702 B43legacy_WARN_ON(!wl);
3703 if (wl->current_dev == wldev)
3704 ieee80211_unregister_hw(wl->hw);
3705
3706 b43legacy_one_core_detach(dev);
3707
3708 if (list_empty(&wl->devlist))
3709 /* Last core on the chip unregistered.
3710 * We can destroy common struct b43legacy_wl.
3711 */
3712 b43legacy_wireless_exit(dev, wl);
3713}
3714
3715/* Perform a hardware reset. This can be called from any context. */
3716void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3717 const char *reason)
3718{
3719 /* Must avoid requeueing, if we are in shutdown. */
3720 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3721 return;
3722 b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
3723 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3724}
3725
3726#ifdef CONFIG_PM
3727
3728static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3729{
3730 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3731 struct b43legacy_wl *wl = wldev->wl;
3732
3733 b43legacydbg(wl, "Suspending...\n");
3734
3735 mutex_lock(&wl->mutex);
3736 wldev->suspend_init_status = b43legacy_status(wldev);
3737 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3738 b43legacy_wireless_core_stop(wldev);
3739 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3740 b43legacy_wireless_core_exit(wldev);
3741 mutex_unlock(&wl->mutex);
3742
3743 b43legacydbg(wl, "Device suspended.\n");
3744
3745 return 0;
3746}
3747
3748static int b43legacy_resume(struct ssb_device *dev)
3749{
3750 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3751 struct b43legacy_wl *wl = wldev->wl;
3752 int err = 0;
3753
3754 b43legacydbg(wl, "Resuming...\n");
3755
3756 mutex_lock(&wl->mutex);
3757 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3758 err = b43legacy_wireless_core_init(wldev);
3759 if (err) {
3760 b43legacyerr(wl, "Resume failed at core init\n");
3761 goto out;
3762 }
3763 }
3764 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3765 err = b43legacy_wireless_core_start(wldev);
3766 if (err) {
3767 b43legacy_wireless_core_exit(wldev);
3768 b43legacyerr(wl, "Resume failed at core start\n");
3769 goto out;
3770 }
3771 }
3772 mutex_unlock(&wl->mutex);
3773
3774 b43legacydbg(wl, "Device resumed.\n");
3775out:
3776 return err;
3777}
3778
3779#else /* CONFIG_PM */
3780# define b43legacy_suspend NULL
3781# define b43legacy_resume NULL
3782#endif /* CONFIG_PM */
3783
3784static struct ssb_driver b43legacy_ssb_driver = {
3785 .name = KBUILD_MODNAME,
3786 .id_table = b43legacy_ssb_tbl,
3787 .probe = b43legacy_probe,
3788 .remove = b43legacy_remove,
3789 .suspend = b43legacy_suspend,
3790 .resume = b43legacy_resume,
3791};
3792
6fff1c64
SB		 3793static void b43legacy_print_driverinfo(void)
3794{
3795 const char *feat_pci = "", *feat_leds = "", *feat_rfkill = "",
3796 *feat_pio = "", *feat_dma = "";
3797
3798#ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3799 feat_pci = "P";
3800#endif
3801#ifdef CONFIG_B43LEGACY_LEDS
3802 feat_leds = "L";
3803#endif
3804#ifdef CONFIG_B43LEGACY_RFKILL
3805 feat_rfkill = "R";
3806#endif
3807#ifdef CONFIG_B43LEGACY_PIO
3808 feat_pio = "I";
3809#endif
3810#ifdef CONFIG_B43LEGACY_DMA
3811 feat_dma = "D";
3812#endif
3813 printk(KERN_INFO "Broadcom 43xx driver loaded "
3814 "[ Features: %s%s%s%s%s, Firmware-ID: "
3815 B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
3816 feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma);
3817}
3818
75388acd
LF		 3819static int __init b43legacy_init(void)
3820{
3821 int err;
3822
3823 b43legacy_debugfs_init();
3824
3825 err = ssb_driver_register(&b43legacy_ssb_driver);
3826 if (err)
3827 goto err_dfs_exit;
3828
6fff1c64
SB		 3829 b43legacy_print_driverinfo();
3830
75388acd
LF		 3831 return err;
3832
3833err_dfs_exit:
3834 b43legacy_debugfs_exit();
3835 return err;
3836}
3837
3838static void __exit b43legacy_exit(void)
3839{
3840 ssb_driver_unregister(&b43legacy_ssb_driver);
3841 b43legacy_debugfs_exit();
3842}
3843
3844module_init(b43legacy_init)
3845module_exit(b43legacy_exit)