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ath9k: Add data structure for supporting virtual radio/wiphy operation
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
239static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
240{
cbe61d8a 241 struct ath_hw *ah = sc->sc_ah;
ff37e337 242 bool fastcc = true, stopped;
030bb495 243 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
291 sc->sc_flags &= ~SC_OP_FULL_RESET;
292
293 if (ath_startrecv(sc) != 0) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to restart recv logic\n");
296 return -EIO;
297 }
298
299 ath_cache_conf_rate(sc, &hw->conf);
300 ath_update_txpow(sc);
17d7904d 301 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 302 ath9k_ps_restore(sc);
ff37e337
S		 303 return 0;
304}
305
306/*
307 * This routine performs the periodic noise floor calibration function
308 * that is used to adjust and optimize the chip performance. This
309 * takes environmental changes (location, temperature) into account.
310 * When the task is complete, it reschedules itself depending on the
311 * appropriate interval that was calculated.
312 */
313static void ath_ani_calibrate(unsigned long data)
314{
20977d3e
S		 315 struct ath_softc *sc = (struct ath_softc *)data;
316 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 317 bool longcal = false;
318 bool shortcal = false;
319 bool aniflag = false;
320 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 321 u32 cal_interval, short_cal_interval;
ff37e337 322
20977d3e
S		 323 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
324 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 325
326 /*
327 * don't calibrate when we're scanning.
328 * we are most likely not on our home channel.
329 */
0c98de65 330 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 331 goto set_timer;
ff37e337
S		 332
333 /* Long calibration runs independently of short calibration. */
17d7904d 334 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 335 longcal = true;
04bd4638 336 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 337 sc->ani.longcal_timer = timestamp;
ff37e337
S		 338 }
339
17d7904d
S		 340 /* Short calibration applies only while caldone is false */
341 if (!sc->ani.caldone) {
20977d3e 342 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 343 shortcal = true;
04bd4638 344 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 345 sc->ani.shortcal_timer = timestamp;
346 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 347 }
348 } else {
17d7904d 349 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 350 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 351 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 if (sc->ani.caldone)
353 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 354 }
355 }
356
357 /* Verify whether we must check ANI */
20977d3e 358 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 359 aniflag = true;
17d7904d 360 sc->ani.checkani_timer = timestamp;
ff37e337
S		 361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
20977d3e 367 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 368
369 /* Perform calibration if necessary */
370 if (longcal || shortcal) {
371 bool iscaldone = false;
372
2660b81a 373 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 374 sc->rx_chainmask, longcal,
ff37e337
S		 375 &iscaldone)) {
376 if (longcal)
17d7904d 377 sc->ani.noise_floor =
ff37e337 378 ath9k_hw_getchan_noise(ah,
2660b81a 379 ah->curchan);
ff37e337
S		 380
381 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 382 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 383 ah->curchan->channel,
384 ah->curchan->channelFlags,
17d7904d 385 sc->ani.noise_floor);
ff37e337
S		 386 } else {
387 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 388 "calibrate chan %u/%x failed\n",
2660b81a
S		 389 ah->curchan->channel,
390 ah->curchan->channelFlags);
ff37e337 391 }
17d7904d 392 sc->ani.caldone = iscaldone;
ff37e337
S		 393 }
394 }
395
20977d3e 396set_timer:
ff37e337
S		 397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
aac9207e 402 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 403 if (sc->sc_ah->config.enable_ani)
aac9207e 404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 405 if (!sc->ani.caldone)
20977d3e 406 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 407
17d7904d 408 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 409}
410
411/*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
ff37e337
S		 416 */
417static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
418{
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9 420 if (is_ht ||
2660b81a
S		 421 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
423 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 424 } else {
17d7904d
S		 425 sc->tx_chainmask = 1;
426 sc->rx_chainmask = 1;
ff37e337
S		 427 }
428
04bd4638 429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 430 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 431}
432
433static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434{
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445}
446
447static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448{
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453}
454
455static void ath9k_tasklet(unsigned long data)
456{
457 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 458 u32 status = sc->intrstatus;
ff37e337
S		 459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 468 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 469 ath_rx_tasklet(sc, 0);
b77f483f 470 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
17d7904d 478 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 479}
480
6baff7f9 481irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 482{
483 struct ath_softc *sc = dev;
cbe61d8a 484 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
17d7904d 509 status &= sc->imask; /* discard unasked-for bits */
ff37e337
S		 510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
17d7904d 518 sc->intrstatus = status;
541d8dd5 519 ath9k_ps_wakeup(sc);
ff37e337
S		 520
521 if (status & ATH9K_INT_FATAL) {
522 /* need a chip reset */
523 sched = true;
524 } else if (status & ATH9K_INT_RXORN) {
525 /* need a chip reset */
526 sched = true;
527 } else {
528 if (status & ATH9K_INT_SWBA) {
529 /* schedule a tasklet for beacon handling */
530 tasklet_schedule(&sc->bcon_tasklet);
531 }
532 if (status & ATH9K_INT_RXEOL) {
533 /*
534 * NB: the hardware should re-read the link when
535 * RXE bit is written, but it doesn't work
536 * at least on older hardware revs.
537 */
538 sched = true;
539 }
540
541 if (status & ATH9K_INT_TXURN)
542 /* bump tx trigger level */
543 ath9k_hw_updatetxtriglevel(ah, true);
544 /* XXX: optimize this */
545 if (status & ATH9K_INT_RX)
546 sched = true;
547 if (status & ATH9K_INT_TX)
548 sched = true;
549 if (status & ATH9K_INT_BMISS)
550 sched = true;
551 /* carrier sense timeout */
552 if (status & ATH9K_INT_CST)
553 sched = true;
554 if (status & ATH9K_INT_MIB) {
555 /*
556 * Disable interrupts until we service the MIB
557 * interrupt; otherwise it will continue to
558 * fire.
559 */
560 ath9k_hw_set_interrupts(ah, 0);
561 /*
562 * Let the hal handle the event. We assume
563 * it will clear whatever condition caused
564 * the interrupt.
565 */
17d7904d
S		 566 ath9k_hw_procmibevent(ah, &sc->nodestats);
567 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 568 }
569 if (status & ATH9K_INT_TIM_TIMER) {
2660b81a 570 if (!(ah->caps.hw_caps &
ff37e337
S		 571 ATH9K_HW_CAP_AUTOSLEEP)) {
572 /* Clear RxAbort bit so that we can
573 * receive frames */
3cbb5dd7 574 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 575 ath9k_hw_setrxabort(ah, 0);
576 sched = true;
3cbb5dd7 577 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 578 }
579 }
4af9cf4f
S		 580 if (status & ATH9K_INT_TSFOOR) {
581 /* FIXME: Handle this interrupt for power save */
582 sched = true;
583 }
ff37e337 584 }
541d8dd5 585 ath9k_ps_restore(sc);
ff37e337
S		 586 } while (0);
587
817e11de
S		 588 ath_debug_stat_interrupt(sc, status);
589
ff37e337
S		 590 if (sched) {
591 /* turn off every interrupt except SWBA */
17d7904d 592 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
597}
598
f078f209 599static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 600 struct ieee80211_channel *chan,
094d05dc 601 enum nl80211_channel_type channel_type)
f078f209
LR		 602{
603 u32 chanmode = 0;
f078f209
LR		 604
605 switch (chan->band) {
606 case IEEE80211_BAND_2GHZ:
094d05dc
S		 607 switch(channel_type) {
608 case NL80211_CHAN_NO_HT:
609 case NL80211_CHAN_HT20:
f078f209 610 chanmode = CHANNEL_G_HT20;
094d05dc
S		 611 break;
612 case NL80211_CHAN_HT40PLUS:
f078f209 613 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 614 break;
615 case NL80211_CHAN_HT40MINUS:
f078f209 616 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 617 break;
618 }
f078f209
LR		 619 break;
620 case IEEE80211_BAND_5GHZ:
094d05dc
S		 621 switch(channel_type) {
622 case NL80211_CHAN_NO_HT:
623 case NL80211_CHAN_HT20:
f078f209 624 chanmode = CHANNEL_A_HT20;
094d05dc
S		 625 break;
626 case NL80211_CHAN_HT40PLUS:
f078f209 627 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 628 break;
629 case NL80211_CHAN_HT40MINUS:
f078f209 630 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 631 break;
632 }
f078f209
LR		 633 break;
634 default:
635 break;
636 }
637
638 return chanmode;
639}
640
6ace2891 641static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 642 struct ath9k_keyval *hk, const u8 *addr,
643 bool authenticator)
f078f209 644{
6ace2891
JM		 645 const u8 *key_rxmic;
646 const u8 *key_txmic;
f078f209 647
6ace2891
JM		 648 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
649 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 650
651 if (addr == NULL) {
d216aaa6
JM		 652 /*
653 * Group key installation - only two key cache entries are used
654 * regardless of splitmic capability since group key is only
655 * used either for TX or RX.
656 */
3f53dd64
JM		 657 if (authenticator) {
658 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
659 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
660 } else {
661 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
662 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
663 }
d216aaa6 664 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 665 }
17d7904d 666 if (!sc->splitmic) {
d216aaa6 667 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 670 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 671 }
d216aaa6
JM		 672
673 /* Separate key cache entries for TX and RX */
674
675 /* TX key goes at first index, RX key at +32. */
f078f209 676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 677 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
678 /* TX MIC entry failed. No need to proceed further */
f078f209 679 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 680 "Setting TX MIC Key Failed\n");
f078f209
LR		 681 return 0;
682 }
683
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 /* XXX delete tx key on failure? */
d216aaa6 686 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 687}
688
689static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
690{
691 int i;
692
17d7904d
S		 693 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
694 if (test_bit(i, sc->keymap) ||
695 test_bit(i + 64, sc->keymap))
6ace2891 696 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 697 if (sc->splitmic &&
698 (test_bit(i + 32, sc->keymap) ||
699 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 700 continue; /* At least one part of TKIP key allocated */
701
702 /* Found a free slot for a TKIP key */
703 return i;
704 }
705 return -1;
706}
707
708static int ath_reserve_key_cache_slot(struct ath_softc *sc)
709{
710 int i;
711
712 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 713 if (sc->splitmic) {
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
715 if (!test_bit(i, sc->keymap) &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 719 return i;
17d7904d
S		 720 if (!test_bit(i + 32, sc->keymap) &&
721 (test_bit(i, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 724 return i + 32;
17d7904d
S		 725 if (!test_bit(i + 64, sc->keymap) &&
726 (test_bit(i , sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
ea612132 729 return i + 64;
17d7904d
S		 730 if (!test_bit(i + 64 + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64, sc->keymap)))
ea612132 734 return i + 64 + 32;
6ace2891
JM		 735 }
736 } else {
17d7904d
S		 737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 test_bit(i + 64, sc->keymap))
6ace2891 740 return i;
17d7904d
S		 741 if (test_bit(i, sc->keymap) &&
742 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 743 return i + 64;
744 }
745 }
746
747 /* No partially used TKIP slots, pick any available slot */
17d7904d 748 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 749 /* Do not allow slots that could be needed for TKIP group keys
750 * to be used. This limitation could be removed if we know that
751 * TKIP will not be used. */
752 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 continue;
17d7904d 754 if (sc->splitmic) {
be2864cf
JM		 755 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
756 continue;
757 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
758 continue;
759 }
760
17d7904d 761 if (!test_bit(i, sc->keymap))
6ace2891
JM		 762 return i; /* Found a free slot for a key */
763 }
764
765 /* No free slot found */
766 return -1;
f078f209
LR		 767}
768
769static int ath_key_config(struct ath_softc *sc,
3f53dd64 770 struct ieee80211_vif *vif,
dc822b5d 771 struct ieee80211_sta *sta,
f078f209
LR		 772 struct ieee80211_key_conf *key)
773{
f078f209
LR		 774 struct ath9k_keyval hk;
775 const u8 *mac = NULL;
776 int ret = 0;
6ace2891 777 int idx;
f078f209
LR		 778
779 memset(&hk, 0, sizeof(hk));
780
781 switch (key->alg) {
782 case ALG_WEP:
783 hk.kv_type = ATH9K_CIPHER_WEP;
784 break;
785 case ALG_TKIP:
786 hk.kv_type = ATH9K_CIPHER_TKIP;
787 break;
788 case ALG_CCMP:
789 hk.kv_type = ATH9K_CIPHER_AES_CCM;
790 break;
791 default:
ca470b29 792 return -EOPNOTSUPP;
f078f209
LR		 793 }
794
6ace2891 795 hk.kv_len = key->keylen;
f078f209
LR		 796 memcpy(hk.kv_val, key->key, key->keylen);
797
6ace2891
JM		 798 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
799 /* For now, use the default keys for broadcast keys. This may
800 * need to change with virtual interfaces. */
801 idx = key->keyidx;
802 } else if (key->keyidx) {
dc822b5d
JB		 803 if (WARN_ON(!sta))
804 return -EOPNOTSUPP;
805 mac = sta->addr;
806
6ace2891
JM		 807 if (vif->type != NL80211_IFTYPE_AP) {
808 /* Only keyidx 0 should be used with unicast key, but
809 * allow this for client mode for now. */
810 idx = key->keyidx;
811 } else
812 return -EIO;
f078f209 813 } else {
dc822b5d
JB		 814 if (WARN_ON(!sta))
815 return -EOPNOTSUPP;
816 mac = sta->addr;
817
6ace2891
JM		 818 if (key->alg == ALG_TKIP)
819 idx = ath_reserve_key_cache_slot_tkip(sc);
820 else
821 idx = ath_reserve_key_cache_slot(sc);
822 if (idx < 0)
ca470b29 823 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 824 }
825
826 if (key->alg == ALG_TKIP)
3f53dd64
JM		 827 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
828 vif->type == NL80211_IFTYPE_AP);
f078f209 829 else
d216aaa6 830 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 831
832 if (!ret)
833 return -EIO;
834
17d7904d 835 set_bit(idx, sc->keymap);
6ace2891 836 if (key->alg == ALG_TKIP) {
17d7904d
S		 837 set_bit(idx + 64, sc->keymap);
838 if (sc->splitmic) {
839 set_bit(idx + 32, sc->keymap);
840 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 841 }
842 }
843
844 return idx;
f078f209
LR		 845}
846
847static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
848{
6ace2891
JM		 849 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
850 if (key->hw_key_idx < IEEE80211_WEP_NKID)
851 return;
852
17d7904d 853 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 854 if (key->alg != ALG_TKIP)
855 return;
f078f209 856
17d7904d
S		 857 clear_bit(key->hw_key_idx + 64, sc->keymap);
858 if (sc->splitmic) {
859 clear_bit(key->hw_key_idx + 32, sc->keymap);
860 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 861 }
f078f209
LR		 862}
863
eb2599ca
S		 864static void setup_ht_cap(struct ath_softc *sc,
865 struct ieee80211_sta_ht_cap *ht_info)
f078f209 866{
60653678
S		 867#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
868#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 869
d9fe60de
JB		 870 ht_info->ht_supported = true;
871 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
872 IEEE80211_HT_CAP_SM_PS |
873 IEEE80211_HT_CAP_SGI_40 |
874 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 875
60653678
S		 876 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
877 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 878
d9fe60de
JB		 879 /* set up supported mcs set */
880 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 881
17d7904d 882 switch(sc->rx_chainmask) {
eb2599ca
S		 883 case 1:
884 ht_info->mcs.rx_mask[0] = 0xff;
885 break;
3c457265 886 case 3:
eb2599ca
S		 887 case 5:
888 case 7:
889 default:
890 ht_info->mcs.rx_mask[0] = 0xff;
891 ht_info->mcs.rx_mask[1] = 0xff;
892 break;
893 }
894
d9fe60de 895 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 896}
897
8feceb67 898static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 899 struct ieee80211_vif *vif,
8feceb67 900 struct ieee80211_bss_conf *bss_conf)
f078f209 901{
17d7904d 902 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 903
8feceb67 904 if (bss_conf->assoc) {
094d05dc 905 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 906 bss_conf->aid, sc->curbssid);
f078f209 907
8feceb67 908 /* New association, store aid */
d97809db 909 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 910 sc->curaid = bss_conf->aid;
ba52da58 911 ath9k_hw_write_associd(sc);
8feceb67 912 }
f078f209 913
8feceb67 914 /* Configure the beacon */
2c3db3d5 915 ath_beacon_config(sc, vif);
f078f209 916
8feceb67 917 /* Reset rssi stats */
17d7904d
S		 918 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 922
6f255425 923 /* Start ANI */
17d7904d 924 mod_timer(&sc->ani.timer,
20977d3e 925 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
8feceb67 926 } else {
04bd4638 927 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
17d7904d 928 sc->curaid = 0;
f078f209 929 }
8feceb67 930}
f078f209 931
8feceb67
VT		 932/********************************/
933/* LED functions */
934/********************************/
f078f209 935
f2bffa7e
VT		 936static void ath_led_blink_work(struct work_struct *work)
937{
938 struct ath_softc *sc = container_of(work, struct ath_softc,
939 ath_led_blink_work.work);
940
941 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
942 return;
943 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
944 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
945
946 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
947 (sc->sc_flags & SC_OP_LED_ON) ?
948 msecs_to_jiffies(sc->led_off_duration) :
949 msecs_to_jiffies(sc->led_on_duration));
950
951 sc->led_on_duration =
952 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
953 sc->led_off_duration =
954 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
955 sc->led_on_cnt = sc->led_off_cnt = 0;
956 if (sc->sc_flags & SC_OP_LED_ON)
957 sc->sc_flags &= ~SC_OP_LED_ON;
958 else
959 sc->sc_flags |= SC_OP_LED_ON;
960}
961
8feceb67
VT		 962static void ath_led_brightness(struct led_classdev *led_cdev,
963 enum led_brightness brightness)
964{
965 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
966 struct ath_softc *sc = led->sc;
f078f209 967
8feceb67
VT		 968 switch (brightness) {
969 case LED_OFF:
970 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 971 led->led_type == ATH_LED_RADIO) {
972 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
973 (led->led_type == ATH_LED_RADIO));
8feceb67 974 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 975 if (led->led_type == ATH_LED_RADIO)
976 sc->sc_flags &= ~SC_OP_LED_ON;
977 } else {
978 sc->led_off_cnt++;
979 }
8feceb67
VT		 980 break;
981 case LED_FULL:
f2bffa7e 982 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 983 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 984 queue_delayed_work(sc->hw->workqueue,
985 &sc->ath_led_blink_work, 0);
986 } else if (led->led_type == ATH_LED_RADIO) {
987 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
988 sc->sc_flags |= SC_OP_LED_ON;
989 } else {
990 sc->led_on_cnt++;
991 }
8feceb67
VT		 992 break;
993 default:
994 break;
f078f209 995 }
8feceb67 996}
f078f209 997
8feceb67
VT		 998static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
999 char *trigger)
1000{
1001 int ret;
f078f209 1002
8feceb67
VT		 1003 led->sc = sc;
1004 led->led_cdev.name = led->name;
1005 led->led_cdev.default_trigger = trigger;
1006 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1007
8feceb67
VT		 1008 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009 if (ret)
1010 DPRINTF(sc, ATH_DBG_FATAL,
1011 "Failed to register led:%s", led->name);
1012 else
1013 led->registered = 1;
1014 return ret;
1015}
f078f209 1016
8feceb67
VT		 1017static void ath_unregister_led(struct ath_led *led)
1018{
1019 if (led->registered) {
1020 led_classdev_unregister(&led->led_cdev);
1021 led->registered = 0;
f078f209 1022 }
f078f209
LR		 1023}
1024
8feceb67 1025static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1026{
f2bffa7e 1027 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1028 ath_unregister_led(&sc->assoc_led);
1029 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030 ath_unregister_led(&sc->tx_led);
1031 ath_unregister_led(&sc->rx_led);
1032 ath_unregister_led(&sc->radio_led);
1033 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034}
f078f209 1035
8feceb67
VT		 1036static void ath_init_leds(struct ath_softc *sc)
1037{
1038 char *trigger;
1039 int ret;
f078f209 1040
8feceb67
VT		 1041 /* Configure gpio 1 for output */
1042 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044 /* LED off, active low */
1045 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1046
f2bffa7e
VT		 1047 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
8feceb67
VT		 1049 trigger = ieee80211_get_radio_led_name(sc->hw);
1050 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1051 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1052 ret = ath_register_led(sc, &sc->radio_led, trigger);
1053 sc->radio_led.led_type = ATH_LED_RADIO;
1054 if (ret)
1055 goto fail;
7dcfdcd9 1056
8feceb67
VT		 1057 trigger = ieee80211_get_assoc_led_name(sc->hw);
1058 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1059 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1060 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061 sc->assoc_led.led_type = ATH_LED_ASSOC;
1062 if (ret)
1063 goto fail;
f078f209 1064
8feceb67
VT		 1065 trigger = ieee80211_get_tx_led_name(sc->hw);
1066 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1067 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1068 ret = ath_register_led(sc, &sc->tx_led, trigger);
1069 sc->tx_led.led_type = ATH_LED_TX;
1070 if (ret)
1071 goto fail;
f078f209 1072
8feceb67
VT		 1073 trigger = ieee80211_get_rx_led_name(sc->hw);
1074 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1075 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1076 ret = ath_register_led(sc, &sc->rx_led, trigger);
1077 sc->rx_led.led_type = ATH_LED_RX;
1078 if (ret)
1079 goto fail;
f078f209 1080
8feceb67
VT		 1081 return;
1082
1083fail:
1084 ath_deinit_leds(sc);
f078f209
LR		 1085}
1086
e97275cb 1087#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1088
500c064d
VT		 1089/*******************/
1090/* Rfkill */
1091/*******************/
1092
1093static void ath_radio_enable(struct ath_softc *sc)
1094{
cbe61d8a 1095 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1096 struct ieee80211_channel *channel = sc->hw->conf.channel;
1097 int r;
500c064d 1098
3cbb5dd7 1099 ath9k_ps_wakeup(sc);
500c064d 1100 spin_lock_bh(&sc->sc_resetlock);
ae8d2858 1101
2660b81a 1102 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858
LR		 1103
1104 if (r) {
500c064d 1105 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1106 "Unable to reset channel %u (%uMhz) ",
1107 "reset status %u\n",
1108 channel->center_freq, r);
500c064d
VT		 1109 }
1110 spin_unlock_bh(&sc->sc_resetlock);
1111
1112 ath_update_txpow(sc);
1113 if (ath_startrecv(sc) != 0) {
1114 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1115 "Unable to restart recv logic\n");
500c064d
VT		 1116 return;
1117 }
1118
1119 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1120 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1121
1122 /* Re-Enable interrupts */
17d7904d 1123 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1124
1125 /* Enable LED */
1126 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1127 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1128 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1129
1130 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1131 ath9k_ps_restore(sc);
500c064d
VT		 1132}
1133
1134static void ath_radio_disable(struct ath_softc *sc)
1135{
cbe61d8a 1136 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1137 struct ieee80211_channel *channel = sc->hw->conf.channel;
1138 int r;
500c064d 1139
3cbb5dd7 1140 ath9k_ps_wakeup(sc);
500c064d
VT		 1141 ieee80211_stop_queues(sc->hw);
1142
1143 /* Disable LED */
1144 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1145 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1146
1147 /* Disable interrupts */
1148 ath9k_hw_set_interrupts(ah, 0);
1149
043a0405 1150 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1151 ath_stoprecv(sc); /* turn off frame recv */
1152 ath_flushrecv(sc); /* flush recv queue */
1153
1154 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1155 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1156 if (r) {
500c064d 1157 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1158 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1159 "reset status %u\n",
1160 channel->center_freq, r);
500c064d
VT		 1161 }
1162 spin_unlock_bh(&sc->sc_resetlock);
1163
1164 ath9k_hw_phy_disable(ah);
1165 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1166 ath9k_ps_restore(sc);
500c064d
VT		 1167}
1168
1169static bool ath_is_rfkill_set(struct ath_softc *sc)
1170{
cbe61d8a 1171 struct ath_hw *ah = sc->sc_ah;
500c064d 1172
2660b81a
S		 1173 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1174 ah->rfkill_polarity;
500c064d
VT		 1175}
1176
1177/* h/w rfkill poll function */
1178static void ath_rfkill_poll(struct work_struct *work)
1179{
1180 struct ath_softc *sc = container_of(work, struct ath_softc,
1181 rf_kill.rfkill_poll.work);
1182 bool radio_on;
1183
1184 if (sc->sc_flags & SC_OP_INVALID)
1185 return;
1186
1187 radio_on = !ath_is_rfkill_set(sc);
1188
1189 /*
1190 * enable/disable radio only when there is a
1191 * state change in RF switch
1192 */
1193 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194 enum rfkill_state state;
1195
1196 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198 : RFKILL_STATE_HARD_BLOCKED;
1199 } else if (radio_on) {
1200 ath_radio_enable(sc);
1201 state = RFKILL_STATE_UNBLOCKED;
1202 } else {
1203 ath_radio_disable(sc);
1204 state = RFKILL_STATE_HARD_BLOCKED;
1205 }
1206
1207 if (state == RFKILL_STATE_HARD_BLOCKED)
1208 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1209 else
1210 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1211
1212 rfkill_force_state(sc->rf_kill.rfkill, state);
1213 }
1214
1215 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1217}
1218
1219/* s/w rfkill handler */
1220static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1221{
1222 struct ath_softc *sc = data;
1223
1224 switch (state) {
1225 case RFKILL_STATE_SOFT_BLOCKED:
1226 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227 SC_OP_RFKILL_SW_BLOCKED)))
1228 ath_radio_disable(sc);
1229 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1230 return 0;
1231 case RFKILL_STATE_UNBLOCKED:
1232 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1236 "radio as it is disabled by h/w\n");
500c064d
VT		 1237 return -EPERM;
1238 }
1239 ath_radio_enable(sc);
1240 }
1241 return 0;
1242 default:
1243 return -EINVAL;
1244 }
1245}
1246
1247/* Init s/w rfkill */
1248static int ath_init_sw_rfkill(struct ath_softc *sc)
1249{
1250 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1251 RFKILL_TYPE_WLAN);
1252 if (!sc->rf_kill.rfkill) {
1253 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1254 return -ENOMEM;
1255 }
1256
1257 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1258 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1259 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260 sc->rf_kill.rfkill->data = sc;
1261 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1264
1265 return 0;
1266}
1267
1268/* Deinitialize rfkill */
1269static void ath_deinit_rfkill(struct ath_softc *sc)
1270{
2660b81a 1271 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1272 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275 rfkill_unregister(sc->rf_kill.rfkill);
1276 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277 sc->rf_kill.rfkill = NULL;
1278 }
1279}
9c84b797
S		 1280
1281static int ath_start_rfkill_poll(struct ath_softc *sc)
1282{
2660b81a 1283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1284 queue_delayed_work(sc->hw->workqueue,
1285 &sc->rf_kill.rfkill_poll, 0);
1286
1287 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288 if (rfkill_register(sc->rf_kill.rfkill)) {
1289 DPRINTF(sc, ATH_DBG_FATAL,
1290 "Unable to register rfkill\n");
1291 rfkill_free(sc->rf_kill.rfkill);
1292
1293 /* Deinitialize the device */
39c3c2f2 1294 ath_cleanup(sc);
9c84b797
S		 1295 return -EIO;
1296 } else {
1297 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298 }
1299 }
1300
1301 return 0;
1302}
500c064d
VT		 1303#endif /* CONFIG_RFKILL */
1304
6baff7f9 1305void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1306{
1307 ath_detach(sc);
1308 free_irq(sc->irq, sc);
1309 ath_bus_cleanup(sc);
1310 ieee80211_free_hw(sc->hw);
1311}
1312
6baff7f9 1313void ath_detach(struct ath_softc *sc)
f078f209 1314{
8feceb67 1315 struct ieee80211_hw *hw = sc->hw;
9c84b797 1316 int i = 0;
f078f209 1317
3cbb5dd7
VN		 1318 ath9k_ps_wakeup(sc);
1319
04bd4638 1320 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1321
e97275cb 1322#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1323 ath_deinit_rfkill(sc);
1324#endif
3fcdfb4b
VT		 1325 ath_deinit_leds(sc);
1326
1327 ieee80211_unregister_hw(hw);
8feceb67
VT		 1328 ath_rx_cleanup(sc);
1329 ath_tx_cleanup(sc);
f078f209 1330
9c84b797
S		 1331 tasklet_kill(&sc->intr_tq);
1332 tasklet_kill(&sc->bcon_tasklet);
f078f209 1333
9c84b797
S		 1334 if (!(sc->sc_flags & SC_OP_INVALID))
1335 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1336
9c84b797
S		 1337 /* cleanup tx queues */
1338 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1339 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1340 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1341
1342 ath9k_hw_detach(sc->sc_ah);
826d2680 1343 ath9k_exit_debug(sc);
3cbb5dd7 1344 ath9k_ps_restore(sc);
f078f209
LR		 1345}
1346
ff37e337
S		 1347static int ath_init(u16 devid, struct ath_softc *sc)
1348{
cbe61d8a 1349 struct ath_hw *ah = NULL;
ff37e337
S		 1350 int status;
1351 int error = 0, i;
1352 int csz = 0;
1353
1354 /* XXX: hardware will not be ready until ath_open() being called */
1355 sc->sc_flags |= SC_OP_INVALID;
88b126af 1356
826d2680
S		 1357 if (ath9k_init_debug(sc) < 0)
1358 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1359
1360 spin_lock_init(&sc->sc_resetlock);
aa33de09 1361 mutex_init(&sc->mutex);
ff37e337 1362 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1363 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1364 (unsigned long)sc);
1365
1366 /*
1367 * Cache line size is used to size and align various
1368 * structures used to communicate with the hardware.
1369 */
88d15707 1370 ath_read_cachesize(sc, &csz);
ff37e337 1371 /* XXX assert csz is non-zero */
17d7904d 1372 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1373
cbe61d8a 1374 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1375 if (ah == NULL) {
1376 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1377 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1378 error = -ENXIO;
1379 goto bad;
1380 }
1381 sc->sc_ah = ah;
1382
1383 /* Get the hardware key cache size. */
2660b81a 1384 sc->keymax = ah->caps.keycache_size;
17d7904d 1385 if (sc->keymax > ATH_KEYMAX) {
ff37e337 1386 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 1387 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1388 ATH_KEYMAX, sc->keymax);
1389 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1390 }
1391
1392 /*
1393 * Reset the key cache since some parts do not
1394 * reset the contents on initial power up.
1395 */
17d7904d 1396 for (i = 0; i < sc->keymax; i++)
ff37e337 1397 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1398
5f8e077c 1399 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1400 goto bad;
1401
1402 /* default to MONITOR mode */
2660b81a 1403 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1404
ff37e337
S		 1405 /* Setup rate tables */
1406
1407 ath_rate_attach(sc);
1408 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1409 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1410
1411 /*
1412 * Allocate hardware transmit queues: one queue for
1413 * beacon frames and one data queue for each QoS
1414 * priority. Note that the hal handles reseting
1415 * these queues at the needed time.
1416 */
b77f483f
S		 1417 sc->beacon.beaconq = ath_beaconq_setup(ah);
1418 if (sc->beacon.beaconq == -1) {
ff37e337 1419 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1420 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1421 error = -EIO;
1422 goto bad2;
1423 }
b77f483f
S		 1424 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1425 if (sc->beacon.cabq == NULL) {
ff37e337 1426 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1427 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1428 error = -EIO;
1429 goto bad2;
1430 }
1431
17d7904d 1432 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1433 ath_cabq_update(sc);
1434
b77f483f
S		 1435 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1436 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1437
1438 /* Setup data queues */
1439 /* NB: ensure BK queue is the lowest priority h/w queue */
1440 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1441 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1442 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1443 error = -EIO;
1444 goto bad2;
1445 }
1446
1447 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1448 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1449 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1450 error = -EIO;
1451 goto bad2;
1452 }
1453 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1454 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1455 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1456 error = -EIO;
1457 goto bad2;
1458 }
1459 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1460 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1461 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1462 error = -EIO;
1463 goto bad2;
1464 }
1465
1466 /* Initializes the noise floor to a reasonable default value.
1467 * Later on this will be updated during ANI processing. */
1468
17d7904d
S		 1469 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1470 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1471
1472 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1473 ATH9K_CIPHER_TKIP, NULL)) {
1474 /*
1475 * Whether we should enable h/w TKIP MIC.
1476 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1477 * report WMM capable, so it's always safe to turn on
1478 * TKIP MIC in this case.
1479 */
1480 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1481 0, 1, NULL);
1482 }
1483
1484 /*
1485 * Check whether the separate key cache entries
1486 * are required to handle both tx+rx MIC keys.
1487 * With split mic keys the number of stations is limited
1488 * to 27 otherwise 59.
1489 */
1490 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1491 ATH9K_CIPHER_TKIP, NULL)
1492 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493 ATH9K_CIPHER_MIC, NULL)
1494 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1495 0, NULL))
17d7904d 1496 sc->splitmic = 1;
ff37e337
S		 1497
1498 /* turn on mcast key search if possible */
1499 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1500 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1501 1, NULL);
1502
17d7904d 1503 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1504
1505 /* 11n Capabilities */
2660b81a 1506 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1507 sc->sc_flags |= SC_OP_TXAGGR;
1508 sc->sc_flags |= SC_OP_RXAGGR;
1509 }
1510
2660b81a
S		 1511 sc->tx_chainmask = ah->caps.tx_chainmask;
1512 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1513
1514 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1515 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1516
8ca21f01 1517 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1518 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1519
b77f483f 1520 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1521
1522 /* initialize beacon slots */
b77f483f 1523 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
2c3db3d5 1524 sc->beacon.bslot[i] = NULL;
ff37e337
S		 1525
1526 /* save MISC configurations */
17d7904d 1527 sc->config.swBeaconProcess = 1;
ff37e337 1528
ff37e337
S		 1529 /* setup channels and rates */
1530
5f8e077c 1531 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1532 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1533 sc->rates[IEEE80211_BAND_2GHZ];
1534 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1535 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1536 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1537
2660b81a 1538 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1539 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1540 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1541 sc->rates[IEEE80211_BAND_5GHZ];
1542 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1543 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1544 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1545 }
1546
2660b81a 1547 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1548 ath9k_hw_btcoex_enable(sc->sc_ah);
1549
ff37e337
S		 1550 return 0;
1551bad2:
1552 /* cleanup tx queues */
1553 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1554 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1555 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1556bad:
1557 if (ah)
1558 ath9k_hw_detach(ah);
40b130a9 1559 ath9k_exit_debug(sc);
ff37e337
S		 1560
1561 return error;
1562}
1563
6baff7f9 1564int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1565{
8feceb67 1566 struct ieee80211_hw *hw = sc->hw;
191a99b7 1567 const struct ieee80211_regdomain *regd;
40b130a9 1568 int error = 0, i;
f078f209 1569
04bd4638 1570 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1571
8feceb67
VT		 1572 error = ath_init(devid, sc);
1573 if (error != 0)
1574 return error;
f078f209 1575
8feceb67 1576 /* get mac address from hardware and set in mac80211 */
f078f209 1577
ba52da58 1578 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
f078f209 1579
9c84b797
S		 1580 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1581 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1582 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1583 IEEE80211_HW_AMPDU_AGGREGATION |
1584 IEEE80211_HW_SUPPORTS_PS |
1585 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1586
b3bd89ce 1587 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1588 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1589
9c84b797
S		 1590 hw->wiphy->interface_modes =
1591 BIT(NL80211_IFTYPE_AP) |
1592 BIT(NL80211_IFTYPE_STATION) |
1593 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1594
5f8e077c
LR		 1595 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1596 hw->wiphy->strict_regulatory = true;
1597
8feceb67 1598 hw->queues = 4;
e63835b0 1599 hw->max_rates = 4;
171387ef 1600 hw->channel_change_time = 5000;
e63835b0 1601 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1602 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1603 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1604
8feceb67 1605 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1606
2660b81a 1607 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1608 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1609 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1610 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1611 }
1612
1613 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
2660b81a 1614 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
9c84b797
S		 1615 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1616 &sc->sbands[IEEE80211_BAND_5GHZ];
1617
db93e7b5
SB		 1618 /* initialize tx/rx engine */
1619 error = ath_tx_init(sc, ATH_TXBUF);
1620 if (error != 0)
40b130a9 1621 goto error_attach;
8feceb67 1622
db93e7b5
SB		 1623 error = ath_rx_init(sc, ATH_RXBUF);
1624 if (error != 0)
40b130a9 1625 goto error_attach;
8feceb67 1626
e97275cb 1627#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1628 /* Initialze h/w Rfkill */
2660b81a 1629 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1630 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1631
1632 /* Initialize s/w rfkill */
40b130a9
VT		 1633 error = ath_init_sw_rfkill(sc);
1634 if (error)
1635 goto error_attach;
500c064d
VT		 1636#endif
1637
5f8e077c 1638 if (ath9k_is_world_regd(sc->sc_ah)) {
191a99b7 1639 /* Anything applied here (prior to wiphy registration) gets
5f8e077c 1640 * saved on the wiphy orig_* parameters */
191a99b7 1641 regd = ath9k_world_regdomain(sc->sc_ah);
5f8e077c
LR		 1642 hw->wiphy->custom_regulatory = true;
1643 hw->wiphy->strict_regulatory = false;
5f8e077c
LR		 1644 } else {
1645 /* This gets applied in the case of the absense of CRDA,
191a99b7 1646 * it's our own custom world regulatory domain, similar to
5f8e077c 1647 * cfg80211's but we enable passive scanning */
191a99b7 1648 regd = ath9k_default_world_regdomain();
5f8e077c 1649 }
191a99b7
BC		 1650 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1651 ath9k_reg_apply_radar_flags(hw->wiphy);
1652 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
5f8e077c 1653
db93e7b5 1654 error = ieee80211_register_hw(hw);
8feceb67 1655
fe33eb39
LR		 1656 if (!ath9k_is_world_regd(sc->sc_ah)) {
1657 error = regulatory_hint(hw->wiphy,
1658 sc->sc_ah->regulatory.alpha2);
1659 if (error)
1660 goto error_attach;
1661 }
5f8e077c 1662
db93e7b5
SB		 1663 /* Initialize LED control */
1664 ath_init_leds(sc);
8feceb67 1665
5f8e077c 1666
8feceb67 1667 return 0;
40b130a9
VT		 1668
1669error_attach:
1670 /* cleanup tx queues */
1671 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1672 if (ATH_TXQ_SETUP(sc, i))
1673 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1674
1675 ath9k_hw_detach(sc->sc_ah);
1676 ath9k_exit_debug(sc);
1677
8feceb67 1678 return error;
f078f209
LR		 1679}
1680
ff37e337
S		 1681int ath_reset(struct ath_softc *sc, bool retry_tx)
1682{
cbe61d8a 1683 struct ath_hw *ah = sc->sc_ah;
030bb495 1684 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1685 int r;
ff37e337
S		 1686
1687 ath9k_hw_set_interrupts(ah, 0);
043a0405 1688 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1689 ath_stoprecv(sc);
1690 ath_flushrecv(sc);
1691
1692 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1693 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1694 if (r)
ff37e337 1695 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1696 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1697 spin_unlock_bh(&sc->sc_resetlock);
1698
1699 if (ath_startrecv(sc) != 0)
04bd4638 1700 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1701
1702 /*
1703 * We may be doing a reset in response to a request
1704 * that changes the channel so update any state that
1705 * might change as a result.
1706 */
ce111bad 1707 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1708
1709 ath_update_txpow(sc);
1710
1711 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1712 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1713
17d7904d 1714 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1715
1716 if (retry_tx) {
1717 int i;
1718 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1719 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1720 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1721 ath_txq_schedule(sc, &sc->tx.txq[i]);
1722 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1723 }
1724 }
1725 }
1726
ae8d2858 1727 return r;
ff37e337
S		 1728}
1729
1730/*
1731 * This function will allocate both the DMA descriptor structure, and the
1732 * buffers it contains. These are used to contain the descriptors used
1733 * by the system.
1734*/
1735int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1736 struct list_head *head, const char *name,
1737 int nbuf, int ndesc)
1738{
1739#define DS2PHYS(_dd, _ds) \
1740 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1741#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1742#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1743
1744 struct ath_desc *ds;
1745 struct ath_buf *bf;
1746 int i, bsize, error;
1747
04bd4638
S		 1748 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1749 name, nbuf, ndesc);
ff37e337
S		 1750
1751 /* ath_desc must be a multiple of DWORDs */
1752 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1753 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1754 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1755 error = -ENOMEM;
1756 goto fail;
1757 }
1758
1759 dd->dd_name = name;
1760 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1761
1762 /*
1763 * Need additional DMA memory because we can't use
1764 * descriptors that cross the 4K page boundary. Assume
1765 * one skipped descriptor per 4K page.
1766 */
2660b81a 1767 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1768 u32 ndesc_skipped =
1769 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1770 u32 dma_len;
1771
1772 while (ndesc_skipped) {
1773 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1774 dd->dd_desc_len += dma_len;
1775
1776 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1777 };
1778 }
1779
1780 /* allocate descriptors */
7da3c55c
GJ		 1781 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1782 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1783 if (dd->dd_desc == NULL) {
1784 error = -ENOMEM;
1785 goto fail;
1786 }
1787 ds = dd->dd_desc;
04bd4638
S		 1788 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1789 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1790 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1791
1792 /* allocate buffers */
1793 bsize = sizeof(struct ath_buf) * nbuf;
1794 bf = kmalloc(bsize, GFP_KERNEL);
1795 if (bf == NULL) {
1796 error = -ENOMEM;
1797 goto fail2;
1798 }
1799 memset(bf, 0, bsize);
1800 dd->dd_bufptr = bf;
1801
1802 INIT_LIST_HEAD(head);
1803 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1804 bf->bf_desc = ds;
1805 bf->bf_daddr = DS2PHYS(dd, ds);
1806
2660b81a 1807 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1808 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1809 /*
1810 * Skip descriptor addresses which can cause 4KB
1811 * boundary crossing (addr + length) with a 32 dword
1812 * descriptor fetch.
1813 */
1814 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1815 ASSERT((caddr_t) bf->bf_desc <
1816 ((caddr_t) dd->dd_desc +
1817 dd->dd_desc_len));
1818
1819 ds += ndesc;
1820 bf->bf_desc = ds;
1821 bf->bf_daddr = DS2PHYS(dd, ds);
1822 }
1823 }
1824 list_add_tail(&bf->list, head);
1825 }
1826 return 0;
1827fail2:
7da3c55c
GJ		 1828 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1829 dd->dd_desc_paddr);
ff37e337
S		 1830fail:
1831 memset(dd, 0, sizeof(*dd));
1832 return error;
1833#undef ATH_DESC_4KB_BOUND_CHECK
1834#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1835#undef DS2PHYS
1836}
1837
1838void ath_descdma_cleanup(struct ath_softc *sc,
1839 struct ath_descdma *dd,
1840 struct list_head *head)
1841{
7da3c55c
GJ		 1842 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1843 dd->dd_desc_paddr);
ff37e337
S		 1844
1845 INIT_LIST_HEAD(head);
1846 kfree(dd->dd_bufptr);
1847 memset(dd, 0, sizeof(*dd));
1848}
1849
1850int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1851{
1852 int qnum;
1853
1854 switch (queue) {
1855 case 0:
b77f483f 1856 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1857 break;
1858 case 1:
b77f483f 1859 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1860 break;
1861 case 2:
b77f483f 1862 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1863 break;
1864 case 3:
b77f483f 1865 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1866 break;
1867 default:
b77f483f 1868 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1869 break;
1870 }
1871
1872 return qnum;
1873}
1874
1875int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1876{
1877 int qnum;
1878
1879 switch (queue) {
1880 case ATH9K_WME_AC_VO:
1881 qnum = 0;
1882 break;
1883 case ATH9K_WME_AC_VI:
1884 qnum = 1;
1885 break;
1886 case ATH9K_WME_AC_BE:
1887 qnum = 2;
1888 break;
1889 case ATH9K_WME_AC_BK:
1890 qnum = 3;
1891 break;
1892 default:
1893 qnum = -1;
1894 break;
1895 }
1896
1897 return qnum;
1898}
1899
5f8e077c
LR		 1900/* XXX: Remove me once we don't depend on ath9k_channel for all
1901 * this redundant data */
1902static void ath9k_update_ichannel(struct ath_softc *sc,
1903 struct ath9k_channel *ichan)
1904{
1905 struct ieee80211_hw *hw = sc->hw;
1906 struct ieee80211_channel *chan = hw->conf.channel;
1907 struct ieee80211_conf *conf = &hw->conf;
1908
1909 ichan->channel = chan->center_freq;
1910 ichan->chan = chan;
1911
1912 if (chan->band == IEEE80211_BAND_2GHZ) {
1913 ichan->chanmode = CHANNEL_G;
1914 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1915 } else {
1916 ichan->chanmode = CHANNEL_A;
1917 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1918 }
1919
1920 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1921
1922 if (conf_is_ht(conf)) {
1923 if (conf_is_ht40(conf))
1924 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1925
1926 ichan->chanmode = ath_get_extchanmode(sc, chan,
1927 conf->channel_type);
1928 }
1929}
1930
ff37e337
S		 1931/**********************/
1932/* mac80211 callbacks */
1933/**********************/
1934
8feceb67 1935static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1936{
bce048d7
JM		 1937 struct ath_wiphy *aphy = hw->priv;
1938 struct ath_softc *sc = aphy->sc;
8feceb67 1939 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1940 struct ath9k_channel *init_channel;
ae8d2858 1941 int r, pos;
f078f209 1942
04bd4638
S		 1943 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1944 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1945
141b38b6
S		 1946 mutex_lock(&sc->mutex);
1947
8feceb67 1948 /* setup initial channel */
f078f209 1949
5f8e077c 1950 pos = curchan->hw_value;
f078f209 1951
2660b81a 1952 init_channel = &sc->sc_ah->channels[pos];
5f8e077c 1953 ath9k_update_ichannel(sc, init_channel);
ff37e337
S		 1954
1955 /* Reset SERDES registers */
1956 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1957
1958 /*
1959 * The basic interface to setting the hardware in a good
1960 * state is ``reset''. On return the hardware is known to
1961 * be powered up and with interrupts disabled. This must
1962 * be followed by initialization of the appropriate bits
1963 * and then setup of the interrupt mask.
1964 */
1965 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1966 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1967 if (r) {
ff37e337 1968 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1969 "Unable to reset hardware; reset status %u "
1970 "(freq %u MHz)\n", r,
1971 curchan->center_freq);
ff37e337 1972 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1973 goto mutex_unlock;
ff37e337
S		 1974 }
1975 spin_unlock_bh(&sc->sc_resetlock);
1976
1977 /*
1978 * This is needed only to setup initial state
1979 * but it's best done after a reset.
1980 */
1981 ath_update_txpow(sc);
8feceb67 1982
ff37e337
S		 1983 /*
1984 * Setup the hardware after reset:
1985 * The receive engine is set going.
1986 * Frame transmit is handled entirely
1987 * in the frame output path; there's nothing to do
1988 * here except setup the interrupt mask.
1989 */
1990 if (ath_startrecv(sc) != 0) {
8feceb67 1991 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1992 "Unable to start recv logic\n");
141b38b6
S		 1993 r = -EIO;
1994 goto mutex_unlock;
f078f209 1995 }
8feceb67 1996
ff37e337 1997 /* Setup our intr mask. */
17d7904d 1998 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1999 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2000 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2001
2660b81a 2002 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2003 sc->imask |= ATH9K_INT_GTT;
ff37e337 2004
2660b81a 2005 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2006 sc->imask |= ATH9K_INT_CST;
ff37e337 2007
ce111bad 2008 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2009
2010 sc->sc_flags &= ~SC_OP_INVALID;
2011
2012 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2013 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2014 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2015
bce048d7 2016 ieee80211_wake_queues(hw);
ff37e337 2017
e97275cb 2018#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2019 r = ath_start_rfkill_poll(sc);
500c064d 2020#endif
141b38b6
S		 2021
2022mutex_unlock:
2023 mutex_unlock(&sc->mutex);
2024
ae8d2858 2025 return r;
f078f209
LR		 2026}
2027
8feceb67
VT		 2028static int ath9k_tx(struct ieee80211_hw *hw,
2029 struct sk_buff *skb)
f078f209 2030{
528f0c6b 2031 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2032 struct ath_wiphy *aphy = hw->priv;
2033 struct ath_softc *sc = aphy->sc;
528f0c6b 2034 struct ath_tx_control txctl;
8feceb67 2035 int hdrlen, padsize;
528f0c6b
S		 2036
2037 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2038
8feceb67
VT		 2039 /*
2040 * As a temporary workaround, assign seq# here; this will likely need
2041 * to be cleaned up to work better with Beacon transmission and virtual
2042 * BSSes.
2043 */
2044 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2045 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2046 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2047 sc->tx.seq_no += 0x10;
8feceb67 2048 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2049 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2050 }
f078f209 2051
8feceb67
VT		 2052 /* Add the padding after the header if this is not already done */
2053 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2054 if (hdrlen & 3) {
2055 padsize = hdrlen % 4;
2056 if (skb_headroom(skb) < padsize)
2057 return -1;
2058 skb_push(skb, padsize);
2059 memmove(skb->data, skb->data + padsize, hdrlen);
2060 }
2061
528f0c6b
S		 2062 /* Check if a tx queue is available */
2063
2064 txctl.txq = ath_test_get_txq(sc, skb);
2065 if (!txctl.txq)
2066 goto exit;
2067
04bd4638 2068 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2069
528f0c6b 2070 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2071 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2072 goto exit;
8feceb67
VT		 2073 }
2074
528f0c6b
S		 2075 return 0;
2076exit:
2077 dev_kfree_skb_any(skb);
8feceb67 2078 return 0;
f078f209
LR		 2079}
2080
8feceb67 2081static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2082{
bce048d7
JM		 2083 struct ath_wiphy *aphy = hw->priv;
2084 struct ath_softc *sc = aphy->sc;
f078f209 2085
9c84b797 2086 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2087 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2088 return;
2089 }
8feceb67 2090
141b38b6 2091 mutex_lock(&sc->mutex);
ff37e337 2092
bce048d7 2093 ieee80211_stop_queues(hw);
ff37e337
S		 2094
2095 /* make sure h/w will not generate any interrupt
2096 * before setting the invalid flag. */
2097 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2098
2099 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2100 ath_drain_all_txq(sc, false);
ff37e337
S		 2101 ath_stoprecv(sc);
2102 ath9k_hw_phy_disable(sc->sc_ah);
2103 } else
b77f483f 2104 sc->rx.rxlink = NULL;
ff37e337
S		 2105
2106#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2107 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2108 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2109#endif
2110 /* disable HAL and put h/w to sleep */
2111 ath9k_hw_disable(sc->sc_ah);
2112 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2113
2114 sc->sc_flags |= SC_OP_INVALID;
500c064d 2115
141b38b6
S		 2116 mutex_unlock(&sc->mutex);
2117
04bd4638 2118 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2119}
2120
8feceb67
VT		 2121static int ath9k_add_interface(struct ieee80211_hw *hw,
2122 struct ieee80211_if_init_conf *conf)
f078f209 2123{
bce048d7
JM		 2124 struct ath_wiphy *aphy = hw->priv;
2125 struct ath_softc *sc = aphy->sc;
17d7904d 2126 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2127 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2128 int ret = 0;
8feceb67 2129
141b38b6
S		 2130 mutex_lock(&sc->mutex);
2131
8ca21f01
JM		 2132 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2133 sc->nvifs > 0) {
2134 ret = -ENOBUFS;
2135 goto out;
2136 }
2137
8feceb67 2138 switch (conf->type) {
05c914fe 2139 case NL80211_IFTYPE_STATION:
d97809db 2140 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2141 break;
05c914fe 2142 case NL80211_IFTYPE_ADHOC:
2c3db3d5
JM		 2143 if (sc->nbcnvifs >= ATH_BCBUF) {
2144 ret = -ENOBUFS;
2145 goto out;
2146 }
d97809db 2147 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2148 break;
05c914fe 2149 case NL80211_IFTYPE_AP:
2c3db3d5
JM		 2150 if (sc->nbcnvifs >= ATH_BCBUF) {
2151 ret = -ENOBUFS;
2152 goto out;
2153 }
d97809db 2154 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2155 break;
2156 default:
2157 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2158 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2159 ret = -EOPNOTSUPP;
2160 goto out;
f078f209
LR		 2161 }
2162
17d7904d 2163 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2164
17d7904d 2165 /* Set the VIF opmode */
5640b08e
S		 2166 avp->av_opmode = ic_opmode;
2167 avp->av_bslot = -1;
2168
2c3db3d5 2169 sc->nvifs++;
8ca21f01
JM		 2170
2171 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2172 ath9k_set_bssid_mask(hw);
2173
2c3db3d5
JM		 2174 if (sc->nvifs > 1)
2175 goto out; /* skip global settings for secondary vif */
2176
b238e90e 2177 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2178 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2179 sc->sc_flags |= SC_OP_TSF_RESET;
2180 }
5640b08e 2181
5640b08e 2182 /* Set the device opmode */
2660b81a 2183 sc->sc_ah->opmode = ic_opmode;
5640b08e 2184
4e30ffa2
VN		 2185 /*
2186 * Enable MIB interrupts when there are hardware phy counters.
2187 * Note we only do this (at the moment) for station mode.
2188 */
4af9cf4f
S		 2189 if ((conf->type == NL80211_IFTYPE_STATION) ||
2190 (conf->type == NL80211_IFTYPE_ADHOC)) {
2191 if (ath9k_hw_phycounters(sc->sc_ah))
2192 sc->imask |= ATH9K_INT_MIB;
2193 sc->imask |= ATH9K_INT_TSFOOR;
2194 }
2195
4e30ffa2
VN		 2196 /*
2197 * Some hardware processes the TIM IE and fires an
2198 * interrupt when the TIM bit is set. For hardware
2199 * that does, if not overridden by configuration,
2200 * enable the TIM interrupt when operating as station.
2201 */
2660b81a 2202 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
4e30ffa2 2203 (conf->type == NL80211_IFTYPE_STATION) &&
17d7904d
S		 2204 !sc->config.swBeaconProcess)
2205 sc->imask |= ATH9K_INT_TIM;
4e30ffa2 2206
17d7904d 2207 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2208
6f255425
LR		 2209 if (conf->type == NL80211_IFTYPE_AP) {
2210 /* TODO: is this a suitable place to start ANI for AP mode? */
2211 /* Start ANI */
17d7904d 2212 mod_timer(&sc->ani.timer,
6f255425
LR		 2213 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2214 }
2215
2c3db3d5 2216out:
141b38b6 2217 mutex_unlock(&sc->mutex);
2c3db3d5 2218 return ret;
f078f209
LR		 2219}
2220
8feceb67
VT		 2221static void ath9k_remove_interface(struct ieee80211_hw *hw,
2222 struct ieee80211_if_init_conf *conf)
f078f209 2223{
bce048d7
JM		 2224 struct ath_wiphy *aphy = hw->priv;
2225 struct ath_softc *sc = aphy->sc;
17d7904d 2226 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2227 int i;
f078f209 2228
04bd4638 2229 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2230
141b38b6
S		 2231 mutex_lock(&sc->mutex);
2232
6f255425 2233 /* Stop ANI */
17d7904d 2234 del_timer_sync(&sc->ani.timer);
580f0b8a 2235
8feceb67 2236 /* Reclaim beacon resources */
2660b81a
S		 2237 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2238 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2239 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2240 ath_beacon_return(sc, avp);
580f0b8a 2241 }
f078f209 2242
8feceb67 2243 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2244
2c3db3d5
JM		 2245 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2246 if (sc->beacon.bslot[i] == conf->vif) {
2247 printk(KERN_DEBUG "%s: vif had allocated beacon "
2248 "slot\n", __func__);
2249 sc->beacon.bslot[i] = NULL;
2250 }
2251 }
2252
17d7904d 2253 sc->nvifs--;
141b38b6
S		 2254
2255 mutex_unlock(&sc->mutex);
f078f209
LR		 2256}
2257
e8975581 2258static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2259{
bce048d7
JM		 2260 struct ath_wiphy *aphy = hw->priv;
2261 struct ath_softc *sc = aphy->sc;
e8975581 2262 struct ieee80211_conf *conf = &hw->conf;
f078f209 2263
aa33de09 2264 mutex_lock(&sc->mutex);
141b38b6 2265
3cbb5dd7
VN		 2266 if (changed & IEEE80211_CONF_CHANGE_PS) {
2267 if (conf->flags & IEEE80211_CONF_PS) {
17d7904d
S		 2268 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2269 sc->imask |= ATH9K_INT_TIM_TIMER;
3cbb5dd7 2270 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2271 sc->imask);
3cbb5dd7
VN		 2272 }
2273 ath9k_hw_setrxabort(sc->sc_ah, 1);
2274 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2275 } else {
2276 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2277 ath9k_hw_setrxabort(sc->sc_ah, 0);
2278 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
17d7904d
S		 2279 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2280 sc->imask &= ~ATH9K_INT_TIM_TIMER;
3cbb5dd7 2281 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2282 sc->imask);
3cbb5dd7
VN		 2283 }
2284 }
2285 }
2286
4797938c 2287 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2288 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2289 int pos = curchan->hw_value;
ae5eb026 2290
04bd4638
S		 2291 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2292 curchan->center_freq);
f078f209 2293
5f8e077c 2294 /* XXX: remove me eventualy */
2660b81a 2295 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
e11602b7 2296
ecf70441 2297 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2298
2660b81a 2299 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2300 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2301 mutex_unlock(&sc->mutex);
e11602b7
S		 2302 return -EINVAL;
2303 }
094d05dc 2304 }
f078f209 2305
5c020dc6 2306 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2307 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2308
b238e90e
S		 2309 /*
2310 * The HW TSF has to be reset when the beacon interval changes.
2311 * We set the flag here, and ath_beacon_config_ap() would take this
2312 * into account when it gets called through the subsequent
2313 * config_interface() call - with IFCC_BEACON in the changed field.
2314 */
2315
2316 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2317 sc->sc_flags |= SC_OP_TSF_RESET;
2318
aa33de09 2319 mutex_unlock(&sc->mutex);
141b38b6 2320
f078f209
LR		 2321 return 0;
2322}
2323
8feceb67
VT		 2324static int ath9k_config_interface(struct ieee80211_hw *hw,
2325 struct ieee80211_vif *vif,
2326 struct ieee80211_if_conf *conf)
c83be688 2327{
bce048d7
JM		 2328 struct ath_wiphy *aphy = hw->priv;
2329 struct ath_softc *sc = aphy->sc;
cbe61d8a 2330 struct ath_hw *ah = sc->sc_ah;
17d7904d 2331 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2332 u32 rfilt = 0;
2333 int error, i;
c83be688 2334
2554935b
S		 2335 mutex_lock(&sc->mutex);
2336
8feceb67
VT		 2337 /* TODO: Need to decide which hw opmode to use for multi-interface
2338 * cases */
05c914fe 2339 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2340 ah->opmode != NL80211_IFTYPE_AP) {
2341 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2342 ath9k_hw_setopmode(ah);
ba52da58
S		 2343 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2344 sc->curaid = 0;
2345 ath9k_hw_write_associd(sc);
8feceb67
VT		 2346 /* Request full reset to get hw opmode changed properly */
2347 sc->sc_flags |= SC_OP_FULL_RESET;
2348 }
c83be688 2349
8feceb67
VT		 2350 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2351 !is_zero_ether_addr(conf->bssid)) {
2352 switch (vif->type) {
05c914fe
JB		 2353 case NL80211_IFTYPE_STATION:
2354 case NL80211_IFTYPE_ADHOC:
8feceb67 2355 /* Set BSSID */
17d7904d
S		 2356 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2357 sc->curaid = 0;
ba52da58 2358 ath9k_hw_write_associd(sc);
c83be688 2359
8feceb67 2360 /* Set aggregation protection mode parameters */
17d7904d 2361 sc->config.ath_aggr_prot = 0;
c83be688 2362
8feceb67 2363 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2364 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2365 rfilt, sc->curbssid, sc->curaid);
c83be688 2366
8feceb67
VT		 2367 /* need to reconfigure the beacon */
2368 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2369
8feceb67
VT		 2370 break;
2371 default:
2372 break;
2373 }
2374 }
c83be688 2375
1f7d6cbf
S		 2376 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2377 (vif->type == NL80211_IFTYPE_AP)) {
2378 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2379 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2380 conf->enable_beacon)) {
2381 /*
2382 * Allocate and setup the beacon frame.
2383 *
2384 * Stop any previous beacon DMA. This may be
2385 * necessary, for example, when an ibss merge
2386 * causes reconfiguration; we may be called
2387 * with beacon transmission active.
2388 */
2389 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2390
2c3db3d5 2391 error = ath_beacon_alloc(sc, vif);
2554935b
S		 2392 if (error != 0) {
2393 mutex_unlock(&sc->mutex);
1f7d6cbf 2394 return error;
2554935b 2395 }
c83be688 2396
2c3db3d5 2397 ath_beacon_config(sc, vif);
1f7d6cbf 2398 }
8feceb67 2399 }
c83be688 2400
8feceb67 2401 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2402 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2403 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2404 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2405 ath9k_hw_keysetmac(sc->sc_ah,
2406 (u16)i,
17d7904d 2407 sc->curbssid);
8feceb67 2408 }
c83be688 2409
8feceb67 2410 /* Only legacy IBSS for now */
05c914fe 2411 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2412 ath_update_chainmask(sc, 0);
f078f209 2413
2554935b
S		 2414 mutex_unlock(&sc->mutex);
2415
8feceb67
VT		 2416 return 0;
2417}
f078f209 2418
8feceb67
VT		 2419#define SUPPORTED_FILTERS \
2420 (FIF_PROMISC_IN_BSS | \
2421 FIF_ALLMULTI | \
2422 FIF_CONTROL | \
2423 FIF_OTHER_BSS | \
2424 FIF_BCN_PRBRESP_PROMISC | \
2425 FIF_FCSFAIL)
c83be688 2426
8feceb67
VT		 2427/* FIXME: sc->sc_full_reset ? */
2428static void ath9k_configure_filter(struct ieee80211_hw *hw,
2429 unsigned int changed_flags,
2430 unsigned int *total_flags,
2431 int mc_count,
2432 struct dev_mc_list *mclist)
2433{
bce048d7
JM		 2434 struct ath_wiphy *aphy = hw->priv;
2435 struct ath_softc *sc = aphy->sc;
8feceb67 2436 u32 rfilt;
f078f209 2437
8feceb67
VT		 2438 changed_flags &= SUPPORTED_FILTERS;
2439 *total_flags &= SUPPORTED_FILTERS;
f078f209 2440
b77f483f 2441 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2442 rfilt = ath_calcrxfilter(sc);
2443 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2444
b77f483f 2445 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2446}
f078f209 2447
8feceb67
VT		 2448static void ath9k_sta_notify(struct ieee80211_hw *hw,
2449 struct ieee80211_vif *vif,
2450 enum sta_notify_cmd cmd,
17741cdc 2451 struct ieee80211_sta *sta)
8feceb67 2452{
bce048d7
JM		 2453 struct ath_wiphy *aphy = hw->priv;
2454 struct ath_softc *sc = aphy->sc;
f078f209 2455
8feceb67
VT		 2456 switch (cmd) {
2457 case STA_NOTIFY_ADD:
5640b08e 2458 ath_node_attach(sc, sta);
8feceb67
VT		 2459 break;
2460 case STA_NOTIFY_REMOVE:
b5aa9bf9 2461 ath_node_detach(sc, sta);
8feceb67
VT		 2462 break;
2463 default:
2464 break;
2465 }
f078f209
LR		 2466}
2467
141b38b6 2468static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2469 const struct ieee80211_tx_queue_params *params)
f078f209 2470{
bce048d7
JM		 2471 struct ath_wiphy *aphy = hw->priv;
2472 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2473 struct ath9k_tx_queue_info qi;
2474 int ret = 0, qnum;
f078f209 2475
8feceb67
VT		 2476 if (queue >= WME_NUM_AC)
2477 return 0;
f078f209 2478
141b38b6
S		 2479 mutex_lock(&sc->mutex);
2480
8feceb67
VT		 2481 qi.tqi_aifs = params->aifs;
2482 qi.tqi_cwmin = params->cw_min;
2483 qi.tqi_cwmax = params->cw_max;
2484 qi.tqi_burstTime = params->txop;
2485 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2486
8feceb67 2487 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2488 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2489 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2490 queue, qnum, params->aifs, params->cw_min,
2491 params->cw_max, params->txop);
f078f209 2492
8feceb67
VT		 2493 ret = ath_txq_update(sc, qnum, &qi);
2494 if (ret)
04bd4638 2495 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2496
141b38b6
S		 2497 mutex_unlock(&sc->mutex);
2498
8feceb67
VT		 2499 return ret;
2500}
f078f209 2501
8feceb67
VT		 2502static int ath9k_set_key(struct ieee80211_hw *hw,
2503 enum set_key_cmd cmd,
dc822b5d
JB		 2504 struct ieee80211_vif *vif,
2505 struct ieee80211_sta *sta,
8feceb67
VT		 2506 struct ieee80211_key_conf *key)
2507{
bce048d7
JM		 2508 struct ath_wiphy *aphy = hw->priv;
2509 struct ath_softc *sc = aphy->sc;
8feceb67 2510 int ret = 0;
f078f209 2511
b3bd89ce
JM		 2512 if (modparam_nohwcrypt)
2513 return -ENOSPC;
2514
141b38b6 2515 mutex_lock(&sc->mutex);
3cbb5dd7 2516 ath9k_ps_wakeup(sc);
04bd4638 2517 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2518
8feceb67
VT		 2519 switch (cmd) {
2520 case SET_KEY:
3f53dd64 2521 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2522 if (ret >= 0) {
2523 key->hw_key_idx = ret;
8feceb67
VT		 2524 /* push IV and Michael MIC generation to stack */
2525 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2526 if (key->alg == ALG_TKIP)
2527 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2528 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2529 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2530 ret = 0;
8feceb67
VT		 2531 }
2532 break;
2533 case DISABLE_KEY:
2534 ath_key_delete(sc, key);
8feceb67
VT		 2535 break;
2536 default:
2537 ret = -EINVAL;
2538 }
f078f209 2539
3cbb5dd7 2540 ath9k_ps_restore(sc);
141b38b6
S		 2541 mutex_unlock(&sc->mutex);
2542
8feceb67
VT		 2543 return ret;
2544}
f078f209 2545
8feceb67
VT		 2546static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2547 struct ieee80211_vif *vif,
2548 struct ieee80211_bss_conf *bss_conf,
2549 u32 changed)
2550{
bce048d7
JM		 2551 struct ath_wiphy *aphy = hw->priv;
2552 struct ath_softc *sc = aphy->sc;
f078f209 2553
141b38b6
S		 2554 mutex_lock(&sc->mutex);
2555
8feceb67 2556 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2557 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2558 bss_conf->use_short_preamble);
2559 if (bss_conf->use_short_preamble)
2560 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2561 else
2562 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2563 }
f078f209 2564
8feceb67 2565 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2566 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2567 bss_conf->use_cts_prot);
2568 if (bss_conf->use_cts_prot &&
2569 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2570 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2571 else
2572 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2573 }
f078f209 2574
8feceb67 2575 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2576 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2577 bss_conf->assoc);
5640b08e 2578 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2579 }
141b38b6
S		 2580
2581 mutex_unlock(&sc->mutex);
8feceb67 2582}
f078f209 2583
8feceb67
VT		 2584static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2585{
2586 u64 tsf;
bce048d7
JM		 2587 struct ath_wiphy *aphy = hw->priv;
2588 struct ath_softc *sc = aphy->sc;
f078f209 2589
141b38b6
S		 2590 mutex_lock(&sc->mutex);
2591 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2592 mutex_unlock(&sc->mutex);
f078f209 2593
8feceb67
VT		 2594 return tsf;
2595}
f078f209 2596
3b5d665b
AF		 2597static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2598{
bce048d7
JM		 2599 struct ath_wiphy *aphy = hw->priv;
2600 struct ath_softc *sc = aphy->sc;
3b5d665b 2601
141b38b6
S		 2602 mutex_lock(&sc->mutex);
2603 ath9k_hw_settsf64(sc->sc_ah, tsf);
2604 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2605}
2606
8feceb67
VT		 2607static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2608{
bce048d7
JM		 2609 struct ath_wiphy *aphy = hw->priv;
2610 struct ath_softc *sc = aphy->sc;
c83be688 2611
141b38b6
S		 2612 mutex_lock(&sc->mutex);
2613 ath9k_hw_reset_tsf(sc->sc_ah);
2614 mutex_unlock(&sc->mutex);
8feceb67 2615}
f078f209 2616
8feceb67 2617static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2618 enum ieee80211_ampdu_mlme_action action,
2619 struct ieee80211_sta *sta,
2620 u16 tid, u16 *ssn)
8feceb67 2621{
bce048d7
JM		 2622 struct ath_wiphy *aphy = hw->priv;
2623 struct ath_softc *sc = aphy->sc;
8feceb67 2624 int ret = 0;
f078f209 2625
8feceb67
VT		 2626 switch (action) {
2627 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2628 if (!(sc->sc_flags & SC_OP_RXAGGR))
2629 ret = -ENOTSUPP;
8feceb67
VT		 2630 break;
2631 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2632 break;
2633 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2634 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2635 if (ret < 0)
2636 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2637 "Unable to start TX aggregation\n");
8feceb67 2638 else
17741cdc 2639 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2640 break;
2641 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2642 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2643 if (ret < 0)
2644 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2645 "Unable to stop TX aggregation\n");
f078f209 2646
17741cdc 2647 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2648 break;
8469cdef
S		 2649 case IEEE80211_AMPDU_TX_RESUME:
2650 ath_tx_aggr_resume(sc, sta, tid);
2651 break;
8feceb67 2652 default:
04bd4638 2653 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2654 }
2655
2656 return ret;
f078f209
LR		 2657}
2658
0c98de65
S		 2659static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2660{
bce048d7
JM		 2661 struct ath_wiphy *aphy = hw->priv;
2662 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2663
2664 mutex_lock(&sc->mutex);
2665 sc->sc_flags |= SC_OP_SCANNING;
2666 mutex_unlock(&sc->mutex);
2667}
2668
2669static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2670{
bce048d7
JM		 2671 struct ath_wiphy *aphy = hw->priv;
2672 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2673
2674 mutex_lock(&sc->mutex);
2675 sc->sc_flags &= ~SC_OP_SCANNING;
2676 mutex_unlock(&sc->mutex);
2677}
2678
6baff7f9 2679struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2680 .tx = ath9k_tx,
2681 .start = ath9k_start,
2682 .stop = ath9k_stop,
2683 .add_interface = ath9k_add_interface,
2684 .remove_interface = ath9k_remove_interface,
2685 .config = ath9k_config,
2686 .config_interface = ath9k_config_interface,
2687 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2688 .sta_notify = ath9k_sta_notify,
2689 .conf_tx = ath9k_conf_tx,
8feceb67 2690 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2691 .set_key = ath9k_set_key,
8feceb67 2692 .get_tsf = ath9k_get_tsf,
3b5d665b 2693 .set_tsf = ath9k_set_tsf,
8feceb67 2694 .reset_tsf = ath9k_reset_tsf,
4233df6b 2695 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2696 .sw_scan_start = ath9k_sw_scan_start,
2697 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2698};
2699
392dff83
BP		 2700static struct {
2701 u32 version;
2702 const char * name;
2703} ath_mac_bb_names[] = {
2704 { AR_SREV_VERSION_5416_PCI, "5416" },
2705 { AR_SREV_VERSION_5416_PCIE, "5418" },
2706 { AR_SREV_VERSION_9100, "9100" },
2707 { AR_SREV_VERSION_9160, "9160" },
2708 { AR_SREV_VERSION_9280, "9280" },
2709 { AR_SREV_VERSION_9285, "9285" }
2710};
2711
2712static struct {
2713 u16 version;
2714 const char * name;
2715} ath_rf_names[] = {
2716 { 0, "5133" },
2717 { AR_RAD5133_SREV_MAJOR, "5133" },
2718 { AR_RAD5122_SREV_MAJOR, "5122" },
2719 { AR_RAD2133_SREV_MAJOR, "2133" },
2720 { AR_RAD2122_SREV_MAJOR, "2122" }
2721};
2722
2723/*
2724 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2725 */
6baff7f9 2726const char *
392dff83
BP		 2727ath_mac_bb_name(u32 mac_bb_version)
2728{
2729 int i;
2730
2731 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2732 if (ath_mac_bb_names[i].version == mac_bb_version) {
2733 return ath_mac_bb_names[i].name;
2734 }
2735 }
2736
2737 return "????";
2738}
2739
2740/*
2741 * Return the RF name. "????" is returned if the RF is unknown.
2742 */
6baff7f9 2743const char *
392dff83
BP		 2744ath_rf_name(u16 rf_version)
2745{
2746 int i;
2747
2748 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2749 if (ath_rf_names[i].version == rf_version) {
2750 return ath_rf_names[i].name;
2751 }
2752 }
2753
2754 return "????";
2755}
2756
6baff7f9 2757static int __init ath9k_init(void)
f078f209 2758{
ca8a8560
VT		 2759 int error;
2760
ca8a8560
VT		 2761 /* Register rate control algorithm */
2762 error = ath_rate_control_register();
2763 if (error != 0) {
2764 printk(KERN_ERR
b51bb3cd
LR		 2765 "ath9k: Unable to register rate control "
2766 "algorithm: %d\n",
ca8a8560 2767 error);
6baff7f9 2768 goto err_out;
ca8a8560
VT		 2769 }
2770
6baff7f9
GJ		 2771 error = ath_pci_init();
2772 if (error < 0) {
f078f209 2773 printk(KERN_ERR
b51bb3cd 2774 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ		 2775 error = -ENODEV;
2776 goto err_rate_unregister;
f078f209
LR		 2777 }
2778
09329d37
GJ		 2779 error = ath_ahb_init();
2780 if (error < 0) {
2781 error = -ENODEV;
2782 goto err_pci_exit;
2783 }
2784
f078f209 2785 return 0;
6baff7f9 2786
09329d37
GJ		 2787 err_pci_exit:
2788 ath_pci_exit();
2789
6baff7f9
GJ		 2790 err_rate_unregister:
2791 ath_rate_control_unregister();
2792 err_out:
2793 return error;
f078f209 2794}
6baff7f9 2795module_init(ath9k_init);
f078f209 2796
6baff7f9 2797static void __exit ath9k_exit(void)
f078f209 2798{
09329d37 2799 ath_ahb_exit();
6baff7f9 2800 ath_pci_exit();
ca8a8560 2801 ath_rate_control_unregister();
04bd4638 2802 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2803}
6baff7f9 2804module_exit(ath9k_exit);
kernel source for telekom puls (alcatel/mediatek)