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ath5k: more RF2413 stuff
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath5k / hw.c
CommitLineData
fa1c114f
JS		 1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23/*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27#include <linux/pci.h>
28#include <linux/delay.h>
29
30#include "reg.h"
31#include "base.h"
32#include "debug.h"
33
34/*Rate tables*/
35static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40
41/*Prototypes*/
42static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
45 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int);
b9887638 48static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
fa1c114f
JS		 49 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50 unsigned int);
51static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
52static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
53 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
54 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int);
56static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
57static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *, struct ath5k_desc *);
58static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *, struct ath5k_desc *);
59static int ath5k_hw_get_capabilities(struct ath5k_hw *);
60
61static int ath5k_eeprom_init(struct ath5k_hw *);
62static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
63
64static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
65static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
66
67/*
68 * Enable to overwrite the country code (use "00" for debug)
69 */
70#if 0
71#define COUNTRYCODE "00"
72#endif
73
74/*******************\
75 General Functions
76\*******************/
77
78/*
79 * Functions used internaly
80 */
81
82static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
83{
84 return turbo == true ? (usec * 80) : (usec * 40);
85}
86
87static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
88{
89 return turbo == true ? (clock / 80) : (clock / 40);
90}
91
92/*
93 * Check if a register write has been completed
94 */
95int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
96 bool is_set)
97{
98 int i;
99 u32 data;
100
101 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
102 data = ath5k_hw_reg_read(ah, reg);
103 if ((is_set == true) && (data & flag))
104 break;
105 else if ((data & flag) == val)
106 break;
107 udelay(15);
108 }
109
110 return (i <= 0) ? -EAGAIN : 0;
111}
112
113
114/***************************************\
115 Attach/Detach Functions
116\***************************************/
117
118/*
119 * Check if the device is supported and initialize the needed structs
120 */
121struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
122{
123 struct ath5k_hw *ah;
124 u8 mac[ETH_ALEN];
125 int ret;
126 u32 srev;
127
128 /*If we passed the test malloc a ath5k_hw struct*/
129 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
130 if (ah == NULL) {
131 ret = -ENOMEM;
132 ATH5K_ERR(sc, "out of memory\n");
133 goto err;
134 }
135
136 ah->ah_sc = sc;
137 ah->ah_iobase = sc->iobase;
138
139 /*
140 * HW information
141 */
142
fa1c114f
JS		 143 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
144 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
145 ah->ah_turbo = false;
146 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
147 ah->ah_imr = 0;
148 ah->ah_atim_window = 0;
149 ah->ah_aifs = AR5K_TUNE_AIFS;
150 ah->ah_cw_min = AR5K_TUNE_CWMIN;
151 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
152 ah->ah_software_retry = false;
153 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
154
155 /*
156 * Set the mac revision based on the pci id
157 */
158 ah->ah_version = mac_version;
159
160 /*Fill the ath5k_hw struct with the needed functions*/
161 if (ah->ah_version == AR5K_AR5212)
162 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
163 else if (ah->ah_version == AR5K_AR5211)
164 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
165
166 if (ah->ah_version == AR5K_AR5212) {
167 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
168 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
169 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
170 } else {
171 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
172 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
173 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
174 }
175
176 if (ah->ah_version == AR5K_AR5212)
177 ah->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status;
178 else if (ah->ah_version <= AR5K_AR5211)
179 ah->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status;
180
181 /* Bring device out of sleep and reset it's units */
182 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
183 if (ret)
184 goto err_free;
185
186 /* Get MAC, PHY and RADIO revisions */
187 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
188 ah->ah_mac_srev = srev;
189 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
190 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
191 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
192 0xffffffff;
193 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
194 CHANNEL_5GHZ);
195
196 if (ah->ah_version == AR5K_AR5210)
197 ah->ah_radio_2ghz_revision = 0;
198 else
199 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
200 CHANNEL_2GHZ);
201
202 /* Return on unsuported chips (unsupported eeprom etc) */
203 if(srev >= AR5K_SREV_VER_AR5416){
204 ATH5K_ERR(sc, "Device not yet supported.\n");
205 ret = -ENODEV;
206 goto err_free;
207 }
208
209 /* Identify single chip solutions */
210 if((srev <= AR5K_SREV_VER_AR5414) &&
0af22563 211 (srev >= AR5K_SREV_VER_AR2413)) {
fa1c114f
JS		 212 ah->ah_single_chip = true;
213 } else {
214 ah->ah_single_chip = false;
215 }
216
217 /* Single chip radio */
218 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
219 ah->ah_radio_2ghz_revision = 0;
220
221 /* Identify the radio chip*/
222 if (ah->ah_version == AR5K_AR5210) {
223 ah->ah_radio = AR5K_RF5110;
224 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
225 ah->ah_radio = AR5K_RF5111;
0af22563
NK		 226 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
227 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
228
fa1c114f 229 ah->ah_radio = AR5K_RF5112;
0af22563
NK		 230
231 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
232 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
233 } else {
234 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
235 }
236
237 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
238 ah->ah_radio = AR5K_RF2413;
239 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
fa1c114f 240 } else {
0af22563 241
fa1c114f 242 ah->ah_radio = AR5K_RF5413;
0af22563
NK		 243
244 if (ah->ah_mac_srev <= AR5K_SREV_VER_AR5424 &&
245 ah->ah_mac_srev >= AR5K_SREV_VER_AR2424)
246 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424;
247 else if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2425)
248 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
249 else
250 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
251
252
fa1c114f
JS		 253 }
254
255 ah->ah_phy = AR5K_PHY(0);
256
257 /*
258 * Get card capabilities, values, ...
259 */
260
261 ret = ath5k_eeprom_init(ah);
262 if (ret) {
263 ATH5K_ERR(sc, "unable to init EEPROM\n");
264 goto err_free;
265 }
266
267 /* Get misc capabilities */
268 ret = ath5k_hw_get_capabilities(ah);
269 if (ret) {
270 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
271 sc->pdev->device);
272 goto err_free;
273 }
274
275 /* Get MAC address */
276 ret = ath5k_eeprom_read_mac(ah, mac);
277 if (ret) {
278 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
279 sc->pdev->device);
280 goto err_free;
281 }
282
283 ath5k_hw_set_lladdr(ah, mac);
284 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
285 memset(ah->ah_bssid, 0xff, ETH_ALEN);
286 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
287 ath5k_hw_set_opmode(ah);
288
289 ath5k_hw_set_rfgain_opt(ah);
290
291 return ah;
292err_free:
293 kfree(ah);
294err:
295 return ERR_PTR(ret);
296}
297
298/*
299 * Bring up MAC + PHY Chips
300 */
301static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
302{
303 u32 turbo, mode, clock;
304 int ret;
305
306 turbo = 0;
307 mode = 0;
308 clock = 0;
309
310 ATH5K_TRACE(ah->ah_sc);
311
312 /* Wakeup the device */
313 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
314 if (ret) {
315 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
316 return ret;
317 }
318
319 if (ah->ah_version != AR5K_AR5210) {
320 /*
321 * Get channel mode flags
322 */
323
324 if (ah->ah_radio >= AR5K_RF5112) {
325 mode = AR5K_PHY_MODE_RAD_RF5112;
326 clock = AR5K_PHY_PLL_RF5112;
327 } else {
328 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
329 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
330 }
331
332 if (flags & CHANNEL_2GHZ) {
333 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
334 clock |= AR5K_PHY_PLL_44MHZ;
335
336 if (flags & CHANNEL_CCK) {
337 mode |= AR5K_PHY_MODE_MOD_CCK;
338 } else if (flags & CHANNEL_OFDM) {
339 /* XXX Dynamic OFDM/CCK is not supported by the
340 * AR5211 so we set MOD_OFDM for plain g (no
341 * CCK headers) operation. We need to test
342 * this, 5211 might support ofdm-only g after
343 * all, there are also initial register values
344 * in the code for g mode (see initvals.c). */
345 if (ah->ah_version == AR5K_AR5211)
346 mode |= AR5K_PHY_MODE_MOD_OFDM;
347 else
348 mode |= AR5K_PHY_MODE_MOD_DYN;
349 } else {
350 ATH5K_ERR(ah->ah_sc,
351 "invalid radio modulation mode\n");
352 return -EINVAL;
353 }
354 } else if (flags & CHANNEL_5GHZ) {
355 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
356 clock |= AR5K_PHY_PLL_40MHZ;
357
358 if (flags & CHANNEL_OFDM)
359 mode |= AR5K_PHY_MODE_MOD_OFDM;
360 else {
361 ATH5K_ERR(ah->ah_sc,
362 "invalid radio modulation mode\n");
363 return -EINVAL;
364 }
365 } else {
366 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
367 return -EINVAL;
368 }
369
370 if (flags & CHANNEL_TURBO)
371 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
372 } else { /* Reset the device */
373
374 /* ...enable Atheros turbo mode if requested */
375 if (flags & CHANNEL_TURBO)
376 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
377 AR5K_PHY_TURBO);
378 }
379
380 /* ...reset chipset and PCI device */
381 if (ah->ah_single_chip == false && ath5k_hw_nic_reset(ah,
382 AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) {
383 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip + PCI\n");
384 return -EIO;
385 }
386
387 if (ah->ah_version == AR5K_AR5210)
388 udelay(2300);
389
390 /* ...wakeup again!*/
391 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
392 if (ret) {
393 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
394 return ret;
395 }
396
397 /* ...final warm reset */
398 if (ath5k_hw_nic_reset(ah, 0)) {
399 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
400 return -EIO;
401 }
402
403 if (ah->ah_version != AR5K_AR5210) {
404 /* ...set the PHY operating mode */
405 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
406 udelay(300);
407
408 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
409 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
410 }
411
412 return 0;
413}
414
415/*
416 * Get the rate table for a specific operation mode
417 */
418const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
419 unsigned int mode)
420{
421 ATH5K_TRACE(ah->ah_sc);
422
423 if (!test_bit(mode, ah->ah_capabilities.cap_mode))
424 return NULL;
425
426 /* Get rate tables */
427 switch (mode) {
d8ee398d 428 case AR5K_MODE_11A:
fa1c114f 429 return &ath5k_rt_11a;
d8ee398d 430 case AR5K_MODE_11A_TURBO:
fa1c114f 431 return &ath5k_rt_turbo;
d8ee398d 432 case AR5K_MODE_11B:
fa1c114f 433 return &ath5k_rt_11b;
d8ee398d 434 case AR5K_MODE_11G:
fa1c114f 435 return &ath5k_rt_11g;
d8ee398d 436 case AR5K_MODE_11G_TURBO:
fa1c114f
JS		 437 return &ath5k_rt_xr;
438 }
439
440 return NULL;
441}
442
443/*
444 * Free the ath5k_hw struct
445 */
446void ath5k_hw_detach(struct ath5k_hw *ah)
447{
448 ATH5K_TRACE(ah->ah_sc);
449
450 if (ah->ah_rf_banks != NULL)
451 kfree(ah->ah_rf_banks);
452
453 /* assume interrupts are down */
454 kfree(ah);
455}
456
457/****************************\
458 Reset function and helpers
459\****************************/
460
461/**
462 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
463 *
464 * @ah: the &struct ath5k_hw
465 * @channel: the currently set channel upon reset
466 *
467 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
468 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
469 * depending on the bandwidth of the channel.
470 *
471 */
472static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
473 struct ieee80211_channel *channel)
474{
475 /* Get exponent and mantissa and set it */
476 u32 coef_scaled, coef_exp, coef_man,
477 ds_coef_exp, ds_coef_man, clock;
478
479 if (!(ah->ah_version == AR5K_AR5212) ||
d8ee398d 480 !(channel->hw_value & CHANNEL_OFDM))
fa1c114f
JS		 481 BUG();
482
483 /* Seems there are two PLLs, one for baseband sampling and one
484 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
485 * turbo. */
d8ee398d 486 clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
fa1c114f 487 coef_scaled = ((5 * (clock << 24)) / 2) /
d8ee398d 488 channel->center_freq;
fa1c114f
JS		 489
490 for (coef_exp = 31; coef_exp > 0; coef_exp--)
491 if ((coef_scaled >> coef_exp) & 0x1)
492 break;
493
494 if (!coef_exp)
495 return -EINVAL;
496
497 coef_exp = 14 - (coef_exp - 24);
498 coef_man = coef_scaled +
499 (1 << (24 - coef_exp - 1));
500 ds_coef_man = coef_man >> (24 - coef_exp);
501 ds_coef_exp = coef_exp - 16;
502
503 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
504 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
505 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
506 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
507
508 return 0;
509}
510
511/**
512 * ath5k_hw_write_rate_duration - set rate duration during hw resets
513 *
514 * @ah: the &struct ath5k_hw
d8ee398d 515 * @mode: one of enum ath5k_driver_mode
fa1c114f
JS		 516 *
517 * Write the rate duration table for the current mode upon hw reset. This
518 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
519 * an ACK timeout for the hardware for the current mode for each rate. The
520 * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps,
521 * and 11Mbps) have another register for the short preamble ACK timeout
522 * calculation.
523 *
524 */
525static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
d8ee398d 526 unsigned int mode)
fa1c114f
JS		 527{
528 struct ath5k_softc *sc = ah->ah_sc;
529 const struct ath5k_rate_table *rt;
d8ee398d 530 struct ieee80211_rate srate = {};
fa1c114f
JS		 531 unsigned int i;
532
533 /* Get rate table for the current operating mode */
d8ee398d 534 rt = ath5k_hw_get_rate_table(ah, mode);
fa1c114f
JS		 535
536 /* Write rate duration table */
537 for (i = 0; i < rt->rate_count; i++) {
538 const struct ath5k_rate *rate, *control_rate;
d8ee398d 539
fa1c114f
JS		 540 u32 reg;
541 u16 tx_time;
542
543 rate = &rt->rates[i];
544 control_rate = &rt->rates[rate->control_rate];
545
546 /* Set ACK timeout */
547 reg = AR5K_RATE_DUR(rate->rate_code);
548
d8ee398d
LR		 549 srate.bitrate = control_rate->rate_kbps/100;
550
fa1c114f
JS		 551 /* An ACK frame consists of 10 bytes. If you add the FCS,
552 * which ieee80211_generic_frame_duration() adds,
553 * its 14 bytes. Note we use the control rate and not the
554 * actual rate for this rate. See mac80211 tx.c
555 * ieee80211_duration() for a brief description of
556 * what rate we should choose to TX ACKs. */
38c07b43
PR		 557 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
558 sc->vif, 10, &srate));
fa1c114f
JS		 559
560 ath5k_hw_reg_write(ah, tx_time, reg);
561
562 if (!HAS_SHPREAMBLE(i))
563 continue;
564
565 /*
566 * We're not distinguishing short preamble here,
567 * This is true, all we'll get is a longer value here
568 * which is not necessarilly bad. We could use
569 * export ieee80211_frame_duration() but that needs to be
570 * fixed first to be properly used by mac802111 drivers:
571 *
572 * - remove erp stuff and let the routine figure ofdm
573 * erp rates
574 * - remove passing argument ieee80211_local as
575 * drivers don't have access to it
576 * - move drivers using ieee80211_generic_frame_duration()
577 * to this
578 */
579 ath5k_hw_reg_write(ah, tx_time,
580 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
581 }
582}
583
584/*
585 * Main reset function
586 */
587int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
588 struct ieee80211_channel *channel, bool change_channel)
589{
590 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
591 u32 data, s_seq, s_ant, s_led[3];
d8ee398d 592 unsigned int i, mode, freq, ee_mode, ant[2];
fa1c114f
JS		 593 int ret;
594
595 ATH5K_TRACE(ah->ah_sc);
596
597 s_seq = 0;
598 s_ant = 0;
599 ee_mode = 0;
600 freq = 0;
601 mode = 0;
602
603 /*
604 * Save some registers before a reset
605 */
606 /*DCU/Antenna selection not available on 5210*/
607 if (ah->ah_version != AR5K_AR5210) {
608 if (change_channel == true) {
609 /* Seq number for queue 0 -do this for all queues ? */
610 s_seq = ath5k_hw_reg_read(ah,
611 AR5K_QUEUE_DFS_SEQNUM(0));
612 /*Default antenna*/
613 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
614 }
615 }
616
617 /*GPIOs*/
618 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
619 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
620 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
621
622 if (change_channel == true && ah->ah_rf_banks != NULL)
623 ath5k_hw_get_rf_gain(ah);
624
625
626 /*Wakeup the device*/
d8ee398d 627 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
fa1c114f
JS		 628 if (ret)
629 return ret;
630
631 /*
632 * Initialize operating mode
633 */
634 ah->ah_op_mode = op_mode;
635
636 /*
637 * 5111/5112 Settings
638 * 5210 only comes with RF5110
639 */
640 if (ah->ah_version != AR5K_AR5210) {
641 if (ah->ah_radio != AR5K_RF5111 &&
642 ah->ah_radio != AR5K_RF5112 &&
903b474e
NK		 643 ah->ah_radio != AR5K_RF5413 &&
644 ah->ah_radio != AR5K_RF2413) {
fa1c114f
JS		 645 ATH5K_ERR(ah->ah_sc,
646 "invalid phy radio: %u\n", ah->ah_radio);
647 return -EINVAL;
648 }
649
d8ee398d 650 switch (channel->hw_value & CHANNEL_MODES) {
fa1c114f 651 case CHANNEL_A:
d8ee398d 652 mode = AR5K_MODE_11A;
fa1c114f
JS		 653 freq = AR5K_INI_RFGAIN_5GHZ;
654 ee_mode = AR5K_EEPROM_MODE_11A;
fa1c114f
JS		 655 break;
656 case CHANNEL_G:
d8ee398d 657 mode = AR5K_MODE_11G;
fa1c114f
JS		 658 freq = AR5K_INI_RFGAIN_2GHZ;
659 ee_mode = AR5K_EEPROM_MODE_11G;
fa1c114f
JS		 660 break;
661 case CHANNEL_B:
d8ee398d 662 mode = AR5K_MODE_11B;
fa1c114f
JS		 663 freq = AR5K_INI_RFGAIN_2GHZ;
664 ee_mode = AR5K_EEPROM_MODE_11B;
fa1c114f
JS		 665 break;
666 case CHANNEL_T:
d8ee398d 667 mode = AR5K_MODE_11A_TURBO;
fa1c114f
JS		 668 freq = AR5K_INI_RFGAIN_5GHZ;
669 ee_mode = AR5K_EEPROM_MODE_11A;
fa1c114f
JS		 670 break;
671 /*Is this ok on 5211 too ?*/
672 case CHANNEL_TG:
d8ee398d 673 mode = AR5K_MODE_11G_TURBO;
fa1c114f
JS		 674 freq = AR5K_INI_RFGAIN_2GHZ;
675 ee_mode = AR5K_EEPROM_MODE_11G;
fa1c114f
JS		 676 break;
677 case CHANNEL_XR:
678 if (ah->ah_version == AR5K_AR5211) {
679 ATH5K_ERR(ah->ah_sc,
680 "XR mode not available on 5211");
681 return -EINVAL;
682 }
d8ee398d 683 mode = AR5K_MODE_XR;
fa1c114f
JS		 684 freq = AR5K_INI_RFGAIN_5GHZ;
685 ee_mode = AR5K_EEPROM_MODE_11A;
fa1c114f
JS		 686 break;
687 default:
688 ATH5K_ERR(ah->ah_sc,
d8ee398d 689 "invalid channel: %d\n", channel->center_freq);
fa1c114f
JS		 690 return -EINVAL;
691 }
692
693 /* PHY access enable */
694 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
695
696 }
697
698 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
699 if (ret)
700 return ret;
701
702 /*
703 * 5211/5212 Specific
704 */
705 if (ah->ah_version != AR5K_AR5210) {
706 /*
707 * Write initial RF gain settings
708 * This should work for both 5111/5112
709 */
710 ret = ath5k_hw_rfgain(ah, freq);
711 if (ret)
712 return ret;
713
714 mdelay(1);
715
716 /*
717 * Write some more initial register settings
718 */
719 if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */
720 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
721
d8ee398d 722 if (channel->hw_value == CHANNEL_G)
fa1c114f
JS		 723 ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */
724 else
725 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83));
726
727 ath5k_hw_reg_write(ah, 0x000001b5, 0xa228); /* 0x000009b5 */
728 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
729 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);
730 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
731 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
732 }
733
734 /* Fix for first revision of the RF5112 RF chipset */
735 if (ah->ah_radio >= AR5K_RF5112 &&
736 ah->ah_radio_5ghz_revision <
737 AR5K_SREV_RAD_5112A) {
738 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
739 AR5K_PHY_CCKTXCTL);
d8ee398d 740 if (channel->hw_value & CHANNEL_5GHZ)
fa1c114f
JS		 741 data = 0xffb81020;
742 else
743 data = 0xffb80d20;
744 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
745 }
746
747 /*
748 * Set TX power (FIXME)
749 */
750 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
751 if (ret)
752 return ret;
753
132127e5
LR		 754 /* Write rate duration table only on AR5212 and if
755 * virtual interface has already been brought up
756 * XXX: rethink this after new mode changes to
757 * mac80211 are integrated */
758 if (ah->ah_version == AR5K_AR5212 &&
759 ah->ah_sc->vif != NULL)
d8ee398d 760 ath5k_hw_write_rate_duration(ah, mode);
fa1c114f
JS		 761
762 /*
763 * Write RF registers
764 * TODO:Does this work on 5211 (5111) ?
765 */
766 ret = ath5k_hw_rfregs(ah, channel, mode);
767 if (ret)
768 return ret;
769
770 /*
771 * Configure additional registers
772 */
773
774 /* Write OFDM timings on 5212*/
775 if (ah->ah_version == AR5K_AR5212 &&
d8ee398d 776 channel->hw_value & CHANNEL_OFDM) {
fa1c114f
JS		 777 ret = ath5k_hw_write_ofdm_timings(ah, channel);
778 if (ret)
779 return ret;
780 }
781
782 /*Enable/disable 802.11b mode on 5111
783 (enable 2111 frequency converter + CCK)*/
784 if (ah->ah_radio == AR5K_RF5111) {
d8ee398d 785 if (mode == AR5K_MODE_11B)
fa1c114f
JS		 786 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
787 AR5K_TXCFG_B_MODE);
788 else
789 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
790 AR5K_TXCFG_B_MODE);
791 }
792
793 /*
794 * Set channel and calibrate the PHY
795 */
796 ret = ath5k_hw_channel(ah, channel);
797 if (ret)
798 return ret;
799
800 /* Set antenna mode */
801 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44),
802 ah->ah_antenna[ee_mode][0], 0xfffffc06);
803
804 /*
805 * In case a fixed antenna was set as default
806 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
807 * registers.
808 */
809 if (s_ant != 0){
810 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
811 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
812 else /* 2 - Aux */
813 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
814 } else {
815 ant[0] = AR5K_ANT_FIXED_A;
816 ant[1] = AR5K_ANT_FIXED_B;
817 }
818
819 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
820 AR5K_PHY_ANT_SWITCH_TABLE_0);
821 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
822 AR5K_PHY_ANT_SWITCH_TABLE_1);
823
824 /* Commit values from EEPROM */
825 if (ah->ah_radio == AR5K_RF5111)
826 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
827 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
828
829 ath5k_hw_reg_write(ah,
830 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
831 AR5K_PHY(0x5a));
832
833 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11),
834 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
835 0xffffc07f);
836 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12),
837 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
838 0xfffc0fff);
839 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14),
840 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
841 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
842 0xffff0000);
843
844 ath5k_hw_reg_write(ah,
845 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
846 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
847 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
848 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
849
850 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a),
851 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
852 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19),
853 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
854 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01);
855
856 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
857 AR5K_PHY_IQ_CORR_ENABLE |
858 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
859 ee->ee_q_cal[ee_mode]);
860
861 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
862 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
863 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
864 ee->ee_margin_tx_rx[ee_mode]);
865
866 } else {
867 mdelay(1);
868 /* Disable phy and wait */
869 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
870 mdelay(1);
871 }
872
873 /*
874 * Restore saved values
875 */
876 /*DCU/Antenna selection not available on 5210*/
877 if (ah->ah_version != AR5K_AR5210) {
878 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
879 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
880 }
881 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
882 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
883 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
884
885 /*
886 * Misc
887 */
888 /* XXX: add ah->aid once mac80211 gives this to us */
889 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
890
891 ath5k_hw_set_opmode(ah);
892 /*PISR/SISR Not available on 5210*/
893 if (ah->ah_version != AR5K_AR5210) {
894 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
895 /* If we later allow tuning for this, store into sc structure */
896 data = AR5K_TUNE_RSSI_THRES |
897 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
898 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
899 }
900
901 /*
902 * Set Rx/Tx DMA Configuration
903 *(passing dma size not available on 5210)
904 */
905 if (ah->ah_version != AR5K_AR5210) {
906 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR,
907 AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE);
908 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW,
909 AR5K_DMASIZE_512B);
910 }
911
912 /*
913 * Enable the PHY and wait until completion
914 */
915 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
916
917 /*
918 * 5111/5112 Specific
919 */
920 if (ah->ah_version != AR5K_AR5210) {
921 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
922 AR5K_PHY_RX_DELAY_M;
d8ee398d 923 data = (channel->hw_value & CHANNEL_CCK) ?
fa1c114f
JS		 924 ((data << 2) / 22) : (data / 10);
925
926 udelay(100 + data);
927 } else {
928 mdelay(1);
929 }
930
931 /*
932 * Enable calibration and wait until completion
933 */
934 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
935 AR5K_PHY_AGCCTL_CAL);
936
937 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
938 AR5K_PHY_AGCCTL_CAL, 0, false)) {
939 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
d8ee398d 940 channel->center_freq);
fa1c114f
JS		 941 return -EAGAIN;
942 }
943
d8ee398d 944 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
fa1c114f
JS		 945 if (ret)
946 return ret;
947
948 ah->ah_calibration = false;
949
950 /* A and G modes can use QAM modulation which requires enabling
951 * I and Q calibration. Don't bother in B mode. */
d8ee398d 952 if (!(mode == AR5K_MODE_11B)) {
fa1c114f
JS		 953 ah->ah_calibration = true;
954 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
955 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
956 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
957 AR5K_PHY_IQ_RUN);
958 }
959
960 /*
961 * Reset queues and start beacon timers at the end of the reset routine
962 */
963 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
964 /*No QCU on 5210*/
965 if (ah->ah_version != AR5K_AR5210)
966 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
967
968 ret = ath5k_hw_reset_tx_queue(ah, i);
969 if (ret) {
970 ATH5K_ERR(ah->ah_sc,
971 "failed to reset TX queue #%d\n", i);
972 return ret;
973 }
974 }
975
976 /* Pre-enable interrupts on 5211/5212*/
977 if (ah->ah_version != AR5K_AR5210)
978 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
979 AR5K_INT_FATAL);
980
981 /*
982 * Set RF kill flags if supported by the device (read from the EEPROM)
983 * Disable gpio_intr for now since it results system hang.
984 * TODO: Handle this in ath5k_intr
985 */
986#if 0
987 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
988 ath5k_hw_set_gpio_input(ah, 0);
989 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
990 if (ah->ah_gpio[0] == 0)
991 ath5k_hw_set_gpio_intr(ah, 0, 1);
992 else
993 ath5k_hw_set_gpio_intr(ah, 0, 0);
994 }
995#endif
996
997 /*
998 * Set the 32MHz reference clock on 5212 phy clock sleep register
999 */
1000 if (ah->ah_version == AR5K_AR5212) {
1001 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
1002 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
1003 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
1004 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
1005 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
903b474e 1006 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
fa1c114f
JS		 1007 }
1008
1009 /*
1010 * Disable beacons and reset the register
1011 */
1012 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1013 AR5K_BEACON_RESET_TSF);
1014
1015 return 0;
1016}
1017
1018/*
1019 * Reset chipset
1020 */
1021static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1022{
1023 int ret;
1024 u32 mask = val ? val : ~0U;
1025
1026 ATH5K_TRACE(ah->ah_sc);
1027
1028 /* Read-and-clear RX Descriptor Pointer*/
1029 ath5k_hw_reg_read(ah, AR5K_RXDP);
1030
1031 /*
1032 * Reset the device and wait until success
1033 */
1034 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1035
1036 /* Wait at least 128 PCI clocks */
1037 udelay(15);
1038
1039 if (ah->ah_version == AR5K_AR5210) {
1040 val &= AR5K_RESET_CTL_CHIP;
1041 mask &= AR5K_RESET_CTL_CHIP;
1042 } else {
1043 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1044 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1045 }
1046
1047 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1048
1049 /*
1050 * Reset configuration register (for hw byte-swap). Note that this
1051 * is only set for big endian. We do the necessary magic in
1052 * AR5K_INIT_CFG.
1053 */
1054 if ((val & AR5K_RESET_CTL_PCU) == 0)
1055 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1056
1057 return ret;
1058}
1059
1060/*
1061 * Power management functions
1062 */
1063
1064/*
1065 * Sleep control
1066 */
1067int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1068 bool set_chip, u16 sleep_duration)
1069{
1070 unsigned int i;
1071 u32 staid;
1072
1073 ATH5K_TRACE(ah->ah_sc);
1074 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1075
1076 switch (mode) {
1077 case AR5K_PM_AUTO:
1078 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1079 /* fallthrough */
1080 case AR5K_PM_NETWORK_SLEEP:
1081 if (set_chip == true)
1082 ath5k_hw_reg_write(ah,
1083 AR5K_SLEEP_CTL_SLE | sleep_duration,
1084 AR5K_SLEEP_CTL);
1085
1086 staid |= AR5K_STA_ID1_PWR_SV;
1087 break;
1088
1089 case AR5K_PM_FULL_SLEEP:
1090 if (set_chip == true)
1091 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1092 AR5K_SLEEP_CTL);
1093
1094 staid |= AR5K_STA_ID1_PWR_SV;
1095 break;
1096
1097 case AR5K_PM_AWAKE:
1098 if (set_chip == false)
1099 goto commit;
1100
1101 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1102 AR5K_SLEEP_CTL);
1103
1104 for (i = 5000; i > 0; i--) {
1105 /* Check if the chip did wake up */
1106 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1107 AR5K_PCICFG_SPWR_DN) == 0)
1108 break;
1109
1110 /* Wait a bit and retry */
1111 udelay(200);
1112 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1113 AR5K_SLEEP_CTL);
1114 }
1115
1116 /* Fail if the chip didn't wake up */
1117 if (i <= 0)
1118 return -EIO;
1119
1120 staid &= ~AR5K_STA_ID1_PWR_SV;
1121 break;
1122
1123 default:
1124 return -EINVAL;
1125 }
1126
1127commit:
1128 ah->ah_power_mode = mode;
1129 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1130
1131 return 0;
1132}
1133
1134/***********************\
1135 DMA Related Functions
1136\***********************/
1137
1138/*
1139 * Receive functions
1140 */
1141
1142/*
1143 * Start DMA receive
1144 */
1145void ath5k_hw_start_rx(struct ath5k_hw *ah)
1146{
1147 ATH5K_TRACE(ah->ah_sc);
1148 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
1149}
1150
1151/*
1152 * Stop DMA receive
1153 */
1154int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1155{
1156 unsigned int i;
1157
1158 ATH5K_TRACE(ah->ah_sc);
1159 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1160
1161 /*
1162 * It may take some time to disable the DMA receive unit
1163 */
1164 for (i = 2000; i > 0 &&
1165 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1166 i--)
1167 udelay(10);
1168
1169 return i ? 0 : -EBUSY;
1170}
1171
1172/*
1173 * Get the address of the RX Descriptor
1174 */
1175u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1176{
1177 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1178}
1179
1180/*
1181 * Set the address of the RX Descriptor
1182 */
1183void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1184{
1185 ATH5K_TRACE(ah->ah_sc);
1186
1187 /*TODO:Shouldn't we check if RX is enabled first ?*/
1188 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1189}
1190
1191/*
1192 * Transmit functions
1193 */
1194
1195/*
1196 * Start DMA transmit for a specific queue
1197 * (see also QCU/DCU functions)
1198 */
1199int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1200{
1201 u32 tx_queue;
1202
1203 ATH5K_TRACE(ah->ah_sc);
1204 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1205
1206 /* Return if queue is declared inactive */
1207 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1208 return -EIO;
1209
1210 if (ah->ah_version == AR5K_AR5210) {
1211 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1212
1213 /*
1214 * Set the queue by type on 5210
1215 */
1216 switch (ah->ah_txq[queue].tqi_type) {
1217 case AR5K_TX_QUEUE_DATA:
1218 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1219 break;
1220 case AR5K_TX_QUEUE_BEACON:
1221 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1222 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1223 AR5K_BSR);
1224 break;
1225 case AR5K_TX_QUEUE_CAB:
1226 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1227 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1228 AR5K_BCR_BDMAE, AR5K_BSR);
1229 break;
1230 default:
1231 return -EINVAL;
1232 }
1233 /* Start queue */
1234 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1235 } else {
1236 /* Return if queue is disabled */
1237 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1238 return -EIO;
1239
1240 /* Start queue */
1241 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1242 }
1243
1244 return 0;
1245}
1246
1247/*
1248 * Stop DMA transmit for a specific queue
1249 * (see also QCU/DCU functions)
1250 */
1251int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1252{
1253 unsigned int i = 100;
1254 u32 tx_queue, pending;
1255
1256 ATH5K_TRACE(ah->ah_sc);
1257 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1258
1259 /* Return if queue is declared inactive */
1260 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1261 return -EIO;
1262
1263 if (ah->ah_version == AR5K_AR5210) {
1264 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1265
1266 /*
1267 * Set by queue type
1268 */
1269 switch (ah->ah_txq[queue].tqi_type) {
1270 case AR5K_TX_QUEUE_DATA:
1271 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1272 break;
1273 case AR5K_TX_QUEUE_BEACON:
1274 case AR5K_TX_QUEUE_CAB:
1275 /* XXX Fix me... */
1276 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1277 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1278 break;
1279 default:
1280 return -EINVAL;
1281 }
1282
1283 /* Stop queue */
1284 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1285 } else {
1286 /*
1287 * Schedule TX disable and wait until queue is empty
1288 */
1289 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1290
1291 /*Check for pending frames*/
1292 do {
1293 pending = ath5k_hw_reg_read(ah,
1294 AR5K_QUEUE_STATUS(queue)) &
1295 AR5K_QCU_STS_FRMPENDCNT;
1296 udelay(100);
1297 } while (--i && pending);
1298
1299 /* Clear register */
1300 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
1301 }
1302
1303 /* TODO: Check for success else return error */
1304 return 0;
1305}
1306
1307/*
1308 * Get the address of the TX Descriptor for a specific queue
1309 * (see also QCU/DCU functions)
1310 */
1311u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1312{
1313 u16 tx_reg;
1314
1315 ATH5K_TRACE(ah->ah_sc);
1316 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1317
1318 /*
1319 * Get the transmit queue descriptor pointer from the selected queue
1320 */
1321 /*5210 doesn't have QCU*/
1322 if (ah->ah_version == AR5K_AR5210) {
1323 switch (ah->ah_txq[queue].tqi_type) {
1324 case AR5K_TX_QUEUE_DATA:
1325 tx_reg = AR5K_NOQCU_TXDP0;
1326 break;
1327 case AR5K_TX_QUEUE_BEACON:
1328 case AR5K_TX_QUEUE_CAB:
1329 tx_reg = AR5K_NOQCU_TXDP1;
1330 break;
1331 default:
1332 return 0xffffffff;
1333 }
1334 } else {
1335 tx_reg = AR5K_QUEUE_TXDP(queue);
1336 }
1337
1338 return ath5k_hw_reg_read(ah, tx_reg);
1339}
1340
1341/*
1342 * Set the address of the TX Descriptor for a specific queue
1343 * (see also QCU/DCU functions)
1344 */
1345int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1346{
1347 u16 tx_reg;
1348
1349 ATH5K_TRACE(ah->ah_sc);
1350 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1351
1352 /*
1353 * Set the transmit queue descriptor pointer register by type
1354 * on 5210
1355 */
1356 if (ah->ah_version == AR5K_AR5210) {
1357 switch (ah->ah_txq[queue].tqi_type) {
1358 case AR5K_TX_QUEUE_DATA:
1359 tx_reg = AR5K_NOQCU_TXDP0;
1360 break;
1361 case AR5K_TX_QUEUE_BEACON:
1362 case AR5K_TX_QUEUE_CAB:
1363 tx_reg = AR5K_NOQCU_TXDP1;
1364 break;
1365 default:
1366 return -EINVAL;
1367 }
1368 } else {
1369 /*
1370 * Set the transmit queue descriptor pointer for
1371 * the selected queue on QCU for 5211+
1372 * (this won't work if the queue is still active)
1373 */
1374 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1375 return -EIO;
1376
1377 tx_reg = AR5K_QUEUE_TXDP(queue);
1378 }
1379
1380 /* Set descriptor pointer */
1381 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1382
1383 return 0;
1384}
1385
1386/*
1387 * Update tx trigger level
1388 */
1389int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1390{
1391 u32 trigger_level, imr;
1392 int ret = -EIO;
1393
1394 ATH5K_TRACE(ah->ah_sc);
1395
1396 /*
1397 * Disable interrupts by setting the mask
1398 */
1399 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1400
1401 /*TODO: Boundary check on trigger_level*/
1402 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1403 AR5K_TXCFG_TXFULL);
1404
1405 if (increase == false) {
1406 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1407 goto done;
1408 } else
1409 trigger_level +=
1410 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1411
1412 /*
1413 * Update trigger level on success
1414 */
1415 if (ah->ah_version == AR5K_AR5210)
1416 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1417 else
1418 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1419 AR5K_TXCFG_TXFULL, trigger_level);
1420
1421 ret = 0;
1422
1423done:
1424 /*
1425 * Restore interrupt mask
1426 */
1427 ath5k_hw_set_intr(ah, imr);
1428
1429 return ret;
1430}
1431
1432/*
1433 * Interrupt handling
1434 */
1435
1436/*
1437 * Check if we have pending interrupts
1438 */
1439bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1440{
1441 ATH5K_TRACE(ah->ah_sc);
1442 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1443}
1444
1445/*
1446 * Get interrupt mask (ISR)
1447 */
1448int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1449{
1450 u32 data;
1451
1452 ATH5K_TRACE(ah->ah_sc);
1453
1454 /*
1455 * Read interrupt status from the Interrupt Status register
1456 * on 5210
1457 */
1458 if (ah->ah_version == AR5K_AR5210) {
1459 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1460 if (unlikely(data == AR5K_INT_NOCARD)) {
1461 *interrupt_mask = data;
1462 return -ENODEV;
1463 }
1464 } else {
1465 /*
1466 * Read interrupt status from the Read-And-Clear shadow register
1467 * Note: PISR/SISR Not available on 5210
1468 */
1469 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1470 }
1471
1472 /*
1473 * Get abstract interrupt mask (driver-compatible)
1474 */
1475 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1476
1477 if (unlikely(data == AR5K_INT_NOCARD))
1478 return -ENODEV;
1479
1480 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1481 *interrupt_mask |= AR5K_INT_RX;
1482
1483 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1484 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1485 *interrupt_mask |= AR5K_INT_TX;
1486
1487 if (ah->ah_version != AR5K_AR5210) {
1488 /*HIU = Host Interface Unit (PCI etc)*/
1489 if (unlikely(data & (AR5K_ISR_HIUERR)))
1490 *interrupt_mask |= AR5K_INT_FATAL;
1491
1492 /*Beacon Not Ready*/
1493 if (unlikely(data & (AR5K_ISR_BNR)))
1494 *interrupt_mask |= AR5K_INT_BNR;
1495 }
1496
1497 /*
1498 * XXX: BMISS interrupts may occur after association.
1499 * I found this on 5210 code but it needs testing. If this is
1500 * true we should disable them before assoc and re-enable them
1501 * after a successfull assoc + some jiffies.
1502 */
1503#if 0
1504 interrupt_mask &= ~AR5K_INT_BMISS;
1505#endif
1506
1507 /*
1508 * In case we didn't handle anything,
1509 * print the register value.
1510 */
1511 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1512 ATH5K_PRINTF("0x%08x\n", data);
1513
1514 return 0;
1515}
1516
1517/*
1518 * Set interrupt mask
1519 */
1520enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1521{
1522 enum ath5k_int old_mask, int_mask;
1523
1524 /*
1525 * Disable card interrupts to prevent any race conditions
1526 * (they will be re-enabled afterwards).
1527 */
1528 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
1529
1530 old_mask = ah->ah_imr;
1531
1532 /*
1533 * Add additional, chipset-dependent interrupt mask flags
1534 * and write them to the IMR (interrupt mask register).
1535 */
1536 int_mask = new_mask & AR5K_INT_COMMON;
1537
1538 if (new_mask & AR5K_INT_RX)
1539 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1540 AR5K_IMR_RXDESC;
1541
1542 if (new_mask & AR5K_INT_TX)
1543 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1544 AR5K_IMR_TXURN;
1545
1546 if (ah->ah_version != AR5K_AR5210) {
1547 if (new_mask & AR5K_INT_FATAL) {
1548 int_mask |= AR5K_IMR_HIUERR;
1549 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1550 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1551 }
1552 }
1553
1554 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1555
1556 /* Store new interrupt mask */
1557 ah->ah_imr = new_mask;
1558
1559 /* ..re-enable interrupts */
1560 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
1561
1562 return old_mask;
1563}
1564
1565
1566/*************************\
1567 EEPROM access functions
1568\*************************/
1569
1570/*
1571 * Read from eeprom
1572 */
1573static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1574{
1575 u32 status, timeout;
1576
1577 ATH5K_TRACE(ah->ah_sc);
1578 /*
1579 * Initialize EEPROM access
1580 */
1581 if (ah->ah_version == AR5K_AR5210) {
1582 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1583 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1584 } else {
1585 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1586 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1587 AR5K_EEPROM_CMD_READ);
1588 }
1589
1590 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1591 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1592 if (status & AR5K_EEPROM_STAT_RDDONE) {
1593 if (status & AR5K_EEPROM_STAT_RDERR)
1594 return -EIO;
1595 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1596 0xffff);
1597 return 0;
1598 }
1599 udelay(15);
1600 }
1601
1602 return -ETIMEDOUT;
1603}
1604
1605/*
1606 * Write to eeprom - currently disabled, use at your own risk
1607 */
d8ee398d 1608#if 0
fa1c114f
JS		 1609static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1610{
d8ee398d 1611
fa1c114f
JS		 1612 u32 status, timeout;
1613
1614 ATH5K_TRACE(ah->ah_sc);
1615
1616 /*
1617 * Initialize eeprom access
1618 */
1619
1620 if (ah->ah_version == AR5K_AR5210) {
1621 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1622 } else {
1623 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1624 AR5K_EEPROM_CMD_RESET);
1625 }
1626
1627 /*
1628 * Write data to data register
1629 */
1630
1631 if (ah->ah_version == AR5K_AR5210) {
1632 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1633 } else {
1634 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1635 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1636 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1637 AR5K_EEPROM_CMD_WRITE);
1638 }
1639
1640 /*
1641 * Check status
1642 */
1643
1644 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1645 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1646 if (status & AR5K_EEPROM_STAT_WRDONE) {
1647 if (status & AR5K_EEPROM_STAT_WRERR)
1648 return EIO;
1649 return 0;
1650 }
1651 udelay(15);
1652 }
d8ee398d 1653
fa1c114f
JS		 1654 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1655 return -EIO;
1656}
d8ee398d 1657#endif
fa1c114f
JS		 1658
1659/*
1660 * Translate binary channel representation in EEPROM to frequency
1661 */
1662static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1663{
1664 u16 val;
1665
1666 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1667 return bin;
1668
1669 if (mode == AR5K_EEPROM_MODE_11A) {
1670 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1671 val = (5 * bin) + 4800;
1672 else
1673 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1674 (bin * 10) + 5100;
1675 } else {
1676 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1677 val = bin + 2300;
1678 else
1679 val = bin + 2400;
1680 }
1681
1682 return val;
1683}
1684
1685/*
1686 * Read antenna infos from eeprom
1687 */
1688static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1689 unsigned int mode)
1690{
1691 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1692 u32 o = *offset;
1693 u16 val;
1694 int ret, i = 0;
1695
1696 AR5K_EEPROM_READ(o++, val);
1697 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1698 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1699 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1700
1701 AR5K_EEPROM_READ(o++, val);
1702 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1703 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1704 ee->ee_ant_control[mode][i++] = val & 0x3f;
1705
1706 AR5K_EEPROM_READ(o++, val);
1707 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1708 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1709 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1710
1711 AR5K_EEPROM_READ(o++, val);
1712 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1713 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1714 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1715 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1716
1717 AR5K_EEPROM_READ(o++, val);
1718 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1719 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1720 ee->ee_ant_control[mode][i++] = val & 0x3f;
1721
1722 /* Get antenna modes */
1723 ah->ah_antenna[mode][0] =
1724 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1725 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1726 ee->ee_ant_control[mode][1] |
1727 (ee->ee_ant_control[mode][2] << 6) |
1728 (ee->ee_ant_control[mode][3] << 12) |
1729 (ee->ee_ant_control[mode][4] << 18) |
1730 (ee->ee_ant_control[mode][5] << 24);
1731 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1732 ee->ee_ant_control[mode][6] |
1733 (ee->ee_ant_control[mode][7] << 6) |
1734 (ee->ee_ant_control[mode][8] << 12) |
1735 (ee->ee_ant_control[mode][9] << 18) |
1736 (ee->ee_ant_control[mode][10] << 24);
1737
1738 /* return new offset */
1739 *offset = o;
1740
1741 return 0;
1742}
1743
1744/*
1745 * Read supported modes from eeprom
1746 */
1747static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1748 unsigned int mode)
1749{
1750 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1751 u32 o = *offset;
1752 u16 val;
1753 int ret;
1754
1755 AR5K_EEPROM_READ(o++, val);
1756 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1757 ee->ee_thr_62[mode] = val & 0xff;
1758
1759 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1760 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1761
1762 AR5K_EEPROM_READ(o++, val);
1763 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1764 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1765
1766 AR5K_EEPROM_READ(o++, val);
1767 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1768
1769 if ((val & 0xff) & 0x80)
1770 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1771 else
1772 ee->ee_noise_floor_thr[mode] = val & 0xff;
1773
1774 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1775 ee->ee_noise_floor_thr[mode] =
1776 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1777
1778 AR5K_EEPROM_READ(o++, val);
1779 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1780 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
1781 ee->ee_xpd[mode] = val & 0x1;
1782
1783 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
1784 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
1785
1786 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
1787 AR5K_EEPROM_READ(o++, val);
1788 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
1789
1790 if (mode == AR5K_EEPROM_MODE_11A)
1791 ee->ee_xr_power[mode] = val & 0x3f;
1792 else {
1793 ee->ee_ob[mode][0] = val & 0x7;
1794 ee->ee_db[mode][0] = (val >> 3) & 0x7;
1795 }
1796 }
1797
1798 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
1799 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
1800 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
1801 } else {
1802 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
1803
1804 AR5K_EEPROM_READ(o++, val);
1805 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
1806
1807 if (mode == AR5K_EEPROM_MODE_11G)
1808 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1809 }
1810
1811 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
1812 mode == AR5K_EEPROM_MODE_11A) {
1813 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1814 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1815 }
1816
1817 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
1818 mode == AR5K_EEPROM_MODE_11G)
1819 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
1820
1821 /* return new offset */
1822 *offset = o;
1823
1824 return 0;
1825}
1826
1827/*
1828 * Initialize eeprom & capabilities structs
1829 */
1830static int ath5k_eeprom_init(struct ath5k_hw *ah)
1831{
1832 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1833 unsigned int mode, i;
1834 int ret;
1835 u32 offset;
1836 u16 val;
1837
1838 /* Initial TX thermal adjustment values */
1839 ee->ee_tx_clip = 4;
1840 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
1841 ee->ee_gain_select = 1;
1842
1843 /*
1844 * Read values from EEPROM and store them in the capability structure
1845 */
1846 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
1847 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
1848 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
1849 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
1850 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
1851
1852 /* Return if we have an old EEPROM */
1853 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
1854 return 0;
1855
1856#ifdef notyet
1857 /*
1858 * Validate the checksum of the EEPROM date. There are some
1859 * devices with invalid EEPROMs.
1860 */
1861 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
1862 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
1863 cksum ^= val;
1864 }
1865 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
1866 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
1867 return -EIO;
1868 }
1869#endif
1870
1871 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
1872 ee_ant_gain);
1873
1874 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1875 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
1876 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
1877 }
1878
1879 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
1880 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
1881 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
1882 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
1883
1884 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
1885 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
1886 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
1887 }
1888
1889 /*
1890 * Get conformance test limit values
1891 */
1892 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
1893 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
1894
1895 for (i = 0; i < ee->ee_ctls; i++) {
1896 AR5K_EEPROM_READ(offset++, val);
1897 ee->ee_ctl[i] = (val >> 8) & 0xff;
1898 ee->ee_ctl[i + 1] = val & 0xff;
1899 }
1900
1901 /*
1902 * Get values for 802.11a (5GHz)
1903 */
1904 mode = AR5K_EEPROM_MODE_11A;
1905
1906 ee->ee_turbo_max_power[mode] =
1907 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
1908
1909 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
1910
1911 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1912 if (ret)
1913 return ret;
1914
1915 AR5K_EEPROM_READ(offset++, val);
1916 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1917 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
1918 ee->ee_db[mode][3] = (val >> 2) & 0x7;
1919 ee->ee_ob[mode][2] = (val << 1) & 0x7;
1920
1921 AR5K_EEPROM_READ(offset++, val);
1922 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
1923 ee->ee_db[mode][2] = (val >> 12) & 0x7;
1924 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
1925 ee->ee_db[mode][1] = (val >> 6) & 0x7;
1926 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
1927 ee->ee_db[mode][0] = val & 0x7;
1928
1929 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1930 if (ret)
1931 return ret;
1932
1933 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
1934 AR5K_EEPROM_READ(offset++, val);
1935 ee->ee_margin_tx_rx[mode] = val & 0x3f;
1936 }
1937
1938 /*
1939 * Get values for 802.11b (2.4GHz)
1940 */
1941 mode = AR5K_EEPROM_MODE_11B;
1942 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
1943
1944 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1945 if (ret)
1946 return ret;
1947
1948 AR5K_EEPROM_READ(offset++, val);
1949 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1950 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1951 ee->ee_db[mode][1] = val & 0x7;
1952
1953 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1954 if (ret)
1955 return ret;
1956
1957 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1958 AR5K_EEPROM_READ(offset++, val);
1959 ee->ee_cal_pier[mode][0] =
1960 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1961 ee->ee_cal_pier[mode][1] =
1962 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
1963
1964 AR5K_EEPROM_READ(offset++, val);
1965 ee->ee_cal_pier[mode][2] =
1966 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1967 }
1968
1969 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1970 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
1971
1972 /*
1973 * Get values for 802.11g (2.4GHz)
1974 */
1975 mode = AR5K_EEPROM_MODE_11G;
1976 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
1977
1978 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1979 if (ret)
1980 return ret;
1981
1982 AR5K_EEPROM_READ(offset++, val);
1983 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1984 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1985 ee->ee_db[mode][1] = val & 0x7;
1986
1987 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1988 if (ret)
1989 return ret;
1990
1991 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1992 AR5K_EEPROM_READ(offset++, val);
1993 ee->ee_cal_pier[mode][0] =
1994 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1995 ee->ee_cal_pier[mode][1] =
1996 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
1997
1998 AR5K_EEPROM_READ(offset++, val);
1999 ee->ee_turbo_max_power[mode] = val & 0x7f;
2000 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
2001
2002 AR5K_EEPROM_READ(offset++, val);
2003 ee->ee_cal_pier[mode][2] =
2004 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2005
2006 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2007 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2008
2009 AR5K_EEPROM_READ(offset++, val);
2010 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
2011 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
2012
2013 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
2014 AR5K_EEPROM_READ(offset++, val);
2015 ee->ee_cck_ofdm_gain_delta = val & 0xff;
2016 }
2017 }
2018
2019 /*
2020 * Read 5GHz EEPROM channels
2021 */
2022
2023 return 0;
2024}
2025
2026/*
2027 * Read the MAC address from eeprom
2028 */
2029static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2030{
2031 u8 mac_d[ETH_ALEN];
2032 u32 total, offset;
2033 u16 data;
2034 int octet, ret;
2035
2036 memset(mac, 0, ETH_ALEN);
2037 memset(mac_d, 0, ETH_ALEN);
2038
2039 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2040 if (ret)
2041 return ret;
2042
2043 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2044 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2045 if (ret)
2046 return ret;
2047
2048 total += data;
2049 mac_d[octet + 1] = data & 0xff;
2050 mac_d[octet] = data >> 8;
2051 octet += 2;
2052 }
2053
2054 memcpy(mac, mac_d, ETH_ALEN);
2055
2056 if (!total || total == 3 * 0xffff)
2057 return -EINVAL;
2058
2059 return 0;
2060}
2061
fa1c114f
JS		 2062/*
2063 * Fill the capabilities struct
2064 */
2065static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2066{
2067 u16 ee_header;
2068
2069 ATH5K_TRACE(ah->ah_sc);
2070 /* Capabilities stored in the EEPROM */
2071 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2072
2073 if (ah->ah_version == AR5K_AR5210) {
2074 /*
2075 * Set radio capabilities
2076 * (The AR5110 only supports the middle 5GHz band)
2077 */
2078 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2079 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2080 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2081 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2082
2083 /* Set supported modes */
d8ee398d
LR		 2084 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
2085 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
fa1c114f
JS		 2086 } else {
2087 /*
2088 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2089 * XXX and from 2312 to 2732GHz. There are problems with the
2090 * XXX current ieee80211 implementation because the IEEE
2091 * XXX channel mapping does not support negative channel
2092 * XXX numbers (2312MHz is channel -19). Of course, this
2093 * XXX doesn't matter because these channels are out of range
2094 * XXX but some regulation domains like MKK (Japan) will
2095 * XXX support frequencies somewhere around 4.8GHz.
2096 */
2097
2098 /*
2099 * Set radio capabilities
2100 */
2101
2102 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2103 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2104 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2105
2106 /* Set supported modes */
d8ee398d 2107 __set_bit(AR5K_MODE_11A,
fa1c114f 2108 ah->ah_capabilities.cap_mode);
d8ee398d 2109 __set_bit(AR5K_MODE_11A_TURBO,
fa1c114f
JS		 2110 ah->ah_capabilities.cap_mode);
2111 if (ah->ah_version == AR5K_AR5212)
d8ee398d 2112 __set_bit(AR5K_MODE_11G_TURBO,
fa1c114f
JS		 2113 ah->ah_capabilities.cap_mode);
2114 }
2115
2116 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2117 * connected */
2118 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2119 AR5K_EEPROM_HDR_11G(ee_header)) {
2120 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2121 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2122
2123 if (AR5K_EEPROM_HDR_11B(ee_header))
d8ee398d 2124 __set_bit(AR5K_MODE_11B,
fa1c114f
JS		 2125 ah->ah_capabilities.cap_mode);
2126
2127 if (AR5K_EEPROM_HDR_11G(ee_header))
d8ee398d 2128 __set_bit(AR5K_MODE_11G,
fa1c114f
JS		 2129 ah->ah_capabilities.cap_mode);
2130 }
2131 }
2132
2133 /* GPIO */
2134 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2135
2136 /* Set number of supported TX queues */
2137 if (ah->ah_version == AR5K_AR5210)
2138 ah->ah_capabilities.cap_queues.q_tx_num =
2139 AR5K_NUM_TX_QUEUES_NOQCU;
2140 else
2141 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2142
2143 return 0;
2144}
2145
2146/*********************************\
2147 Protocol Control Unit Functions
2148\*********************************/
2149
2150/*
2151 * Set Operation mode
2152 */
2153int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2154{
2155 u32 pcu_reg, beacon_reg, low_id, high_id;
2156
2157 pcu_reg = 0;
2158 beacon_reg = 0;
2159
2160 ATH5K_TRACE(ah->ah_sc);
2161
2162 switch (ah->ah_op_mode) {
2163 case IEEE80211_IF_TYPE_IBSS:
2164 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2165 (ah->ah_version == AR5K_AR5210 ?
2166 AR5K_STA_ID1_NO_PSPOLL : 0);
2167 beacon_reg |= AR5K_BCR_ADHOC;
2168 break;
2169
2170 case IEEE80211_IF_TYPE_AP:
2171 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2172 (ah->ah_version == AR5K_AR5210 ?
2173 AR5K_STA_ID1_NO_PSPOLL : 0);
2174 beacon_reg |= AR5K_BCR_AP;
2175 break;
2176
2177 case IEEE80211_IF_TYPE_STA:
2178 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2179 (ah->ah_version == AR5K_AR5210 ?
2180 AR5K_STA_ID1_PWR_SV : 0);
2181 case IEEE80211_IF_TYPE_MNTR:
2182 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2183 (ah->ah_version == AR5K_AR5210 ?
2184 AR5K_STA_ID1_NO_PSPOLL : 0);
2185 break;
2186
2187 default:
2188 return -EINVAL;
2189 }
2190
2191 /*
2192 * Set PCU registers
2193 */
2194 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2195 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2196 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2197 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2198
2199 /*
2200 * Set Beacon Control Register on 5210
2201 */
2202 if (ah->ah_version == AR5K_AR5210)
2203 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2204
2205 return 0;
2206}
2207
2208/*
2209 * BSSID Functions
2210 */
2211
2212/*
2213 * Get station id
2214 */
2215void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2216{
2217 ATH5K_TRACE(ah->ah_sc);
2218 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2219}
2220
2221/*
2222 * Set station id
2223 */
2224int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2225{
2226 u32 low_id, high_id;
2227
2228 ATH5K_TRACE(ah->ah_sc);
2229 /* Set new station ID */
2230 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2231
2232 low_id = AR5K_LOW_ID(mac);
2233 high_id = AR5K_HIGH_ID(mac);
2234
2235 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2236 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2237
2238 return 0;
2239}
2240
2241/*
2242 * Set BSSID
2243 */
2244void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2245{
2246 u32 low_id, high_id;
2247 u16 tim_offset = 0;
2248
2249 /*
2250 * Set simple BSSID mask on 5212
2251 */
2252 if (ah->ah_version == AR5K_AR5212) {
2253 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM0);
2254 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM1);
2255 }
2256
2257 /*
2258 * Set BSSID which triggers the "SME Join" operation
2259 */
2260 low_id = AR5K_LOW_ID(bssid);
2261 high_id = AR5K_HIGH_ID(bssid);
2262 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2263 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2264 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2265
2266 if (assoc_id == 0) {
2267 ath5k_hw_disable_pspoll(ah);
2268 return;
2269 }
2270
2271 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2272 tim_offset ? tim_offset + 4 : 0);
2273
2274 ath5k_hw_enable_pspoll(ah, NULL, 0);
2275}
2276/**
2277 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2278 *
2279 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2280 * which bits of the interface's MAC address should be looked at when trying
2281 * to decide which packets to ACK. In station mode every bit matters. In AP
2282 * mode with a single BSS every bit matters as well. In AP mode with
2283 * multiple BSSes not every bit matters.
2284 *
2285 * @ah: the &struct ath5k_hw
2286 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2287 *
2288 * Note that this is a simple filter and *does* not filter out all
2289 * relevant frames. Some non-relevant frames will get through, probability
2290 * jocks are welcomed to compute.
2291 *
2292 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2293 * computing the set of:
2294 *
2295 * ~ ( MAC XOR BSSID )
2296 *
2297 * When you do this you are essentially computing the common bits. Later it
2298 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2299 * to obtain the relevant bits which should match on the destination frame.
2300 *
2301 * Simple example: on your card you have have two BSSes you have created with
2302 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2303 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2304 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2305 *
2306 * \
2307 * MAC: 0001 |
2308 * BSSID-01: 0100 | --> Belongs to us
2309 * BSSID-02: 1001 |
2310 * /
2311 * -------------------
2312 * BSSID-03: 0110 | --> External
2313 * -------------------
2314 *
2315 * Our bssid_mask would then be:
2316 *
2317 * On loop iteration for BSSID-01:
2318 * ~(0001 ^ 0100) -> ~(0101)
2319 * -> 1010
2320 * bssid_mask = 1010
2321 *
2322 * On loop iteration for BSSID-02:
2323 * bssid_mask &= ~(0001 ^ 1001)
2324 * bssid_mask = (1010) & ~(0001 ^ 1001)
2325 * bssid_mask = (1010) & ~(1001)
2326 * bssid_mask = (1010) & (0110)
2327 * bssid_mask = 0010
2328 *
2329 * A bssid_mask of 0010 means "only pay attention to the second least
2330 * significant bit". This is because its the only bit common
2331 * amongst the MAC and all BSSIDs we support. To findout what the real
2332 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2333 * or our MAC address (we assume the hardware uses the MAC address).
2334 *
2335 * Now, suppose there's an incoming frame for BSSID-03:
2336 *
2337 * IFRAME-01: 0110
2338 *
2339 * An easy eye-inspeciton of this already should tell you that this frame
2340 * will not pass our check. This is beacuse the bssid_mask tells the
2341 * hardware to only look at the second least significant bit and the
2342 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2343 * as 1, which does not match 0.
2344 *
2345 * So with IFRAME-01 we *assume* the hardware will do:
2346 *
2347 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2348 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2349 * --> allow = (0010) == 0000 ? 1 : 0;
2350 * --> allow = 0
2351 *
2352 * Lets now test a frame that should work:
2353 *
2354 * IFRAME-02: 0001 (we should allow)
2355 *
2356 * allow = (0001 & 1010) == 1010
2357 *
2358 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2359 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2360 * --> allow = (0010) == (0010)
2361 * --> allow = 1
2362 *
2363 * Other examples:
2364 *
2365 * IFRAME-03: 0100 --> allowed
2366 * IFRAME-04: 1001 --> allowed
2367 * IFRAME-05: 1101 --> allowed but its not for us!!!
2368 *
2369 */
2370int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2371{
2372 u32 low_id, high_id;
2373 ATH5K_TRACE(ah->ah_sc);
2374
2375 if (ah->ah_version == AR5K_AR5212) {
2376 low_id = AR5K_LOW_ID(mask);
2377 high_id = AR5K_HIGH_ID(mask);
2378
2379 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2380 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2381
2382 return 0;
2383 }
2384
2385 return -EIO;
2386}
2387
2388/*
2389 * Receive start/stop functions
2390 */
2391
2392/*
2393 * Start receive on PCU
2394 */
2395void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2396{
2397 ATH5K_TRACE(ah->ah_sc);
2398 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2399}
2400
2401/*
2402 * Stop receive on PCU
2403 */
2404void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2405{
2406 ATH5K_TRACE(ah->ah_sc);
2407 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2408}
2409
2410/*
2411 * RX Filter functions
2412 */
2413
2414/*
2415 * Set multicast filter
2416 */
2417void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2418{
2419 ATH5K_TRACE(ah->ah_sc);
2420 /* Set the multicat filter */
2421 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2422 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2423}
2424
2425/*
2426 * Set multicast filter by index
2427 */
2428int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2429{
2430
2431 ATH5K_TRACE(ah->ah_sc);
2432 if (index >= 64)
2433 return -EINVAL;
2434 else if (index >= 32)
2435 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2436 (1 << (index - 32)));
2437 else
2438 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2439
2440 return 0;
2441}
2442
2443/*
2444 * Clear Multicast filter by index
2445 */
2446int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2447{
2448
2449 ATH5K_TRACE(ah->ah_sc);
2450 if (index >= 64)
2451 return -EINVAL;
2452 else if (index >= 32)
2453 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2454 (1 << (index - 32)));
2455 else
2456 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2457
2458 return 0;
2459}
2460
2461/*
2462 * Get current rx filter
2463 */
2464u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2465{
2466 u32 data, filter = 0;
2467
2468 ATH5K_TRACE(ah->ah_sc);
2469 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2470
2471 /*Radar detection for 5212*/
2472 if (ah->ah_version == AR5K_AR5212) {
2473 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2474
2475 if (data & AR5K_PHY_ERR_FIL_RADAR)
2476 filter |= AR5K_RX_FILTER_RADARERR;
2477 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2478 filter |= AR5K_RX_FILTER_PHYERR;
2479 }
2480
2481 return filter;
2482}
2483
2484/*
2485 * Set rx filter
2486 */
2487void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2488{
2489 u32 data = 0;
2490
2491 ATH5K_TRACE(ah->ah_sc);
2492
2493 /* Set PHY error filter register on 5212*/
2494 if (ah->ah_version == AR5K_AR5212) {
2495 if (filter & AR5K_RX_FILTER_RADARERR)
2496 data |= AR5K_PHY_ERR_FIL_RADAR;
2497 if (filter & AR5K_RX_FILTER_PHYERR)
2498 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2499 }
2500
2501 /*
2502 * The AR5210 uses promiscous mode to detect radar activity
2503 */
2504 if (ah->ah_version == AR5K_AR5210 &&
2505 (filter & AR5K_RX_FILTER_RADARERR)) {
2506 filter &= ~AR5K_RX_FILTER_RADARERR;
2507 filter |= AR5K_RX_FILTER_PROM;
2508 }
2509
2510 /*Zero length DMA*/
2511 if (data)
2512 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2513 else
2514 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2515
2516 /*Write RX Filter register*/
2517 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2518
2519 /*Write PHY error filter register on 5212*/
2520 if (ah->ah_version == AR5K_AR5212)
2521 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2522
2523}
2524
2525/*
2526 * Beacon related functions
2527 */
2528
2529/*
2530 * Get a 32bit TSF
2531 */
2532u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2533{
2534 ATH5K_TRACE(ah->ah_sc);
2535 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2536}
2537
2538/*
2539 * Get the full 64bit TSF
2540 */
2541u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2542{
2543 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2544 ATH5K_TRACE(ah->ah_sc);
2545
2546 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2547}
2548
2549/*
2550 * Force a TSF reset
2551 */
2552void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2553{
2554 ATH5K_TRACE(ah->ah_sc);
2555 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2556}
2557
2558/*
2559 * Initialize beacon timers
2560 */
2561void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2562{
2563 u32 timer1, timer2, timer3;
2564
2565 ATH5K_TRACE(ah->ah_sc);
2566 /*
2567 * Set the additional timers by mode
2568 */
2569 switch (ah->ah_op_mode) {
2570 case IEEE80211_IF_TYPE_STA:
2571 if (ah->ah_version == AR5K_AR5210) {
2572 timer1 = 0xffffffff;
2573 timer2 = 0xffffffff;
2574 } else {
2575 timer1 = 0x0000ffff;
2576 timer2 = 0x0007ffff;
2577 }
2578 break;
2579
2580 default:
1008e0f7
BR		 2581 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2582 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
fa1c114f
JS		 2583 }
2584
2585 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2586
2587 /*
2588 * Set the beacon register and enable all timers.
2589 * (next beacon, DMA beacon, software beacon, ATIM window time)
2590 */
2591 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2592 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2593 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2594 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2595
2596 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2597 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2598 AR5K_BEACON);
2599}
2600
2601#if 0
2602/*
2603 * Set beacon timers
2604 */
2605int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2606 const struct ath5k_beacon_state *state)
2607{
2608 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2609
2610 /*
2611 * TODO: should be changed through *state
2612 * review struct ath5k_beacon_state struct
2613 *
2614 * XXX: These are used for cfp period bellow, are they
2615 * ok ? Is it O.K. for tsf here to be 0 or should we use
2616 * get_tsf ?
2617 */
2618 u32 dtim_count = 0; /* XXX */
2619 u32 cfp_count = 0; /* XXX */
2620 u32 tsf = 0; /* XXX */
2621
2622 ATH5K_TRACE(ah->ah_sc);
2623 /* Return on an invalid beacon state */
2624 if (state->bs_interval < 1)
2625 return -EINVAL;
2626
2627 interval = state->bs_interval;
2628 dtim = state->bs_dtim_period;
2629
2630 /*
2631 * PCF support?
2632 */
2633 if (state->bs_cfp_period > 0) {
2634 /*
2635 * Enable PCF mode and set the CFP
2636 * (Contention Free Period) and timer registers
2637 */
2638 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2639 state->bs_interval;
2640 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2641 state->bs_interval;
2642
2643 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2644 AR5K_STA_ID1_DEFAULT_ANTENNA |
2645 AR5K_STA_ID1_PCF);
2646 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2647 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2648 AR5K_CFP_DUR);
2649 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2650 next_cfp)) << 3, AR5K_TIMER2);
2651 } else {
2652 /* Disable PCF mode */
2653 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2654 AR5K_STA_ID1_DEFAULT_ANTENNA |
2655 AR5K_STA_ID1_PCF);
2656 }
2657
2658 /*
2659 * Enable the beacon timer register
2660 */
2661 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2662
2663 /*
2664 * Start the beacon timers
2665 */
2666 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2667 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2668 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2669 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2670 AR5K_BEACON_PERIOD), AR5K_BEACON);
2671
2672 /*
2673 * Write new beacon miss threshold, if it appears to be valid
2674 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2675 * and return if its not in range. We can test this by reading value and
2676 * setting value to a largest value and seeing which values register.
2677 */
2678
2679 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2680 state->bs_bmiss_threshold);
2681
2682 /*
2683 * Set sleep control register
2684 * XXX: Didn't find this in 5210 code but since this register
2685 * exists also in ar5k's 5210 headers i leave it as common code.
2686 */
2687 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2688 (state->bs_sleep_duration - 3) << 3);
2689
2690 /*
2691 * Set enhanced sleep registers on 5212
2692 */
2693 if (ah->ah_version == AR5K_AR5212) {
2694 if (state->bs_sleep_duration > state->bs_interval &&
2695 roundup(state->bs_sleep_duration, interval) ==
2696 state->bs_sleep_duration)
2697 interval = state->bs_sleep_duration;
2698
2699 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2700 roundup(state->bs_sleep_duration, dtim) ==
2701 state->bs_sleep_duration))
2702 dtim = state->bs_sleep_duration;
2703
2704 if (interval > dtim)
2705 return -EINVAL;
2706
2707 next_beacon = interval == dtim ? state->bs_next_dtim :
2708 state->bs_next_beacon;
2709
2710 ath5k_hw_reg_write(ah,
2711 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2712 AR5K_SLEEP0_NEXT_DTIM) |
2713 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2714 AR5K_SLEEP0_ENH_SLEEP_EN |
2715 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2716
2717 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2718 AR5K_SLEEP1_NEXT_TIM) |
2719 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2720
2721 ath5k_hw_reg_write(ah,
2722 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2723 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2724 }
2725
2726 return 0;
2727}
2728
2729/*
2730 * Reset beacon timers
2731 */
2732void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2733{
2734 ATH5K_TRACE(ah->ah_sc);
2735 /*
2736 * Disable beacon timer
2737 */
2738 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2739
2740 /*
2741 * Disable some beacon register values
2742 */
2743 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2744 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2745 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2746}
2747
2748/*
2749 * Wait for beacon queue to finish
2750 */
2751int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2752{
2753 unsigned int i;
2754 int ret;
2755
2756 ATH5K_TRACE(ah->ah_sc);
2757
2758 /* 5210 doesn't have QCU*/
2759 if (ah->ah_version == AR5K_AR5210) {
2760 /*
2761 * Wait for beaconn queue to finish by checking
2762 * Control Register and Beacon Status Register.
2763 */
2764 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2765 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2766 ||
2767 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2768 break;
2769 udelay(10);
2770 }
2771
2772 /* Timeout... */
2773 if (i <= 0) {
2774 /*
2775 * Re-schedule the beacon queue
2776 */
2777 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
2778 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
2779 AR5K_BCR);
2780
2781 return -EIO;
2782 }
2783 ret = 0;
2784 } else {
2785 /*5211/5212*/
2786 ret = ath5k_hw_register_timeout(ah,
2787 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
2788 AR5K_QCU_STS_FRMPENDCNT, 0, false);
2789
2790 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
2791 return -EIO;
2792 }
2793
2794 return ret;
2795}
2796#endif
2797
2798/*
2799 * Update mib counters (statistics)
2800 */
2801void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2802 struct ath5k_mib_stats *statistics)
2803{
2804 ATH5K_TRACE(ah->ah_sc);
2805 /* Read-And-Clear */
2806 statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2807 statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2808 statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2809 statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2810 statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2811
2812 /* Reset profile count registers on 5212*/
2813 if (ah->ah_version == AR5K_AR5212) {
2814 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
2815 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
2816 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
2817 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
2818 }
2819}
2820
2821/** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
2822 *
2823 * @ah: the &struct ath5k_hw
2824 * @high: determines if to use low bit rate or now
2825 */
2826void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
2827{
2828 if (ah->ah_version != AR5K_AR5212)
2829 return;
2830 else {
2831 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
2832 if (high)
2833 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
2834 else
2835 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
2836 }
2837}
2838
2839
2840/*
2841 * ACK/CTS Timeouts
2842 */
2843
2844/*
2845 * Set ACK timeout on PCU
2846 */
2847int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
2848{
2849 ATH5K_TRACE(ah->ah_sc);
2850 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
2851 ah->ah_turbo) <= timeout)
2852 return -EINVAL;
2853
2854 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
2855 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2856
2857 return 0;
2858}
2859
2860/*
2861 * Read the ACK timeout from PCU
2862 */
2863unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
2864{
2865 ATH5K_TRACE(ah->ah_sc);
2866
2867 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2868 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
2869}
2870
2871/*
2872 * Set CTS timeout on PCU
2873 */
2874int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
2875{
2876 ATH5K_TRACE(ah->ah_sc);
2877 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
2878 ah->ah_turbo) <= timeout)
2879 return -EINVAL;
2880
2881 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
2882 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2883
2884 return 0;
2885}
2886
2887/*
2888 * Read CTS timeout from PCU
2889 */
2890unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
2891{
2892 ATH5K_TRACE(ah->ah_sc);
2893 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2894 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
2895}
2896
2897/*
2898 * Key table (WEP) functions
2899 */
2900
2901int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
2902{
2903 unsigned int i;
2904
2905 ATH5K_TRACE(ah->ah_sc);
2906 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2907
2908 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
2909 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
2910
2911 /* Set NULL encryption on non-5210*/
2912 if (ah->ah_version != AR5K_AR5210)
2913 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
2914 AR5K_KEYTABLE_TYPE(entry));
2915
2916 return 0;
2917}
2918
2919int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
2920{
2921 ATH5K_TRACE(ah->ah_sc);
2922 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2923
2924 /* Check the validation flag at the end of the entry */
2925 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
2926 AR5K_KEYTABLE_VALID;
2927}
2928
2929int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
2930 const struct ieee80211_key_conf *key, const u8 *mac)
2931{
2932 unsigned int i;
2933 __le32 key_v[5] = {};
2934 u32 keytype;
2935
2936 ATH5K_TRACE(ah->ah_sc);
2937
2938 /* key->keylen comes in from mac80211 in bytes */
2939
2940 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
2941 return -EOPNOTSUPP;
2942
2943 switch (key->keylen) {
2944 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
2945 case 40 / 8:
2946 memcpy(&key_v[0], key->key, 5);
2947 keytype = AR5K_KEYTABLE_TYPE_40;
2948 break;
2949
2950 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
2951 case 104 / 8:
2952 memcpy(&key_v[0], &key->key[0], 6);
2953 memcpy(&key_v[2], &key->key[6], 6);
2954 memcpy(&key_v[4], &key->key[12], 1);
2955 keytype = AR5K_KEYTABLE_TYPE_104;
2956 break;
2957 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
2958 case 128 / 8:
2959 memcpy(&key_v[0], &key->key[0], 6);
2960 memcpy(&key_v[2], &key->key[6], 6);
2961 memcpy(&key_v[4], &key->key[12], 4);
2962 keytype = AR5K_KEYTABLE_TYPE_128;
2963 break;
2964
2965 default:
2966 return -EINVAL; /* shouldn't happen */
2967 }
2968
2969 for (i = 0; i < ARRAY_SIZE(key_v); i++)
2970 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
2971 AR5K_KEYTABLE_OFF(entry, i));
2972
2973 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
2974
2975 return ath5k_hw_set_key_lladdr(ah, entry, mac);
2976}
2977
2978int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
2979{
2980 u32 low_id, high_id;
2981
2982 ATH5K_TRACE(ah->ah_sc);
2983 /* Invalid entry (key table overflow) */
2984 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2985
2986 /* MAC may be NULL if it's a broadcast key. In this case no need to
2987 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
2988 if (unlikely(mac == NULL)) {
2989 low_id = 0xffffffff;
2990 high_id = 0xffff | AR5K_KEYTABLE_VALID;
2991 } else {
2992 low_id = AR5K_LOW_ID(mac);
2993 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
2994 }
2995
2996 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
2997 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
2998
2999 return 0;
3000}
3001
3002
3003/********************************************\
3004Queue Control Unit, DFS Control Unit Functions
3005\********************************************/
3006
3007/*
3008 * Initialize a transmit queue
3009 */
3010int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
3011 struct ath5k_txq_info *queue_info)
3012{
3013 unsigned int queue;
3014 int ret;
3015
3016 ATH5K_TRACE(ah->ah_sc);
3017
3018 /*
3019 * Get queue by type
3020 */
3021 /*5210 only has 2 queues*/
3022 if (ah->ah_version == AR5K_AR5210) {
3023 switch (queue_type) {
3024 case AR5K_TX_QUEUE_DATA:
3025 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3026 break;
3027 case AR5K_TX_QUEUE_BEACON:
3028 case AR5K_TX_QUEUE_CAB:
3029 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3030 break;
3031 default:
3032 return -EINVAL;
3033 }
3034 } else {
3035 switch (queue_type) {
3036 case AR5K_TX_QUEUE_DATA:
3037 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3038 ah->ah_txq[queue].tqi_type !=
3039 AR5K_TX_QUEUE_INACTIVE; queue++) {
3040
3041 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3042 return -EINVAL;
3043 }
3044 break;
3045 case AR5K_TX_QUEUE_UAPSD:
3046 queue = AR5K_TX_QUEUE_ID_UAPSD;
3047 break;
3048 case AR5K_TX_QUEUE_BEACON:
3049 queue = AR5K_TX_QUEUE_ID_BEACON;
3050 break;
3051 case AR5K_TX_QUEUE_CAB:
3052 queue = AR5K_TX_QUEUE_ID_CAB;
3053 break;
3054 case AR5K_TX_QUEUE_XR_DATA:
3055 if (ah->ah_version != AR5K_AR5212)
3056 ATH5K_ERR(ah->ah_sc,
3057 "XR data queues only supported in"
3058 " 5212!\n");
3059 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3060 break;
3061 default:
3062 return -EINVAL;
3063 }
3064 }
3065
3066 /*
3067 * Setup internal queue structure
3068 */
3069 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3070 ah->ah_txq[queue].tqi_type = queue_type;
3071
3072 if (queue_info != NULL) {
3073 queue_info->tqi_type = queue_type;
3074 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3075 if (ret)
3076 return ret;
3077 }
3078 /*
3079 * We use ah_txq_status to hold a temp value for
3080 * the Secondary interrupt mask registers on 5211+
3081 * check out ath5k_hw_reset_tx_queue
3082 */
3083 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3084
3085 return queue;
3086}
3087
3088/*
3089 * Setup a transmit queue
3090 */
3091int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3092 const struct ath5k_txq_info *queue_info)
3093{
3094 ATH5K_TRACE(ah->ah_sc);
3095 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3096
3097 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3098 return -EIO;
3099
3100 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3101
3102 /*XXX: Is this supported on 5210 ?*/
3103 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3104 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3105 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3106 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3107 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3108
3109 return 0;
3110}
3111
3112/*
3113 * Get properties for a specific transmit queue
3114 */
3115int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3116 struct ath5k_txq_info *queue_info)
3117{
3118 ATH5K_TRACE(ah->ah_sc);
3119 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3120 return 0;
3121}
3122
3123/*
3124 * Set a transmit queue inactive
3125 */
3126void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3127{
3128 ATH5K_TRACE(ah->ah_sc);
3129 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3130 return;
3131
3132 /* This queue will be skipped in further operations */
3133 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3134 /*For SIMR setup*/
3135 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3136}
3137
3138/*
3139 * Set DFS params for a transmit queue
3140 */
3141int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3142{
3143 u32 cw_min, cw_max, retry_lg, retry_sh;
3144 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3145
3146 ATH5K_TRACE(ah->ah_sc);
3147 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3148
3149 tq = &ah->ah_txq[queue];
3150
3151 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3152 return 0;
3153
3154 if (ah->ah_version == AR5K_AR5210) {
3155 /* Only handle data queues, others will be ignored */
3156 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3157 return 0;
3158
3159 /* Set Slot time */
3160 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3161 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3162 AR5K_SLOT_TIME);
3163 /* Set ACK_CTS timeout */
3164 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3165 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3166 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3167 /* Set Transmit Latency */
3168 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3169 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3170 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3171 /* Set IFS0 */
3172 if (ah->ah_turbo == true)
3173 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3174 (ah->ah_aifs + tq->tqi_aifs) *
3175 AR5K_INIT_SLOT_TIME_TURBO) <<
3176 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3177 AR5K_IFS0);
3178 else
3179 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3180 (ah->ah_aifs + tq->tqi_aifs) *
3181 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3182 AR5K_INIT_SIFS, AR5K_IFS0);
3183
3184 /* Set IFS1 */
3185 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3186 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3187 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3188 /* Set PHY register 0x9844 (??) */
3189 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3190 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
3191 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
3192 AR5K_PHY(17));
3193 /* Set Frame Control Register */
3194 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3195 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3196 AR5K_PHY_TURBO_SHORT | 0x2020) :
3197 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3198 AR5K_PHY_FRAME_CTL_5210);
3199 }
3200
3201 /*
3202 * Calculate cwmin/max by channel mode
3203 */
3204 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3205 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3206 ah->ah_aifs = AR5K_TUNE_AIFS;
3207 /*XR is only supported on 5212*/
3208 if (IS_CHAN_XR(ah->ah_current_channel) &&
3209 ah->ah_version == AR5K_AR5212) {
3210 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3211 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3212 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3213 /*B mode is not supported on 5210*/
3214 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3215 ah->ah_version != AR5K_AR5210) {
3216 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3217 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3218 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3219 }
3220
3221 cw_min = 1;
3222 while (cw_min < ah->ah_cw_min)
3223 cw_min = (cw_min << 1) | 1;
3224
3225 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3226 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3227 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3228 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3229
3230 /*
3231 * Calculate and set retry limits
3232 */
3233 if (ah->ah_software_retry == true) {
3234 /* XXX Need to test this */
3235 retry_lg = ah->ah_limit_tx_retries;
3236 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3237 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3238 } else {
3239 retry_lg = AR5K_INIT_LG_RETRY;
3240 retry_sh = AR5K_INIT_SH_RETRY;
3241 }
3242
3243 /*No QCU/DCU [5210]*/
3244 if (ah->ah_version == AR5K_AR5210) {
3245 ath5k_hw_reg_write(ah,
3246 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3247 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3248 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3249 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3250 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3251 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3252 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3253 AR5K_NODCU_RETRY_LMT);
3254 } else {
3255 /*QCU/DCU [5211+]*/
3256 ath5k_hw_reg_write(ah,
3257 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3258 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3259 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3260 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3261 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3262 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3263 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3264
3265 /*===Rest is also for QCU/DCU only [5211+]===*/
3266
3267 /*
3268 * Set initial content window (cw_min/cw_max)
3269 * and arbitrated interframe space (aifs)...
3270 */
3271 ath5k_hw_reg_write(ah,
3272 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3273 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3274 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3275 AR5K_DCU_LCL_IFS_AIFS),
3276 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3277
3278 /*
3279 * Set misc registers
3280 */
3281 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3282 AR5K_QUEUE_MISC(queue));
3283
3284 if (tq->tqi_cbr_period) {
3285 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3286 AR5K_QCU_CBRCFG_INTVAL) |
3287 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3288 AR5K_QCU_CBRCFG_ORN_THRES),
3289 AR5K_QUEUE_CBRCFG(queue));
3290 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3291 AR5K_QCU_MISC_FRSHED_CBR);
3292 if (tq->tqi_cbr_overflow_limit)
3293 AR5K_REG_ENABLE_BITS(ah,
3294 AR5K_QUEUE_MISC(queue),
3295 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3296 }
3297
3298 if (tq->tqi_ready_time)
3299 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3300 AR5K_QCU_RDYTIMECFG_INTVAL) |
3301 AR5K_QCU_RDYTIMECFG_ENABLE,
3302 AR5K_QUEUE_RDYTIMECFG(queue));
3303
3304 if (tq->tqi_burst_time) {
3305 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3306 AR5K_DCU_CHAN_TIME_DUR) |
3307 AR5K_DCU_CHAN_TIME_ENABLE,
3308 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3309
3310 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3311 AR5K_REG_ENABLE_BITS(ah,
3312 AR5K_QUEUE_MISC(queue),
3313 AR5K_QCU_MISC_TXE);
3314 }
3315
3316 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3317 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3318 AR5K_QUEUE_DFS_MISC(queue));
3319
3320 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3321 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3322 AR5K_QUEUE_DFS_MISC(queue));
3323
3324 /*
3325 * Set registers by queue type
3326 */
3327 switch (tq->tqi_type) {
3328 case AR5K_TX_QUEUE_BEACON:
3329 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3330 AR5K_QCU_MISC_FRSHED_DBA_GT |
3331 AR5K_QCU_MISC_CBREXP_BCN |
3332 AR5K_QCU_MISC_BCN_ENABLE);
3333
3334 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3335 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3336 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3337 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3338 AR5K_DCU_MISC_BCN_ENABLE);
3339
3340 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3341 (AR5K_TUNE_SW_BEACON_RESP -
3342 AR5K_TUNE_DMA_BEACON_RESP) -
3343 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3344 AR5K_QCU_RDYTIMECFG_ENABLE,
3345 AR5K_QUEUE_RDYTIMECFG(queue));
3346 break;
3347
3348 case AR5K_TX_QUEUE_CAB:
3349 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3350 AR5K_QCU_MISC_FRSHED_DBA_GT |
3351 AR5K_QCU_MISC_CBREXP |
3352 AR5K_QCU_MISC_CBREXP_BCN);
3353
3354 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3355 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3356 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3357 break;
3358
3359 case AR5K_TX_QUEUE_UAPSD:
3360 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3361 AR5K_QCU_MISC_CBREXP);
3362 break;
3363
3364 case AR5K_TX_QUEUE_DATA:
3365 default:
3366 break;
3367 }
3368
3369 /*
3370 * Enable interrupts for this tx queue
3371 * in the secondary interrupt mask registers
3372 */
3373 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3374 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3375
3376 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3377 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3378
3379 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3380 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3381
3382 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3383 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3384
3385 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3386 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3387
3388
3389 /* Update secondary interrupt mask registers */
3390 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3391 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3392 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3393 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3394 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3395
3396 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3397 AR5K_SIMR0_QCU_TXOK) |
3398 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3399 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3400 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3401 AR5K_SIMR1_QCU_TXERR) |
3402 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3403 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3404 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3405 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3406 }
3407
3408 return 0;
3409}
3410
3411/*
3412 * Get number of pending frames
3413 * for a specific queue [5211+]
3414 */
3415u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3416 ATH5K_TRACE(ah->ah_sc);
3417 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3418
3419 /* Return if queue is declared inactive */
3420 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3421 return false;
3422
3423 /* XXX: How about AR5K_CFG_TXCNT ? */
3424 if (ah->ah_version == AR5K_AR5210)
3425 return false;
3426
3427 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3428}
3429
3430/*
3431 * Set slot time
3432 */
3433int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3434{
3435 ATH5K_TRACE(ah->ah_sc);
3436 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3437 return -EINVAL;
3438
3439 if (ah->ah_version == AR5K_AR5210)
3440 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3441 ah->ah_turbo), AR5K_SLOT_TIME);
3442 else
3443 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3444
3445 return 0;
3446}
3447
3448/*
3449 * Get slot time
3450 */
3451unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3452{
3453 ATH5K_TRACE(ah->ah_sc);
3454 if (ah->ah_version == AR5K_AR5210)
3455 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3456 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3457 else
3458 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3459}
3460
3461
3462/******************************\
3463 Hardware Descriptor Functions
3464\******************************/
3465
3466/*
3467 * TX Descriptor
3468 */
3469
3470/*
3471 * Initialize the 2-word tx descriptor on 5210/5211
3472 */
3473static int
3474ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3475 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3476 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3477 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3478 unsigned int rtscts_rate, unsigned int rtscts_duration)
3479{
3480 u32 frame_type;
3481 struct ath5k_hw_2w_tx_desc *tx_desc;
281c56dd 3482 unsigned int frame_len;
fa1c114f
JS		 3483
3484 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
3485
3486 /*
3487 * Validate input
3488 * - Zero retries don't make sense.
3489 * - A zero rate will put the HW into a mode where it continously sends
3490 * noise on the channel, so it is important to avoid this.
3491 */
3492 if (unlikely(tx_tries0 == 0)) {
3493 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3494 WARN_ON(1);
3495 return -EINVAL;
3496 }
3497 if (unlikely(tx_rate0 == 0)) {
3498 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3499 WARN_ON(1);
3500 return -EINVAL;
3501 }
3502
3503 /* Clear status descriptor */
3504 memset(desc->ds_hw, 0, sizeof(struct ath5k_hw_tx_status));
3505
3506 /* Initialize control descriptor */
3507 tx_desc->tx_control_0 = 0;
3508 tx_desc->tx_control_1 = 0;
3509
3510 /* Setup control descriptor */
3511
3512 /* Verify and set frame length */
281c56dd
BR		 3513
3514 /* remove padding we might have added before */
3515 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3516
3517 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
fa1c114f
JS		 3518 return -EINVAL;
3519
281c56dd 3520 tx_desc->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
fa1c114f
JS		 3521
3522 /* Verify and set buffer length */
fa1c114f
JS		 3523
3524 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3525 if(type == AR5K_PKT_TYPE_BEACON)
281c56dd 3526 pkt_len = roundup(pkt_len, 4);
fa1c114f 3527
281c56dd 3528 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
fa1c114f
JS		 3529 return -EINVAL;
3530
281c56dd 3531 tx_desc->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
fa1c114f
JS		 3532
3533 /*
3534 * Verify and set header length
3535 * XXX: I only found that on 5210 code, does it work on 5211 ?
3536 */
3537 if (ah->ah_version == AR5K_AR5210) {
3538 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3539 return -EINVAL;
3540 tx_desc->tx_control_0 |=
3541 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3542 }
3543
3544 /*Diferences between 5210-5211*/
3545 if (ah->ah_version == AR5K_AR5210) {
3546 switch (type) {
3547 case AR5K_PKT_TYPE_BEACON:
3548 case AR5K_PKT_TYPE_PROBE_RESP:
3549 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3550 case AR5K_PKT_TYPE_PIFS:
3551 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3552 default:
3553 frame_type = type /*<< 2 ?*/;
3554 }
3555
3556 tx_desc->tx_control_0 |=
3557 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3558 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3559 } else {
3560 tx_desc->tx_control_0 |=
3561 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3562 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3563 tx_desc->tx_control_1 |=
3564 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3565 }
3566#define _TX_FLAGS(_c, _flag) \
3567 if (flags & AR5K_TXDESC_##_flag) \
3568 tx_desc->tx_control_##_c |= \
3569 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3570
3571 _TX_FLAGS(0, CLRDMASK);
3572 _TX_FLAGS(0, VEOL);
3573 _TX_FLAGS(0, INTREQ);
3574 _TX_FLAGS(0, RTSENA);
3575 _TX_FLAGS(1, NOACK);
3576
3577#undef _TX_FLAGS
3578
3579 /*
3580 * WEP crap
3581 */
3582 if (key_index != AR5K_TXKEYIX_INVALID) {
3583 tx_desc->tx_control_0 |=
3584 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3585 tx_desc->tx_control_1 |=
3586 AR5K_REG_SM(key_index,
3587 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3588 }
3589
3590 /*
3591 * RTS/CTS Duration [5210 ?]
3592 */
3593 if ((ah->ah_version == AR5K_AR5210) &&
3594 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3595 tx_desc->tx_control_1 |= rtscts_duration &
3596 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3597
3598 return 0;
3599}
3600
3601/*
3602 * Initialize the 4-word tx descriptor on 5212
3603 */
3604static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3605 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3606 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3607 unsigned int tx_tries0, unsigned int key_index,
3608 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3609 unsigned int rtscts_duration)
3610{
3611 struct ath5k_hw_4w_tx_desc *tx_desc;
3612 struct ath5k_hw_tx_status *tx_status;
281c56dd 3613 unsigned int frame_len;
fa1c114f
JS		 3614
3615 ATH5K_TRACE(ah->ah_sc);
3616 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3617 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3618
3619 /*
3620 * Validate input
3621 * - Zero retries don't make sense.
3622 * - A zero rate will put the HW into a mode where it continously sends
3623 * noise on the channel, so it is important to avoid this.
3624 */
3625 if (unlikely(tx_tries0 == 0)) {
3626 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3627 WARN_ON(1);
3628 return -EINVAL;
3629 }
3630 if (unlikely(tx_rate0 == 0)) {
3631 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3632 WARN_ON(1);
3633 return -EINVAL;
3634 }
3635
3636 /* Clear status descriptor */
3637 memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status));
3638
3639 /* Initialize control descriptor */
3640 tx_desc->tx_control_0 = 0;
3641 tx_desc->tx_control_1 = 0;
3642 tx_desc->tx_control_2 = 0;
3643 tx_desc->tx_control_3 = 0;
3644
3645 /* Setup control descriptor */
3646
3647 /* Verify and set frame length */
281c56dd
BR		 3648
3649 /* remove padding we might have added before */
3650 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3651
3652 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
fa1c114f
JS		 3653 return -EINVAL;
3654
281c56dd 3655 tx_desc->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
fa1c114f
JS		 3656
3657 /* Verify and set buffer length */
fa1c114f
JS		 3658
3659 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3660 if(type == AR5K_PKT_TYPE_BEACON)
281c56dd 3661 pkt_len = roundup(pkt_len, 4);
fa1c114f 3662
281c56dd 3663 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
fa1c114f
JS		 3664 return -EINVAL;
3665
281c56dd 3666 tx_desc->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
fa1c114f
JS		 3667
3668 tx_desc->tx_control_0 |=
3669 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3670 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3671 tx_desc->tx_control_1 |= AR5K_REG_SM(type,
3672 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3673 tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3674 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3675 tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3676
3677#define _TX_FLAGS(_c, _flag) \
3678 if (flags & AR5K_TXDESC_##_flag) \
3679 tx_desc->tx_control_##_c |= \
3680 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3681
3682 _TX_FLAGS(0, CLRDMASK);
3683 _TX_FLAGS(0, VEOL);
3684 _TX_FLAGS(0, INTREQ);
3685 _TX_FLAGS(0, RTSENA);
3686 _TX_FLAGS(0, CTSENA);
3687 _TX_FLAGS(1, NOACK);
3688
3689#undef _TX_FLAGS
3690
3691 /*
3692 * WEP crap
3693 */
3694 if (key_index != AR5K_TXKEYIX_INVALID) {
3695 tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3696 tx_desc->tx_control_1 |= AR5K_REG_SM(key_index,
3697 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3698 }
3699
3700 /*
3701 * RTS/CTS
3702 */
3703 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3704 if ((flags & AR5K_TXDESC_RTSENA) &&
3705 (flags & AR5K_TXDESC_CTSENA))
3706 return -EINVAL;
3707 tx_desc->tx_control_2 |= rtscts_duration &
3708 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3709 tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3710 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3711 }
3712
3713 return 0;
3714}
3715
3716/*
3717 * Initialize a 4-word multirate tx descriptor on 5212
3718 */
b9887638 3719static int
fa1c114f
JS		 3720ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3721 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3722 unsigned int tx_rate3, u_int tx_tries3)
3723{
3724 struct ath5k_hw_4w_tx_desc *tx_desc;
3725
3726 /*
3727 * Rates can be 0 as long as the retry count is 0 too.
3728 * A zero rate and nonzero retry count will put the HW into a mode where
3729 * it continously sends noise on the channel, so it is important to
3730 * avoid this.
3731 */
3732 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3733 (tx_rate2 == 0 && tx_tries2 != 0) ||
3734 (tx_rate3 == 0 && tx_tries3 != 0))) {
3735 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3736 WARN_ON(1);
3737 return -EINVAL;
3738 }
3739
3740 if (ah->ah_version == AR5K_AR5212) {
3741 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3742
3743#define _XTX_TRIES(_n) \
3744 if (tx_tries##_n) { \
3745 tx_desc->tx_control_2 |= \
3746 AR5K_REG_SM(tx_tries##_n, \
3747 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3748 tx_desc->tx_control_3 |= \
3749 AR5K_REG_SM(tx_rate##_n, \
3750 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3751 }
3752
3753 _XTX_TRIES(1);
3754 _XTX_TRIES(2);
3755 _XTX_TRIES(3);
3756
3757#undef _XTX_TRIES
3758
b9887638 3759 return 1;
fa1c114f
JS		 3760 }
3761
b9887638 3762 return 0;
fa1c114f
JS		 3763}
3764
3765/*
3766 * Proccess the tx status descriptor on 5210/5211
3767 */
3768static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3769 struct ath5k_desc *desc)
3770{
3771 struct ath5k_hw_tx_status *tx_status;
3772 struct ath5k_hw_2w_tx_desc *tx_desc;
3773
3774 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
3775 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0];
3776
3777 /* No frame has been send or error */
3778 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3779 return -EINPROGRESS;
3780
3781 /*
3782 * Get descriptor status
3783 */
3784 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3785 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3786 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3787 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3788 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3789 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3790 /*TODO: desc->ds_us.tx.ts_virtcol + test*/
3791 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3792 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3793 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3794 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3795 desc->ds_us.tx.ts_antenna = 1;
3796 desc->ds_us.tx.ts_status = 0;
3797 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0,
3798 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3799
3800 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3801 if (tx_status->tx_status_0 &
3802 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3803 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
3804
3805 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3806 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
3807
3808 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3809 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
3810 }
3811
3812 return 0;
3813}
3814
3815/*
3816 * Proccess a tx descriptor on 5212
3817 */
3818static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3819 struct ath5k_desc *desc)
3820{
3821 struct ath5k_hw_tx_status *tx_status;
3822 struct ath5k_hw_4w_tx_desc *tx_desc;
3823
3824 ATH5K_TRACE(ah->ah_sc);
3825 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3826 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3827
3828 /* No frame has been send or error */
3829 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3830 return -EINPROGRESS;
3831
3832 /*
3833 * Get descriptor status
3834 */
3835 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3836 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3837 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3838 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3839 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3840 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3841 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3842 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3843 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3844 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3845 desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
3846 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
3847 desc->ds_us.tx.ts_status = 0;
3848
3849 switch (AR5K_REG_MS(tx_status->tx_status_1,
3850 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
3851 case 0:
3852 desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
3853 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3854 break;
3855 case 1:
3856 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3857 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
3858 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3859 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
3860 break;
3861 case 2:
3862 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3863 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
3864 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3865 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
3866 break;
3867 case 3:
3868 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3869 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
3870 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3871 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
3872 break;
3873 }
3874
3875 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3876 if (tx_status->tx_status_0 &
3877 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3878 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
3879
3880 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3881 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
3882
3883 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3884 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
3885 }
3886
3887 return 0;
3888}
3889
3890/*
3891 * RX Descriptor
3892 */
3893
3894/*
3895 * Initialize an rx descriptor
3896 */
3897int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3898 u32 size, unsigned int flags)
3899{
3900 struct ath5k_rx_desc *rx_desc;
3901
3902 ATH5K_TRACE(ah->ah_sc);
3903 rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0;
3904
3905 /*
3906 *Clear ds_hw
3907 * If we don't clean the status descriptor,
3908 * while scanning we get too many results,
3909 * most of them virtual, after some secs
3910 * of scanning system hangs. M.F.
3911 */
3912 memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
3913
3914 /*Initialize rx descriptor*/
3915 rx_desc->rx_control_0 = 0;
3916 rx_desc->rx_control_1 = 0;
3917
3918 /* Setup descriptor */
3919 rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
3920 if (unlikely(rx_desc->rx_control_1 != size))
3921 return -EINVAL;
3922
3923 if (flags & AR5K_RXDESC_INTREQ)
3924 rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
3925
3926 return 0;
3927}
3928
3929/*
3930 * Proccess the rx status descriptor on 5210/5211
3931 */
3932static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *ah,
3933 struct ath5k_desc *desc)
3934{
3935 struct ath5k_hw_old_rx_status *rx_status;
3936
3937 rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0];
3938
3939 /* No frame received / not ready */
3940 if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE)
3941 == 0))
3942 return -EINPROGRESS;
3943
3944 /*
3945 * Frame receive status
3946 */
3947 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
3948 AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
3949 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
3950 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
3951 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
3952 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
3953 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
3954 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
3955 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
3956 AR5K_OLD_RX_DESC_STATUS0_MORE;
3957 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
3958 AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
3959 desc->ds_us.rx.rs_status = 0;
3960
3961 /*
3962 * Key table status
3963 */
3964 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
3965 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
3966 AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
3967 else
3968 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
3969
3970 /*
3971 * Receive/descriptor errors
3972 */
3973 if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK)
3974 == 0) {
3975 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR)
3976 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
3977
3978 if (rx_status->rx_status_1 &
3979 AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN)
3980 desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO;
3981
3982 if (rx_status->rx_status_1 &
3983 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) {
3984 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
3985 desc->ds_us.rx.rs_phyerr =
3986 AR5K_REG_MS(rx_status->rx_status_1,
3987 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR);
3988 }
3989
3990 if (rx_status->rx_status_1 &
3991 AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
3992 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
3993 }
3994
3995 return 0;
3996}
3997
3998/*
3999 * Proccess the rx status descriptor on 5212
4000 */
4001static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *ah,
4002 struct ath5k_desc *desc)
4003{
4004 struct ath5k_hw_new_rx_status *rx_status;
4005 struct ath5k_hw_rx_error *rx_err;
4006
4007 ATH5K_TRACE(ah->ah_sc);
4008 rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0];
4009
4010 /* Overlay on error */
4011 rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0];
4012
4013 /* No frame received / not ready */
4014 if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE)
4015 == 0))
4016 return -EINPROGRESS;
4017
4018 /*
4019 * Frame receive status
4020 */
4021 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
4022 AR5K_NEW_RX_DESC_STATUS0_DATA_LEN;
4023 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4024 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4025 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4026 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE);
4027 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
4028 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4029 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
4030 AR5K_NEW_RX_DESC_STATUS0_MORE;
4031 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4032 AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4033 desc->ds_us.rx.rs_status = 0;
4034
4035 /*
4036 * Key table status
4037 */
4038 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID)
4039 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4040 AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX);
4041 else
4042 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
4043
4044 /*
4045 * Receive/descriptor errors
4046 */
4047 if ((rx_status->rx_status_1 &
4048 AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4049 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR)
4050 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
4051
4052 if (rx_status->rx_status_1 &
4053 AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) {
4054 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
4055 desc->ds_us.rx.rs_phyerr =
4056 AR5K_REG_MS(rx_err->rx_error_1,
4057 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4058 }
4059
4060 if (rx_status->rx_status_1 &
4061 AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4062 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
4063
4064 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR)
4065 desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC;
4066 }
4067
4068 return 0;
4069}
4070
4071
4072/****************\
4073 GPIO Functions
4074\****************/
4075
4076/*
4077 * Set led state
4078 */
4079void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4080{
4081 u32 led;
4082 /*5210 has different led mode handling*/
4083 u32 led_5210;
4084
4085 ATH5K_TRACE(ah->ah_sc);
4086
4087 /*Reset led status*/
4088 if (ah->ah_version != AR5K_AR5210)
4089 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4090 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4091 else
4092 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4093
4094 /*
4095 * Some blinking values, define at your wish
4096 */
4097 switch (state) {
4098 case AR5K_LED_SCAN:
4099 case AR5K_LED_AUTH:
4100 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4101 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4102 break;
4103
4104 case AR5K_LED_INIT:
4105 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4106 led_5210 = AR5K_PCICFG_LED_PEND;
4107 break;
4108
4109 case AR5K_LED_ASSOC:
4110 case AR5K_LED_RUN:
4111 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4112 led_5210 = AR5K_PCICFG_LED_ASSOC;
4113 break;
4114
4115 default:
4116 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4117 led_5210 = AR5K_PCICFG_LED_PEND;
4118 break;
4119 }
4120
4121 /*Write new status to the register*/
4122 if (ah->ah_version != AR5K_AR5210)
4123 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4124 else
4125 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4126}
4127
4128/*
4129 * Set GPIO outputs
4130 */
4131int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4132{
4133 ATH5K_TRACE(ah->ah_sc);
4134 if (gpio > AR5K_NUM_GPIO)
4135 return -EINVAL;
4136
4137 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4138 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4139
4140 return 0;
4141}
4142
4143/*
4144 * Set GPIO inputs
4145 */
4146int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4147{
4148 ATH5K_TRACE(ah->ah_sc);
4149 if (gpio > AR5K_NUM_GPIO)
4150 return -EINVAL;
4151
4152 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4153 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4154
4155 return 0;
4156}
4157
4158/*
4159 * Get GPIO state
4160 */
4161u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4162{
4163 ATH5K_TRACE(ah->ah_sc);
4164 if (gpio > AR5K_NUM_GPIO)
4165 return 0xffffffff;
4166
4167 /* GPIO input magic */
4168 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4169 0x1;
4170}
4171
4172/*
4173 * Set GPIO state
4174 */
4175int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4176{
4177 u32 data;
4178 ATH5K_TRACE(ah->ah_sc);
4179
4180 if (gpio > AR5K_NUM_GPIO)
4181 return -EINVAL;
4182
4183 /* GPIO output magic */
4184 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4185
4186 data &= ~(1 << gpio);
4187 data |= (val & 1) << gpio;
4188
4189 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4190
4191 return 0;
4192}
4193
4194/*
4195 * Initialize the GPIO interrupt (RFKill switch)
4196 */
4197void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4198 u32 interrupt_level)
4199{
4200 u32 data;
4201
4202 ATH5K_TRACE(ah->ah_sc);
4203 if (gpio > AR5K_NUM_GPIO)
4204 return;
4205
4206 /*
4207 * Set the GPIO interrupt
4208 */
4209 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4210 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4211 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4212 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4213
4214 ath5k_hw_reg_write(ah, interrupt_level ? data :
4215 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4216
4217 ah->ah_imr |= AR5K_IMR_GPIO;
4218
4219 /* Enable GPIO interrupts */
4220 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4221}
4222
4223
fa1c114f
JS		 4224
4225
4226/****************\
4227 Misc functions
4228\****************/
4229
4230int ath5k_hw_get_capability(struct ath5k_hw *ah,
4231 enum ath5k_capability_type cap_type,
4232 u32 capability, u32 *result)
4233{
4234 ATH5K_TRACE(ah->ah_sc);
4235
4236 switch (cap_type) {
4237 case AR5K_CAP_NUM_TXQUEUES:
4238 if (result) {
4239 if (ah->ah_version == AR5K_AR5210)
4240 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4241 else
4242 *result = AR5K_NUM_TX_QUEUES;
4243 goto yes;
4244 }
4245 case AR5K_CAP_VEOL:
4246 goto yes;
4247 case AR5K_CAP_COMPRESSION:
4248 if (ah->ah_version == AR5K_AR5212)
4249 goto yes;
4250 else
4251 goto no;
4252 case AR5K_CAP_BURST:
4253 goto yes;
4254 case AR5K_CAP_TPC:
4255 goto yes;
4256 case AR5K_CAP_BSSIDMASK:
4257 if (ah->ah_version == AR5K_AR5212)
4258 goto yes;
4259 else
4260 goto no;
4261 case AR5K_CAP_XR:
4262 if (ah->ah_version == AR5K_AR5212)
4263 goto yes;
4264 else
4265 goto no;
4266 default:
4267 goto no;
4268 }
4269
4270no:
4271 return -EINVAL;
4272yes:
4273 return 0;
4274}
4275
4276static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4277 u16 assoc_id)
4278{
4279 ATH5K_TRACE(ah->ah_sc);
4280
4281 if (ah->ah_version == AR5K_AR5210) {
4282 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4283 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4284 return 0;
4285 }
4286
4287 return -EIO;
4288}
4289
4290static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4291{
4292 ATH5K_TRACE(ah->ah_sc);
4293
4294 if (ah->ah_version == AR5K_AR5210) {
4295 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4296 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4297 return 0;
4298 }
4299
4300 return -EIO;
4301}
kernel source for telekom puls (alcatel/mediatek)