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dma-mapping: add the device argument to dma_mapping_error()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
46#include <linux/if.h>
47#include <linux/netdevice.h>
48#include <linux/cache.h>
49#include <linux/pci.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52
53#include <net/ieee80211_radiotap.h>
54
55#include <asm/unaligned.h>
56
57#include "base.h"
58#include "reg.h"
59#include "debug.h"
60
fa1c114f
JS		 61static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
62
63
64/******************\
65* Internal defines *
66\******************/
67
68/* Module info */
69MODULE_AUTHOR("Jiri Slaby");
70MODULE_AUTHOR("Nick Kossifidis");
71MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
72MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
73MODULE_LICENSE("Dual BSD/GPL");
400ec45a 74MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 75
76
77/* Known PCI ids */
78static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
79 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
80 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
81 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
82 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
83 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
84 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
85 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
86 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
88 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
94 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
95 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
96 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
97 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
98 { 0 }
99};
100MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
101
102/* Known SREVs */
103static struct ath5k_srev_name srev_names[] = {
104 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
105 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
106 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
107 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
108 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
109 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
110 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
111 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
bb0c9dc2
NK		 112 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
113 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
fa1c114f
JS		 114 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
115 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
116 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
117 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
118 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
119 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
136bfc79 120 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
fa1c114f
JS		 121 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
124 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
125 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
126 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
127 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
128 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
bb0c9dc2 129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
fa1c114f
JS		 130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
131 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
133 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
134};
135
136/*
137 * Prototypes - PCI stack related functions
138 */
139static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
140 const struct pci_device_id *id);
141static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
142#ifdef CONFIG_PM
143static int ath5k_pci_suspend(struct pci_dev *pdev,
144 pm_message_t state);
145static int ath5k_pci_resume(struct pci_dev *pdev);
146#else
147#define ath5k_pci_suspend NULL
148#define ath5k_pci_resume NULL
149#endif /* CONFIG_PM */
150
04a9e451 151static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 152 .name = "ath5k_pci",
153 .id_table = ath5k_pci_id_table,
154 .probe = ath5k_pci_probe,
155 .remove = __devexit_p(ath5k_pci_remove),
156 .suspend = ath5k_pci_suspend,
157 .resume = ath5k_pci_resume,
158};
159
160
161
162/*
163 * Prototypes - MAC 802.11 stack related functions
164 */
e039fa4a 165static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
fa1c114f
JS		 166static int ath5k_reset(struct ieee80211_hw *hw);
167static int ath5k_start(struct ieee80211_hw *hw);
168static void ath5k_stop(struct ieee80211_hw *hw);
169static int ath5k_add_interface(struct ieee80211_hw *hw,
170 struct ieee80211_if_init_conf *conf);
171static void ath5k_remove_interface(struct ieee80211_hw *hw,
172 struct ieee80211_if_init_conf *conf);
173static int ath5k_config(struct ieee80211_hw *hw,
174 struct ieee80211_conf *conf);
32bfd35d
JB		 175static int ath5k_config_interface(struct ieee80211_hw *hw,
176 struct ieee80211_vif *vif,
fa1c114f
JS		 177 struct ieee80211_if_conf *conf);
178static void ath5k_configure_filter(struct ieee80211_hw *hw,
179 unsigned int changed_flags,
180 unsigned int *new_flags,
181 int mc_count, struct dev_mc_list *mclist);
182static int ath5k_set_key(struct ieee80211_hw *hw,
183 enum set_key_cmd cmd,
184 const u8 *local_addr, const u8 *addr,
185 struct ieee80211_key_conf *key);
186static int ath5k_get_stats(struct ieee80211_hw *hw,
187 struct ieee80211_low_level_stats *stats);
188static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
189 struct ieee80211_tx_queue_stats *stats);
190static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
191static void ath5k_reset_tsf(struct ieee80211_hw *hw);
192static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 193 struct sk_buff *skb);
fa1c114f
JS		 194
195static struct ieee80211_ops ath5k_hw_ops = {
196 .tx = ath5k_tx,
197 .start = ath5k_start,
198 .stop = ath5k_stop,
199 .add_interface = ath5k_add_interface,
200 .remove_interface = ath5k_remove_interface,
201 .config = ath5k_config,
202 .config_interface = ath5k_config_interface,
203 .configure_filter = ath5k_configure_filter,
204 .set_key = ath5k_set_key,
205 .get_stats = ath5k_get_stats,
206 .conf_tx = NULL,
207 .get_tx_stats = ath5k_get_tx_stats,
208 .get_tsf = ath5k_get_tsf,
209 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 210};
211
212/*
213 * Prototypes - Internal functions
214 */
215/* Attach detach */
216static int ath5k_attach(struct pci_dev *pdev,
217 struct ieee80211_hw *hw);
218static void ath5k_detach(struct pci_dev *pdev,
219 struct ieee80211_hw *hw);
220/* Channel/mode setup */
221static inline short ath5k_ieee2mhz(short chan);
222static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
223 const struct ath5k_rate_table *rt,
224 unsigned int max);
225static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
226 struct ieee80211_channel *channels,
227 unsigned int mode,
228 unsigned int max);
229static int ath5k_getchannels(struct ieee80211_hw *hw);
230static int ath5k_chan_set(struct ath5k_softc *sc,
231 struct ieee80211_channel *chan);
232static void ath5k_setcurmode(struct ath5k_softc *sc,
233 unsigned int mode);
234static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d
LR		 235static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
236
fa1c114f
JS		 237/* Descriptor setup */
238static int ath5k_desc_alloc(struct ath5k_softc *sc,
239 struct pci_dev *pdev);
240static void ath5k_desc_free(struct ath5k_softc *sc,
241 struct pci_dev *pdev);
242/* Buffers setup */
243static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
244 struct ath5k_buf *bf);
245static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 246 struct ath5k_buf *bf);
fa1c114f
JS		 247static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
248 struct ath5k_buf *bf)
249{
250 BUG_ON(!bf);
251 if (!bf->skb)
252 return;
253 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
254 PCI_DMA_TODEVICE);
255 dev_kfree_skb(bf->skb);
256 bf->skb = NULL;
257}
258
259/* Queues setup */
260static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
261 int qtype, int subtype);
262static int ath5k_beaconq_setup(struct ath5k_hw *ah);
263static int ath5k_beaconq_config(struct ath5k_softc *sc);
264static void ath5k_txq_drainq(struct ath5k_softc *sc,
265 struct ath5k_txq *txq);
266static void ath5k_txq_cleanup(struct ath5k_softc *sc);
267static void ath5k_txq_release(struct ath5k_softc *sc);
268/* Rx handling */
269static int ath5k_rx_start(struct ath5k_softc *sc);
270static void ath5k_rx_stop(struct ath5k_softc *sc);
271static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
272 struct ath5k_desc *ds,
b47f407b
BR		 273 struct sk_buff *skb,
274 struct ath5k_rx_status *rs);
fa1c114f
JS		 275static void ath5k_tasklet_rx(unsigned long data);
276/* Tx handling */
277static void ath5k_tx_processq(struct ath5k_softc *sc,
278 struct ath5k_txq *txq);
279static void ath5k_tasklet_tx(unsigned long data);
280/* Beacon handling */
281static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 282 struct ath5k_buf *bf);
fa1c114f
JS		 283static void ath5k_beacon_send(struct ath5k_softc *sc);
284static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 285static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 286
287static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
288{
289 u64 tsf = ath5k_hw_get_tsf64(ah);
290
291 if ((tsf & 0x7fff) < rstamp)
292 tsf -= 0x8000;
293
294 return (tsf & ~0x7fff) | rstamp;
295}
296
297/* Interrupt handling */
298static int ath5k_init(struct ath5k_softc *sc);
299static int ath5k_stop_locked(struct ath5k_softc *sc);
300static int ath5k_stop_hw(struct ath5k_softc *sc);
301static irqreturn_t ath5k_intr(int irq, void *dev_id);
302static void ath5k_tasklet_reset(unsigned long data);
303
304static void ath5k_calibrate(unsigned long data);
305/* LED functions */
3a078876
BC		 306static int ath5k_init_leds(struct ath5k_softc *sc);
307static void ath5k_led_enable(struct ath5k_softc *sc);
308static void ath5k_led_off(struct ath5k_softc *sc);
309static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 310
311/*
312 * Module init/exit functions
313 */
314static int __init
315init_ath5k_pci(void)
316{
317 int ret;
318
319 ath5k_debug_init();
320
04a9e451 321 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 322 if (ret) {
323 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
324 return ret;
325 }
326
327 return 0;
328}
329
330static void __exit
331exit_ath5k_pci(void)
332{
04a9e451 333 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 334
335 ath5k_debug_finish();
336}
337
338module_init(init_ath5k_pci);
339module_exit(exit_ath5k_pci);
340
341
342/********************\
343* PCI Initialization *
344\********************/
345
346static const char *
347ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
348{
349 const char *name = "xxxxx";
350 unsigned int i;
351
352 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
353 if (srev_names[i].sr_type != type)
354 continue;
355 if ((val & 0xff) < srev_names[i + 1].sr_val) {
356 name = srev_names[i].sr_name;
357 break;
358 }
359 }
360
361 return name;
362}
363
364static int __devinit
365ath5k_pci_probe(struct pci_dev *pdev,
366 const struct pci_device_id *id)
367{
368 void __iomem *mem;
369 struct ath5k_softc *sc;
370 struct ieee80211_hw *hw;
371 int ret;
372 u8 csz;
373
374 ret = pci_enable_device(pdev);
375 if (ret) {
376 dev_err(&pdev->dev, "can't enable device\n");
377 goto err;
378 }
379
380 /* XXX 32-bit addressing only */
381 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
382 if (ret) {
383 dev_err(&pdev->dev, "32-bit DMA not available\n");
384 goto err_dis;
385 }
386
387 /*
388 * Cache line size is used to size and align various
389 * structures used to communicate with the hardware.
390 */
391 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
392 if (csz == 0) {
393 /*
394 * Linux 2.4.18 (at least) writes the cache line size
395 * register as a 16-bit wide register which is wrong.
396 * We must have this setup properly for rx buffer
397 * DMA to work so force a reasonable value here if it
398 * comes up zero.
399 */
400 csz = L1_CACHE_BYTES / sizeof(u32);
401 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
402 }
403 /*
404 * The default setting of latency timer yields poor results,
405 * set it to the value used by other systems. It may be worth
406 * tweaking this setting more.
407 */
408 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
409
410 /* Enable bus mastering */
411 pci_set_master(pdev);
412
413 /*
414 * Disable the RETRY_TIMEOUT register (0x41) to keep
415 * PCI Tx retries from interfering with C3 CPU state.
416 */
417 pci_write_config_byte(pdev, 0x41, 0);
418
419 ret = pci_request_region(pdev, 0, "ath5k");
420 if (ret) {
421 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
422 goto err_dis;
423 }
424
425 mem = pci_iomap(pdev, 0, 0);
426 if (!mem) {
427 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
428 ret = -EIO;
429 goto err_reg;
430 }
431
432 /*
433 * Allocate hw (mac80211 main struct)
434 * and hw->priv (driver private data)
435 */
436 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
437 if (hw == NULL) {
438 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
439 ret = -ENOMEM;
440 goto err_map;
441 }
442
443 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
444
445 /* Initialize driver private data */
446 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 447 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
448 IEEE80211_HW_SIGNAL_DBM |
449 IEEE80211_HW_NOISE_DBM;
fa1c114f
JS		 450 hw->extra_tx_headroom = 2;
451 hw->channel_change_time = 5000;
fa1c114f
JS		 452 sc = hw->priv;
453 sc->hw = hw;
454 sc->pdev = pdev;
455
456 ath5k_debug_init_device(sc);
457
458 /*
459 * Mark the device as detached to avoid processing
460 * interrupts until setup is complete.
461 */
462 __set_bit(ATH_STAT_INVALID, sc->status);
463
464 sc->iobase = mem; /* So we can unmap it on detach */
465 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
466 sc->opmode = IEEE80211_IF_TYPE_STA;
467 mutex_init(&sc->lock);
468 spin_lock_init(&sc->rxbuflock);
469 spin_lock_init(&sc->txbuflock);
470
471 /* Set private data */
472 pci_set_drvdata(pdev, hw);
473
474 /* Enable msi for devices that support it */
475 pci_enable_msi(pdev);
476
477 /* Setup interrupt handler */
478 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
479 if (ret) {
480 ATH5K_ERR(sc, "request_irq failed\n");
481 goto err_free;
482 }
483
484 /* Initialize device */
485 sc->ah = ath5k_hw_attach(sc, id->driver_data);
486 if (IS_ERR(sc->ah)) {
487 ret = PTR_ERR(sc->ah);
488 goto err_irq;
489 }
490
491 /* Finish private driver data initialization */
492 ret = ath5k_attach(pdev, hw);
493 if (ret)
494 goto err_ah;
495
496 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
497 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
498 sc->ah->ah_mac_srev,
499 sc->ah->ah_phy_revision);
500
400ec45a 501 if (!sc->ah->ah_single_chip) {
fa1c114f 502 /* Single chip radio (!RF5111) */
400ec45a
LR		 503 if (sc->ah->ah_radio_5ghz_revision &&
504 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 505 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 506 if (!test_bit(AR5K_MODE_11A,
507 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 508 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 509 ath5k_chip_name(AR5K_VERSION_RAD,
510 sc->ah->ah_radio_5ghz_revision),
511 sc->ah->ah_radio_5ghz_revision);
512 /* No 2GHz support (5110 and some
513 * 5Ghz only cards) -> report 5Ghz radio */
514 } else if (!test_bit(AR5K_MODE_11B,
515 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 516 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 517 ath5k_chip_name(AR5K_VERSION_RAD,
518 sc->ah->ah_radio_5ghz_revision),
519 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 520 /* Multiband radio */
521 } else {
522 ATH5K_INFO(sc, "RF%s multiband radio found"
523 " (0x%x)\n",
400ec45a
LR		 524 ath5k_chip_name(AR5K_VERSION_RAD,
525 sc->ah->ah_radio_5ghz_revision),
526 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 527 }
528 }
400ec45a
LR		 529 /* Multi chip radio (RF5111 - RF2111) ->
530 * report both 2GHz/5GHz radios */
531 else if (sc->ah->ah_radio_5ghz_revision &&
532 sc->ah->ah_radio_2ghz_revision){
fa1c114f 533 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 534 ath5k_chip_name(AR5K_VERSION_RAD,
535 sc->ah->ah_radio_5ghz_revision),
536 sc->ah->ah_radio_5ghz_revision);
fa1c114f 537 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 538 ath5k_chip_name(AR5K_VERSION_RAD,
539 sc->ah->ah_radio_2ghz_revision),
540 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 541 }
542 }
543
544
545 /* ready to process interrupts */
546 __clear_bit(ATH_STAT_INVALID, sc->status);
547
548 return 0;
549err_ah:
550 ath5k_hw_detach(sc->ah);
551err_irq:
552 free_irq(pdev->irq, sc);
553err_free:
554 pci_disable_msi(pdev);
555 ieee80211_free_hw(hw);
556err_map:
557 pci_iounmap(pdev, mem);
558err_reg:
559 pci_release_region(pdev, 0);
560err_dis:
561 pci_disable_device(pdev);
562err:
563 return ret;
564}
565
566static void __devexit
567ath5k_pci_remove(struct pci_dev *pdev)
568{
569 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
570 struct ath5k_softc *sc = hw->priv;
571
572 ath5k_debug_finish_device(sc);
573 ath5k_detach(pdev, hw);
574 ath5k_hw_detach(sc->ah);
575 free_irq(pdev->irq, sc);
576 pci_disable_msi(pdev);
577 pci_iounmap(pdev, sc->iobase);
578 pci_release_region(pdev, 0);
579 pci_disable_device(pdev);
580 ieee80211_free_hw(hw);
581}
582
583#ifdef CONFIG_PM
584static int
585ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
586{
587 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
588 struct ath5k_softc *sc = hw->priv;
589
3a078876 590 ath5k_led_off(sc);
fa1c114f
JS		 591
592 ath5k_stop_hw(sc);
593 pci_save_state(pdev);
594 pci_disable_device(pdev);
595 pci_set_power_state(pdev, PCI_D3hot);
596
597 return 0;
598}
599
600static int
601ath5k_pci_resume(struct pci_dev *pdev)
602{
603 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
604 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 605 struct ath5k_hw *ah = sc->ah;
606 int i, err;
fa1c114f
JS		 607
608 err = pci_set_power_state(pdev, PCI_D0);
609 if (err)
610 return err;
611
612 err = pci_enable_device(pdev);
613 if (err)
614 return err;
615
616 pci_restore_state(pdev);
617 /*
618 * Suspend/Resume resets the PCI configuration space, so we have to
619 * re-disable the RETRY_TIMEOUT register (0x41) to keep
620 * PCI Tx retries from interfering with C3 CPU state
621 */
622 pci_write_config_byte(pdev, 0x41, 0);
623
624 ath5k_init(sc);
3a078876 625 ath5k_led_enable(sc);
fa1c114f 626
247ae449
JL		 627 /*
628 * Reset the key cache since some parts do not
629 * reset the contents on initial power up or resume.
630 *
631 * FIXME: This may need to be revisited when mac80211 becomes
632 * aware of suspend/resume.
633 */
634 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
635 ath5k_hw_reset_key(ah, i);
636
fa1c114f
JS		 637 return 0;
638}
639#endif /* CONFIG_PM */
640
641
642
643/***********************\
644* Driver Initialization *
645\***********************/
646
647static int
648ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
649{
650 struct ath5k_softc *sc = hw->priv;
651 struct ath5k_hw *ah = sc->ah;
652 u8 mac[ETH_ALEN];
653 unsigned int i;
654 int ret;
655
656 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
657
658 /*
659 * Check if the MAC has multi-rate retry support.
660 * We do this by trying to setup a fake extended
661 * descriptor. MAC's that don't have support will
662 * return false w/o doing anything. MAC's that do
663 * support it will return true w/o doing anything.
664 */
b9887638
JS		 665 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
666 if (ret < 0)
667 goto err;
668 if (ret > 0)
fa1c114f
JS		 669 __set_bit(ATH_STAT_MRRETRY, sc->status);
670
671 /*
672 * Reset the key cache since some parts do not
673 * reset the contents on initial power up.
674 */
c65638a7 675 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 676 ath5k_hw_reset_key(ah, i);
677
678 /*
679 * Collect the channel list. The 802.11 layer
680 * is resposible for filtering this list based
681 * on settings like the phy mode and regulatory
682 * domain restrictions.
683 */
684 ret = ath5k_getchannels(hw);
685 if (ret) {
686 ATH5K_ERR(sc, "can't get channels\n");
687 goto err;
688 }
689
d8ee398d
LR		 690 /* Set *_rates so we can map hw rate index */
691 ath5k_set_total_hw_rates(sc);
692
fa1c114f 693 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 694 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
695 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 696 else
d8ee398d 697 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 698
699 /*
700 * Allocate tx+rx descriptors and populate the lists.
701 */
702 ret = ath5k_desc_alloc(sc, pdev);
703 if (ret) {
704 ATH5K_ERR(sc, "can't allocate descriptors\n");
705 goto err;
706 }
707
708 /*
709 * Allocate hardware transmit queues: one queue for
710 * beacon frames and one data queue for each QoS
711 * priority. Note that hw functions handle reseting
712 * these queues at the needed time.
713 */
714 ret = ath5k_beaconq_setup(ah);
715 if (ret < 0) {
716 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
717 goto err_desc;
718 }
719 sc->bhalq = ret;
720
721 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
722 if (IS_ERR(sc->txq)) {
723 ATH5K_ERR(sc, "can't setup xmit queue\n");
724 ret = PTR_ERR(sc->txq);
725 goto err_bhal;
726 }
727
728 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
729 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
730 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
731 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 732
733 ath5k_hw_get_lladdr(ah, mac);
734 SET_IEEE80211_PERM_ADDR(hw, mac);
735 /* All MAC address bits matter for ACKs */
736 memset(sc->bssidmask, 0xff, ETH_ALEN);
737 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
738
739 ret = ieee80211_register_hw(hw);
740 if (ret) {
741 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
742 goto err_queues;
743 }
744
3a078876
BC		 745 ath5k_init_leds(sc);
746
fa1c114f
JS		 747 return 0;
748err_queues:
749 ath5k_txq_release(sc);
750err_bhal:
751 ath5k_hw_release_tx_queue(ah, sc->bhalq);
752err_desc:
753 ath5k_desc_free(sc, pdev);
754err:
755 return ret;
756}
757
758static void
759ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
760{
761 struct ath5k_softc *sc = hw->priv;
762
763 /*
764 * NB: the order of these is important:
765 * o call the 802.11 layer before detaching ath5k_hw to
766 * insure callbacks into the driver to delete global
767 * key cache entries can be handled
768 * o reclaim the tx queue data structures after calling
769 * the 802.11 layer as we'll get called back to reclaim
770 * node state and potentially want to use them
771 * o to cleanup the tx queues the hal is called, so detach
772 * it last
773 * XXX: ??? detach ath5k_hw ???
774 * Other than that, it's straightforward...
775 */
776 ieee80211_unregister_hw(hw);
777 ath5k_desc_free(sc, pdev);
778 ath5k_txq_release(sc);
779 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 780 ath5k_unregister_leds(sc);
fa1c114f
JS		 781
782 /*
783 * NB: can't reclaim these until after ieee80211_ifdetach
784 * returns because we'll get called back to reclaim node
785 * state and potentially want to use them.
786 */
787}
788
789
790
791
792/********************\
793* Channel/mode setup *
794\********************/
795
796/*
797 * Convert IEEE channel number to MHz frequency.
798 */
799static inline short
800ath5k_ieee2mhz(short chan)
801{
802 if (chan <= 14 || chan >= 27)
803 return ieee80211chan2mhz(chan);
804 else
805 return 2212 + chan * 20;
806}
807
808static unsigned int
809ath5k_copy_rates(struct ieee80211_rate *rates,
810 const struct ath5k_rate_table *rt,
811 unsigned int max)
812{
813 unsigned int i, count;
814
815 if (rt == NULL)
816 return 0;
817
818 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
d8ee398d
LR		 819 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
820 rates[count].hw_value = rt->rates[i].rate_code;
821 rates[count].flags = rt->rates[i].modulation;
fa1c114f
JS		 822 count++;
823 max--;
824 }
825
826 return count;
827}
828
829static unsigned int
830ath5k_copy_channels(struct ath5k_hw *ah,
831 struct ieee80211_channel *channels,
832 unsigned int mode,
833 unsigned int max)
834{
d8ee398d 835 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 836
837 if (!test_bit(mode, ah->ah_modes))
838 return 0;
839
fa1c114f 840 switch (mode) {
d8ee398d
LR		 841 case AR5K_MODE_11A:
842 case AR5K_MODE_11A_TURBO:
fa1c114f 843 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 844 size = 220 ;
fa1c114f
JS		 845 chfreq = CHANNEL_5GHZ;
846 break;
d8ee398d
LR		 847 case AR5K_MODE_11B:
848 case AR5K_MODE_11G:
849 case AR5K_MODE_11G_TURBO:
850 size = 26;
fa1c114f
JS		 851 chfreq = CHANNEL_2GHZ;
852 break;
853 default:
854 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
855 return 0;
856 }
857
858 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 859 ch = i + 1 ;
860 freq = ath5k_ieee2mhz(ch);
fa1c114f 861
d8ee398d
LR		 862 /* Check if channel is supported by the chipset */
863 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 864 continue;
865
d8ee398d
LR		 866 /* Write channel info and increment counter */
867 channels[count].center_freq = freq;
a3f4b914
LR		 868 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
869 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 870 switch (mode) {
871 case AR5K_MODE_11A:
872 case AR5K_MODE_11G:
873 channels[count].hw_value = chfreq | CHANNEL_OFDM;
874 break;
875 case AR5K_MODE_11A_TURBO:
876 case AR5K_MODE_11G_TURBO:
877 channels[count].hw_value = chfreq |
878 CHANNEL_OFDM | CHANNEL_TURBO;
879 break;
880 case AR5K_MODE_11B:
d8ee398d
LR		 881 channels[count].hw_value = CHANNEL_B;
882 }
fa1c114f 883
fa1c114f
JS		 884 count++;
885 max--;
886 }
887
888 return count;
889}
890
d8ee398d
LR		 891static int
892ath5k_getchannels(struct ieee80211_hw *hw)
fa1c114f
JS		 893{
894 struct ath5k_softc *sc = hw->priv;
d8ee398d
LR		 895 struct ath5k_hw *ah = sc->ah;
896 struct ieee80211_supported_band *sbands = sc->sbands;
897 const struct ath5k_rate_table *hw_rates;
898 unsigned int max_r, max_c, count_r, count_c;
899 int mode2g = AR5K_MODE_11G;
fa1c114f 900
d8ee398d 901 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
fa1c114f 902
d8ee398d
LR		 903 max_r = ARRAY_SIZE(sc->rates);
904 max_c = ARRAY_SIZE(sc->channels);
905 count_r = count_c = 0;
906
907 /* 2GHz band */
400ec45a 908 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
d8ee398d 909 mode2g = AR5K_MODE_11B;
400ec45a
LR		 910 if (!test_bit(AR5K_MODE_11B,
911 sc->ah->ah_capabilities.cap_mode))
d8ee398d 912 mode2g = -1;
fa1c114f 913 }
fa1c114f 914
400ec45a
LR		 915 if (mode2g > 0) {
916 struct ieee80211_supported_band *sband =
917 &sbands[IEEE80211_BAND_2GHZ];
fa1c114f 918
d8ee398d
LR		 919 sband->bitrates = sc->rates;
920 sband->channels = sc->channels;
fa1c114f 921
d8ee398d
LR		 922 sband->band = IEEE80211_BAND_2GHZ;
923 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
924 mode2g, max_c);
fa1c114f 925
d8ee398d
LR		 926 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
927 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 928 hw_rates, max_r);
fa1c114f 929
d8ee398d
LR		 930 count_c = sband->n_channels;
931 count_r = sband->n_bitrates;
fa1c114f 932
d8ee398d
LR		 933 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
934
935 max_r -= count_r;
936 max_c -= count_c;
fa1c114f 937
fa1c114f
JS		 938 }
939
d8ee398d 940 /* 5GHz band */
fa1c114f 941
400ec45a
LR		 942 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
943 struct ieee80211_supported_band *sband =
944 &sbands[IEEE80211_BAND_5GHZ];
fa1c114f 945
d8ee398d
LR		 946 sband->bitrates = &sc->rates[count_r];
947 sband->channels = &sc->channels[count_c];
fa1c114f 948
d8ee398d
LR		 949 sband->band = IEEE80211_BAND_5GHZ;
950 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
951 AR5K_MODE_11A, max_c);
952
953 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
954 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 955 hw_rates, max_r);
d8ee398d
LR		 956
957 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
958 }
959
b446197c 960 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 961
962 return 0;
fa1c114f
JS		 963}
964
965/*
966 * Set/change channels. If the channel is really being changed,
967 * it's done by reseting the chip. To accomplish this we must
968 * first cleanup any pending DMA, then restart stuff after a la
969 * ath5k_init.
970 */
971static int
972ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
973{
974 struct ath5k_hw *ah = sc->ah;
975 int ret;
976
d8ee398d
LR		 977 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
978 sc->curchan->center_freq, chan->center_freq);
979
980 if (chan->center_freq != sc->curchan->center_freq ||
981 chan->hw_value != sc->curchan->hw_value) {
982
983 sc->curchan = chan;
984 sc->curband = &sc->sbands[chan->band];
fa1c114f 985
fa1c114f
JS		 986 /*
987 * To switch channels clear any pending DMA operations;
988 * wait long enough for the RX fifo to drain, reset the
989 * hardware at the new frequency, and then re-enable
990 * the relevant bits of the h/w.
991 */
992 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
993 ath5k_txq_cleanup(sc); /* clear pending tx frames */
994 ath5k_rx_stop(sc); /* turn off frame recv */
d8ee398d 995 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
fa1c114f 996 if (ret) {
d8ee398d
LR		 997 ATH5K_ERR(sc, "%s: unable to reset channel "
998 "(%u Mhz)\n", __func__, chan->center_freq);
fa1c114f
JS		 999 return ret;
1000 }
d8ee398d 1001
fa1c114f
JS		 1002 ath5k_hw_set_txpower_limit(sc->ah, 0);
1003
1004 /*
1005 * Re-enable rx framework.
1006 */
1007 ret = ath5k_rx_start(sc);
1008 if (ret) {
1009 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1010 __func__);
1011 return ret;
1012 }
1013
1014 /*
1015 * Change channels and update the h/w rate map
1016 * if we're switching; e.g. 11a to 11b/g.
1017 *
1018 * XXX needed?
1019 */
1020/* ath5k_chan_change(sc, chan); */
1021
1022 ath5k_beacon_config(sc);
1023 /*
1024 * Re-enable interrupts.
1025 */
1026 ath5k_hw_set_intr(ah, sc->imask);
1027 }
1028
1029 return 0;
1030}
1031
1032static void
1033ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1034{
fa1c114f 1035 sc->curmode = mode;
d8ee398d 1036
400ec45a 1037 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1038 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1039 } else {
1040 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1041 }
fa1c114f
JS		 1042}
1043
1044static void
1045ath5k_mode_setup(struct ath5k_softc *sc)
1046{
1047 struct ath5k_hw *ah = sc->ah;
1048 u32 rfilt;
1049
1050 /* configure rx filter */
1051 rfilt = sc->filter_flags;
1052 ath5k_hw_set_rx_filter(ah, rfilt);
1053
1054 if (ath5k_hw_hasbssidmask(ah))
1055 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1056
1057 /* configure operational mode */
1058 ath5k_hw_set_opmode(ah);
1059
1060 ath5k_hw_set_mcast_filter(ah, 0, 0);
1061 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1062}
1063
d8ee398d
LR		 1064/*
1065 * Match the hw provided rate index (through descriptors)
1066 * to an index for sc->curband->bitrates, so it can be used
1067 * by the stack.
1068 *
1069 * This one is a little bit tricky but i think i'm right
1070 * about this...
1071 *
1072 * We have 4 rate tables in the following order:
1073 * XR (4 rates)
1074 * 802.11a (8 rates)
1075 * 802.11b (4 rates)
1076 * 802.11g (12 rates)
1077 * that make the hw rate table.
1078 *
1079 * Lets take a 5211 for example that supports a and b modes only.
1080 * First comes the 802.11a table and then 802.11b (total 12 rates).
1081 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1082 * if it returns 2 it points to the second 802.11a rate etc.
1083 *
1084 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1085 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1086 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1087 */
1088static void
400ec45a 1089ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
d8ee398d
LR		 1090
1091 struct ath5k_hw *ah = sc->ah;
1092
400ec45a 1093 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
d8ee398d
LR		 1094 sc->a_rates = 8;
1095
400ec45a 1096 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
d8ee398d
LR		 1097 sc->b_rates = 4;
1098
400ec45a 1099 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
d8ee398d
LR		 1100 sc->g_rates = 12;
1101
1102 /* XXX: Need to see what what happens when
1103 xr disable bits in eeprom are set */
400ec45a 1104 if (ah->ah_version >= AR5K_AR5212)
d8ee398d
LR		 1105 sc->xr_rates = 4;
1106
1107}
1108
1109static inline int
400ec45a 1110ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
d8ee398d
LR		 1111
1112 int mac80211_rix;
1113
400ec45a 1114 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
d8ee398d 1115 /* We setup a g ratetable for both b/g modes */
400ec45a
LR		 1116 mac80211_rix =
1117 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
d8ee398d
LR		 1118 } else {
1119 mac80211_rix = hw_rix - sc->xr_rates;
1120 }
1121
1122 /* Something went wrong, fallback to basic rate for this band */
400ec45a
LR		 1123 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1124 (mac80211_rix <= 0 ))
d8ee398d 1125 mac80211_rix = 1;
d8ee398d
LR		 1126
1127 return mac80211_rix;
1128}
1129
fa1c114f
JS		 1130
1131
1132
1133/***************\
1134* Buffers setup *
1135\***************/
1136
1137static int
1138ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1139{
1140 struct ath5k_hw *ah = sc->ah;
1141 struct sk_buff *skb = bf->skb;
1142 struct ath5k_desc *ds;
1143
1144 if (likely(skb == NULL)) {
1145 unsigned int off;
1146
1147 /*
1148 * Allocate buffer with headroom_needed space for the
1149 * fake physical layer header at the start.
1150 */
1151 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1152 if (unlikely(skb == NULL)) {
1153 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1154 sc->rxbufsize + sc->cachelsz - 1);
1155 return -ENOMEM;
1156 }
1157 /*
1158 * Cache-line-align. This is important (for the
1159 * 5210 at least) as not doing so causes bogus data
1160 * in rx'd frames.
1161 */
1162 off = ((unsigned long)skb->data) % sc->cachelsz;
1163 if (off != 0)
1164 skb_reserve(skb, sc->cachelsz - off);
1165
1166 bf->skb = skb;
1167 bf->skbaddr = pci_map_single(sc->pdev,
1168 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1169 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1170 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1171 dev_kfree_skb(skb);
1172 bf->skb = NULL;
1173 return -ENOMEM;
1174 }
1175 }
1176
1177 /*
1178 * Setup descriptors. For receive we always terminate
1179 * the descriptor list with a self-linked entry so we'll
1180 * not get overrun under high load (as can happen with a
1181 * 5212 when ANI processing enables PHY error frames).
1182 *
1183 * To insure the last descriptor is self-linked we create
1184 * each descriptor as self-linked and add it to the end. As
1185 * each additional descriptor is added the previous self-linked
1186 * entry is ``fixed'' naturally. This should be safe even
1187 * if DMA is happening. When processing RX interrupts we
1188 * never remove/process the last, self-linked, entry on the
1189 * descriptor list. This insures the hardware always has
1190 * someplace to write a new frame.
1191 */
1192 ds = bf->desc;
1193 ds->ds_link = bf->daddr; /* link to self */
1194 ds->ds_data = bf->skbaddr;
1195 ath5k_hw_setup_rx_desc(ah, ds,
1196 skb_tailroom(skb), /* buffer size */
1197 0);
1198
1199 if (sc->rxlink != NULL)
1200 *sc->rxlink = bf->daddr;
1201 sc->rxlink = &ds->ds_link;
1202 return 0;
1203}
1204
1205static int
e039fa4a 1206ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1207{
1208 struct ath5k_hw *ah = sc->ah;
1209 struct ath5k_txq *txq = sc->txq;
1210 struct ath5k_desc *ds = bf->desc;
1211 struct sk_buff *skb = bf->skb;
a888d52d 1212 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1213 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1214 int ret;
1215
1216 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1217
fa1c114f
JS		 1218 /* XXX endianness */
1219 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1220 PCI_DMA_TODEVICE);
1221
e039fa4a 1222 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1223 flags |= AR5K_TXDESC_NOACK;
1224
281c56dd 1225 pktlen = skb->len;
fa1c114f 1226
e039fa4a
JB		 1227 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
1228 keyidx = info->control.hw_key->hw_key_idx;
1229 pktlen += info->control.icv_len;
fa1c114f 1230 }
fa1c114f
JS		 1231 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1232 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1233 (sc->power_level * 2),
e039fa4a
JB		 1234 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1235 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1236 if (ret)
1237 goto err_unmap;
1238
1239 ds->ds_link = 0;
1240 ds->ds_data = bf->skbaddr;
1241
1242 spin_lock_bh(&txq->lock);
1243 list_add_tail(&bf->list, &txq->q);
57ffc589 1244 sc->tx_stats[txq->qnum].len++;
fa1c114f
JS		 1245 if (txq->link == NULL) /* is this first packet? */
1246 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1247 else /* no, so only link it */
1248 *txq->link = bf->daddr;
1249
1250 txq->link = &ds->ds_link;
1251 ath5k_hw_tx_start(ah, txq->qnum);
1252 spin_unlock_bh(&txq->lock);
1253
1254 return 0;
1255err_unmap:
1256 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1257 return ret;
1258}
1259
1260/*******************\
1261* Descriptors setup *
1262\*******************/
1263
1264static int
1265ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1266{
1267 struct ath5k_desc *ds;
1268 struct ath5k_buf *bf;
1269 dma_addr_t da;
1270 unsigned int i;
1271 int ret;
1272
1273 /* allocate descriptors */
1274 sc->desc_len = sizeof(struct ath5k_desc) *
1275 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1276 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1277 if (sc->desc == NULL) {
1278 ATH5K_ERR(sc, "can't allocate descriptors\n");
1279 ret = -ENOMEM;
1280 goto err;
1281 }
1282 ds = sc->desc;
1283 da = sc->desc_daddr;
1284 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1285 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1286
1287 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1288 sizeof(struct ath5k_buf), GFP_KERNEL);
1289 if (bf == NULL) {
1290 ATH5K_ERR(sc, "can't allocate bufptr\n");
1291 ret = -ENOMEM;
1292 goto err_free;
1293 }
1294 sc->bufptr = bf;
1295
1296 INIT_LIST_HEAD(&sc->rxbuf);
1297 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1298 bf->desc = ds;
1299 bf->daddr = da;
1300 list_add_tail(&bf->list, &sc->rxbuf);
1301 }
1302
1303 INIT_LIST_HEAD(&sc->txbuf);
1304 sc->txbuf_len = ATH_TXBUF;
1305 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1306 da += sizeof(*ds)) {
1307 bf->desc = ds;
1308 bf->daddr = da;
1309 list_add_tail(&bf->list, &sc->txbuf);
1310 }
1311
1312 /* beacon buffer */
1313 bf->desc = ds;
1314 bf->daddr = da;
1315 sc->bbuf = bf;
1316
1317 return 0;
1318err_free:
1319 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1320err:
1321 sc->desc = NULL;
1322 return ret;
1323}
1324
1325static void
1326ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1327{
1328 struct ath5k_buf *bf;
1329
1330 ath5k_txbuf_free(sc, sc->bbuf);
1331 list_for_each_entry(bf, &sc->txbuf, list)
1332 ath5k_txbuf_free(sc, bf);
1333 list_for_each_entry(bf, &sc->rxbuf, list)
1334 ath5k_txbuf_free(sc, bf);
1335
1336 /* Free memory associated with all descriptors */
1337 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1338
1339 kfree(sc->bufptr);
1340 sc->bufptr = NULL;
1341}
1342
1343
1344
1345
1346
1347/**************\
1348* Queues setup *
1349\**************/
1350
1351static struct ath5k_txq *
1352ath5k_txq_setup(struct ath5k_softc *sc,
1353 int qtype, int subtype)
1354{
1355 struct ath5k_hw *ah = sc->ah;
1356 struct ath5k_txq *txq;
1357 struct ath5k_txq_info qi = {
1358 .tqi_subtype = subtype,
1359 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1360 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1361 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1362 };
1363 int qnum;
1364
1365 /*
1366 * Enable interrupts only for EOL and DESC conditions.
1367 * We mark tx descriptors to receive a DESC interrupt
1368 * when a tx queue gets deep; otherwise waiting for the
1369 * EOL to reap descriptors. Note that this is done to
1370 * reduce interrupt load and this only defers reaping
1371 * descriptors, never transmitting frames. Aside from
1372 * reducing interrupts this also permits more concurrency.
1373 * The only potential downside is if the tx queue backs
1374 * up in which case the top half of the kernel may backup
1375 * due to a lack of tx descriptors.
1376 */
1377 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1378 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1379 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1380 if (qnum < 0) {
1381 /*
1382 * NB: don't print a message, this happens
1383 * normally on parts with too few tx queues
1384 */
1385 return ERR_PTR(qnum);
1386 }
1387 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1388 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1389 qnum, ARRAY_SIZE(sc->txqs));
1390 ath5k_hw_release_tx_queue(ah, qnum);
1391 return ERR_PTR(-EINVAL);
1392 }
1393 txq = &sc->txqs[qnum];
1394 if (!txq->setup) {
1395 txq->qnum = qnum;
1396 txq->link = NULL;
1397 INIT_LIST_HEAD(&txq->q);
1398 spin_lock_init(&txq->lock);
1399 txq->setup = true;
1400 }
1401 return &sc->txqs[qnum];
1402}
1403
1404static int
1405ath5k_beaconq_setup(struct ath5k_hw *ah)
1406{
1407 struct ath5k_txq_info qi = {
1408 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1409 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1410 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1411 /* NB: for dynamic turbo, don't enable any other interrupts */
1412 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1413 };
1414
1415 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1416}
1417
1418static int
1419ath5k_beaconq_config(struct ath5k_softc *sc)
1420{
1421 struct ath5k_hw *ah = sc->ah;
1422 struct ath5k_txq_info qi;
1423 int ret;
1424
1425 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1426 if (ret)
1427 return ret;
6d91e1d8 1428 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
fa1c114f
JS		 1429 /*
1430 * Always burst out beacon and CAB traffic
1431 * (aifs = cwmin = cwmax = 0)
1432 */
1433 qi.tqi_aifs = 0;
1434 qi.tqi_cw_min = 0;
1435 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1436 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1437 /*
1438 * Adhoc mode; backoff between 0 and (2 * cw_min).
1439 */
1440 qi.tqi_aifs = 0;
1441 qi.tqi_cw_min = 0;
1442 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1443 }
1444
6d91e1d8
BR		 1445 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1446 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1447 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1448
fa1c114f
JS		 1449 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1450 if (ret) {
1451 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1452 "hardware queue!\n", __func__);
1453 return ret;
1454 }
1455
1456 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1457}
1458
1459static void
1460ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1461{
1462 struct ath5k_buf *bf, *bf0;
1463
1464 /*
1465 * NB: this assumes output has been stopped and
1466 * we do not need to block ath5k_tx_tasklet
1467 */
1468 spin_lock_bh(&txq->lock);
1469 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1470 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1471
1472 ath5k_txbuf_free(sc, bf);
1473
1474 spin_lock_bh(&sc->txbuflock);
57ffc589 1475 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1476 list_move_tail(&bf->list, &sc->txbuf);
1477 sc->txbuf_len++;
1478 spin_unlock_bh(&sc->txbuflock);
1479 }
1480 txq->link = NULL;
1481 spin_unlock_bh(&txq->lock);
1482}
1483
1484/*
1485 * Drain the transmit queues and reclaim resources.
1486 */
1487static void
1488ath5k_txq_cleanup(struct ath5k_softc *sc)
1489{
1490 struct ath5k_hw *ah = sc->ah;
1491 unsigned int i;
1492
1493 /* XXX return value */
1494 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1495 /* don't touch the hardware if marked invalid */
1496 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1497 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1498 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1499 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1500 if (sc->txqs[i].setup) {
1501 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1502 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1503 "link %p\n",
1504 sc->txqs[i].qnum,
1505 ath5k_hw_get_tx_buf(ah,
1506 sc->txqs[i].qnum),
1507 sc->txqs[i].link);
1508 }
1509 }
36d6825b 1510 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1511
1512 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1513 if (sc->txqs[i].setup)
1514 ath5k_txq_drainq(sc, &sc->txqs[i]);
1515}
1516
1517static void
1518ath5k_txq_release(struct ath5k_softc *sc)
1519{
1520 struct ath5k_txq *txq = sc->txqs;
1521 unsigned int i;
1522
1523 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1524 if (txq->setup) {
1525 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1526 txq->setup = false;
1527 }
1528}
1529
1530
1531
1532
1533/*************\
1534* RX Handling *
1535\*************/
1536
1537/*
1538 * Enable the receive h/w following a reset.
1539 */
1540static int
1541ath5k_rx_start(struct ath5k_softc *sc)
1542{
1543 struct ath5k_hw *ah = sc->ah;
1544 struct ath5k_buf *bf;
1545 int ret;
1546
1547 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1548
1549 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1550 sc->cachelsz, sc->rxbufsize);
1551
1552 sc->rxlink = NULL;
1553
1554 spin_lock_bh(&sc->rxbuflock);
1555 list_for_each_entry(bf, &sc->rxbuf, list) {
1556 ret = ath5k_rxbuf_setup(sc, bf);
1557 if (ret != 0) {
1558 spin_unlock_bh(&sc->rxbuflock);
1559 goto err;
1560 }
1561 }
1562 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1563 spin_unlock_bh(&sc->rxbuflock);
1564
1565 ath5k_hw_put_rx_buf(ah, bf->daddr);
1566 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1567 ath5k_mode_setup(sc); /* set filters, etc. */
1568 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1569
1570 return 0;
1571err:
1572 return ret;
1573}
1574
1575/*
1576 * Disable the receive h/w in preparation for a reset.
1577 */
1578static void
1579ath5k_rx_stop(struct ath5k_softc *sc)
1580{
1581 struct ath5k_hw *ah = sc->ah;
1582
1583 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1584 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1585 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1586 mdelay(3); /* 3ms is long enough for 1 frame */
1587
1588 ath5k_debug_printrxbuffs(sc, ah);
1589
1590 sc->rxlink = NULL; /* just in case */
1591}
1592
1593static unsigned int
1594ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1595 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1596{
1597 struct ieee80211_hdr *hdr = (void *)skb->data;
1598 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1599
b47f407b
BR		 1600 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1601 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1602 return RX_FLAG_DECRYPTED;
1603
1604 /* Apparently when a default key is used to decrypt the packet
1605 the hw does not set the index used to decrypt. In such cases
1606 get the index from the packet. */
24b56e70
HH		 1607 if (ieee80211_has_protected(hdr->frame_control) &&
1608 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1609 skb->len >= hlen + 4) {
fa1c114f
JS		 1610 keyix = skb->data[hlen + 3] >> 6;
1611
1612 if (test_bit(keyix, sc->keymap))
1613 return RX_FLAG_DECRYPTED;
1614 }
1615
1616 return 0;
1617}
1618
036cd1ec
BR		 1619
1620static void
6ba81c2c
BR		 1621ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1622 struct ieee80211_rx_status *rxs)
036cd1ec 1623{
6ba81c2c 1624 u64 tsf, bc_tstamp;
036cd1ec
BR		 1625 u32 hw_tu;
1626 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1627
24b56e70 1628 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1629 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1630 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1631 /*
6ba81c2c
BR		 1632 * Received an IBSS beacon with the same BSSID. Hardware *must*
1633 * have updated the local TSF. We have to work around various
1634 * hardware bugs, though...
036cd1ec 1635 */
6ba81c2c
BR		 1636 tsf = ath5k_hw_get_tsf64(sc->ah);
1637 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1638 hw_tu = TSF_TO_TU(tsf);
1639
1640 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1641 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1642 (unsigned long long)bc_tstamp,
1643 (unsigned long long)rxs->mactime,
1644 (unsigned long long)(rxs->mactime - bc_tstamp),
1645 (unsigned long long)tsf);
6ba81c2c
BR		 1646
1647 /*
1648 * Sometimes the HW will give us a wrong tstamp in the rx
1649 * status, causing the timestamp extension to go wrong.
1650 * (This seems to happen especially with beacon frames bigger
1651 * than 78 byte (incl. FCS))
1652 * But we know that the receive timestamp must be later than the
1653 * timestamp of the beacon since HW must have synced to that.
1654 *
1655 * NOTE: here we assume mactime to be after the frame was
1656 * received, not like mac80211 which defines it at the start.
1657 */
1658 if (bc_tstamp > rxs->mactime) {
036cd1ec 1659 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1660 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1661 (unsigned long long)rxs->mactime,
1662 (unsigned long long)tsf);
6ba81c2c 1663 rxs->mactime = tsf;
036cd1ec 1664 }
6ba81c2c
BR		 1665
1666 /*
1667 * Local TSF might have moved higher than our beacon timers,
1668 * in that case we have to update them to continue sending
1669 * beacons. This also takes care of synchronizing beacon sending
1670 * times with other stations.
1671 */
1672 if (hw_tu >= sc->nexttbtt)
1673 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1674 }
1675}
1676
1677
fa1c114f
JS		 1678static void
1679ath5k_tasklet_rx(unsigned long data)
1680{
1681 struct ieee80211_rx_status rxs = {};
b47f407b 1682 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1683 struct sk_buff *skb;
1684 struct ath5k_softc *sc = (void *)data;
1685 struct ath5k_buf *bf;
1686 struct ath5k_desc *ds;
fa1c114f
JS		 1687 int ret;
1688 int hdrlen;
1689 int pad;
1690
1691 spin_lock(&sc->rxbuflock);
1692 do {
d6894b5b
BC		 1693 rxs.flag = 0;
1694
fa1c114f
JS		 1695 if (unlikely(list_empty(&sc->rxbuf))) {
1696 ATH5K_WARN(sc, "empty rx buf pool\n");
1697 break;
1698 }
1699 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1700 BUG_ON(bf->skb == NULL);
1701 skb = bf->skb;
1702 ds = bf->desc;
1703
1704 /* TODO only one segment */
1705 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1706 sc->desc_len, PCI_DMA_FROMDEVICE);
1707
1708 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1709 break;
1710
b47f407b 1711 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1712 if (unlikely(ret == -EINPROGRESS))
1713 break;
1714 else if (unlikely(ret)) {
1715 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1716 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1717 return;
1718 }
1719
b47f407b 1720 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1721 ATH5K_WARN(sc, "unsupported jumbo\n");
1722 goto next;
1723 }
1724
b47f407b
BR		 1725 if (unlikely(rs.rs_status)) {
1726 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1727 goto next;
b47f407b 1728 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1729 /*
1730 * Decrypt error. If the error occurred
1731 * because there was no hardware key, then
1732 * let the frame through so the upper layers
1733 * can process it. This is necessary for 5210
1734 * parts which have no way to setup a ``clear''
1735 * key cache entry.
1736 *
1737 * XXX do key cache faulting
1738 */
b47f407b
BR		 1739 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1740 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1741 goto accept;
1742 }
b47f407b 1743 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1744 rxs.flag |= RX_FLAG_MMIC_ERROR;
1745 goto accept;
1746 }
1747
1748 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1749 if ((rs.rs_status &
1750 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
fa1c114f
JS		 1751 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1752 goto next;
1753 }
1754accept:
b47f407b
BR		 1755 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr,
1756 rs.rs_datalen, PCI_DMA_FROMDEVICE);
fa1c114f
JS		 1757 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1758 PCI_DMA_FROMDEVICE);
1759 bf->skb = NULL;
1760
b47f407b 1761 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1762
1763 /*
1764 * the hardware adds a padding to 4 byte boundaries between
1765 * the header and the payload data if the header length is
1766 * not multiples of 4 - remove it
1767 */
1768 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1769 if (hdrlen & 3) {
1770 pad = hdrlen % 4;
1771 memmove(skb->data + pad, skb->data, hdrlen);
1772 skb_pull(skb, pad);
1773 }
1774
c0e1899b
BR		 1775 /*
1776 * always extend the mac timestamp, since this information is
1777 * also needed for proper IBSS merging.
1778 *
1779 * XXX: it might be too late to do it here, since rs_tstamp is
1780 * 15bit only. that means TSF extension has to be done within
1781 * 32768usec (about 32ms). it might be necessary to move this to
1782 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1783 *
1784 * Unfortunately we don't know when the hardware takes the rx
1785 * timestamp (beginning of phy frame, data frame, end of rx?).
1786 * The only thing we know is that it is hardware specific...
1787 * On AR5213 it seems the rx timestamp is at the end of the
1788 * frame, but i'm not sure.
1789 *
1790 * NOTE: mac80211 defines mactime at the beginning of the first
1791 * data symbol. Since we don't have any time references it's
1792 * impossible to comply to that. This affects IBSS merge only
1793 * right now, so it's not too bad...
c0e1899b 1794 */
b47f407b 1795 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1796 rxs.flag |= RX_FLAG_TSFT;
1797
d8ee398d
LR		 1798 rxs.freq = sc->curchan->center_freq;
1799 rxs.band = sc->curband->band;
fa1c114f 1800
fa1c114f 1801 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1802 rxs.signal = rxs.noise + rs.rs_rssi;
1803 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1804
b47f407b
BR		 1805 rxs.antenna = rs.rs_antenna;
1806 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1807 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f
JS		 1808
1809 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1810
036cd1ec
BR		 1811 /* check beacons in IBSS mode */
1812 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
6ba81c2c 1813 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1814
fa1c114f 1815 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1816next:
1817 list_move_tail(&bf->list, &sc->rxbuf);
1818 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1819 spin_unlock(&sc->rxbuflock);
1820}
1821
1822
1823
1824
1825/*************\
1826* TX Handling *
1827\*************/
1828
1829static void
1830ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1831{
b47f407b 1832 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1833 struct ath5k_buf *bf, *bf0;
1834 struct ath5k_desc *ds;
1835 struct sk_buff *skb;
e039fa4a 1836 struct ieee80211_tx_info *info;
fa1c114f
JS		 1837 int ret;
1838
1839 spin_lock(&txq->lock);
1840 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1841 ds = bf->desc;
1842
1843 /* TODO only one segment */
1844 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1845 sc->desc_len, PCI_DMA_FROMDEVICE);
b47f407b 1846 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1847 if (unlikely(ret == -EINPROGRESS))
1848 break;
1849 else if (unlikely(ret)) {
1850 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1851 ret, txq->qnum);
1852 break;
1853 }
1854
1855 skb = bf->skb;
a888d52d 1856 info = IEEE80211_SKB_CB(skb);
fa1c114f 1857 bf->skb = NULL;
e039fa4a 1858
fa1c114f
JS		 1859 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1860 PCI_DMA_TODEVICE);
1861
e039fa4a 1862 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1863 if (unlikely(ts.ts_status)) {
fa1c114f 1864 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1865 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1866 info->status.excessive_retries = 1;
b47f407b 1867 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1868 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1869 } else {
e039fa4a
JB		 1870 info->flags |= IEEE80211_TX_STAT_ACK;
1871 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1872 }
1873
e039fa4a 1874 ieee80211_tx_status(sc->hw, skb);
57ffc589 1875 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1876
1877 spin_lock(&sc->txbuflock);
57ffc589 1878 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1879 list_move_tail(&bf->list, &sc->txbuf);
1880 sc->txbuf_len++;
1881 spin_unlock(&sc->txbuflock);
1882 }
1883 if (likely(list_empty(&txq->q)))
1884 txq->link = NULL;
1885 spin_unlock(&txq->lock);
1886 if (sc->txbuf_len > ATH_TXBUF / 5)
1887 ieee80211_wake_queues(sc->hw);
1888}
1889
1890static void
1891ath5k_tasklet_tx(unsigned long data)
1892{
1893 struct ath5k_softc *sc = (void *)data;
1894
1895 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1896}
1897
1898
fa1c114f
JS		 1899/*****************\
1900* Beacon handling *
1901\*****************/
1902
1903/*
1904 * Setup the beacon frame for transmit.
1905 */
1906static int
e039fa4a 1907ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1908{
1909 struct sk_buff *skb = bf->skb;
a888d52d 1910 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1911 struct ath5k_hw *ah = sc->ah;
1912 struct ath5k_desc *ds;
1913 int ret, antenna = 0;
1914 u32 flags;
1915
1916 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1917 PCI_DMA_TODEVICE);
1918 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1919 "skbaddr %llx\n", skb, skb->data, skb->len,
1920 (unsigned long long)bf->skbaddr);
8d8bb39b 1921 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1922 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1923 return -EIO;
1924 }
1925
1926 ds = bf->desc;
1927
1928 flags = AR5K_TXDESC_NOACK;
1929 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1930 ds->ds_link = bf->daddr; /* self-linked */
1931 flags |= AR5K_TXDESC_VEOL;
1932 /*
1933 * Let hardware handle antenna switching if txantenna is not set
1934 */
1935 } else {
1936 ds->ds_link = 0;
1937 /*
1938 * Switch antenna every 4 beacons if txantenna is not set
1939 * XXX assumes two antennas
1940 */
1941 if (antenna == 0)
1942 antenna = sc->bsent & 4 ? 2 : 1;
1943 }
1944
1945 ds->ds_data = bf->skbaddr;
281c56dd 1946 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1947 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1948 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1949 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1950 1, AR5K_TXKEYIX_INVALID,
400ec45a 1951 antenna, flags, 0, 0);
fa1c114f
JS		 1952 if (ret)
1953 goto err_unmap;
1954
1955 return 0;
1956err_unmap:
1957 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1958 return ret;
1959}
1960
1961/*
1962 * Transmit a beacon frame at SWBA. Dynamic updates to the
1963 * frame contents are done as needed and the slot time is
1964 * also adjusted based on current state.
1965 *
1966 * this is usually called from interrupt context (ath5k_intr())
1967 * but also from ath5k_beacon_config() in IBSS mode which in turn
1968 * can be called from a tasklet and user context
1969 */
1970static void
1971ath5k_beacon_send(struct ath5k_softc *sc)
1972{
1973 struct ath5k_buf *bf = sc->bbuf;
1974 struct ath5k_hw *ah = sc->ah;
1975
be9b7259 1976 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 1977
1978 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1979 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1980 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1981 return;
1982 }
1983 /*
1984 * Check if the previous beacon has gone out. If
1985 * not don't don't try to post another, skip this
1986 * period and wait for the next. Missed beacons
1987 * indicate a problem and should not occur. If we
1988 * miss too many consecutive beacons reset the device.
1989 */
1990 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1991 sc->bmisscount++;
be9b7259 1992 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1993 "missed %u consecutive beacons\n", sc->bmisscount);
1994 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 1995 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1996 "stuck beacon time (%u missed)\n",
1997 sc->bmisscount);
1998 tasklet_schedule(&sc->restq);
1999 }
2000 return;
2001 }
2002 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2003 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2004 "resume beacon xmit after %u misses\n",
2005 sc->bmisscount);
2006 sc->bmisscount = 0;
2007 }
2008
2009 /*
2010 * Stop any current dma and put the new frame on the queue.
2011 * This should never fail since we check above that no frames
2012 * are still pending on the queue.
2013 */
2014 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2015 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2016 /* NB: hw still stops DMA, so proceed */
2017 }
2018 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2019 PCI_DMA_TODEVICE);
2020
2021 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2022 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2023 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2024 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2025
2026 sc->bsent++;
2027}
2028
2029
9804b98d
BR		 2030/**
2031 * ath5k_beacon_update_timers - update beacon timers
2032 *
2033 * @sc: struct ath5k_softc pointer we are operating on
2034 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2035 * beacon timer update based on the current HW TSF.
2036 *
2037 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2038 * of a received beacon or the current local hardware TSF and write it to the
2039 * beacon timer registers.
2040 *
2041 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2042 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2043 * when we otherwise know we have to update the timers, but we keep it in this
2044 * function to have it all together in one place.
2045 */
fa1c114f 2046static void
9804b98d 2047ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2048{
2049 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2050 u32 nexttbtt, intval, hw_tu, bc_tu;
2051 u64 hw_tsf;
fa1c114f
JS		 2052
2053 intval = sc->bintval & AR5K_BEACON_PERIOD;
2054 if (WARN_ON(!intval))
2055 return;
2056
9804b98d
BR		 2057 /* beacon TSF converted to TU */
2058 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2059
9804b98d
BR		 2060 /* current TSF converted to TU */
2061 hw_tsf = ath5k_hw_get_tsf64(ah);
2062 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2063
9804b98d
BR		 2064#define FUDGE 3
2065 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2066 if (bc_tsf == -1) {
2067 /*
2068 * no beacons received, called internally.
2069 * just need to refresh timers based on HW TSF.
2070 */
2071 nexttbtt = roundup(hw_tu + FUDGE, intval);
2072 } else if (bc_tsf == 0) {
2073 /*
2074 * no beacon received, probably called by ath5k_reset_tsf().
2075 * reset TSF to start with 0.
2076 */
2077 nexttbtt = intval;
2078 intval |= AR5K_BEACON_RESET_TSF;
2079 } else if (bc_tsf > hw_tsf) {
2080 /*
2081 * beacon received, SW merge happend but HW TSF not yet updated.
2082 * not possible to reconfigure timers yet, but next time we
2083 * receive a beacon with the same BSSID, the hardware will
2084 * automatically update the TSF and then we need to reconfigure
2085 * the timers.
2086 */
2087 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2088 "need to wait for HW TSF sync\n");
2089 return;
2090 } else {
2091 /*
2092 * most important case for beacon synchronization between STA.
2093 *
2094 * beacon received and HW TSF has been already updated by HW.
2095 * update next TBTT based on the TSF of the beacon, but make
2096 * sure it is ahead of our local TSF timer.
2097 */
2098 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2099 }
2100#undef FUDGE
fa1c114f 2101
036cd1ec
BR		 2102 sc->nexttbtt = nexttbtt;
2103
fa1c114f 2104 intval |= AR5K_BEACON_ENA;
fa1c114f 2105 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2106
2107 /*
2108 * debugging output last in order to preserve the time critical aspect
2109 * of this function
2110 */
2111 if (bc_tsf == -1)
2112 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2113 "reconfigured timers based on HW TSF\n");
2114 else if (bc_tsf == 0)
2115 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2116 "reset HW TSF and timers\n");
2117 else
2118 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2119 "updated timers based on beacon TSF\n");
2120
2121 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2122 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2123 (unsigned long long) bc_tsf,
2124 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2125 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2126 intval & AR5K_BEACON_PERIOD,
2127 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2128 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2129}
2130
2131
036cd1ec
BR		 2132/**
2133 * ath5k_beacon_config - Configure the beacon queues and interrupts
2134 *
2135 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2136 *
2137 * When operating in station mode we want to receive a BMISS interrupt when we
2138 * stop seeing beacons from the AP we've associated with so we can look for
2139 * another AP to associate with.
2140 *
036cd1ec 2141 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2142 * interrupts to detect TSF updates only.
036cd1ec
BR		 2143 *
2144 * AP mode is missing.
fa1c114f
JS		 2145 */
2146static void
2147ath5k_beacon_config(struct ath5k_softc *sc)
2148{
2149 struct ath5k_hw *ah = sc->ah;
2150
2151 ath5k_hw_set_intr(ah, 0);
2152 sc->bmisscount = 0;
2153
2154 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2155 sc->imask |= AR5K_INT_BMISS;
2156 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2157 /*
036cd1ec
BR		 2158 * In IBSS mode we use a self-linked tx descriptor and let the
2159 * hardware send the beacons automatically. We have to load it
fa1c114f 2160 * only once here.
036cd1ec 2161 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2162 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2163 */
2164 ath5k_beaconq_config(sc);
fa1c114f 2165
036cd1ec
BR		 2166 sc->imask |= AR5K_INT_SWBA;
2167
2168 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2169 ath5k_beacon_send(sc);
2170 }
2171 /* TODO else AP */
2172
2173 ath5k_hw_set_intr(ah, sc->imask);
2174}
2175
2176
2177/********************\
2178* Interrupt handling *
2179\********************/
2180
2181static int
2182ath5k_init(struct ath5k_softc *sc)
2183{
2184 int ret;
2185
2186 mutex_lock(&sc->lock);
2187
2188 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2189
2190 /*
2191 * Stop anything previously setup. This is safe
2192 * no matter this is the first time through or not.
2193 */
2194 ath5k_stop_locked(sc);
2195
2196 /*
2197 * The basic interface to setting the hardware in a good
2198 * state is ``reset''. On return the hardware is known to
2199 * be powered up and with interrupts disabled. This must
2200 * be followed by initialization of the appropriate bits
2201 * and then setup of the interrupt mask.
2202 */
d8ee398d
LR		 2203 sc->curchan = sc->hw->conf.channel;
2204 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f
JS		 2205 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2206 if (ret) {
2207 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2208 goto done;
2209 }
2210 /*
2211 * This is needed only to setup initial state
2212 * but it's best done after a reset.
2213 */
2214 ath5k_hw_set_txpower_limit(sc->ah, 0);
2215
2216 /*
2217 * Setup the hardware after reset: the key cache
2218 * is filled as needed and the receive engine is
2219 * set going. Frame transmit is handled entirely
2220 * in the frame output path; there's nothing to do
2221 * here except setup the interrupt mask.
2222 */
2223 ret = ath5k_rx_start(sc);
2224 if (ret)
2225 goto done;
2226
2227 /*
2228 * Enable interrupts.
2229 */
2230 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2231 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2232 AR5K_INT_MIB;
fa1c114f
JS		 2233
2234 ath5k_hw_set_intr(sc->ah, sc->imask);
2235 /* Set ack to be sent at low bit-rates */
2236 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2237
2238 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2239 msecs_to_jiffies(ath5k_calinterval * 1000)));
2240
2241 ret = 0;
2242done:
2243 mutex_unlock(&sc->lock);
2244 return ret;
2245}
2246
2247static int
2248ath5k_stop_locked(struct ath5k_softc *sc)
2249{
2250 struct ath5k_hw *ah = sc->ah;
2251
2252 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2253 test_bit(ATH_STAT_INVALID, sc->status));
2254
2255 /*
2256 * Shutdown the hardware and driver:
2257 * stop output from above
2258 * disable interrupts
2259 * turn off timers
2260 * turn off the radio
2261 * clear transmit machinery
2262 * clear receive machinery
2263 * drain and release tx queues
2264 * reclaim beacon resources
2265 * power down hardware
2266 *
2267 * Note that some of this work is not possible if the
2268 * hardware is gone (invalid).
2269 */
2270 ieee80211_stop_queues(sc->hw);
2271
2272 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2273 ath5k_led_off(sc);
fa1c114f
JS		 2274 ath5k_hw_set_intr(ah, 0);
2275 }
2276 ath5k_txq_cleanup(sc);
2277 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2278 ath5k_rx_stop(sc);
2279 ath5k_hw_phy_disable(ah);
2280 } else
2281 sc->rxlink = NULL;
2282
2283 return 0;
2284}
2285
2286/*
2287 * Stop the device, grabbing the top-level lock to protect
2288 * against concurrent entry through ath5k_init (which can happen
2289 * if another thread does a system call and the thread doing the
2290 * stop is preempted).
2291 */
2292static int
2293ath5k_stop_hw(struct ath5k_softc *sc)
2294{
2295 int ret;
2296
2297 mutex_lock(&sc->lock);
2298 ret = ath5k_stop_locked(sc);
2299 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2300 /*
2301 * Set the chip in full sleep mode. Note that we are
2302 * careful to do this only when bringing the interface
2303 * completely to a stop. When the chip is in this state
2304 * it must be carefully woken up or references to
2305 * registers in the PCI clock domain may freeze the bus
2306 * (and system). This varies by chip and is mostly an
2307 * issue with newer parts that go to sleep more quickly.
2308 */
2309 if (sc->ah->ah_mac_srev >= 0x78) {
2310 /*
2311 * XXX
2312 * don't put newer MAC revisions > 7.8 to sleep because
2313 * of the above mentioned problems
2314 */
2315 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2316 "not putting device to sleep\n");
2317 } else {
2318 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2319 "putting device to full sleep\n");
2320 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2321 }
2322 }
2323 ath5k_txbuf_free(sc, sc->bbuf);
2324 mutex_unlock(&sc->lock);
2325
2326 del_timer_sync(&sc->calib_tim);
2327
2328 return ret;
2329}
2330
2331static irqreturn_t
2332ath5k_intr(int irq, void *dev_id)
2333{
2334 struct ath5k_softc *sc = dev_id;
2335 struct ath5k_hw *ah = sc->ah;
2336 enum ath5k_int status;
2337 unsigned int counter = 1000;
2338
2339 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2340 !ath5k_hw_is_intr_pending(ah)))
2341 return IRQ_NONE;
2342
2343 do {
2344 /*
2345 * Figure out the reason(s) for the interrupt. Note
2346 * that get_isr returns a pseudo-ISR that may include
2347 * bits we haven't explicitly enabled so we mask the
2348 * value to insure we only process bits we requested.
2349 */
2350 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2351 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2352 status, sc->imask);
2353 status &= sc->imask; /* discard unasked for bits */
2354 if (unlikely(status & AR5K_INT_FATAL)) {
2355 /*
2356 * Fatal errors are unrecoverable.
2357 * Typically these are caused by DMA errors.
2358 */
2359 tasklet_schedule(&sc->restq);
2360 } else if (unlikely(status & AR5K_INT_RXORN)) {
2361 tasklet_schedule(&sc->restq);
2362 } else {
2363 if (status & AR5K_INT_SWBA) {
2364 /*
2365 * Software beacon alert--time to send a beacon.
2366 * Handle beacon transmission directly; deferring
2367 * this is too slow to meet timing constraints
2368 * under load.
036cd1ec
BR		 2369 *
2370 * In IBSS mode we use this interrupt just to
2371 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2372 * transmission time) in order to detect wether
2373 * automatic TSF updates happened.
fa1c114f 2374 */
036cd1ec
BR		 2375 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2376 /* XXX: only if VEOL suppported */
2377 u64 tsf = ath5k_hw_get_tsf64(ah);
2378 sc->nexttbtt += sc->bintval;
2379 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2380 "SWBA nexttbtt: %x hw_tu: %x "
2381 "TSF: %llx\n",
2382 sc->nexttbtt,
2383 TSF_TO_TU(tsf),
2384 (unsigned long long) tsf);
036cd1ec
BR		 2385 } else {
2386 ath5k_beacon_send(sc);
2387 }
fa1c114f
JS		 2388 }
2389 if (status & AR5K_INT_RXEOL) {
2390 /*
2391 * NB: the hardware should re-read the link when
2392 * RXE bit is written, but it doesn't work at
2393 * least on older hardware revs.
2394 */
2395 sc->rxlink = NULL;
2396 }
2397 if (status & AR5K_INT_TXURN) {
2398 /* bump tx trigger level */
2399 ath5k_hw_update_tx_triglevel(ah, true);
2400 }
2401 if (status & AR5K_INT_RX)
2402 tasklet_schedule(&sc->rxtq);
2403 if (status & AR5K_INT_TX)
2404 tasklet_schedule(&sc->txtq);
2405 if (status & AR5K_INT_BMISS) {
2406 }
2407 if (status & AR5K_INT_MIB) {
194828a2
NK		 2408 /*
2409 * These stats are also used for ANI i think
2410 * so how about updating them more often ?
2411 */
2412 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2413 }
2414 }
2415 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2416
2417 if (unlikely(!counter))
2418 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2419
2420 return IRQ_HANDLED;
2421}
2422
2423static void
2424ath5k_tasklet_reset(unsigned long data)
2425{
2426 struct ath5k_softc *sc = (void *)data;
2427
2428 ath5k_reset(sc->hw);
2429}
2430
2431/*
2432 * Periodically recalibrate the PHY to account
2433 * for temperature/environment changes.
2434 */
2435static void
2436ath5k_calibrate(unsigned long data)
2437{
2438 struct ath5k_softc *sc = (void *)data;
2439 struct ath5k_hw *ah = sc->ah;
2440
2441 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2442 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2443 sc->curchan->hw_value);
fa1c114f
JS		 2444
2445 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2446 /*
2447 * Rfgain is out of bounds, reset the chip
2448 * to load new gain values.
2449 */
2450 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2451 ath5k_reset(sc->hw);
2452 }
2453 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2454 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2455 ieee80211_frequency_to_channel(
2456 sc->curchan->center_freq));
fa1c114f
JS		 2457
2458 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2459 msecs_to_jiffies(ath5k_calinterval * 1000)));
2460}
2461
2462
2463
2464/***************\
2465* LED functions *
2466\***************/
2467
2468static void
3a078876 2469ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2470{
3a078876
BC		 2471 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2472 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2473 ath5k_led_off(sc);
fa1c114f
JS		 2474 }
2475}
2476
fa1c114f 2477static void
3a078876 2478ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2479{
3a078876
BC		 2480 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2481 return;
fa1c114f 2482 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2483}
2484
2485static void
3a078876 2486ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2487{
3a078876 2488 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2489 return;
3a078876
BC		 2490 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2491}
2492
2493static void
2494ath5k_led_brightness_set(struct led_classdev *led_dev,
2495 enum led_brightness brightness)
2496{
2497 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2498 led_dev);
2499
2500 if (brightness == LED_OFF)
2501 ath5k_led_off(led->sc);
2502 else
2503 ath5k_led_on(led->sc);
2504}
2505
2506static int
2507ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2508 const char *name, char *trigger)
2509{
2510 int err;
2511
2512 led->sc = sc;
2513 strncpy(led->name, name, sizeof(led->name));
2514 led->led_dev.name = led->name;
2515 led->led_dev.default_trigger = trigger;
2516 led->led_dev.brightness_set = ath5k_led_brightness_set;
2517
2518 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2519 if (err)
2520 {
2521 ATH5K_WARN(sc, "could not register LED %s\n", name);
2522 led->sc = NULL;
fa1c114f 2523 }
3a078876 2524 return err;
fa1c114f
JS		 2525}
2526
3a078876
BC		 2527static void
2528ath5k_unregister_led(struct ath5k_led *led)
2529{
2530 if (!led->sc)
2531 return;
2532 led_classdev_unregister(&led->led_dev);
2533 ath5k_led_off(led->sc);
2534 led->sc = NULL;
2535}
2536
2537static void
2538ath5k_unregister_leds(struct ath5k_softc *sc)
2539{
2540 ath5k_unregister_led(&sc->rx_led);
2541 ath5k_unregister_led(&sc->tx_led);
2542}
2543
2544
2545static int
2546ath5k_init_leds(struct ath5k_softc *sc)
2547{
2548 int ret = 0;
2549 struct ieee80211_hw *hw = sc->hw;
2550 struct pci_dev *pdev = sc->pdev;
2551 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2552
2553 sc->led_on = 0; /* active low */
fa1c114f 2554
3a078876
BC		 2555 /*
2556 * Auto-enable soft led processing for IBM cards and for
2557 * 5211 minipci cards.
2558 */
2559 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2560 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2561 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2562 sc->led_pin = 0;
2563 }
2564 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2565 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2566 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2567 sc->led_pin = 1;
2568 }
2569 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2570 goto out;
2571
2572 ath5k_led_enable(sc);
2573
2574 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2575 ret = ath5k_register_led(sc, &sc->rx_led, name,
2576 ieee80211_get_rx_led_name(hw));
2577 if (ret)
2578 goto out;
2579
2580 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2581 ret = ath5k_register_led(sc, &sc->tx_led, name,
2582 ieee80211_get_tx_led_name(hw));
2583out:
2584 return ret;
2585}
fa1c114f
JS		 2586
2587
2588/********************\
2589* Mac80211 functions *
2590\********************/
2591
2592static int
e039fa4a 2593ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2594{
2595 struct ath5k_softc *sc = hw->priv;
2596 struct ath5k_buf *bf;
2597 unsigned long flags;
2598 int hdrlen;
2599 int pad;
2600
2601 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2602
2603 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2604 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2605
2606 /*
2607 * the hardware expects the header padded to 4 byte boundaries
2608 * if this is not the case we add the padding after the header
2609 */
2610 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2611 if (hdrlen & 3) {
2612 pad = hdrlen % 4;
2613 if (skb_headroom(skb) < pad) {
2614 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2615 " headroom to pad %d\n", hdrlen, pad);
2616 return -1;
2617 }
2618 skb_push(skb, pad);
2619 memmove(skb->data, skb->data+pad, hdrlen);
2620 }
2621
fa1c114f
JS		 2622 spin_lock_irqsave(&sc->txbuflock, flags);
2623 if (list_empty(&sc->txbuf)) {
2624 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2625 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2626 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2627 return -1;
2628 }
2629 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2630 list_del(&bf->list);
2631 sc->txbuf_len--;
2632 if (list_empty(&sc->txbuf))
2633 ieee80211_stop_queues(hw);
2634 spin_unlock_irqrestore(&sc->txbuflock, flags);
2635
2636 bf->skb = skb;
2637
e039fa4a 2638 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2639 bf->skb = NULL;
2640 spin_lock_irqsave(&sc->txbuflock, flags);
2641 list_add_tail(&bf->list, &sc->txbuf);
2642 sc->txbuf_len++;
2643 spin_unlock_irqrestore(&sc->txbuflock, flags);
2644 dev_kfree_skb_any(skb);
2645 return 0;
2646 }
2647
2648 return 0;
2649}
2650
2651static int
2652ath5k_reset(struct ieee80211_hw *hw)
2653{
2654 struct ath5k_softc *sc = hw->priv;
2655 struct ath5k_hw *ah = sc->ah;
2656 int ret;
2657
2658 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f
JS		 2659
2660 ath5k_hw_set_intr(ah, 0);
2661 ath5k_txq_cleanup(sc);
2662 ath5k_rx_stop(sc);
2663
2664 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2665 if (unlikely(ret)) {
2666 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2667 goto err;
2668 }
2669 ath5k_hw_set_txpower_limit(sc->ah, 0);
2670
2671 ret = ath5k_rx_start(sc);
2672 if (unlikely(ret)) {
2673 ATH5K_ERR(sc, "can't start recv logic\n");
2674 goto err;
2675 }
2676 /*
2677 * We may be doing a reset in response to an ioctl
2678 * that changes the channel so update any state that
2679 * might change as a result.
2680 *
2681 * XXX needed?
2682 */
2683/* ath5k_chan_change(sc, c); */
2684 ath5k_beacon_config(sc);
2685 /* intrs are started by ath5k_beacon_config */
2686
2687 ieee80211_wake_queues(hw);
2688
2689 return 0;
2690err:
2691 return ret;
2692}
2693
2694static int ath5k_start(struct ieee80211_hw *hw)
2695{
2696 return ath5k_init(hw->priv);
2697}
2698
2699static void ath5k_stop(struct ieee80211_hw *hw)
2700{
2701 ath5k_stop_hw(hw->priv);
2702}
2703
2704static int ath5k_add_interface(struct ieee80211_hw *hw,
2705 struct ieee80211_if_init_conf *conf)
2706{
2707 struct ath5k_softc *sc = hw->priv;
2708 int ret;
2709
2710 mutex_lock(&sc->lock);
32bfd35d 2711 if (sc->vif) {
fa1c114f
JS		 2712 ret = 0;
2713 goto end;
2714 }
2715
32bfd35d 2716 sc->vif = conf->vif;
fa1c114f
JS		 2717
2718 switch (conf->type) {
2719 case IEEE80211_IF_TYPE_STA:
2720 case IEEE80211_IF_TYPE_IBSS:
2721 case IEEE80211_IF_TYPE_MNTR:
2722 sc->opmode = conf->type;
2723 break;
2724 default:
2725 ret = -EOPNOTSUPP;
2726 goto end;
2727 }
2728 ret = 0;
2729end:
2730 mutex_unlock(&sc->lock);
2731 return ret;
2732}
2733
2734static void
2735ath5k_remove_interface(struct ieee80211_hw *hw,
2736 struct ieee80211_if_init_conf *conf)
2737{
2738 struct ath5k_softc *sc = hw->priv;
2739
2740 mutex_lock(&sc->lock);
32bfd35d 2741 if (sc->vif != conf->vif)
fa1c114f
JS		 2742 goto end;
2743
32bfd35d 2744 sc->vif = NULL;
fa1c114f
JS		 2745end:
2746 mutex_unlock(&sc->lock);
2747}
2748
d8ee398d
LR		 2749/*
2750 * TODO: Phy disable/diversity etc
2751 */
fa1c114f
JS		 2752static int
2753ath5k_config(struct ieee80211_hw *hw,
2754 struct ieee80211_conf *conf)
2755{
2756 struct ath5k_softc *sc = hw->priv;
2757
e535c1ac 2758 sc->bintval = conf->beacon_int;
d8ee398d 2759 sc->power_level = conf->power_level;
fa1c114f 2760
d8ee398d 2761 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2762}
2763
2764static int
32bfd35d 2765ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2766 struct ieee80211_if_conf *conf)
2767{
2768 struct ath5k_softc *sc = hw->priv;
2769 struct ath5k_hw *ah = sc->ah;
2770 int ret;
2771
2772 /* Set to a reasonable value. Note that this will
2773 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2774 sc->bintval = 1000;
fa1c114f 2775 mutex_lock(&sc->lock);
32bfd35d 2776 if (sc->vif != vif) {
fa1c114f
JS		 2777 ret = -EIO;
2778 goto unlock;
2779 }
2780 if (conf->bssid) {
2781 /* Cache for later use during resets */
2782 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2783 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2784 * a clean way of letting us retrieve this yet. */
2785 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2786 }
9d139c81
JB		 2787
2788 if (conf->changed & IEEE80211_IFCC_BEACON &&
2789 vif->type == IEEE80211_IF_TYPE_IBSS) {
2790 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2791 if (!beacon) {
2792 ret = -ENOMEM;
2793 goto unlock;
2794 }
2795 /* call old handler for now */
2796 ath5k_beacon_update(hw, beacon);
2797 }
2798
fa1c114f
JS		 2799 mutex_unlock(&sc->lock);
2800
2801 return ath5k_reset(hw);
2802unlock:
2803 mutex_unlock(&sc->lock);
2804 return ret;
2805}
2806
2807#define SUPPORTED_FIF_FLAGS \
2808 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2809 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2810 FIF_BCN_PRBRESP_PROMISC
2811/*
2812 * o always accept unicast, broadcast, and multicast traffic
2813 * o multicast traffic for all BSSIDs will be enabled if mac80211
2814 * says it should be
2815 * o maintain current state of phy ofdm or phy cck error reception.
2816 * If the hardware detects any of these type of errors then
2817 * ath5k_hw_get_rx_filter() will pass to us the respective
2818 * hardware filters to be able to receive these type of frames.
2819 * o probe request frames are accepted only when operating in
2820 * hostap, adhoc, or monitor modes
2821 * o enable promiscuous mode according to the interface state
2822 * o accept beacons:
2823 * - when operating in adhoc mode so the 802.11 layer creates
2824 * node table entries for peers,
2825 * - when operating in station mode for collecting rssi data when
2826 * the station is otherwise quiet, or
2827 * - when scanning
2828 */
2829static void ath5k_configure_filter(struct ieee80211_hw *hw,
2830 unsigned int changed_flags,
2831 unsigned int *new_flags,
2832 int mc_count, struct dev_mc_list *mclist)
2833{
2834 struct ath5k_softc *sc = hw->priv;
2835 struct ath5k_hw *ah = sc->ah;
2836 u32 mfilt[2], val, rfilt;
2837 u8 pos;
2838 int i;
2839
2840 mfilt[0] = 0;
2841 mfilt[1] = 0;
2842
2843 /* Only deal with supported flags */
2844 changed_flags &= SUPPORTED_FIF_FLAGS;
2845 *new_flags &= SUPPORTED_FIF_FLAGS;
2846
2847 /* If HW detects any phy or radar errors, leave those filters on.
2848 * Also, always enable Unicast, Broadcasts and Multicast
2849 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2850 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2851 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2852 AR5K_RX_FILTER_MCAST);
2853
2854 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2855 if (*new_flags & FIF_PROMISC_IN_BSS) {
2856 rfilt |= AR5K_RX_FILTER_PROM;
2857 __set_bit(ATH_STAT_PROMISC, sc->status);
2858 }
2859 else
2860 __clear_bit(ATH_STAT_PROMISC, sc->status);
2861 }
2862
2863 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2864 if (*new_flags & FIF_ALLMULTI) {
2865 mfilt[0] = ~0;
2866 mfilt[1] = ~0;
2867 } else {
2868 for (i = 0; i < mc_count; i++) {
2869 if (!mclist)
2870 break;
2871 /* calculate XOR of eight 6-bit values */
533dd1b0 2872 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2873 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2874 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2875 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2876 pos &= 0x3f;
2877 mfilt[pos / 32] |= (1 << (pos % 32));
2878 /* XXX: we might be able to just do this instead,
2879 * but not sure, needs testing, if we do use this we'd
2880 * neet to inform below to not reset the mcast */
2881 /* ath5k_hw_set_mcast_filterindex(ah,
2882 * mclist->dmi_addr[5]); */
2883 mclist = mclist->next;
2884 }
2885 }
2886
2887 /* This is the best we can do */
2888 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2889 rfilt |= AR5K_RX_FILTER_PHYERR;
2890
2891 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2892 * and probes for any BSSID, this needs testing */
2893 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2894 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2895
2896 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2897 * set we should only pass on control frames for this
2898 * station. This needs testing. I believe right now this
2899 * enables *all* control frames, which is OK.. but
2900 * but we should see if we can improve on granularity */
2901 if (*new_flags & FIF_CONTROL)
2902 rfilt |= AR5K_RX_FILTER_CONTROL;
2903
2904 /* Additional settings per mode -- this is per ath5k */
2905
2906 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2907
2908 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2909 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2910 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2911 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2912 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2913 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2914 test_bit(ATH_STAT_PROMISC, sc->status))
2915 rfilt |= AR5K_RX_FILTER_PROM;
2916 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2917 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2918 rfilt |= AR5K_RX_FILTER_BEACON;
2919 }
2920
2921 /* Set filters */
2922 ath5k_hw_set_rx_filter(ah,rfilt);
2923
2924 /* Set multicast bits */
2925 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2926 /* Set the cached hw filter flags, this will alter actually
2927 * be set in HW */
2928 sc->filter_flags = rfilt;
2929}
2930
2931static int
2932ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2933 const u8 *local_addr, const u8 *addr,
2934 struct ieee80211_key_conf *key)
2935{
2936 struct ath5k_softc *sc = hw->priv;
2937 int ret = 0;
2938
2939 switch(key->alg) {
2940 case ALG_WEP:
6844e63a
LR		 2941 /* XXX: fix hardware encryption, its not working. For now
2942 * allow software encryption */
2943 /* break; */
fa1c114f
JS		 2944 case ALG_TKIP:
2945 case ALG_CCMP:
2946 return -EOPNOTSUPP;
2947 default:
2948 WARN_ON(1);
2949 return -EINVAL;
2950 }
2951
2952 mutex_lock(&sc->lock);
2953
2954 switch (cmd) {
2955 case SET_KEY:
2956 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2957 if (ret) {
2958 ATH5K_ERR(sc, "can't set the key\n");
2959 goto unlock;
2960 }
2961 __set_bit(key->keyidx, sc->keymap);
2962 key->hw_key_idx = key->keyidx;
2963 break;
2964 case DISABLE_KEY:
2965 ath5k_hw_reset_key(sc->ah, key->keyidx);
2966 __clear_bit(key->keyidx, sc->keymap);
2967 break;
2968 default:
2969 ret = -EINVAL;
2970 goto unlock;
2971 }
2972
2973unlock:
2974 mutex_unlock(&sc->lock);
2975 return ret;
2976}
2977
2978static int
2979ath5k_get_stats(struct ieee80211_hw *hw,
2980 struct ieee80211_low_level_stats *stats)
2981{
2982 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2983 struct ath5k_hw *ah = sc->ah;
2984
2985 /* Force update */
2986 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2987
2988 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2989
2990 return 0;
2991}
2992
2993static int
2994ath5k_get_tx_stats(struct ieee80211_hw *hw,
2995 struct ieee80211_tx_queue_stats *stats)
2996{
2997 struct ath5k_softc *sc = hw->priv;
2998
2999 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3000
3001 return 0;
3002}
3003
3004static u64
3005ath5k_get_tsf(struct ieee80211_hw *hw)
3006{
3007 struct ath5k_softc *sc = hw->priv;
3008
3009 return ath5k_hw_get_tsf64(sc->ah);
3010}
3011
3012static void
3013ath5k_reset_tsf(struct ieee80211_hw *hw)
3014{
3015 struct ath5k_softc *sc = hw->priv;
3016
9804b98d
BR		 3017 /*
3018 * in IBSS mode we need to update the beacon timers too.
3019 * this will also reset the TSF if we call it with 0
3020 */
3021 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3022 ath5k_beacon_update_timers(sc, 0);
3023 else
3024 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3025}
3026
3027static int
e039fa4a 3028ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3029{
3030 struct ath5k_softc *sc = hw->priv;
3031 int ret;
3032
3033 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3034
3035 mutex_lock(&sc->lock);
3036
3037 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3038 ret = -EIO;
3039 goto end;
3040 }
3041
3042 ath5k_txbuf_free(sc, sc->bbuf);
3043 sc->bbuf->skb = skb;
e039fa4a 3044 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3045 if (ret)
3046 sc->bbuf->skb = NULL;
3047 else
3048 ath5k_beacon_config(sc);
3049
3050end:
3051 mutex_unlock(&sc->lock);
3052 return ret;
3053}
3054
kernel source for telekom puls (alcatel/mediatek)