Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
313eb87f | 22 | u8 ath9k_parse_mpdudensity(u8 mpdudensity) |
ff37e337 S |
23 | { |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
63 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
64 | pending = true; | |
69081624 VT |
65 | |
66 | spin_unlock_bh(&txq->axq_lock); | |
67 | return pending; | |
68 | } | |
69 | ||
6d79cb4c | 70 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
71 | { |
72 | unsigned long flags; | |
73 | bool ret; | |
74 | ||
9ecdef4b LR |
75 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
76 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
77 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
78 | |
79 | return ret; | |
80 | } | |
81 | ||
a91d75ae LR |
82 | void ath9k_ps_wakeup(struct ath_softc *sc) |
83 | { | |
898c914a | 84 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 85 | unsigned long flags; |
fbb078fc | 86 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
87 | |
88 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
89 | if (++sc->ps_usecount != 1) | |
90 | goto unlock; | |
91 | ||
fbb078fc | 92 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 93 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 94 | |
898c914a FF |
95 | /* |
96 | * While the hardware is asleep, the cycle counters contain no | |
97 | * useful data. Better clear them now so that they don't mess up | |
98 | * survey data results. | |
99 | */ | |
fbb078fc FF |
100 | if (power_mode != ATH9K_PM_AWAKE) { |
101 | spin_lock(&common->cc_lock); | |
102 | ath_hw_cycle_counters_update(common); | |
103 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
c9ae6ab4 | 104 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); |
fbb078fc FF |
105 | spin_unlock(&common->cc_lock); |
106 | } | |
898c914a | 107 | |
a91d75ae LR |
108 | unlock: |
109 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
110 | } | |
111 | ||
112 | void ath9k_ps_restore(struct ath_softc *sc) | |
113 | { | |
898c914a | 114 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 115 | enum ath9k_power_mode mode; |
a91d75ae | 116 | unsigned long flags; |
ad128860 | 117 | bool reset; |
a91d75ae LR |
118 | |
119 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
120 | if (--sc->ps_usecount != 0) | |
121 | goto unlock; | |
122 | ||
ad128860 SM |
123 | if (sc->ps_idle) { |
124 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
125 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
c6c539f0 | 126 | mode = ATH9K_PM_FULL_SLEEP; |
ad128860 SM |
127 | } else if (sc->ps_enabled && |
128 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
129 | PS_WAIT_FOR_CAB | | |
130 | PS_WAIT_FOR_PSPOLL_DATA | | |
131 | PS_WAIT_FOR_TX_ACK))) { | |
c6c539f0 | 132 | mode = ATH9K_PM_NETWORK_SLEEP; |
08d4df41 RM |
133 | if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) |
134 | ath9k_btcoex_stop_gen_timer(sc); | |
ad128860 | 135 | } else { |
c6c539f0 | 136 | goto unlock; |
ad128860 | 137 | } |
c6c539f0 FF |
138 | |
139 | spin_lock(&common->cc_lock); | |
140 | ath_hw_cycle_counters_update(common); | |
141 | spin_unlock(&common->cc_lock); | |
142 | ||
1a8f0d39 | 143 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
144 | |
145 | unlock: | |
146 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
147 | } | |
148 | ||
9adcf440 | 149 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 150 | { |
5ee08656 FF |
151 | cancel_work_sync(&sc->paprd_work); |
152 | cancel_work_sync(&sc->hw_check_work); | |
153 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 154 | cancel_delayed_work_sync(&sc->hw_pll_work); |
fad29cd2 | 155 | |
bf52592f | 156 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
fad29cd2 SM |
157 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
158 | cancel_work_sync(&sc->mci_work); | |
bf52592f | 159 | #endif |
9adcf440 | 160 | } |
5ee08656 | 161 | |
9adcf440 FF |
162 | static void ath_cancel_work(struct ath_softc *sc) |
163 | { | |
164 | __ath_cancel_work(sc); | |
165 | cancel_work_sync(&sc->hw_reset_work); | |
166 | } | |
3cbb5dd7 | 167 | |
af68abad SM |
168 | static void ath_restart_work(struct ath_softc *sc) |
169 | { | |
170 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
171 | ||
172 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); | |
173 | ||
c12b6021 GJ |
174 | if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || |
175 | AR_SREV_9550(sc->sc_ah)) | |
af68abad SM |
176 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, |
177 | msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); | |
178 | ||
179 | ath_start_rx_poll(sc, 3); | |
180 | ||
181 | if (!common->disable_ani) | |
182 | ath_start_ani(common); | |
183 | } | |
184 | ||
9adcf440 FF |
185 | static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) |
186 | { | |
187 | struct ath_hw *ah = sc->sc_ah; | |
188 | struct ath_common *common = ath9k_hw_common(ah); | |
ceea2a51 | 189 | bool ret = true; |
6a6733f2 | 190 | |
9adcf440 | 191 | ieee80211_stop_queues(sc->hw); |
5e848f78 | 192 | |
9adcf440 FF |
193 | sc->hw_busy_count = 0; |
194 | del_timer_sync(&common->ani.timer); | |
01e18918 | 195 | del_timer_sync(&sc->rx_poll_timer); |
ff37e337 | 196 | |
9adcf440 FF |
197 | ath9k_debug_samp_bb_mac(sc); |
198 | ath9k_hw_disable_interrupts(ah); | |
8b3f4616 | 199 | |
9adcf440 FF |
200 | if (!ath_stoprecv(sc)) |
201 | ret = false; | |
c0d7c7af | 202 | |
ceea2a51 FF |
203 | if (!ath_drain_all_txq(sc, retry_tx)) |
204 | ret = false; | |
205 | ||
9adcf440 FF |
206 | if (!flush) { |
207 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
3483288c FF |
208 | ath_rx_tasklet(sc, 1, true); |
209 | ath_rx_tasklet(sc, 1, false); | |
9adcf440 FF |
210 | } else { |
211 | ath_flushrecv(sc); | |
212 | } | |
20bd2a09 | 213 | |
9adcf440 FF |
214 | return ret; |
215 | } | |
ff37e337 | 216 | |
9adcf440 FF |
217 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
218 | { | |
219 | struct ath_hw *ah = sc->sc_ah; | |
220 | struct ath_common *common = ath9k_hw_common(ah); | |
196fb860 | 221 | unsigned long flags; |
c0d7c7af | 222 | |
c0d7c7af | 223 | if (ath_startrecv(sc) != 0) { |
3800276a | 224 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 225 | return false; |
c0d7c7af LR |
226 | } |
227 | ||
5048e8c3 RM |
228 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
229 | sc->config.txpowlimit, &sc->curtxpow); | |
b74713d0 SM |
230 | |
231 | clear_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
72d874c6 | 232 | ath9k_hw_set_interrupts(ah); |
b037b693 | 233 | ath9k_hw_enable_interrupts(ah); |
3989279c | 234 | |
4cb54fa3 | 235 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { |
196fb860 SM |
236 | if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) |
237 | goto work; | |
238 | ||
ef4ad633 | 239 | ath9k_set_beacon(sc); |
196fb860 SM |
240 | |
241 | if (ah->opmode == NL80211_IFTYPE_STATION && | |
242 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
243 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
244 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
245 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
246 | } | |
247 | work: | |
af68abad | 248 | ath_restart_work(sc); |
5ee08656 FF |
249 | } |
250 | ||
8da07830 SM |
251 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) |
252 | ath_ant_comb_update(sc); | |
43c35284 | 253 | |
9adcf440 FF |
254 | ieee80211_wake_queues(sc->hw); |
255 | ||
256 | return true; | |
257 | } | |
258 | ||
259 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | |
260 | bool retry_tx) | |
261 | { | |
262 | struct ath_hw *ah = sc->sc_ah; | |
263 | struct ath_common *common = ath9k_hw_common(ah); | |
264 | struct ath9k_hw_cal_data *caldata = NULL; | |
265 | bool fastcc = true; | |
266 | bool flush = false; | |
267 | int r; | |
268 | ||
269 | __ath_cancel_work(sc); | |
270 | ||
271 | spin_lock_bh(&sc->sc_pcu_lock); | |
92460412 | 272 | |
4cb54fa3 | 273 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { |
9adcf440 FF |
274 | fastcc = false; |
275 | caldata = &sc->caldata; | |
276 | } | |
277 | ||
278 | if (!hchan) { | |
279 | fastcc = false; | |
280 | flush = true; | |
281 | hchan = ah->curchan; | |
282 | } | |
283 | ||
9adcf440 FF |
284 | if (!ath_prepare_reset(sc, retry_tx, flush)) |
285 | fastcc = false; | |
286 | ||
d2182b69 | 287 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 288 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
289 | |
290 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
291 | if (r) { | |
292 | ath_err(common, | |
293 | "Unable to reset channel, reset status %d\n", r); | |
294 | goto out; | |
295 | } | |
296 | ||
297 | if (!ath_complete_reset(sc, true)) | |
298 | r = -EIO; | |
299 | ||
300 | out: | |
6a6733f2 | 301 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 FF |
302 | return r; |
303 | } | |
304 | ||
305 | ||
306 | /* | |
307 | * Set/change channels. If the channel is really being changed, it's done | |
308 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
309 | * DMA, then restart stuff. | |
310 | */ | |
311 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
312 | struct ath9k_channel *hchan) | |
313 | { | |
314 | int r; | |
315 | ||
781b14a3 | 316 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
9adcf440 FF |
317 | return -EIO; |
318 | ||
9adcf440 | 319 | r = ath_reset_internal(sc, hchan, false); |
6a6733f2 | 320 | |
3989279c | 321 | return r; |
ff37e337 S |
322 | } |
323 | ||
7e1e3864 BG |
324 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
325 | struct ieee80211_vif *vif) | |
ff37e337 S |
326 | { |
327 | struct ath_node *an; | |
313eb87f | 328 | u8 density; |
ff37e337 S |
329 | an = (struct ath_node *)sta->drv_priv; |
330 | ||
7f010c93 BG |
331 | #ifdef CONFIG_ATH9K_DEBUGFS |
332 | spin_lock(&sc->nodes_lock); | |
333 | list_add(&an->list, &sc->nodes); | |
334 | spin_unlock(&sc->nodes_lock); | |
156369fa | 335 | #endif |
7f010c93 | 336 | an->sta = sta; |
7e1e3864 | 337 | an->vif = vif; |
3d4e20f2 | 338 | |
a4d6367f | 339 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
ff37e337 | 340 | ath_tx_node_init(sc, an); |
9e98ac65 | 341 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc | 342 | sta->ht_cap.ampdu_factor); |
313eb87f SE |
343 | density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); |
344 | an->mpdudensity = density; | |
87792efc | 345 | } |
ff37e337 S |
346 | } |
347 | ||
348 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
349 | { | |
350 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
351 | ||
7f010c93 BG |
352 | #ifdef CONFIG_ATH9K_DEBUGFS |
353 | spin_lock(&sc->nodes_lock); | |
354 | list_del(&an->list); | |
355 | spin_unlock(&sc->nodes_lock); | |
356 | an->sta = NULL; | |
357 | #endif | |
358 | ||
a4d6367f | 359 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
ff37e337 S |
360 | ath_tx_node_cleanup(sc, an); |
361 | } | |
362 | ||
55624204 | 363 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
364 | { |
365 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 366 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 367 | struct ath_common *common = ath9k_hw_common(ah); |
07c15a3f | 368 | unsigned long flags; |
17d7904d | 369 | u32 status = sc->intrstatus; |
b5c80475 | 370 | u32 rxmask; |
ff37e337 | 371 | |
e3927007 FF |
372 | ath9k_ps_wakeup(sc); |
373 | spin_lock(&sc->sc_pcu_lock); | |
374 | ||
a4d86d95 RM |
375 | if ((status & ATH9K_INT_FATAL) || |
376 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
030d6294 FF |
377 | #ifdef CONFIG_ATH9K_DEBUGFS |
378 | enum ath_reset_type type; | |
379 | ||
380 | if (status & ATH9K_INT_FATAL) | |
381 | type = RESET_TYPE_FATAL_INT; | |
382 | else | |
383 | type = RESET_TYPE_BB_WATCHDOG; | |
384 | ||
385 | RESET_STAT_INC(sc, type); | |
386 | #endif | |
b74713d0 | 387 | set_bit(SC_OP_HW_RESET, &sc->sc_flags); |
236de514 | 388 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
e3927007 | 389 | goto out; |
063d8be3 | 390 | } |
ff37e337 | 391 | |
07c15a3f | 392 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
4105f807 RM |
393 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
394 | /* | |
395 | * TSF sync does not look correct; remain awake to sync with | |
396 | * the next Beacon. | |
397 | */ | |
d2182b69 | 398 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 399 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 | 400 | } |
07c15a3f | 401 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
4105f807 | 402 | |
b5c80475 FF |
403 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
404 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
405 | ATH9K_INT_RXORN); | |
406 | else | |
407 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
408 | ||
409 | if (status & rxmask) { | |
b5c80475 FF |
410 | /* Check for high priority Rx first */ |
411 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
412 | (status & ATH9K_INT_RXHP)) | |
413 | ath_rx_tasklet(sc, 0, true); | |
414 | ||
415 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
416 | } |
417 | ||
e5003249 VT |
418 | if (status & ATH9K_INT_TX) { |
419 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
420 | ath_tx_edma_tasklet(sc); | |
421 | else | |
422 | ath_tx_tasklet(sc); | |
423 | } | |
063d8be3 | 424 | |
56ca0dba | 425 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 426 | |
e3927007 | 427 | out: |
ff37e337 | 428 | /* re-enable hardware interrupt */ |
4df3071e | 429 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 430 | |
52671e43 | 431 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 432 | ath9k_ps_restore(sc); |
ff37e337 S |
433 | } |
434 | ||
6baff7f9 | 435 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 436 | { |
063d8be3 S |
437 | #define SCHED_INTR ( \ |
438 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 439 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
440 | ATH9K_INT_RXORN | \ |
441 | ATH9K_INT_RXEOL | \ | |
442 | ATH9K_INT_RX | \ | |
b5c80475 FF |
443 | ATH9K_INT_RXLP | \ |
444 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
445 | ATH9K_INT_TX | \ |
446 | ATH9K_INT_BMISS | \ | |
447 | ATH9K_INT_CST | \ | |
ebb8e1d7 | 448 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
449 | ATH9K_INT_GENTIMER | \ |
450 | ATH9K_INT_MCI) | |
063d8be3 | 451 | |
ff37e337 | 452 | struct ath_softc *sc = dev; |
cbe61d8a | 453 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 454 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
455 | enum ath9k_int status; |
456 | bool sched = false; | |
457 | ||
063d8be3 S |
458 | /* |
459 | * The hardware is not ready/present, don't | |
460 | * touch anything. Note this can happen early | |
461 | * on if the IRQ is shared. | |
462 | */ | |
781b14a3 | 463 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
063d8be3 | 464 | return IRQ_NONE; |
ff37e337 | 465 | |
063d8be3 S |
466 | /* shared irq, not for us */ |
467 | ||
153e080d | 468 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 469 | return IRQ_NONE; |
063d8be3 | 470 | |
b74713d0 SM |
471 | if(test_bit(SC_OP_HW_RESET, &sc->sc_flags)) |
472 | return IRQ_HANDLED; | |
473 | ||
063d8be3 S |
474 | /* |
475 | * Figure out the reason(s) for the interrupt. Note | |
476 | * that the hal returns a pseudo-ISR that may include | |
477 | * bits we haven't explicitly enabled so we mask the | |
478 | * value to insure we only process bits we requested. | |
479 | */ | |
480 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 481 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 482 | |
063d8be3 S |
483 | /* |
484 | * If there are no status bits set, then this interrupt was not | |
485 | * for me (should have been caught above). | |
486 | */ | |
153e080d | 487 | if (!status) |
063d8be3 | 488 | return IRQ_NONE; |
ff37e337 | 489 | |
063d8be3 S |
490 | /* Cache the status */ |
491 | sc->intrstatus = status; | |
492 | ||
493 | if (status & SCHED_INTR) | |
494 | sched = true; | |
495 | ||
b11e640a MSS |
496 | #ifdef CONFIG_PM_SLEEP |
497 | if (status & ATH9K_INT_BMISS) { | |
498 | if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { | |
499 | ath_dbg(common, ANY, "during WoW we got a BMISS\n"); | |
500 | atomic_inc(&sc->wow_got_bmiss_intr); | |
501 | atomic_dec(&sc->wow_sleep_proc_intr); | |
502 | } | |
503 | ath_dbg(common, INTERRUPT, "beacon miss interrupt\n"); | |
504 | } | |
505 | #endif | |
506 | ||
063d8be3 S |
507 | /* |
508 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
509 | * chip immediately. | |
510 | */ | |
b5c80475 FF |
511 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
512 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
513 | goto chip_reset; |
514 | ||
08578b8f LR |
515 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
516 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
517 | |
518 | spin_lock(&common->cc_lock); | |
519 | ath_hw_cycle_counters_update(common); | |
08578b8f | 520 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
521 | spin_unlock(&common->cc_lock); |
522 | ||
08578b8f LR |
523 | goto chip_reset; |
524 | } | |
525 | ||
063d8be3 S |
526 | if (status & ATH9K_INT_SWBA) |
527 | tasklet_schedule(&sc->bcon_tasklet); | |
528 | ||
529 | if (status & ATH9K_INT_TXURN) | |
530 | ath9k_hw_updatetxtriglevel(ah, true); | |
531 | ||
0682c9b5 RM |
532 | if (status & ATH9K_INT_RXEOL) { |
533 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 534 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
535 | } |
536 | ||
153e080d VT |
537 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
538 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
539 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
540 | goto chip_reset; | |
063d8be3 S |
541 | /* Clear RxAbort bit so that we can |
542 | * receive frames */ | |
9ecdef4b | 543 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
07c15a3f | 544 | spin_lock(&sc->sc_pm_lock); |
153e080d | 545 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 546 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
07c15a3f | 547 | spin_unlock(&sc->sc_pm_lock); |
ff37e337 | 548 | } |
063d8be3 S |
549 | |
550 | chip_reset: | |
ff37e337 | 551 | |
817e11de S |
552 | ath_debug_stat_interrupt(sc, status); |
553 | ||
ff37e337 | 554 | if (sched) { |
4df3071e FF |
555 | /* turn off every interrupt */ |
556 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
557 | tasklet_schedule(&sc->intr_tq); |
558 | } | |
559 | ||
560 | return IRQ_HANDLED; | |
063d8be3 S |
561 | |
562 | #undef SCHED_INTR | |
ff37e337 S |
563 | } |
564 | ||
236de514 | 565 | static int ath_reset(struct ath_softc *sc, bool retry_tx) |
ff37e337 | 566 | { |
ae8d2858 | 567 | int r; |
ff37e337 | 568 | |
783cd01e | 569 | ath9k_ps_wakeup(sc); |
6a6733f2 | 570 | |
9adcf440 | 571 | r = ath_reset_internal(sc, NULL, retry_tx); |
ff37e337 S |
572 | |
573 | if (retry_tx) { | |
574 | int i; | |
575 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
576 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
577 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
578 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
579 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
580 | } |
581 | } | |
582 | } | |
583 | ||
783cd01e | 584 | ath9k_ps_restore(sc); |
2ab81d4a | 585 | |
ae8d2858 | 586 | return r; |
ff37e337 S |
587 | } |
588 | ||
236de514 FF |
589 | void ath_reset_work(struct work_struct *work) |
590 | { | |
591 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
592 | ||
236de514 | 593 | ath_reset(sc, true); |
236de514 FF |
594 | } |
595 | ||
ff37e337 S |
596 | /**********************/ |
597 | /* mac80211 callbacks */ | |
598 | /**********************/ | |
599 | ||
8feceb67 | 600 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 601 | { |
9ac58615 | 602 | struct ath_softc *sc = hw->priv; |
af03abec | 603 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 604 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 605 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 606 | struct ath9k_channel *init_channel; |
82880a7c | 607 | int r; |
f078f209 | 608 | |
d2182b69 | 609 | ath_dbg(common, CONFIG, |
226afe68 JP |
610 | "Starting driver with initial channel: %d MHz\n", |
611 | curchan->center_freq); | |
f078f209 | 612 | |
f62d816f | 613 | ath9k_ps_wakeup(sc); |
141b38b6 S |
614 | mutex_lock(&sc->mutex); |
615 | ||
c344c9cb | 616 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
617 | |
618 | /* Reset SERDES registers */ | |
84c87dc8 | 619 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
620 | |
621 | /* | |
622 | * The basic interface to setting the hardware in a good | |
623 | * state is ``reset''. On return the hardware is known to | |
624 | * be powered up and with interrupts disabled. This must | |
625 | * be followed by initialization of the appropriate bits | |
626 | * and then setup of the interrupt mask. | |
627 | */ | |
4bdd1e97 | 628 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
629 | |
630 | atomic_set(&ah->intr_ref_cnt, -1); | |
631 | ||
20bd2a09 | 632 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 633 | if (r) { |
3800276a JP |
634 | ath_err(common, |
635 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
636 | r, curchan->center_freq); | |
4bdd1e97 | 637 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 638 | goto mutex_unlock; |
ff37e337 | 639 | } |
ff37e337 | 640 | |
ff37e337 | 641 | /* Setup our intr mask. */ |
b5c80475 FF |
642 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
643 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
644 | ATH9K_INT_GLOBAL; | |
645 | ||
646 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
647 | ah->imask |= ATH9K_INT_RXHP | |
648 | ATH9K_INT_RXLP | | |
649 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
650 | else |
651 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 652 | |
364734fa | 653 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 654 | |
af03abec | 655 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 656 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 657 | |
e270e776 | 658 | ath_mci_enable(sc); |
40dc5392 | 659 | |
781b14a3 | 660 | clear_bit(SC_OP_INVALID, &sc->sc_flags); |
5f841b41 | 661 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 662 | |
9adcf440 FF |
663 | if (!ath_complete_reset(sc, false)) { |
664 | r = -EIO; | |
665 | spin_unlock_bh(&sc->sc_pcu_lock); | |
666 | goto mutex_unlock; | |
667 | } | |
ff37e337 | 668 | |
c0c11741 FF |
669 | if (ah->led_pin >= 0) { |
670 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
671 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
672 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
673 | } | |
674 | ||
675 | /* | |
676 | * Reset key cache to sane defaults (all entries cleared) instead of | |
677 | * semi-random values after suspend/resume. | |
678 | */ | |
679 | ath9k_cmn_init_crypto(sc->sc_ah); | |
680 | ||
9adcf440 | 681 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 682 | |
8060e169 VT |
683 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
684 | common->bus_ops->extn_synch_en(common); | |
685 | ||
141b38b6 S |
686 | mutex_unlock: |
687 | mutex_unlock(&sc->mutex); | |
688 | ||
f62d816f FF |
689 | ath9k_ps_restore(sc); |
690 | ||
ae8d2858 | 691 | return r; |
f078f209 LR |
692 | } |
693 | ||
7bb45683 | 694 | static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 695 | { |
9ac58615 | 696 | struct ath_softc *sc = hw->priv; |
c46917bb | 697 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 698 | struct ath_tx_control txctl; |
1bc14880 | 699 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
07c15a3f | 700 | unsigned long flags; |
528f0c6b | 701 | |
96148326 | 702 | if (sc->ps_enabled) { |
dc8c4585 JM |
703 | /* |
704 | * mac80211 does not set PM field for normal data frames, so we | |
705 | * need to update that based on the current PS mode. | |
706 | */ | |
707 | if (ieee80211_is_data(hdr->frame_control) && | |
708 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
709 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 710 | ath_dbg(common, PS, |
226afe68 | 711 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
712 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
713 | } | |
714 | } | |
715 | ||
ad128860 | 716 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
717 | /* |
718 | * We are using PS-Poll and mac80211 can request TX while in | |
719 | * power save mode. Need to wake up hardware for the TX to be | |
720 | * completed and if needed, also for RX of buffered frames. | |
721 | */ | |
9a23f9ca | 722 | ath9k_ps_wakeup(sc); |
07c15a3f | 723 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
fdf76622 VT |
724 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
725 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 726 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 727 | ath_dbg(common, PS, |
226afe68 | 728 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 729 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 730 | } else { |
d2182b69 | 731 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 732 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
733 | } |
734 | /* | |
735 | * The actual restore operation will happen only after | |
ad128860 | 736 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
737 | * the ps_usecount here. |
738 | */ | |
07c15a3f | 739 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca JM |
740 | ath9k_ps_restore(sc); |
741 | } | |
742 | ||
ad128860 SM |
743 | /* |
744 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
745 | * chip reset to recover from that | |
746 | */ | |
747 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
748 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
749 | goto exit; | |
750 | } | |
751 | ||
528f0c6b | 752 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 753 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 754 | |
d2182b69 | 755 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 756 | |
c52f33d0 | 757 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 758 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 759 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 760 | goto exit; |
8feceb67 VT |
761 | } |
762 | ||
7bb45683 | 763 | return; |
528f0c6b S |
764 | exit: |
765 | dev_kfree_skb_any(skb); | |
f078f209 LR |
766 | } |
767 | ||
8feceb67 | 768 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 769 | { |
9ac58615 | 770 | struct ath_softc *sc = hw->priv; |
af03abec | 771 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 772 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 773 | bool prev_idle; |
f078f209 | 774 | |
4c483817 S |
775 | mutex_lock(&sc->mutex); |
776 | ||
9adcf440 | 777 | ath_cancel_work(sc); |
01e18918 | 778 | del_timer_sync(&sc->rx_poll_timer); |
c94dbff7 | 779 | |
781b14a3 | 780 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 781 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 782 | mutex_unlock(&sc->mutex); |
9c84b797 S |
783 | return; |
784 | } | |
8feceb67 | 785 | |
3867cf6a S |
786 | /* Ensure HW is awake when we try to shut it down. */ |
787 | ath9k_ps_wakeup(sc); | |
788 | ||
6a6733f2 LR |
789 | spin_lock_bh(&sc->sc_pcu_lock); |
790 | ||
203043f5 SG |
791 | /* prevent tasklets to enable interrupts once we disable them */ |
792 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
793 | ||
ff37e337 S |
794 | /* make sure h/w will not generate any interrupt |
795 | * before setting the invalid flag. */ | |
4df3071e | 796 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 797 | |
c0c11741 FF |
798 | spin_unlock_bh(&sc->sc_pcu_lock); |
799 | ||
800 | /* we can now sync irq and kill any running tasklets, since we already | |
801 | * disabled interrupts and not holding a spin lock */ | |
802 | synchronize_irq(sc->irq); | |
803 | tasklet_kill(&sc->intr_tq); | |
804 | tasklet_kill(&sc->bcon_tasklet); | |
805 | ||
806 | prev_idle = sc->ps_idle; | |
807 | sc->ps_idle = true; | |
808 | ||
809 | spin_lock_bh(&sc->sc_pcu_lock); | |
810 | ||
811 | if (ah->led_pin >= 0) { | |
812 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
813 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
814 | } | |
815 | ||
816 | ath_prepare_reset(sc, false, true); | |
ff37e337 | 817 | |
0d95521e FF |
818 | if (sc->rx.frag) { |
819 | dev_kfree_skb_any(sc->rx.frag); | |
820 | sc->rx.frag = NULL; | |
821 | } | |
822 | ||
c0c11741 FF |
823 | if (!ah->curchan) |
824 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); | |
6a6733f2 | 825 | |
c0c11741 FF |
826 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
827 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 828 | |
c0c11741 | 829 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 830 | |
c0c11741 | 831 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 832 | |
c0c11741 | 833 | ath9k_ps_restore(sc); |
ff37e337 | 834 | |
781b14a3 | 835 | set_bit(SC_OP_INVALID, &sc->sc_flags); |
c0c11741 | 836 | sc->ps_idle = prev_idle; |
500c064d | 837 | |
141b38b6 S |
838 | mutex_unlock(&sc->mutex); |
839 | ||
d2182b69 | 840 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
841 | } |
842 | ||
4801416c BG |
843 | bool ath9k_uses_beacons(int type) |
844 | { | |
845 | switch (type) { | |
846 | case NL80211_IFTYPE_AP: | |
847 | case NL80211_IFTYPE_ADHOC: | |
848 | case NL80211_IFTYPE_MESH_POINT: | |
849 | return true; | |
850 | default: | |
851 | return false; | |
852 | } | |
853 | } | |
854 | ||
4801416c BG |
855 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
856 | { | |
857 | struct ath9k_vif_iter_data *iter_data = data; | |
858 | int i; | |
859 | ||
860 | if (iter_data->hw_macaddr) | |
861 | for (i = 0; i < ETH_ALEN; i++) | |
862 | iter_data->mask[i] &= | |
863 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 864 | |
1ed32e4f | 865 | switch (vif->type) { |
4801416c BG |
866 | case NL80211_IFTYPE_AP: |
867 | iter_data->naps++; | |
f078f209 | 868 | break; |
4801416c BG |
869 | case NL80211_IFTYPE_STATION: |
870 | iter_data->nstations++; | |
e51f3eff | 871 | break; |
05c914fe | 872 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
873 | iter_data->nadhocs++; |
874 | break; | |
9cb5412b | 875 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
876 | iter_data->nmeshes++; |
877 | break; | |
878 | case NL80211_IFTYPE_WDS: | |
879 | iter_data->nwds++; | |
f078f209 LR |
880 | break; |
881 | default: | |
4801416c | 882 | break; |
f078f209 | 883 | } |
4801416c | 884 | } |
f078f209 | 885 | |
4801416c BG |
886 | /* Called with sc->mutex held. */ |
887 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
888 | struct ieee80211_vif *vif, | |
889 | struct ath9k_vif_iter_data *iter_data) | |
890 | { | |
9ac58615 | 891 | struct ath_softc *sc = hw->priv; |
4801416c BG |
892 | struct ath_hw *ah = sc->sc_ah; |
893 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 894 | |
4801416c BG |
895 | /* |
896 | * Use the hardware MAC address as reference, the hardware uses it | |
897 | * together with the BSSID mask when matching addresses. | |
898 | */ | |
899 | memset(iter_data, 0, sizeof(*iter_data)); | |
900 | iter_data->hw_macaddr = common->macaddr; | |
901 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 902 | |
4801416c BG |
903 | if (vif) |
904 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
905 | ||
906 | /* Get list of all active MAC addresses */ | |
4801416c BG |
907 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
908 | iter_data); | |
4801416c | 909 | } |
8ca21f01 | 910 | |
4801416c BG |
911 | /* Called with sc->mutex held. */ |
912 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
913 | struct ieee80211_vif *vif) | |
914 | { | |
9ac58615 | 915 | struct ath_softc *sc = hw->priv; |
4801416c BG |
916 | struct ath_hw *ah = sc->sc_ah; |
917 | struct ath_common *common = ath9k_hw_common(ah); | |
918 | struct ath9k_vif_iter_data iter_data; | |
8ca21f01 | 919 | |
4801416c | 920 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 921 | |
4801416c BG |
922 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); |
923 | ath_hw_setbssidmask(common); | |
924 | ||
4801416c | 925 | if (iter_data.naps > 0) { |
60ca9f87 | 926 | ath9k_hw_set_tsfadjust(ah, true); |
4801416c BG |
927 | ah->opmode = NL80211_IFTYPE_AP; |
928 | } else { | |
60ca9f87 | 929 | ath9k_hw_set_tsfadjust(ah, false); |
5640b08e | 930 | |
fd5999cf JC |
931 | if (iter_data.nmeshes) |
932 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
933 | else if (iter_data.nwds) | |
4801416c BG |
934 | ah->opmode = NL80211_IFTYPE_AP; |
935 | else if (iter_data.nadhocs) | |
936 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
937 | else | |
938 | ah->opmode = NL80211_IFTYPE_STATION; | |
939 | } | |
5640b08e | 940 | |
df35d29e SM |
941 | ath9k_hw_setopmode(ah); |
942 | ||
198823fd | 943 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) |
3069168c | 944 | ah->imask |= ATH9K_INT_TSFOOR; |
198823fd | 945 | else |
4801416c | 946 | ah->imask &= ~ATH9K_INT_TSFOOR; |
4af9cf4f | 947 | |
72d874c6 | 948 | ath9k_hw_set_interrupts(ah); |
4801416c | 949 | } |
6f255425 | 950 | |
4801416c BG |
951 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
952 | struct ieee80211_vif *vif) | |
6b3b991d | 953 | { |
9ac58615 | 954 | struct ath_softc *sc = hw->priv; |
4801416c BG |
955 | struct ath_hw *ah = sc->sc_ah; |
956 | struct ath_common *common = ath9k_hw_common(ah); | |
4801416c | 957 | int ret = 0; |
6b3b991d | 958 | |
96f372c9 | 959 | ath9k_ps_wakeup(sc); |
4801416c | 960 | mutex_lock(&sc->mutex); |
6b3b991d | 961 | |
4801416c BG |
962 | switch (vif->type) { |
963 | case NL80211_IFTYPE_STATION: | |
964 | case NL80211_IFTYPE_WDS: | |
965 | case NL80211_IFTYPE_ADHOC: | |
966 | case NL80211_IFTYPE_AP: | |
967 | case NL80211_IFTYPE_MESH_POINT: | |
968 | break; | |
969 | default: | |
970 | ath_err(common, "Interface type %d not yet supported\n", | |
971 | vif->type); | |
972 | ret = -EOPNOTSUPP; | |
973 | goto out; | |
974 | } | |
6b3b991d | 975 | |
4801416c BG |
976 | if (ath9k_uses_beacons(vif->type)) { |
977 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
978 | ath_err(common, "Not enough beacon buffers when adding" | |
979 | " new interface of type: %i\n", | |
980 | vif->type); | |
981 | ret = -ENOBUFS; | |
982 | goto out; | |
983 | } | |
984 | } | |
985 | ||
d2182b69 | 986 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
4801416c | 987 | |
4801416c BG |
988 | sc->nvifs++; |
989 | ||
130ef6e9 SM |
990 | ath9k_calculate_summary_state(hw, vif); |
991 | if (ath9k_uses_beacons(vif->type)) | |
992 | ath9k_beacon_assign_slot(sc, vif); | |
993 | ||
4801416c BG |
994 | out: |
995 | mutex_unlock(&sc->mutex); | |
96f372c9 | 996 | ath9k_ps_restore(sc); |
4801416c | 997 | return ret; |
6b3b991d RM |
998 | } |
999 | ||
1000 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1001 | struct ieee80211_vif *vif, | |
1002 | enum nl80211_iftype new_type, | |
1003 | bool p2p) | |
1004 | { | |
9ac58615 | 1005 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1006 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6dab55bf | 1007 | int ret = 0; |
6b3b991d | 1008 | |
d2182b69 | 1009 | ath_dbg(common, CONFIG, "Change Interface\n"); |
130ef6e9 | 1010 | |
6b3b991d | 1011 | mutex_lock(&sc->mutex); |
96f372c9 | 1012 | ath9k_ps_wakeup(sc); |
6b3b991d | 1013 | |
4801416c BG |
1014 | if (ath9k_uses_beacons(new_type) && |
1015 | !ath9k_uses_beacons(vif->type)) { | |
6b3b991d RM |
1016 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1017 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1018 | ret = -ENOBUFS; |
1019 | goto out; | |
6b3b991d | 1020 | } |
6b3b991d | 1021 | } |
4801416c | 1022 | |
4801416c | 1023 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1024 | ath9k_beacon_remove_slot(sc, vif); |
4801416c | 1025 | |
6b3b991d RM |
1026 | vif->type = new_type; |
1027 | vif->p2p = p2p; | |
1028 | ||
130ef6e9 SM |
1029 | ath9k_calculate_summary_state(hw, vif); |
1030 | if (ath9k_uses_beacons(vif->type)) | |
1031 | ath9k_beacon_assign_slot(sc, vif); | |
1032 | ||
6dab55bf | 1033 | out: |
96f372c9 | 1034 | ath9k_ps_restore(sc); |
6b3b991d | 1035 | mutex_unlock(&sc->mutex); |
6dab55bf | 1036 | return ret; |
6b3b991d RM |
1037 | } |
1038 | ||
8feceb67 | 1039 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1040 | struct ieee80211_vif *vif) |
f078f209 | 1041 | { |
9ac58615 | 1042 | struct ath_softc *sc = hw->priv; |
c46917bb | 1043 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1044 | |
d2182b69 | 1045 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1046 | |
96f372c9 | 1047 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1048 | mutex_lock(&sc->mutex); |
1049 | ||
4801416c | 1050 | sc->nvifs--; |
580f0b8a | 1051 | |
4801416c | 1052 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1053 | ath9k_beacon_remove_slot(sc, vif); |
2c3db3d5 | 1054 | |
4801416c | 1055 | ath9k_calculate_summary_state(hw, NULL); |
141b38b6 S |
1056 | |
1057 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1058 | ath9k_ps_restore(sc); |
f078f209 LR |
1059 | } |
1060 | ||
fbab7390 | 1061 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1062 | { |
3069168c | 1063 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1064 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1065 | |
3f7c5c10 | 1066 | sc->ps_enabled = true; |
3069168c PR |
1067 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1068 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1069 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1070 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1071 | } |
fdf76622 | 1072 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1073 | } |
ad128860 | 1074 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1075 | } |
1076 | ||
845d708e SB |
1077 | static void ath9k_disable_ps(struct ath_softc *sc) |
1078 | { | |
1079 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1080 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e SB |
1081 | |
1082 | sc->ps_enabled = false; | |
1083 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1084 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1085 | ath9k_hw_setrxabort(ah, 0); | |
1086 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1087 | PS_WAIT_FOR_CAB | | |
1088 | PS_WAIT_FOR_PSPOLL_DATA | | |
1089 | PS_WAIT_FOR_TX_ACK); | |
1090 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1091 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1092 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1093 | } |
1094 | } | |
ad128860 | 1095 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1096 | } |
1097 | ||
e8975581 | 1098 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1099 | { |
9ac58615 | 1100 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1101 | struct ath_hw *ah = sc->sc_ah; |
1102 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1103 | struct ieee80211_conf *conf = &hw->conf; |
75600abf | 1104 | bool reset_channel = false; |
f078f209 | 1105 | |
c0c11741 | 1106 | ath9k_ps_wakeup(sc); |
aa33de09 | 1107 | mutex_lock(&sc->mutex); |
141b38b6 | 1108 | |
daa1b6ee | 1109 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1110 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
b73f3e78 | 1111 | if (sc->ps_idle) { |
daa1b6ee | 1112 | ath_cancel_work(sc); |
b73f3e78 RM |
1113 | ath9k_stop_btcoex(sc); |
1114 | } else { | |
1115 | ath9k_start_btcoex(sc); | |
75600abf FF |
1116 | /* |
1117 | * The chip needs a reset to properly wake up from | |
1118 | * full sleep | |
1119 | */ | |
1120 | reset_channel = ah->chip_fullsleep; | |
b73f3e78 | 1121 | } |
daa1b6ee | 1122 | } |
64839170 | 1123 | |
e7824a50 LR |
1124 | /* |
1125 | * We just prepare to enable PS. We have to wait until our AP has | |
1126 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1127 | * those ACKs and end up retransmitting the same null data frames. | |
1128 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1129 | */ | |
3cbb5dd7 | 1130 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1131 | unsigned long flags; |
1132 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1133 | if (conf->flags & IEEE80211_CONF_PS) |
1134 | ath9k_enable_ps(sc); | |
845d708e SB |
1135 | else |
1136 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1137 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1138 | } |
1139 | ||
199afd9d S |
1140 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1141 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1142 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1143 | sc->sc_ah->is_monitoring = true; |
1144 | } else { | |
d2182b69 | 1145 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1146 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1147 | } |
1148 | } | |
1149 | ||
75600abf | 1150 | if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { |
99405f93 | 1151 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1152 | int pos = curchan->hw_value; |
3430098a FF |
1153 | int old_pos = -1; |
1154 | unsigned long flags; | |
1155 | ||
1156 | if (ah->curchan) | |
1157 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1158 | |
d2182b69 | 1159 | ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", |
8c79a610 | 1160 | curchan->center_freq, conf->channel_type); |
f078f209 | 1161 | |
3430098a FF |
1162 | /* update survey stats for the old channel before switching */ |
1163 | spin_lock_irqsave(&common->cc_lock, flags); | |
1164 | ath_update_survey_stats(sc); | |
1165 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1166 | ||
e338a85e RM |
1167 | /* |
1168 | * Preserve the current channel values, before updating | |
1169 | * the same channel | |
1170 | */ | |
1a19f77f RM |
1171 | if (ah->curchan && (old_pos == pos)) |
1172 | ath9k_hw_getnf(ah, ah->curchan); | |
e338a85e RM |
1173 | |
1174 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], | |
1175 | curchan, conf->channel_type); | |
1176 | ||
3430098a FF |
1177 | /* |
1178 | * If the operating channel changes, change the survey in-use flags | |
1179 | * along with it. | |
1180 | * Reset the survey data for the new channel, unless we're switching | |
1181 | * back to the operating channel from an off-channel operation. | |
1182 | */ | |
1183 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1184 | sc->cur_survey != &sc->survey[pos]) { | |
1185 | ||
1186 | if (sc->cur_survey) | |
1187 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1188 | ||
1189 | sc->cur_survey = &sc->survey[pos]; | |
1190 | ||
1191 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1192 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1193 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1194 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1195 | } | |
1196 | ||
0e2dedf9 | 1197 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1198 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1199 | mutex_unlock(&sc->mutex); |
8389fb3f | 1200 | ath9k_ps_restore(sc); |
e11602b7 S |
1201 | return -EINVAL; |
1202 | } | |
3430098a FF |
1203 | |
1204 | /* | |
1205 | * The most recent snapshot of channel->noisefloor for the old | |
1206 | * channel is only available after the hardware reset. Copy it to | |
1207 | * the survey stats now. | |
1208 | */ | |
1209 | if (old_pos >= 0) | |
1210 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1211 | } |
f078f209 | 1212 | |
c9f6a656 | 1213 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
d2182b69 | 1214 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
17d7904d | 1215 | sc->config.txpowlimit = 2 * conf->power_level; |
5048e8c3 RM |
1216 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1217 | sc->config.txpowlimit, &sc->curtxpow); | |
64839170 LR |
1218 | } |
1219 | ||
aa33de09 | 1220 | mutex_unlock(&sc->mutex); |
c0c11741 | 1221 | ath9k_ps_restore(sc); |
141b38b6 | 1222 | |
f078f209 LR |
1223 | return 0; |
1224 | } | |
1225 | ||
8feceb67 VT |
1226 | #define SUPPORTED_FILTERS \ |
1227 | (FIF_PROMISC_IN_BSS | \ | |
1228 | FIF_ALLMULTI | \ | |
1229 | FIF_CONTROL | \ | |
af6a3fc7 | 1230 | FIF_PSPOLL | \ |
8feceb67 VT |
1231 | FIF_OTHER_BSS | \ |
1232 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1233 | FIF_PROBE_REQ | \ |
8feceb67 | 1234 | FIF_FCSFAIL) |
c83be688 | 1235 | |
8feceb67 VT |
1236 | /* FIXME: sc->sc_full_reset ? */ |
1237 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1238 | unsigned int changed_flags, | |
1239 | unsigned int *total_flags, | |
3ac64bee | 1240 | u64 multicast) |
8feceb67 | 1241 | { |
9ac58615 | 1242 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1243 | u32 rfilt; |
f078f209 | 1244 | |
8feceb67 VT |
1245 | changed_flags &= SUPPORTED_FILTERS; |
1246 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1247 | |
b77f483f | 1248 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1249 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1250 | rfilt = ath_calcrxfilter(sc); |
1251 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1252 | ath9k_ps_restore(sc); |
f078f209 | 1253 | |
d2182b69 JP |
1254 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1255 | rfilt); | |
8feceb67 | 1256 | } |
f078f209 | 1257 | |
4ca77860 JB |
1258 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1259 | struct ieee80211_vif *vif, | |
1260 | struct ieee80211_sta *sta) | |
8feceb67 | 1261 | { |
9ac58615 | 1262 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1263 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1264 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1265 | struct ieee80211_key_conf ps_key = { }; | |
f078f209 | 1266 | |
7e1e3864 | 1267 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1268 | |
1269 | if (vif->type != NL80211_IFTYPE_AP && | |
1270 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1271 | return 0; | |
1272 | ||
93ae2dd2 | 1273 | an->ps_key = ath_key_config(common, vif, sta, &ps_key); |
4ca77860 JB |
1274 | |
1275 | return 0; | |
1276 | } | |
1277 | ||
93ae2dd2 FF |
1278 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1279 | struct ieee80211_vif *vif, | |
1280 | struct ieee80211_sta *sta) | |
1281 | { | |
1282 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1283 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1284 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1285 | ||
1286 | if (!an->ps_key) | |
1287 | return; | |
1288 | ||
1289 | ath_key_delete(common, &ps_key); | |
1290 | } | |
1291 | ||
4ca77860 JB |
1292 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1293 | struct ieee80211_vif *vif, | |
1294 | struct ieee80211_sta *sta) | |
1295 | { | |
9ac58615 | 1296 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1297 | |
93ae2dd2 | 1298 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1299 | ath_node_detach(sc, sta); |
1300 | ||
1301 | return 0; | |
f078f209 LR |
1302 | } |
1303 | ||
5519541d FF |
1304 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1305 | struct ieee80211_vif *vif, | |
1306 | enum sta_notify_cmd cmd, | |
1307 | struct ieee80211_sta *sta) | |
1308 | { | |
1309 | struct ath_softc *sc = hw->priv; | |
1310 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1311 | ||
3d4e20f2 | 1312 | if (!sta->ht_cap.ht_supported) |
b25bfda3 MSS |
1313 | return; |
1314 | ||
5519541d FF |
1315 | switch (cmd) { |
1316 | case STA_NOTIFY_SLEEP: | |
1317 | an->sleeping = true; | |
042ec453 | 1318 | ath_tx_aggr_sleep(sta, sc, an); |
5519541d FF |
1319 | break; |
1320 | case STA_NOTIFY_AWAKE: | |
1321 | an->sleeping = false; | |
1322 | ath_tx_aggr_wakeup(sc, an); | |
1323 | break; | |
1324 | } | |
1325 | } | |
1326 | ||
8a3a3c85 EP |
1327 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1328 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1329 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1330 | { |
9ac58615 | 1331 | struct ath_softc *sc = hw->priv; |
c46917bb | 1332 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1333 | struct ath_txq *txq; |
8feceb67 | 1334 | struct ath9k_tx_queue_info qi; |
066dae93 | 1335 | int ret = 0; |
f078f209 | 1336 | |
8feceb67 VT |
1337 | if (queue >= WME_NUM_AC) |
1338 | return 0; | |
f078f209 | 1339 | |
066dae93 FF |
1340 | txq = sc->tx.txq_map[queue]; |
1341 | ||
96f372c9 | 1342 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1343 | mutex_lock(&sc->mutex); |
1344 | ||
1ffb0610 S |
1345 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1346 | ||
8feceb67 VT |
1347 | qi.tqi_aifs = params->aifs; |
1348 | qi.tqi_cwmin = params->cw_min; | |
1349 | qi.tqi_cwmax = params->cw_max; | |
531bd079 | 1350 | qi.tqi_burstTime = params->txop * 32; |
f078f209 | 1351 | |
d2182b69 | 1352 | ath_dbg(common, CONFIG, |
226afe68 JP |
1353 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1354 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1355 | params->cw_max, params->txop); | |
f078f209 | 1356 | |
aa5955c3 | 1357 | ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); |
066dae93 | 1358 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1359 | if (ret) |
3800276a | 1360 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1361 | |
141b38b6 | 1362 | mutex_unlock(&sc->mutex); |
96f372c9 | 1363 | ath9k_ps_restore(sc); |
141b38b6 | 1364 | |
8feceb67 VT |
1365 | return ret; |
1366 | } | |
f078f209 | 1367 | |
8feceb67 VT |
1368 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1369 | enum set_key_cmd cmd, | |
dc822b5d JB |
1370 | struct ieee80211_vif *vif, |
1371 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1372 | struct ieee80211_key_conf *key) |
1373 | { | |
9ac58615 | 1374 | struct ath_softc *sc = hw->priv; |
c46917bb | 1375 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1376 | int ret = 0; |
f078f209 | 1377 | |
3e6109c5 | 1378 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1379 | return -ENOSPC; |
1380 | ||
5bd5e9a6 CYY |
1381 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1382 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1383 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1384 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1385 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1386 | /* | |
1387 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1388 | * could be optimized in the future to use a modified key cache | |
1389 | * design to support per-STA RX GTK, but until that gets | |
1390 | * implemented, use of software crypto for group addressed | |
1391 | * frames is a acceptable to allow RSN IBSS to be used. | |
1392 | */ | |
1393 | return -EOPNOTSUPP; | |
1394 | } | |
1395 | ||
141b38b6 | 1396 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1397 | ath9k_ps_wakeup(sc); |
d2182b69 | 1398 | ath_dbg(common, CONFIG, "Set HW Key\n"); |
f078f209 | 1399 | |
8feceb67 VT |
1400 | switch (cmd) { |
1401 | case SET_KEY: | |
93ae2dd2 FF |
1402 | if (sta) |
1403 | ath9k_del_ps_key(sc, vif, sta); | |
1404 | ||
040e539e | 1405 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1406 | if (ret >= 0) { |
1407 | key->hw_key_idx = ret; | |
8feceb67 VT |
1408 | /* push IV and Michael MIC generation to stack */ |
1409 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1410 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1411 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1412 | if (sc->sc_ah->sw_mgmt_crypto && |
1413 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1414 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1415 | ret = 0; |
8feceb67 VT |
1416 | } |
1417 | break; | |
1418 | case DISABLE_KEY: | |
040e539e | 1419 | ath_key_delete(common, key); |
8feceb67 VT |
1420 | break; |
1421 | default: | |
1422 | ret = -EINVAL; | |
1423 | } | |
f078f209 | 1424 | |
3cbb5dd7 | 1425 | ath9k_ps_restore(sc); |
141b38b6 S |
1426 | mutex_unlock(&sc->mutex); |
1427 | ||
8feceb67 VT |
1428 | return ret; |
1429 | } | |
6c43c090 SM |
1430 | |
1431 | static void ath9k_set_assoc_state(struct ath_softc *sc, | |
1432 | struct ieee80211_vif *vif) | |
4f5ef75b | 1433 | { |
4f5ef75b | 1434 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4f5ef75b | 1435 | struct ath_vif *avp = (void *)vif->drv_priv; |
6c43c090 | 1436 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
07c15a3f | 1437 | unsigned long flags; |
6c43c090 SM |
1438 | |
1439 | set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1440 | avp->primary_sta_vif = true; | |
1441 | ||
2e5ef459 | 1442 | /* |
6c43c090 SM |
1443 | * Set the AID, BSSID and do beacon-sync only when |
1444 | * the HW opmode is STATION. | |
1445 | * | |
1446 | * But the primary bit is set above in any case. | |
2e5ef459 | 1447 | */ |
6c43c090 | 1448 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
2e5ef459 RM |
1449 | return; |
1450 | ||
6c43c090 SM |
1451 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1452 | common->curaid = bss_conf->aid; | |
1453 | ath9k_hw_write_associd(sc->sc_ah); | |
07c15a3f | 1454 | |
6c43c090 SM |
1455 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
1456 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1457 | |
6c43c090 SM |
1458 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
1459 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1460 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
05c0be2f | 1461 | |
6c43c090 SM |
1462 | ath_dbg(common, CONFIG, |
1463 | "Primary Station interface: %pM, BSSID: %pM\n", | |
1464 | vif->addr, common->curbssid); | |
4f5ef75b RM |
1465 | } |
1466 | ||
6c43c090 | 1467 | static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
4f5ef75b | 1468 | { |
6c43c090 | 1469 | struct ath_softc *sc = data; |
4f5ef75b | 1470 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
4f5ef75b | 1471 | |
6c43c090 | 1472 | if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) |
2e5ef459 RM |
1473 | return; |
1474 | ||
6c43c090 SM |
1475 | if (bss_conf->assoc) |
1476 | ath9k_set_assoc_state(sc, vif); | |
4f5ef75b | 1477 | } |
f078f209 | 1478 | |
8feceb67 VT |
1479 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1480 | struct ieee80211_vif *vif, | |
1481 | struct ieee80211_bss_conf *bss_conf, | |
1482 | u32 changed) | |
1483 | { | |
9ac58615 | 1484 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1485 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1486 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1487 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1488 | int slottime; |
f078f209 | 1489 | |
96f372c9 | 1490 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1491 | mutex_lock(&sc->mutex); |
1492 | ||
9f61903c | 1493 | if (changed & BSS_CHANGED_ASSOC) { |
6c43c090 SM |
1494 | ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", |
1495 | bss_conf->bssid, bss_conf->assoc); | |
1496 | ||
1497 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
1498 | clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1499 | avp->primary_sta_vif = false; | |
1500 | ||
1501 | if (ah->opmode == NL80211_IFTYPE_STATION) | |
1502 | clear_bit(SC_OP_BEACONS, &sc->sc_flags); | |
1503 | } | |
1504 | ||
1505 | ieee80211_iterate_active_interfaces_atomic(sc->hw, | |
1506 | ath9k_bss_assoc_iter, sc); | |
2d0ddec5 | 1507 | |
6c43c090 SM |
1508 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && |
1509 | ah->opmode == NL80211_IFTYPE_STATION) { | |
1510 | memset(common->curbssid, 0, ETH_ALEN); | |
1511 | common->curaid = 0; | |
1512 | ath9k_hw_write_associd(sc->sc_ah); | |
1513 | } | |
c6089ccc | 1514 | } |
2d0ddec5 | 1515 | |
2e5ef459 | 1516 | if (changed & BSS_CHANGED_IBSS) { |
2e5ef459 RM |
1517 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1518 | common->curaid = bss_conf->aid; | |
1519 | ath9k_hw_write_associd(sc->sc_ah); | |
1520 | ||
1521 | if (bss_conf->ibss_joined) { | |
05c0be2f | 1522 | if (!common->disable_ani) { |
781b14a3 | 1523 | set_bit(SC_OP_ANI_RUN, &sc->sc_flags); |
05c0be2f MSS |
1524 | ath_start_ani(common); |
1525 | } | |
2e5ef459 | 1526 | } else { |
781b14a3 | 1527 | clear_bit(SC_OP_ANI_RUN, &sc->sc_flags); |
2e5ef459 RM |
1528 | del_timer_sync(&common->ani.timer); |
1529 | } | |
1530 | } | |
1531 | ||
ef4ad633 SM |
1532 | if ((changed & BSS_CHANGED_BEACON_ENABLED) || |
1533 | (changed & BSS_CHANGED_BEACON_INT)) { | |
2f8e82e8 SM |
1534 | if (ah->opmode == NL80211_IFTYPE_AP && |
1535 | bss_conf->enable_beacon) | |
1536 | ath9k_set_tsfadjust(sc, vif); | |
ef4ad633 SM |
1537 | if (ath9k_allow_beacon_config(sc, vif)) |
1538 | ath9k_beacon_config(sc, vif, changed); | |
0005baf4 FF |
1539 | } |
1540 | ||
1541 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1542 | if (bss_conf->use_short_slot) | |
1543 | slottime = 9; | |
1544 | else | |
1545 | slottime = 20; | |
1546 | if (vif->type == NL80211_IFTYPE_AP) { | |
1547 | /* | |
1548 | * Defer update, so that connected stations can adjust | |
1549 | * their settings at the same time. | |
1550 | * See beacon.c for more details | |
1551 | */ | |
1552 | sc->beacon.slottime = slottime; | |
1553 | sc->beacon.updateslot = UPDATE; | |
1554 | } else { | |
1555 | ah->slottime = slottime; | |
1556 | ath9k_hw_init_global_settings(ah); | |
1557 | } | |
2d0ddec5 JB |
1558 | } |
1559 | ||
141b38b6 | 1560 | mutex_unlock(&sc->mutex); |
96f372c9 | 1561 | ath9k_ps_restore(sc); |
8feceb67 | 1562 | } |
f078f209 | 1563 | |
37a41b4a | 1564 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1565 | { |
9ac58615 | 1566 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1567 | u64 tsf; |
f078f209 | 1568 | |
141b38b6 | 1569 | mutex_lock(&sc->mutex); |
9abbfb27 | 1570 | ath9k_ps_wakeup(sc); |
141b38b6 | 1571 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1572 | ath9k_ps_restore(sc); |
141b38b6 | 1573 | mutex_unlock(&sc->mutex); |
f078f209 | 1574 | |
8feceb67 VT |
1575 | return tsf; |
1576 | } | |
f078f209 | 1577 | |
37a41b4a EP |
1578 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
1579 | struct ieee80211_vif *vif, | |
1580 | u64 tsf) | |
3b5d665b | 1581 | { |
9ac58615 | 1582 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1583 | |
141b38b6 | 1584 | mutex_lock(&sc->mutex); |
9abbfb27 | 1585 | ath9k_ps_wakeup(sc); |
141b38b6 | 1586 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1587 | ath9k_ps_restore(sc); |
141b38b6 | 1588 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1589 | } |
1590 | ||
37a41b4a | 1591 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1592 | { |
9ac58615 | 1593 | struct ath_softc *sc = hw->priv; |
c83be688 | 1594 | |
141b38b6 | 1595 | mutex_lock(&sc->mutex); |
21526d57 LR |
1596 | |
1597 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1598 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1599 | ath9k_ps_restore(sc); |
1600 | ||
141b38b6 | 1601 | mutex_unlock(&sc->mutex); |
8feceb67 | 1602 | } |
f078f209 | 1603 | |
8feceb67 | 1604 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1605 | struct ieee80211_vif *vif, |
141b38b6 S |
1606 | enum ieee80211_ampdu_mlme_action action, |
1607 | struct ieee80211_sta *sta, | |
0b01f030 | 1608 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 1609 | { |
9ac58615 | 1610 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1611 | int ret = 0; |
f078f209 | 1612 | |
85ad181e JB |
1613 | local_bh_disable(); |
1614 | ||
8feceb67 VT |
1615 | switch (action) { |
1616 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
1617 | break; |
1618 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1619 | break; |
1620 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1621 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1622 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1623 | if (!ret) | |
1624 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1625 | ath9k_ps_restore(sc); |
8feceb67 VT |
1626 | break; |
1627 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1628 | ath9k_ps_wakeup(sc); |
f83da965 | 1629 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1630 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1631 | ath9k_ps_restore(sc); |
8feceb67 | 1632 | break; |
b1720231 | 1633 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1634 | ath9k_ps_wakeup(sc); |
8469cdef | 1635 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1636 | ath9k_ps_restore(sc); |
8469cdef | 1637 | break; |
8feceb67 | 1638 | default: |
3800276a | 1639 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
1640 | } |
1641 | ||
85ad181e JB |
1642 | local_bh_enable(); |
1643 | ||
8feceb67 | 1644 | return ret; |
f078f209 LR |
1645 | } |
1646 | ||
62dad5b0 BP |
1647 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1648 | struct survey_info *survey) | |
1649 | { | |
9ac58615 | 1650 | struct ath_softc *sc = hw->priv; |
3430098a | 1651 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 1652 | struct ieee80211_supported_band *sband; |
3430098a FF |
1653 | struct ieee80211_channel *chan; |
1654 | unsigned long flags; | |
1655 | int pos; | |
1656 | ||
1657 | spin_lock_irqsave(&common->cc_lock, flags); | |
1658 | if (idx == 0) | |
1659 | ath_update_survey_stats(sc); | |
39162dbe FF |
1660 | |
1661 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
1662 | if (sband && idx >= sband->n_channels) { | |
1663 | idx -= sband->n_channels; | |
1664 | sband = NULL; | |
1665 | } | |
62dad5b0 | 1666 | |
39162dbe FF |
1667 | if (!sband) |
1668 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 1669 | |
3430098a FF |
1670 | if (!sband || idx >= sband->n_channels) { |
1671 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1672 | return -ENOENT; | |
4f1a5a4b | 1673 | } |
62dad5b0 | 1674 | |
3430098a FF |
1675 | chan = &sband->channels[idx]; |
1676 | pos = chan->hw_value; | |
1677 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
1678 | survey->channel = chan; | |
1679 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1680 | ||
62dad5b0 BP |
1681 | return 0; |
1682 | } | |
1683 | ||
e239d859 FF |
1684 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
1685 | { | |
9ac58615 | 1686 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
1687 | struct ath_hw *ah = sc->sc_ah; |
1688 | ||
1689 | mutex_lock(&sc->mutex); | |
1690 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
1691 | |
1692 | ath9k_ps_wakeup(sc); | |
e239d859 | 1693 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
1694 | ath9k_ps_restore(sc); |
1695 | ||
e239d859 FF |
1696 | mutex_unlock(&sc->mutex); |
1697 | } | |
1698 | ||
69081624 VT |
1699 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
1700 | { | |
69081624 | 1701 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
1702 | struct ath_hw *ah = sc->sc_ah; |
1703 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
1704 | int timeout = 200; /* ms */ |
1705 | int i, j; | |
2f6fc351 | 1706 | bool drain_txq; |
69081624 VT |
1707 | |
1708 | mutex_lock(&sc->mutex); | |
69081624 VT |
1709 | cancel_delayed_work_sync(&sc->tx_complete_work); |
1710 | ||
6a6b3f3e | 1711 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 1712 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
1713 | mutex_unlock(&sc->mutex); |
1714 | return; | |
1715 | } | |
1716 | ||
781b14a3 | 1717 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 1718 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
1719 | mutex_unlock(&sc->mutex); |
1720 | return; | |
1721 | } | |
1722 | ||
86271e46 | 1723 | for (j = 0; j < timeout; j++) { |
108697c4 | 1724 | bool npend = false; |
86271e46 FF |
1725 | |
1726 | if (j) | |
1727 | usleep_range(1000, 2000); | |
69081624 | 1728 | |
86271e46 FF |
1729 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
1730 | if (!ATH_TXQ_SETUP(sc, i)) | |
1731 | continue; | |
1732 | ||
108697c4 MSS |
1733 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
1734 | ||
1735 | if (npend) | |
1736 | break; | |
69081624 | 1737 | } |
86271e46 FF |
1738 | |
1739 | if (!npend) | |
9df0d6a2 | 1740 | break; |
69081624 VT |
1741 | } |
1742 | ||
9df0d6a2 FF |
1743 | if (drop) { |
1744 | ath9k_ps_wakeup(sc); | |
1745 | spin_lock_bh(&sc->sc_pcu_lock); | |
1746 | drain_txq = ath_drain_all_txq(sc, false); | |
1747 | spin_unlock_bh(&sc->sc_pcu_lock); | |
9adcf440 | 1748 | |
9df0d6a2 FF |
1749 | if (!drain_txq) |
1750 | ath_reset(sc, false); | |
9adcf440 | 1751 | |
9df0d6a2 FF |
1752 | ath9k_ps_restore(sc); |
1753 | ieee80211_wake_queues(hw); | |
1754 | } | |
d78f4b3e | 1755 | |
69081624 VT |
1756 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
1757 | mutex_unlock(&sc->mutex); | |
1758 | } | |
1759 | ||
15b91e83 VN |
1760 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
1761 | { | |
1762 | struct ath_softc *sc = hw->priv; | |
1763 | int i; | |
1764 | ||
1765 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1766 | if (!ATH_TXQ_SETUP(sc, i)) | |
1767 | continue; | |
1768 | ||
1769 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
1770 | return true; | |
1771 | } | |
1772 | return false; | |
1773 | } | |
1774 | ||
5595f119 | 1775 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
1776 | { |
1777 | struct ath_softc *sc = hw->priv; | |
1778 | struct ath_hw *ah = sc->sc_ah; | |
1779 | struct ieee80211_vif *vif; | |
1780 | struct ath_vif *avp; | |
1781 | struct ath_buf *bf; | |
1782 | struct ath_tx_status ts; | |
4286df60 | 1783 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
1784 | int status; |
1785 | ||
1786 | vif = sc->beacon.bslot[0]; | |
1787 | if (!vif) | |
1788 | return 0; | |
1789 | ||
aa45fe96 | 1790 | if (!vif->bss_conf.enable_beacon) |
ba4903f9 FF |
1791 | return 0; |
1792 | ||
aa45fe96 SM |
1793 | avp = (void *)vif->drv_priv; |
1794 | ||
4286df60 | 1795 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
1796 | tasklet_disable(&sc->bcon_tasklet); |
1797 | ||
1798 | bf = avp->av_bcbuf; | |
1799 | if (!bf || !bf->bf_mpdu) | |
1800 | goto skip; | |
1801 | ||
1802 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
1803 | if (status == -EINPROGRESS) | |
1804 | goto skip; | |
1805 | ||
1806 | sc->beacon.tx_processed = true; | |
1807 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
1808 | ||
1809 | skip: | |
1810 | tasklet_enable(&sc->bcon_tasklet); | |
1811 | } | |
1812 | ||
1813 | return sc->beacon.tx_last; | |
1814 | } | |
1815 | ||
52c94f41 MSS |
1816 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
1817 | struct ieee80211_low_level_stats *stats) | |
1818 | { | |
1819 | struct ath_softc *sc = hw->priv; | |
1820 | struct ath_hw *ah = sc->sc_ah; | |
1821 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
1822 | ||
1823 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
1824 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
1825 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
1826 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
1827 | return 0; | |
1828 | } | |
1829 | ||
43c35284 FF |
1830 | static u32 fill_chainmask(u32 cap, u32 new) |
1831 | { | |
1832 | u32 filled = 0; | |
1833 | int i; | |
1834 | ||
1835 | for (i = 0; cap && new; i++, cap >>= 1) { | |
1836 | if (!(cap & BIT(0))) | |
1837 | continue; | |
1838 | ||
1839 | if (new & BIT(0)) | |
1840 | filled |= BIT(i); | |
1841 | ||
1842 | new >>= 1; | |
1843 | } | |
1844 | ||
1845 | return filled; | |
1846 | } | |
1847 | ||
5d9c7e3c FF |
1848 | static bool validate_antenna_mask(struct ath_hw *ah, u32 val) |
1849 | { | |
1850 | switch (val & 0x7) { | |
1851 | case 0x1: | |
1852 | case 0x3: | |
1853 | case 0x7: | |
1854 | return true; | |
1855 | case 0x2: | |
1856 | return (ah->caps.rx_chainmask == 1); | |
1857 | default: | |
1858 | return false; | |
1859 | } | |
1860 | } | |
1861 | ||
43c35284 FF |
1862 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
1863 | { | |
1864 | struct ath_softc *sc = hw->priv; | |
1865 | struct ath_hw *ah = sc->sc_ah; | |
1866 | ||
5d9c7e3c FF |
1867 | if (ah->caps.rx_chainmask != 1) |
1868 | rx_ant |= tx_ant; | |
1869 | ||
1870 | if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) | |
43c35284 FF |
1871 | return -EINVAL; |
1872 | ||
1873 | sc->ant_rx = rx_ant; | |
1874 | sc->ant_tx = tx_ant; | |
1875 | ||
1876 | if (ah->caps.rx_chainmask == 1) | |
1877 | return 0; | |
1878 | ||
1879 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
1880 | if (AR_SREV_9100(ah)) | |
1881 | ah->rxchainmask = 0x7; | |
1882 | else | |
1883 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
1884 | ||
1885 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
1886 | ath9k_reload_chainmask_settings(sc); | |
1887 | ||
1888 | return 0; | |
1889 | } | |
1890 | ||
1891 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
1892 | { | |
1893 | struct ath_softc *sc = hw->priv; | |
1894 | ||
1895 | *tx_ant = sc->ant_tx; | |
1896 | *rx_ant = sc->ant_rx; | |
1897 | return 0; | |
1898 | } | |
1899 | ||
b90bd9d1 BG |
1900 | #ifdef CONFIG_ATH9K_DEBUGFS |
1901 | ||
1902 | /* Ethtool support for get-stats */ | |
1903 | ||
1904 | #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO" | |
1905 | static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = { | |
1906 | "tx_pkts_nic", | |
1907 | "tx_bytes_nic", | |
1908 | "rx_pkts_nic", | |
1909 | "rx_bytes_nic", | |
1910 | AMKSTR(d_tx_pkts), | |
1911 | AMKSTR(d_tx_bytes), | |
1912 | AMKSTR(d_tx_mpdus_queued), | |
1913 | AMKSTR(d_tx_mpdus_completed), | |
1914 | AMKSTR(d_tx_mpdu_xretries), | |
1915 | AMKSTR(d_tx_aggregates), | |
1916 | AMKSTR(d_tx_ampdus_queued_hw), | |
1917 | AMKSTR(d_tx_ampdus_queued_sw), | |
1918 | AMKSTR(d_tx_ampdus_completed), | |
1919 | AMKSTR(d_tx_ampdu_retries), | |
1920 | AMKSTR(d_tx_ampdu_xretries), | |
1921 | AMKSTR(d_tx_fifo_underrun), | |
1922 | AMKSTR(d_tx_op_exceeded), | |
1923 | AMKSTR(d_tx_timer_expiry), | |
1924 | AMKSTR(d_tx_desc_cfg_err), | |
1925 | AMKSTR(d_tx_data_underrun), | |
1926 | AMKSTR(d_tx_delim_underrun), | |
1927 | ||
1928 | "d_rx_decrypt_crc_err", | |
1929 | "d_rx_phy_err", | |
1930 | "d_rx_mic_err", | |
1931 | "d_rx_pre_delim_crc_err", | |
1932 | "d_rx_post_delim_crc_err", | |
1933 | "d_rx_decrypt_busy_err", | |
1934 | ||
1935 | "d_rx_phyerr_radar", | |
1936 | "d_rx_phyerr_ofdm_timing", | |
1937 | "d_rx_phyerr_cck_timing", | |
1938 | ||
1939 | }; | |
1940 | #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats) | |
1941 | ||
1942 | static void ath9k_get_et_strings(struct ieee80211_hw *hw, | |
1943 | struct ieee80211_vif *vif, | |
1944 | u32 sset, u8 *data) | |
1945 | { | |
1946 | if (sset == ETH_SS_STATS) | |
1947 | memcpy(data, *ath9k_gstrings_stats, | |
1948 | sizeof(ath9k_gstrings_stats)); | |
1949 | } | |
1950 | ||
1951 | static int ath9k_get_et_sset_count(struct ieee80211_hw *hw, | |
1952 | struct ieee80211_vif *vif, int sset) | |
1953 | { | |
1954 | if (sset == ETH_SS_STATS) | |
1955 | return ATH9K_SSTATS_LEN; | |
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum) | |
1960 | #define AWDATA(elem) \ | |
1961 | do { \ | |
1962 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \ | |
1963 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \ | |
1964 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \ | |
1965 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \ | |
1966 | } while (0) | |
1967 | ||
1968 | #define AWDATA_RX(elem) \ | |
1969 | do { \ | |
1970 | data[i++] = sc->debug.stats.rxstats.elem; \ | |
1971 | } while (0) | |
1972 | ||
1973 | static void ath9k_get_et_stats(struct ieee80211_hw *hw, | |
1974 | struct ieee80211_vif *vif, | |
1975 | struct ethtool_stats *stats, u64 *data) | |
1976 | { | |
1977 | struct ath_softc *sc = hw->priv; | |
1978 | int i = 0; | |
1979 | ||
1980 | data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all + | |
1981 | sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all + | |
1982 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all + | |
1983 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all); | |
1984 | data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all + | |
1985 | sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all + | |
1986 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all + | |
1987 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all); | |
1988 | AWDATA_RX(rx_pkts_all); | |
1989 | AWDATA_RX(rx_bytes_all); | |
1990 | ||
1991 | AWDATA(tx_pkts_all); | |
1992 | AWDATA(tx_bytes_all); | |
1993 | AWDATA(queued); | |
1994 | AWDATA(completed); | |
1995 | AWDATA(xretries); | |
1996 | AWDATA(a_aggr); | |
1997 | AWDATA(a_queued_hw); | |
1998 | AWDATA(a_queued_sw); | |
1999 | AWDATA(a_completed); | |
2000 | AWDATA(a_retries); | |
2001 | AWDATA(a_xretries); | |
2002 | AWDATA(fifo_underrun); | |
2003 | AWDATA(xtxop); | |
2004 | AWDATA(timer_exp); | |
2005 | AWDATA(desc_cfg_err); | |
2006 | AWDATA(data_underrun); | |
2007 | AWDATA(delim_underrun); | |
2008 | ||
2009 | AWDATA_RX(decrypt_crc_err); | |
2010 | AWDATA_RX(phy_err); | |
2011 | AWDATA_RX(mic_err); | |
2012 | AWDATA_RX(pre_delim_crc_err); | |
2013 | AWDATA_RX(post_delim_crc_err); | |
2014 | AWDATA_RX(decrypt_busy_err); | |
2015 | ||
2016 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]); | |
2017 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]); | |
2018 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]); | |
2019 | ||
2020 | WARN_ON(i != ATH9K_SSTATS_LEN); | |
2021 | } | |
2022 | ||
2023 | /* End of ethtool get-stats functions */ | |
2024 | ||
2025 | #endif | |
2026 | ||
2027 | ||
b11e640a MSS |
2028 | #ifdef CONFIG_PM_SLEEP |
2029 | ||
2030 | static void ath9k_wow_map_triggers(struct ath_softc *sc, | |
2031 | struct cfg80211_wowlan *wowlan, | |
2032 | u32 *wow_triggers) | |
2033 | { | |
2034 | if (wowlan->disconnect) | |
2035 | *wow_triggers |= AH_WOW_LINK_CHANGE | | |
2036 | AH_WOW_BEACON_MISS; | |
2037 | if (wowlan->magic_pkt) | |
2038 | *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; | |
2039 | ||
2040 | if (wowlan->n_patterns) | |
2041 | *wow_triggers |= AH_WOW_USER_PATTERN_EN; | |
2042 | ||
2043 | sc->wow_enabled = *wow_triggers; | |
2044 | ||
2045 | } | |
2046 | ||
2047 | static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) | |
2048 | { | |
2049 | struct ath_hw *ah = sc->sc_ah; | |
2050 | struct ath_common *common = ath9k_hw_common(ah); | |
2051 | struct ath9k_hw_capabilities *pcaps = &ah->caps; | |
2052 | int pattern_count = 0; | |
2053 | int i, byte_cnt; | |
2054 | u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; | |
2055 | u8 dis_deauth_mask[MAX_PATTERN_SIZE]; | |
2056 | ||
2057 | memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); | |
2058 | memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); | |
2059 | ||
2060 | /* | |
2061 | * Create Dissassociate / Deauthenticate packet filter | |
2062 | * | |
2063 | * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes | |
2064 | * +--------------+----------+---------+--------+--------+---- | |
2065 | * + Frame Control+ Duration + DA + SA + BSSID + | |
2066 | * +--------------+----------+---------+--------+--------+---- | |
2067 | * | |
2068 | * The above is the management frame format for disassociate/ | |
2069 | * deauthenticate pattern, from this we need to match the first byte | |
2070 | * of 'Frame Control' and DA, SA, and BSSID fields | |
2071 | * (skipping 2nd byte of FC and Duration feild. | |
2072 | * | |
2073 | * Disassociate pattern | |
2074 | * -------------------- | |
2075 | * Frame control = 00 00 1010 | |
2076 | * DA, SA, BSSID = x:x:x:x:x:x | |
2077 | * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x | |
2078 | * | x:x:x:x:x:x -- 22 bytes | |
2079 | * | |
2080 | * Deauthenticate pattern | |
2081 | * ---------------------- | |
2082 | * Frame control = 00 00 1100 | |
2083 | * DA, SA, BSSID = x:x:x:x:x:x | |
2084 | * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x | |
2085 | * | x:x:x:x:x:x -- 22 bytes | |
2086 | */ | |
2087 | ||
2088 | /* Create Disassociate Pattern first */ | |
2089 | ||
2090 | byte_cnt = 0; | |
2091 | ||
2092 | /* Fill out the mask with all FF's */ | |
2093 | ||
2094 | for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) | |
2095 | dis_deauth_mask[i] = 0xff; | |
2096 | ||
2097 | /* copy the first byte of frame control field */ | |
2098 | dis_deauth_pattern[byte_cnt] = 0xa0; | |
2099 | byte_cnt++; | |
2100 | ||
2101 | /* skip 2nd byte of frame control and Duration field */ | |
2102 | byte_cnt += 3; | |
2103 | ||
2104 | /* | |
2105 | * need not match the destination mac address, it can be a broadcast | |
2106 | * mac address or an unicast to this station | |
2107 | */ | |
2108 | byte_cnt += 6; | |
2109 | ||
2110 | /* copy the source mac address */ | |
2111 | memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); | |
2112 | ||
2113 | byte_cnt += 6; | |
2114 | ||
2115 | /* copy the bssid, its same as the source mac address */ | |
2116 | ||
2117 | memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); | |
2118 | ||
2119 | /* Create Disassociate pattern mask */ | |
2120 | ||
2121 | if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { | |
2122 | ||
2123 | if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { | |
2124 | /* | |
2125 | * for AR9280, because of hardware limitation, the | |
2126 | * first 4 bytes have to be matched for all patterns. | |
2127 | * the mask for disassociation and de-auth pattern | |
2128 | * matching need to enable the first 4 bytes. | |
2129 | * also the duration field needs to be filled. | |
2130 | */ | |
2131 | dis_deauth_mask[0] = 0xf0; | |
2132 | ||
2133 | /* | |
2134 | * fill in duration field | |
2135 | FIXME: what is the exact value ? | |
2136 | */ | |
2137 | dis_deauth_pattern[2] = 0xff; | |
2138 | dis_deauth_pattern[3] = 0xff; | |
2139 | } else { | |
2140 | dis_deauth_mask[0] = 0xfe; | |
2141 | } | |
2142 | ||
2143 | dis_deauth_mask[1] = 0x03; | |
2144 | dis_deauth_mask[2] = 0xc0; | |
2145 | } else { | |
2146 | dis_deauth_mask[0] = 0xef; | |
2147 | dis_deauth_mask[1] = 0x3f; | |
2148 | dis_deauth_mask[2] = 0x00; | |
2149 | dis_deauth_mask[3] = 0xfc; | |
2150 | } | |
2151 | ||
2152 | ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); | |
2153 | ||
2154 | ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, | |
2155 | pattern_count, byte_cnt); | |
2156 | ||
2157 | pattern_count++; | |
2158 | /* | |
2159 | * for de-authenticate pattern, only the first byte of the frame | |
2160 | * control field gets changed from 0xA0 to 0xC0 | |
2161 | */ | |
2162 | dis_deauth_pattern[0] = 0xC0; | |
2163 | ||
2164 | ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, | |
2165 | pattern_count, byte_cnt); | |
2166 | ||
2167 | } | |
2168 | ||
2169 | static void ath9k_wow_add_pattern(struct ath_softc *sc, | |
2170 | struct cfg80211_wowlan *wowlan) | |
2171 | { | |
2172 | struct ath_hw *ah = sc->sc_ah; | |
2173 | struct ath9k_wow_pattern *wow_pattern = NULL; | |
2174 | struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; | |
2175 | int mask_len; | |
2176 | s8 i = 0; | |
2177 | ||
2178 | if (!wowlan->n_patterns) | |
2179 | return; | |
2180 | ||
2181 | /* | |
2182 | * Add the new user configured patterns | |
2183 | */ | |
2184 | for (i = 0; i < wowlan->n_patterns; i++) { | |
2185 | ||
2186 | wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); | |
2187 | ||
2188 | if (!wow_pattern) | |
2189 | return; | |
2190 | ||
2191 | /* | |
2192 | * TODO: convert the generic user space pattern to | |
2193 | * appropriate chip specific/802.11 pattern. | |
2194 | */ | |
2195 | ||
2196 | mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); | |
2197 | memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); | |
2198 | memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); | |
2199 | memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, | |
2200 | patterns[i].pattern_len); | |
2201 | memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); | |
2202 | wow_pattern->pattern_len = patterns[i].pattern_len; | |
2203 | ||
2204 | /* | |
2205 | * just need to take care of deauth and disssoc pattern, | |
2206 | * make sure we don't overwrite them. | |
2207 | */ | |
2208 | ||
2209 | ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, | |
2210 | wow_pattern->mask_bytes, | |
2211 | i + 2, | |
2212 | wow_pattern->pattern_len); | |
2213 | kfree(wow_pattern); | |
2214 | ||
2215 | } | |
2216 | ||
2217 | } | |
2218 | ||
2219 | static int ath9k_suspend(struct ieee80211_hw *hw, | |
2220 | struct cfg80211_wowlan *wowlan) | |
2221 | { | |
2222 | struct ath_softc *sc = hw->priv; | |
2223 | struct ath_hw *ah = sc->sc_ah; | |
2224 | struct ath_common *common = ath9k_hw_common(ah); | |
2225 | u32 wow_triggers_enabled = 0; | |
2226 | int ret = 0; | |
2227 | ||
2228 | mutex_lock(&sc->mutex); | |
2229 | ||
2230 | ath_cancel_work(sc); | |
2231 | del_timer_sync(&common->ani.timer); | |
2232 | del_timer_sync(&sc->rx_poll_timer); | |
2233 | ||
2234 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { | |
2235 | ath_dbg(common, ANY, "Device not present\n"); | |
2236 | ret = -EINVAL; | |
2237 | goto fail_wow; | |
2238 | } | |
2239 | ||
2240 | if (WARN_ON(!wowlan)) { | |
2241 | ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); | |
2242 | ret = -EINVAL; | |
2243 | goto fail_wow; | |
2244 | } | |
2245 | ||
2246 | if (!device_can_wakeup(sc->dev)) { | |
2247 | ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); | |
2248 | ret = 1; | |
2249 | goto fail_wow; | |
2250 | } | |
2251 | ||
2252 | /* | |
2253 | * none of the sta vifs are associated | |
2254 | * and we are not currently handling multivif | |
2255 | * cases, for instance we have to seperately | |
2256 | * configure 'keep alive frame' for each | |
2257 | * STA. | |
2258 | */ | |
2259 | ||
2260 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
2261 | ath_dbg(common, WOW, "None of the STA vifs are associated\n"); | |
2262 | ret = 1; | |
2263 | goto fail_wow; | |
2264 | } | |
2265 | ||
2266 | if (sc->nvifs > 1) { | |
2267 | ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); | |
2268 | ret = 1; | |
2269 | goto fail_wow; | |
2270 | } | |
2271 | ||
2272 | ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); | |
2273 | ||
2274 | ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", | |
2275 | wow_triggers_enabled); | |
2276 | ||
2277 | ath9k_ps_wakeup(sc); | |
2278 | ||
2279 | ath9k_stop_btcoex(sc); | |
2280 | ||
2281 | /* | |
2282 | * Enable wake up on recieving disassoc/deauth | |
2283 | * frame by default. | |
2284 | */ | |
2285 | ath9k_wow_add_disassoc_deauth_pattern(sc); | |
2286 | ||
2287 | if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) | |
2288 | ath9k_wow_add_pattern(sc, wowlan); | |
2289 | ||
2290 | spin_lock_bh(&sc->sc_pcu_lock); | |
2291 | /* | |
2292 | * To avoid false wake, we enable beacon miss interrupt only | |
2293 | * when we go to sleep. We save the current interrupt mask | |
2294 | * so we can restore it after the system wakes up | |
2295 | */ | |
2296 | sc->wow_intr_before_sleep = ah->imask; | |
2297 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
2298 | ath9k_hw_disable_interrupts(ah); | |
2299 | ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; | |
2300 | ath9k_hw_set_interrupts(ah); | |
2301 | ath9k_hw_enable_interrupts(ah); | |
2302 | ||
2303 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2304 | ||
2305 | /* | |
2306 | * we can now sync irq and kill any running tasklets, since we already | |
2307 | * disabled interrupts and not holding a spin lock | |
2308 | */ | |
2309 | synchronize_irq(sc->irq); | |
2310 | tasklet_kill(&sc->intr_tq); | |
2311 | ||
2312 | ath9k_hw_wow_enable(ah, wow_triggers_enabled); | |
2313 | ||
2314 | ath9k_ps_restore(sc); | |
2315 | ath_dbg(common, ANY, "WoW enabled in ath9k\n"); | |
2316 | atomic_inc(&sc->wow_sleep_proc_intr); | |
2317 | ||
2318 | fail_wow: | |
2319 | mutex_unlock(&sc->mutex); | |
2320 | return ret; | |
2321 | } | |
2322 | ||
2323 | static int ath9k_resume(struct ieee80211_hw *hw) | |
2324 | { | |
2325 | struct ath_softc *sc = hw->priv; | |
2326 | struct ath_hw *ah = sc->sc_ah; | |
2327 | struct ath_common *common = ath9k_hw_common(ah); | |
2328 | u32 wow_status; | |
2329 | ||
2330 | mutex_lock(&sc->mutex); | |
2331 | ||
2332 | ath9k_ps_wakeup(sc); | |
2333 | ||
2334 | spin_lock_bh(&sc->sc_pcu_lock); | |
2335 | ||
2336 | ath9k_hw_disable_interrupts(ah); | |
2337 | ah->imask = sc->wow_intr_before_sleep; | |
2338 | ath9k_hw_set_interrupts(ah); | |
2339 | ath9k_hw_enable_interrupts(ah); | |
2340 | ||
2341 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2342 | ||
2343 | wow_status = ath9k_hw_wow_wakeup(ah); | |
2344 | ||
2345 | if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { | |
2346 | /* | |
2347 | * some devices may not pick beacon miss | |
2348 | * as the reason they woke up so we add | |
2349 | * that here for that shortcoming. | |
2350 | */ | |
2351 | wow_status |= AH_WOW_BEACON_MISS; | |
2352 | atomic_dec(&sc->wow_got_bmiss_intr); | |
2353 | ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); | |
2354 | } | |
2355 | ||
2356 | atomic_dec(&sc->wow_sleep_proc_intr); | |
2357 | ||
2358 | if (wow_status) { | |
2359 | ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", | |
2360 | ath9k_hw_wow_event_to_string(wow_status), wow_status); | |
2361 | } | |
2362 | ||
2363 | ath_restart_work(sc); | |
2364 | ath9k_start_btcoex(sc); | |
2365 | ||
2366 | ath9k_ps_restore(sc); | |
2367 | mutex_unlock(&sc->mutex); | |
2368 | ||
2369 | return 0; | |
2370 | } | |
2371 | ||
2372 | static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) | |
2373 | { | |
2374 | struct ath_softc *sc = hw->priv; | |
2375 | ||
2376 | mutex_lock(&sc->mutex); | |
2377 | device_init_wakeup(sc->dev, 1); | |
2378 | device_set_wakeup_enable(sc->dev, enabled); | |
2379 | mutex_unlock(&sc->mutex); | |
2380 | } | |
2381 | ||
2382 | #endif | |
2383 | ||
6baff7f9 | 2384 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2385 | .tx = ath9k_tx, |
2386 | .start = ath9k_start, | |
2387 | .stop = ath9k_stop, | |
2388 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2389 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2390 | .remove_interface = ath9k_remove_interface, |
2391 | .config = ath9k_config, | |
8feceb67 | 2392 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2393 | .sta_add = ath9k_sta_add, |
2394 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2395 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2396 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2397 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2398 | .set_key = ath9k_set_key, |
8feceb67 | 2399 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2400 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2401 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2402 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2403 | .get_survey = ath9k_get_survey, |
3b319aae | 2404 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2405 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2406 | .flush = ath9k_flush, |
15b91e83 | 2407 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 MSS |
2408 | .tx_last_beacon = ath9k_tx_last_beacon, |
2409 | .get_stats = ath9k_get_stats, | |
43c35284 FF |
2410 | .set_antenna = ath9k_set_antenna, |
2411 | .get_antenna = ath9k_get_antenna, | |
b90bd9d1 | 2412 | |
b11e640a MSS |
2413 | #ifdef CONFIG_PM_SLEEP |
2414 | .suspend = ath9k_suspend, | |
2415 | .resume = ath9k_resume, | |
2416 | .set_wakeup = ath9k_set_wakeup, | |
2417 | #endif | |
2418 | ||
b90bd9d1 BG |
2419 | #ifdef CONFIG_ATH9K_DEBUGFS |
2420 | .get_et_sset_count = ath9k_get_et_sset_count, | |
2421 | .get_et_stats = ath9k_get_et_stats, | |
2422 | .get_et_strings = ath9k_get_et_strings, | |
2423 | #endif | |
8feceb67 | 2424 | }; |