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cfg80211: allow wext to remove keys that don't exist
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
4f0fc7c3 192 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
0e2dedf9
JM		 239int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
ff37e337 241{
cbe61d8a 242 struct ath_hw *ah = sc->sc_ah;
ff37e337 243 bool fastcc = true, stopped;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
6b45784f 283 "reset status %d\n",
c0d7c7af
LR		 284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
c0d7c7af
LR		 290 sc->sc_flags &= ~SC_OP_FULL_RESET;
291
292 if (ath_startrecv(sc) != 0) {
293 DPRINTF(sc, ATH_DBG_FATAL,
294 "Unable to restart recv logic\n");
295 return -EIO;
296 }
297
298 ath_cache_conf_rate(sc, &hw->conf);
299 ath_update_txpow(sc);
17d7904d 300 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 301 ath9k_ps_restore(sc);
ff37e337
S		 302 return 0;
303}
304
305/*
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
311 */
312static void ath_ani_calibrate(unsigned long data)
313{
20977d3e
S		 314 struct ath_softc *sc = (struct ath_softc *)data;
315 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 316 bool longcal = false;
317 bool shortcal = false;
318 bool aniflag = false;
319 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 320 u32 cal_interval, short_cal_interval;
ff37e337 321
20977d3e
S		 322 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 324
325 /*
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
328 */
0c98de65 329 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 330 goto set_timer;
ff37e337
S		 331
332 /* Long calibration runs independently of short calibration. */
17d7904d 333 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 334 longcal = true;
04bd4638 335 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 336 sc->ani.longcal_timer = timestamp;
ff37e337
S		 337 }
338
17d7904d
S		 339 /* Short calibration applies only while caldone is false */
340 if (!sc->ani.caldone) {
20977d3e 341 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 342 shortcal = true;
04bd4638 343 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 344 sc->ani.shortcal_timer = timestamp;
345 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 346 }
347 } else {
17d7904d 348 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 349 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 350 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
351 if (sc->ani.caldone)
352 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 353 }
354 }
355
356 /* Verify whether we must check ANI */
20977d3e 357 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 358 aniflag = true;
17d7904d 359 sc->ani.checkani_timer = timestamp;
ff37e337
S		 360 }
361
362 /* Skip all processing if there's nothing to do. */
363 if (longcal || shortcal || aniflag) {
364 /* Call ANI routine if necessary */
365 if (aniflag)
20977d3e 366 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 367
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
379f0440
S		 370 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
371 sc->rx_chainmask, longcal);
372
373 if (longcal)
374 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
375 ah->curchan);
376
377 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
378 ah->curchan->channel, ah->curchan->channelFlags,
379 sc->ani.noise_floor);
ff37e337
S		 380 }
381 }
382
20977d3e 383set_timer:
ff37e337
S		 384 /*
385 * Set timer interval based on previous results.
386 * The interval must be the shortest necessary to satisfy ANI,
387 * short calibration and long calibration.
388 */
aac9207e 389 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 390 if (sc->sc_ah->config.enable_ani)
aac9207e 391 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 392 if (!sc->ani.caldone)
20977d3e 393 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 394
17d7904d 395 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 396}
397
415f738e
S		 398static void ath_start_ani(struct ath_softc *sc)
399{
400 unsigned long timestamp = jiffies_to_msecs(jiffies);
401
402 sc->ani.longcal_timer = timestamp;
403 sc->ani.shortcal_timer = timestamp;
404 sc->ani.checkani_timer = timestamp;
405
406 mod_timer(&sc->ani.timer,
407 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
408}
409
ff37e337
S		 410/*
411 * Update tx/rx chainmask. For legacy association,
412 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 413 * the chainmask configuration, for bt coexistence, use
414 * the chainmask configuration even in legacy mode.
ff37e337 415 */
0e2dedf9 416void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 417{
c97c92d9 418 if (is_ht ||
2660b81a
S		 419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 422 } else {
17d7904d
S		 423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
ff37e337
S		 425 }
426
04bd4638 427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 428 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 429}
430
431static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432{
433 struct ath_node *an;
434
435 an = (struct ath_node *)sta->drv_priv;
436
87792efc 437 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 438 ath_tx_node_init(sc, an);
87792efc
S		 439 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
440 sta->ht_cap.ampdu_factor);
441 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
442 }
ff37e337
S		 443}
444
445static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446{
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
451}
452
453static void ath9k_tasklet(unsigned long data)
454{
455 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 456 u32 status = sc->intrstatus;
ff37e337
S		 457
458 if (status & ATH9K_INT_FATAL) {
ff37e337
S		 459 ath_reset(sc, false);
460 return;
063d8be3 461 }
ff37e337 462
063d8be3
S		 463 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
464 spin_lock_bh(&sc->rx.rxflushlock);
465 ath_rx_tasklet(sc, 0);
466 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 467 }
468
063d8be3
S		 469 if (status & ATH9K_INT_TX)
470 ath_tx_tasklet(sc);
471
ff37e337 472 /* re-enable hardware interrupt */
17d7904d 473 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 474}
475
6baff7f9 476irqreturn_t ath_isr(int irq, void *dev)
ff37e337 477{
063d8be3
S		 478#define SCHED_INTR ( \
479 ATH9K_INT_FATAL | \
480 ATH9K_INT_RXORN | \
481 ATH9K_INT_RXEOL | \
482 ATH9K_INT_RX | \
483 ATH9K_INT_TX | \
484 ATH9K_INT_BMISS | \
485 ATH9K_INT_CST | \
486 ATH9K_INT_TSFOOR)
487
ff37e337 488 struct ath_softc *sc = dev;
cbe61d8a 489 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 490 enum ath9k_int status;
491 bool sched = false;
492
063d8be3
S		 493 /*
494 * The hardware is not ready/present, don't
495 * touch anything. Note this can happen early
496 * on if the IRQ is shared.
497 */
498 if (sc->sc_flags & SC_OP_INVALID)
499 return IRQ_NONE;
ff37e337 500
063d8be3
S		 501 ath9k_ps_wakeup(sc);
502
503 /* shared irq, not for us */
504
505 if (!ath9k_hw_intrpend(ah)) {
506 ath9k_ps_restore(sc);
507 return IRQ_NONE;
508 }
509
510 /*
511 * Figure out the reason(s) for the interrupt. Note
512 * that the hal returns a pseudo-ISR that may include
513 * bits we haven't explicitly enabled so we mask the
514 * value to insure we only process bits we requested.
515 */
516 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
517 status &= sc->imask; /* discard unasked-for bits */
ff37e337 518
063d8be3
S		 519 /*
520 * If there are no status bits set, then this interrupt was not
521 * for me (should have been caught above).
522 */
523 if (!status) {
524 ath9k_ps_restore(sc);
525 return IRQ_NONE;
526 }
ff37e337 527
063d8be3
S		 528 /* Cache the status */
529 sc->intrstatus = status;
530
531 if (status & SCHED_INTR)
532 sched = true;
533
534 /*
535 * If a FATAL or RXORN interrupt is received, we have to reset the
536 * chip immediately.
537 */
538 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
539 goto chip_reset;
540
541 if (status & ATH9K_INT_SWBA)
542 tasklet_schedule(&sc->bcon_tasklet);
543
544 if (status & ATH9K_INT_TXURN)
545 ath9k_hw_updatetxtriglevel(ah, true);
546
547 if (status & ATH9K_INT_MIB) {
ff37e337 548 /*
063d8be3
S		 549 * Disable interrupts until we service the MIB
550 * interrupt; otherwise it will continue to
551 * fire.
ff37e337 552 */
063d8be3
S		 553 ath9k_hw_set_interrupts(ah, 0);
554 /*
555 * Let the hal handle the event. We assume
556 * it will clear whatever condition caused
557 * the interrupt.
558 */
559 ath9k_hw_procmibevent(ah, &sc->nodestats);
560 ath9k_hw_set_interrupts(ah, sc->imask);
561 }
ff37e337 562
063d8be3
S		 563 if (status & ATH9K_INT_TIM_TIMER) {
564 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
565 /* Clear RxAbort bit so that we can
566 * receive frames */
567 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
568 ath9k_hw_setrxabort(ah, 0);
ff37e337 569 sched = true;
063d8be3 570 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 571 }
063d8be3
S		 572 }
573
574chip_reset:
ff37e337 575
063d8be3 576 ath9k_ps_restore(sc);
817e11de
S		 577 ath_debug_stat_interrupt(sc, status);
578
ff37e337
S		 579 if (sched) {
580 /* turn off every interrupt except SWBA */
17d7904d 581 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 582 tasklet_schedule(&sc->intr_tq);
583 }
584
585 return IRQ_HANDLED;
063d8be3
S		 586
587#undef SCHED_INTR
ff37e337
S		 588}
589
f078f209 590static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 591 struct ieee80211_channel *chan,
094d05dc 592 enum nl80211_channel_type channel_type)
f078f209
LR		 593{
594 u32 chanmode = 0;
f078f209
LR		 595
596 switch (chan->band) {
597 case IEEE80211_BAND_2GHZ:
094d05dc
S		 598 switch(channel_type) {
599 case NL80211_CHAN_NO_HT:
600 case NL80211_CHAN_HT20:
f078f209 601 chanmode = CHANNEL_G_HT20;
094d05dc
S		 602 break;
603 case NL80211_CHAN_HT40PLUS:
f078f209 604 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 605 break;
606 case NL80211_CHAN_HT40MINUS:
f078f209 607 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 608 break;
609 }
f078f209
LR		 610 break;
611 case IEEE80211_BAND_5GHZ:
094d05dc
S		 612 switch(channel_type) {
613 case NL80211_CHAN_NO_HT:
614 case NL80211_CHAN_HT20:
f078f209 615 chanmode = CHANNEL_A_HT20;
094d05dc
S		 616 break;
617 case NL80211_CHAN_HT40PLUS:
f078f209 618 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 619 break;
620 case NL80211_CHAN_HT40MINUS:
f078f209 621 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 622 break;
623 }
f078f209
LR		 624 break;
625 default:
626 break;
627 }
628
629 return chanmode;
630}
631
6ace2891 632static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 633 struct ath9k_keyval *hk, const u8 *addr,
634 bool authenticator)
f078f209 635{
6ace2891
JM		 636 const u8 *key_rxmic;
637 const u8 *key_txmic;
f078f209 638
6ace2891
JM		 639 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
640 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 641
642 if (addr == NULL) {
d216aaa6
JM		 643 /*
644 * Group key installation - only two key cache entries are used
645 * regardless of splitmic capability since group key is only
646 * used either for TX or RX.
647 */
3f53dd64
JM		 648 if (authenticator) {
649 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
650 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
651 } else {
652 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
653 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
654 }
d216aaa6 655 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 656 }
17d7904d 657 if (!sc->splitmic) {
d216aaa6 658 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 659 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
660 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 661 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 662 }
d216aaa6
JM		 663
664 /* Separate key cache entries for TX and RX */
665
666 /* TX key goes at first index, RX key at +32. */
f078f209 667 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 668 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
669 /* TX MIC entry failed. No need to proceed further */
d8baa939 670 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 671 "Setting TX MIC Key Failed\n");
f078f209
LR		 672 return 0;
673 }
674
675 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
676 /* XXX delete tx key on failure? */
d216aaa6 677 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 678}
679
680static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
681{
682 int i;
683
17d7904d
S		 684 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
685 if (test_bit(i, sc->keymap) ||
686 test_bit(i + 64, sc->keymap))
6ace2891 687 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 688 if (sc->splitmic &&
689 (test_bit(i + 32, sc->keymap) ||
690 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 691 continue; /* At least one part of TKIP key allocated */
692
693 /* Found a free slot for a TKIP key */
694 return i;
695 }
696 return -1;
697}
698
699static int ath_reserve_key_cache_slot(struct ath_softc *sc)
700{
701 int i;
702
703 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 704 if (sc->splitmic) {
705 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
706 if (!test_bit(i, sc->keymap) &&
707 (test_bit(i + 32, sc->keymap) ||
708 test_bit(i + 64, sc->keymap) ||
709 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 710 return i;
17d7904d
S		 711 if (!test_bit(i + 32, sc->keymap) &&
712 (test_bit(i, sc->keymap) ||
713 test_bit(i + 64, sc->keymap) ||
714 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 715 return i + 32;
17d7904d
S		 716 if (!test_bit(i + 64, sc->keymap) &&
717 (test_bit(i , sc->keymap) ||
718 test_bit(i + 32, sc->keymap) ||
719 test_bit(i + 64 + 32, sc->keymap)))
ea612132 720 return i + 64;
17d7904d
S		 721 if (!test_bit(i + 64 + 32, sc->keymap) &&
722 (test_bit(i, sc->keymap) ||
723 test_bit(i + 32, sc->keymap) ||
724 test_bit(i + 64, sc->keymap)))
ea612132 725 return i + 64 + 32;
6ace2891
JM		 726 }
727 } else {
17d7904d
S		 728 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
729 if (!test_bit(i, sc->keymap) &&
730 test_bit(i + 64, sc->keymap))
6ace2891 731 return i;
17d7904d
S		 732 if (test_bit(i, sc->keymap) &&
733 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 734 return i + 64;
735 }
736 }
737
738 /* No partially used TKIP slots, pick any available slot */
17d7904d 739 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 740 /* Do not allow slots that could be needed for TKIP group keys
741 * to be used. This limitation could be removed if we know that
742 * TKIP will not be used. */
743 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
744 continue;
17d7904d 745 if (sc->splitmic) {
be2864cf
JM		 746 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
747 continue;
748 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
749 continue;
750 }
751
17d7904d 752 if (!test_bit(i, sc->keymap))
6ace2891
JM		 753 return i; /* Found a free slot for a key */
754 }
755
756 /* No free slot found */
757 return -1;
f078f209
LR		 758}
759
760static int ath_key_config(struct ath_softc *sc,
3f53dd64 761 struct ieee80211_vif *vif,
dc822b5d 762 struct ieee80211_sta *sta,
f078f209
LR		 763 struct ieee80211_key_conf *key)
764{
f078f209
LR		 765 struct ath9k_keyval hk;
766 const u8 *mac = NULL;
767 int ret = 0;
6ace2891 768 int idx;
f078f209
LR		 769
770 memset(&hk, 0, sizeof(hk));
771
772 switch (key->alg) {
773 case ALG_WEP:
774 hk.kv_type = ATH9K_CIPHER_WEP;
775 break;
776 case ALG_TKIP:
777 hk.kv_type = ATH9K_CIPHER_TKIP;
778 break;
779 case ALG_CCMP:
780 hk.kv_type = ATH9K_CIPHER_AES_CCM;
781 break;
782 default:
ca470b29 783 return -EOPNOTSUPP;
f078f209
LR		 784 }
785
6ace2891 786 hk.kv_len = key->keylen;
f078f209
LR		 787 memcpy(hk.kv_val, key->key, key->keylen);
788
6ace2891
JM		 789 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
790 /* For now, use the default keys for broadcast keys. This may
791 * need to change with virtual interfaces. */
792 idx = key->keyidx;
793 } else if (key->keyidx) {
dc822b5d
JB		 794 if (WARN_ON(!sta))
795 return -EOPNOTSUPP;
796 mac = sta->addr;
797
6ace2891
JM		 798 if (vif->type != NL80211_IFTYPE_AP) {
799 /* Only keyidx 0 should be used with unicast key, but
800 * allow this for client mode for now. */
801 idx = key->keyidx;
802 } else
803 return -EIO;
f078f209 804 } else {
dc822b5d
JB		 805 if (WARN_ON(!sta))
806 return -EOPNOTSUPP;
807 mac = sta->addr;
808
6ace2891
JM		 809 if (key->alg == ALG_TKIP)
810 idx = ath_reserve_key_cache_slot_tkip(sc);
811 else
812 idx = ath_reserve_key_cache_slot(sc);
813 if (idx < 0)
ca470b29 814 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 815 }
816
817 if (key->alg == ALG_TKIP)
3f53dd64
JM		 818 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
819 vif->type == NL80211_IFTYPE_AP);
f078f209 820 else
d216aaa6 821 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 822
823 if (!ret)
824 return -EIO;
825
17d7904d 826 set_bit(idx, sc->keymap);
6ace2891 827 if (key->alg == ALG_TKIP) {
17d7904d
S		 828 set_bit(idx + 64, sc->keymap);
829 if (sc->splitmic) {
830 set_bit(idx + 32, sc->keymap);
831 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 832 }
833 }
834
835 return idx;
f078f209
LR		 836}
837
838static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
839{
6ace2891
JM		 840 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
841 if (key->hw_key_idx < IEEE80211_WEP_NKID)
842 return;
843
17d7904d 844 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 845 if (key->alg != ALG_TKIP)
846 return;
f078f209 847
17d7904d
S		 848 clear_bit(key->hw_key_idx + 64, sc->keymap);
849 if (sc->splitmic) {
850 clear_bit(key->hw_key_idx + 32, sc->keymap);
851 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 852 }
f078f209
LR		 853}
854
eb2599ca
S		 855static void setup_ht_cap(struct ath_softc *sc,
856 struct ieee80211_sta_ht_cap *ht_info)
f078f209 857{
60653678
S		 858#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
859#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 860
d9fe60de
JB		 861 ht_info->ht_supported = true;
862 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
863 IEEE80211_HT_CAP_SM_PS |
864 IEEE80211_HT_CAP_SGI_40 |
865 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 866
60653678
S		 867 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
868 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 869
d9fe60de
JB		 870 /* set up supported mcs set */
871 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 872
17d7904d 873 switch(sc->rx_chainmask) {
eb2599ca
S		 874 case 1:
875 ht_info->mcs.rx_mask[0] = 0xff;
876 break;
3c457265 877 case 3:
eb2599ca
S		 878 case 5:
879 case 7:
880 default:
881 ht_info->mcs.rx_mask[0] = 0xff;
882 ht_info->mcs.rx_mask[1] = 0xff;
883 break;
884 }
885
d9fe60de 886 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 887}
888
8feceb67 889static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 890 struct ieee80211_vif *vif,
8feceb67 891 struct ieee80211_bss_conf *bss_conf)
f078f209 892{
17d7904d 893 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 894
8feceb67 895 if (bss_conf->assoc) {
094d05dc 896 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 897 bss_conf->aid, sc->curbssid);
f078f209 898
8feceb67 899 /* New association, store aid */
d97809db 900 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 901 sc->curaid = bss_conf->aid;
ba52da58 902 ath9k_hw_write_associd(sc);
8feceb67 903 }
f078f209 904
8feceb67 905 /* Configure the beacon */
2c3db3d5 906 ath_beacon_config(sc, vif);
f078f209 907
8feceb67 908 /* Reset rssi stats */
17d7904d
S		 909 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
910 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
911 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
912 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 913
415f738e 914 ath_start_ani(sc);
8feceb67 915 } else {
1ffb0610 916 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 917 sc->curaid = 0;
f078f209 918 }
8feceb67 919}
f078f209 920
8feceb67
VT		 921/********************************/
922/* LED functions */
923/********************************/
f078f209 924
f2bffa7e
VT		 925static void ath_led_blink_work(struct work_struct *work)
926{
927 struct ath_softc *sc = container_of(work, struct ath_softc,
928 ath_led_blink_work.work);
929
930 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
931 return;
85067c06
VT		 932
933 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
934 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
935 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
936 else
937 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
938 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 939
940 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
941 (sc->sc_flags & SC_OP_LED_ON) ?
942 msecs_to_jiffies(sc->led_off_duration) :
943 msecs_to_jiffies(sc->led_on_duration));
944
85067c06
VT		 945 sc->led_on_duration = sc->led_on_cnt ?
946 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
947 ATH_LED_ON_DURATION_IDLE;
948 sc->led_off_duration = sc->led_off_cnt ?
949 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
950 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 951 sc->led_on_cnt = sc->led_off_cnt = 0;
952 if (sc->sc_flags & SC_OP_LED_ON)
953 sc->sc_flags &= ~SC_OP_LED_ON;
954 else
955 sc->sc_flags |= SC_OP_LED_ON;
956}
957
8feceb67
VT		 958static void ath_led_brightness(struct led_classdev *led_cdev,
959 enum led_brightness brightness)
960{
961 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
962 struct ath_softc *sc = led->sc;
f078f209 963
8feceb67
VT		 964 switch (brightness) {
965 case LED_OFF:
966 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 967 led->led_type == ATH_LED_RADIO) {
968 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
969 (led->led_type == ATH_LED_RADIO));
8feceb67 970 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 971 if (led->led_type == ATH_LED_RADIO)
972 sc->sc_flags &= ~SC_OP_LED_ON;
973 } else {
974 sc->led_off_cnt++;
975 }
8feceb67
VT		 976 break;
977 case LED_FULL:
f2bffa7e 978 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 979 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 980 queue_delayed_work(sc->hw->workqueue,
981 &sc->ath_led_blink_work, 0);
982 } else if (led->led_type == ATH_LED_RADIO) {
983 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
984 sc->sc_flags |= SC_OP_LED_ON;
985 } else {
986 sc->led_on_cnt++;
987 }
8feceb67
VT		 988 break;
989 default:
990 break;
f078f209 991 }
8feceb67 992}
f078f209 993
8feceb67
VT		 994static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
995 char *trigger)
996{
997 int ret;
f078f209 998
8feceb67
VT		 999 led->sc = sc;
1000 led->led_cdev.name = led->name;
1001 led->led_cdev.default_trigger = trigger;
1002 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1003
8feceb67
VT		 1004 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1005 if (ret)
1006 DPRINTF(sc, ATH_DBG_FATAL,
1007 "Failed to register led:%s", led->name);
1008 else
1009 led->registered = 1;
1010 return ret;
1011}
f078f209 1012
8feceb67
VT		 1013static void ath_unregister_led(struct ath_led *led)
1014{
1015 if (led->registered) {
1016 led_classdev_unregister(&led->led_cdev);
1017 led->registered = 0;
f078f209 1018 }
f078f209
LR		 1019}
1020
8feceb67 1021static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1022{
f2bffa7e 1023 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1024 ath_unregister_led(&sc->assoc_led);
1025 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1026 ath_unregister_led(&sc->tx_led);
1027 ath_unregister_led(&sc->rx_led);
1028 ath_unregister_led(&sc->radio_led);
1029 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1030}
f078f209 1031
8feceb67
VT		 1032static void ath_init_leds(struct ath_softc *sc)
1033{
1034 char *trigger;
1035 int ret;
f078f209 1036
8feceb67
VT		 1037 /* Configure gpio 1 for output */
1038 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1039 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1040 /* LED off, active low */
1041 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1042
f2bffa7e
VT		 1043 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1044
8feceb67
VT		 1045 trigger = ieee80211_get_radio_led_name(sc->hw);
1046 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1047 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1048 ret = ath_register_led(sc, &sc->radio_led, trigger);
1049 sc->radio_led.led_type = ATH_LED_RADIO;
1050 if (ret)
1051 goto fail;
7dcfdcd9 1052
8feceb67
VT		 1053 trigger = ieee80211_get_assoc_led_name(sc->hw);
1054 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1055 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1056 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1057 sc->assoc_led.led_type = ATH_LED_ASSOC;
1058 if (ret)
1059 goto fail;
f078f209 1060
8feceb67
VT		 1061 trigger = ieee80211_get_tx_led_name(sc->hw);
1062 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1063 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1064 ret = ath_register_led(sc, &sc->tx_led, trigger);
1065 sc->tx_led.led_type = ATH_LED_TX;
1066 if (ret)
1067 goto fail;
f078f209 1068
8feceb67
VT		 1069 trigger = ieee80211_get_rx_led_name(sc->hw);
1070 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1071 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1072 ret = ath_register_led(sc, &sc->rx_led, trigger);
1073 sc->rx_led.led_type = ATH_LED_RX;
1074 if (ret)
1075 goto fail;
f078f209 1076
8feceb67
VT		 1077 return;
1078
1079fail:
1080 ath_deinit_leds(sc);
f078f209
LR		 1081}
1082
7ec3e514 1083void ath_radio_enable(struct ath_softc *sc)
500c064d 1084{
cbe61d8a 1085 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1086 struct ieee80211_channel *channel = sc->hw->conf.channel;
1087 int r;
500c064d 1088
3cbb5dd7 1089 ath9k_ps_wakeup(sc);
d2f5b3a6 1090 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1091
d2f5b3a6 1092 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1093 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1094 if (r) {
500c064d 1095 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1096 "Unable to reset channel %u (%uMhz) ",
6b45784f 1097 "reset status %d\n",
ae8d2858 1098 channel->center_freq, r);
500c064d
VT		 1099 }
1100 spin_unlock_bh(&sc->sc_resetlock);
1101
1102 ath_update_txpow(sc);
1103 if (ath_startrecv(sc) != 0) {
1104 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1105 "Unable to restart recv logic\n");
500c064d
VT		 1106 return;
1107 }
1108
1109 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1110 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1111
1112 /* Re-Enable interrupts */
17d7904d 1113 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1114
1115 /* Enable LED */
1116 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1117 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1118 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1119
1120 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1121 ath9k_ps_restore(sc);
500c064d
VT		 1122}
1123
7ec3e514 1124void ath_radio_disable(struct ath_softc *sc)
500c064d 1125{
cbe61d8a 1126 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1127 struct ieee80211_channel *channel = sc->hw->conf.channel;
1128 int r;
500c064d 1129
3cbb5dd7 1130 ath9k_ps_wakeup(sc);
500c064d
VT		 1131 ieee80211_stop_queues(sc->hw);
1132
1133 /* Disable LED */
1134 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1135 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1136
1137 /* Disable interrupts */
1138 ath9k_hw_set_interrupts(ah, 0);
1139
043a0405 1140 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1141 ath_stoprecv(sc); /* turn off frame recv */
1142 ath_flushrecv(sc); /* flush recv queue */
1143
1144 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1145 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1146 if (r) {
500c064d 1147 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1148 "Unable to reset channel %u (%uMhz) "
6b45784f 1149 "reset status %d\n",
ae8d2858 1150 channel->center_freq, r);
500c064d
VT		 1151 }
1152 spin_unlock_bh(&sc->sc_resetlock);
1153
1154 ath9k_hw_phy_disable(ah);
d2f5b3a6 1155 ath9k_hw_configpcipowersave(ah, 1);
500c064d 1156 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1157 ath9k_ps_restore(sc);
500c064d
VT		 1158}
1159
5077fd35
GJ		 1160#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1161
1162/*******************/
1163/* Rfkill */
1164/*******************/
1165
500c064d
VT		 1166static bool ath_is_rfkill_set(struct ath_softc *sc)
1167{
cbe61d8a 1168 struct ath_hw *ah = sc->sc_ah;
500c064d 1169
2660b81a
S		 1170 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1171 ah->rfkill_polarity;
500c064d
VT		 1172}
1173
1174/* h/w rfkill poll function */
1175static void ath_rfkill_poll(struct work_struct *work)
1176{
1177 struct ath_softc *sc = container_of(work, struct ath_softc,
1178 rf_kill.rfkill_poll.work);
1179 bool radio_on;
1180
1181 if (sc->sc_flags & SC_OP_INVALID)
1182 return;
1183
1184 radio_on = !ath_is_rfkill_set(sc);
1185
1186 /*
1187 * enable/disable radio only when there is a
1188 * state change in RF switch
1189 */
1190 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1191 enum rfkill_state state;
1192
1193 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1194 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1195 : RFKILL_STATE_HARD_BLOCKED;
1196 } else if (radio_on) {
1197 ath_radio_enable(sc);
1198 state = RFKILL_STATE_UNBLOCKED;
1199 } else {
1200 ath_radio_disable(sc);
1201 state = RFKILL_STATE_HARD_BLOCKED;
1202 }
1203
1204 if (state == RFKILL_STATE_HARD_BLOCKED)
1205 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1206 else
1207 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1208
1209 rfkill_force_state(sc->rf_kill.rfkill, state);
1210 }
1211
1212 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1213 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1214}
1215
1216/* s/w rfkill handler */
1217static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1218{
1219 struct ath_softc *sc = data;
1220
1221 switch (state) {
1222 case RFKILL_STATE_SOFT_BLOCKED:
1223 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1224 SC_OP_RFKILL_SW_BLOCKED)))
1225 ath_radio_disable(sc);
1226 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1227 return 0;
1228 case RFKILL_STATE_UNBLOCKED:
1229 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1230 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1231 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1232 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1233 "radio as it is disabled by h/w\n");
500c064d
VT		 1234 return -EPERM;
1235 }
1236 ath_radio_enable(sc);
1237 }
1238 return 0;
1239 default:
1240 return -EINVAL;
1241 }
1242}
1243
1244/* Init s/w rfkill */
1245static int ath_init_sw_rfkill(struct ath_softc *sc)
1246{
1247 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1248 RFKILL_TYPE_WLAN);
1249 if (!sc->rf_kill.rfkill) {
1250 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1251 return -ENOMEM;
1252 }
1253
1254 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1255 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1256 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1257 sc->rf_kill.rfkill->data = sc;
1258 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1259 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
500c064d
VT		 1260
1261 return 0;
1262}
1263
1264/* Deinitialize rfkill */
1265static void ath_deinit_rfkill(struct ath_softc *sc)
1266{
2660b81a 1267 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1268 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1269
1270 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1271 rfkill_unregister(sc->rf_kill.rfkill);
1272 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1273 sc->rf_kill.rfkill = NULL;
1274 }
1275}
9c84b797
S		 1276
1277static int ath_start_rfkill_poll(struct ath_softc *sc)
1278{
2660b81a 1279 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1280 queue_delayed_work(sc->hw->workqueue,
1281 &sc->rf_kill.rfkill_poll, 0);
1282
1283 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1284 if (rfkill_register(sc->rf_kill.rfkill)) {
1285 DPRINTF(sc, ATH_DBG_FATAL,
1286 "Unable to register rfkill\n");
1287 rfkill_free(sc->rf_kill.rfkill);
1288
1289 /* Deinitialize the device */
39c3c2f2 1290 ath_cleanup(sc);
9c84b797
S		 1291 return -EIO;
1292 } else {
1293 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1294 }
1295 }
1296
1297 return 0;
1298}
500c064d
VT		 1299#endif /* CONFIG_RFKILL */
1300
6baff7f9 1301void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1302{
1303 ath_detach(sc);
1304 free_irq(sc->irq, sc);
1305 ath_bus_cleanup(sc);
c52f33d0 1306 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1307 ieee80211_free_hw(sc->hw);
1308}
1309
6baff7f9 1310void ath_detach(struct ath_softc *sc)
f078f209 1311{
8feceb67 1312 struct ieee80211_hw *hw = sc->hw;
9c84b797 1313 int i = 0;
f078f209 1314
3cbb5dd7
VN		 1315 ath9k_ps_wakeup(sc);
1316
04bd4638 1317 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1318
e97275cb 1319#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1320 ath_deinit_rfkill(sc);
1321#endif
3fcdfb4b 1322 ath_deinit_leds(sc);
0e2dedf9 1323 cancel_work_sync(&sc->chan_work);
f98c3bd2 1324 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1325
c52f33d0
JM		 1326 for (i = 0; i < sc->num_sec_wiphy; i++) {
1327 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1328 if (aphy == NULL)
1329 continue;
1330 sc->sec_wiphy[i] = NULL;
1331 ieee80211_unregister_hw(aphy->hw);
1332 ieee80211_free_hw(aphy->hw);
1333 }
3fcdfb4b 1334 ieee80211_unregister_hw(hw);
8feceb67
VT		 1335 ath_rx_cleanup(sc);
1336 ath_tx_cleanup(sc);
f078f209 1337
9c84b797
S		 1338 tasklet_kill(&sc->intr_tq);
1339 tasklet_kill(&sc->bcon_tasklet);
f078f209 1340
9c84b797
S		 1341 if (!(sc->sc_flags & SC_OP_INVALID))
1342 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1343
9c84b797
S		 1344 /* cleanup tx queues */
1345 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1346 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1347 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1348
1349 ath9k_hw_detach(sc->sc_ah);
826d2680 1350 ath9k_exit_debug(sc);
3cbb5dd7 1351 ath9k_ps_restore(sc);
f078f209
LR		 1352}
1353
e3bb249b
BC		 1354static int ath9k_reg_notifier(struct wiphy *wiphy,
1355 struct regulatory_request *request)
1356{
1357 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1358 struct ath_wiphy *aphy = hw->priv;
1359 struct ath_softc *sc = aphy->sc;
1360 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1361
1362 return ath_reg_notifier_apply(wiphy, request, reg);
1363}
1364
ff37e337
S		 1365static int ath_init(u16 devid, struct ath_softc *sc)
1366{
cbe61d8a 1367 struct ath_hw *ah = NULL;
ff37e337
S		 1368 int status;
1369 int error = 0, i;
1370 int csz = 0;
1371
1372 /* XXX: hardware will not be ready until ath_open() being called */
1373 sc->sc_flags |= SC_OP_INVALID;
88b126af 1374
826d2680
S		 1375 if (ath9k_init_debug(sc) < 0)
1376 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1377
c52f33d0 1378 spin_lock_init(&sc->wiphy_lock);
ff37e337 1379 spin_lock_init(&sc->sc_resetlock);
6158425b 1380 spin_lock_init(&sc->sc_serial_rw);
aa33de09 1381 mutex_init(&sc->mutex);
ff37e337 1382 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1383 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1384 (unsigned long)sc);
1385
1386 /*
1387 * Cache line size is used to size and align various
1388 * structures used to communicate with the hardware.
1389 */
88d15707 1390 ath_read_cachesize(sc, &csz);
ff37e337 1391 /* XXX assert csz is non-zero */
17d7904d 1392 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1393
cbe61d8a 1394 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1395 if (ah == NULL) {
1396 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1397 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1398 error = -ENXIO;
1399 goto bad;
1400 }
1401 sc->sc_ah = ah;
1402
1403 /* Get the hardware key cache size. */
2660b81a 1404 sc->keymax = ah->caps.keycache_size;
17d7904d 1405 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1406 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1407 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1408 ATH_KEYMAX, sc->keymax);
1409 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1410 }
1411
1412 /*
1413 * Reset the key cache since some parts do not
1414 * reset the contents on initial power up.
1415 */
17d7904d 1416 for (i = 0; i < sc->keymax; i++)
ff37e337 1417 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1418
85efc86e
LR		 1419 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1420 ath9k_reg_notifier);
1421 if (error)
ff37e337
S		 1422 goto bad;
1423
1424 /* default to MONITOR mode */
2660b81a 1425 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1426
ff37e337
S		 1427 /* Setup rate tables */
1428
1429 ath_rate_attach(sc);
1430 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1431 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1432
1433 /*
1434 * Allocate hardware transmit queues: one queue for
1435 * beacon frames and one data queue for each QoS
1436 * priority. Note that the hal handles reseting
1437 * these queues at the needed time.
1438 */
b77f483f
S		 1439 sc->beacon.beaconq = ath_beaconq_setup(ah);
1440 if (sc->beacon.beaconq == -1) {
ff37e337 1441 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1442 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1443 error = -EIO;
1444 goto bad2;
1445 }
b77f483f
S		 1446 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1447 if (sc->beacon.cabq == NULL) {
ff37e337 1448 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1449 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1450 error = -EIO;
1451 goto bad2;
1452 }
1453
17d7904d 1454 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1455 ath_cabq_update(sc);
1456
b77f483f
S		 1457 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1458 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1459
1460 /* Setup data queues */
1461 /* NB: ensure BK queue is the lowest priority h/w queue */
1462 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1463 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1464 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1465 error = -EIO;
1466 goto bad2;
1467 }
1468
1469 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1470 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1471 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1472 error = -EIO;
1473 goto bad2;
1474 }
1475 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1476 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1477 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1478 error = -EIO;
1479 goto bad2;
1480 }
1481 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1482 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1483 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1484 error = -EIO;
1485 goto bad2;
1486 }
1487
1488 /* Initializes the noise floor to a reasonable default value.
1489 * Later on this will be updated during ANI processing. */
1490
17d7904d
S		 1491 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1492 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1493
1494 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1495 ATH9K_CIPHER_TKIP, NULL)) {
1496 /*
1497 * Whether we should enable h/w TKIP MIC.
1498 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1499 * report WMM capable, so it's always safe to turn on
1500 * TKIP MIC in this case.
1501 */
1502 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1503 0, 1, NULL);
1504 }
1505
1506 /*
1507 * Check whether the separate key cache entries
1508 * are required to handle both tx+rx MIC keys.
1509 * With split mic keys the number of stations is limited
1510 * to 27 otherwise 59.
1511 */
1512 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1513 ATH9K_CIPHER_TKIP, NULL)
1514 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1515 ATH9K_CIPHER_MIC, NULL)
1516 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1517 0, NULL))
17d7904d 1518 sc->splitmic = 1;
ff37e337
S		 1519
1520 /* turn on mcast key search if possible */
1521 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1522 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1523 1, NULL);
1524
17d7904d 1525 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1526
1527 /* 11n Capabilities */
2660b81a 1528 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1529 sc->sc_flags |= SC_OP_TXAGGR;
1530 sc->sc_flags |= SC_OP_RXAGGR;
1531 }
1532
2660b81a
S		 1533 sc->tx_chainmask = ah->caps.tx_chainmask;
1534 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1535
1536 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1537 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1538
8ca21f01 1539 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1540 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1541
b77f483f 1542 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1543
1544 /* initialize beacon slots */
c52f33d0 1545 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1546 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1547 sc->beacon.bslot_aphy[i] = NULL;
1548 }
ff37e337 1549
ff37e337
S		 1550 /* setup channels and rates */
1551
5f8e077c 1552 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1553 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1554 sc->rates[IEEE80211_BAND_2GHZ];
1555 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1556 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1557 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1558
2660b81a 1559 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1560 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1561 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1562 sc->rates[IEEE80211_BAND_5GHZ];
1563 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1564 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1565 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1566 }
1567
2660b81a 1568 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1569 ath9k_hw_btcoex_enable(sc->sc_ah);
1570
ff37e337
S		 1571 return 0;
1572bad2:
1573 /* cleanup tx queues */
1574 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1575 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1576 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1577bad:
1578 if (ah)
1579 ath9k_hw_detach(ah);
40b130a9 1580 ath9k_exit_debug(sc);
ff37e337
S		 1581
1582 return error;
1583}
1584
c52f33d0 1585void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1586{
9c84b797
S		 1587 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1588 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1589 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1590 IEEE80211_HW_AMPDU_AGGREGATION |
1591 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1592 IEEE80211_HW_PS_NULLFUNC_STACK |
1593 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1594
b3bd89ce 1595 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1596 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1597
9c84b797
S		 1598 hw->wiphy->interface_modes =
1599 BIT(NL80211_IFTYPE_AP) |
1600 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1601 BIT(NL80211_IFTYPE_ADHOC) |
1602 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1603
8feceb67 1604 hw->queues = 4;
e63835b0 1605 hw->max_rates = 4;
171387ef 1606 hw->channel_change_time = 5000;
465ca84d 1607 hw->max_listen_interval = 10;
e63835b0 1608 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1609 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1610 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1611
8feceb67 1612 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1613
c52f33d0
JM		 1614 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1615 &sc->sbands[IEEE80211_BAND_2GHZ];
1616 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1617 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1618 &sc->sbands[IEEE80211_BAND_5GHZ];
1619}
1620
1621int ath_attach(u16 devid, struct ath_softc *sc)
1622{
1623 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1624 int error = 0, i;
3a702e49 1625 struct ath_regulatory *reg;
c52f33d0
JM		 1626
1627 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1628
1629 error = ath_init(devid, sc);
1630 if (error != 0)
1631 return error;
1632
c02cf373
BC		 1633 reg = &sc->sc_ah->regulatory;
1634
c52f33d0
JM		 1635 /* get mac address from hardware and set in mac80211 */
1636
1637 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1638
1639 ath_set_hw_capab(sc, hw);
1640
2660b81a 1641 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1642 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1643 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1644 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1645 }
1646
db93e7b5
SB		 1647 /* initialize tx/rx engine */
1648 error = ath_tx_init(sc, ATH_TXBUF);
1649 if (error != 0)
40b130a9 1650 goto error_attach;
8feceb67 1651
db93e7b5
SB		 1652 error = ath_rx_init(sc, ATH_RXBUF);
1653 if (error != 0)
40b130a9 1654 goto error_attach;
8feceb67 1655
e97275cb 1656#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1657 /* Initialze h/w Rfkill */
2660b81a 1658 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1659 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1660
1661 /* Initialize s/w rfkill */
40b130a9
VT		 1662 error = ath_init_sw_rfkill(sc);
1663 if (error)
1664 goto error_attach;
500c064d
VT		 1665#endif
1666
0e2dedf9 1667 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1668 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1669 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1670
db93e7b5 1671 error = ieee80211_register_hw(hw);
8feceb67 1672
3a702e49 1673 if (!ath_is_world_regd(reg)) {
c02cf373 1674 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1675 if (error)
1676 goto error_attach;
1677 }
5f8e077c 1678
db93e7b5
SB		 1679 /* Initialize LED control */
1680 ath_init_leds(sc);
8feceb67 1681
5f8e077c 1682
8feceb67 1683 return 0;
40b130a9
VT		 1684
1685error_attach:
1686 /* cleanup tx queues */
1687 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1688 if (ATH_TXQ_SETUP(sc, i))
1689 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1690
1691 ath9k_hw_detach(sc->sc_ah);
1692 ath9k_exit_debug(sc);
1693
8feceb67 1694 return error;
f078f209
LR		 1695}
1696
ff37e337
S		 1697int ath_reset(struct ath_softc *sc, bool retry_tx)
1698{
cbe61d8a 1699 struct ath_hw *ah = sc->sc_ah;
030bb495 1700 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1701 int r;
ff37e337
S		 1702
1703 ath9k_hw_set_interrupts(ah, 0);
043a0405 1704 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1705 ath_stoprecv(sc);
1706 ath_flushrecv(sc);
1707
1708 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1709 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1710 if (r)
ff37e337 1711 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1712 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1713 spin_unlock_bh(&sc->sc_resetlock);
1714
1715 if (ath_startrecv(sc) != 0)
04bd4638 1716 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1717
1718 /*
1719 * We may be doing a reset in response to a request
1720 * that changes the channel so update any state that
1721 * might change as a result.
1722 */
ce111bad 1723 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1724
1725 ath_update_txpow(sc);
1726
1727 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1728 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1729
17d7904d 1730 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1731
1732 if (retry_tx) {
1733 int i;
1734 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1735 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1736 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1737 ath_txq_schedule(sc, &sc->tx.txq[i]);
1738 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1739 }
1740 }
1741 }
1742
ae8d2858 1743 return r;
ff37e337
S		 1744}
1745
1746/*
1747 * This function will allocate both the DMA descriptor structure, and the
1748 * buffers it contains. These are used to contain the descriptors used
1749 * by the system.
1750*/
1751int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1752 struct list_head *head, const char *name,
1753 int nbuf, int ndesc)
1754{
1755#define DS2PHYS(_dd, _ds) \
1756 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1757#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1758#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1759
1760 struct ath_desc *ds;
1761 struct ath_buf *bf;
1762 int i, bsize, error;
1763
04bd4638
S		 1764 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1765 name, nbuf, ndesc);
ff37e337 1766
b03a9db9 1767 INIT_LIST_HEAD(head);
ff37e337
S		 1768 /* ath_desc must be a multiple of DWORDs */
1769 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1770 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1771 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1772 error = -ENOMEM;
1773 goto fail;
1774 }
1775
ff37e337
S		 1776 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1777
1778 /*
1779 * Need additional DMA memory because we can't use
1780 * descriptors that cross the 4K page boundary. Assume
1781 * one skipped descriptor per 4K page.
1782 */
2660b81a 1783 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1784 u32 ndesc_skipped =
1785 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1786 u32 dma_len;
1787
1788 while (ndesc_skipped) {
1789 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1790 dd->dd_desc_len += dma_len;
1791
1792 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1793 };
1794 }
1795
1796 /* allocate descriptors */
7da3c55c 1797 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1798 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1799 if (dd->dd_desc == NULL) {
1800 error = -ENOMEM;
1801 goto fail;
1802 }
1803 ds = dd->dd_desc;
04bd4638 1804 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1805 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1806 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1807
1808 /* allocate buffers */
1809 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1810 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1811 if (bf == NULL) {
1812 error = -ENOMEM;
1813 goto fail2;
1814 }
ff37e337
S		 1815 dd->dd_bufptr = bf;
1816
ff37e337
S		 1817 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1818 bf->bf_desc = ds;
1819 bf->bf_daddr = DS2PHYS(dd, ds);
1820
2660b81a 1821 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1822 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1823 /*
1824 * Skip descriptor addresses which can cause 4KB
1825 * boundary crossing (addr + length) with a 32 dword
1826 * descriptor fetch.
1827 */
1828 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1829 ASSERT((caddr_t) bf->bf_desc <
1830 ((caddr_t) dd->dd_desc +
1831 dd->dd_desc_len));
1832
1833 ds += ndesc;
1834 bf->bf_desc = ds;
1835 bf->bf_daddr = DS2PHYS(dd, ds);
1836 }
1837 }
1838 list_add_tail(&bf->list, head);
1839 }
1840 return 0;
1841fail2:
7da3c55c
GJ		 1842 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1843 dd->dd_desc_paddr);
ff37e337
S		 1844fail:
1845 memset(dd, 0, sizeof(*dd));
1846 return error;
1847#undef ATH_DESC_4KB_BOUND_CHECK
1848#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1849#undef DS2PHYS
1850}
1851
1852void ath_descdma_cleanup(struct ath_softc *sc,
1853 struct ath_descdma *dd,
1854 struct list_head *head)
1855{
7da3c55c
GJ		 1856 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1857 dd->dd_desc_paddr);
ff37e337
S		 1858
1859 INIT_LIST_HEAD(head);
1860 kfree(dd->dd_bufptr);
1861 memset(dd, 0, sizeof(*dd));
1862}
1863
1864int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1865{
1866 int qnum;
1867
1868 switch (queue) {
1869 case 0:
b77f483f 1870 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1871 break;
1872 case 1:
b77f483f 1873 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1874 break;
1875 case 2:
b77f483f 1876 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1877 break;
1878 case 3:
b77f483f 1879 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1880 break;
1881 default:
b77f483f 1882 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1883 break;
1884 }
1885
1886 return qnum;
1887}
1888
1889int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1890{
1891 int qnum;
1892
1893 switch (queue) {
1894 case ATH9K_WME_AC_VO:
1895 qnum = 0;
1896 break;
1897 case ATH9K_WME_AC_VI:
1898 qnum = 1;
1899 break;
1900 case ATH9K_WME_AC_BE:
1901 qnum = 2;
1902 break;
1903 case ATH9K_WME_AC_BK:
1904 qnum = 3;
1905 break;
1906 default:
1907 qnum = -1;
1908 break;
1909 }
1910
1911 return qnum;
1912}
1913
5f8e077c
LR		 1914/* XXX: Remove me once we don't depend on ath9k_channel for all
1915 * this redundant data */
0e2dedf9
JM		 1916void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1917 struct ath9k_channel *ichan)
5f8e077c 1918{
5f8e077c
LR		 1919 struct ieee80211_channel *chan = hw->conf.channel;
1920 struct ieee80211_conf *conf = &hw->conf;
1921
1922 ichan->channel = chan->center_freq;
1923 ichan->chan = chan;
1924
1925 if (chan->band == IEEE80211_BAND_2GHZ) {
1926 ichan->chanmode = CHANNEL_G;
1927 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1928 } else {
1929 ichan->chanmode = CHANNEL_A;
1930 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1931 }
1932
1933 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1934
1935 if (conf_is_ht(conf)) {
1936 if (conf_is_ht40(conf))
1937 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1938
1939 ichan->chanmode = ath_get_extchanmode(sc, chan,
1940 conf->channel_type);
1941 }
1942}
1943
ff37e337
S		 1944/**********************/
1945/* mac80211 callbacks */
1946/**********************/
1947
8feceb67 1948static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1949{
bce048d7
JM		 1950 struct ath_wiphy *aphy = hw->priv;
1951 struct ath_softc *sc = aphy->sc;
8feceb67 1952 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1953 struct ath9k_channel *init_channel;
ae8d2858 1954 int r, pos;
f078f209 1955
04bd4638
S		 1956 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1957 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1958
141b38b6
S		 1959 mutex_lock(&sc->mutex);
1960
9580a222
JM		 1961 if (ath9k_wiphy_started(sc)) {
1962 if (sc->chan_idx == curchan->hw_value) {
1963 /*
1964 * Already on the operational channel, the new wiphy
1965 * can be marked active.
1966 */
1967 aphy->state = ATH_WIPHY_ACTIVE;
1968 ieee80211_wake_queues(hw);
1969 } else {
1970 /*
1971 * Another wiphy is on another channel, start the new
1972 * wiphy in paused state.
1973 */
1974 aphy->state = ATH_WIPHY_PAUSED;
1975 ieee80211_stop_queues(hw);
1976 }
1977 mutex_unlock(&sc->mutex);
1978 return 0;
1979 }
1980 aphy->state = ATH_WIPHY_ACTIVE;
1981
8feceb67 1982 /* setup initial channel */
f078f209 1983
5f8e077c 1984 pos = curchan->hw_value;
f078f209 1985
0e2dedf9 1986 sc->chan_idx = pos;
2660b81a 1987 init_channel = &sc->sc_ah->channels[pos];
0e2dedf9 1988 ath9k_update_ichannel(sc, hw, init_channel);
ff37e337
S		 1989
1990 /* Reset SERDES registers */
1991 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1992
1993 /*
1994 * The basic interface to setting the hardware in a good
1995 * state is ``reset''. On return the hardware is known to
1996 * be powered up and with interrupts disabled. This must
1997 * be followed by initialization of the appropriate bits
1998 * and then setup of the interrupt mask.
1999 */
2000 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 2001 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2002 if (r) {
ff37e337 2003 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 2004 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 2005 "(freq %u MHz)\n", r,
2006 curchan->center_freq);
ff37e337 2007 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2008 goto mutex_unlock;
ff37e337
S		 2009 }
2010 spin_unlock_bh(&sc->sc_resetlock);
2011
2012 /*
2013 * This is needed only to setup initial state
2014 * but it's best done after a reset.
2015 */
2016 ath_update_txpow(sc);
8feceb67 2017
ff37e337
S		 2018 /*
2019 * Setup the hardware after reset:
2020 * The receive engine is set going.
2021 * Frame transmit is handled entirely
2022 * in the frame output path; there's nothing to do
2023 * here except setup the interrupt mask.
2024 */
2025 if (ath_startrecv(sc) != 0) {
1ffb0610 2026 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 2027 r = -EIO;
2028 goto mutex_unlock;
f078f209 2029 }
8feceb67 2030
ff37e337 2031 /* Setup our intr mask. */
17d7904d 2032 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2033 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2034 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2035
2660b81a 2036 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2037 sc->imask |= ATH9K_INT_GTT;
ff37e337 2038
2660b81a 2039 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2040 sc->imask |= ATH9K_INT_CST;
ff37e337 2041
ce111bad 2042 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2043
2044 sc->sc_flags &= ~SC_OP_INVALID;
2045
2046 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2047 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2048 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2049
bce048d7 2050 ieee80211_wake_queues(hw);
ff37e337 2051
e97275cb 2052#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2053 r = ath_start_rfkill_poll(sc);
500c064d 2054#endif
141b38b6
S		 2055
2056mutex_unlock:
2057 mutex_unlock(&sc->mutex);
2058
ae8d2858 2059 return r;
f078f209
LR		 2060}
2061
8feceb67
VT		 2062static int ath9k_tx(struct ieee80211_hw *hw,
2063 struct sk_buff *skb)
f078f209 2064{
528f0c6b 2065 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2066 struct ath_wiphy *aphy = hw->priv;
2067 struct ath_softc *sc = aphy->sc;
528f0c6b 2068 struct ath_tx_control txctl;
8feceb67 2069 int hdrlen, padsize;
528f0c6b 2070
8089cc47 2071 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2072 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2073 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2074 goto exit;
2075 }
2076
528f0c6b 2077 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2078
8feceb67
VT		 2079 /*
2080 * As a temporary workaround, assign seq# here; this will likely need
2081 * to be cleaned up to work better with Beacon transmission and virtual
2082 * BSSes.
2083 */
2084 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2085 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2086 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2087 sc->tx.seq_no += 0x10;
8feceb67 2088 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2089 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2090 }
f078f209 2091
8feceb67
VT		 2092 /* Add the padding after the header if this is not already done */
2093 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2094 if (hdrlen & 3) {
2095 padsize = hdrlen % 4;
2096 if (skb_headroom(skb) < padsize)
2097 return -1;
2098 skb_push(skb, padsize);
2099 memmove(skb->data, skb->data + padsize, hdrlen);
2100 }
2101
528f0c6b
S		 2102 /* Check if a tx queue is available */
2103
2104 txctl.txq = ath_test_get_txq(sc, skb);
2105 if (!txctl.txq)
2106 goto exit;
2107
04bd4638 2108 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2109
c52f33d0 2110 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2111 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2112 goto exit;
8feceb67
VT		 2113 }
2114
528f0c6b
S		 2115 return 0;
2116exit:
2117 dev_kfree_skb_any(skb);
8feceb67 2118 return 0;
f078f209
LR		 2119}
2120
8feceb67 2121static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2122{
bce048d7
JM		 2123 struct ath_wiphy *aphy = hw->priv;
2124 struct ath_softc *sc = aphy->sc;
f078f209 2125
9580a222
JM		 2126 aphy->state = ATH_WIPHY_INACTIVE;
2127
9c84b797 2128 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2129 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2130 return;
2131 }
8feceb67 2132
141b38b6 2133 mutex_lock(&sc->mutex);
ff37e337 2134
bce048d7 2135 ieee80211_stop_queues(hw);
ff37e337 2136
9580a222
JM		 2137 if (ath9k_wiphy_started(sc)) {
2138 mutex_unlock(&sc->mutex);
2139 return; /* another wiphy still in use */
2140 }
2141
ff37e337
S		 2142 /* make sure h/w will not generate any interrupt
2143 * before setting the invalid flag. */
2144 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2145
2146 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2147 ath_drain_all_txq(sc, false);
ff37e337
S		 2148 ath_stoprecv(sc);
2149 ath9k_hw_phy_disable(sc->sc_ah);
2150 } else
b77f483f 2151 sc->rx.rxlink = NULL;
ff37e337
S		 2152
2153#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2154 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2155 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2156#endif
2157 /* disable HAL and put h/w to sleep */
2158 ath9k_hw_disable(sc->sc_ah);
2159 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2160
2161 sc->sc_flags |= SC_OP_INVALID;
500c064d 2162
141b38b6
S		 2163 mutex_unlock(&sc->mutex);
2164
04bd4638 2165 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2166}
2167
8feceb67
VT		 2168static int ath9k_add_interface(struct ieee80211_hw *hw,
2169 struct ieee80211_if_init_conf *conf)
f078f209 2170{
bce048d7
JM		 2171 struct ath_wiphy *aphy = hw->priv;
2172 struct ath_softc *sc = aphy->sc;
17d7904d 2173 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2174 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2175 int ret = 0;
8feceb67 2176
141b38b6
S		 2177 mutex_lock(&sc->mutex);
2178
8ca21f01
JM		 2179 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2180 sc->nvifs > 0) {
2181 ret = -ENOBUFS;
2182 goto out;
2183 }
2184
8feceb67 2185 switch (conf->type) {
05c914fe 2186 case NL80211_IFTYPE_STATION:
d97809db 2187 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2188 break;
05c914fe 2189 case NL80211_IFTYPE_ADHOC:
05c914fe 2190 case NL80211_IFTYPE_AP:
9cb5412b 2191 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2192 if (sc->nbcnvifs >= ATH_BCBUF) {
2193 ret = -ENOBUFS;
2194 goto out;
2195 }
9cb5412b 2196 ic_opmode = conf->type;
f078f209
LR		 2197 break;
2198 default:
2199 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2200 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2201 ret = -EOPNOTSUPP;
2202 goto out;
f078f209
LR		 2203 }
2204
17d7904d 2205 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2206
17d7904d 2207 /* Set the VIF opmode */
5640b08e
S		 2208 avp->av_opmode = ic_opmode;
2209 avp->av_bslot = -1;
2210
2c3db3d5 2211 sc->nvifs++;
8ca21f01
JM		 2212
2213 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2214 ath9k_set_bssid_mask(hw);
2215
2c3db3d5
JM		 2216 if (sc->nvifs > 1)
2217 goto out; /* skip global settings for secondary vif */
2218
b238e90e 2219 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2220 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2221 sc->sc_flags |= SC_OP_TSF_RESET;
2222 }
5640b08e 2223
5640b08e 2224 /* Set the device opmode */
2660b81a 2225 sc->sc_ah->opmode = ic_opmode;
5640b08e 2226
4e30ffa2
VN		 2227 /*
2228 * Enable MIB interrupts when there are hardware phy counters.
2229 * Note we only do this (at the moment) for station mode.
2230 */
4af9cf4f 2231 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2232 (conf->type == NL80211_IFTYPE_ADHOC) ||
2233 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2234 if (ath9k_hw_phycounters(sc->sc_ah))
2235 sc->imask |= ATH9K_INT_MIB;
2236 sc->imask |= ATH9K_INT_TSFOOR;
2237 }
2238
17d7904d 2239 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2240
415f738e
S		 2241 if (conf->type == NL80211_IFTYPE_AP)
2242 ath_start_ani(sc);
6f255425 2243
2c3db3d5 2244out:
141b38b6 2245 mutex_unlock(&sc->mutex);
2c3db3d5 2246 return ret;
f078f209
LR		 2247}
2248
8feceb67
VT		 2249static void ath9k_remove_interface(struct ieee80211_hw *hw,
2250 struct ieee80211_if_init_conf *conf)
f078f209 2251{
bce048d7
JM		 2252 struct ath_wiphy *aphy = hw->priv;
2253 struct ath_softc *sc = aphy->sc;
17d7904d 2254 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2255 int i;
f078f209 2256
04bd4638 2257 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2258
141b38b6
S		 2259 mutex_lock(&sc->mutex);
2260
6f255425 2261 /* Stop ANI */
17d7904d 2262 del_timer_sync(&sc->ani.timer);
580f0b8a 2263
8feceb67 2264 /* Reclaim beacon resources */
9cb5412b
PE		 2265 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2266 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2267 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2268 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2269 ath_beacon_return(sc, avp);
580f0b8a 2270 }
f078f209 2271
8feceb67 2272 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2273
2c3db3d5
JM		 2274 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2275 if (sc->beacon.bslot[i] == conf->vif) {
2276 printk(KERN_DEBUG "%s: vif had allocated beacon "
2277 "slot\n", __func__);
2278 sc->beacon.bslot[i] = NULL;
c52f33d0 2279 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2280 }
2281 }
2282
17d7904d 2283 sc->nvifs--;
141b38b6
S		 2284
2285 mutex_unlock(&sc->mutex);
f078f209
LR		 2286}
2287
e8975581 2288static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2289{
bce048d7
JM		 2290 struct ath_wiphy *aphy = hw->priv;
2291 struct ath_softc *sc = aphy->sc;
e8975581 2292 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2293 struct ath_hw *ah = sc->sc_ah;
f078f209 2294
aa33de09 2295 mutex_lock(&sc->mutex);
141b38b6 2296
3cbb5dd7
VN		 2297 if (changed & IEEE80211_CONF_CHANGE_PS) {
2298 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2299 if (!(ah->caps.hw_caps &
2300 ATH9K_HW_CAP_AUTOSLEEP)) {
2301 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2302 sc->imask |= ATH9K_INT_TIM_TIMER;
2303 ath9k_hw_set_interrupts(sc->sc_ah,
2304 sc->imask);
2305 }
2306 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2307 }
3cbb5dd7
VN		 2308 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2309 } else {
2310 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2311 if (!(ah->caps.hw_caps &
2312 ATH9K_HW_CAP_AUTOSLEEP)) {
2313 ath9k_hw_setrxabort(sc->sc_ah, 0);
2314 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2315 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2316 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2317 ath9k_hw_set_interrupts(sc->sc_ah,
2318 sc->imask);
2319 }
3cbb5dd7
VN		 2320 }
2321 }
2322 }
2323
4797938c 2324 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2325 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2326 int pos = curchan->hw_value;
ae5eb026 2327
0e2dedf9
JM		 2328 aphy->chan_idx = pos;
2329 aphy->chan_is_ht = conf_is_ht(conf);
2330
8089cc47
JM		 2331 if (aphy->state == ATH_WIPHY_SCAN ||
2332 aphy->state == ATH_WIPHY_ACTIVE)
2333 ath9k_wiphy_pause_all_forced(sc, aphy);
2334 else {
2335 /*
2336 * Do not change operational channel based on a paused
2337 * wiphy changes.
2338 */
2339 goto skip_chan_change;
2340 }
0e2dedf9 2341
04bd4638
S		 2342 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2343 curchan->center_freq);
f078f209 2344
5f8e077c 2345 /* XXX: remove me eventualy */
0e2dedf9 2346 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2347
ecf70441 2348 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2349
0e2dedf9 2350 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2351 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2352 mutex_unlock(&sc->mutex);
e11602b7
S		 2353 return -EINVAL;
2354 }
094d05dc 2355 }
f078f209 2356
8089cc47 2357skip_chan_change:
5c020dc6 2358 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2359 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2360
aa33de09 2361 mutex_unlock(&sc->mutex);
141b38b6 2362
f078f209
LR		 2363 return 0;
2364}
2365
8feceb67
VT		 2366#define SUPPORTED_FILTERS \
2367 (FIF_PROMISC_IN_BSS | \
2368 FIF_ALLMULTI | \
2369 FIF_CONTROL | \
2370 FIF_OTHER_BSS | \
2371 FIF_BCN_PRBRESP_PROMISC | \
2372 FIF_FCSFAIL)
c83be688 2373
8feceb67
VT		 2374/* FIXME: sc->sc_full_reset ? */
2375static void ath9k_configure_filter(struct ieee80211_hw *hw,
2376 unsigned int changed_flags,
2377 unsigned int *total_flags,
2378 int mc_count,
2379 struct dev_mc_list *mclist)
2380{
bce048d7
JM		 2381 struct ath_wiphy *aphy = hw->priv;
2382 struct ath_softc *sc = aphy->sc;
8feceb67 2383 u32 rfilt;
f078f209 2384
8feceb67
VT		 2385 changed_flags &= SUPPORTED_FILTERS;
2386 *total_flags &= SUPPORTED_FILTERS;
f078f209 2387
b77f483f 2388 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2389 rfilt = ath_calcrxfilter(sc);
2390 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2391
b77f483f 2392 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2393}
f078f209 2394
8feceb67
VT		 2395static void ath9k_sta_notify(struct ieee80211_hw *hw,
2396 struct ieee80211_vif *vif,
2397 enum sta_notify_cmd cmd,
17741cdc 2398 struct ieee80211_sta *sta)
8feceb67 2399{
bce048d7
JM		 2400 struct ath_wiphy *aphy = hw->priv;
2401 struct ath_softc *sc = aphy->sc;
f078f209 2402
8feceb67
VT		 2403 switch (cmd) {
2404 case STA_NOTIFY_ADD:
5640b08e 2405 ath_node_attach(sc, sta);
8feceb67
VT		 2406 break;
2407 case STA_NOTIFY_REMOVE:
b5aa9bf9 2408 ath_node_detach(sc, sta);
8feceb67
VT		 2409 break;
2410 default:
2411 break;
2412 }
f078f209
LR		 2413}
2414
141b38b6 2415static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2416 const struct ieee80211_tx_queue_params *params)
f078f209 2417{
bce048d7
JM		 2418 struct ath_wiphy *aphy = hw->priv;
2419 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2420 struct ath9k_tx_queue_info qi;
2421 int ret = 0, qnum;
f078f209 2422
8feceb67
VT		 2423 if (queue >= WME_NUM_AC)
2424 return 0;
f078f209 2425
141b38b6
S		 2426 mutex_lock(&sc->mutex);
2427
1ffb0610
S		 2428 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2429
8feceb67
VT		 2430 qi.tqi_aifs = params->aifs;
2431 qi.tqi_cwmin = params->cw_min;
2432 qi.tqi_cwmax = params->cw_max;
2433 qi.tqi_burstTime = params->txop;
2434 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2435
8feceb67 2436 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2437 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2438 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2439 queue, qnum, params->aifs, params->cw_min,
2440 params->cw_max, params->txop);
f078f209 2441
8feceb67
VT		 2442 ret = ath_txq_update(sc, qnum, &qi);
2443 if (ret)
04bd4638 2444 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2445
141b38b6
S		 2446 mutex_unlock(&sc->mutex);
2447
8feceb67
VT		 2448 return ret;
2449}
f078f209 2450
8feceb67
VT		 2451static int ath9k_set_key(struct ieee80211_hw *hw,
2452 enum set_key_cmd cmd,
dc822b5d
JB		 2453 struct ieee80211_vif *vif,
2454 struct ieee80211_sta *sta,
8feceb67
VT		 2455 struct ieee80211_key_conf *key)
2456{
bce048d7
JM		 2457 struct ath_wiphy *aphy = hw->priv;
2458 struct ath_softc *sc = aphy->sc;
8feceb67 2459 int ret = 0;
f078f209 2460
b3bd89ce
JM		 2461 if (modparam_nohwcrypt)
2462 return -ENOSPC;
2463
141b38b6 2464 mutex_lock(&sc->mutex);
3cbb5dd7 2465 ath9k_ps_wakeup(sc);
d8baa939 2466 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2467
8feceb67
VT		 2468 switch (cmd) {
2469 case SET_KEY:
3f53dd64 2470 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2471 if (ret >= 0) {
2472 key->hw_key_idx = ret;
8feceb67
VT		 2473 /* push IV and Michael MIC generation to stack */
2474 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2475 if (key->alg == ALG_TKIP)
2476 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2477 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2478 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2479 ret = 0;
8feceb67
VT		 2480 }
2481 break;
2482 case DISABLE_KEY:
2483 ath_key_delete(sc, key);
8feceb67
VT		 2484 break;
2485 default:
2486 ret = -EINVAL;
2487 }
f078f209 2488
3cbb5dd7 2489 ath9k_ps_restore(sc);
141b38b6
S		 2490 mutex_unlock(&sc->mutex);
2491
8feceb67
VT		 2492 return ret;
2493}
f078f209 2494
8feceb67
VT		 2495static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2496 struct ieee80211_vif *vif,
2497 struct ieee80211_bss_conf *bss_conf,
2498 u32 changed)
2499{
bce048d7
JM		 2500 struct ath_wiphy *aphy = hw->priv;
2501 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2502 struct ath_hw *ah = sc->sc_ah;
2503 struct ath_vif *avp = (void *)vif->drv_priv;
2504 u32 rfilt = 0;
2505 int error, i;
f078f209 2506
141b38b6
S		 2507 mutex_lock(&sc->mutex);
2508
2d0ddec5
JB		 2509 /*
2510 * TODO: Need to decide which hw opmode to use for
2511 * multi-interface cases
2512 * XXX: This belongs into add_interface!
2513 */
2514 if (vif->type == NL80211_IFTYPE_AP &&
2515 ah->opmode != NL80211_IFTYPE_AP) {
2516 ah->opmode = NL80211_IFTYPE_STATION;
2517 ath9k_hw_setopmode(ah);
2518 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2519 sc->curaid = 0;
2520 ath9k_hw_write_associd(sc);
2521 /* Request full reset to get hw opmode changed properly */
2522 sc->sc_flags |= SC_OP_FULL_RESET;
2523 }
2524
2525 if ((changed & BSS_CHANGED_BSSID) &&
2526 !is_zero_ether_addr(bss_conf->bssid)) {
2527 switch (vif->type) {
2528 case NL80211_IFTYPE_STATION:
2529 case NL80211_IFTYPE_ADHOC:
2530 case NL80211_IFTYPE_MESH_POINT:
2531 /* Set BSSID */
2532 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2533 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2534 sc->curaid = 0;
2535 ath9k_hw_write_associd(sc);
2536
2537 /* Set aggregation protection mode parameters */
2538 sc->config.ath_aggr_prot = 0;
2539
2540 DPRINTF(sc, ATH_DBG_CONFIG,
2541 "RX filter 0x%x bssid %pM aid 0x%x\n",
2542 rfilt, sc->curbssid, sc->curaid);
2543
2544 /* need to reconfigure the beacon */
2545 sc->sc_flags &= ~SC_OP_BEACONS ;
2546
2547 break;
2548 default:
2549 break;
2550 }
2551 }
2552
2553 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2554 (vif->type == NL80211_IFTYPE_AP) ||
2555 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2556 if ((changed & BSS_CHANGED_BEACON) ||
2557 (changed & BSS_CHANGED_BEACON_ENABLED &&
2558 bss_conf->enable_beacon)) {
2559 /*
2560 * Allocate and setup the beacon frame.
2561 *
2562 * Stop any previous beacon DMA. This may be
2563 * necessary, for example, when an ibss merge
2564 * causes reconfiguration; we may be called
2565 * with beacon transmission active.
2566 */
2567 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2568
2569 error = ath_beacon_alloc(aphy, vif);
2570 if (!error)
2571 ath_beacon_config(sc, vif);
2572 }
2573 }
2574
2575 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2576 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2577 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2578 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2579 ath9k_hw_keysetmac(sc->sc_ah,
2580 (u16)i,
2581 sc->curbssid);
2582 }
2583
2584 /* Only legacy IBSS for now */
2585 if (vif->type == NL80211_IFTYPE_ADHOC)
2586 ath_update_chainmask(sc, 0);
2587
8feceb67 2588 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2589 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2590 bss_conf->use_short_preamble);
2591 if (bss_conf->use_short_preamble)
2592 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2593 else
2594 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2595 }
f078f209 2596
8feceb67 2597 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2598 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2599 bss_conf->use_cts_prot);
2600 if (bss_conf->use_cts_prot &&
2601 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2602 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2603 else
2604 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2605 }
f078f209 2606
8feceb67 2607 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2608 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2609 bss_conf->assoc);
5640b08e 2610 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2611 }
141b38b6 2612
57c4d7b4
JB		 2613 /*
2614 * The HW TSF has to be reset when the beacon interval changes.
2615 * We set the flag here, and ath_beacon_config_ap() would take this
2616 * into account when it gets called through the subsequent
2617 * config_interface() call - with IFCC_BEACON in the changed field.
2618 */
2619
2620 if (changed & BSS_CHANGED_BEACON_INT) {
2621 sc->sc_flags |= SC_OP_TSF_RESET;
2622 sc->beacon_interval = bss_conf->beacon_int;
2623 }
2624
141b38b6 2625 mutex_unlock(&sc->mutex);
8feceb67 2626}
f078f209 2627
8feceb67
VT		 2628static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2629{
2630 u64 tsf;
bce048d7
JM		 2631 struct ath_wiphy *aphy = hw->priv;
2632 struct ath_softc *sc = aphy->sc;
f078f209 2633
141b38b6
S		 2634 mutex_lock(&sc->mutex);
2635 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2636 mutex_unlock(&sc->mutex);
f078f209 2637
8feceb67
VT		 2638 return tsf;
2639}
f078f209 2640
3b5d665b
AF		 2641static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2642{
bce048d7
JM		 2643 struct ath_wiphy *aphy = hw->priv;
2644 struct ath_softc *sc = aphy->sc;
3b5d665b 2645
141b38b6
S		 2646 mutex_lock(&sc->mutex);
2647 ath9k_hw_settsf64(sc->sc_ah, tsf);
2648 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2649}
2650
8feceb67
VT		 2651static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2652{
bce048d7
JM		 2653 struct ath_wiphy *aphy = hw->priv;
2654 struct ath_softc *sc = aphy->sc;
c83be688 2655
141b38b6
S		 2656 mutex_lock(&sc->mutex);
2657 ath9k_hw_reset_tsf(sc->sc_ah);
2658 mutex_unlock(&sc->mutex);
8feceb67 2659}
f078f209 2660
8feceb67 2661static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2662 enum ieee80211_ampdu_mlme_action action,
2663 struct ieee80211_sta *sta,
2664 u16 tid, u16 *ssn)
8feceb67 2665{
bce048d7
JM		 2666 struct ath_wiphy *aphy = hw->priv;
2667 struct ath_softc *sc = aphy->sc;
8feceb67 2668 int ret = 0;
f078f209 2669
8feceb67
VT		 2670 switch (action) {
2671 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2672 if (!(sc->sc_flags & SC_OP_RXAGGR))
2673 ret = -ENOTSUPP;
8feceb67
VT		 2674 break;
2675 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2676 break;
2677 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2678 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2679 if (ret < 0)
2680 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2681 "Unable to start TX aggregation\n");
8feceb67 2682 else
17741cdc 2683 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2684 break;
2685 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2686 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2687 if (ret < 0)
2688 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2689 "Unable to stop TX aggregation\n");
f078f209 2690
17741cdc 2691 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2692 break;
b1720231 2693 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2694 ath_tx_aggr_resume(sc, sta, tid);
2695 break;
8feceb67 2696 default:
04bd4638 2697 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2698 }
2699
2700 return ret;
f078f209
LR		 2701}
2702
0c98de65
S		 2703static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2704{
bce048d7
JM		 2705 struct ath_wiphy *aphy = hw->priv;
2706 struct ath_softc *sc = aphy->sc;
0c98de65 2707
8089cc47
JM		 2708 if (ath9k_wiphy_scanning(sc)) {
2709 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2710 "same time\n");
2711 /*
2712 * Do not allow the concurrent scanning state for now. This
2713 * could be improved with scanning control moved into ath9k.
2714 */
2715 return;
2716 }
2717
2718 aphy->state = ATH_WIPHY_SCAN;
2719 ath9k_wiphy_pause_all_forced(sc, aphy);
2720
0c98de65
S		 2721 mutex_lock(&sc->mutex);
2722 sc->sc_flags |= SC_OP_SCANNING;
2723 mutex_unlock(&sc->mutex);
2724}
2725
2726static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2727{
bce048d7
JM		 2728 struct ath_wiphy *aphy = hw->priv;
2729 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2730
2731 mutex_lock(&sc->mutex);
8089cc47 2732 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2733 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2734 sc->sc_flags |= SC_OP_FULL_RESET;
0c98de65
S		 2735 mutex_unlock(&sc->mutex);
2736}
2737
6baff7f9 2738struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2739 .tx = ath9k_tx,
2740 .start = ath9k_start,
2741 .stop = ath9k_stop,
2742 .add_interface = ath9k_add_interface,
2743 .remove_interface = ath9k_remove_interface,
2744 .config = ath9k_config,
8feceb67 2745 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2746 .sta_notify = ath9k_sta_notify,
2747 .conf_tx = ath9k_conf_tx,
8feceb67 2748 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2749 .set_key = ath9k_set_key,
8feceb67 2750 .get_tsf = ath9k_get_tsf,
3b5d665b 2751 .set_tsf = ath9k_set_tsf,
8feceb67 2752 .reset_tsf = ath9k_reset_tsf,
4233df6b 2753 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2754 .sw_scan_start = ath9k_sw_scan_start,
2755 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2756};
2757
392dff83
BP		 2758static struct {
2759 u32 version;
2760 const char * name;
2761} ath_mac_bb_names[] = {
2762 { AR_SREV_VERSION_5416_PCI, "5416" },
2763 { AR_SREV_VERSION_5416_PCIE, "5418" },
2764 { AR_SREV_VERSION_9100, "9100" },
2765 { AR_SREV_VERSION_9160, "9160" },
2766 { AR_SREV_VERSION_9280, "9280" },
2767 { AR_SREV_VERSION_9285, "9285" }
2768};
2769
2770static struct {
2771 u16 version;
2772 const char * name;
2773} ath_rf_names[] = {
2774 { 0, "5133" },
2775 { AR_RAD5133_SREV_MAJOR, "5133" },
2776 { AR_RAD5122_SREV_MAJOR, "5122" },
2777 { AR_RAD2133_SREV_MAJOR, "2133" },
2778 { AR_RAD2122_SREV_MAJOR, "2122" }
2779};
2780
2781/*
2782 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2783 */
6baff7f9 2784const char *
392dff83
BP		 2785ath_mac_bb_name(u32 mac_bb_version)
2786{
2787 int i;
2788
2789 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2790 if (ath_mac_bb_names[i].version == mac_bb_version) {
2791 return ath_mac_bb_names[i].name;
2792 }
2793 }
2794
2795 return "????";
2796}
2797
2798/*
2799 * Return the RF name. "????" is returned if the RF is unknown.
2800 */
6baff7f9 2801const char *
392dff83
BP		 2802ath_rf_name(u16 rf_version)
2803{
2804 int i;
2805
2806 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2807 if (ath_rf_names[i].version == rf_version) {
2808 return ath_rf_names[i].name;
2809 }
2810 }
2811
2812 return "????";
2813}
2814
6baff7f9 2815static int __init ath9k_init(void)
f078f209 2816{
ca8a8560
VT		 2817 int error;
2818
ca8a8560
VT		 2819 /* Register rate control algorithm */
2820 error = ath_rate_control_register();
2821 if (error != 0) {
2822 printk(KERN_ERR
b51bb3cd
LR		 2823 "ath9k: Unable to register rate control "
2824 "algorithm: %d\n",
ca8a8560 2825 error);
6baff7f9 2826 goto err_out;
ca8a8560
VT		 2827 }
2828
19d8bc22
GJ		 2829 error = ath9k_debug_create_root();
2830 if (error) {
2831 printk(KERN_ERR
2832 "ath9k: Unable to create debugfs root: %d\n",
2833 error);
2834 goto err_rate_unregister;
2835 }
2836
6baff7f9
GJ		 2837 error = ath_pci_init();
2838 if (error < 0) {
f078f209 2839 printk(KERN_ERR
b51bb3cd 2840 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2841 error = -ENODEV;
19d8bc22 2842 goto err_remove_root;
f078f209
LR		 2843 }
2844
09329d37
GJ		 2845 error = ath_ahb_init();
2846 if (error < 0) {
2847 error = -ENODEV;
2848 goto err_pci_exit;
2849 }
2850
f078f209 2851 return 0;
6baff7f9 2852
09329d37
GJ		 2853 err_pci_exit:
2854 ath_pci_exit();
2855
19d8bc22
GJ		 2856 err_remove_root:
2857 ath9k_debug_remove_root();
6baff7f9
GJ		 2858 err_rate_unregister:
2859 ath_rate_control_unregister();
2860 err_out:
2861 return error;
f078f209 2862}
6baff7f9 2863module_init(ath9k_init);
f078f209 2864
6baff7f9 2865static void __exit ath9k_exit(void)
f078f209 2866{
09329d37 2867 ath_ahb_exit();
6baff7f9 2868 ath_pci_exit();
19d8bc22 2869 ath9k_debug_remove_root();
ca8a8560 2870 ath_rate_control_unregister();
04bd4638 2871 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2872}
6baff7f9 2873module_exit(ath9k_exit);
kernel source for telekom puls (alcatel/mediatek)