ath9k: always issue a full hw reset after waking up from full-sleep mode
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 114 enum ath9k_power_mode mode;
a91d75ae
LR
115 unsigned long flags;
116
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 if (--sc->ps_usecount != 0)
119 goto unlock;
120
c8e8868e 121 if (sc->ps_idle && (sc->ps_flags & PS_WAIT_FOR_TX_ACK))
c6c539f0 122 mode = ATH9K_PM_FULL_SLEEP;
1dbfd9d4
VN
123 else if (sc->ps_enabled &&
124 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
125 PS_WAIT_FOR_CAB |
126 PS_WAIT_FOR_PSPOLL_DATA |
127 PS_WAIT_FOR_TX_ACK)))
c6c539f0
FF
128 mode = ATH9K_PM_NETWORK_SLEEP;
129 else
130 goto unlock;
131
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 spin_unlock(&common->cc_lock);
135
1a8f0d39 136 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
137
138 unlock:
139 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
140}
141
05c0be2f 142void ath_start_ani(struct ath_common *common)
5ee08656
FF
143{
144 struct ath_hw *ah = common->ah;
145 unsigned long timestamp = jiffies_to_msecs(jiffies);
146 struct ath_softc *sc = (struct ath_softc *) common->priv;
147
148 if (!(sc->sc_flags & SC_OP_ANI_RUN))
149 return;
150
151 if (sc->sc_flags & SC_OP_OFFCHANNEL)
152 return;
153
154 common->ani.longcal_timer = timestamp;
155 common->ani.shortcal_timer = timestamp;
156 common->ani.checkani_timer = timestamp;
157
158 mod_timer(&common->ani.timer,
159 jiffies +
160 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
161}
162
3430098a
FF
163static void ath_update_survey_nf(struct ath_softc *sc, int channel)
164{
165 struct ath_hw *ah = sc->sc_ah;
166 struct ath9k_channel *chan = &ah->channels[channel];
167 struct survey_info *survey = &sc->survey[channel];
168
169 if (chan->noisefloor) {
170 survey->filled |= SURVEY_INFO_NOISE_DBM;
f749b946 171 survey->noise = ath9k_hw_getchan_noise(ah, chan);
3430098a
FF
172 }
173}
174
cb8d61de
FF
175/*
176 * Updates the survey statistics and returns the busy time since last
177 * update in %, if the measurement duration was long enough for the
178 * result to be useful, -1 otherwise.
179 */
180static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
181{
182 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah);
184 int pos = ah->curchan - &ah->channels[0];
185 struct survey_info *survey = &sc->survey[pos];
186 struct ath_cycle_counters *cc = &common->cc_survey;
187 unsigned int div = common->clockrate * 1000;
cb8d61de 188 int ret = 0;
3430098a 189
0845735e 190 if (!ah->curchan)
cb8d61de 191 return -1;
0845735e 192
898c914a
FF
193 if (ah->power_mode == ATH9K_PM_AWAKE)
194 ath_hw_cycle_counters_update(common);
3430098a
FF
195
196 if (cc->cycles > 0) {
197 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
198 SURVEY_INFO_CHANNEL_TIME_BUSY |
199 SURVEY_INFO_CHANNEL_TIME_RX |
200 SURVEY_INFO_CHANNEL_TIME_TX;
201 survey->channel_time += cc->cycles / div;
202 survey->channel_time_busy += cc->rx_busy / div;
203 survey->channel_time_rx += cc->rx_frame / div;
204 survey->channel_time_tx += cc->tx_frame / div;
205 }
cb8d61de
FF
206
207 if (cc->cycles < div)
208 return -1;
209
210 if (cc->cycles > 0)
211 ret = cc->rx_busy * 100 / cc->cycles;
212
3430098a
FF
213 memset(cc, 0, sizeof(*cc));
214
215 ath_update_survey_nf(sc, pos);
cb8d61de
FF
216
217 return ret;
3430098a
FF
218}
219
9adcf440 220static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 221{
5ee08656
FF
222 cancel_work_sync(&sc->paprd_work);
223 cancel_work_sync(&sc->hw_check_work);
224 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 225 cancel_delayed_work_sync(&sc->hw_pll_work);
9adcf440 226}
5ee08656 227
9adcf440
FF
228static void ath_cancel_work(struct ath_softc *sc)
229{
230 __ath_cancel_work(sc);
231 cancel_work_sync(&sc->hw_reset_work);
232}
3cbb5dd7 233
9adcf440
FF
234static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
235{
236 struct ath_hw *ah = sc->sc_ah;
237 struct ath_common *common = ath9k_hw_common(ah);
238 bool ret;
6a6733f2 239
9adcf440 240 ieee80211_stop_queues(sc->hw);
5e848f78 241
9adcf440
FF
242 sc->hw_busy_count = 0;
243 del_timer_sync(&common->ani.timer);
ff37e337 244
9adcf440
FF
245 ath9k_debug_samp_bb_mac(sc);
246 ath9k_hw_disable_interrupts(ah);
8b3f4616 247
9adcf440 248 ret = ath_drain_all_txq(sc, retry_tx);
ff37e337 249
9adcf440
FF
250 if (!ath_stoprecv(sc))
251 ret = false;
c0d7c7af 252
9adcf440
FF
253 if (!flush) {
254 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF
255 ath_rx_tasklet(sc, 1, true);
256 ath_rx_tasklet(sc, 1, false);
9adcf440
FF
257 } else {
258 ath_flushrecv(sc);
259 }
20bd2a09 260
9adcf440
FF
261 return ret;
262}
ff37e337 263
9adcf440
FF
264static bool ath_complete_reset(struct ath_softc *sc, bool start)
265{
266 struct ath_hw *ah = sc->sc_ah;
267 struct ath_common *common = ath9k_hw_common(ah);
c0d7c7af 268
c0d7c7af 269 if (ath_startrecv(sc) != 0) {
3800276a 270 ath_err(common, "Unable to restart recv logic\n");
9adcf440 271 return false;
c0d7c7af
LR
272 }
273
5048e8c3
RM
274 ath9k_cmn_update_txpow(ah, sc->curtxpow,
275 sc->config.txpowlimit, &sc->curtxpow);
72d874c6 276 ath9k_hw_set_interrupts(ah);
b037b693 277 ath9k_hw_enable_interrupts(ah);
3989279c 278
9adcf440 279 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
1186488b 280 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 281 ath_set_beacon(sc);
9adcf440 282
5ee08656 283 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 284 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
05c0be2f
MSS
285 if (!common->disable_ani)
286 ath_start_ani(common);
5ee08656
FF
287 }
288
43c35284
FF
289 if (ath9k_hw_ops(ah)->antdiv_comb_conf_get && sc->ant_rx != 3) {
290 struct ath_hw_antcomb_conf div_ant_conf;
291 u8 lna_conf;
292
293 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
294
295 if (sc->ant_rx == 1)
296 lna_conf = ATH_ANT_DIV_COMB_LNA1;
297 else
298 lna_conf = ATH_ANT_DIV_COMB_LNA2;
299 div_ant_conf.main_lna_conf = lna_conf;
300 div_ant_conf.alt_lna_conf = lna_conf;
301
302 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
303 }
304
9adcf440
FF
305 ieee80211_wake_queues(sc->hw);
306
307 return true;
308}
309
310static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
311 bool retry_tx)
312{
313 struct ath_hw *ah = sc->sc_ah;
314 struct ath_common *common = ath9k_hw_common(ah);
315 struct ath9k_hw_cal_data *caldata = NULL;
316 bool fastcc = true;
317 bool flush = false;
318 int r;
319
320 __ath_cancel_work(sc);
321
322 spin_lock_bh(&sc->sc_pcu_lock);
92460412 323
9adcf440
FF
324 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
325 fastcc = false;
326 caldata = &sc->caldata;
327 }
328
329 if (!hchan) {
330 fastcc = false;
331 flush = true;
332 hchan = ah->curchan;
333 }
334
c8e8868e
FF
335 if (fastcc && (ah->chip_fullsleep ||
336 !ath9k_hw_check_alive(ah)))
9adcf440
FF
337 fastcc = false;
338
339 if (!ath_prepare_reset(sc, retry_tx, flush))
340 fastcc = false;
341
342 ath_dbg(common, ATH_DBG_CONFIG,
343 "Reset to %u MHz, HT40: %d fastcc: %d\n",
344 hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS |
345 CHANNEL_HT40PLUS)),
346 fastcc);
347
348 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
349 if (r) {
350 ath_err(common,
351 "Unable to reset channel, reset status %d\n", r);
352 goto out;
353 }
354
355 if (!ath_complete_reset(sc, true))
356 r = -EIO;
357
358out:
6a6733f2 359 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF
360 return r;
361}
362
363
364/*
365 * Set/change channels. If the channel is really being changed, it's done
366 * by reseting the chip. To accomplish this we must first cleanup any pending
367 * DMA, then restart stuff.
368*/
369static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
370 struct ath9k_channel *hchan)
371{
372 int r;
373
374 if (sc->sc_flags & SC_OP_INVALID)
375 return -EIO;
376
377 ath9k_ps_wakeup(sc);
378
379 r = ath_reset_internal(sc, hchan, false);
6a6733f2 380
3cbb5dd7 381 ath9k_ps_restore(sc);
9adcf440 382
3989279c 383 return r;
ff37e337
S
384}
385
9f42c2b6
FF
386static void ath_paprd_activate(struct ath_softc *sc)
387{
388 struct ath_hw *ah = sc->sc_ah;
20bd2a09 389 struct ath9k_hw_cal_data *caldata = ah->caldata;
9f42c2b6
FF
390 int chain;
391
20bd2a09 392 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
393 return;
394
395 ath9k_ps_wakeup(sc);
ddfef792 396 ar9003_paprd_enable(ah, false);
9f42c2b6 397 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 398 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
399 continue;
400
20bd2a09 401 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
402 }
403
404 ar9003_paprd_enable(ah, true);
405 ath9k_ps_restore(sc);
406}
407
7607cbe2
FF
408static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
409{
410 struct ieee80211_hw *hw = sc->hw;
411 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
412 struct ath_hw *ah = sc->sc_ah;
413 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
414 struct ath_tx_control txctl;
415 int time_left;
416
417 memset(&txctl, 0, sizeof(txctl));
418 txctl.txq = sc->tx.txq_map[WME_AC_BE];
419
420 memset(tx_info, 0, sizeof(*tx_info));
421 tx_info->band = hw->conf.channel->band;
422 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
423 tx_info->control.rates[0].idx = 0;
424 tx_info->control.rates[0].count = 1;
425 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
426 tx_info->control.rates[1].idx = -1;
427
428 init_completion(&sc->paprd_complete);
7607cbe2 429 txctl.paprd = BIT(chain);
47960077
MSS
430
431 if (ath_tx_start(hw, skb, &txctl) != 0) {
d4bb17c4 432 ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n");
47960077 433 dev_kfree_skb_any(skb);
7607cbe2 434 return false;
47960077 435 }
7607cbe2
FF
436
437 time_left = wait_for_completion_timeout(&sc->paprd_complete,
438 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
439
440 if (!time_left)
d4bb17c4 441 ath_dbg(common, ATH_DBG_CALIBRATE,
7607cbe2
FF
442 "Timeout waiting for paprd training on TX chain %d\n",
443 chain);
444
445 return !!time_left;
446}
447
9f42c2b6
FF
448void ath_paprd_calibrate(struct work_struct *work)
449{
450 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
451 struct ieee80211_hw *hw = sc->hw;
452 struct ath_hw *ah = sc->sc_ah;
453 struct ieee80211_hdr *hdr;
454 struct sk_buff *skb = NULL;
20bd2a09 455 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 456 struct ath_common *common = ath9k_hw_common(ah);
066dae93 457 int ftype;
9f42c2b6
FF
458 int chain_ok = 0;
459 int chain;
460 int len = 1800;
9f42c2b6 461
20bd2a09
FF
462 if (!caldata)
463 return;
464
b942471b
MSS
465 ath9k_ps_wakeup(sc);
466
1bf38661 467 if (ar9003_paprd_init_table(ah) < 0)
b942471b 468 goto fail_paprd;
1bf38661 469
9f42c2b6
FF
470 skb = alloc_skb(len, GFP_KERNEL);
471 if (!skb)
b942471b 472 goto fail_paprd;
9f42c2b6 473
9f42c2b6
FF
474 skb_put(skb, len);
475 memset(skb->data, 0, len);
476 hdr = (struct ieee80211_hdr *)skb->data;
477 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
478 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 479 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
480 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
481 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
482 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
483
9f42c2b6 484 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 485 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
486 continue;
487
488 chain_ok = 0;
9f42c2b6 489
7607cbe2
FF
490 ath_dbg(common, ATH_DBG_CALIBRATE,
491 "Sending PAPRD frame for thermal measurement "
492 "on chain %d\n", chain);
493 if (!ath_paprd_send_frame(sc, skb, chain))
494 goto fail_paprd;
9f42c2b6 495
9f42c2b6 496 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 497
7607cbe2
FF
498 ath_dbg(common, ATH_DBG_CALIBRATE,
499 "Sending PAPRD training frame on chain %d\n", chain);
500 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 501 goto fail_paprd;
9f42c2b6 502
d4bb17c4
MSS
503 if (!ar9003_paprd_is_done(ah)) {
504 ath_dbg(common, ATH_DBG_CALIBRATE,
505 "PAPRD not yet done on chain %d\n", chain);
9f42c2b6 506 break;
d4bb17c4 507 }
9f42c2b6 508
d4bb17c4
MSS
509 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
510 ath_dbg(common, ATH_DBG_CALIBRATE,
511 "PAPRD create curve failed on chain %d\n",
512 chain);
9f42c2b6 513 break;
d4bb17c4 514 }
9f42c2b6
FF
515
516 chain_ok = 1;
517 }
518 kfree_skb(skb);
519
520 if (chain_ok) {
20bd2a09 521 caldata->paprd_done = true;
9f42c2b6
FF
522 ath_paprd_activate(sc);
523 }
524
ca369eb4 525fail_paprd:
9f42c2b6
FF
526 ath9k_ps_restore(sc);
527}
528
ff37e337
S
529/*
530 * This routine performs the periodic noise floor calibration function
531 * that is used to adjust and optimize the chip performance. This
532 * takes environmental changes (location, temperature) into account.
533 * When the task is complete, it reschedules itself depending on the
534 * appropriate interval that was calculated.
535 */
55624204 536void ath_ani_calibrate(unsigned long data)
ff37e337 537{
20977d3e
S
538 struct ath_softc *sc = (struct ath_softc *)data;
539 struct ath_hw *ah = sc->sc_ah;
c46917bb 540 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
541 bool longcal = false;
542 bool shortcal = false;
543 bool aniflag = false;
544 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 545 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 546 unsigned long flags;
6044474e
FF
547
548 if (ah->caldata && ah->caldata->nfcal_interference)
549 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
550 else
551 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 552
20977d3e
S
553 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
554 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 555
1ffc1c61
JM
556 /* Only calibrate if awake */
557 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
558 goto set_timer;
559
560 ath9k_ps_wakeup(sc);
561
ff37e337 562 /* Long calibration runs independently of short calibration. */
6044474e 563 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 564 longcal = true;
226afe68 565 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 566 common->ani.longcal_timer = timestamp;
ff37e337
S
567 }
568
17d7904d 569 /* Short calibration applies only while caldone is false */
3d536acf
LR
570 if (!common->ani.caldone) {
571 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 572 shortcal = true;
226afe68
JP
573 ath_dbg(common, ATH_DBG_ANI,
574 "shortcal @%lu\n", jiffies);
3d536acf
LR
575 common->ani.shortcal_timer = timestamp;
576 common->ani.resetcal_timer = timestamp;
ff37e337
S
577 }
578 } else {
3d536acf 579 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 580 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
581 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
582 if (common->ani.caldone)
583 common->ani.resetcal_timer = timestamp;
ff37e337
S
584 }
585 }
586
587 /* Verify whether we must check ANI */
e36b27af
LR
588 if ((timestamp - common->ani.checkani_timer) >=
589 ah->config.ani_poll_interval) {
ff37e337 590 aniflag = true;
3d536acf 591 common->ani.checkani_timer = timestamp;
ff37e337
S
592 }
593
e62ddec9
MSS
594 /* Call ANI routine if necessary */
595 if (aniflag) {
596 spin_lock_irqsave(&common->cc_lock, flags);
597 ath9k_hw_ani_monitor(ah, ah->curchan);
598 ath_update_survey_stats(sc);
599 spin_unlock_irqrestore(&common->cc_lock, flags);
600 }
ff37e337 601
e62ddec9
MSS
602 /* Perform calibration if necessary */
603 if (longcal || shortcal) {
604 common->ani.caldone =
605 ath9k_hw_calibrate(ah, ah->curchan,
82b2d334 606 ah->rxchainmask, longcal);
ff37e337
S
607 }
608
1ffc1c61
JM
609 ath9k_ps_restore(sc);
610
20977d3e 611set_timer:
ff37e337
S
612 /*
613 * Set timer interval based on previous results.
614 * The interval must be the shortest necessary to satisfy ANI,
615 * short calibration and long calibration.
616 */
cf3af748 617 ath9k_debug_samp_bb_mac(sc);
aac9207e 618 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 619 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
620 cal_interval = min(cal_interval,
621 (u32)ah->config.ani_poll_interval);
3d536acf 622 if (!common->ani.caldone)
20977d3e 623 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 624
3d536acf 625 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
626 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
627 if (!ah->caldata->paprd_done)
9f42c2b6 628 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 629 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
630 ath_paprd_activate(sc);
631 }
ff37e337
S
632}
633
7e1e3864
BG
634static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
635 struct ieee80211_vif *vif)
ff37e337
S
636{
637 struct ath_node *an;
ff37e337
S
638 an = (struct ath_node *)sta->drv_priv;
639
7f010c93
BG
640#ifdef CONFIG_ATH9K_DEBUGFS
641 spin_lock(&sc->nodes_lock);
642 list_add(&an->list, &sc->nodes);
643 spin_unlock(&sc->nodes_lock);
644 an->sta = sta;
7e1e3864 645 an->vif = vif;
7f010c93 646#endif
87792efc 647 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 648 ath_tx_node_init(sc, an);
9e98ac65 649 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
650 sta->ht_cap.ampdu_factor);
651 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
652 }
ff37e337
S
653}
654
655static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
656{
657 struct ath_node *an = (struct ath_node *)sta->drv_priv;
658
7f010c93
BG
659#ifdef CONFIG_ATH9K_DEBUGFS
660 spin_lock(&sc->nodes_lock);
661 list_del(&an->list);
662 spin_unlock(&sc->nodes_lock);
663 an->sta = NULL;
664#endif
665
ff37e337
S
666 if (sc->sc_flags & SC_OP_TXAGGR)
667 ath_tx_node_cleanup(sc, an);
668}
669
9eab61c2 670
55624204 671void ath9k_tasklet(unsigned long data)
ff37e337
S
672{
673 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 674 struct ath_hw *ah = sc->sc_ah;
c46917bb 675 struct ath_common *common = ath9k_hw_common(ah);
af03abec 676
17d7904d 677 u32 status = sc->intrstatus;
b5c80475 678 u32 rxmask;
ff37e337 679
e3927007
FF
680 ath9k_ps_wakeup(sc);
681 spin_lock(&sc->sc_pcu_lock);
682
a4d86d95
RM
683 if ((status & ATH9K_INT_FATAL) ||
684 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF
685#ifdef CONFIG_ATH9K_DEBUGFS
686 enum ath_reset_type type;
687
688 if (status & ATH9K_INT_FATAL)
689 type = RESET_TYPE_FATAL_INT;
690 else
691 type = RESET_TYPE_BB_WATCHDOG;
692
693 RESET_STAT_INC(sc, type);
694#endif
236de514 695 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e3927007 696 goto out;
063d8be3 697 }
ff37e337 698
8b3f4616
FF
699 /*
700 * Only run the baseband hang check if beacons stop working in AP or
701 * IBSS mode, because it has a high false positive rate. For station
702 * mode it should not be necessary, since the upper layers will detect
703 * this through a beacon miss automatically and the following channel
704 * change will trigger a hardware reset anyway
705 */
706 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
707 !ath9k_hw_check_alive(ah))
347809fc
FF
708 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
709
4105f807
RM
710 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
711 /*
712 * TSF sync does not look correct; remain awake to sync with
713 * the next Beacon.
714 */
715 ath_dbg(common, ATH_DBG_PS,
716 "TSFOOR - Sync with next Beacon\n");
e8fe7336 717 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807
RM
718 }
719
b5c80475
FF
720 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
721 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
722 ATH9K_INT_RXORN);
723 else
724 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
725
726 if (status & rxmask) {
b5c80475
FF
727 /* Check for high priority Rx first */
728 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
729 (status & ATH9K_INT_RXHP))
730 ath_rx_tasklet(sc, 0, true);
731
732 ath_rx_tasklet(sc, 0, false);
ff37e337
S
733 }
734
e5003249
VT
735 if (status & ATH9K_INT_TX) {
736 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
737 ath_tx_edma_tasklet(sc);
738 else
739 ath_tx_tasklet(sc);
740 }
063d8be3 741
766ec4a9 742 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
743 if (status & ATH9K_INT_GENTIMER)
744 ath_gen_timer_isr(sc->sc_ah);
745
19686ddf
MSS
746 if (status & ATH9K_INT_MCI)
747 ath_mci_intr(sc);
748
e3927007 749out:
ff37e337 750 /* re-enable hardware interrupt */
4df3071e 751 ath9k_hw_enable_interrupts(ah);
6a6733f2 752
52671e43 753 spin_unlock(&sc->sc_pcu_lock);
153e080d 754 ath9k_ps_restore(sc);
ff37e337
S
755}
756
6baff7f9 757irqreturn_t ath_isr(int irq, void *dev)
ff37e337 758{
063d8be3
S
759#define SCHED_INTR ( \
760 ATH9K_INT_FATAL | \
a4d86d95 761 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
762 ATH9K_INT_RXORN | \
763 ATH9K_INT_RXEOL | \
764 ATH9K_INT_RX | \
b5c80475
FF
765 ATH9K_INT_RXLP | \
766 ATH9K_INT_RXHP | \
063d8be3
S
767 ATH9K_INT_TX | \
768 ATH9K_INT_BMISS | \
769 ATH9K_INT_CST | \
ebb8e1d7 770 ATH9K_INT_TSFOOR | \
40dc5392
MSS
771 ATH9K_INT_GENTIMER | \
772 ATH9K_INT_MCI)
063d8be3 773
ff37e337 774 struct ath_softc *sc = dev;
cbe61d8a 775 struct ath_hw *ah = sc->sc_ah;
b5bfc568 776 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
777 enum ath9k_int status;
778 bool sched = false;
779
063d8be3
S
780 /*
781 * The hardware is not ready/present, don't
782 * touch anything. Note this can happen early
783 * on if the IRQ is shared.
784 */
785 if (sc->sc_flags & SC_OP_INVALID)
786 return IRQ_NONE;
ff37e337 787
063d8be3
S
788
789 /* shared irq, not for us */
790
153e080d 791 if (!ath9k_hw_intrpend(ah))
063d8be3 792 return IRQ_NONE;
063d8be3
S
793
794 /*
795 * Figure out the reason(s) for the interrupt. Note
796 * that the hal returns a pseudo-ISR that may include
797 * bits we haven't explicitly enabled so we mask the
798 * value to insure we only process bits we requested.
799 */
800 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 801 status &= ah->imask; /* discard unasked-for bits */
ff37e337 802
063d8be3
S
803 /*
804 * If there are no status bits set, then this interrupt was not
805 * for me (should have been caught above).
806 */
153e080d 807 if (!status)
063d8be3 808 return IRQ_NONE;
ff37e337 809
063d8be3
S
810 /* Cache the status */
811 sc->intrstatus = status;
812
813 if (status & SCHED_INTR)
814 sched = true;
815
816 /*
817 * If a FATAL or RXORN interrupt is received, we have to reset the
818 * chip immediately.
819 */
b5c80475
FF
820 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
821 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
822 goto chip_reset;
823
08578b8f
LR
824 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
825 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
826
827 spin_lock(&common->cc_lock);
828 ath_hw_cycle_counters_update(common);
08578b8f 829 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
830 spin_unlock(&common->cc_lock);
831
08578b8f
LR
832 goto chip_reset;
833 }
834
063d8be3
S
835 if (status & ATH9K_INT_SWBA)
836 tasklet_schedule(&sc->bcon_tasklet);
837
838 if (status & ATH9K_INT_TXURN)
839 ath9k_hw_updatetxtriglevel(ah, true);
840
0682c9b5
RM
841 if (status & ATH9K_INT_RXEOL) {
842 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 843 ath9k_hw_set_interrupts(ah);
b5c80475
FF
844 }
845
063d8be3 846 if (status & ATH9K_INT_MIB) {
ff37e337 847 /*
063d8be3
S
848 * Disable interrupts until we service the MIB
849 * interrupt; otherwise it will continue to
850 * fire.
ff37e337 851 */
4df3071e 852 ath9k_hw_disable_interrupts(ah);
063d8be3
S
853 /*
854 * Let the hal handle the event. We assume
855 * it will clear whatever condition caused
856 * the interrupt.
857 */
88eac2da 858 spin_lock(&common->cc_lock);
bfc472bb 859 ath9k_hw_proc_mib_event(ah);
88eac2da 860 spin_unlock(&common->cc_lock);
4df3071e 861 ath9k_hw_enable_interrupts(ah);
063d8be3 862 }
ff37e337 863
153e080d
VT
864 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
865 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
866 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
867 goto chip_reset;
063d8be3
S
868 /* Clear RxAbort bit so that we can
869 * receive frames */
9ecdef4b 870 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 871 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 872 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 873 }
063d8be3
S
874
875chip_reset:
ff37e337 876
817e11de
S
877 ath_debug_stat_interrupt(sc, status);
878
ff37e337 879 if (sched) {
4df3071e
FF
880 /* turn off every interrupt */
881 ath9k_hw_disable_interrupts(ah);
ff37e337
S
882 tasklet_schedule(&sc->intr_tq);
883 }
884
885 return IRQ_HANDLED;
063d8be3
S
886
887#undef SCHED_INTR
ff37e337
S
888}
889
5595f119 890static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 891{
cbe61d8a 892 struct ath_hw *ah = sc->sc_ah;
c46917bb 893 struct ath_common *common = ath9k_hw_common(ah);
68a89116 894 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 895 int r;
500c064d 896
3cbb5dd7 897 ath9k_ps_wakeup(sc);
6a6733f2 898 spin_lock_bh(&sc->sc_pcu_lock);
e8fe7336 899 atomic_set(&ah->intr_ref_cnt, -1);
6a6733f2 900
84c87dc8 901 ath9k_hw_configpcipowersave(ah, false);
ae8d2858 902
159cd468 903 if (!ah->curchan)
c344c9cb 904 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 905
20bd2a09 906 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 907 if (r) {
3800276a
JP
908 ath_err(common,
909 "Unable to reset channel (%u MHz), reset status %d\n",
910 channel->center_freq, r);
500c064d 911 }
500c064d 912
9adcf440 913 ath_complete_reset(sc, true);
500c064d
VT
914
915 /* Enable LED */
08fc5c1b 916 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 917 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 918 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 919
6a6733f2
LR
920 spin_unlock_bh(&sc->sc_pcu_lock);
921
3cbb5dd7 922 ath9k_ps_restore(sc);
500c064d
VT
923}
924
68a89116 925void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 926{
cbe61d8a 927 struct ath_hw *ah = sc->sc_ah;
68a89116 928 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 929 int r;
500c064d 930
3cbb5dd7 931 ath9k_ps_wakeup(sc);
7e3514fd 932
9adcf440 933 ath_cancel_work(sc);
6a6733f2 934
9adcf440 935 spin_lock_bh(&sc->sc_pcu_lock);
500c064d 936
982723df
VN
937 /*
938 * Keep the LED on when the radio is disabled
939 * during idle unassociated state.
940 */
941 if (!sc->ps_idle) {
942 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
943 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
944 }
500c064d 945
9adcf440 946 ath_prepare_reset(sc, false, true);
500c064d 947
159cd468 948 if (!ah->curchan)
c344c9cb 949 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 950
20bd2a09 951 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 952 if (r) {
3800276a
JP
953 ath_err(ath9k_hw_common(sc->sc_ah),
954 "Unable to reset channel (%u MHz), reset status %d\n",
955 channel->center_freq, r);
500c064d 956 }
500c064d
VT
957
958 ath9k_hw_phy_disable(ah);
5e848f78 959
84c87dc8 960 ath9k_hw_configpcipowersave(ah, true);
6a6733f2
LR
961
962 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 963 ath9k_ps_restore(sc);
500c064d
VT
964}
965
236de514 966static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 967{
ae8d2858 968 int r;
ff37e337 969
783cd01e 970 ath9k_ps_wakeup(sc);
6a6733f2 971
9adcf440 972 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S
973
974 if (retry_tx) {
975 int i;
976 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
977 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
978 spin_lock_bh(&sc->tx.txq[i].axq_lock);
979 ath_txq_schedule(sc, &sc->tx.txq[i]);
980 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
981 }
982 }
983 }
984
783cd01e 985 ath9k_ps_restore(sc);
2ab81d4a 986
ae8d2858 987 return r;
ff37e337
S
988}
989
236de514
FF
990void ath_reset_work(struct work_struct *work)
991{
992 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
993
236de514 994 ath_reset(sc, true);
236de514
FF
995}
996
e8cfe9f8
FF
997void ath_hw_check(struct work_struct *work)
998{
999 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
1000 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1001 unsigned long flags;
1002 int busy;
1003
1004 ath9k_ps_wakeup(sc);
1005 if (ath9k_hw_check_alive(sc->sc_ah))
1006 goto out;
1007
1008 spin_lock_irqsave(&common->cc_lock, flags);
1009 busy = ath_update_survey_stats(sc);
1010 spin_unlock_irqrestore(&common->cc_lock, flags);
1011
1012 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
1013 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
1014 if (busy >= 99) {
030d6294
FF
1015 if (++sc->hw_busy_count >= 3) {
1016 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
9adcf440 1017 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
030d6294 1018 }
e8cfe9f8
FF
1019
1020 } else if (busy >= 0)
1021 sc->hw_busy_count = 0;
1022
1023out:
1024 ath9k_ps_restore(sc);
1025}
1026
1027static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
1028{
1029 static int count;
1030 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1031
1032 if (pll_sqsum >= 0x40000) {
1033 count++;
1034 if (count == 3) {
1035 /* Rx is hung for more than 500ms. Reset it */
1036 ath_dbg(common, ATH_DBG_RESET,
1037 "Possible RX hang, resetting");
030d6294 1038 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
9adcf440 1039 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e8cfe9f8
FF
1040 count = 0;
1041 }
1042 } else
1043 count = 0;
1044}
1045
1046void ath_hw_pll_work(struct work_struct *work)
1047{
1048 struct ath_softc *sc = container_of(work, struct ath_softc,
1049 hw_pll_work.work);
1050 u32 pll_sqsum;
1051
1052 if (AR_SREV_9485(sc->sc_ah)) {
1053
1054 ath9k_ps_wakeup(sc);
1055 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
1056 ath9k_ps_restore(sc);
1057
1058 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
1059
1060 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
1061 }
1062}
1063
ff37e337
S
1064/**********************/
1065/* mac80211 callbacks */
1066/**********************/
1067
8feceb67 1068static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1069{
9ac58615 1070 struct ath_softc *sc = hw->priv;
af03abec 1071 struct ath_hw *ah = sc->sc_ah;
c46917bb 1072 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1073 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1074 struct ath9k_channel *init_channel;
82880a7c 1075 int r;
f078f209 1076
226afe68
JP
1077 ath_dbg(common, ATH_DBG_CONFIG,
1078 "Starting driver with initial channel: %d MHz\n",
1079 curchan->center_freq);
f078f209 1080
f62d816f
FF
1081 ath9k_ps_wakeup(sc);
1082
141b38b6
S
1083 mutex_lock(&sc->mutex);
1084
8feceb67 1085 /* setup initial channel */
82880a7c 1086 sc->chan_idx = curchan->hw_value;
f078f209 1087
c344c9cb 1088 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1089
1090 /* Reset SERDES registers */
84c87dc8 1091 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
1092
1093 /*
1094 * The basic interface to setting the hardware in a good
1095 * state is ``reset''. On return the hardware is known to
1096 * be powered up and with interrupts disabled. This must
1097 * be followed by initialization of the appropriate bits
1098 * and then setup of the interrupt mask.
1099 */
4bdd1e97 1100 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1101 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1102 if (r) {
3800276a
JP
1103 ath_err(common,
1104 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1105 r, curchan->center_freq);
4bdd1e97 1106 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1107 goto mutex_unlock;
ff37e337 1108 }
ff37e337 1109
ff37e337 1110 /* Setup our intr mask. */
b5c80475
FF
1111 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1112 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1113 ATH9K_INT_GLOBAL;
1114
1115 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1116 ah->imask |= ATH9K_INT_RXHP |
1117 ATH9K_INT_RXLP |
1118 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1119 else
1120 ah->imask |= ATH9K_INT_RX;
ff37e337 1121
364734fa 1122 ah->imask |= ATH9K_INT_GTT;
ff37e337 1123
af03abec 1124 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1125 ah->imask |= ATH9K_INT_CST;
ff37e337 1126
40dc5392
MSS
1127 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1128 ah->imask |= ATH9K_INT_MCI;
1129
ff37e337 1130 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1131 sc->sc_ah->is_monitoring = false;
ff37e337
S
1132
1133 /* Disable BMISS interrupt when we're not associated */
3069168c 1134 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
ff37e337 1135
9adcf440
FF
1136 if (!ath_complete_reset(sc, false)) {
1137 r = -EIO;
1138 spin_unlock_bh(&sc->sc_pcu_lock);
1139 goto mutex_unlock;
1140 }
ff37e337 1141
9adcf440 1142 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 1143
766ec4a9
LR
1144 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1145 !ah->btcoex_hw.enabled) {
7dc181c2
RM
1146 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI))
1147 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1148 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1149 ath9k_hw_btcoex_enable(ah);
f985ad12 1150
766ec4a9 1151 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1152 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1153 }
1154
8060e169
VT
1155 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1156 common->bus_ops->extn_synch_en(common);
1157
141b38b6
S
1158mutex_unlock:
1159 mutex_unlock(&sc->mutex);
1160
f62d816f
FF
1161 ath9k_ps_restore(sc);
1162
ae8d2858 1163 return r;
f078f209
LR
1164}
1165
7bb45683 1166static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1167{
9ac58615 1168 struct ath_softc *sc = hw->priv;
c46917bb 1169 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1170 struct ath_tx_control txctl;
1bc14880 1171 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1172
96148326 1173 if (sc->ps_enabled) {
dc8c4585
JM
1174 /*
1175 * mac80211 does not set PM field for normal data frames, so we
1176 * need to update that based on the current PS mode.
1177 */
1178 if (ieee80211_is_data(hdr->frame_control) &&
1179 !ieee80211_is_nullfunc(hdr->frame_control) &&
1180 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1181 ath_dbg(common, ATH_DBG_PS,
1182 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1183 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1184 }
1185 }
1186
c8e8868e
FF
1187 /*
1188 * Cannot tx while the hardware is in full sleep, it first needs a full
1189 * chip reset to recover from that
1190 */
1191 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP))
1192 goto exit;
1193
9a23f9ca
JM
1194 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1195 /*
1196 * We are using PS-Poll and mac80211 can request TX while in
1197 * power save mode. Need to wake up hardware for the TX to be
1198 * completed and if needed, also for RX of buffered frames.
1199 */
9a23f9ca 1200 ath9k_ps_wakeup(sc);
fdf76622
VT
1201 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1202 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1203 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1204 ath_dbg(common, ATH_DBG_PS,
1205 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1206 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1207 } else {
226afe68
JP
1208 ath_dbg(common, ATH_DBG_PS,
1209 "Wake up to complete TX\n");
1b04b930 1210 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1211 }
1212 /*
1213 * The actual restore operation will happen only after
1214 * the sc_flags bit is cleared. We are just dropping
1215 * the ps_usecount here.
1216 */
1217 ath9k_ps_restore(sc);
1218 }
1219
528f0c6b 1220 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1221 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1222
226afe68 1223 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1224
c52f33d0 1225 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1226 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1227 goto exit;
8feceb67
VT
1228 }
1229
7bb45683 1230 return;
528f0c6b
S
1231exit:
1232 dev_kfree_skb_any(skb);
f078f209
LR
1233}
1234
8feceb67 1235static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1236{
9ac58615 1237 struct ath_softc *sc = hw->priv;
af03abec 1238 struct ath_hw *ah = sc->sc_ah;
c46917bb 1239 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1240
4c483817
S
1241 mutex_lock(&sc->mutex);
1242
9adcf440 1243 ath_cancel_work(sc);
c94dbff7 1244
9c84b797 1245 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1246 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1247 mutex_unlock(&sc->mutex);
9c84b797
S
1248 return;
1249 }
8feceb67 1250
3867cf6a
S
1251 /* Ensure HW is awake when we try to shut it down. */
1252 ath9k_ps_wakeup(sc);
1253
766ec4a9 1254 if (ah->btcoex_hw.enabled) {
af03abec 1255 ath9k_hw_btcoex_disable(ah);
766ec4a9 1256 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1257 ath9k_btcoex_timer_pause(sc);
7dc181c2 1258 ath_mci_flush_profile(&sc->btcoex.mci);
1773912b
VT
1259 }
1260
6a6733f2
LR
1261 spin_lock_bh(&sc->sc_pcu_lock);
1262
203043f5
SG
1263 /* prevent tasklets to enable interrupts once we disable them */
1264 ah->imask &= ~ATH9K_INT_GLOBAL;
1265
ff37e337
S
1266 /* make sure h/w will not generate any interrupt
1267 * before setting the invalid flag. */
4df3071e 1268 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1269
1270 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1271 ath_drain_all_txq(sc, false);
ff37e337 1272 ath_stoprecv(sc);
af03abec 1273 ath9k_hw_phy_disable(ah);
6a6733f2 1274 } else
b77f483f 1275 sc->rx.rxlink = NULL;
ff37e337 1276
0d95521e
FF
1277 if (sc->rx.frag) {
1278 dev_kfree_skb_any(sc->rx.frag);
1279 sc->rx.frag = NULL;
1280 }
1281
ff37e337 1282 /* disable HAL and put h/w to sleep */
af03abec 1283 ath9k_hw_disable(ah);
6a6733f2
LR
1284
1285 spin_unlock_bh(&sc->sc_pcu_lock);
1286
203043f5
SG
1287 /* we can now sync irq and kill any running tasklets, since we already
1288 * disabled interrupts and not holding a spin lock */
1289 synchronize_irq(sc->irq);
1290 tasklet_kill(&sc->intr_tq);
1291 tasklet_kill(&sc->bcon_tasklet);
1292
3867cf6a
S
1293 ath9k_ps_restore(sc);
1294
a08e7ade
LR
1295 sc->ps_idle = true;
1296 ath_radio_disable(sc, hw);
ff37e337
S
1297
1298 sc->sc_flags |= SC_OP_INVALID;
500c064d 1299
141b38b6
S
1300 mutex_unlock(&sc->mutex);
1301
226afe68 1302 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1303}
1304
4801416c
BG
1305bool ath9k_uses_beacons(int type)
1306{
1307 switch (type) {
1308 case NL80211_IFTYPE_AP:
1309 case NL80211_IFTYPE_ADHOC:
1310 case NL80211_IFTYPE_MESH_POINT:
1311 return true;
1312 default:
1313 return false;
1314 }
1315}
1316
1317static void ath9k_reclaim_beacon(struct ath_softc *sc,
1318 struct ieee80211_vif *vif)
f078f209 1319{
1ed32e4f 1320 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1321
014cf3bb 1322 ath9k_set_beaconing_status(sc, false);
4801416c 1323 ath_beacon_return(sc, avp);
014cf3bb 1324 ath9k_set_beaconing_status(sc, true);
4801416c 1325 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1326}
1327
1328static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1329{
1330 struct ath9k_vif_iter_data *iter_data = data;
1331 int i;
1332
1333 if (iter_data->hw_macaddr)
1334 for (i = 0; i < ETH_ALEN; i++)
1335 iter_data->mask[i] &=
1336 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1337
1ed32e4f 1338 switch (vif->type) {
4801416c
BG
1339 case NL80211_IFTYPE_AP:
1340 iter_data->naps++;
f078f209 1341 break;
4801416c
BG
1342 case NL80211_IFTYPE_STATION:
1343 iter_data->nstations++;
e51f3eff 1344 break;
05c914fe 1345 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1346 iter_data->nadhocs++;
1347 break;
9cb5412b 1348 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1349 iter_data->nmeshes++;
1350 break;
1351 case NL80211_IFTYPE_WDS:
1352 iter_data->nwds++;
f078f209
LR
1353 break;
1354 default:
4801416c
BG
1355 iter_data->nothers++;
1356 break;
f078f209 1357 }
4801416c 1358}
f078f209 1359
4801416c
BG
1360/* Called with sc->mutex held. */
1361void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1362 struct ieee80211_vif *vif,
1363 struct ath9k_vif_iter_data *iter_data)
1364{
9ac58615 1365 struct ath_softc *sc = hw->priv;
4801416c
BG
1366 struct ath_hw *ah = sc->sc_ah;
1367 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1368
4801416c
BG
1369 /*
1370 * Use the hardware MAC address as reference, the hardware uses it
1371 * together with the BSSID mask when matching addresses.
1372 */
1373 memset(iter_data, 0, sizeof(*iter_data));
1374 iter_data->hw_macaddr = common->macaddr;
1375 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1376
4801416c
BG
1377 if (vif)
1378 ath9k_vif_iter(iter_data, vif->addr, vif);
1379
1380 /* Get list of all active MAC addresses */
4801416c
BG
1381 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1382 iter_data);
4801416c 1383}
8ca21f01 1384
4801416c
BG
1385/* Called with sc->mutex held. */
1386static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1387 struct ieee80211_vif *vif)
1388{
9ac58615 1389 struct ath_softc *sc = hw->priv;
4801416c
BG
1390 struct ath_hw *ah = sc->sc_ah;
1391 struct ath_common *common = ath9k_hw_common(ah);
1392 struct ath9k_vif_iter_data iter_data;
8ca21f01 1393
4801416c 1394 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1395
4801416c
BG
1396 /* Set BSSID mask. */
1397 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1398 ath_hw_setbssidmask(common);
1399
1400 /* Set op-mode & TSF */
1401 if (iter_data.naps > 0) {
3069168c 1402 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1403 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1404 ah->opmode = NL80211_IFTYPE_AP;
1405 } else {
1406 ath9k_hw_set_tsfadjust(ah, 0);
1407 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1408
fd5999cf
JC
1409 if (iter_data.nmeshes)
1410 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1411 else if (iter_data.nwds)
4801416c
BG
1412 ah->opmode = NL80211_IFTYPE_AP;
1413 else if (iter_data.nadhocs)
1414 ah->opmode = NL80211_IFTYPE_ADHOC;
1415 else
1416 ah->opmode = NL80211_IFTYPE_STATION;
1417 }
5640b08e 1418
4e30ffa2
VN
1419 /*
1420 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1421 */
4801416c 1422 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1423 if (ah->config.enable_ani)
1424 ah->imask |= ATH9K_INT_MIB;
3069168c 1425 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1426 } else {
1427 ah->imask &= ~ATH9K_INT_MIB;
1428 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1429 }
1430
72d874c6 1431 ath9k_hw_set_interrupts(ah);
4e30ffa2 1432
4801416c 1433 /* Set up ANI */
2e5ef459 1434 if (iter_data.naps > 0) {
729da390 1435 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1436
1437 if (!common->disable_ani) {
1438 sc->sc_flags |= SC_OP_ANI_RUN;
1439 ath_start_ani(common);
1440 }
1441
f60c49b6
RM
1442 } else {
1443 sc->sc_flags &= ~SC_OP_ANI_RUN;
1444 del_timer_sync(&common->ani.timer);
6c3118e2 1445 }
4801416c 1446}
6f255425 1447
4801416c
BG
1448/* Called with sc->mutex held, vif counts set up properly. */
1449static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1450 struct ieee80211_vif *vif)
1451{
9ac58615 1452 struct ath_softc *sc = hw->priv;
4801416c
BG
1453
1454 ath9k_calculate_summary_state(hw, vif);
1455
1456 if (ath9k_uses_beacons(vif->type)) {
1457 int error;
4801416c
BG
1458 /* This may fail because upper levels do not have beacons
1459 * properly configured yet. That's OK, we assume it
1460 * will be properly configured and then we will be notified
1461 * in the info_changed method and set up beacons properly
1462 * there.
1463 */
014cf3bb 1464 ath9k_set_beaconing_status(sc, false);
9ac58615 1465 error = ath_beacon_alloc(sc, vif);
391bd1c4 1466 if (!error)
4801416c 1467 ath_beacon_config(sc, vif);
014cf3bb 1468 ath9k_set_beaconing_status(sc, true);
4801416c 1469 }
f078f209
LR
1470}
1471
4801416c
BG
1472
1473static int ath9k_add_interface(struct ieee80211_hw *hw,
1474 struct ieee80211_vif *vif)
6b3b991d 1475{
9ac58615 1476 struct ath_softc *sc = hw->priv;
4801416c
BG
1477 struct ath_hw *ah = sc->sc_ah;
1478 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1479 int ret = 0;
6b3b991d 1480
96f372c9 1481 ath9k_ps_wakeup(sc);
4801416c 1482 mutex_lock(&sc->mutex);
6b3b991d 1483
4801416c
BG
1484 switch (vif->type) {
1485 case NL80211_IFTYPE_STATION:
1486 case NL80211_IFTYPE_WDS:
1487 case NL80211_IFTYPE_ADHOC:
1488 case NL80211_IFTYPE_AP:
1489 case NL80211_IFTYPE_MESH_POINT:
1490 break;
1491 default:
1492 ath_err(common, "Interface type %d not yet supported\n",
1493 vif->type);
1494 ret = -EOPNOTSUPP;
1495 goto out;
1496 }
6b3b991d 1497
4801416c
BG
1498 if (ath9k_uses_beacons(vif->type)) {
1499 if (sc->nbcnvifs >= ATH_BCBUF) {
1500 ath_err(common, "Not enough beacon buffers when adding"
1501 " new interface of type: %i\n",
1502 vif->type);
1503 ret = -ENOBUFS;
1504 goto out;
1505 }
1506 }
1507
59575d1c
RM
1508 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1509 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1510 sc->nvifs > 0)) {
4801416c
BG
1511 ath_err(common, "Cannot create ADHOC interface when other"
1512 " interfaces already exist.\n");
1513 ret = -EINVAL;
1514 goto out;
6b3b991d 1515 }
4801416c
BG
1516
1517 ath_dbg(common, ATH_DBG_CONFIG,
1518 "Attach a VIF of type: %d\n", vif->type);
1519
4801416c
BG
1520 sc->nvifs++;
1521
1522 ath9k_do_vif_add_setup(hw, vif);
1523out:
1524 mutex_unlock(&sc->mutex);
96f372c9 1525 ath9k_ps_restore(sc);
4801416c 1526 return ret;
6b3b991d
RM
1527}
1528
1529static int ath9k_change_interface(struct ieee80211_hw *hw,
1530 struct ieee80211_vif *vif,
1531 enum nl80211_iftype new_type,
1532 bool p2p)
1533{
9ac58615 1534 struct ath_softc *sc = hw->priv;
6b3b991d 1535 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1536 int ret = 0;
6b3b991d
RM
1537
1538 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1539 mutex_lock(&sc->mutex);
96f372c9 1540 ath9k_ps_wakeup(sc);
6b3b991d 1541
4801416c
BG
1542 /* See if new interface type is valid. */
1543 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1544 (sc->nvifs > 1)) {
1545 ath_err(common, "When using ADHOC, it must be the only"
1546 " interface.\n");
1547 ret = -EINVAL;
1548 goto out;
1549 }
1550
1551 if (ath9k_uses_beacons(new_type) &&
1552 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1553 if (sc->nbcnvifs >= ATH_BCBUF) {
1554 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1555 ret = -ENOBUFS;
1556 goto out;
6b3b991d 1557 }
6b3b991d 1558 }
4801416c
BG
1559
1560 /* Clean up old vif stuff */
1561 if (ath9k_uses_beacons(vif->type))
1562 ath9k_reclaim_beacon(sc, vif);
1563
1564 /* Add new settings */
6b3b991d
RM
1565 vif->type = new_type;
1566 vif->p2p = p2p;
1567
4801416c 1568 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1569out:
96f372c9 1570 ath9k_ps_restore(sc);
6b3b991d 1571 mutex_unlock(&sc->mutex);
6dab55bf 1572 return ret;
6b3b991d
RM
1573}
1574
8feceb67 1575static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1576 struct ieee80211_vif *vif)
f078f209 1577{
9ac58615 1578 struct ath_softc *sc = hw->priv;
c46917bb 1579 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1580
226afe68 1581 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1582
96f372c9 1583 ath9k_ps_wakeup(sc);
141b38b6
S
1584 mutex_lock(&sc->mutex);
1585
4801416c 1586 sc->nvifs--;
580f0b8a 1587
8feceb67 1588 /* Reclaim beacon resources */
4801416c 1589 if (ath9k_uses_beacons(vif->type))
6b3b991d 1590 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1591
4801416c 1592 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1593
1594 mutex_unlock(&sc->mutex);
96f372c9 1595 ath9k_ps_restore(sc);
f078f209
LR
1596}
1597
fbab7390 1598static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1599{
3069168c
PR
1600 struct ath_hw *ah = sc->sc_ah;
1601
3f7c5c10 1602 sc->ps_enabled = true;
3069168c
PR
1603 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1604 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1605 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1606 ath9k_hw_set_interrupts(ah);
3f7c5c10 1607 }
fdf76622 1608 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1609 }
3f7c5c10
SB
1610}
1611
845d708e
SB
1612static void ath9k_disable_ps(struct ath_softc *sc)
1613{
1614 struct ath_hw *ah = sc->sc_ah;
1615
1616 sc->ps_enabled = false;
1617 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1618 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1619 ath9k_hw_setrxabort(ah, 0);
1620 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1621 PS_WAIT_FOR_CAB |
1622 PS_WAIT_FOR_PSPOLL_DATA |
1623 PS_WAIT_FOR_TX_ACK);
1624 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1625 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1626 ath9k_hw_set_interrupts(ah);
845d708e
SB
1627 }
1628 }
1629
1630}
1631
e8975581 1632static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1633{
9ac58615 1634 struct ath_softc *sc = hw->priv;
3430098a
FF
1635 struct ath_hw *ah = sc->sc_ah;
1636 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1637 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1638 bool disable_radio = false;
f078f209 1639
aa33de09 1640 mutex_lock(&sc->mutex);
141b38b6 1641
194b7c13
LR
1642 /*
1643 * Leave this as the first check because we need to turn on the
1644 * radio if it was disabled before prior to processing the rest
1645 * of the changes. Likewise we must only disable the radio towards
1646 * the end.
1647 */
64839170 1648 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF
1649 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1650 if (!sc->ps_idle) {
68a89116 1651 ath_radio_enable(sc, hw);
226afe68
JP
1652 ath_dbg(common, ATH_DBG_CONFIG,
1653 "not-idle: enabling radio\n");
7545daf4
FF
1654 } else {
1655 disable_radio = true;
64839170
LR
1656 }
1657 }
1658
e7824a50
LR
1659 /*
1660 * We just prepare to enable PS. We have to wait until our AP has
1661 * ACK'd our null data frame to disable RX otherwise we'll ignore
1662 * those ACKs and end up retransmitting the same null data frames.
1663 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1664 */
3cbb5dd7 1665 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1666 unsigned long flags;
1667 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1668 if (conf->flags & IEEE80211_CONF_PS)
1669 ath9k_enable_ps(sc);
845d708e
SB
1670 else
1671 ath9k_disable_ps(sc);
8ab2cd09 1672 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1673 }
1674
199afd9d
S
1675 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1676 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1677 ath_dbg(common, ATH_DBG_CONFIG,
1678 "Monitor mode is enabled\n");
5f841b41
RM
1679 sc->sc_ah->is_monitoring = true;
1680 } else {
226afe68
JP
1681 ath_dbg(common, ATH_DBG_CONFIG,
1682 "Monitor mode is disabled\n");
5f841b41 1683 sc->sc_ah->is_monitoring = false;
199afd9d
S
1684 }
1685 }
1686
4797938c 1687 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1688 struct ieee80211_channel *curchan = hw->conf.channel;
e338a85e 1689 struct ath9k_channel old_chan;
5f8e077c 1690 int pos = curchan->hw_value;
3430098a
FF
1691 int old_pos = -1;
1692 unsigned long flags;
1693
1694 if (ah->curchan)
1695 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1696
5ee08656
FF
1697 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1698 sc->sc_flags |= SC_OP_OFFCHANNEL;
1699 else
1700 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1701
8c79a610
BG
1702 ath_dbg(common, ATH_DBG_CONFIG,
1703 "Set channel: %d MHz type: %d\n",
1704 curchan->center_freq, conf->channel_type);
f078f209 1705
3430098a
FF
1706 /* update survey stats for the old channel before switching */
1707 spin_lock_irqsave(&common->cc_lock, flags);
1708 ath_update_survey_stats(sc);
1709 spin_unlock_irqrestore(&common->cc_lock, flags);
1710
e338a85e
RM
1711 /*
1712 * Preserve the current channel values, before updating
1713 * the same channel
1714 */
1715 if (old_pos == pos) {
1716 memcpy(&old_chan, &sc->sc_ah->channels[pos],
1717 sizeof(struct ath9k_channel));
1718 ah->curchan = &old_chan;
1719 }
1720
1721 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1722 curchan, conf->channel_type);
1723
3430098a
FF
1724 /*
1725 * If the operating channel changes, change the survey in-use flags
1726 * along with it.
1727 * Reset the survey data for the new channel, unless we're switching
1728 * back to the operating channel from an off-channel operation.
1729 */
1730 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1731 sc->cur_survey != &sc->survey[pos]) {
1732
1733 if (sc->cur_survey)
1734 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1735
1736 sc->cur_survey = &sc->survey[pos];
1737
1738 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1739 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1740 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1741 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1742 }
1743
0e2dedf9 1744 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1745 ath_err(common, "Unable to set channel\n");
aa33de09 1746 mutex_unlock(&sc->mutex);
e11602b7
S
1747 return -EINVAL;
1748 }
3430098a
FF
1749
1750 /*
1751 * The most recent snapshot of channel->noisefloor for the old
1752 * channel is only available after the hardware reset. Copy it to
1753 * the survey stats now.
1754 */
1755 if (old_pos >= 0)
1756 ath_update_survey_nf(sc, old_pos);
094d05dc 1757 }
f078f209 1758
c9f6a656 1759 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG
1760 ath_dbg(common, ATH_DBG_CONFIG,
1761 "Set power: %d\n", conf->power_level);
17d7904d 1762 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1763 ath9k_ps_wakeup(sc);
5048e8c3
RM
1764 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1765 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1766 ath9k_ps_restore(sc);
c9f6a656 1767 }
f078f209 1768
64839170 1769 if (disable_radio) {
226afe68 1770 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1771 ath_radio_disable(sc, hw);
64839170
LR
1772 }
1773
aa33de09 1774 mutex_unlock(&sc->mutex);
141b38b6 1775
f078f209
LR
1776 return 0;
1777}
1778
8feceb67
VT
1779#define SUPPORTED_FILTERS \
1780 (FIF_PROMISC_IN_BSS | \
1781 FIF_ALLMULTI | \
1782 FIF_CONTROL | \
af6a3fc7 1783 FIF_PSPOLL | \
8feceb67
VT
1784 FIF_OTHER_BSS | \
1785 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1786 FIF_PROBE_REQ | \
8feceb67 1787 FIF_FCSFAIL)
c83be688 1788
8feceb67
VT
1789/* FIXME: sc->sc_full_reset ? */
1790static void ath9k_configure_filter(struct ieee80211_hw *hw,
1791 unsigned int changed_flags,
1792 unsigned int *total_flags,
3ac64bee 1793 u64 multicast)
8feceb67 1794{
9ac58615 1795 struct ath_softc *sc = hw->priv;
8feceb67 1796 u32 rfilt;
f078f209 1797
8feceb67
VT
1798 changed_flags &= SUPPORTED_FILTERS;
1799 *total_flags &= SUPPORTED_FILTERS;
f078f209 1800
b77f483f 1801 sc->rx.rxfilter = *total_flags;
aa68aeaa 1802 ath9k_ps_wakeup(sc);
8feceb67
VT
1803 rfilt = ath_calcrxfilter(sc);
1804 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1805 ath9k_ps_restore(sc);
f078f209 1806
226afe68
JP
1807 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1808 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1809}
f078f209 1810
4ca77860
JB
1811static int ath9k_sta_add(struct ieee80211_hw *hw,
1812 struct ieee80211_vif *vif,
1813 struct ieee80211_sta *sta)
8feceb67 1814{
9ac58615 1815 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1816 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1817 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1818 struct ieee80211_key_conf ps_key = { };
f078f209 1819
7e1e3864 1820 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1821
1822 if (vif->type != NL80211_IFTYPE_AP &&
1823 vif->type != NL80211_IFTYPE_AP_VLAN)
1824 return 0;
1825
93ae2dd2 1826 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1827
1828 return 0;
1829}
1830
93ae2dd2
FF
1831static void ath9k_del_ps_key(struct ath_softc *sc,
1832 struct ieee80211_vif *vif,
1833 struct ieee80211_sta *sta)
1834{
1835 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1836 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1837 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1838
1839 if (!an->ps_key)
1840 return;
1841
1842 ath_key_delete(common, &ps_key);
1843}
1844
4ca77860
JB
1845static int ath9k_sta_remove(struct ieee80211_hw *hw,
1846 struct ieee80211_vif *vif,
1847 struct ieee80211_sta *sta)
1848{
9ac58615 1849 struct ath_softc *sc = hw->priv;
4ca77860 1850
93ae2dd2 1851 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1852 ath_node_detach(sc, sta);
1853
1854 return 0;
f078f209
LR
1855}
1856
5519541d
FF
1857static void ath9k_sta_notify(struct ieee80211_hw *hw,
1858 struct ieee80211_vif *vif,
1859 enum sta_notify_cmd cmd,
1860 struct ieee80211_sta *sta)
1861{
1862 struct ath_softc *sc = hw->priv;
1863 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1864
1865 switch (cmd) {
1866 case STA_NOTIFY_SLEEP:
1867 an->sleeping = true;
042ec453 1868 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF
1869 break;
1870 case STA_NOTIFY_AWAKE:
1871 an->sleeping = false;
1872 ath_tx_aggr_wakeup(sc, an);
1873 break;
1874 }
1875}
1876
8a3a3c85
EP
1877static int ath9k_conf_tx(struct ieee80211_hw *hw,
1878 struct ieee80211_vif *vif, u16 queue,
8feceb67 1879 const struct ieee80211_tx_queue_params *params)
f078f209 1880{
9ac58615 1881 struct ath_softc *sc = hw->priv;
c46917bb 1882 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1883 struct ath_txq *txq;
8feceb67 1884 struct ath9k_tx_queue_info qi;
066dae93 1885 int ret = 0;
f078f209 1886
8feceb67
VT
1887 if (queue >= WME_NUM_AC)
1888 return 0;
f078f209 1889
066dae93
FF
1890 txq = sc->tx.txq_map[queue];
1891
96f372c9 1892 ath9k_ps_wakeup(sc);
141b38b6
S
1893 mutex_lock(&sc->mutex);
1894
1ffb0610
S
1895 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1896
8feceb67
VT
1897 qi.tqi_aifs = params->aifs;
1898 qi.tqi_cwmin = params->cw_min;
1899 qi.tqi_cwmax = params->cw_max;
1900 qi.tqi_burstTime = params->txop;
f078f209 1901
226afe68
JP
1902 ath_dbg(common, ATH_DBG_CONFIG,
1903 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1904 queue, txq->axq_qnum, params->aifs, params->cw_min,
1905 params->cw_max, params->txop);
f078f209 1906
066dae93 1907 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1908 if (ret)
3800276a 1909 ath_err(common, "TXQ Update failed\n");
f078f209 1910
94db2936 1911 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1912 if (queue == WME_AC_BE && !ret)
94db2936
VN
1913 ath_beaconq_config(sc);
1914
141b38b6 1915 mutex_unlock(&sc->mutex);
96f372c9 1916 ath9k_ps_restore(sc);
141b38b6 1917
8feceb67
VT
1918 return ret;
1919}
f078f209 1920
8feceb67
VT
1921static int ath9k_set_key(struct ieee80211_hw *hw,
1922 enum set_key_cmd cmd,
dc822b5d
JB
1923 struct ieee80211_vif *vif,
1924 struct ieee80211_sta *sta,
8feceb67
VT
1925 struct ieee80211_key_conf *key)
1926{
9ac58615 1927 struct ath_softc *sc = hw->priv;
c46917bb 1928 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1929 int ret = 0;
f078f209 1930
3e6109c5 1931 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1932 return -ENOSPC;
1933
cfdc9a8b
JM
1934 if (vif->type == NL80211_IFTYPE_ADHOC &&
1935 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1936 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1937 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1938 /*
1939 * For now, disable hw crypto for the RSN IBSS group keys. This
1940 * could be optimized in the future to use a modified key cache
1941 * design to support per-STA RX GTK, but until that gets
1942 * implemented, use of software crypto for group addressed
1943 * frames is a acceptable to allow RSN IBSS to be used.
1944 */
1945 return -EOPNOTSUPP;
1946 }
1947
141b38b6 1948 mutex_lock(&sc->mutex);
3cbb5dd7 1949 ath9k_ps_wakeup(sc);
226afe68 1950 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1951
8feceb67
VT
1952 switch (cmd) {
1953 case SET_KEY:
93ae2dd2
FF
1954 if (sta)
1955 ath9k_del_ps_key(sc, vif, sta);
1956
040e539e 1957 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1958 if (ret >= 0) {
1959 key->hw_key_idx = ret;
8feceb67
VT
1960 /* push IV and Michael MIC generation to stack */
1961 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1962 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1963 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1964 if (sc->sc_ah->sw_mgmt_crypto &&
1965 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1966 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1967 ret = 0;
8feceb67
VT
1968 }
1969 break;
1970 case DISABLE_KEY:
040e539e 1971 ath_key_delete(common, key);
8feceb67
VT
1972 break;
1973 default:
1974 ret = -EINVAL;
1975 }
f078f209 1976
3cbb5dd7 1977 ath9k_ps_restore(sc);
141b38b6
S
1978 mutex_unlock(&sc->mutex);
1979
8feceb67
VT
1980 return ret;
1981}
4f5ef75b
RM
1982static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1983{
1984 struct ath_softc *sc = data;
1985 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1986 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1987 struct ath_vif *avp = (void *)vif->drv_priv;
1988
2e5ef459
RM
1989 /*
1990 * Skip iteration if primary station vif's bss info
1991 * was not changed
1992 */
1993 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1994 return;
1995
1996 if (bss_conf->assoc) {
1997 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1998 avp->primary_sta_vif = true;
4f5ef75b
RM
1999 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2000 common->curaid = bss_conf->aid;
2001 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459 2002 ath_dbg(common, ATH_DBG_CONFIG,
99e4d43a
RM
2003 "Bss Info ASSOC %d, bssid: %pM\n",
2004 bss_conf->aid, common->curbssid);
2e5ef459
RM
2005 ath_beacon_config(sc, vif);
2006 /*
2007 * Request a re-configuration of Beacon related timers
2008 * on the receipt of the first Beacon frame (i.e.,
2009 * after time sync with the AP).
2010 */
2011 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
2012 /* Reset rssi stats */
2013 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
2014 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 2015
05c0be2f
MSS
2016 if (!common->disable_ani) {
2017 sc->sc_flags |= SC_OP_ANI_RUN;
2018 ath_start_ani(common);
2019 }
2020
4f5ef75b
RM
2021 }
2022}
2023
2024static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2025{
2026 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2027 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2028 struct ath_vif *avp = (void *)vif->drv_priv;
2029
2e5ef459
RM
2030 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2031 return;
2032
4f5ef75b
RM
2033 /* Reconfigure bss info */
2034 if (avp->primary_sta_vif && !bss_conf->assoc) {
99e4d43a
RM
2035 ath_dbg(common, ATH_DBG_CONFIG,
2036 "Bss Info DISASSOC %d, bssid %pM\n",
2037 common->curaid, common->curbssid);
2038 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
2039 avp->primary_sta_vif = false;
2040 memset(common->curbssid, 0, ETH_ALEN);
2041 common->curaid = 0;
2042 }
2043
2044 ieee80211_iterate_active_interfaces_atomic(
2045 sc->hw, ath9k_bss_iter, sc);
2046
2047 /*
2048 * None of station vifs are associated.
2049 * Clear bssid & aid
2050 */
2e5ef459 2051 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 2052 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
2053 /* Stop ANI */
2054 sc->sc_flags &= ~SC_OP_ANI_RUN;
2055 del_timer_sync(&common->ani.timer);
d2c71c20 2056 memset(&sc->caldata, 0, sizeof(sc->caldata));
99e4d43a 2057 }
4f5ef75b 2058}
f078f209 2059
8feceb67
VT
2060static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2061 struct ieee80211_vif *vif,
2062 struct ieee80211_bss_conf *bss_conf,
2063 u32 changed)
2064{
9ac58615 2065 struct ath_softc *sc = hw->priv;
2d0ddec5 2066 struct ath_hw *ah = sc->sc_ah;
1510718d 2067 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2068 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2069 int slottime;
c6089ccc 2070 int error;
f078f209 2071
96f372c9 2072 ath9k_ps_wakeup(sc);
141b38b6
S
2073 mutex_lock(&sc->mutex);
2074
c6089ccc 2075 if (changed & BSS_CHANGED_BSSID) {
4f5ef75b 2076 ath9k_config_bss(sc, vif);
2d0ddec5 2077
226afe68
JP
2078 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2079 common->curbssid, common->curaid);
c6089ccc 2080 }
2d0ddec5 2081
2e5ef459
RM
2082 if (changed & BSS_CHANGED_IBSS) {
2083 /* There can be only one vif available */
2084 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2085 common->curaid = bss_conf->aid;
2086 ath9k_hw_write_associd(sc->sc_ah);
2087
2088 if (bss_conf->ibss_joined) {
2089 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
2090
2091 if (!common->disable_ani) {
2092 sc->sc_flags |= SC_OP_ANI_RUN;
2093 ath_start_ani(common);
2094 }
2095
2e5ef459
RM
2096 } else {
2097 sc->sc_flags &= ~SC_OP_ANI_RUN;
2098 del_timer_sync(&common->ani.timer);
2099 }
2100 }
2101
c6089ccc
S
2102 /* Enable transmission of beacons (AP, IBSS, MESH) */
2103 if ((changed & BSS_CHANGED_BEACON) ||
2104 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2105 ath9k_set_beaconing_status(sc, false);
9ac58615 2106 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
2107 if (!error)
2108 ath_beacon_config(sc, vif);
014cf3bb 2109 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
2110 }
2111
2112 if (changed & BSS_CHANGED_ERP_SLOT) {
2113 if (bss_conf->use_short_slot)
2114 slottime = 9;
2115 else
2116 slottime = 20;
2117 if (vif->type == NL80211_IFTYPE_AP) {
2118 /*
2119 * Defer update, so that connected stations can adjust
2120 * their settings at the same time.
2121 * See beacon.c for more details
2122 */
2123 sc->beacon.slottime = slottime;
2124 sc->beacon.updateslot = UPDATE;
2125 } else {
2126 ah->slottime = slottime;
2127 ath9k_hw_init_global_settings(ah);
2128 }
2d0ddec5
JB
2129 }
2130
c6089ccc 2131 /* Disable transmission of beacons */
014cf3bb
RM
2132 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2133 !bss_conf->enable_beacon) {
2134 ath9k_set_beaconing_status(sc, false);
2135 avp->is_bslot_active = false;
2136 ath9k_set_beaconing_status(sc, true);
2137 }
2d0ddec5 2138
c6089ccc 2139 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S
2140 /*
2141 * In case of AP mode, the HW TSF has to be reset
2142 * when the beacon interval changes.
2143 */
2144 if (vif->type == NL80211_IFTYPE_AP) {
2145 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2146 ath9k_set_beaconing_status(sc, false);
9ac58615 2147 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
2148 if (!error)
2149 ath_beacon_config(sc, vif);
014cf3bb 2150 ath9k_set_beaconing_status(sc, true);
99e4d43a 2151 } else
c6089ccc 2152 ath_beacon_config(sc, vif);
2d0ddec5
JB
2153 }
2154
8feceb67 2155 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
2156 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2157 bss_conf->use_short_preamble);
8feceb67
VT
2158 if (bss_conf->use_short_preamble)
2159 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2160 else
2161 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2162 }
f078f209 2163
8feceb67 2164 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
2165 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2166 bss_conf->use_cts_prot);
8feceb67
VT
2167 if (bss_conf->use_cts_prot &&
2168 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2169 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2170 else
2171 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2172 }
f078f209 2173
141b38b6 2174 mutex_unlock(&sc->mutex);
96f372c9 2175 ath9k_ps_restore(sc);
8feceb67 2176}
f078f209 2177
37a41b4a 2178static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 2179{
9ac58615 2180 struct ath_softc *sc = hw->priv;
8feceb67 2181 u64 tsf;
f078f209 2182
141b38b6 2183 mutex_lock(&sc->mutex);
9abbfb27 2184 ath9k_ps_wakeup(sc);
141b38b6 2185 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2186 ath9k_ps_restore(sc);
141b38b6 2187 mutex_unlock(&sc->mutex);
f078f209 2188
8feceb67
VT
2189 return tsf;
2190}
f078f209 2191
37a41b4a
EP
2192static void ath9k_set_tsf(struct ieee80211_hw *hw,
2193 struct ieee80211_vif *vif,
2194 u64 tsf)
3b5d665b 2195{
9ac58615 2196 struct ath_softc *sc = hw->priv;
3b5d665b 2197
141b38b6 2198 mutex_lock(&sc->mutex);
9abbfb27 2199 ath9k_ps_wakeup(sc);
141b38b6 2200 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2201 ath9k_ps_restore(sc);
141b38b6 2202 mutex_unlock(&sc->mutex);
3b5d665b
AF
2203}
2204
37a41b4a 2205static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 2206{
9ac58615 2207 struct ath_softc *sc = hw->priv;
c83be688 2208
141b38b6 2209 mutex_lock(&sc->mutex);
21526d57
LR
2210
2211 ath9k_ps_wakeup(sc);
141b38b6 2212 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2213 ath9k_ps_restore(sc);
2214
141b38b6 2215 mutex_unlock(&sc->mutex);
8feceb67 2216}
f078f209 2217
8feceb67 2218static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2219 struct ieee80211_vif *vif,
141b38b6
S
2220 enum ieee80211_ampdu_mlme_action action,
2221 struct ieee80211_sta *sta,
0b01f030 2222 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2223{
9ac58615 2224 struct ath_softc *sc = hw->priv;
8feceb67 2225 int ret = 0;
f078f209 2226
85ad181e
JB
2227 local_bh_disable();
2228
8feceb67
VT
2229 switch (action) {
2230 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2231 if (!(sc->sc_flags & SC_OP_RXAGGR))
2232 ret = -ENOTSUPP;
8feceb67
VT
2233 break;
2234 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2235 break;
2236 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2237 if (!(sc->sc_flags & SC_OP_TXAGGR))
2238 return -EOPNOTSUPP;
2239
8b685ba9 2240 ath9k_ps_wakeup(sc);
231c3a1f
FF
2241 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2242 if (!ret)
2243 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2244 ath9k_ps_restore(sc);
8feceb67
VT
2245 break;
2246 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2247 ath9k_ps_wakeup(sc);
f83da965 2248 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2249 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2250 ath9k_ps_restore(sc);
8feceb67 2251 break;
b1720231 2252 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2253 ath9k_ps_wakeup(sc);
8469cdef 2254 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2255 ath9k_ps_restore(sc);
8469cdef 2256 break;
8feceb67 2257 default:
3800276a 2258 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2259 }
2260
85ad181e
JB
2261 local_bh_enable();
2262
8feceb67 2263 return ret;
f078f209
LR
2264}
2265
62dad5b0
BP
2266static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2267 struct survey_info *survey)
2268{
9ac58615 2269 struct ath_softc *sc = hw->priv;
3430098a 2270 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2271 struct ieee80211_supported_band *sband;
3430098a
FF
2272 struct ieee80211_channel *chan;
2273 unsigned long flags;
2274 int pos;
2275
2276 spin_lock_irqsave(&common->cc_lock, flags);
2277 if (idx == 0)
2278 ath_update_survey_stats(sc);
39162dbe
FF
2279
2280 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2281 if (sband && idx >= sband->n_channels) {
2282 idx -= sband->n_channels;
2283 sband = NULL;
2284 }
62dad5b0 2285
39162dbe
FF
2286 if (!sband)
2287 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2288
3430098a
FF
2289 if (!sband || idx >= sband->n_channels) {
2290 spin_unlock_irqrestore(&common->cc_lock, flags);
2291 return -ENOENT;
4f1a5a4b 2292 }
62dad5b0 2293
3430098a
FF
2294 chan = &sband->channels[idx];
2295 pos = chan->hw_value;
2296 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2297 survey->channel = chan;
2298 spin_unlock_irqrestore(&common->cc_lock, flags);
2299
62dad5b0
BP
2300 return 0;
2301}
2302
e239d859
FF
2303static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2304{
9ac58615 2305 struct ath_softc *sc = hw->priv;
e239d859
FF
2306 struct ath_hw *ah = sc->sc_ah;
2307
2308 mutex_lock(&sc->mutex);
2309 ah->coverage_class = coverage_class;
8b2a3827
MSS
2310
2311 ath9k_ps_wakeup(sc);
e239d859 2312 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS
2313 ath9k_ps_restore(sc);
2314
e239d859
FF
2315 mutex_unlock(&sc->mutex);
2316}
2317
69081624
VT
2318static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2319{
69081624 2320 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2321 struct ath_hw *ah = sc->sc_ah;
2322 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
2323 int timeout = 200; /* ms */
2324 int i, j;
2f6fc351 2325 bool drain_txq;
69081624
VT
2326
2327 mutex_lock(&sc->mutex);
69081624
VT
2328 cancel_delayed_work_sync(&sc->tx_complete_work);
2329
6a6b3f3e
MSS
2330 if (ah->ah_flags & AH_UNPLUGGED) {
2331 ath_dbg(common, ATH_DBG_ANY, "Device has been unplugged!\n");
2332 mutex_unlock(&sc->mutex);
2333 return;
2334 }
2335
99aa55b6
MSS
2336 if (sc->sc_flags & SC_OP_INVALID) {
2337 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
2338 mutex_unlock(&sc->mutex);
2339 return;
2340 }
2341
86271e46
FF
2342 if (drop)
2343 timeout = 1;
69081624 2344
86271e46 2345 for (j = 0; j < timeout; j++) {
108697c4 2346 bool npend = false;
86271e46
FF
2347
2348 if (j)
2349 usleep_range(1000, 2000);
69081624 2350
86271e46
FF
2351 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2352 if (!ATH_TXQ_SETUP(sc, i))
2353 continue;
2354
108697c4
MSS
2355 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2356
2357 if (npend)
2358 break;
69081624 2359 }
86271e46
FF
2360
2361 if (!npend)
2362 goto out;
69081624
VT
2363 }
2364
51513906 2365 ath9k_ps_wakeup(sc);
2f6fc351
RM
2366 spin_lock_bh(&sc->sc_pcu_lock);
2367 drain_txq = ath_drain_all_txq(sc, false);
9adcf440
FF
2368 spin_unlock_bh(&sc->sc_pcu_lock);
2369
2f6fc351 2370 if (!drain_txq)
69081624 2371 ath_reset(sc, false);
9adcf440 2372
51513906 2373 ath9k_ps_restore(sc);
d78f4b3e
SB
2374 ieee80211_wake_queues(hw);
2375
86271e46 2376out:
69081624
VT
2377 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2378 mutex_unlock(&sc->mutex);
2379}
2380
15b91e83
VN
2381static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2382{
2383 struct ath_softc *sc = hw->priv;
2384 int i;
2385
2386 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2387 if (!ATH_TXQ_SETUP(sc, i))
2388 continue;
2389
2390 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2391 return true;
2392 }
2393 return false;
2394}
2395
5595f119 2396static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2397{
2398 struct ath_softc *sc = hw->priv;
2399 struct ath_hw *ah = sc->sc_ah;
2400 struct ieee80211_vif *vif;
2401 struct ath_vif *avp;
2402 struct ath_buf *bf;
2403 struct ath_tx_status ts;
2404 int status;
2405
2406 vif = sc->beacon.bslot[0];
2407 if (!vif)
2408 return 0;
2409
2410 avp = (void *)vif->drv_priv;
2411 if (!avp->is_bslot_active)
2412 return 0;
2413
2414 if (!sc->beacon.tx_processed) {
2415 tasklet_disable(&sc->bcon_tasklet);
2416
2417 bf = avp->av_bcbuf;
2418 if (!bf || !bf->bf_mpdu)
2419 goto skip;
2420
2421 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2422 if (status == -EINPROGRESS)
2423 goto skip;
2424
2425 sc->beacon.tx_processed = true;
2426 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2427
2428skip:
2429 tasklet_enable(&sc->bcon_tasklet);
2430 }
2431
2432 return sc->beacon.tx_last;
2433}
2434
52c94f41
MSS
2435static int ath9k_get_stats(struct ieee80211_hw *hw,
2436 struct ieee80211_low_level_stats *stats)
2437{
2438 struct ath_softc *sc = hw->priv;
2439 struct ath_hw *ah = sc->sc_ah;
2440 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2441
2442 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2443 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2444 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2445 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2446 return 0;
2447}
2448
43c35284
FF
2449static u32 fill_chainmask(u32 cap, u32 new)
2450{
2451 u32 filled = 0;
2452 int i;
2453
2454 for (i = 0; cap && new; i++, cap >>= 1) {
2455 if (!(cap & BIT(0)))
2456 continue;
2457
2458 if (new & BIT(0))
2459 filled |= BIT(i);
2460
2461 new >>= 1;
2462 }
2463
2464 return filled;
2465}
2466
2467static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2468{
2469 struct ath_softc *sc = hw->priv;
2470 struct ath_hw *ah = sc->sc_ah;
2471
2472 if (!rx_ant || !tx_ant)
2473 return -EINVAL;
2474
2475 sc->ant_rx = rx_ant;
2476 sc->ant_tx = tx_ant;
2477
2478 if (ah->caps.rx_chainmask == 1)
2479 return 0;
2480
2481 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2482 if (AR_SREV_9100(ah))
2483 ah->rxchainmask = 0x7;
2484 else
2485 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2486
2487 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2488 ath9k_reload_chainmask_settings(sc);
2489
2490 return 0;
2491}
2492
2493static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2494{
2495 struct ath_softc *sc = hw->priv;
2496
2497 *tx_ant = sc->ant_tx;
2498 *rx_ant = sc->ant_rx;
2499 return 0;
2500}
2501
6baff7f9 2502struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2503 .tx = ath9k_tx,
2504 .start = ath9k_start,
2505 .stop = ath9k_stop,
2506 .add_interface = ath9k_add_interface,
6b3b991d 2507 .change_interface = ath9k_change_interface,
8feceb67
VT
2508 .remove_interface = ath9k_remove_interface,
2509 .config = ath9k_config,
8feceb67 2510 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2511 .sta_add = ath9k_sta_add,
2512 .sta_remove = ath9k_sta_remove,
5519541d 2513 .sta_notify = ath9k_sta_notify,
8feceb67 2514 .conf_tx = ath9k_conf_tx,
8feceb67 2515 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2516 .set_key = ath9k_set_key,
8feceb67 2517 .get_tsf = ath9k_get_tsf,
3b5d665b 2518 .set_tsf = ath9k_set_tsf,
8feceb67 2519 .reset_tsf = ath9k_reset_tsf,
4233df6b 2520 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2521 .get_survey = ath9k_get_survey,
3b319aae 2522 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2523 .set_coverage_class = ath9k_set_coverage_class,
69081624 2524 .flush = ath9k_flush,
15b91e83 2525 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2526 .tx_last_beacon = ath9k_tx_last_beacon,
2527 .get_stats = ath9k_get_stats,
43c35284
FF
2528 .set_antenna = ath9k_set_antenna,
2529 .get_antenna = ath9k_get_antenna,
8feceb67 2530};