ath9k: Fix PS wrappers and enabling LED
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
114 unsigned long flags;
115
116 spin_lock_irqsave(&sc->sc_pm_lock, flags);
117 if (--sc->ps_usecount != 0)
118 goto unlock;
119
898c914a
FF
120 spin_lock(&common->cc_lock);
121 ath_hw_cycle_counters_update(common);
122 spin_unlock(&common->cc_lock);
123
1dbfd9d4
VN
124 if (sc->ps_idle)
125 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
126 else if (sc->ps_enabled &&
127 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
128 PS_WAIT_FOR_CAB |
129 PS_WAIT_FOR_PSPOLL_DATA |
130 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 131 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
132
133 unlock:
134 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
135}
136
05c0be2f 137void ath_start_ani(struct ath_common *common)
5ee08656
FF
138{
139 struct ath_hw *ah = common->ah;
140 unsigned long timestamp = jiffies_to_msecs(jiffies);
141 struct ath_softc *sc = (struct ath_softc *) common->priv;
142
143 if (!(sc->sc_flags & SC_OP_ANI_RUN))
144 return;
145
146 if (sc->sc_flags & SC_OP_OFFCHANNEL)
147 return;
148
149 common->ani.longcal_timer = timestamp;
150 common->ani.shortcal_timer = timestamp;
151 common->ani.checkani_timer = timestamp;
152
153 mod_timer(&common->ani.timer,
154 jiffies +
155 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
156}
157
3430098a
FF
158static void ath_update_survey_nf(struct ath_softc *sc, int channel)
159{
160 struct ath_hw *ah = sc->sc_ah;
161 struct ath9k_channel *chan = &ah->channels[channel];
162 struct survey_info *survey = &sc->survey[channel];
163
164 if (chan->noisefloor) {
165 survey->filled |= SURVEY_INFO_NOISE_DBM;
f749b946 166 survey->noise = ath9k_hw_getchan_noise(ah, chan);
3430098a
FF
167 }
168}
169
cb8d61de
FF
170/*
171 * Updates the survey statistics and returns the busy time since last
172 * update in %, if the measurement duration was long enough for the
173 * result to be useful, -1 otherwise.
174 */
175static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
176{
177 struct ath_hw *ah = sc->sc_ah;
178 struct ath_common *common = ath9k_hw_common(ah);
179 int pos = ah->curchan - &ah->channels[0];
180 struct survey_info *survey = &sc->survey[pos];
181 struct ath_cycle_counters *cc = &common->cc_survey;
182 unsigned int div = common->clockrate * 1000;
cb8d61de 183 int ret = 0;
3430098a 184
0845735e 185 if (!ah->curchan)
cb8d61de 186 return -1;
0845735e 187
898c914a
FF
188 if (ah->power_mode == ATH9K_PM_AWAKE)
189 ath_hw_cycle_counters_update(common);
3430098a
FF
190
191 if (cc->cycles > 0) {
192 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
193 SURVEY_INFO_CHANNEL_TIME_BUSY |
194 SURVEY_INFO_CHANNEL_TIME_RX |
195 SURVEY_INFO_CHANNEL_TIME_TX;
196 survey->channel_time += cc->cycles / div;
197 survey->channel_time_busy += cc->rx_busy / div;
198 survey->channel_time_rx += cc->rx_frame / div;
199 survey->channel_time_tx += cc->tx_frame / div;
200 }
cb8d61de
FF
201
202 if (cc->cycles < div)
203 return -1;
204
205 if (cc->cycles > 0)
206 ret = cc->rx_busy * 100 / cc->cycles;
207
3430098a
FF
208 memset(cc, 0, sizeof(*cc));
209
210 ath_update_survey_nf(sc, pos);
cb8d61de
FF
211
212 return ret;
3430098a
FF
213}
214
9adcf440 215static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 216{
5ee08656
FF
217 cancel_work_sync(&sc->paprd_work);
218 cancel_work_sync(&sc->hw_check_work);
219 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 220 cancel_delayed_work_sync(&sc->hw_pll_work);
9adcf440 221}
5ee08656 222
9adcf440
FF
223static void ath_cancel_work(struct ath_softc *sc)
224{
225 __ath_cancel_work(sc);
226 cancel_work_sync(&sc->hw_reset_work);
227}
3cbb5dd7 228
9adcf440
FF
229static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
230{
231 struct ath_hw *ah = sc->sc_ah;
232 struct ath_common *common = ath9k_hw_common(ah);
233 bool ret;
6a6733f2 234
9adcf440 235 ieee80211_stop_queues(sc->hw);
5e848f78 236
9adcf440
FF
237 sc->hw_busy_count = 0;
238 del_timer_sync(&common->ani.timer);
ff37e337 239
9adcf440
FF
240 ath9k_debug_samp_bb_mac(sc);
241 ath9k_hw_disable_interrupts(ah);
8b3f4616 242
9adcf440 243 ret = ath_drain_all_txq(sc, retry_tx);
ff37e337 244
9adcf440
FF
245 if (!ath_stoprecv(sc))
246 ret = false;
c0d7c7af 247
9adcf440
FF
248 if (!flush) {
249 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
250 ath_rx_tasklet(sc, 0, true);
251 ath_rx_tasklet(sc, 0, false);
252 } else {
253 ath_flushrecv(sc);
254 }
20bd2a09 255
9adcf440
FF
256 return ret;
257}
ff37e337 258
9adcf440
FF
259static bool ath_complete_reset(struct ath_softc *sc, bool start)
260{
261 struct ath_hw *ah = sc->sc_ah;
262 struct ath_common *common = ath9k_hw_common(ah);
c0d7c7af 263
c0d7c7af 264 if (ath_startrecv(sc) != 0) {
3800276a 265 ath_err(common, "Unable to restart recv logic\n");
9adcf440 266 return false;
c0d7c7af
LR
267 }
268
5048e8c3
RM
269 ath9k_cmn_update_txpow(ah, sc->curtxpow,
270 sc->config.txpowlimit, &sc->curtxpow);
3069168c 271 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 272 ath9k_hw_enable_interrupts(ah);
3989279c 273
9adcf440 274 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
1186488b 275 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 276 ath_set_beacon(sc);
9adcf440 277
5ee08656 278 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 279 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
05c0be2f
MSS
280 if (!common->disable_ani)
281 ath_start_ani(common);
5ee08656
FF
282 }
283
43c35284
FF
284 if (ath9k_hw_ops(ah)->antdiv_comb_conf_get && sc->ant_rx != 3) {
285 struct ath_hw_antcomb_conf div_ant_conf;
286 u8 lna_conf;
287
288 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
289
290 if (sc->ant_rx == 1)
291 lna_conf = ATH_ANT_DIV_COMB_LNA1;
292 else
293 lna_conf = ATH_ANT_DIV_COMB_LNA2;
294 div_ant_conf.main_lna_conf = lna_conf;
295 div_ant_conf.alt_lna_conf = lna_conf;
296
297 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
298 }
299
9adcf440
FF
300 ieee80211_wake_queues(sc->hw);
301
302 return true;
303}
304
305static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
306 bool retry_tx)
307{
308 struct ath_hw *ah = sc->sc_ah;
309 struct ath_common *common = ath9k_hw_common(ah);
310 struct ath9k_hw_cal_data *caldata = NULL;
311 bool fastcc = true;
312 bool flush = false;
313 int r;
314
315 __ath_cancel_work(sc);
316
317 spin_lock_bh(&sc->sc_pcu_lock);
92460412 318
9adcf440
FF
319 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
320 fastcc = false;
321 caldata = &sc->caldata;
322 }
323
324 if (!hchan) {
325 fastcc = false;
326 flush = true;
327 hchan = ah->curchan;
328 }
329
330 if (fastcc && !ath9k_hw_check_alive(ah))
331 fastcc = false;
332
333 if (!ath_prepare_reset(sc, retry_tx, flush))
334 fastcc = false;
335
336 ath_dbg(common, ATH_DBG_CONFIG,
337 "Reset to %u MHz, HT40: %d fastcc: %d\n",
338 hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS |
339 CHANNEL_HT40PLUS)),
340 fastcc);
341
342 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
343 if (r) {
344 ath_err(common,
345 "Unable to reset channel, reset status %d\n", r);
346 goto out;
347 }
348
349 if (!ath_complete_reset(sc, true))
350 r = -EIO;
351
352out:
6a6733f2 353 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF
354 return r;
355}
356
357
358/*
359 * Set/change channels. If the channel is really being changed, it's done
360 * by reseting the chip. To accomplish this we must first cleanup any pending
361 * DMA, then restart stuff.
362*/
363static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
364 struct ath9k_channel *hchan)
365{
366 int r;
367
368 if (sc->sc_flags & SC_OP_INVALID)
369 return -EIO;
370
371 ath9k_ps_wakeup(sc);
372
373 r = ath_reset_internal(sc, hchan, false);
6a6733f2 374
3cbb5dd7 375 ath9k_ps_restore(sc);
9adcf440 376
3989279c 377 return r;
ff37e337
S
378}
379
9f42c2b6
FF
380static void ath_paprd_activate(struct ath_softc *sc)
381{
382 struct ath_hw *ah = sc->sc_ah;
20bd2a09 383 struct ath9k_hw_cal_data *caldata = ah->caldata;
9f42c2b6
FF
384 int chain;
385
20bd2a09 386 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
387 return;
388
389 ath9k_ps_wakeup(sc);
ddfef792 390 ar9003_paprd_enable(ah, false);
9f42c2b6 391 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 392 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
393 continue;
394
20bd2a09 395 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
396 }
397
398 ar9003_paprd_enable(ah, true);
399 ath9k_ps_restore(sc);
400}
401
7607cbe2
FF
402static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
403{
404 struct ieee80211_hw *hw = sc->hw;
405 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
406 struct ath_hw *ah = sc->sc_ah;
407 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
408 struct ath_tx_control txctl;
409 int time_left;
410
411 memset(&txctl, 0, sizeof(txctl));
412 txctl.txq = sc->tx.txq_map[WME_AC_BE];
413
414 memset(tx_info, 0, sizeof(*tx_info));
415 tx_info->band = hw->conf.channel->band;
416 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
417 tx_info->control.rates[0].idx = 0;
418 tx_info->control.rates[0].count = 1;
419 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
420 tx_info->control.rates[1].idx = -1;
421
422 init_completion(&sc->paprd_complete);
7607cbe2 423 txctl.paprd = BIT(chain);
47960077
MSS
424
425 if (ath_tx_start(hw, skb, &txctl) != 0) {
d4bb17c4 426 ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n");
47960077 427 dev_kfree_skb_any(skb);
7607cbe2 428 return false;
47960077 429 }
7607cbe2
FF
430
431 time_left = wait_for_completion_timeout(&sc->paprd_complete,
432 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
433
434 if (!time_left)
d4bb17c4 435 ath_dbg(common, ATH_DBG_CALIBRATE,
7607cbe2
FF
436 "Timeout waiting for paprd training on TX chain %d\n",
437 chain);
438
439 return !!time_left;
440}
441
9f42c2b6
FF
442void ath_paprd_calibrate(struct work_struct *work)
443{
444 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
445 struct ieee80211_hw *hw = sc->hw;
446 struct ath_hw *ah = sc->sc_ah;
447 struct ieee80211_hdr *hdr;
448 struct sk_buff *skb = NULL;
20bd2a09 449 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 450 struct ath_common *common = ath9k_hw_common(ah);
066dae93 451 int ftype;
9f42c2b6
FF
452 int chain_ok = 0;
453 int chain;
454 int len = 1800;
9f42c2b6 455
20bd2a09
FF
456 if (!caldata)
457 return;
458
b942471b
MSS
459 ath9k_ps_wakeup(sc);
460
1bf38661 461 if (ar9003_paprd_init_table(ah) < 0)
b942471b 462 goto fail_paprd;
1bf38661 463
9f42c2b6
FF
464 skb = alloc_skb(len, GFP_KERNEL);
465 if (!skb)
b942471b 466 goto fail_paprd;
9f42c2b6 467
9f42c2b6
FF
468 skb_put(skb, len);
469 memset(skb->data, 0, len);
470 hdr = (struct ieee80211_hdr *)skb->data;
471 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
472 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 473 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
474 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
475 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
476 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
477
9f42c2b6 478 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 479 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
480 continue;
481
482 chain_ok = 0;
9f42c2b6 483
7607cbe2
FF
484 ath_dbg(common, ATH_DBG_CALIBRATE,
485 "Sending PAPRD frame for thermal measurement "
486 "on chain %d\n", chain);
487 if (!ath_paprd_send_frame(sc, skb, chain))
488 goto fail_paprd;
9f42c2b6 489
9f42c2b6 490 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 491
7607cbe2
FF
492 ath_dbg(common, ATH_DBG_CALIBRATE,
493 "Sending PAPRD training frame on chain %d\n", chain);
494 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 495 goto fail_paprd;
9f42c2b6 496
d4bb17c4
MSS
497 if (!ar9003_paprd_is_done(ah)) {
498 ath_dbg(common, ATH_DBG_CALIBRATE,
499 "PAPRD not yet done on chain %d\n", chain);
9f42c2b6 500 break;
d4bb17c4 501 }
9f42c2b6 502
d4bb17c4
MSS
503 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
504 ath_dbg(common, ATH_DBG_CALIBRATE,
505 "PAPRD create curve failed on chain %d\n",
506 chain);
9f42c2b6 507 break;
d4bb17c4 508 }
9f42c2b6
FF
509
510 chain_ok = 1;
511 }
512 kfree_skb(skb);
513
514 if (chain_ok) {
20bd2a09 515 caldata->paprd_done = true;
9f42c2b6
FF
516 ath_paprd_activate(sc);
517 }
518
ca369eb4 519fail_paprd:
9f42c2b6
FF
520 ath9k_ps_restore(sc);
521}
522
ff37e337
S
523/*
524 * This routine performs the periodic noise floor calibration function
525 * that is used to adjust and optimize the chip performance. This
526 * takes environmental changes (location, temperature) into account.
527 * When the task is complete, it reschedules itself depending on the
528 * appropriate interval that was calculated.
529 */
55624204 530void ath_ani_calibrate(unsigned long data)
ff37e337 531{
20977d3e
S
532 struct ath_softc *sc = (struct ath_softc *)data;
533 struct ath_hw *ah = sc->sc_ah;
c46917bb 534 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
535 bool longcal = false;
536 bool shortcal = false;
537 bool aniflag = false;
538 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 539 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 540 unsigned long flags;
6044474e
FF
541
542 if (ah->caldata && ah->caldata->nfcal_interference)
543 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
544 else
545 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 546
20977d3e
S
547 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
548 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 549
1ffc1c61
JM
550 /* Only calibrate if awake */
551 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
552 goto set_timer;
553
554 ath9k_ps_wakeup(sc);
555
ff37e337 556 /* Long calibration runs independently of short calibration. */
6044474e 557 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 558 longcal = true;
226afe68 559 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 560 common->ani.longcal_timer = timestamp;
ff37e337
S
561 }
562
17d7904d 563 /* Short calibration applies only while caldone is false */
3d536acf
LR
564 if (!common->ani.caldone) {
565 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 566 shortcal = true;
226afe68
JP
567 ath_dbg(common, ATH_DBG_ANI,
568 "shortcal @%lu\n", jiffies);
3d536acf
LR
569 common->ani.shortcal_timer = timestamp;
570 common->ani.resetcal_timer = timestamp;
ff37e337
S
571 }
572 } else {
3d536acf 573 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 574 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
575 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
576 if (common->ani.caldone)
577 common->ani.resetcal_timer = timestamp;
ff37e337
S
578 }
579 }
580
581 /* Verify whether we must check ANI */
e36b27af
LR
582 if ((timestamp - common->ani.checkani_timer) >=
583 ah->config.ani_poll_interval) {
ff37e337 584 aniflag = true;
3d536acf 585 common->ani.checkani_timer = timestamp;
ff37e337
S
586 }
587
e62ddec9
MSS
588 /* Call ANI routine if necessary */
589 if (aniflag) {
590 spin_lock_irqsave(&common->cc_lock, flags);
591 ath9k_hw_ani_monitor(ah, ah->curchan);
592 ath_update_survey_stats(sc);
593 spin_unlock_irqrestore(&common->cc_lock, flags);
594 }
ff37e337 595
e62ddec9
MSS
596 /* Perform calibration if necessary */
597 if (longcal || shortcal) {
598 common->ani.caldone =
599 ath9k_hw_calibrate(ah, ah->curchan,
82b2d334 600 ah->rxchainmask, longcal);
ff37e337
S
601 }
602
1ffc1c61
JM
603 ath9k_ps_restore(sc);
604
20977d3e 605set_timer:
ff37e337
S
606 /*
607 * Set timer interval based on previous results.
608 * The interval must be the shortest necessary to satisfy ANI,
609 * short calibration and long calibration.
610 */
cf3af748 611 ath9k_debug_samp_bb_mac(sc);
aac9207e 612 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 613 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
614 cal_interval = min(cal_interval,
615 (u32)ah->config.ani_poll_interval);
3d536acf 616 if (!common->ani.caldone)
20977d3e 617 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 618
3d536acf 619 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
620 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
621 if (!ah->caldata->paprd_done)
9f42c2b6 622 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 623 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
624 ath_paprd_activate(sc);
625 }
ff37e337
S
626}
627
ff37e337
S
628static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
629{
630 struct ath_node *an;
ff37e337
S
631 an = (struct ath_node *)sta->drv_priv;
632
7f010c93
BG
633#ifdef CONFIG_ATH9K_DEBUGFS
634 spin_lock(&sc->nodes_lock);
635 list_add(&an->list, &sc->nodes);
636 spin_unlock(&sc->nodes_lock);
637 an->sta = sta;
638#endif
87792efc 639 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 640 ath_tx_node_init(sc, an);
9e98ac65 641 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
642 sta->ht_cap.ampdu_factor);
643 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
644 }
ff37e337
S
645}
646
647static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
648{
649 struct ath_node *an = (struct ath_node *)sta->drv_priv;
650
7f010c93
BG
651#ifdef CONFIG_ATH9K_DEBUGFS
652 spin_lock(&sc->nodes_lock);
653 list_del(&an->list);
654 spin_unlock(&sc->nodes_lock);
655 an->sta = NULL;
656#endif
657
ff37e337
S
658 if (sc->sc_flags & SC_OP_TXAGGR)
659 ath_tx_node_cleanup(sc, an);
660}
661
9eab61c2 662
55624204 663void ath9k_tasklet(unsigned long data)
ff37e337
S
664{
665 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 666 struct ath_hw *ah = sc->sc_ah;
c46917bb 667 struct ath_common *common = ath9k_hw_common(ah);
af03abec 668
17d7904d 669 u32 status = sc->intrstatus;
b5c80475 670 u32 rxmask;
ff37e337 671
a4d86d95
RM
672 if ((status & ATH9K_INT_FATAL) ||
673 (status & ATH9K_INT_BB_WATCHDOG)) {
236de514 674 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
ff37e337 675 return;
063d8be3 676 }
ff37e337 677
783cd01e 678 ath9k_ps_wakeup(sc);
52671e43 679 spin_lock(&sc->sc_pcu_lock);
6a6733f2 680
8b3f4616
FF
681 /*
682 * Only run the baseband hang check if beacons stop working in AP or
683 * IBSS mode, because it has a high false positive rate. For station
684 * mode it should not be necessary, since the upper layers will detect
685 * this through a beacon miss automatically and the following channel
686 * change will trigger a hardware reset anyway
687 */
688 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
689 !ath9k_hw_check_alive(ah))
347809fc
FF
690 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
691
4105f807
RM
692 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
693 /*
694 * TSF sync does not look correct; remain awake to sync with
695 * the next Beacon.
696 */
697 ath_dbg(common, ATH_DBG_PS,
698 "TSFOOR - Sync with next Beacon\n");
e8fe7336 699 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807
RM
700 }
701
b5c80475
FF
702 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
703 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
704 ATH9K_INT_RXORN);
705 else
706 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
707
708 if (status & rxmask) {
b5c80475
FF
709 /* Check for high priority Rx first */
710 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
711 (status & ATH9K_INT_RXHP))
712 ath_rx_tasklet(sc, 0, true);
713
714 ath_rx_tasklet(sc, 0, false);
ff37e337
S
715 }
716
e5003249
VT
717 if (status & ATH9K_INT_TX) {
718 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
719 ath_tx_edma_tasklet(sc);
720 else
721 ath_tx_tasklet(sc);
722 }
063d8be3 723
766ec4a9 724 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
725 if (status & ATH9K_INT_GENTIMER)
726 ath_gen_timer_isr(sc->sc_ah);
727
ff37e337 728 /* re-enable hardware interrupt */
4df3071e 729 ath9k_hw_enable_interrupts(ah);
6a6733f2 730
52671e43 731 spin_unlock(&sc->sc_pcu_lock);
153e080d 732 ath9k_ps_restore(sc);
ff37e337
S
733}
734
6baff7f9 735irqreturn_t ath_isr(int irq, void *dev)
ff37e337 736{
063d8be3
S
737#define SCHED_INTR ( \
738 ATH9K_INT_FATAL | \
a4d86d95 739 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
740 ATH9K_INT_RXORN | \
741 ATH9K_INT_RXEOL | \
742 ATH9K_INT_RX | \
b5c80475
FF
743 ATH9K_INT_RXLP | \
744 ATH9K_INT_RXHP | \
063d8be3
S
745 ATH9K_INT_TX | \
746 ATH9K_INT_BMISS | \
747 ATH9K_INT_CST | \
ebb8e1d7
VT
748 ATH9K_INT_TSFOOR | \
749 ATH9K_INT_GENTIMER)
063d8be3 750
ff37e337 751 struct ath_softc *sc = dev;
cbe61d8a 752 struct ath_hw *ah = sc->sc_ah;
b5bfc568 753 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
754 enum ath9k_int status;
755 bool sched = false;
756
063d8be3
S
757 /*
758 * The hardware is not ready/present, don't
759 * touch anything. Note this can happen early
760 * on if the IRQ is shared.
761 */
762 if (sc->sc_flags & SC_OP_INVALID)
763 return IRQ_NONE;
ff37e337 764
063d8be3
S
765
766 /* shared irq, not for us */
767
153e080d 768 if (!ath9k_hw_intrpend(ah))
063d8be3 769 return IRQ_NONE;
063d8be3
S
770
771 /*
772 * Figure out the reason(s) for the interrupt. Note
773 * that the hal returns a pseudo-ISR that may include
774 * bits we haven't explicitly enabled so we mask the
775 * value to insure we only process bits we requested.
776 */
777 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 778 status &= ah->imask; /* discard unasked-for bits */
ff37e337 779
063d8be3
S
780 /*
781 * If there are no status bits set, then this interrupt was not
782 * for me (should have been caught above).
783 */
153e080d 784 if (!status)
063d8be3 785 return IRQ_NONE;
ff37e337 786
063d8be3
S
787 /* Cache the status */
788 sc->intrstatus = status;
789
790 if (status & SCHED_INTR)
791 sched = true;
792
793 /*
794 * If a FATAL or RXORN interrupt is received, we have to reset the
795 * chip immediately.
796 */
b5c80475
FF
797 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
798 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
799 goto chip_reset;
800
08578b8f
LR
801 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
802 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
803
804 spin_lock(&common->cc_lock);
805 ath_hw_cycle_counters_update(common);
08578b8f 806 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
807 spin_unlock(&common->cc_lock);
808
08578b8f
LR
809 goto chip_reset;
810 }
811
063d8be3
S
812 if (status & ATH9K_INT_SWBA)
813 tasklet_schedule(&sc->bcon_tasklet);
814
815 if (status & ATH9K_INT_TXURN)
816 ath9k_hw_updatetxtriglevel(ah, true);
817
0682c9b5
RM
818 if (status & ATH9K_INT_RXEOL) {
819 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
820 ath9k_hw_set_interrupts(ah, ah->imask);
b5c80475
FF
821 }
822
063d8be3 823 if (status & ATH9K_INT_MIB) {
ff37e337 824 /*
063d8be3
S
825 * Disable interrupts until we service the MIB
826 * interrupt; otherwise it will continue to
827 * fire.
ff37e337 828 */
4df3071e 829 ath9k_hw_disable_interrupts(ah);
063d8be3
S
830 /*
831 * Let the hal handle the event. We assume
832 * it will clear whatever condition caused
833 * the interrupt.
834 */
88eac2da 835 spin_lock(&common->cc_lock);
bfc472bb 836 ath9k_hw_proc_mib_event(ah);
88eac2da 837 spin_unlock(&common->cc_lock);
4df3071e 838 ath9k_hw_enable_interrupts(ah);
063d8be3 839 }
ff37e337 840
153e080d
VT
841 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
842 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
843 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
844 goto chip_reset;
063d8be3
S
845 /* Clear RxAbort bit so that we can
846 * receive frames */
9ecdef4b 847 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 848 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 849 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 850 }
063d8be3
S
851
852chip_reset:
ff37e337 853
817e11de
S
854 ath_debug_stat_interrupt(sc, status);
855
ff37e337 856 if (sched) {
4df3071e
FF
857 /* turn off every interrupt */
858 ath9k_hw_disable_interrupts(ah);
ff37e337
S
859 tasklet_schedule(&sc->intr_tq);
860 }
861
862 return IRQ_HANDLED;
063d8be3
S
863
864#undef SCHED_INTR
ff37e337
S
865}
866
5595f119 867static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 868{
cbe61d8a 869 struct ath_hw *ah = sc->sc_ah;
c46917bb 870 struct ath_common *common = ath9k_hw_common(ah);
68a89116 871 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 872 int r;
500c064d 873
3cbb5dd7 874 ath9k_ps_wakeup(sc);
6a6733f2 875 spin_lock_bh(&sc->sc_pcu_lock);
e8fe7336 876 atomic_set(&ah->intr_ref_cnt, -1);
6a6733f2 877
84c87dc8 878 ath9k_hw_configpcipowersave(ah, false);
ae8d2858 879
159cd468 880 if (!ah->curchan)
c344c9cb 881 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 882
20bd2a09 883 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 884 if (r) {
3800276a
JP
885 ath_err(common,
886 "Unable to reset channel (%u MHz), reset status %d\n",
887 channel->center_freq, r);
500c064d 888 }
500c064d 889
9adcf440 890 ath_complete_reset(sc, true);
500c064d
VT
891
892 /* Enable LED */
08fc5c1b 893 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 894 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 895 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 896
6a6733f2
LR
897 spin_unlock_bh(&sc->sc_pcu_lock);
898
3cbb5dd7 899 ath9k_ps_restore(sc);
500c064d
VT
900}
901
68a89116 902void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 903{
cbe61d8a 904 struct ath_hw *ah = sc->sc_ah;
68a89116 905 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 906 int r;
500c064d 907
3cbb5dd7 908 ath9k_ps_wakeup(sc);
7e3514fd 909
9adcf440 910 ath_cancel_work(sc);
6a6733f2 911
9adcf440 912 spin_lock_bh(&sc->sc_pcu_lock);
500c064d 913
982723df
VN
914 /*
915 * Keep the LED on when the radio is disabled
916 * during idle unassociated state.
917 */
918 if (!sc->ps_idle) {
919 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
920 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
921 }
500c064d 922
9adcf440 923 ath_prepare_reset(sc, false, true);
500c064d 924
159cd468 925 if (!ah->curchan)
c344c9cb 926 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 927
20bd2a09 928 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 929 if (r) {
3800276a
JP
930 ath_err(ath9k_hw_common(sc->sc_ah),
931 "Unable to reset channel (%u MHz), reset status %d\n",
932 channel->center_freq, r);
500c064d 933 }
500c064d
VT
934
935 ath9k_hw_phy_disable(ah);
5e848f78 936
84c87dc8 937 ath9k_hw_configpcipowersave(ah, true);
6a6733f2
LR
938
939 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 940 ath9k_ps_restore(sc);
500c064d
VT
941}
942
236de514 943static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 944{
ae8d2858 945 int r;
ff37e337 946
783cd01e 947 ath9k_ps_wakeup(sc);
6a6733f2 948
9adcf440 949 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S
950
951 if (retry_tx) {
952 int i;
953 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
954 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
955 spin_lock_bh(&sc->tx.txq[i].axq_lock);
956 ath_txq_schedule(sc, &sc->tx.txq[i]);
957 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
958 }
959 }
960 }
961
783cd01e 962 ath9k_ps_restore(sc);
2ab81d4a 963
ae8d2858 964 return r;
ff37e337
S
965}
966
236de514
FF
967void ath_reset_work(struct work_struct *work)
968{
969 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
970
236de514 971 ath_reset(sc, true);
236de514
FF
972}
973
e8cfe9f8
FF
974void ath_hw_check(struct work_struct *work)
975{
976 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
977 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
978 unsigned long flags;
979 int busy;
980
981 ath9k_ps_wakeup(sc);
982 if (ath9k_hw_check_alive(sc->sc_ah))
983 goto out;
984
985 spin_lock_irqsave(&common->cc_lock, flags);
986 busy = ath_update_survey_stats(sc);
987 spin_unlock_irqrestore(&common->cc_lock, flags);
988
989 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
990 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
991 if (busy >= 99) {
9adcf440
FF
992 if (++sc->hw_busy_count >= 3)
993 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e8cfe9f8
FF
994
995 } else if (busy >= 0)
996 sc->hw_busy_count = 0;
997
998out:
999 ath9k_ps_restore(sc);
1000}
1001
1002static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
1003{
1004 static int count;
1005 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1006
1007 if (pll_sqsum >= 0x40000) {
1008 count++;
1009 if (count == 3) {
1010 /* Rx is hung for more than 500ms. Reset it */
1011 ath_dbg(common, ATH_DBG_RESET,
1012 "Possible RX hang, resetting");
9adcf440 1013 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e8cfe9f8
FF
1014 count = 0;
1015 }
1016 } else
1017 count = 0;
1018}
1019
1020void ath_hw_pll_work(struct work_struct *work)
1021{
1022 struct ath_softc *sc = container_of(work, struct ath_softc,
1023 hw_pll_work.work);
1024 u32 pll_sqsum;
1025
1026 if (AR_SREV_9485(sc->sc_ah)) {
1027
1028 ath9k_ps_wakeup(sc);
1029 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
1030 ath9k_ps_restore(sc);
1031
1032 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
1033
1034 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
1035 }
1036}
1037
ff37e337
S
1038/**********************/
1039/* mac80211 callbacks */
1040/**********************/
1041
8feceb67 1042static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1043{
9ac58615 1044 struct ath_softc *sc = hw->priv;
af03abec 1045 struct ath_hw *ah = sc->sc_ah;
c46917bb 1046 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1047 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1048 struct ath9k_channel *init_channel;
82880a7c 1049 int r;
f078f209 1050
226afe68
JP
1051 ath_dbg(common, ATH_DBG_CONFIG,
1052 "Starting driver with initial channel: %d MHz\n",
1053 curchan->center_freq);
f078f209 1054
f62d816f
FF
1055 ath9k_ps_wakeup(sc);
1056
141b38b6
S
1057 mutex_lock(&sc->mutex);
1058
8feceb67 1059 /* setup initial channel */
82880a7c 1060 sc->chan_idx = curchan->hw_value;
f078f209 1061
c344c9cb 1062 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1063
1064 /* Reset SERDES registers */
84c87dc8 1065 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
1066
1067 /*
1068 * The basic interface to setting the hardware in a good
1069 * state is ``reset''. On return the hardware is known to
1070 * be powered up and with interrupts disabled. This must
1071 * be followed by initialization of the appropriate bits
1072 * and then setup of the interrupt mask.
1073 */
4bdd1e97 1074 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1075 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1076 if (r) {
3800276a
JP
1077 ath_err(common,
1078 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1079 r, curchan->center_freq);
4bdd1e97 1080 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1081 goto mutex_unlock;
ff37e337 1082 }
ff37e337 1083
ff37e337 1084 /* Setup our intr mask. */
b5c80475
FF
1085 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1086 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1087 ATH9K_INT_GLOBAL;
1088
1089 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1090 ah->imask |= ATH9K_INT_RXHP |
1091 ATH9K_INT_RXLP |
1092 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1093 else
1094 ah->imask |= ATH9K_INT_RX;
ff37e337 1095
364734fa 1096 ah->imask |= ATH9K_INT_GTT;
ff37e337 1097
af03abec 1098 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1099 ah->imask |= ATH9K_INT_CST;
ff37e337 1100
ff37e337 1101 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1102 sc->sc_ah->is_monitoring = false;
ff37e337
S
1103
1104 /* Disable BMISS interrupt when we're not associated */
3069168c 1105 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
ff37e337 1106
9adcf440
FF
1107 if (!ath_complete_reset(sc, false)) {
1108 r = -EIO;
1109 spin_unlock_bh(&sc->sc_pcu_lock);
1110 goto mutex_unlock;
1111 }
ff37e337 1112
9adcf440 1113 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 1114
766ec4a9
LR
1115 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1116 !ah->btcoex_hw.enabled) {
5e197292
LR
1117 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1118 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1119 ath9k_hw_btcoex_enable(ah);
f985ad12 1120
766ec4a9 1121 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1122 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1123 }
1124
8060e169
VT
1125 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1126 common->bus_ops->extn_synch_en(common);
1127
141b38b6
S
1128mutex_unlock:
1129 mutex_unlock(&sc->mutex);
1130
f62d816f
FF
1131 ath9k_ps_restore(sc);
1132
ae8d2858 1133 return r;
f078f209
LR
1134}
1135
7bb45683 1136static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1137{
9ac58615 1138 struct ath_softc *sc = hw->priv;
c46917bb 1139 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1140 struct ath_tx_control txctl;
1bc14880 1141 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1142
96148326 1143 if (sc->ps_enabled) {
dc8c4585
JM
1144 /*
1145 * mac80211 does not set PM field for normal data frames, so we
1146 * need to update that based on the current PS mode.
1147 */
1148 if (ieee80211_is_data(hdr->frame_control) &&
1149 !ieee80211_is_nullfunc(hdr->frame_control) &&
1150 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1151 ath_dbg(common, ATH_DBG_PS,
1152 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1153 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1154 }
1155 }
1156
9a23f9ca
JM
1157 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1158 /*
1159 * We are using PS-Poll and mac80211 can request TX while in
1160 * power save mode. Need to wake up hardware for the TX to be
1161 * completed and if needed, also for RX of buffered frames.
1162 */
9a23f9ca 1163 ath9k_ps_wakeup(sc);
fdf76622
VT
1164 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1165 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1166 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1167 ath_dbg(common, ATH_DBG_PS,
1168 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1169 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1170 } else {
226afe68
JP
1171 ath_dbg(common, ATH_DBG_PS,
1172 "Wake up to complete TX\n");
1b04b930 1173 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1174 }
1175 /*
1176 * The actual restore operation will happen only after
1177 * the sc_flags bit is cleared. We are just dropping
1178 * the ps_usecount here.
1179 */
1180 ath9k_ps_restore(sc);
1181 }
1182
528f0c6b 1183 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1184 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1185
226afe68 1186 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1187
c52f33d0 1188 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1189 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1190 goto exit;
8feceb67
VT
1191 }
1192
7bb45683 1193 return;
528f0c6b
S
1194exit:
1195 dev_kfree_skb_any(skb);
f078f209
LR
1196}
1197
8feceb67 1198static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1199{
9ac58615 1200 struct ath_softc *sc = hw->priv;
af03abec 1201 struct ath_hw *ah = sc->sc_ah;
c46917bb 1202 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1203
4c483817
S
1204 mutex_lock(&sc->mutex);
1205
9adcf440 1206 ath_cancel_work(sc);
c94dbff7 1207
9c84b797 1208 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1209 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1210 mutex_unlock(&sc->mutex);
9c84b797
S
1211 return;
1212 }
8feceb67 1213
3867cf6a
S
1214 /* Ensure HW is awake when we try to shut it down. */
1215 ath9k_ps_wakeup(sc);
1216
766ec4a9 1217 if (ah->btcoex_hw.enabled) {
af03abec 1218 ath9k_hw_btcoex_disable(ah);
766ec4a9 1219 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1220 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1221 }
1222
6a6733f2
LR
1223 spin_lock_bh(&sc->sc_pcu_lock);
1224
203043f5
SG
1225 /* prevent tasklets to enable interrupts once we disable them */
1226 ah->imask &= ~ATH9K_INT_GLOBAL;
1227
ff37e337
S
1228 /* make sure h/w will not generate any interrupt
1229 * before setting the invalid flag. */
4df3071e 1230 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1231
1232 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1233 ath_drain_all_txq(sc, false);
ff37e337 1234 ath_stoprecv(sc);
af03abec 1235 ath9k_hw_phy_disable(ah);
6a6733f2 1236 } else
b77f483f 1237 sc->rx.rxlink = NULL;
ff37e337 1238
0d95521e
FF
1239 if (sc->rx.frag) {
1240 dev_kfree_skb_any(sc->rx.frag);
1241 sc->rx.frag = NULL;
1242 }
1243
ff37e337 1244 /* disable HAL and put h/w to sleep */
af03abec 1245 ath9k_hw_disable(ah);
6a6733f2
LR
1246
1247 spin_unlock_bh(&sc->sc_pcu_lock);
1248
203043f5
SG
1249 /* we can now sync irq and kill any running tasklets, since we already
1250 * disabled interrupts and not holding a spin lock */
1251 synchronize_irq(sc->irq);
1252 tasklet_kill(&sc->intr_tq);
1253 tasklet_kill(&sc->bcon_tasklet);
1254
3867cf6a
S
1255 ath9k_ps_restore(sc);
1256
a08e7ade
LR
1257 sc->ps_idle = true;
1258 ath_radio_disable(sc, hw);
ff37e337
S
1259
1260 sc->sc_flags |= SC_OP_INVALID;
500c064d 1261
141b38b6
S
1262 mutex_unlock(&sc->mutex);
1263
226afe68 1264 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1265}
1266
4801416c
BG
1267bool ath9k_uses_beacons(int type)
1268{
1269 switch (type) {
1270 case NL80211_IFTYPE_AP:
1271 case NL80211_IFTYPE_ADHOC:
1272 case NL80211_IFTYPE_MESH_POINT:
1273 return true;
1274 default:
1275 return false;
1276 }
1277}
1278
1279static void ath9k_reclaim_beacon(struct ath_softc *sc,
1280 struct ieee80211_vif *vif)
f078f209 1281{
1ed32e4f 1282 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1283
014cf3bb 1284 ath9k_set_beaconing_status(sc, false);
4801416c 1285 ath_beacon_return(sc, avp);
014cf3bb 1286 ath9k_set_beaconing_status(sc, true);
4801416c 1287 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1288}
1289
1290static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1291{
1292 struct ath9k_vif_iter_data *iter_data = data;
1293 int i;
1294
1295 if (iter_data->hw_macaddr)
1296 for (i = 0; i < ETH_ALEN; i++)
1297 iter_data->mask[i] &=
1298 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1299
1ed32e4f 1300 switch (vif->type) {
4801416c
BG
1301 case NL80211_IFTYPE_AP:
1302 iter_data->naps++;
f078f209 1303 break;
4801416c
BG
1304 case NL80211_IFTYPE_STATION:
1305 iter_data->nstations++;
e51f3eff 1306 break;
05c914fe 1307 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1308 iter_data->nadhocs++;
1309 break;
9cb5412b 1310 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1311 iter_data->nmeshes++;
1312 break;
1313 case NL80211_IFTYPE_WDS:
1314 iter_data->nwds++;
f078f209
LR
1315 break;
1316 default:
4801416c
BG
1317 iter_data->nothers++;
1318 break;
f078f209 1319 }
4801416c 1320}
f078f209 1321
4801416c
BG
1322/* Called with sc->mutex held. */
1323void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1324 struct ieee80211_vif *vif,
1325 struct ath9k_vif_iter_data *iter_data)
1326{
9ac58615 1327 struct ath_softc *sc = hw->priv;
4801416c
BG
1328 struct ath_hw *ah = sc->sc_ah;
1329 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1330
4801416c
BG
1331 /*
1332 * Use the hardware MAC address as reference, the hardware uses it
1333 * together with the BSSID mask when matching addresses.
1334 */
1335 memset(iter_data, 0, sizeof(*iter_data));
1336 iter_data->hw_macaddr = common->macaddr;
1337 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1338
4801416c
BG
1339 if (vif)
1340 ath9k_vif_iter(iter_data, vif->addr, vif);
1341
1342 /* Get list of all active MAC addresses */
4801416c
BG
1343 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1344 iter_data);
4801416c 1345}
8ca21f01 1346
4801416c
BG
1347/* Called with sc->mutex held. */
1348static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1349 struct ieee80211_vif *vif)
1350{
9ac58615 1351 struct ath_softc *sc = hw->priv;
4801416c
BG
1352 struct ath_hw *ah = sc->sc_ah;
1353 struct ath_common *common = ath9k_hw_common(ah);
1354 struct ath9k_vif_iter_data iter_data;
8ca21f01 1355
4801416c 1356 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1357
4801416c
BG
1358 /* Set BSSID mask. */
1359 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1360 ath_hw_setbssidmask(common);
1361
1362 /* Set op-mode & TSF */
1363 if (iter_data.naps > 0) {
3069168c 1364 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1365 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1366 ah->opmode = NL80211_IFTYPE_AP;
1367 } else {
1368 ath9k_hw_set_tsfadjust(ah, 0);
1369 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1370
fd5999cf
JC
1371 if (iter_data.nmeshes)
1372 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1373 else if (iter_data.nwds)
4801416c
BG
1374 ah->opmode = NL80211_IFTYPE_AP;
1375 else if (iter_data.nadhocs)
1376 ah->opmode = NL80211_IFTYPE_ADHOC;
1377 else
1378 ah->opmode = NL80211_IFTYPE_STATION;
1379 }
5640b08e 1380
4e30ffa2
VN
1381 /*
1382 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1383 */
4801416c 1384 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1385 if (ah->config.enable_ani)
1386 ah->imask |= ATH9K_INT_MIB;
3069168c 1387 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1388 } else {
1389 ah->imask &= ~ATH9K_INT_MIB;
1390 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1391 }
1392
3069168c 1393 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1394
4801416c 1395 /* Set up ANI */
2e5ef459 1396 if (iter_data.naps > 0) {
729da390 1397 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1398
1399 if (!common->disable_ani) {
1400 sc->sc_flags |= SC_OP_ANI_RUN;
1401 ath_start_ani(common);
1402 }
1403
f60c49b6
RM
1404 } else {
1405 sc->sc_flags &= ~SC_OP_ANI_RUN;
1406 del_timer_sync(&common->ani.timer);
6c3118e2 1407 }
4801416c 1408}
6f255425 1409
4801416c
BG
1410/* Called with sc->mutex held, vif counts set up properly. */
1411static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1412 struct ieee80211_vif *vif)
1413{
9ac58615 1414 struct ath_softc *sc = hw->priv;
4801416c
BG
1415
1416 ath9k_calculate_summary_state(hw, vif);
1417
1418 if (ath9k_uses_beacons(vif->type)) {
1419 int error;
4801416c
BG
1420 /* This may fail because upper levels do not have beacons
1421 * properly configured yet. That's OK, we assume it
1422 * will be properly configured and then we will be notified
1423 * in the info_changed method and set up beacons properly
1424 * there.
1425 */
014cf3bb 1426 ath9k_set_beaconing_status(sc, false);
9ac58615 1427 error = ath_beacon_alloc(sc, vif);
391bd1c4 1428 if (!error)
4801416c 1429 ath_beacon_config(sc, vif);
014cf3bb 1430 ath9k_set_beaconing_status(sc, true);
4801416c 1431 }
f078f209
LR
1432}
1433
4801416c
BG
1434
1435static int ath9k_add_interface(struct ieee80211_hw *hw,
1436 struct ieee80211_vif *vif)
6b3b991d 1437{
9ac58615 1438 struct ath_softc *sc = hw->priv;
4801416c
BG
1439 struct ath_hw *ah = sc->sc_ah;
1440 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1441 int ret = 0;
6b3b991d 1442
96f372c9 1443 ath9k_ps_wakeup(sc);
4801416c 1444 mutex_lock(&sc->mutex);
6b3b991d 1445
4801416c
BG
1446 switch (vif->type) {
1447 case NL80211_IFTYPE_STATION:
1448 case NL80211_IFTYPE_WDS:
1449 case NL80211_IFTYPE_ADHOC:
1450 case NL80211_IFTYPE_AP:
1451 case NL80211_IFTYPE_MESH_POINT:
1452 break;
1453 default:
1454 ath_err(common, "Interface type %d not yet supported\n",
1455 vif->type);
1456 ret = -EOPNOTSUPP;
1457 goto out;
1458 }
6b3b991d 1459
4801416c
BG
1460 if (ath9k_uses_beacons(vif->type)) {
1461 if (sc->nbcnvifs >= ATH_BCBUF) {
1462 ath_err(common, "Not enough beacon buffers when adding"
1463 " new interface of type: %i\n",
1464 vif->type);
1465 ret = -ENOBUFS;
1466 goto out;
1467 }
1468 }
1469
59575d1c
RM
1470 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1471 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1472 sc->nvifs > 0)) {
4801416c
BG
1473 ath_err(common, "Cannot create ADHOC interface when other"
1474 " interfaces already exist.\n");
1475 ret = -EINVAL;
1476 goto out;
6b3b991d 1477 }
4801416c
BG
1478
1479 ath_dbg(common, ATH_DBG_CONFIG,
1480 "Attach a VIF of type: %d\n", vif->type);
1481
4801416c
BG
1482 sc->nvifs++;
1483
1484 ath9k_do_vif_add_setup(hw, vif);
1485out:
1486 mutex_unlock(&sc->mutex);
96f372c9 1487 ath9k_ps_restore(sc);
4801416c 1488 return ret;
6b3b991d
RM
1489}
1490
1491static int ath9k_change_interface(struct ieee80211_hw *hw,
1492 struct ieee80211_vif *vif,
1493 enum nl80211_iftype new_type,
1494 bool p2p)
1495{
9ac58615 1496 struct ath_softc *sc = hw->priv;
6b3b991d 1497 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1498 int ret = 0;
6b3b991d
RM
1499
1500 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1501 mutex_lock(&sc->mutex);
96f372c9 1502 ath9k_ps_wakeup(sc);
6b3b991d 1503
4801416c
BG
1504 /* See if new interface type is valid. */
1505 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1506 (sc->nvifs > 1)) {
1507 ath_err(common, "When using ADHOC, it must be the only"
1508 " interface.\n");
1509 ret = -EINVAL;
1510 goto out;
1511 }
1512
1513 if (ath9k_uses_beacons(new_type) &&
1514 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1515 if (sc->nbcnvifs >= ATH_BCBUF) {
1516 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1517 ret = -ENOBUFS;
1518 goto out;
6b3b991d 1519 }
6b3b991d 1520 }
4801416c
BG
1521
1522 /* Clean up old vif stuff */
1523 if (ath9k_uses_beacons(vif->type))
1524 ath9k_reclaim_beacon(sc, vif);
1525
1526 /* Add new settings */
6b3b991d
RM
1527 vif->type = new_type;
1528 vif->p2p = p2p;
1529
4801416c 1530 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1531out:
96f372c9 1532 ath9k_ps_restore(sc);
6b3b991d 1533 mutex_unlock(&sc->mutex);
6dab55bf 1534 return ret;
6b3b991d
RM
1535}
1536
8feceb67 1537static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1538 struct ieee80211_vif *vif)
f078f209 1539{
9ac58615 1540 struct ath_softc *sc = hw->priv;
c46917bb 1541 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1542
226afe68 1543 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1544
96f372c9 1545 ath9k_ps_wakeup(sc);
141b38b6
S
1546 mutex_lock(&sc->mutex);
1547
4801416c 1548 sc->nvifs--;
580f0b8a 1549
8feceb67 1550 /* Reclaim beacon resources */
4801416c 1551 if (ath9k_uses_beacons(vif->type))
6b3b991d 1552 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1553
4801416c 1554 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1555
1556 mutex_unlock(&sc->mutex);
96f372c9 1557 ath9k_ps_restore(sc);
f078f209
LR
1558}
1559
fbab7390 1560static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1561{
3069168c
PR
1562 struct ath_hw *ah = sc->sc_ah;
1563
3f7c5c10 1564 sc->ps_enabled = true;
3069168c
PR
1565 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1566 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1567 ah->imask |= ATH9K_INT_TIM_TIMER;
1568 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1569 }
fdf76622 1570 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1571 }
3f7c5c10
SB
1572}
1573
845d708e
SB
1574static void ath9k_disable_ps(struct ath_softc *sc)
1575{
1576 struct ath_hw *ah = sc->sc_ah;
1577
1578 sc->ps_enabled = false;
1579 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1580 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1581 ath9k_hw_setrxabort(ah, 0);
1582 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1583 PS_WAIT_FOR_CAB |
1584 PS_WAIT_FOR_PSPOLL_DATA |
1585 PS_WAIT_FOR_TX_ACK);
1586 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1587 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1588 ath9k_hw_set_interrupts(ah, ah->imask);
1589 }
1590 }
1591
1592}
1593
e8975581 1594static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1595{
9ac58615 1596 struct ath_softc *sc = hw->priv;
3430098a
FF
1597 struct ath_hw *ah = sc->sc_ah;
1598 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1599 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1600 bool disable_radio = false;
f078f209 1601
aa33de09 1602 mutex_lock(&sc->mutex);
141b38b6 1603
194b7c13
LR
1604 /*
1605 * Leave this as the first check because we need to turn on the
1606 * radio if it was disabled before prior to processing the rest
1607 * of the changes. Likewise we must only disable the radio towards
1608 * the end.
1609 */
64839170 1610 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF
1611 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1612 if (!sc->ps_idle) {
68a89116 1613 ath_radio_enable(sc, hw);
226afe68
JP
1614 ath_dbg(common, ATH_DBG_CONFIG,
1615 "not-idle: enabling radio\n");
7545daf4
FF
1616 } else {
1617 disable_radio = true;
64839170
LR
1618 }
1619 }
1620
e7824a50
LR
1621 /*
1622 * We just prepare to enable PS. We have to wait until our AP has
1623 * ACK'd our null data frame to disable RX otherwise we'll ignore
1624 * those ACKs and end up retransmitting the same null data frames.
1625 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1626 */
3cbb5dd7 1627 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1628 unsigned long flags;
1629 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1630 if (conf->flags & IEEE80211_CONF_PS)
1631 ath9k_enable_ps(sc);
845d708e
SB
1632 else
1633 ath9k_disable_ps(sc);
8ab2cd09 1634 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1635 }
1636
199afd9d
S
1637 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1638 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1639 ath_dbg(common, ATH_DBG_CONFIG,
1640 "Monitor mode is enabled\n");
5f841b41
RM
1641 sc->sc_ah->is_monitoring = true;
1642 } else {
226afe68
JP
1643 ath_dbg(common, ATH_DBG_CONFIG,
1644 "Monitor mode is disabled\n");
5f841b41 1645 sc->sc_ah->is_monitoring = false;
199afd9d
S
1646 }
1647 }
1648
4797938c 1649 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1650 struct ieee80211_channel *curchan = hw->conf.channel;
e338a85e 1651 struct ath9k_channel old_chan;
5f8e077c 1652 int pos = curchan->hw_value;
3430098a
FF
1653 int old_pos = -1;
1654 unsigned long flags;
1655
1656 if (ah->curchan)
1657 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1658
5ee08656
FF
1659 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1660 sc->sc_flags |= SC_OP_OFFCHANNEL;
1661 else
1662 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1663
8c79a610
BG
1664 ath_dbg(common, ATH_DBG_CONFIG,
1665 "Set channel: %d MHz type: %d\n",
1666 curchan->center_freq, conf->channel_type);
f078f209 1667
3430098a
FF
1668 /* update survey stats for the old channel before switching */
1669 spin_lock_irqsave(&common->cc_lock, flags);
1670 ath_update_survey_stats(sc);
1671 spin_unlock_irqrestore(&common->cc_lock, flags);
1672
e338a85e
RM
1673 /*
1674 * Preserve the current channel values, before updating
1675 * the same channel
1676 */
1677 if (old_pos == pos) {
1678 memcpy(&old_chan, &sc->sc_ah->channels[pos],
1679 sizeof(struct ath9k_channel));
1680 ah->curchan = &old_chan;
1681 }
1682
1683 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1684 curchan, conf->channel_type);
1685
3430098a
FF
1686 /*
1687 * If the operating channel changes, change the survey in-use flags
1688 * along with it.
1689 * Reset the survey data for the new channel, unless we're switching
1690 * back to the operating channel from an off-channel operation.
1691 */
1692 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1693 sc->cur_survey != &sc->survey[pos]) {
1694
1695 if (sc->cur_survey)
1696 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1697
1698 sc->cur_survey = &sc->survey[pos];
1699
1700 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1701 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1702 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1703 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1704 }
1705
0e2dedf9 1706 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1707 ath_err(common, "Unable to set channel\n");
aa33de09 1708 mutex_unlock(&sc->mutex);
e11602b7
S
1709 return -EINVAL;
1710 }
3430098a
FF
1711
1712 /*
1713 * The most recent snapshot of channel->noisefloor for the old
1714 * channel is only available after the hardware reset. Copy it to
1715 * the survey stats now.
1716 */
1717 if (old_pos >= 0)
1718 ath_update_survey_nf(sc, old_pos);
094d05dc 1719 }
f078f209 1720
c9f6a656 1721 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG
1722 ath_dbg(common, ATH_DBG_CONFIG,
1723 "Set power: %d\n", conf->power_level);
17d7904d 1724 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1725 ath9k_ps_wakeup(sc);
5048e8c3
RM
1726 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1727 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1728 ath9k_ps_restore(sc);
c9f6a656 1729 }
f078f209 1730
64839170 1731 if (disable_radio) {
226afe68 1732 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1733 ath_radio_disable(sc, hw);
64839170
LR
1734 }
1735
aa33de09 1736 mutex_unlock(&sc->mutex);
141b38b6 1737
f078f209
LR
1738 return 0;
1739}
1740
8feceb67
VT
1741#define SUPPORTED_FILTERS \
1742 (FIF_PROMISC_IN_BSS | \
1743 FIF_ALLMULTI | \
1744 FIF_CONTROL | \
af6a3fc7 1745 FIF_PSPOLL | \
8feceb67
VT
1746 FIF_OTHER_BSS | \
1747 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1748 FIF_PROBE_REQ | \
8feceb67 1749 FIF_FCSFAIL)
c83be688 1750
8feceb67
VT
1751/* FIXME: sc->sc_full_reset ? */
1752static void ath9k_configure_filter(struct ieee80211_hw *hw,
1753 unsigned int changed_flags,
1754 unsigned int *total_flags,
3ac64bee 1755 u64 multicast)
8feceb67 1756{
9ac58615 1757 struct ath_softc *sc = hw->priv;
8feceb67 1758 u32 rfilt;
f078f209 1759
8feceb67
VT
1760 changed_flags &= SUPPORTED_FILTERS;
1761 *total_flags &= SUPPORTED_FILTERS;
f078f209 1762
b77f483f 1763 sc->rx.rxfilter = *total_flags;
aa68aeaa 1764 ath9k_ps_wakeup(sc);
8feceb67
VT
1765 rfilt = ath_calcrxfilter(sc);
1766 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1767 ath9k_ps_restore(sc);
f078f209 1768
226afe68
JP
1769 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1770 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1771}
f078f209 1772
4ca77860
JB
1773static int ath9k_sta_add(struct ieee80211_hw *hw,
1774 struct ieee80211_vif *vif,
1775 struct ieee80211_sta *sta)
8feceb67 1776{
9ac58615 1777 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1778 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1779 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1780 struct ieee80211_key_conf ps_key = { };
f078f209 1781
4ca77860 1782 ath_node_attach(sc, sta);
f59a59fe
FF
1783
1784 if (vif->type != NL80211_IFTYPE_AP &&
1785 vif->type != NL80211_IFTYPE_AP_VLAN)
1786 return 0;
1787
93ae2dd2 1788 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1789
1790 return 0;
1791}
1792
93ae2dd2
FF
1793static void ath9k_del_ps_key(struct ath_softc *sc,
1794 struct ieee80211_vif *vif,
1795 struct ieee80211_sta *sta)
1796{
1797 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1798 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1799 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1800
1801 if (!an->ps_key)
1802 return;
1803
1804 ath_key_delete(common, &ps_key);
1805}
1806
4ca77860
JB
1807static int ath9k_sta_remove(struct ieee80211_hw *hw,
1808 struct ieee80211_vif *vif,
1809 struct ieee80211_sta *sta)
1810{
9ac58615 1811 struct ath_softc *sc = hw->priv;
4ca77860 1812
93ae2dd2 1813 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1814 ath_node_detach(sc, sta);
1815
1816 return 0;
f078f209
LR
1817}
1818
5519541d
FF
1819static void ath9k_sta_notify(struct ieee80211_hw *hw,
1820 struct ieee80211_vif *vif,
1821 enum sta_notify_cmd cmd,
1822 struct ieee80211_sta *sta)
1823{
1824 struct ath_softc *sc = hw->priv;
1825 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1826
1827 switch (cmd) {
1828 case STA_NOTIFY_SLEEP:
1829 an->sleeping = true;
1830 if (ath_tx_aggr_sleep(sc, an))
1831 ieee80211_sta_set_tim(sta);
1832 break;
1833 case STA_NOTIFY_AWAKE:
1834 an->sleeping = false;
1835 ath_tx_aggr_wakeup(sc, an);
1836 break;
1837 }
1838}
1839
141b38b6 1840static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1841 const struct ieee80211_tx_queue_params *params)
f078f209 1842{
9ac58615 1843 struct ath_softc *sc = hw->priv;
c46917bb 1844 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1845 struct ath_txq *txq;
8feceb67 1846 struct ath9k_tx_queue_info qi;
066dae93 1847 int ret = 0;
f078f209 1848
8feceb67
VT
1849 if (queue >= WME_NUM_AC)
1850 return 0;
f078f209 1851
066dae93
FF
1852 txq = sc->tx.txq_map[queue];
1853
96f372c9 1854 ath9k_ps_wakeup(sc);
141b38b6
S
1855 mutex_lock(&sc->mutex);
1856
1ffb0610
S
1857 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1858
8feceb67
VT
1859 qi.tqi_aifs = params->aifs;
1860 qi.tqi_cwmin = params->cw_min;
1861 qi.tqi_cwmax = params->cw_max;
1862 qi.tqi_burstTime = params->txop;
f078f209 1863
226afe68
JP
1864 ath_dbg(common, ATH_DBG_CONFIG,
1865 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1866 queue, txq->axq_qnum, params->aifs, params->cw_min,
1867 params->cw_max, params->txop);
f078f209 1868
066dae93 1869 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1870 if (ret)
3800276a 1871 ath_err(common, "TXQ Update failed\n");
f078f209 1872
94db2936 1873 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1874 if (queue == WME_AC_BE && !ret)
94db2936
VN
1875 ath_beaconq_config(sc);
1876
141b38b6 1877 mutex_unlock(&sc->mutex);
96f372c9 1878 ath9k_ps_restore(sc);
141b38b6 1879
8feceb67
VT
1880 return ret;
1881}
f078f209 1882
8feceb67
VT
1883static int ath9k_set_key(struct ieee80211_hw *hw,
1884 enum set_key_cmd cmd,
dc822b5d
JB
1885 struct ieee80211_vif *vif,
1886 struct ieee80211_sta *sta,
8feceb67
VT
1887 struct ieee80211_key_conf *key)
1888{
9ac58615 1889 struct ath_softc *sc = hw->priv;
c46917bb 1890 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1891 int ret = 0;
f078f209 1892
3e6109c5 1893 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1894 return -ENOSPC;
1895
cfdc9a8b
JM
1896 if (vif->type == NL80211_IFTYPE_ADHOC &&
1897 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1898 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1899 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1900 /*
1901 * For now, disable hw crypto for the RSN IBSS group keys. This
1902 * could be optimized in the future to use a modified key cache
1903 * design to support per-STA RX GTK, but until that gets
1904 * implemented, use of software crypto for group addressed
1905 * frames is a acceptable to allow RSN IBSS to be used.
1906 */
1907 return -EOPNOTSUPP;
1908 }
1909
141b38b6 1910 mutex_lock(&sc->mutex);
3cbb5dd7 1911 ath9k_ps_wakeup(sc);
226afe68 1912 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1913
8feceb67
VT
1914 switch (cmd) {
1915 case SET_KEY:
93ae2dd2
FF
1916 if (sta)
1917 ath9k_del_ps_key(sc, vif, sta);
1918
040e539e 1919 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1920 if (ret >= 0) {
1921 key->hw_key_idx = ret;
8feceb67
VT
1922 /* push IV and Michael MIC generation to stack */
1923 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1924 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1925 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1926 if (sc->sc_ah->sw_mgmt_crypto &&
1927 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1928 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1929 ret = 0;
8feceb67
VT
1930 }
1931 break;
1932 case DISABLE_KEY:
040e539e 1933 ath_key_delete(common, key);
8feceb67
VT
1934 break;
1935 default:
1936 ret = -EINVAL;
1937 }
f078f209 1938
3cbb5dd7 1939 ath9k_ps_restore(sc);
141b38b6
S
1940 mutex_unlock(&sc->mutex);
1941
8feceb67
VT
1942 return ret;
1943}
4f5ef75b
RM
1944static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1945{
1946 struct ath_softc *sc = data;
1947 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1948 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1949 struct ath_vif *avp = (void *)vif->drv_priv;
1950
2e5ef459
RM
1951 /*
1952 * Skip iteration if primary station vif's bss info
1953 * was not changed
1954 */
1955 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1956 return;
1957
1958 if (bss_conf->assoc) {
1959 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1960 avp->primary_sta_vif = true;
4f5ef75b
RM
1961 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1962 common->curaid = bss_conf->aid;
1963 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459 1964 ath_dbg(common, ATH_DBG_CONFIG,
99e4d43a
RM
1965 "Bss Info ASSOC %d, bssid: %pM\n",
1966 bss_conf->aid, common->curbssid);
2e5ef459
RM
1967 ath_beacon_config(sc, vif);
1968 /*
1969 * Request a re-configuration of Beacon related timers
1970 * on the receipt of the first Beacon frame (i.e.,
1971 * after time sync with the AP).
1972 */
1973 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1974 /* Reset rssi stats */
1975 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1976 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1977
05c0be2f
MSS
1978 if (!common->disable_ani) {
1979 sc->sc_flags |= SC_OP_ANI_RUN;
1980 ath_start_ani(common);
1981 }
1982
4f5ef75b
RM
1983 }
1984}
1985
1986static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1987{
1988 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1989 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1990 struct ath_vif *avp = (void *)vif->drv_priv;
1991
2e5ef459
RM
1992 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1993 return;
1994
4f5ef75b
RM
1995 /* Reconfigure bss info */
1996 if (avp->primary_sta_vif && !bss_conf->assoc) {
99e4d43a
RM
1997 ath_dbg(common, ATH_DBG_CONFIG,
1998 "Bss Info DISASSOC %d, bssid %pM\n",
1999 common->curaid, common->curbssid);
2000 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
2001 avp->primary_sta_vif = false;
2002 memset(common->curbssid, 0, ETH_ALEN);
2003 common->curaid = 0;
2004 }
2005
2006 ieee80211_iterate_active_interfaces_atomic(
2007 sc->hw, ath9k_bss_iter, sc);
2008
2009 /*
2010 * None of station vifs are associated.
2011 * Clear bssid & aid
2012 */
2e5ef459 2013 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 2014 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
2015 /* Stop ANI */
2016 sc->sc_flags &= ~SC_OP_ANI_RUN;
2017 del_timer_sync(&common->ani.timer);
2018 }
4f5ef75b 2019}
f078f209 2020
8feceb67
VT
2021static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2022 struct ieee80211_vif *vif,
2023 struct ieee80211_bss_conf *bss_conf,
2024 u32 changed)
2025{
9ac58615 2026 struct ath_softc *sc = hw->priv;
2d0ddec5 2027 struct ath_hw *ah = sc->sc_ah;
1510718d 2028 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2029 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2030 int slottime;
c6089ccc 2031 int error;
f078f209 2032
96f372c9 2033 ath9k_ps_wakeup(sc);
141b38b6
S
2034 mutex_lock(&sc->mutex);
2035
c6089ccc 2036 if (changed & BSS_CHANGED_BSSID) {
4f5ef75b 2037 ath9k_config_bss(sc, vif);
2d0ddec5 2038
226afe68
JP
2039 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2040 common->curbssid, common->curaid);
c6089ccc 2041 }
2d0ddec5 2042
2e5ef459
RM
2043 if (changed & BSS_CHANGED_IBSS) {
2044 /* There can be only one vif available */
2045 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2046 common->curaid = bss_conf->aid;
2047 ath9k_hw_write_associd(sc->sc_ah);
2048
2049 if (bss_conf->ibss_joined) {
2050 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
2051
2052 if (!common->disable_ani) {
2053 sc->sc_flags |= SC_OP_ANI_RUN;
2054 ath_start_ani(common);
2055 }
2056
2e5ef459
RM
2057 } else {
2058 sc->sc_flags &= ~SC_OP_ANI_RUN;
2059 del_timer_sync(&common->ani.timer);
2060 }
2061 }
2062
c6089ccc
S
2063 /* Enable transmission of beacons (AP, IBSS, MESH) */
2064 if ((changed & BSS_CHANGED_BEACON) ||
2065 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2066 ath9k_set_beaconing_status(sc, false);
9ac58615 2067 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
2068 if (!error)
2069 ath_beacon_config(sc, vif);
014cf3bb 2070 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
2071 }
2072
2073 if (changed & BSS_CHANGED_ERP_SLOT) {
2074 if (bss_conf->use_short_slot)
2075 slottime = 9;
2076 else
2077 slottime = 20;
2078 if (vif->type == NL80211_IFTYPE_AP) {
2079 /*
2080 * Defer update, so that connected stations can adjust
2081 * their settings at the same time.
2082 * See beacon.c for more details
2083 */
2084 sc->beacon.slottime = slottime;
2085 sc->beacon.updateslot = UPDATE;
2086 } else {
2087 ah->slottime = slottime;
2088 ath9k_hw_init_global_settings(ah);
2089 }
2d0ddec5
JB
2090 }
2091
c6089ccc 2092 /* Disable transmission of beacons */
014cf3bb
RM
2093 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2094 !bss_conf->enable_beacon) {
2095 ath9k_set_beaconing_status(sc, false);
2096 avp->is_bslot_active = false;
2097 ath9k_set_beaconing_status(sc, true);
2098 }
2d0ddec5 2099
c6089ccc 2100 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S
2101 /*
2102 * In case of AP mode, the HW TSF has to be reset
2103 * when the beacon interval changes.
2104 */
2105 if (vif->type == NL80211_IFTYPE_AP) {
2106 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2107 ath9k_set_beaconing_status(sc, false);
9ac58615 2108 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
2109 if (!error)
2110 ath_beacon_config(sc, vif);
014cf3bb 2111 ath9k_set_beaconing_status(sc, true);
99e4d43a 2112 } else
c6089ccc 2113 ath_beacon_config(sc, vif);
2d0ddec5
JB
2114 }
2115
8feceb67 2116 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
2117 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2118 bss_conf->use_short_preamble);
8feceb67
VT
2119 if (bss_conf->use_short_preamble)
2120 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2121 else
2122 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2123 }
f078f209 2124
8feceb67 2125 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
2126 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2127 bss_conf->use_cts_prot);
8feceb67
VT
2128 if (bss_conf->use_cts_prot &&
2129 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2130 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2131 else
2132 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2133 }
f078f209 2134
141b38b6 2135 mutex_unlock(&sc->mutex);
96f372c9 2136 ath9k_ps_restore(sc);
8feceb67 2137}
f078f209 2138
8feceb67
VT
2139static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2140{
9ac58615 2141 struct ath_softc *sc = hw->priv;
8feceb67 2142 u64 tsf;
f078f209 2143
141b38b6 2144 mutex_lock(&sc->mutex);
9abbfb27 2145 ath9k_ps_wakeup(sc);
141b38b6 2146 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2147 ath9k_ps_restore(sc);
141b38b6 2148 mutex_unlock(&sc->mutex);
f078f209 2149
8feceb67
VT
2150 return tsf;
2151}
f078f209 2152
3b5d665b
AF
2153static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2154{
9ac58615 2155 struct ath_softc *sc = hw->priv;
3b5d665b 2156
141b38b6 2157 mutex_lock(&sc->mutex);
9abbfb27 2158 ath9k_ps_wakeup(sc);
141b38b6 2159 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2160 ath9k_ps_restore(sc);
141b38b6 2161 mutex_unlock(&sc->mutex);
3b5d665b
AF
2162}
2163
8feceb67
VT
2164static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2165{
9ac58615 2166 struct ath_softc *sc = hw->priv;
c83be688 2167
141b38b6 2168 mutex_lock(&sc->mutex);
21526d57
LR
2169
2170 ath9k_ps_wakeup(sc);
141b38b6 2171 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2172 ath9k_ps_restore(sc);
2173
141b38b6 2174 mutex_unlock(&sc->mutex);
8feceb67 2175}
f078f209 2176
8feceb67 2177static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2178 struct ieee80211_vif *vif,
141b38b6
S
2179 enum ieee80211_ampdu_mlme_action action,
2180 struct ieee80211_sta *sta,
0b01f030 2181 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2182{
9ac58615 2183 struct ath_softc *sc = hw->priv;
8feceb67 2184 int ret = 0;
f078f209 2185
85ad181e
JB
2186 local_bh_disable();
2187
8feceb67
VT
2188 switch (action) {
2189 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2190 if (!(sc->sc_flags & SC_OP_RXAGGR))
2191 ret = -ENOTSUPP;
8feceb67
VT
2192 break;
2193 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2194 break;
2195 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2196 if (!(sc->sc_flags & SC_OP_TXAGGR))
2197 return -EOPNOTSUPP;
2198
8b685ba9 2199 ath9k_ps_wakeup(sc);
231c3a1f
FF
2200 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2201 if (!ret)
2202 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2203 ath9k_ps_restore(sc);
8feceb67
VT
2204 break;
2205 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2206 ath9k_ps_wakeup(sc);
f83da965 2207 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2208 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2209 ath9k_ps_restore(sc);
8feceb67 2210 break;
b1720231 2211 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2212 ath9k_ps_wakeup(sc);
8469cdef 2213 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2214 ath9k_ps_restore(sc);
8469cdef 2215 break;
8feceb67 2216 default:
3800276a 2217 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2218 }
2219
85ad181e
JB
2220 local_bh_enable();
2221
8feceb67 2222 return ret;
f078f209
LR
2223}
2224
62dad5b0
BP
2225static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2226 struct survey_info *survey)
2227{
9ac58615 2228 struct ath_softc *sc = hw->priv;
3430098a 2229 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2230 struct ieee80211_supported_band *sband;
3430098a
FF
2231 struct ieee80211_channel *chan;
2232 unsigned long flags;
2233 int pos;
2234
2235 spin_lock_irqsave(&common->cc_lock, flags);
2236 if (idx == 0)
2237 ath_update_survey_stats(sc);
39162dbe
FF
2238
2239 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2240 if (sband && idx >= sband->n_channels) {
2241 idx -= sband->n_channels;
2242 sband = NULL;
2243 }
62dad5b0 2244
39162dbe
FF
2245 if (!sband)
2246 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2247
3430098a
FF
2248 if (!sband || idx >= sband->n_channels) {
2249 spin_unlock_irqrestore(&common->cc_lock, flags);
2250 return -ENOENT;
4f1a5a4b 2251 }
62dad5b0 2252
3430098a
FF
2253 chan = &sband->channels[idx];
2254 pos = chan->hw_value;
2255 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2256 survey->channel = chan;
2257 spin_unlock_irqrestore(&common->cc_lock, flags);
2258
62dad5b0
BP
2259 return 0;
2260}
2261
e239d859
FF
2262static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2263{
9ac58615 2264 struct ath_softc *sc = hw->priv;
e239d859
FF
2265 struct ath_hw *ah = sc->sc_ah;
2266
2267 mutex_lock(&sc->mutex);
2268 ah->coverage_class = coverage_class;
2269 ath9k_hw_init_global_settings(ah);
2270 mutex_unlock(&sc->mutex);
2271}
2272
69081624
VT
2273static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2274{
69081624 2275 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2276 struct ath_hw *ah = sc->sc_ah;
2277 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
2278 int timeout = 200; /* ms */
2279 int i, j;
2f6fc351 2280 bool drain_txq;
69081624
VT
2281
2282 mutex_lock(&sc->mutex);
69081624
VT
2283 cancel_delayed_work_sync(&sc->tx_complete_work);
2284
99aa55b6
MSS
2285 if (sc->sc_flags & SC_OP_INVALID) {
2286 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
2287 mutex_unlock(&sc->mutex);
2288 return;
2289 }
2290
86271e46
FF
2291 if (drop)
2292 timeout = 1;
69081624 2293
86271e46 2294 for (j = 0; j < timeout; j++) {
108697c4 2295 bool npend = false;
86271e46
FF
2296
2297 if (j)
2298 usleep_range(1000, 2000);
69081624 2299
86271e46
FF
2300 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2301 if (!ATH_TXQ_SETUP(sc, i))
2302 continue;
2303
108697c4
MSS
2304 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2305
2306 if (npend)
2307 break;
69081624 2308 }
86271e46
FF
2309
2310 if (!npend)
2311 goto out;
69081624
VT
2312 }
2313
51513906 2314 ath9k_ps_wakeup(sc);
2f6fc351
RM
2315 spin_lock_bh(&sc->sc_pcu_lock);
2316 drain_txq = ath_drain_all_txq(sc, false);
9adcf440
FF
2317 spin_unlock_bh(&sc->sc_pcu_lock);
2318
2f6fc351 2319 if (!drain_txq)
69081624 2320 ath_reset(sc, false);
9adcf440 2321
51513906 2322 ath9k_ps_restore(sc);
d78f4b3e
SB
2323 ieee80211_wake_queues(hw);
2324
86271e46 2325out:
69081624
VT
2326 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2327 mutex_unlock(&sc->mutex);
2328}
2329
15b91e83
VN
2330static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2331{
2332 struct ath_softc *sc = hw->priv;
2333 int i;
2334
2335 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2336 if (!ATH_TXQ_SETUP(sc, i))
2337 continue;
2338
2339 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2340 return true;
2341 }
2342 return false;
2343}
2344
5595f119 2345static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2346{
2347 struct ath_softc *sc = hw->priv;
2348 struct ath_hw *ah = sc->sc_ah;
2349 struct ieee80211_vif *vif;
2350 struct ath_vif *avp;
2351 struct ath_buf *bf;
2352 struct ath_tx_status ts;
2353 int status;
2354
2355 vif = sc->beacon.bslot[0];
2356 if (!vif)
2357 return 0;
2358
2359 avp = (void *)vif->drv_priv;
2360 if (!avp->is_bslot_active)
2361 return 0;
2362
2363 if (!sc->beacon.tx_processed) {
2364 tasklet_disable(&sc->bcon_tasklet);
2365
2366 bf = avp->av_bcbuf;
2367 if (!bf || !bf->bf_mpdu)
2368 goto skip;
2369
2370 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2371 if (status == -EINPROGRESS)
2372 goto skip;
2373
2374 sc->beacon.tx_processed = true;
2375 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2376
2377skip:
2378 tasklet_enable(&sc->bcon_tasklet);
2379 }
2380
2381 return sc->beacon.tx_last;
2382}
2383
52c94f41
MSS
2384static int ath9k_get_stats(struct ieee80211_hw *hw,
2385 struct ieee80211_low_level_stats *stats)
2386{
2387 struct ath_softc *sc = hw->priv;
2388 struct ath_hw *ah = sc->sc_ah;
2389 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2390
2391 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2392 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2393 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2394 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2395 return 0;
2396}
2397
43c35284
FF
2398static u32 fill_chainmask(u32 cap, u32 new)
2399{
2400 u32 filled = 0;
2401 int i;
2402
2403 for (i = 0; cap && new; i++, cap >>= 1) {
2404 if (!(cap & BIT(0)))
2405 continue;
2406
2407 if (new & BIT(0))
2408 filled |= BIT(i);
2409
2410 new >>= 1;
2411 }
2412
2413 return filled;
2414}
2415
2416static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2417{
2418 struct ath_softc *sc = hw->priv;
2419 struct ath_hw *ah = sc->sc_ah;
2420
2421 if (!rx_ant || !tx_ant)
2422 return -EINVAL;
2423
2424 sc->ant_rx = rx_ant;
2425 sc->ant_tx = tx_ant;
2426
2427 if (ah->caps.rx_chainmask == 1)
2428 return 0;
2429
2430 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2431 if (AR_SREV_9100(ah))
2432 ah->rxchainmask = 0x7;
2433 else
2434 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2435
2436 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2437 ath9k_reload_chainmask_settings(sc);
2438
2439 return 0;
2440}
2441
2442static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2443{
2444 struct ath_softc *sc = hw->priv;
2445
2446 *tx_ant = sc->ant_tx;
2447 *rx_ant = sc->ant_rx;
2448 return 0;
2449}
2450
6baff7f9 2451struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2452 .tx = ath9k_tx,
2453 .start = ath9k_start,
2454 .stop = ath9k_stop,
2455 .add_interface = ath9k_add_interface,
6b3b991d 2456 .change_interface = ath9k_change_interface,
8feceb67
VT
2457 .remove_interface = ath9k_remove_interface,
2458 .config = ath9k_config,
8feceb67 2459 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2460 .sta_add = ath9k_sta_add,
2461 .sta_remove = ath9k_sta_remove,
5519541d 2462 .sta_notify = ath9k_sta_notify,
8feceb67 2463 .conf_tx = ath9k_conf_tx,
8feceb67 2464 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2465 .set_key = ath9k_set_key,
8feceb67 2466 .get_tsf = ath9k_get_tsf,
3b5d665b 2467 .set_tsf = ath9k_set_tsf,
8feceb67 2468 .reset_tsf = ath9k_reset_tsf,
4233df6b 2469 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2470 .get_survey = ath9k_get_survey,
3b319aae 2471 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2472 .set_coverage_class = ath9k_set_coverage_class,
69081624 2473 .flush = ath9k_flush,
15b91e83 2474 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2475 .tx_last_beacon = ath9k_tx_last_beacon,
2476 .get_stats = ath9k_get_stats,
43c35284
FF
2477 .set_antenna = ath9k_set_antenna,
2478 .get_antenna = ath9k_get_antenna,
8feceb67 2479};