ath9k: Add counters to distinquish AMPDU enqueues.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ff37e337
S
21static void ath_update_txpow(struct ath_softc *sc)
22{
cbe61d8a 23 struct ath_hw *ah = sc->sc_ah;
ff37e337 24
17d7904d 25 if (sc->curtxpow != sc->config.txpowlimit) {
de40f316 26 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
ff37e337 27 /* read back in case value is clamped */
9cc3271f 28 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
ff37e337
S
29 }
30}
31
32static u8 parse_mpdudensity(u8 mpdudensity)
33{
34 /*
35 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
36 * 0 for no restriction
37 * 1 for 1/4 us
38 * 2 for 1/2 us
39 * 3 for 1 us
40 * 4 for 2 us
41 * 5 for 4 us
42 * 6 for 8 us
43 * 7 for 16 us
44 */
45 switch (mpdudensity) {
46 case 0:
47 return 0;
48 case 1:
49 case 2:
50 case 3:
51 /* Our lower layer calculations limit our precision to
52 1 microsecond */
53 return 1;
54 case 4:
55 return 2;
56 case 5:
57 return 4;
58 case 6:
59 return 8;
60 case 7:
61 return 16;
62 default:
63 return 0;
64 }
65}
66
82880a7c
VT
67static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
68 struct ieee80211_hw *hw)
69{
70 struct ieee80211_channel *curchan = hw->conf.channel;
71 struct ath9k_channel *channel;
72 u8 chan_idx;
73
74 chan_idx = curchan->hw_value;
75 channel = &sc->sc_ah->channels[chan_idx];
76 ath9k_update_ichannel(sc, hw, channel);
77 return channel;
78}
79
55624204 80bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
81{
82 unsigned long flags;
83 bool ret;
84
9ecdef4b
LR
85 spin_lock_irqsave(&sc->sc_pm_lock, flags);
86 ret = ath9k_hw_setpower(sc->sc_ah, mode);
87 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
88
89 return ret;
90}
91
a91d75ae
LR
92void ath9k_ps_wakeup(struct ath_softc *sc)
93{
898c914a 94 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 95 unsigned long flags;
fbb078fc 96 enum ath9k_power_mode power_mode;
a91d75ae
LR
97
98 spin_lock_irqsave(&sc->sc_pm_lock, flags);
99 if (++sc->ps_usecount != 1)
100 goto unlock;
101
fbb078fc 102 power_mode = sc->sc_ah->power_mode;
9ecdef4b 103 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 104
898c914a
FF
105 /*
106 * While the hardware is asleep, the cycle counters contain no
107 * useful data. Better clear them now so that they don't mess up
108 * survey data results.
109 */
fbb078fc
FF
110 if (power_mode != ATH9K_PM_AWAKE) {
111 spin_lock(&common->cc_lock);
112 ath_hw_cycle_counters_update(common);
113 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
114 spin_unlock(&common->cc_lock);
115 }
898c914a 116
a91d75ae
LR
117 unlock:
118 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
119}
120
121void ath9k_ps_restore(struct ath_softc *sc)
122{
898c914a 123 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
124 unsigned long flags;
125
126 spin_lock_irqsave(&sc->sc_pm_lock, flags);
127 if (--sc->ps_usecount != 0)
128 goto unlock;
129
898c914a
FF
130 spin_lock(&common->cc_lock);
131 ath_hw_cycle_counters_update(common);
132 spin_unlock(&common->cc_lock);
133
1dbfd9d4
VN
134 if (sc->ps_idle)
135 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
136 else if (sc->ps_enabled &&
137 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
138 PS_WAIT_FOR_CAB |
139 PS_WAIT_FOR_PSPOLL_DATA |
140 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 141 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145}
146
5ee08656
FF
147static void ath_start_ani(struct ath_common *common)
148{
149 struct ath_hw *ah = common->ah;
150 unsigned long timestamp = jiffies_to_msecs(jiffies);
151 struct ath_softc *sc = (struct ath_softc *) common->priv;
152
153 if (!(sc->sc_flags & SC_OP_ANI_RUN))
154 return;
155
156 if (sc->sc_flags & SC_OP_OFFCHANNEL)
157 return;
158
159 common->ani.longcal_timer = timestamp;
160 common->ani.shortcal_timer = timestamp;
161 common->ani.checkani_timer = timestamp;
162
163 mod_timer(&common->ani.timer,
164 jiffies +
165 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
166}
167
3430098a
FF
168static void ath_update_survey_nf(struct ath_softc *sc, int channel)
169{
170 struct ath_hw *ah = sc->sc_ah;
171 struct ath9k_channel *chan = &ah->channels[channel];
172 struct survey_info *survey = &sc->survey[channel];
173
174 if (chan->noisefloor) {
175 survey->filled |= SURVEY_INFO_NOISE_DBM;
176 survey->noise = chan->noisefloor;
177 }
178}
179
180static void ath_update_survey_stats(struct ath_softc *sc)
181{
182 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah);
184 int pos = ah->curchan - &ah->channels[0];
185 struct survey_info *survey = &sc->survey[pos];
186 struct ath_cycle_counters *cc = &common->cc_survey;
187 unsigned int div = common->clockrate * 1000;
188
0845735e
FF
189 if (!ah->curchan)
190 return;
191
898c914a
FF
192 if (ah->power_mode == ATH9K_PM_AWAKE)
193 ath_hw_cycle_counters_update(common);
3430098a
FF
194
195 if (cc->cycles > 0) {
196 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
197 SURVEY_INFO_CHANNEL_TIME_BUSY |
198 SURVEY_INFO_CHANNEL_TIME_RX |
199 SURVEY_INFO_CHANNEL_TIME_TX;
200 survey->channel_time += cc->cycles / div;
201 survey->channel_time_busy += cc->rx_busy / div;
202 survey->channel_time_rx += cc->rx_frame / div;
203 survey->channel_time_tx += cc->tx_frame / div;
204 }
205 memset(cc, 0, sizeof(*cc));
206
207 ath_update_survey_nf(sc, pos);
208}
209
ff37e337
S
210/*
211 * Set/change channels. If the channel is really being changed, it's done
212 * by reseting the chip. To accomplish this we must first cleanup any pending
213 * DMA, then restart stuff.
214*/
0e2dedf9
JM
215int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
216 struct ath9k_channel *hchan)
ff37e337 217{
20bd2a09 218 struct ath_wiphy *aphy = hw->priv;
cbe61d8a 219 struct ath_hw *ah = sc->sc_ah;
c46917bb 220 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 221 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 222 bool fastcc = true, stopped;
ae8d2858 223 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 224 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 225 int r;
ff37e337
S
226
227 if (sc->sc_flags & SC_OP_INVALID)
228 return -EIO;
229
5ee08656
FF
230 del_timer_sync(&common->ani.timer);
231 cancel_work_sync(&sc->paprd_work);
232 cancel_work_sync(&sc->hw_check_work);
233 cancel_delayed_work_sync(&sc->tx_complete_work);
234
3cbb5dd7
VN
235 ath9k_ps_wakeup(sc);
236
6a6733f2
LR
237 spin_lock_bh(&sc->sc_pcu_lock);
238
c0d7c7af
LR
239 /*
240 * This is only performed if the channel settings have
241 * actually changed.
242 *
243 * To switch channels clear any pending DMA operations;
244 * wait long enough for the RX fifo to drain, reset the
245 * hardware at the new frequency, and then re-enable
246 * the relevant bits of the h/w.
247 */
4df3071e 248 ath9k_hw_disable_interrupts(ah);
080e1a25 249 stopped = ath_drain_all_txq(sc, false);
5e848f78 250
080e1a25
FF
251 if (!ath_stoprecv(sc))
252 stopped = false;
ff37e337 253
8b3f4616
FF
254 if (!ath9k_hw_check_alive(ah))
255 stopped = false;
256
c0d7c7af
LR
257 /* XXX: do not flush receive queue here. We don't want
258 * to flush data frames already in queue because of
259 * changing channel. */
ff37e337 260
5ee08656 261 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
262 fastcc = false;
263
20bd2a09
FF
264 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
265 caldata = &aphy->caldata;
266
226afe68
JP
267 ath_dbg(common, ATH_DBG_CONFIG,
268 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
269 sc->sc_ah->curchan->channel,
270 channel->center_freq, conf_is_ht40(conf),
271 fastcc);
ff37e337 272
20bd2a09 273 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 274 if (r) {
3800276a
JP
275 ath_err(common,
276 "Unable to reset channel (%u MHz), reset status %d\n",
277 channel->center_freq, r);
3989279c 278 goto ps_restore;
ff37e337 279 }
c0d7c7af 280
c0d7c7af 281 if (ath_startrecv(sc) != 0) {
3800276a 282 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ
283 r = -EIO;
284 goto ps_restore;
c0d7c7af
LR
285 }
286
c0d7c7af 287 ath_update_txpow(sc);
3069168c 288 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 289
48a6a468 290 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
1186488b
RM
291 if (sc->sc_flags & SC_OP_BEACONS)
292 ath_beacon_config(sc, NULL);
5ee08656 293 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
48a6a468 294 ath_start_ani(common);
5ee08656
FF
295 }
296
3989279c 297 ps_restore:
6a6733f2
LR
298 spin_unlock_bh(&sc->sc_pcu_lock);
299
3cbb5dd7 300 ath9k_ps_restore(sc);
3989279c 301 return r;
ff37e337
S
302}
303
9f42c2b6
FF
304static void ath_paprd_activate(struct ath_softc *sc)
305{
306 struct ath_hw *ah = sc->sc_ah;
20bd2a09 307 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 308 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
309 int chain;
310
20bd2a09 311 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
312 return;
313
314 ath9k_ps_wakeup(sc);
ddfef792 315 ar9003_paprd_enable(ah, false);
9f42c2b6 316 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 317 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
318 continue;
319
20bd2a09 320 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
321 }
322
323 ar9003_paprd_enable(ah, true);
324 ath9k_ps_restore(sc);
325}
326
7607cbe2
FF
327static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
328{
329 struct ieee80211_hw *hw = sc->hw;
330 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
331 struct ath_tx_control txctl;
332 int time_left;
333
334 memset(&txctl, 0, sizeof(txctl));
335 txctl.txq = sc->tx.txq_map[WME_AC_BE];
336
337 memset(tx_info, 0, sizeof(*tx_info));
338 tx_info->band = hw->conf.channel->band;
339 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
340 tx_info->control.rates[0].idx = 0;
341 tx_info->control.rates[0].count = 1;
342 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
343 tx_info->control.rates[1].idx = -1;
344
345 init_completion(&sc->paprd_complete);
346 sc->paprd_pending = true;
347 txctl.paprd = BIT(chain);
348 if (ath_tx_start(hw, skb, &txctl) != 0)
349 return false;
350
351 time_left = wait_for_completion_timeout(&sc->paprd_complete,
352 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
353 sc->paprd_pending = false;
354
355 if (!time_left)
356 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
357 "Timeout waiting for paprd training on TX chain %d\n",
358 chain);
359
360 return !!time_left;
361}
362
9f42c2b6
FF
363void ath_paprd_calibrate(struct work_struct *work)
364{
365 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
366 struct ieee80211_hw *hw = sc->hw;
367 struct ath_hw *ah = sc->sc_ah;
368 struct ieee80211_hdr *hdr;
369 struct sk_buff *skb = NULL;
20bd2a09 370 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 371 struct ath_common *common = ath9k_hw_common(ah);
066dae93 372 int ftype;
9f42c2b6
FF
373 int chain_ok = 0;
374 int chain;
375 int len = 1800;
9f42c2b6 376
20bd2a09
FF
377 if (!caldata)
378 return;
379
1bf38661
FF
380 if (ar9003_paprd_init_table(ah) < 0)
381 return;
382
9f42c2b6
FF
383 skb = alloc_skb(len, GFP_KERNEL);
384 if (!skb)
385 return;
386
9f42c2b6
FF
387 skb_put(skb, len);
388 memset(skb->data, 0, len);
389 hdr = (struct ieee80211_hdr *)skb->data;
390 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
391 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 392 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
393 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
394 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
395 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
396
47399f1a 397 ath9k_ps_wakeup(sc);
9f42c2b6 398 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 399 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
400 continue;
401
402 chain_ok = 0;
9f42c2b6 403
7607cbe2
FF
404 ath_dbg(common, ATH_DBG_CALIBRATE,
405 "Sending PAPRD frame for thermal measurement "
406 "on chain %d\n", chain);
407 if (!ath_paprd_send_frame(sc, skb, chain))
408 goto fail_paprd;
9f42c2b6 409
9f42c2b6 410 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 411
7607cbe2
FF
412 ath_dbg(common, ATH_DBG_CALIBRATE,
413 "Sending PAPRD training frame on chain %d\n", chain);
414 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 415 goto fail_paprd;
9f42c2b6
FF
416
417 if (!ar9003_paprd_is_done(ah))
418 break;
419
20bd2a09 420 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF
421 break;
422
423 chain_ok = 1;
424 }
425 kfree_skb(skb);
426
427 if (chain_ok) {
20bd2a09 428 caldata->paprd_done = true;
9f42c2b6
FF
429 ath_paprd_activate(sc);
430 }
431
ca369eb4 432fail_paprd:
9f42c2b6
FF
433 ath9k_ps_restore(sc);
434}
435
ff37e337
S
436/*
437 * This routine performs the periodic noise floor calibration function
438 * that is used to adjust and optimize the chip performance. This
439 * takes environmental changes (location, temperature) into account.
440 * When the task is complete, it reschedules itself depending on the
441 * appropriate interval that was calculated.
442 */
55624204 443void ath_ani_calibrate(unsigned long data)
ff37e337 444{
20977d3e
S
445 struct ath_softc *sc = (struct ath_softc *)data;
446 struct ath_hw *ah = sc->sc_ah;
c46917bb 447 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
448 bool longcal = false;
449 bool shortcal = false;
450 bool aniflag = false;
451 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 452 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 453 unsigned long flags;
6044474e
FF
454
455 if (ah->caldata && ah->caldata->nfcal_interference)
456 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
457 else
458 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 459
20977d3e
S
460 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
461 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 462
1ffc1c61
JM
463 /* Only calibrate if awake */
464 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
465 goto set_timer;
466
467 ath9k_ps_wakeup(sc);
468
ff37e337 469 /* Long calibration runs independently of short calibration. */
6044474e 470 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 471 longcal = true;
226afe68 472 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 473 common->ani.longcal_timer = timestamp;
ff37e337
S
474 }
475
17d7904d 476 /* Short calibration applies only while caldone is false */
3d536acf
LR
477 if (!common->ani.caldone) {
478 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 479 shortcal = true;
226afe68
JP
480 ath_dbg(common, ATH_DBG_ANI,
481 "shortcal @%lu\n", jiffies);
3d536acf
LR
482 common->ani.shortcal_timer = timestamp;
483 common->ani.resetcal_timer = timestamp;
ff37e337
S
484 }
485 } else {
3d536acf 486 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 487 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
488 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
489 if (common->ani.caldone)
490 common->ani.resetcal_timer = timestamp;
ff37e337
S
491 }
492 }
493
494 /* Verify whether we must check ANI */
e36b27af
LR
495 if ((timestamp - common->ani.checkani_timer) >=
496 ah->config.ani_poll_interval) {
ff37e337 497 aniflag = true;
3d536acf 498 common->ani.checkani_timer = timestamp;
ff37e337
S
499 }
500
501 /* Skip all processing if there's nothing to do. */
502 if (longcal || shortcal || aniflag) {
503 /* Call ANI routine if necessary */
b5bfc568
FF
504 if (aniflag) {
505 spin_lock_irqsave(&common->cc_lock, flags);
22e66a4c 506 ath9k_hw_ani_monitor(ah, ah->curchan);
3430098a 507 ath_update_survey_stats(sc);
b5bfc568
FF
508 spin_unlock_irqrestore(&common->cc_lock, flags);
509 }
ff37e337
S
510
511 /* Perform calibration if necessary */
512 if (longcal || shortcal) {
3d536acf 513 common->ani.caldone =
43c27613
LR
514 ath9k_hw_calibrate(ah,
515 ah->curchan,
516 common->rx_chainmask,
517 longcal);
ff37e337
S
518 }
519 }
520
1ffc1c61
JM
521 ath9k_ps_restore(sc);
522
20977d3e 523set_timer:
ff37e337
S
524 /*
525 * Set timer interval based on previous results.
526 * The interval must be the shortest necessary to satisfy ANI,
527 * short calibration and long calibration.
528 */
aac9207e 529 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 530 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
531 cal_interval = min(cal_interval,
532 (u32)ah->config.ani_poll_interval);
3d536acf 533 if (!common->ani.caldone)
20977d3e 534 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 535
3d536acf 536 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
537 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
538 if (!ah->caldata->paprd_done)
9f42c2b6 539 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 540 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
541 ath_paprd_activate(sc);
542 }
ff37e337
S
543}
544
ff37e337
S
545static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
546{
547 struct ath_node *an;
ea066d5a 548 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
549 an = (struct ath_node *)sta->drv_priv;
550
ea066d5a
MSS
551 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
552 sc->sc_flags |= SC_OP_ENABLE_APM;
553
87792efc 554 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 555 ath_tx_node_init(sc, an);
9e98ac65 556 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
557 sta->ht_cap.ampdu_factor);
558 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
559 }
ff37e337
S
560}
561
562static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
563{
564 struct ath_node *an = (struct ath_node *)sta->drv_priv;
565
566 if (sc->sc_flags & SC_OP_TXAGGR)
567 ath_tx_node_cleanup(sc, an);
568}
569
347809fc
FF
570void ath_hw_check(struct work_struct *work)
571{
572 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
573 int i;
574
575 ath9k_ps_wakeup(sc);
576
577 for (i = 0; i < 3; i++) {
578 if (ath9k_hw_check_alive(sc->sc_ah))
579 goto out;
580
581 msleep(1);
582 }
fac6b6a0 583 ath_reset(sc, true);
347809fc
FF
584
585out:
586 ath9k_ps_restore(sc);
587}
588
55624204 589void ath9k_tasklet(unsigned long data)
ff37e337
S
590{
591 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 592 struct ath_hw *ah = sc->sc_ah;
c46917bb 593 struct ath_common *common = ath9k_hw_common(ah);
af03abec 594
17d7904d 595 u32 status = sc->intrstatus;
b5c80475 596 u32 rxmask;
ff37e337 597
153e080d
VT
598 ath9k_ps_wakeup(sc);
599
347809fc 600 if (status & ATH9K_INT_FATAL) {
fac6b6a0 601 ath_reset(sc, true);
153e080d 602 ath9k_ps_restore(sc);
ff37e337 603 return;
063d8be3 604 }
ff37e337 605
52671e43 606 spin_lock(&sc->sc_pcu_lock);
6a6733f2 607
8b3f4616
FF
608 /*
609 * Only run the baseband hang check if beacons stop working in AP or
610 * IBSS mode, because it has a high false positive rate. For station
611 * mode it should not be necessary, since the upper layers will detect
612 * this through a beacon miss automatically and the following channel
613 * change will trigger a hardware reset anyway
614 */
615 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
616 !ath9k_hw_check_alive(ah))
347809fc
FF
617 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
618
b5c80475
FF
619 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
620 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
621 ATH9K_INT_RXORN);
622 else
623 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
624
625 if (status & rxmask) {
b5c80475
FF
626 /* Check for high priority Rx first */
627 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
628 (status & ATH9K_INT_RXHP))
629 ath_rx_tasklet(sc, 0, true);
630
631 ath_rx_tasklet(sc, 0, false);
ff37e337
S
632 }
633
e5003249
VT
634 if (status & ATH9K_INT_TX) {
635 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
636 ath_tx_edma_tasklet(sc);
637 else
638 ath_tx_tasklet(sc);
639 }
063d8be3 640
96148326 641 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
642 /*
643 * TSF sync does not look correct; remain awake to sync with
644 * the next Beacon.
645 */
226afe68
JP
646 ath_dbg(common, ATH_DBG_PS,
647 "TSFOOR - Sync with next Beacon\n");
1b04b930 648 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
649 }
650
766ec4a9 651 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
652 if (status & ATH9K_INT_GENTIMER)
653 ath_gen_timer_isr(sc->sc_ah);
654
ff37e337 655 /* re-enable hardware interrupt */
4df3071e 656 ath9k_hw_enable_interrupts(ah);
6a6733f2 657
52671e43 658 spin_unlock(&sc->sc_pcu_lock);
153e080d 659 ath9k_ps_restore(sc);
ff37e337
S
660}
661
6baff7f9 662irqreturn_t ath_isr(int irq, void *dev)
ff37e337 663{
063d8be3
S
664#define SCHED_INTR ( \
665 ATH9K_INT_FATAL | \
666 ATH9K_INT_RXORN | \
667 ATH9K_INT_RXEOL | \
668 ATH9K_INT_RX | \
b5c80475
FF
669 ATH9K_INT_RXLP | \
670 ATH9K_INT_RXHP | \
063d8be3
S
671 ATH9K_INT_TX | \
672 ATH9K_INT_BMISS | \
673 ATH9K_INT_CST | \
ebb8e1d7
VT
674 ATH9K_INT_TSFOOR | \
675 ATH9K_INT_GENTIMER)
063d8be3 676
ff37e337 677 struct ath_softc *sc = dev;
cbe61d8a 678 struct ath_hw *ah = sc->sc_ah;
b5bfc568 679 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
680 enum ath9k_int status;
681 bool sched = false;
682
063d8be3
S
683 /*
684 * The hardware is not ready/present, don't
685 * touch anything. Note this can happen early
686 * on if the IRQ is shared.
687 */
688 if (sc->sc_flags & SC_OP_INVALID)
689 return IRQ_NONE;
ff37e337 690
063d8be3
S
691
692 /* shared irq, not for us */
693
153e080d 694 if (!ath9k_hw_intrpend(ah))
063d8be3 695 return IRQ_NONE;
063d8be3
S
696
697 /*
698 * Figure out the reason(s) for the interrupt. Note
699 * that the hal returns a pseudo-ISR that may include
700 * bits we haven't explicitly enabled so we mask the
701 * value to insure we only process bits we requested.
702 */
703 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 704 status &= ah->imask; /* discard unasked-for bits */
ff37e337 705
063d8be3
S
706 /*
707 * If there are no status bits set, then this interrupt was not
708 * for me (should have been caught above).
709 */
153e080d 710 if (!status)
063d8be3 711 return IRQ_NONE;
ff37e337 712
063d8be3
S
713 /* Cache the status */
714 sc->intrstatus = status;
715
716 if (status & SCHED_INTR)
717 sched = true;
718
719 /*
720 * If a FATAL or RXORN interrupt is received, we have to reset the
721 * chip immediately.
722 */
b5c80475
FF
723 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
724 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
725 goto chip_reset;
726
08578b8f
LR
727 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
728 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
729
730 spin_lock(&common->cc_lock);
731 ath_hw_cycle_counters_update(common);
08578b8f 732 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
733 spin_unlock(&common->cc_lock);
734
08578b8f
LR
735 goto chip_reset;
736 }
737
063d8be3
S
738 if (status & ATH9K_INT_SWBA)
739 tasklet_schedule(&sc->bcon_tasklet);
740
741 if (status & ATH9K_INT_TXURN)
742 ath9k_hw_updatetxtriglevel(ah, true);
743
b5c80475
FF
744 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
745 if (status & ATH9K_INT_RXEOL) {
746 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
747 ath9k_hw_set_interrupts(ah, ah->imask);
748 }
749 }
750
063d8be3 751 if (status & ATH9K_INT_MIB) {
ff37e337 752 /*
063d8be3
S
753 * Disable interrupts until we service the MIB
754 * interrupt; otherwise it will continue to
755 * fire.
ff37e337 756 */
4df3071e 757 ath9k_hw_disable_interrupts(ah);
063d8be3
S
758 /*
759 * Let the hal handle the event. We assume
760 * it will clear whatever condition caused
761 * the interrupt.
762 */
88eac2da 763 spin_lock(&common->cc_lock);
bfc472bb 764 ath9k_hw_proc_mib_event(ah);
88eac2da 765 spin_unlock(&common->cc_lock);
4df3071e 766 ath9k_hw_enable_interrupts(ah);
063d8be3 767 }
ff37e337 768
153e080d
VT
769 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
770 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
771 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
772 goto chip_reset;
063d8be3
S
773 /* Clear RxAbort bit so that we can
774 * receive frames */
9ecdef4b 775 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 776 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 777 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 778 }
063d8be3
S
779
780chip_reset:
ff37e337 781
817e11de
S
782 ath_debug_stat_interrupt(sc, status);
783
ff37e337 784 if (sched) {
4df3071e
FF
785 /* turn off every interrupt */
786 ath9k_hw_disable_interrupts(ah);
ff37e337
S
787 tasklet_schedule(&sc->intr_tq);
788 }
789
790 return IRQ_HANDLED;
063d8be3
S
791
792#undef SCHED_INTR
ff37e337
S
793}
794
f078f209 795static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 796 struct ieee80211_channel *chan,
094d05dc 797 enum nl80211_channel_type channel_type)
f078f209
LR
798{
799 u32 chanmode = 0;
f078f209
LR
800
801 switch (chan->band) {
802 case IEEE80211_BAND_2GHZ:
094d05dc
S
803 switch(channel_type) {
804 case NL80211_CHAN_NO_HT:
805 case NL80211_CHAN_HT20:
f078f209 806 chanmode = CHANNEL_G_HT20;
094d05dc
S
807 break;
808 case NL80211_CHAN_HT40PLUS:
f078f209 809 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
810 break;
811 case NL80211_CHAN_HT40MINUS:
f078f209 812 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
813 break;
814 }
f078f209
LR
815 break;
816 case IEEE80211_BAND_5GHZ:
094d05dc
S
817 switch(channel_type) {
818 case NL80211_CHAN_NO_HT:
819 case NL80211_CHAN_HT20:
f078f209 820 chanmode = CHANNEL_A_HT20;
094d05dc
S
821 break;
822 case NL80211_CHAN_HT40PLUS:
f078f209 823 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
824 break;
825 case NL80211_CHAN_HT40MINUS:
f078f209 826 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
827 break;
828 }
f078f209
LR
829 break;
830 default:
831 break;
832 }
833
834 return chanmode;
835}
836
8feceb67 837static void ath9k_bss_assoc_info(struct ath_softc *sc,
9fa23e17 838 struct ieee80211_hw *hw,
5640b08e 839 struct ieee80211_vif *vif,
8feceb67 840 struct ieee80211_bss_conf *bss_conf)
f078f209 841{
9fa23e17 842 struct ath_wiphy *aphy = hw->priv;
f2b2143e 843 struct ath_hw *ah = sc->sc_ah;
1510718d 844 struct ath_common *common = ath9k_hw_common(ah);
f078f209 845
8feceb67 846 if (bss_conf->assoc) {
226afe68
JP
847 ath_dbg(common, ATH_DBG_CONFIG,
848 "Bss Info ASSOC %d, bssid: %pM\n",
849 bss_conf->aid, common->curbssid);
f078f209 850
8feceb67 851 /* New association, store aid */
1510718d 852 common->curaid = bss_conf->aid;
f2b2143e 853 ath9k_hw_write_associd(ah);
2664f201
SB
854
855 /*
856 * Request a re-configuration of Beacon related timers
857 * on the receipt of the first Beacon frame (i.e.,
858 * after time sync with the AP).
859 */
1b04b930 860 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 861
8feceb67 862 /* Configure the beacon */
2c3db3d5 863 ath_beacon_config(sc, vif);
f078f209 864
8feceb67 865 /* Reset rssi stats */
9fa23e17 866 aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
22e66a4c 867 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 868
6c3118e2 869 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 870 ath_start_ani(common);
8feceb67 871 } else {
226afe68 872 ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 873 common->curaid = 0;
f38faa31 874 /* Stop ANI */
6c3118e2 875 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 876 del_timer_sync(&common->ani.timer);
f078f209 877 }
8feceb67 878}
f078f209 879
68a89116 880void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 881{
cbe61d8a 882 struct ath_hw *ah = sc->sc_ah;
c46917bb 883 struct ath_common *common = ath9k_hw_common(ah);
68a89116 884 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 885 int r;
500c064d 886
3cbb5dd7 887 ath9k_ps_wakeup(sc);
6a6733f2
LR
888 spin_lock_bh(&sc->sc_pcu_lock);
889
93b1b37f 890 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 891
159cd468
VT
892 if (!ah->curchan)
893 ah->curchan = ath_get_curchannel(sc, sc->hw);
894
20bd2a09 895 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 896 if (r) {
3800276a
JP
897 ath_err(common,
898 "Unable to reset channel (%u MHz), reset status %d\n",
899 channel->center_freq, r);
500c064d 900 }
500c064d
VT
901
902 ath_update_txpow(sc);
903 if (ath_startrecv(sc) != 0) {
3800276a 904 ath_err(common, "Unable to restart recv logic\n");
c2731b81 905 goto out;
500c064d 906 }
500c064d 907 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 908 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
909
910 /* Re-Enable interrupts */
3069168c 911 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT
912
913 /* Enable LED */
08fc5c1b 914 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 915 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 916 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 917
68a89116 918 ieee80211_wake_queues(hw);
c2731b81 919out:
6a6733f2
LR
920 spin_unlock_bh(&sc->sc_pcu_lock);
921
3cbb5dd7 922 ath9k_ps_restore(sc);
500c064d
VT
923}
924
68a89116 925void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 926{
cbe61d8a 927 struct ath_hw *ah = sc->sc_ah;
68a89116 928 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 929 int r;
500c064d 930
3cbb5dd7 931 ath9k_ps_wakeup(sc);
6a6733f2
LR
932 spin_lock_bh(&sc->sc_pcu_lock);
933
68a89116 934 ieee80211_stop_queues(hw);
500c064d 935
982723df
VN
936 /*
937 * Keep the LED on when the radio is disabled
938 * during idle unassociated state.
939 */
940 if (!sc->ps_idle) {
941 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
942 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
943 }
500c064d
VT
944
945 /* Disable interrupts */
4df3071e 946 ath9k_hw_disable_interrupts(ah);
500c064d 947
043a0405 948 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 949
500c064d
VT
950 ath_stoprecv(sc); /* turn off frame recv */
951 ath_flushrecv(sc); /* flush recv queue */
952
159cd468 953 if (!ah->curchan)
68a89116 954 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 955
20bd2a09 956 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 957 if (r) {
3800276a
JP
958 ath_err(ath9k_hw_common(sc->sc_ah),
959 "Unable to reset channel (%u MHz), reset status %d\n",
960 channel->center_freq, r);
500c064d 961 }
500c064d
VT
962
963 ath9k_hw_phy_disable(ah);
5e848f78 964
93b1b37f 965 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
966
967 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 968 ath9k_ps_restore(sc);
6a6733f2 969
9ecdef4b 970 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT
971}
972
ff37e337
S
973int ath_reset(struct ath_softc *sc, bool retry_tx)
974{
cbe61d8a 975 struct ath_hw *ah = sc->sc_ah;
c46917bb 976 struct ath_common *common = ath9k_hw_common(ah);
030bb495 977 struct ieee80211_hw *hw = sc->hw;
ae8d2858 978 int r;
ff37e337 979
2ab81d4a
S
980 /* Stop ANI */
981 del_timer_sync(&common->ani.timer);
982
6a6733f2
LR
983 spin_lock_bh(&sc->sc_pcu_lock);
984
cc9c378a
S
985 ieee80211_stop_queues(hw);
986
4df3071e 987 ath9k_hw_disable_interrupts(ah);
043a0405 988 ath_drain_all_txq(sc, retry_tx);
5e848f78 989
ff37e337
S
990 ath_stoprecv(sc);
991 ath_flushrecv(sc);
992
20bd2a09 993 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 994 if (r)
3800276a
JP
995 ath_err(common,
996 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
997
998 if (ath_startrecv(sc) != 0)
3800276a 999 ath_err(common, "Unable to start recv logic\n");
ff37e337
S
1000
1001 /*
1002 * We may be doing a reset in response to a request
1003 * that changes the channel so update any state that
1004 * might change as a result.
1005 */
ff37e337
S
1006 ath_update_txpow(sc);
1007
52b8ac92 1008 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
2c3db3d5 1009 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1010
3069168c 1011 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S
1012
1013 if (retry_tx) {
1014 int i;
1015 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1016 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1017 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1018 ath_txq_schedule(sc, &sc->tx.txq[i]);
1019 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1020 }
1021 }
1022 }
1023
cc9c378a 1024 ieee80211_wake_queues(hw);
6a6733f2 1025 spin_unlock_bh(&sc->sc_pcu_lock);
cc9c378a 1026
2ab81d4a
S
1027 /* Start ANI */
1028 ath_start_ani(common);
1029
ae8d2858 1030 return r;
ff37e337
S
1031}
1032
5f8e077c
LR
1033/* XXX: Remove me once we don't depend on ath9k_channel for all
1034 * this redundant data */
0e2dedf9
JM
1035void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1036 struct ath9k_channel *ichan)
5f8e077c 1037{
5f8e077c
LR
1038 struct ieee80211_channel *chan = hw->conf.channel;
1039 struct ieee80211_conf *conf = &hw->conf;
1040
1041 ichan->channel = chan->center_freq;
1042 ichan->chan = chan;
1043
1044 if (chan->band == IEEE80211_BAND_2GHZ) {
1045 ichan->chanmode = CHANNEL_G;
8813262e 1046 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR
1047 } else {
1048 ichan->chanmode = CHANNEL_A;
1049 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1050 }
1051
25c56eec 1052 if (conf_is_ht(conf))
5f8e077c
LR
1053 ichan->chanmode = ath_get_extchanmode(sc, chan,
1054 conf->channel_type);
5f8e077c
LR
1055}
1056
ff37e337
S
1057/**********************/
1058/* mac80211 callbacks */
1059/**********************/
1060
8feceb67 1061static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1062{
bce048d7
JM
1063 struct ath_wiphy *aphy = hw->priv;
1064 struct ath_softc *sc = aphy->sc;
af03abec 1065 struct ath_hw *ah = sc->sc_ah;
c46917bb 1066 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1067 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1068 struct ath9k_channel *init_channel;
82880a7c 1069 int r;
f078f209 1070
226afe68
JP
1071 ath_dbg(common, ATH_DBG_CONFIG,
1072 "Starting driver with initial channel: %d MHz\n",
1073 curchan->center_freq);
f078f209 1074
141b38b6
S
1075 mutex_lock(&sc->mutex);
1076
9580a222
JM
1077 if (ath9k_wiphy_started(sc)) {
1078 if (sc->chan_idx == curchan->hw_value) {
1079 /*
1080 * Already on the operational channel, the new wiphy
1081 * can be marked active.
1082 */
1083 aphy->state = ATH_WIPHY_ACTIVE;
1084 ieee80211_wake_queues(hw);
1085 } else {
1086 /*
1087 * Another wiphy is on another channel, start the new
1088 * wiphy in paused state.
1089 */
1090 aphy->state = ATH_WIPHY_PAUSED;
1091 ieee80211_stop_queues(hw);
1092 }
1093 mutex_unlock(&sc->mutex);
1094 return 0;
1095 }
1096 aphy->state = ATH_WIPHY_ACTIVE;
1097
8feceb67 1098 /* setup initial channel */
f078f209 1099
82880a7c 1100 sc->chan_idx = curchan->hw_value;
f078f209 1101
82880a7c 1102 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S
1103
1104 /* Reset SERDES registers */
af03abec 1105 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1106
1107 /*
1108 * The basic interface to setting the hardware in a good
1109 * state is ``reset''. On return the hardware is known to
1110 * be powered up and with interrupts disabled. This must
1111 * be followed by initialization of the appropriate bits
1112 * and then setup of the interrupt mask.
1113 */
4bdd1e97 1114 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1115 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1116 if (r) {
3800276a
JP
1117 ath_err(common,
1118 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1119 r, curchan->center_freq);
4bdd1e97 1120 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1121 goto mutex_unlock;
ff37e337 1122 }
ff37e337
S
1123
1124 /*
1125 * This is needed only to setup initial state
1126 * but it's best done after a reset.
1127 */
1128 ath_update_txpow(sc);
8feceb67 1129
ff37e337
S
1130 /*
1131 * Setup the hardware after reset:
1132 * The receive engine is set going.
1133 * Frame transmit is handled entirely
1134 * in the frame output path; there's nothing to do
1135 * here except setup the interrupt mask.
1136 */
1137 if (ath_startrecv(sc) != 0) {
3800276a 1138 ath_err(common, "Unable to start recv logic\n");
141b38b6 1139 r = -EIO;
4bdd1e97 1140 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1141 goto mutex_unlock;
f078f209 1142 }
4bdd1e97 1143 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1144
ff37e337 1145 /* Setup our intr mask. */
b5c80475
FF
1146 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1147 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1148 ATH9K_INT_GLOBAL;
1149
1150 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1151 ah->imask |= ATH9K_INT_RXHP |
1152 ATH9K_INT_RXLP |
1153 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1154 else
1155 ah->imask |= ATH9K_INT_RX;
ff37e337 1156
364734fa 1157 ah->imask |= ATH9K_INT_GTT;
ff37e337 1158
af03abec 1159 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1160 ah->imask |= ATH9K_INT_CST;
ff37e337 1161
ff37e337 1162 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1163 sc->sc_ah->is_monitoring = false;
ff37e337
S
1164
1165 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1166 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1167 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1168
bce048d7 1169 ieee80211_wake_queues(hw);
ff37e337 1170
42935eca 1171 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1172
766ec4a9
LR
1173 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1174 !ah->btcoex_hw.enabled) {
5e197292
LR
1175 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1176 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1177 ath9k_hw_btcoex_enable(ah);
f985ad12 1178
5bb12791
LR
1179 if (common->bus_ops->bt_coex_prep)
1180 common->bus_ops->bt_coex_prep(common);
766ec4a9 1181 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1182 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1183 }
1184
2b7e6bce
MSS
1185 /* User has the option to provide pm-qos value as a module
1186 * parameter rather than using the default value of
1187 * 'ATH9K_PM_QOS_DEFAULT_VALUE'.
1188 */
4dc3530d 1189 pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value);
10598c12 1190
8060e169
VT
1191 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1192 common->bus_ops->extn_synch_en(common);
1193
141b38b6
S
1194mutex_unlock:
1195 mutex_unlock(&sc->mutex);
1196
ae8d2858 1197 return r;
f078f209
LR
1198}
1199
8feceb67
VT
1200static int ath9k_tx(struct ieee80211_hw *hw,
1201 struct sk_buff *skb)
f078f209 1202{
bce048d7
JM
1203 struct ath_wiphy *aphy = hw->priv;
1204 struct ath_softc *sc = aphy->sc;
c46917bb 1205 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1206 struct ath_tx_control txctl;
1bc14880 1207 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1208
8089cc47 1209 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
226afe68
JP
1210 ath_dbg(common, ATH_DBG_XMIT,
1211 "ath9k: %s: TX in unexpected wiphy state %d\n",
1212 wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM
1213 goto exit;
1214 }
1215
96148326 1216 if (sc->ps_enabled) {
dc8c4585
JM
1217 /*
1218 * mac80211 does not set PM field for normal data frames, so we
1219 * need to update that based on the current PS mode.
1220 */
1221 if (ieee80211_is_data(hdr->frame_control) &&
1222 !ieee80211_is_nullfunc(hdr->frame_control) &&
1223 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1224 ath_dbg(common, ATH_DBG_PS,
1225 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1226 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1227 }
1228 }
1229
9a23f9ca
JM
1230 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1231 /*
1232 * We are using PS-Poll and mac80211 can request TX while in
1233 * power save mode. Need to wake up hardware for the TX to be
1234 * completed and if needed, also for RX of buffered frames.
1235 */
9a23f9ca 1236 ath9k_ps_wakeup(sc);
fdf76622
VT
1237 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1238 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1239 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1240 ath_dbg(common, ATH_DBG_PS,
1241 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1242 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1243 } else {
226afe68
JP
1244 ath_dbg(common, ATH_DBG_PS,
1245 "Wake up to complete TX\n");
1b04b930 1246 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1247 }
1248 /*
1249 * The actual restore operation will happen only after
1250 * the sc_flags bit is cleared. We are just dropping
1251 * the ps_usecount here.
1252 */
1253 ath9k_ps_restore(sc);
1254 }
1255
528f0c6b 1256 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1257 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1258
226afe68 1259 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1260
c52f33d0 1261 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1262 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1263 goto exit;
8feceb67
VT
1264 }
1265
528f0c6b
S
1266 return 0;
1267exit:
1268 dev_kfree_skb_any(skb);
8feceb67 1269 return 0;
f078f209
LR
1270}
1271
8feceb67 1272static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1273{
bce048d7
JM
1274 struct ath_wiphy *aphy = hw->priv;
1275 struct ath_softc *sc = aphy->sc;
af03abec 1276 struct ath_hw *ah = sc->sc_ah;
c46917bb 1277 struct ath_common *common = ath9k_hw_common(ah);
447a42c2 1278 int i;
f078f209 1279
4c483817
S
1280 mutex_lock(&sc->mutex);
1281
9580a222
JM
1282 aphy->state = ATH_WIPHY_INACTIVE;
1283
9a75c2ff
VN
1284 if (led_blink)
1285 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1286
c94dbff7 1287 cancel_delayed_work_sync(&sc->tx_complete_work);
9f42c2b6 1288 cancel_work_sync(&sc->paprd_work);
347809fc 1289 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1290
447a42c2
RM
1291 for (i = 0; i < sc->num_sec_wiphy; i++) {
1292 if (sc->sec_wiphy[i])
1293 break;
1294 }
1295
1296 if (i == sc->num_sec_wiphy) {
c94dbff7
LR
1297 cancel_delayed_work_sync(&sc->wiphy_work);
1298 cancel_work_sync(&sc->chan_work);
1299 }
1300
9c84b797 1301 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1302 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1303 mutex_unlock(&sc->mutex);
9c84b797
S
1304 return;
1305 }
8feceb67 1306
9580a222
JM
1307 if (ath9k_wiphy_started(sc)) {
1308 mutex_unlock(&sc->mutex);
1309 return; /* another wiphy still in use */
1310 }
1311
3867cf6a
S
1312 /* Ensure HW is awake when we try to shut it down. */
1313 ath9k_ps_wakeup(sc);
1314
766ec4a9 1315 if (ah->btcoex_hw.enabled) {
af03abec 1316 ath9k_hw_btcoex_disable(ah);
766ec4a9 1317 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1318 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1319 }
1320
6a6733f2
LR
1321 spin_lock_bh(&sc->sc_pcu_lock);
1322
ff37e337
S
1323 /* make sure h/w will not generate any interrupt
1324 * before setting the invalid flag. */
4df3071e 1325 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1326
1327 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1328 ath_drain_all_txq(sc, false);
ff37e337 1329 ath_stoprecv(sc);
af03abec 1330 ath9k_hw_phy_disable(ah);
6a6733f2 1331 } else
b77f483f 1332 sc->rx.rxlink = NULL;
ff37e337 1333
ff37e337 1334 /* disable HAL and put h/w to sleep */
af03abec
LR
1335 ath9k_hw_disable(ah);
1336 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
1337
1338 spin_unlock_bh(&sc->sc_pcu_lock);
1339
3867cf6a
S
1340 ath9k_ps_restore(sc);
1341
a08e7ade 1342 sc->ps_idle = true;
afe68d0a 1343 ath9k_set_wiphy_idle(aphy, true);
a08e7ade 1344 ath_radio_disable(sc, hw);
ff37e337
S
1345
1346 sc->sc_flags |= SC_OP_INVALID;
500c064d 1347
98c316e3 1348 pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE);
10598c12 1349
141b38b6
S
1350 mutex_unlock(&sc->mutex);
1351
226afe68 1352 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1353}
1354
4801416c
BG
1355bool ath9k_uses_beacons(int type)
1356{
1357 switch (type) {
1358 case NL80211_IFTYPE_AP:
1359 case NL80211_IFTYPE_ADHOC:
1360 case NL80211_IFTYPE_MESH_POINT:
1361 return true;
1362 default:
1363 return false;
1364 }
1365}
1366
1367static void ath9k_reclaim_beacon(struct ath_softc *sc,
1368 struct ieee80211_vif *vif)
f078f209 1369{
1ed32e4f 1370 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1371
4801416c
BG
1372 /* Disable SWBA interrupt */
1373 sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
1374 ath9k_ps_wakeup(sc);
1375 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1376 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1377 tasklet_kill(&sc->bcon_tasklet);
1378 ath9k_ps_restore(sc);
1379
1380 ath_beacon_return(sc, avp);
1381 sc->sc_flags &= ~SC_OP_BEACONS;
1382
1383 if (sc->nbcnvifs > 0) {
1384 /* Re-enable beaconing */
1385 sc->sc_ah->imask |= ATH9K_INT_SWBA;
1386 ath9k_ps_wakeup(sc);
1387 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1388 ath9k_ps_restore(sc);
1389 }
1390}
1391
1392static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1393{
1394 struct ath9k_vif_iter_data *iter_data = data;
1395 int i;
1396
1397 if (iter_data->hw_macaddr)
1398 for (i = 0; i < ETH_ALEN; i++)
1399 iter_data->mask[i] &=
1400 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1401
1ed32e4f 1402 switch (vif->type) {
4801416c
BG
1403 case NL80211_IFTYPE_AP:
1404 iter_data->naps++;
f078f209 1405 break;
4801416c
BG
1406 case NL80211_IFTYPE_STATION:
1407 iter_data->nstations++;
e51f3eff 1408 break;
05c914fe 1409 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1410 iter_data->nadhocs++;
1411 break;
9cb5412b 1412 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1413 iter_data->nmeshes++;
1414 break;
1415 case NL80211_IFTYPE_WDS:
1416 iter_data->nwds++;
f078f209
LR
1417 break;
1418 default:
4801416c
BG
1419 iter_data->nothers++;
1420 break;
f078f209 1421 }
4801416c 1422}
f078f209 1423
4801416c
BG
1424/* Called with sc->mutex held. */
1425void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1426 struct ieee80211_vif *vif,
1427 struct ath9k_vif_iter_data *iter_data)
1428{
1429 struct ath_wiphy *aphy = hw->priv;
1430 struct ath_softc *sc = aphy->sc;
1431 struct ath_hw *ah = sc->sc_ah;
1432 struct ath_common *common = ath9k_hw_common(ah);
1433 int i;
8feceb67 1434
4801416c
BG
1435 /*
1436 * Use the hardware MAC address as reference, the hardware uses it
1437 * together with the BSSID mask when matching addresses.
1438 */
1439 memset(iter_data, 0, sizeof(*iter_data));
1440 iter_data->hw_macaddr = common->macaddr;
1441 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1442
4801416c
BG
1443 if (vif)
1444 ath9k_vif_iter(iter_data, vif->addr, vif);
1445
1446 /* Get list of all active MAC addresses */
1447 spin_lock_bh(&sc->wiphy_lock);
1448 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1449 iter_data);
1450 for (i = 0; i < sc->num_sec_wiphy; i++) {
1451 if (sc->sec_wiphy[i] == NULL)
1452 continue;
1453 ieee80211_iterate_active_interfaces_atomic(
1454 sc->sec_wiphy[i]->hw, ath9k_vif_iter, iter_data);
1455 }
1456 spin_unlock_bh(&sc->wiphy_lock);
1457}
8ca21f01 1458
4801416c
BG
1459/* Called with sc->mutex held. */
1460static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1461 struct ieee80211_vif *vif)
1462{
1463 struct ath_wiphy *aphy = hw->priv;
1464 struct ath_softc *sc = aphy->sc;
1465 struct ath_hw *ah = sc->sc_ah;
1466 struct ath_common *common = ath9k_hw_common(ah);
1467 struct ath9k_vif_iter_data iter_data;
8ca21f01 1468
4801416c 1469 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1470
4801416c
BG
1471 /* Set BSSID mask. */
1472 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1473 ath_hw_setbssidmask(common);
1474
1475 /* Set op-mode & TSF */
1476 if (iter_data.naps > 0) {
3069168c 1477 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1478 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1479 ah->opmode = NL80211_IFTYPE_AP;
1480 } else {
1481 ath9k_hw_set_tsfadjust(ah, 0);
1482 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1483
4801416c
BG
1484 if (iter_data.nwds + iter_data.nmeshes)
1485 ah->opmode = NL80211_IFTYPE_AP;
1486 else if (iter_data.nadhocs)
1487 ah->opmode = NL80211_IFTYPE_ADHOC;
1488 else
1489 ah->opmode = NL80211_IFTYPE_STATION;
1490 }
5640b08e 1491
4e30ffa2
VN
1492 /*
1493 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1494 */
4801416c 1495 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1496 if (ah->config.enable_ani)
1497 ah->imask |= ATH9K_INT_MIB;
3069168c 1498 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1499 } else {
1500 ah->imask &= ~ATH9K_INT_MIB;
1501 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1502 }
1503
3069168c 1504 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1505
4801416c
BG
1506 /* Set up ANI */
1507 if ((iter_data.naps + iter_data.nadhocs) > 0) {
6c3118e2 1508 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1509 ath_start_ani(common);
4801416c
BG
1510 } else {
1511 sc->sc_flags &= ~SC_OP_ANI_RUN;
1512 del_timer_sync(&common->ani.timer);
6c3118e2 1513 }
4801416c 1514}
6f255425 1515
4801416c
BG
1516/* Called with sc->mutex held, vif counts set up properly. */
1517static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1518 struct ieee80211_vif *vif)
1519{
1520 struct ath_wiphy *aphy = hw->priv;
1521 struct ath_softc *sc = aphy->sc;
1522
1523 ath9k_calculate_summary_state(hw, vif);
1524
1525 if (ath9k_uses_beacons(vif->type)) {
1526 int error;
1527 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1528 /* This may fail because upper levels do not have beacons
1529 * properly configured yet. That's OK, we assume it
1530 * will be properly configured and then we will be notified
1531 * in the info_changed method and set up beacons properly
1532 * there.
1533 */
1534 error = ath_beacon_alloc(aphy, vif);
1535 if (error)
1536 ath9k_reclaim_beacon(sc, vif);
1537 else
1538 ath_beacon_config(sc, vif);
1539 }
f078f209
LR
1540}
1541
4801416c
BG
1542
1543static int ath9k_add_interface(struct ieee80211_hw *hw,
1544 struct ieee80211_vif *vif)
6b3b991d 1545{
4801416c
BG
1546 struct ath_wiphy *aphy = hw->priv;
1547 struct ath_softc *sc = aphy->sc;
1548 struct ath_hw *ah = sc->sc_ah;
1549 struct ath_common *common = ath9k_hw_common(ah);
6b3b991d 1550 struct ath_vif *avp = (void *)vif->drv_priv;
4801416c 1551 int ret = 0;
6b3b991d 1552
4801416c 1553 mutex_lock(&sc->mutex);
6b3b991d 1554
4801416c
BG
1555 switch (vif->type) {
1556 case NL80211_IFTYPE_STATION:
1557 case NL80211_IFTYPE_WDS:
1558 case NL80211_IFTYPE_ADHOC:
1559 case NL80211_IFTYPE_AP:
1560 case NL80211_IFTYPE_MESH_POINT:
1561 break;
1562 default:
1563 ath_err(common, "Interface type %d not yet supported\n",
1564 vif->type);
1565 ret = -EOPNOTSUPP;
1566 goto out;
1567 }
6b3b991d 1568
4801416c
BG
1569 if (ath9k_uses_beacons(vif->type)) {
1570 if (sc->nbcnvifs >= ATH_BCBUF) {
1571 ath_err(common, "Not enough beacon buffers when adding"
1572 " new interface of type: %i\n",
1573 vif->type);
1574 ret = -ENOBUFS;
1575 goto out;
1576 }
1577 }
1578
1579 if ((vif->type == NL80211_IFTYPE_ADHOC) &&
1580 sc->nvifs > 0) {
1581 ath_err(common, "Cannot create ADHOC interface when other"
1582 " interfaces already exist.\n");
1583 ret = -EINVAL;
1584 goto out;
6b3b991d 1585 }
4801416c
BG
1586
1587 ath_dbg(common, ATH_DBG_CONFIG,
1588 "Attach a VIF of type: %d\n", vif->type);
1589
1590 /* Set the VIF opmode */
1591 avp->av_opmode = vif->type;
1592 avp->av_bslot = -1;
1593
1594 sc->nvifs++;
1595
1596 ath9k_do_vif_add_setup(hw, vif);
1597out:
1598 mutex_unlock(&sc->mutex);
1599 return ret;
6b3b991d
RM
1600}
1601
1602static int ath9k_change_interface(struct ieee80211_hw *hw,
1603 struct ieee80211_vif *vif,
1604 enum nl80211_iftype new_type,
1605 bool p2p)
1606{
1607 struct ath_wiphy *aphy = hw->priv;
1608 struct ath_softc *sc = aphy->sc;
1609 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1610 int ret = 0;
6b3b991d
RM
1611
1612 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1613 mutex_lock(&sc->mutex);
1614
4801416c
BG
1615 /* See if new interface type is valid. */
1616 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1617 (sc->nvifs > 1)) {
1618 ath_err(common, "When using ADHOC, it must be the only"
1619 " interface.\n");
1620 ret = -EINVAL;
1621 goto out;
1622 }
1623
1624 if (ath9k_uses_beacons(new_type) &&
1625 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1626 if (sc->nbcnvifs >= ATH_BCBUF) {
1627 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1628 ret = -ENOBUFS;
1629 goto out;
6b3b991d 1630 }
6b3b991d 1631 }
4801416c
BG
1632
1633 /* Clean up old vif stuff */
1634 if (ath9k_uses_beacons(vif->type))
1635 ath9k_reclaim_beacon(sc, vif);
1636
1637 /* Add new settings */
6b3b991d
RM
1638 vif->type = new_type;
1639 vif->p2p = p2p;
1640
4801416c 1641 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1642out:
6b3b991d 1643 mutex_unlock(&sc->mutex);
6dab55bf 1644 return ret;
6b3b991d
RM
1645}
1646
8feceb67 1647static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1648 struct ieee80211_vif *vif)
f078f209 1649{
bce048d7
JM
1650 struct ath_wiphy *aphy = hw->priv;
1651 struct ath_softc *sc = aphy->sc;
c46917bb 1652 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1653
226afe68 1654 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1655
141b38b6
S
1656 mutex_lock(&sc->mutex);
1657
4801416c 1658 sc->nvifs--;
580f0b8a 1659
8feceb67 1660 /* Reclaim beacon resources */
4801416c 1661 if (ath9k_uses_beacons(vif->type))
6b3b991d 1662 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1663
4801416c 1664 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1665
1666 mutex_unlock(&sc->mutex);
f078f209
LR
1667}
1668
fbab7390 1669static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1670{
3069168c
PR
1671 struct ath_hw *ah = sc->sc_ah;
1672
3f7c5c10 1673 sc->ps_enabled = true;
3069168c
PR
1674 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1675 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1676 ah->imask |= ATH9K_INT_TIM_TIMER;
1677 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1678 }
fdf76622 1679 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1680 }
3f7c5c10
SB
1681}
1682
845d708e
SB
1683static void ath9k_disable_ps(struct ath_softc *sc)
1684{
1685 struct ath_hw *ah = sc->sc_ah;
1686
1687 sc->ps_enabled = false;
1688 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1689 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1690 ath9k_hw_setrxabort(ah, 0);
1691 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1692 PS_WAIT_FOR_CAB |
1693 PS_WAIT_FOR_PSPOLL_DATA |
1694 PS_WAIT_FOR_TX_ACK);
1695 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1696 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1697 ath9k_hw_set_interrupts(ah, ah->imask);
1698 }
1699 }
1700
1701}
1702
e8975581 1703static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1704{
bce048d7
JM
1705 struct ath_wiphy *aphy = hw->priv;
1706 struct ath_softc *sc = aphy->sc;
3430098a
FF
1707 struct ath_hw *ah = sc->sc_ah;
1708 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1709 struct ieee80211_conf *conf = &hw->conf;
194b7c13 1710 bool disable_radio;
f078f209 1711
aa33de09 1712 mutex_lock(&sc->mutex);
141b38b6 1713
194b7c13
LR
1714 /*
1715 * Leave this as the first check because we need to turn on the
1716 * radio if it was disabled before prior to processing the rest
1717 * of the changes. Likewise we must only disable the radio towards
1718 * the end.
1719 */
64839170 1720 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR
1721 bool enable_radio;
1722 bool all_wiphys_idle;
1723 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR
1724
1725 spin_lock_bh(&sc->wiphy_lock);
1726 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR
1727 ath9k_set_wiphy_idle(aphy, idle);
1728
11446011 1729 enable_radio = (!idle && all_wiphys_idle);
194b7c13
LR
1730
1731 /*
1732 * After we unlock here its possible another wiphy
1733 * can be re-renabled so to account for that we will
1734 * only disable the radio toward the end of this routine
1735 * if by then all wiphys are still idle.
1736 */
64839170
LR
1737 spin_unlock_bh(&sc->wiphy_lock);
1738
194b7c13 1739 if (enable_radio) {
1dbfd9d4 1740 sc->ps_idle = false;
68a89116 1741 ath_radio_enable(sc, hw);
226afe68
JP
1742 ath_dbg(common, ATH_DBG_CONFIG,
1743 "not-idle: enabling radio\n");
64839170
LR
1744 }
1745 }
1746
e7824a50
LR
1747 /*
1748 * We just prepare to enable PS. We have to wait until our AP has
1749 * ACK'd our null data frame to disable RX otherwise we'll ignore
1750 * those ACKs and end up retransmitting the same null data frames.
1751 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1752 */
3cbb5dd7 1753 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1754 unsigned long flags;
1755 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1756 if (conf->flags & IEEE80211_CONF_PS)
1757 ath9k_enable_ps(sc);
845d708e
SB
1758 else
1759 ath9k_disable_ps(sc);
8ab2cd09 1760 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1761 }
1762
199afd9d
S
1763 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1764 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1765 ath_dbg(common, ATH_DBG_CONFIG,
1766 "Monitor mode is enabled\n");
5f841b41
RM
1767 sc->sc_ah->is_monitoring = true;
1768 } else {
226afe68
JP
1769 ath_dbg(common, ATH_DBG_CONFIG,
1770 "Monitor mode is disabled\n");
5f841b41 1771 sc->sc_ah->is_monitoring = false;
199afd9d
S
1772 }
1773 }
1774
4797938c 1775 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1776 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1777 int pos = curchan->hw_value;
3430098a
FF
1778 int old_pos = -1;
1779 unsigned long flags;
1780
1781 if (ah->curchan)
1782 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1783
0e2dedf9
JM
1784 aphy->chan_idx = pos;
1785 aphy->chan_is_ht = conf_is_ht(conf);
5ee08656
FF
1786 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1787 sc->sc_flags |= SC_OP_OFFCHANNEL;
1788 else
1789 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1790
8089cc47
JM
1791 if (aphy->state == ATH_WIPHY_SCAN ||
1792 aphy->state == ATH_WIPHY_ACTIVE)
1793 ath9k_wiphy_pause_all_forced(sc, aphy);
1794 else {
1795 /*
1796 * Do not change operational channel based on a paused
1797 * wiphy changes.
1798 */
1799 goto skip_chan_change;
1800 }
0e2dedf9 1801
226afe68
JP
1802 ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1803 curchan->center_freq);
f078f209 1804
5f8e077c 1805 /* XXX: remove me eventualy */
0e2dedf9 1806 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1807
3430098a
FF
1808 /* update survey stats for the old channel before switching */
1809 spin_lock_irqsave(&common->cc_lock, flags);
1810 ath_update_survey_stats(sc);
1811 spin_unlock_irqrestore(&common->cc_lock, flags);
1812
1813 /*
1814 * If the operating channel changes, change the survey in-use flags
1815 * along with it.
1816 * Reset the survey data for the new channel, unless we're switching
1817 * back to the operating channel from an off-channel operation.
1818 */
1819 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1820 sc->cur_survey != &sc->survey[pos]) {
1821
1822 if (sc->cur_survey)
1823 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1824
1825 sc->cur_survey = &sc->survey[pos];
1826
1827 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1828 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1829 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1830 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1831 }
1832
0e2dedf9 1833 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1834 ath_err(common, "Unable to set channel\n");
aa33de09 1835 mutex_unlock(&sc->mutex);
e11602b7
S
1836 return -EINVAL;
1837 }
3430098a
FF
1838
1839 /*
1840 * The most recent snapshot of channel->noisefloor for the old
1841 * channel is only available after the hardware reset. Copy it to
1842 * the survey stats now.
1843 */
1844 if (old_pos >= 0)
1845 ath_update_survey_nf(sc, old_pos);
094d05dc 1846 }
f078f209 1847
8089cc47 1848skip_chan_change:
c9f6a656 1849 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1850 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR
1851 ath_update_txpow(sc);
1852 }
f078f209 1853
194b7c13
LR
1854 spin_lock_bh(&sc->wiphy_lock);
1855 disable_radio = ath9k_all_wiphys_idle(sc);
1856 spin_unlock_bh(&sc->wiphy_lock);
1857
64839170 1858 if (disable_radio) {
226afe68 1859 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1860 sc->ps_idle = true;
68a89116 1861 ath_radio_disable(sc, hw);
64839170
LR
1862 }
1863
aa33de09 1864 mutex_unlock(&sc->mutex);
141b38b6 1865
f078f209
LR
1866 return 0;
1867}
1868
8feceb67
VT
1869#define SUPPORTED_FILTERS \
1870 (FIF_PROMISC_IN_BSS | \
1871 FIF_ALLMULTI | \
1872 FIF_CONTROL | \
af6a3fc7 1873 FIF_PSPOLL | \
8feceb67
VT
1874 FIF_OTHER_BSS | \
1875 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1876 FIF_PROBE_REQ | \
8feceb67 1877 FIF_FCSFAIL)
c83be688 1878
8feceb67
VT
1879/* FIXME: sc->sc_full_reset ? */
1880static void ath9k_configure_filter(struct ieee80211_hw *hw,
1881 unsigned int changed_flags,
1882 unsigned int *total_flags,
3ac64bee 1883 u64 multicast)
8feceb67 1884{
bce048d7
JM
1885 struct ath_wiphy *aphy = hw->priv;
1886 struct ath_softc *sc = aphy->sc;
8feceb67 1887 u32 rfilt;
f078f209 1888
8feceb67
VT
1889 changed_flags &= SUPPORTED_FILTERS;
1890 *total_flags &= SUPPORTED_FILTERS;
f078f209 1891
b77f483f 1892 sc->rx.rxfilter = *total_flags;
aa68aeaa 1893 ath9k_ps_wakeup(sc);
8feceb67
VT
1894 rfilt = ath_calcrxfilter(sc);
1895 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1896 ath9k_ps_restore(sc);
f078f209 1897
226afe68
JP
1898 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1899 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1900}
f078f209 1901
4ca77860
JB
1902static int ath9k_sta_add(struct ieee80211_hw *hw,
1903 struct ieee80211_vif *vif,
1904 struct ieee80211_sta *sta)
8feceb67 1905{
bce048d7
JM
1906 struct ath_wiphy *aphy = hw->priv;
1907 struct ath_softc *sc = aphy->sc;
f078f209 1908
4ca77860
JB
1909 ath_node_attach(sc, sta);
1910
1911 return 0;
1912}
1913
1914static int ath9k_sta_remove(struct ieee80211_hw *hw,
1915 struct ieee80211_vif *vif,
1916 struct ieee80211_sta *sta)
1917{
1918 struct ath_wiphy *aphy = hw->priv;
1919 struct ath_softc *sc = aphy->sc;
1920
1921 ath_node_detach(sc, sta);
1922
1923 return 0;
f078f209
LR
1924}
1925
141b38b6 1926static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1927 const struct ieee80211_tx_queue_params *params)
f078f209 1928{
bce048d7
JM
1929 struct ath_wiphy *aphy = hw->priv;
1930 struct ath_softc *sc = aphy->sc;
c46917bb 1931 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1932 struct ath_txq *txq;
8feceb67 1933 struct ath9k_tx_queue_info qi;
066dae93 1934 int ret = 0;
f078f209 1935
8feceb67
VT
1936 if (queue >= WME_NUM_AC)
1937 return 0;
f078f209 1938
066dae93
FF
1939 txq = sc->tx.txq_map[queue];
1940
141b38b6
S
1941 mutex_lock(&sc->mutex);
1942
1ffb0610
S
1943 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1944
8feceb67
VT
1945 qi.tqi_aifs = params->aifs;
1946 qi.tqi_cwmin = params->cw_min;
1947 qi.tqi_cwmax = params->cw_max;
1948 qi.tqi_burstTime = params->txop;
f078f209 1949
226afe68
JP
1950 ath_dbg(common, ATH_DBG_CONFIG,
1951 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1952 queue, txq->axq_qnum, params->aifs, params->cw_min,
1953 params->cw_max, params->txop);
f078f209 1954
066dae93 1955 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1956 if (ret)
3800276a 1957 ath_err(common, "TXQ Update failed\n");
f078f209 1958
94db2936 1959 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1960 if (queue == WME_AC_BE && !ret)
94db2936
VN
1961 ath_beaconq_config(sc);
1962
141b38b6
S
1963 mutex_unlock(&sc->mutex);
1964
8feceb67
VT
1965 return ret;
1966}
f078f209 1967
8feceb67
VT
1968static int ath9k_set_key(struct ieee80211_hw *hw,
1969 enum set_key_cmd cmd,
dc822b5d
JB
1970 struct ieee80211_vif *vif,
1971 struct ieee80211_sta *sta,
8feceb67
VT
1972 struct ieee80211_key_conf *key)
1973{
bce048d7
JM
1974 struct ath_wiphy *aphy = hw->priv;
1975 struct ath_softc *sc = aphy->sc;
c46917bb 1976 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1977 int ret = 0;
f078f209 1978
3e6109c5 1979 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1980 return -ENOSPC;
1981
141b38b6 1982 mutex_lock(&sc->mutex);
3cbb5dd7 1983 ath9k_ps_wakeup(sc);
226afe68 1984 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1985
8feceb67
VT
1986 switch (cmd) {
1987 case SET_KEY:
040e539e 1988 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1989 if (ret >= 0) {
1990 key->hw_key_idx = ret;
8feceb67
VT
1991 /* push IV and Michael MIC generation to stack */
1992 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1993 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1994 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1995 if (sc->sc_ah->sw_mgmt_crypto &&
1996 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1997 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1998 ret = 0;
8feceb67
VT
1999 }
2000 break;
2001 case DISABLE_KEY:
040e539e 2002 ath_key_delete(common, key);
8feceb67
VT
2003 break;
2004 default:
2005 ret = -EINVAL;
2006 }
f078f209 2007
3cbb5dd7 2008 ath9k_ps_restore(sc);
141b38b6
S
2009 mutex_unlock(&sc->mutex);
2010
8feceb67
VT
2011 return ret;
2012}
f078f209 2013
8feceb67
VT
2014static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2015 struct ieee80211_vif *vif,
2016 struct ieee80211_bss_conf *bss_conf,
2017 u32 changed)
2018{
bce048d7
JM
2019 struct ath_wiphy *aphy = hw->priv;
2020 struct ath_softc *sc = aphy->sc;
2d0ddec5 2021 struct ath_hw *ah = sc->sc_ah;
1510718d 2022 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2023 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2024 int slottime;
c6089ccc 2025 int error;
f078f209 2026
141b38b6
S
2027 mutex_lock(&sc->mutex);
2028
c6089ccc
S
2029 if (changed & BSS_CHANGED_BSSID) {
2030 /* Set BSSID */
2031 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2032 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 2033 common->curaid = 0;
f2b2143e 2034 ath9k_hw_write_associd(ah);
2d0ddec5 2035
c6089ccc
S
2036 /* Set aggregation protection mode parameters */
2037 sc->config.ath_aggr_prot = 0;
2d0ddec5 2038
226afe68
JP
2039 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2040 common->curbssid, common->curaid);
2d0ddec5 2041
c6089ccc
S
2042 /* need to reconfigure the beacon */
2043 sc->sc_flags &= ~SC_OP_BEACONS ;
2044 }
2d0ddec5 2045
c6089ccc
S
2046 /* Enable transmission of beacons (AP, IBSS, MESH) */
2047 if ((changed & BSS_CHANGED_BEACON) ||
2048 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2049 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2050 error = ath_beacon_alloc(aphy, vif);
2051 if (!error)
2052 ath_beacon_config(sc, vif);
0005baf4
FF
2053 }
2054
2055 if (changed & BSS_CHANGED_ERP_SLOT) {
2056 if (bss_conf->use_short_slot)
2057 slottime = 9;
2058 else
2059 slottime = 20;
2060 if (vif->type == NL80211_IFTYPE_AP) {
2061 /*
2062 * Defer update, so that connected stations can adjust
2063 * their settings at the same time.
2064 * See beacon.c for more details
2065 */
2066 sc->beacon.slottime = slottime;
2067 sc->beacon.updateslot = UPDATE;
2068 } else {
2069 ah->slottime = slottime;
2070 ath9k_hw_init_global_settings(ah);
2071 }
2d0ddec5
JB
2072 }
2073
c6089ccc
S
2074 /* Disable transmission of beacons */
2075 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
2076 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 2077
c6089ccc
S
2078 if (changed & BSS_CHANGED_BEACON_INT) {
2079 sc->beacon_interval = bss_conf->beacon_int;
2080 /*
2081 * In case of AP mode, the HW TSF has to be reset
2082 * when the beacon interval changes.
2083 */
2084 if (vif->type == NL80211_IFTYPE_AP) {
2085 sc->sc_flags |= SC_OP_TSF_RESET;
2086 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB
2087 error = ath_beacon_alloc(aphy, vif);
2088 if (!error)
2089 ath_beacon_config(sc, vif);
c6089ccc
S
2090 } else {
2091 ath_beacon_config(sc, vif);
2d0ddec5
JB
2092 }
2093 }
2094
8feceb67 2095 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
2096 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2097 bss_conf->use_short_preamble);
8feceb67
VT
2098 if (bss_conf->use_short_preamble)
2099 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2100 else
2101 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2102 }
f078f209 2103
8feceb67 2104 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
2105 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2106 bss_conf->use_cts_prot);
8feceb67
VT
2107 if (bss_conf->use_cts_prot &&
2108 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2109 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2110 else
2111 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2112 }
f078f209 2113
8feceb67 2114 if (changed & BSS_CHANGED_ASSOC) {
226afe68 2115 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2116 bss_conf->assoc);
9fa23e17 2117 ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
8feceb67 2118 }
141b38b6
S
2119
2120 mutex_unlock(&sc->mutex);
8feceb67 2121}
f078f209 2122
8feceb67
VT
2123static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2124{
2125 u64 tsf;
bce048d7
JM
2126 struct ath_wiphy *aphy = hw->priv;
2127 struct ath_softc *sc = aphy->sc;
f078f209 2128
141b38b6 2129 mutex_lock(&sc->mutex);
9abbfb27 2130 ath9k_ps_wakeup(sc);
141b38b6 2131 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2132 ath9k_ps_restore(sc);
141b38b6 2133 mutex_unlock(&sc->mutex);
f078f209 2134
8feceb67
VT
2135 return tsf;
2136}
f078f209 2137
3b5d665b
AF
2138static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2139{
bce048d7
JM
2140 struct ath_wiphy *aphy = hw->priv;
2141 struct ath_softc *sc = aphy->sc;
3b5d665b 2142
141b38b6 2143 mutex_lock(&sc->mutex);
9abbfb27 2144 ath9k_ps_wakeup(sc);
141b38b6 2145 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2146 ath9k_ps_restore(sc);
141b38b6 2147 mutex_unlock(&sc->mutex);
3b5d665b
AF
2148}
2149
8feceb67
VT
2150static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2151{
bce048d7
JM
2152 struct ath_wiphy *aphy = hw->priv;
2153 struct ath_softc *sc = aphy->sc;
c83be688 2154
141b38b6 2155 mutex_lock(&sc->mutex);
21526d57
LR
2156
2157 ath9k_ps_wakeup(sc);
141b38b6 2158 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2159 ath9k_ps_restore(sc);
2160
141b38b6 2161 mutex_unlock(&sc->mutex);
8feceb67 2162}
f078f209 2163
8feceb67 2164static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2165 struct ieee80211_vif *vif,
141b38b6
S
2166 enum ieee80211_ampdu_mlme_action action,
2167 struct ieee80211_sta *sta,
0b01f030 2168 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2169{
bce048d7
JM
2170 struct ath_wiphy *aphy = hw->priv;
2171 struct ath_softc *sc = aphy->sc;
8feceb67 2172 int ret = 0;
f078f209 2173
85ad181e
JB
2174 local_bh_disable();
2175
8feceb67
VT
2176 switch (action) {
2177 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2178 if (!(sc->sc_flags & SC_OP_RXAGGR))
2179 ret = -ENOTSUPP;
8feceb67
VT
2180 break;
2181 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2182 break;
2183 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2184 if (!(sc->sc_flags & SC_OP_TXAGGR))
2185 return -EOPNOTSUPP;
2186
8b685ba9 2187 ath9k_ps_wakeup(sc);
231c3a1f
FF
2188 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2189 if (!ret)
2190 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2191 ath9k_ps_restore(sc);
8feceb67
VT
2192 break;
2193 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2194 ath9k_ps_wakeup(sc);
f83da965 2195 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2196 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2197 ath9k_ps_restore(sc);
8feceb67 2198 break;
b1720231 2199 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2200 ath9k_ps_wakeup(sc);
8469cdef 2201 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2202 ath9k_ps_restore(sc);
8469cdef 2203 break;
8feceb67 2204 default:
3800276a 2205 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2206 }
2207
85ad181e
JB
2208 local_bh_enable();
2209
8feceb67 2210 return ret;
f078f209
LR
2211}
2212
62dad5b0
BP
2213static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2214 struct survey_info *survey)
2215{
2216 struct ath_wiphy *aphy = hw->priv;
2217 struct ath_softc *sc = aphy->sc;
3430098a 2218 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2219 struct ieee80211_supported_band *sband;
3430098a
FF
2220 struct ieee80211_channel *chan;
2221 unsigned long flags;
2222 int pos;
2223
2224 spin_lock_irqsave(&common->cc_lock, flags);
2225 if (idx == 0)
2226 ath_update_survey_stats(sc);
39162dbe
FF
2227
2228 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2229 if (sband && idx >= sband->n_channels) {
2230 idx -= sband->n_channels;
2231 sband = NULL;
2232 }
62dad5b0 2233
39162dbe
FF
2234 if (!sband)
2235 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2236
3430098a
FF
2237 if (!sband || idx >= sband->n_channels) {
2238 spin_unlock_irqrestore(&common->cc_lock, flags);
2239 return -ENOENT;
4f1a5a4b 2240 }
62dad5b0 2241
3430098a
FF
2242 chan = &sband->channels[idx];
2243 pos = chan->hw_value;
2244 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2245 survey->channel = chan;
2246 spin_unlock_irqrestore(&common->cc_lock, flags);
2247
62dad5b0
BP
2248 return 0;
2249}
2250
0c98de65
S
2251static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2252{
bce048d7
JM
2253 struct ath_wiphy *aphy = hw->priv;
2254 struct ath_softc *sc = aphy->sc;
0c98de65 2255
3d832611 2256 mutex_lock(&sc->mutex);
8089cc47 2257 if (ath9k_wiphy_scanning(sc)) {
8089cc47 2258 /*
30888338
LR
2259 * There is a race here in mac80211 but fixing it requires
2260 * we revisit how we handle the scan complete callback.
2261 * After mac80211 fixes we will not have configured hardware
2262 * to the home channel nor would we have configured the RX
2263 * filter yet.
8089cc47 2264 */
3d832611 2265 mutex_unlock(&sc->mutex);
8089cc47
JM
2266 return;
2267 }
2268
2269 aphy->state = ATH_WIPHY_SCAN;
2270 ath9k_wiphy_pause_all_forced(sc, aphy);
3d832611 2271 mutex_unlock(&sc->mutex);
0c98de65
S
2272}
2273
30888338
LR
2274/*
2275 * XXX: this requires a revisit after the driver
2276 * scan_complete gets moved to another place/removed in mac80211.
2277 */
0c98de65
S
2278static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2279{
bce048d7
JM
2280 struct ath_wiphy *aphy = hw->priv;
2281 struct ath_softc *sc = aphy->sc;
0c98de65 2282
3d832611 2283 mutex_lock(&sc->mutex);
8089cc47 2284 aphy->state = ATH_WIPHY_ACTIVE;
3d832611 2285 mutex_unlock(&sc->mutex);
0c98de65
S
2286}
2287
e239d859
FF
2288static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2289{
2290 struct ath_wiphy *aphy = hw->priv;
2291 struct ath_softc *sc = aphy->sc;
2292 struct ath_hw *ah = sc->sc_ah;
2293
2294 mutex_lock(&sc->mutex);
2295 ah->coverage_class = coverage_class;
2296 ath9k_hw_init_global_settings(ah);
2297 mutex_unlock(&sc->mutex);
2298}
2299
6baff7f9 2300struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2301 .tx = ath9k_tx,
2302 .start = ath9k_start,
2303 .stop = ath9k_stop,
2304 .add_interface = ath9k_add_interface,
6b3b991d 2305 .change_interface = ath9k_change_interface,
8feceb67
VT
2306 .remove_interface = ath9k_remove_interface,
2307 .config = ath9k_config,
8feceb67 2308 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2309 .sta_add = ath9k_sta_add,
2310 .sta_remove = ath9k_sta_remove,
8feceb67 2311 .conf_tx = ath9k_conf_tx,
8feceb67 2312 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2313 .set_key = ath9k_set_key,
8feceb67 2314 .get_tsf = ath9k_get_tsf,
3b5d665b 2315 .set_tsf = ath9k_set_tsf,
8feceb67 2316 .reset_tsf = ath9k_reset_tsf,
4233df6b 2317 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2318 .get_survey = ath9k_get_survey,
0c98de65
S
2319 .sw_scan_start = ath9k_sw_scan_start,
2320 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2321 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2322 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2323};