Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ce111bad LR |
21 | static void ath_cache_conf_rate(struct ath_softc *sc, |
22 | struct ieee80211_conf *conf) | |
ff37e337 | 23 | { |
030bb495 LR |
24 | switch (conf->channel->band) { |
25 | case IEEE80211_BAND_2GHZ: | |
26 | if (conf_is_ht20(conf)) | |
545750d3 | 27 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; |
030bb495 | 28 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 29 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; |
030bb495 | 30 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 31 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; |
96742256 | 32 | else |
545750d3 | 33 | sc->cur_rate_mode = ATH9K_MODE_11G; |
030bb495 LR |
34 | break; |
35 | case IEEE80211_BAND_5GHZ: | |
36 | if (conf_is_ht20(conf)) | |
545750d3 | 37 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; |
030bb495 | 38 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 39 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; |
030bb495 | 40 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 41 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; |
030bb495 | 42 | else |
545750d3 | 43 | sc->cur_rate_mode = ATH9K_MODE_11A; |
030bb495 LR |
44 | break; |
45 | default: | |
ce111bad | 46 | BUG_ON(1); |
030bb495 LR |
47 | break; |
48 | } | |
ff37e337 S |
49 | } |
50 | ||
51 | static void ath_update_txpow(struct ath_softc *sc) | |
52 | { | |
cbe61d8a | 53 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 54 | |
17d7904d S |
55 | if (sc->curtxpow != sc->config.txpowlimit) { |
56 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 | 57 | /* read back in case value is clamped */ |
9cc3271f | 58 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
ff37e337 S |
59 | } |
60 | } | |
61 | ||
62 | static u8 parse_mpdudensity(u8 mpdudensity) | |
63 | { | |
64 | /* | |
65 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
66 | * 0 for no restriction | |
67 | * 1 for 1/4 us | |
68 | * 2 for 1/2 us | |
69 | * 3 for 1 us | |
70 | * 4 for 2 us | |
71 | * 5 for 4 us | |
72 | * 6 for 8 us | |
73 | * 7 for 16 us | |
74 | */ | |
75 | switch (mpdudensity) { | |
76 | case 0: | |
77 | return 0; | |
78 | case 1: | |
79 | case 2: | |
80 | case 3: | |
81 | /* Our lower layer calculations limit our precision to | |
82 | 1 microsecond */ | |
83 | return 1; | |
84 | case 4: | |
85 | return 2; | |
86 | case 5: | |
87 | return 4; | |
88 | case 6: | |
89 | return 8; | |
90 | case 7: | |
91 | return 16; | |
92 | default: | |
93 | return 0; | |
94 | } | |
95 | } | |
96 | ||
82880a7c VT |
97 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
98 | struct ieee80211_hw *hw) | |
99 | { | |
100 | struct ieee80211_channel *curchan = hw->conf.channel; | |
101 | struct ath9k_channel *channel; | |
102 | u8 chan_idx; | |
103 | ||
104 | chan_idx = curchan->hw_value; | |
105 | channel = &sc->sc_ah->channels[chan_idx]; | |
106 | ath9k_update_ichannel(sc, hw, channel); | |
107 | return channel; | |
108 | } | |
109 | ||
55624204 | 110 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
111 | { |
112 | unsigned long flags; | |
113 | bool ret; | |
114 | ||
9ecdef4b LR |
115 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
116 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
117 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
118 | |
119 | return ret; | |
120 | } | |
121 | ||
a91d75ae LR |
122 | void ath9k_ps_wakeup(struct ath_softc *sc) |
123 | { | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
127 | if (++sc->ps_usecount != 1) | |
128 | goto unlock; | |
129 | ||
9ecdef4b | 130 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
131 | |
132 | unlock: | |
133 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
134 | } | |
135 | ||
136 | void ath9k_ps_restore(struct ath_softc *sc) | |
137 | { | |
138 | unsigned long flags; | |
139 | ||
140 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
141 | if (--sc->ps_usecount != 0) | |
142 | goto unlock; | |
143 | ||
1dbfd9d4 VN |
144 | if (sc->ps_idle) |
145 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
146 | else if (sc->ps_enabled && | |
147 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
148 | PS_WAIT_FOR_CAB | |
149 | PS_WAIT_FOR_PSPOLL_DATA | | |
150 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 151 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
152 | |
153 | unlock: | |
154 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
155 | } | |
156 | ||
ff37e337 S |
157 | /* |
158 | * Set/change channels. If the channel is really being changed, it's done | |
159 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
160 | * DMA, then restart stuff. | |
161 | */ | |
0e2dedf9 JM |
162 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
163 | struct ath9k_channel *hchan) | |
ff37e337 | 164 | { |
cbe61d8a | 165 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 166 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 167 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 168 | bool fastcc = true, stopped; |
ae8d2858 LR |
169 | struct ieee80211_channel *channel = hw->conf.channel; |
170 | int r; | |
ff37e337 S |
171 | |
172 | if (sc->sc_flags & SC_OP_INVALID) | |
173 | return -EIO; | |
174 | ||
3cbb5dd7 VN |
175 | ath9k_ps_wakeup(sc); |
176 | ||
c0d7c7af LR |
177 | /* |
178 | * This is only performed if the channel settings have | |
179 | * actually changed. | |
180 | * | |
181 | * To switch channels clear any pending DMA operations; | |
182 | * wait long enough for the RX fifo to drain, reset the | |
183 | * hardware at the new frequency, and then re-enable | |
184 | * the relevant bits of the h/w. | |
185 | */ | |
186 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 187 | ath_drain_all_txq(sc, false); |
c0d7c7af | 188 | stopped = ath_stoprecv(sc); |
ff37e337 | 189 | |
c0d7c7af LR |
190 | /* XXX: do not flush receive queue here. We don't want |
191 | * to flush data frames already in queue because of | |
192 | * changing channel. */ | |
ff37e337 | 193 | |
c0d7c7af LR |
194 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
195 | fastcc = false; | |
196 | ||
c46917bb | 197 | ath_print(common, ATH_DBG_CONFIG, |
25c56eec | 198 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n", |
c46917bb | 199 | sc->sc_ah->curchan->channel, |
25c56eec | 200 | channel->center_freq, conf_is_ht40(conf)); |
ff37e337 | 201 | |
c0d7c7af LR |
202 | spin_lock_bh(&sc->sc_resetlock); |
203 | ||
204 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
205 | if (r) { | |
c46917bb | 206 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 207 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
208 | "reset status %d\n", |
209 | channel->center_freq, r); | |
c0d7c7af | 210 | spin_unlock_bh(&sc->sc_resetlock); |
3989279c | 211 | goto ps_restore; |
ff37e337 | 212 | } |
c0d7c7af LR |
213 | spin_unlock_bh(&sc->sc_resetlock); |
214 | ||
c0d7c7af LR |
215 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
216 | ||
217 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
218 | ath_print(common, ATH_DBG_FATAL, |
219 | "Unable to restart recv logic\n"); | |
3989279c GJ |
220 | r = -EIO; |
221 | goto ps_restore; | |
c0d7c7af LR |
222 | } |
223 | ||
224 | ath_cache_conf_rate(sc, &hw->conf); | |
225 | ath_update_txpow(sc); | |
3069168c | 226 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c GJ |
227 | |
228 | ps_restore: | |
3cbb5dd7 | 229 | ath9k_ps_restore(sc); |
3989279c | 230 | return r; |
ff37e337 S |
231 | } |
232 | ||
9f42c2b6 FF |
233 | static void ath_paprd_activate(struct ath_softc *sc) |
234 | { | |
235 | struct ath_hw *ah = sc->sc_ah; | |
236 | int chain; | |
237 | ||
238 | if (!ah->curchan->paprd_done) | |
239 | return; | |
240 | ||
241 | ath9k_ps_wakeup(sc); | |
ddfef792 | 242 | ar9003_paprd_enable(ah, false); |
9f42c2b6 FF |
243 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
244 | if (!(ah->caps.tx_chainmask & BIT(chain))) | |
245 | continue; | |
246 | ||
247 | ar9003_paprd_populate_single_table(ah, ah->curchan, chain); | |
248 | } | |
249 | ||
250 | ar9003_paprd_enable(ah, true); | |
251 | ath9k_ps_restore(sc); | |
252 | } | |
253 | ||
254 | void ath_paprd_calibrate(struct work_struct *work) | |
255 | { | |
256 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
257 | struct ieee80211_hw *hw = sc->hw; | |
258 | struct ath_hw *ah = sc->sc_ah; | |
259 | struct ieee80211_hdr *hdr; | |
260 | struct sk_buff *skb = NULL; | |
261 | struct ieee80211_tx_info *tx_info; | |
262 | int band = hw->conf.channel->band; | |
263 | struct ieee80211_supported_band *sband = &sc->sbands[band]; | |
264 | struct ath_tx_control txctl; | |
265 | int qnum, ftype; | |
266 | int chain_ok = 0; | |
267 | int chain; | |
268 | int len = 1800; | |
269 | int time_left; | |
270 | int i; | |
271 | ||
9f42c2b6 FF |
272 | skb = alloc_skb(len, GFP_KERNEL); |
273 | if (!skb) | |
274 | return; | |
275 | ||
276 | tx_info = IEEE80211_SKB_CB(skb); | |
277 | ||
278 | skb_put(skb, len); | |
279 | memset(skb->data, 0, len); | |
280 | hdr = (struct ieee80211_hdr *)skb->data; | |
281 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
282 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 283 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
284 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
285 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
286 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
287 | ||
288 | memset(&txctl, 0, sizeof(txctl)); | |
289 | qnum = sc->tx.hwq_map[WME_AC_BE]; | |
290 | txctl.txq = &sc->tx.txq[qnum]; | |
291 | ||
47399f1a | 292 | ath9k_ps_wakeup(sc); |
9f42c2b6 FF |
293 | ar9003_paprd_init_table(ah); |
294 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | |
295 | if (!(ah->caps.tx_chainmask & BIT(chain))) | |
296 | continue; | |
297 | ||
298 | chain_ok = 0; | |
299 | memset(tx_info, 0, sizeof(*tx_info)); | |
300 | tx_info->band = band; | |
301 | ||
302 | for (i = 0; i < 4; i++) { | |
303 | tx_info->control.rates[i].idx = sband->n_bitrates - 1; | |
304 | tx_info->control.rates[i].count = 6; | |
305 | } | |
306 | ||
307 | init_completion(&sc->paprd_complete); | |
308 | ar9003_paprd_setup_gain_table(ah, chain); | |
309 | txctl.paprd = BIT(chain); | |
310 | if (ath_tx_start(hw, skb, &txctl) != 0) | |
311 | break; | |
312 | ||
313 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
ca369eb4 | 314 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); |
9f42c2b6 FF |
315 | if (!time_left) { |
316 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | |
317 | "Timeout waiting for paprd training on " | |
318 | "TX chain %d\n", | |
319 | chain); | |
ca369eb4 | 320 | goto fail_paprd; |
9f42c2b6 FF |
321 | } |
322 | ||
323 | if (!ar9003_paprd_is_done(ah)) | |
324 | break; | |
325 | ||
326 | if (ar9003_paprd_create_curve(ah, ah->curchan, chain) != 0) | |
327 | break; | |
328 | ||
329 | chain_ok = 1; | |
330 | } | |
331 | kfree_skb(skb); | |
332 | ||
333 | if (chain_ok) { | |
334 | ah->curchan->paprd_done = true; | |
335 | ath_paprd_activate(sc); | |
336 | } | |
337 | ||
ca369eb4 | 338 | fail_paprd: |
9f42c2b6 FF |
339 | ath9k_ps_restore(sc); |
340 | } | |
341 | ||
ff37e337 S |
342 | /* |
343 | * This routine performs the periodic noise floor calibration function | |
344 | * that is used to adjust and optimize the chip performance. This | |
345 | * takes environmental changes (location, temperature) into account. | |
346 | * When the task is complete, it reschedules itself depending on the | |
347 | * appropriate interval that was calculated. | |
348 | */ | |
55624204 | 349 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 350 | { |
20977d3e S |
351 | struct ath_softc *sc = (struct ath_softc *)data; |
352 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 353 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
354 | bool longcal = false; |
355 | bool shortcal = false; | |
356 | bool aniflag = false; | |
357 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 358 | u32 cal_interval, short_cal_interval; |
ff37e337 | 359 | |
20977d3e S |
360 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
361 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 362 | |
1ffc1c61 JM |
363 | /* Only calibrate if awake */ |
364 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
365 | goto set_timer; | |
366 | ||
367 | ath9k_ps_wakeup(sc); | |
368 | ||
ff37e337 | 369 | /* Long calibration runs independently of short calibration. */ |
3d536acf | 370 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 371 | longcal = true; |
c46917bb | 372 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 373 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
374 | } |
375 | ||
17d7904d | 376 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
377 | if (!common->ani.caldone) { |
378 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 379 | shortcal = true; |
c46917bb LR |
380 | ath_print(common, ATH_DBG_ANI, |
381 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
382 | common->ani.shortcal_timer = timestamp; |
383 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
384 | } |
385 | } else { | |
3d536acf | 386 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 387 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
388 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
389 | if (common->ani.caldone) | |
390 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
391 | } |
392 | } | |
393 | ||
394 | /* Verify whether we must check ANI */ | |
e36b27af LR |
395 | if ((timestamp - common->ani.checkani_timer) >= |
396 | ah->config.ani_poll_interval) { | |
ff37e337 | 397 | aniflag = true; |
3d536acf | 398 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
399 | } |
400 | ||
401 | /* Skip all processing if there's nothing to do. */ | |
402 | if (longcal || shortcal || aniflag) { | |
403 | /* Call ANI routine if necessary */ | |
404 | if (aniflag) | |
22e66a4c | 405 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
406 | |
407 | /* Perform calibration if necessary */ | |
408 | if (longcal || shortcal) { | |
3d536acf | 409 | common->ani.caldone = |
43c27613 LR |
410 | ath9k_hw_calibrate(ah, |
411 | ah->curchan, | |
412 | common->rx_chainmask, | |
413 | longcal); | |
379f0440 S |
414 | |
415 | if (longcal) | |
3d536acf | 416 | common->ani.noise_floor = ath9k_hw_getchan_noise(ah, |
379f0440 S |
417 | ah->curchan); |
418 | ||
c46917bb LR |
419 | ath_print(common, ATH_DBG_ANI, |
420 | " calibrate chan %u/%x nf: %d\n", | |
421 | ah->curchan->channel, | |
422 | ah->curchan->channelFlags, | |
3d536acf | 423 | common->ani.noise_floor); |
ff37e337 S |
424 | } |
425 | } | |
426 | ||
1ffc1c61 JM |
427 | ath9k_ps_restore(sc); |
428 | ||
20977d3e | 429 | set_timer: |
ff37e337 S |
430 | /* |
431 | * Set timer interval based on previous results. | |
432 | * The interval must be the shortest necessary to satisfy ANI, | |
433 | * short calibration and long calibration. | |
434 | */ | |
aac9207e | 435 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 436 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
437 | cal_interval = min(cal_interval, |
438 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 439 | if (!common->ani.caldone) |
20977d3e | 440 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 441 | |
3d536acf | 442 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
9f42c2b6 FF |
443 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && |
444 | !(sc->sc_flags & SC_OP_SCANNING)) { | |
445 | if (!sc->sc_ah->curchan->paprd_done) | |
446 | ieee80211_queue_work(sc->hw, &sc->paprd_work); | |
447 | else | |
448 | ath_paprd_activate(sc); | |
449 | } | |
ff37e337 S |
450 | } |
451 | ||
3d536acf | 452 | static void ath_start_ani(struct ath_common *common) |
415f738e | 453 | { |
e36b27af | 454 | struct ath_hw *ah = common->ah; |
415f738e | 455 | unsigned long timestamp = jiffies_to_msecs(jiffies); |
6c3118e2 VT |
456 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
457 | ||
458 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
459 | return; | |
415f738e | 460 | |
3d536acf LR |
461 | common->ani.longcal_timer = timestamp; |
462 | common->ani.shortcal_timer = timestamp; | |
463 | common->ani.checkani_timer = timestamp; | |
415f738e | 464 | |
3d536acf | 465 | mod_timer(&common->ani.timer, |
e36b27af LR |
466 | jiffies + |
467 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
415f738e S |
468 | } |
469 | ||
ff37e337 S |
470 | /* |
471 | * Update tx/rx chainmask. For legacy association, | |
472 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
473 | * the chainmask configuration, for bt coexistence, use |
474 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 475 | */ |
0e2dedf9 | 476 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 477 | { |
af03abec | 478 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 479 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 480 | |
3d832611 | 481 | if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || |
766ec4a9 | 482 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
483 | common->tx_chainmask = ah->caps.tx_chainmask; |
484 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 485 | } else { |
43c27613 LR |
486 | common->tx_chainmask = 1; |
487 | common->rx_chainmask = 1; | |
ff37e337 S |
488 | } |
489 | ||
43c27613 | 490 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 491 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
492 | common->tx_chainmask, |
493 | common->rx_chainmask); | |
ff37e337 S |
494 | } |
495 | ||
496 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
497 | { | |
498 | struct ath_node *an; | |
499 | ||
500 | an = (struct ath_node *)sta->drv_priv; | |
501 | ||
87792efc | 502 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 503 | ath_tx_node_init(sc, an); |
9e98ac65 | 504 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
505 | sta->ht_cap.ampdu_factor); |
506 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 507 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 508 | } |
ff37e337 S |
509 | } |
510 | ||
511 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
512 | { | |
513 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
514 | ||
515 | if (sc->sc_flags & SC_OP_TXAGGR) | |
516 | ath_tx_node_cleanup(sc, an); | |
517 | } | |
518 | ||
347809fc FF |
519 | void ath_hw_check(struct work_struct *work) |
520 | { | |
521 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
522 | int i; | |
523 | ||
524 | ath9k_ps_wakeup(sc); | |
525 | ||
526 | for (i = 0; i < 3; i++) { | |
527 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
528 | goto out; | |
529 | ||
530 | msleep(1); | |
531 | } | |
532 | ath_reset(sc, false); | |
533 | ||
534 | out: | |
535 | ath9k_ps_restore(sc); | |
536 | } | |
537 | ||
55624204 | 538 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
539 | { |
540 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 541 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 542 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 543 | |
17d7904d | 544 | u32 status = sc->intrstatus; |
b5c80475 | 545 | u32 rxmask; |
ff37e337 | 546 | |
153e080d VT |
547 | ath9k_ps_wakeup(sc); |
548 | ||
347809fc | 549 | if (status & ATH9K_INT_FATAL) { |
ff37e337 | 550 | ath_reset(sc, false); |
153e080d | 551 | ath9k_ps_restore(sc); |
ff37e337 | 552 | return; |
063d8be3 | 553 | } |
ff37e337 | 554 | |
347809fc FF |
555 | if (!ath9k_hw_check_alive(ah)) |
556 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); | |
557 | ||
b5c80475 FF |
558 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
559 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
560 | ATH9K_INT_RXORN); | |
561 | else | |
562 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
563 | ||
564 | if (status & rxmask) { | |
063d8be3 | 565 | spin_lock_bh(&sc->rx.rxflushlock); |
b5c80475 FF |
566 | |
567 | /* Check for high priority Rx first */ | |
568 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
569 | (status & ATH9K_INT_RXHP)) | |
570 | ath_rx_tasklet(sc, 0, true); | |
571 | ||
572 | ath_rx_tasklet(sc, 0, false); | |
063d8be3 | 573 | spin_unlock_bh(&sc->rx.rxflushlock); |
ff37e337 S |
574 | } |
575 | ||
e5003249 VT |
576 | if (status & ATH9K_INT_TX) { |
577 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
578 | ath_tx_edma_tasklet(sc); | |
579 | else | |
580 | ath_tx_tasklet(sc); | |
581 | } | |
063d8be3 | 582 | |
96148326 | 583 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
584 | /* |
585 | * TSF sync does not look correct; remain awake to sync with | |
586 | * the next Beacon. | |
587 | */ | |
c46917bb LR |
588 | ath_print(common, ATH_DBG_PS, |
589 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 590 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
591 | } |
592 | ||
766ec4a9 | 593 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
594 | if (status & ATH9K_INT_GENTIMER) |
595 | ath_gen_timer_isr(sc->sc_ah); | |
596 | ||
ff37e337 | 597 | /* re-enable hardware interrupt */ |
3069168c | 598 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 599 | ath9k_ps_restore(sc); |
ff37e337 S |
600 | } |
601 | ||
6baff7f9 | 602 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 603 | { |
063d8be3 S |
604 | #define SCHED_INTR ( \ |
605 | ATH9K_INT_FATAL | \ | |
606 | ATH9K_INT_RXORN | \ | |
607 | ATH9K_INT_RXEOL | \ | |
608 | ATH9K_INT_RX | \ | |
b5c80475 FF |
609 | ATH9K_INT_RXLP | \ |
610 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
611 | ATH9K_INT_TX | \ |
612 | ATH9K_INT_BMISS | \ | |
613 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
614 | ATH9K_INT_TSFOOR | \ |
615 | ATH9K_INT_GENTIMER) | |
063d8be3 | 616 | |
ff37e337 | 617 | struct ath_softc *sc = dev; |
cbe61d8a | 618 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
619 | enum ath9k_int status; |
620 | bool sched = false; | |
621 | ||
063d8be3 S |
622 | /* |
623 | * The hardware is not ready/present, don't | |
624 | * touch anything. Note this can happen early | |
625 | * on if the IRQ is shared. | |
626 | */ | |
627 | if (sc->sc_flags & SC_OP_INVALID) | |
628 | return IRQ_NONE; | |
ff37e337 | 629 | |
063d8be3 S |
630 | |
631 | /* shared irq, not for us */ | |
632 | ||
153e080d | 633 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 634 | return IRQ_NONE; |
063d8be3 S |
635 | |
636 | /* | |
637 | * Figure out the reason(s) for the interrupt. Note | |
638 | * that the hal returns a pseudo-ISR that may include | |
639 | * bits we haven't explicitly enabled so we mask the | |
640 | * value to insure we only process bits we requested. | |
641 | */ | |
642 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 643 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 644 | |
063d8be3 S |
645 | /* |
646 | * If there are no status bits set, then this interrupt was not | |
647 | * for me (should have been caught above). | |
648 | */ | |
153e080d | 649 | if (!status) |
063d8be3 | 650 | return IRQ_NONE; |
ff37e337 | 651 | |
063d8be3 S |
652 | /* Cache the status */ |
653 | sc->intrstatus = status; | |
654 | ||
655 | if (status & SCHED_INTR) | |
656 | sched = true; | |
657 | ||
658 | /* | |
659 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
660 | * chip immediately. | |
661 | */ | |
b5c80475 FF |
662 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
663 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
664 | goto chip_reset; |
665 | ||
08578b8f LR |
666 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
667 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
668 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
669 | goto chip_reset; | |
670 | } | |
671 | ||
063d8be3 S |
672 | if (status & ATH9K_INT_SWBA) |
673 | tasklet_schedule(&sc->bcon_tasklet); | |
674 | ||
675 | if (status & ATH9K_INT_TXURN) | |
676 | ath9k_hw_updatetxtriglevel(ah, true); | |
677 | ||
b5c80475 FF |
678 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
679 | if (status & ATH9K_INT_RXEOL) { | |
680 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
681 | ath9k_hw_set_interrupts(ah, ah->imask); | |
682 | } | |
683 | } | |
684 | ||
063d8be3 | 685 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 686 | /* |
063d8be3 S |
687 | * Disable interrupts until we service the MIB |
688 | * interrupt; otherwise it will continue to | |
689 | * fire. | |
ff37e337 | 690 | */ |
063d8be3 S |
691 | ath9k_hw_set_interrupts(ah, 0); |
692 | /* | |
693 | * Let the hal handle the event. We assume | |
694 | * it will clear whatever condition caused | |
695 | * the interrupt. | |
696 | */ | |
22e66a4c | 697 | ath9k_hw_procmibevent(ah); |
3069168c | 698 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 699 | } |
ff37e337 | 700 | |
153e080d VT |
701 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
702 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
703 | /* Clear RxAbort bit so that we can |
704 | * receive frames */ | |
9ecdef4b | 705 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 706 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 707 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 708 | } |
063d8be3 S |
709 | |
710 | chip_reset: | |
ff37e337 | 711 | |
817e11de S |
712 | ath_debug_stat_interrupt(sc, status); |
713 | ||
ff37e337 S |
714 | if (sched) { |
715 | /* turn off every interrupt except SWBA */ | |
3069168c | 716 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
717 | tasklet_schedule(&sc->intr_tq); |
718 | } | |
719 | ||
720 | return IRQ_HANDLED; | |
063d8be3 S |
721 | |
722 | #undef SCHED_INTR | |
ff37e337 S |
723 | } |
724 | ||
f078f209 | 725 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 726 | struct ieee80211_channel *chan, |
094d05dc | 727 | enum nl80211_channel_type channel_type) |
f078f209 LR |
728 | { |
729 | u32 chanmode = 0; | |
f078f209 LR |
730 | |
731 | switch (chan->band) { | |
732 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
733 | switch(channel_type) { |
734 | case NL80211_CHAN_NO_HT: | |
735 | case NL80211_CHAN_HT20: | |
f078f209 | 736 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
737 | break; |
738 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 739 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
740 | break; |
741 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 742 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
743 | break; |
744 | } | |
f078f209 LR |
745 | break; |
746 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
747 | switch(channel_type) { |
748 | case NL80211_CHAN_NO_HT: | |
749 | case NL80211_CHAN_HT20: | |
f078f209 | 750 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
751 | break; |
752 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 753 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
754 | break; |
755 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 756 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
757 | break; |
758 | } | |
f078f209 LR |
759 | break; |
760 | default: | |
761 | break; | |
762 | } | |
763 | ||
764 | return chanmode; | |
765 | } | |
766 | ||
8feceb67 | 767 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 768 | struct ieee80211_vif *vif, |
8feceb67 | 769 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 770 | { |
f2b2143e | 771 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 772 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 773 | |
8feceb67 | 774 | if (bss_conf->assoc) { |
c46917bb LR |
775 | ath_print(common, ATH_DBG_CONFIG, |
776 | "Bss Info ASSOC %d, bssid: %pM\n", | |
777 | bss_conf->aid, common->curbssid); | |
f078f209 | 778 | |
8feceb67 | 779 | /* New association, store aid */ |
1510718d | 780 | common->curaid = bss_conf->aid; |
f2b2143e | 781 | ath9k_hw_write_associd(ah); |
2664f201 SB |
782 | |
783 | /* | |
784 | * Request a re-configuration of Beacon related timers | |
785 | * on the receipt of the first Beacon frame (i.e., | |
786 | * after time sync with the AP). | |
787 | */ | |
1b04b930 | 788 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 789 | |
8feceb67 | 790 | /* Configure the beacon */ |
2c3db3d5 | 791 | ath_beacon_config(sc, vif); |
f078f209 | 792 | |
8feceb67 | 793 | /* Reset rssi stats */ |
22e66a4c | 794 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 795 | |
6c3118e2 | 796 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 797 | ath_start_ani(common); |
8feceb67 | 798 | } else { |
c46917bb | 799 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 800 | common->curaid = 0; |
f38faa31 | 801 | /* Stop ANI */ |
6c3118e2 | 802 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 803 | del_timer_sync(&common->ani.timer); |
f078f209 | 804 | } |
8feceb67 | 805 | } |
f078f209 | 806 | |
68a89116 | 807 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 808 | { |
cbe61d8a | 809 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 810 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 811 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 812 | int r; |
500c064d | 813 | |
3cbb5dd7 | 814 | ath9k_ps_wakeup(sc); |
93b1b37f | 815 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 816 | |
159cd468 VT |
817 | if (!ah->curchan) |
818 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
819 | ||
d2f5b3a6 | 820 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 821 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 822 | if (r) { |
c46917bb | 823 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 824 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
825 | "reset status %d\n", |
826 | channel->center_freq, r); | |
500c064d VT |
827 | } |
828 | spin_unlock_bh(&sc->sc_resetlock); | |
829 | ||
830 | ath_update_txpow(sc); | |
831 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
832 | ath_print(common, ATH_DBG_FATAL, |
833 | "Unable to restart recv logic\n"); | |
500c064d VT |
834 | return; |
835 | } | |
836 | ||
837 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 838 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
839 | |
840 | /* Re-Enable interrupts */ | |
3069168c | 841 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
842 | |
843 | /* Enable LED */ | |
08fc5c1b | 844 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 845 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 846 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 847 | |
68a89116 | 848 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 849 | ath9k_ps_restore(sc); |
500c064d VT |
850 | } |
851 | ||
68a89116 | 852 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 853 | { |
cbe61d8a | 854 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 855 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 856 | int r; |
500c064d | 857 | |
3cbb5dd7 | 858 | ath9k_ps_wakeup(sc); |
68a89116 | 859 | ieee80211_stop_queues(hw); |
500c064d | 860 | |
982723df VN |
861 | /* |
862 | * Keep the LED on when the radio is disabled | |
863 | * during idle unassociated state. | |
864 | */ | |
865 | if (!sc->ps_idle) { | |
866 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
867 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
868 | } | |
500c064d VT |
869 | |
870 | /* Disable interrupts */ | |
871 | ath9k_hw_set_interrupts(ah, 0); | |
872 | ||
043a0405 | 873 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
874 | ath_stoprecv(sc); /* turn off frame recv */ |
875 | ath_flushrecv(sc); /* flush recv queue */ | |
876 | ||
159cd468 | 877 | if (!ah->curchan) |
68a89116 | 878 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 879 | |
500c064d | 880 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 881 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 882 | if (r) { |
c46917bb | 883 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 884 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
885 | "reset status %d\n", |
886 | channel->center_freq, r); | |
500c064d VT |
887 | } |
888 | spin_unlock_bh(&sc->sc_resetlock); | |
889 | ||
890 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 891 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 892 | ath9k_ps_restore(sc); |
9ecdef4b | 893 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
894 | } |
895 | ||
ff37e337 S |
896 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
897 | { | |
cbe61d8a | 898 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 899 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 900 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 901 | int r; |
ff37e337 | 902 | |
2ab81d4a S |
903 | /* Stop ANI */ |
904 | del_timer_sync(&common->ani.timer); | |
905 | ||
cc9c378a S |
906 | ieee80211_stop_queues(hw); |
907 | ||
ff37e337 | 908 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 909 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
910 | ath_stoprecv(sc); |
911 | ath_flushrecv(sc); | |
912 | ||
913 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 914 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 915 | if (r) |
c46917bb LR |
916 | ath_print(common, ATH_DBG_FATAL, |
917 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
918 | spin_unlock_bh(&sc->sc_resetlock); |
919 | ||
920 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
921 | ath_print(common, ATH_DBG_FATAL, |
922 | "Unable to start recv logic\n"); | |
ff37e337 S |
923 | |
924 | /* | |
925 | * We may be doing a reset in response to a request | |
926 | * that changes the channel so update any state that | |
927 | * might change as a result. | |
928 | */ | |
ce111bad | 929 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
930 | |
931 | ath_update_txpow(sc); | |
932 | ||
933 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 934 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 935 | |
3069168c | 936 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
937 | |
938 | if (retry_tx) { | |
939 | int i; | |
940 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
941 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
942 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
943 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
944 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
945 | } |
946 | } | |
947 | } | |
948 | ||
cc9c378a S |
949 | ieee80211_wake_queues(hw); |
950 | ||
2ab81d4a S |
951 | /* Start ANI */ |
952 | ath_start_ani(common); | |
953 | ||
ae8d2858 | 954 | return r; |
ff37e337 S |
955 | } |
956 | ||
ebe297c3 | 957 | static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
ff37e337 S |
958 | { |
959 | int qnum; | |
960 | ||
961 | switch (queue) { | |
962 | case 0: | |
1d2231e2 | 963 | qnum = sc->tx.hwq_map[WME_AC_VO]; |
ff37e337 S |
964 | break; |
965 | case 1: | |
1d2231e2 | 966 | qnum = sc->tx.hwq_map[WME_AC_VI]; |
ff37e337 S |
967 | break; |
968 | case 2: | |
1d2231e2 | 969 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
970 | break; |
971 | case 3: | |
1d2231e2 | 972 | qnum = sc->tx.hwq_map[WME_AC_BK]; |
ff37e337 S |
973 | break; |
974 | default: | |
1d2231e2 | 975 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
976 | break; |
977 | } | |
978 | ||
979 | return qnum; | |
980 | } | |
981 | ||
982 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
983 | { | |
984 | int qnum; | |
985 | ||
986 | switch (queue) { | |
1d2231e2 | 987 | case WME_AC_VO: |
ff37e337 S |
988 | qnum = 0; |
989 | break; | |
1d2231e2 | 990 | case WME_AC_VI: |
ff37e337 S |
991 | qnum = 1; |
992 | break; | |
1d2231e2 | 993 | case WME_AC_BE: |
ff37e337 S |
994 | qnum = 2; |
995 | break; | |
1d2231e2 | 996 | case WME_AC_BK: |
ff37e337 S |
997 | qnum = 3; |
998 | break; | |
999 | default: | |
1000 | qnum = -1; | |
1001 | break; | |
1002 | } | |
1003 | ||
1004 | return qnum; | |
1005 | } | |
1006 | ||
5f8e077c LR |
1007 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1008 | * this redundant data */ | |
0e2dedf9 JM |
1009 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1010 | struct ath9k_channel *ichan) | |
5f8e077c | 1011 | { |
5f8e077c LR |
1012 | struct ieee80211_channel *chan = hw->conf.channel; |
1013 | struct ieee80211_conf *conf = &hw->conf; | |
1014 | ||
1015 | ichan->channel = chan->center_freq; | |
1016 | ichan->chan = chan; | |
1017 | ||
1018 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1019 | ichan->chanmode = CHANNEL_G; | |
8813262e | 1020 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
1021 | } else { |
1022 | ichan->chanmode = CHANNEL_A; | |
1023 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1024 | } | |
1025 | ||
25c56eec | 1026 | if (conf_is_ht(conf)) |
5f8e077c LR |
1027 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
1028 | conf->channel_type); | |
5f8e077c LR |
1029 | } |
1030 | ||
ff37e337 S |
1031 | /**********************/ |
1032 | /* mac80211 callbacks */ | |
1033 | /**********************/ | |
1034 | ||
8feceb67 | 1035 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1036 | { |
bce048d7 JM |
1037 | struct ath_wiphy *aphy = hw->priv; |
1038 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1039 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1040 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1041 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1042 | struct ath9k_channel *init_channel; |
82880a7c | 1043 | int r; |
f078f209 | 1044 | |
c46917bb LR |
1045 | ath_print(common, ATH_DBG_CONFIG, |
1046 | "Starting driver with initial channel: %d MHz\n", | |
1047 | curchan->center_freq); | |
f078f209 | 1048 | |
141b38b6 S |
1049 | mutex_lock(&sc->mutex); |
1050 | ||
9580a222 JM |
1051 | if (ath9k_wiphy_started(sc)) { |
1052 | if (sc->chan_idx == curchan->hw_value) { | |
1053 | /* | |
1054 | * Already on the operational channel, the new wiphy | |
1055 | * can be marked active. | |
1056 | */ | |
1057 | aphy->state = ATH_WIPHY_ACTIVE; | |
1058 | ieee80211_wake_queues(hw); | |
1059 | } else { | |
1060 | /* | |
1061 | * Another wiphy is on another channel, start the new | |
1062 | * wiphy in paused state. | |
1063 | */ | |
1064 | aphy->state = ATH_WIPHY_PAUSED; | |
1065 | ieee80211_stop_queues(hw); | |
1066 | } | |
1067 | mutex_unlock(&sc->mutex); | |
1068 | return 0; | |
1069 | } | |
1070 | aphy->state = ATH_WIPHY_ACTIVE; | |
1071 | ||
8feceb67 | 1072 | /* setup initial channel */ |
f078f209 | 1073 | |
82880a7c | 1074 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1075 | |
82880a7c | 1076 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1077 | |
1078 | /* Reset SERDES registers */ | |
af03abec | 1079 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1080 | |
1081 | /* | |
1082 | * The basic interface to setting the hardware in a good | |
1083 | * state is ``reset''. On return the hardware is known to | |
1084 | * be powered up and with interrupts disabled. This must | |
1085 | * be followed by initialization of the appropriate bits | |
1086 | * and then setup of the interrupt mask. | |
1087 | */ | |
1088 | spin_lock_bh(&sc->sc_resetlock); | |
af03abec | 1089 | r = ath9k_hw_reset(ah, init_channel, false); |
ae8d2858 | 1090 | if (r) { |
c46917bb LR |
1091 | ath_print(common, ATH_DBG_FATAL, |
1092 | "Unable to reset hardware; reset status %d " | |
1093 | "(freq %u MHz)\n", r, | |
1094 | curchan->center_freq); | |
ff37e337 | 1095 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 1096 | goto mutex_unlock; |
ff37e337 S |
1097 | } |
1098 | spin_unlock_bh(&sc->sc_resetlock); | |
1099 | ||
1100 | /* | |
1101 | * This is needed only to setup initial state | |
1102 | * but it's best done after a reset. | |
1103 | */ | |
1104 | ath_update_txpow(sc); | |
8feceb67 | 1105 | |
ff37e337 S |
1106 | /* |
1107 | * Setup the hardware after reset: | |
1108 | * The receive engine is set going. | |
1109 | * Frame transmit is handled entirely | |
1110 | * in the frame output path; there's nothing to do | |
1111 | * here except setup the interrupt mask. | |
1112 | */ | |
1113 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
1114 | ath_print(common, ATH_DBG_FATAL, |
1115 | "Unable to start recv logic\n"); | |
141b38b6 S |
1116 | r = -EIO; |
1117 | goto mutex_unlock; | |
f078f209 | 1118 | } |
8feceb67 | 1119 | |
ff37e337 | 1120 | /* Setup our intr mask. */ |
b5c80475 FF |
1121 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1122 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1123 | ATH9K_INT_GLOBAL; | |
1124 | ||
1125 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1126 | ah->imask |= ATH9K_INT_RXHP | |
1127 | ATH9K_INT_RXLP | | |
1128 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1129 | else |
1130 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1131 | |
af03abec | 1132 | if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
3069168c | 1133 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1134 | |
af03abec | 1135 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1136 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1137 | |
ce111bad | 1138 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1139 | |
1140 | sc->sc_flags &= ~SC_OP_INVALID; | |
1141 | ||
1142 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1143 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1144 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1145 | |
bce048d7 | 1146 | ieee80211_wake_queues(hw); |
ff37e337 | 1147 | |
42935eca | 1148 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1149 | |
766ec4a9 LR |
1150 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1151 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1152 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1153 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1154 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1155 | |
5bb12791 LR |
1156 | if (common->bus_ops->bt_coex_prep) |
1157 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1158 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1159 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1160 | } |
1161 | ||
141b38b6 S |
1162 | mutex_unlock: |
1163 | mutex_unlock(&sc->mutex); | |
1164 | ||
ae8d2858 | 1165 | return r; |
f078f209 LR |
1166 | } |
1167 | ||
8feceb67 VT |
1168 | static int ath9k_tx(struct ieee80211_hw *hw, |
1169 | struct sk_buff *skb) | |
f078f209 | 1170 | { |
528f0c6b | 1171 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1172 | struct ath_wiphy *aphy = hw->priv; |
1173 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1174 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1175 | struct ath_tx_control txctl; |
1bc14880 BP |
1176 | int padpos, padsize; |
1177 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
84642d6b | 1178 | int qnum; |
528f0c6b | 1179 | |
8089cc47 | 1180 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1181 | ath_print(common, ATH_DBG_XMIT, |
1182 | "ath9k: %s: TX in unexpected wiphy state " | |
1183 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1184 | goto exit; |
1185 | } | |
1186 | ||
96148326 | 1187 | if (sc->ps_enabled) { |
dc8c4585 JM |
1188 | /* |
1189 | * mac80211 does not set PM field for normal data frames, so we | |
1190 | * need to update that based on the current PS mode. | |
1191 | */ | |
1192 | if (ieee80211_is_data(hdr->frame_control) && | |
1193 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1194 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1195 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1196 | "while in PS mode\n"); | |
dc8c4585 JM |
1197 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1198 | } | |
1199 | } | |
1200 | ||
9a23f9ca JM |
1201 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1202 | /* | |
1203 | * We are using PS-Poll and mac80211 can request TX while in | |
1204 | * power save mode. Need to wake up hardware for the TX to be | |
1205 | * completed and if needed, also for RX of buffered frames. | |
1206 | */ | |
9a23f9ca | 1207 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1208 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1209 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1210 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
c46917bb LR |
1211 | ath_print(common, ATH_DBG_PS, |
1212 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1213 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1214 | } else { |
c46917bb LR |
1215 | ath_print(common, ATH_DBG_PS, |
1216 | "Wake up to complete TX\n"); | |
1b04b930 | 1217 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1218 | } |
1219 | /* | |
1220 | * The actual restore operation will happen only after | |
1221 | * the sc_flags bit is cleared. We are just dropping | |
1222 | * the ps_usecount here. | |
1223 | */ | |
1224 | ath9k_ps_restore(sc); | |
1225 | } | |
1226 | ||
528f0c6b | 1227 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1228 | |
8feceb67 VT |
1229 | /* |
1230 | * As a temporary workaround, assign seq# here; this will likely need | |
1231 | * to be cleaned up to work better with Beacon transmission and virtual | |
1232 | * BSSes. | |
1233 | */ | |
1234 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1235 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1236 | sc->tx.seq_no += 0x10; |
8feceb67 | 1237 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1238 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1239 | } |
f078f209 | 1240 | |
8feceb67 | 1241 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1242 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1243 | padsize = padpos & 3; | |
1244 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1245 | if (skb_headroom(skb) < padsize) |
1246 | return -1; | |
1247 | skb_push(skb, padsize); | |
1bc14880 | 1248 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1249 | } |
1250 | ||
84642d6b FF |
1251 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1252 | txctl.txq = &sc->tx.txq[qnum]; | |
528f0c6b | 1253 | |
c46917bb | 1254 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1255 | |
c52f33d0 | 1256 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1257 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1258 | goto exit; |
8feceb67 VT |
1259 | } |
1260 | ||
528f0c6b S |
1261 | return 0; |
1262 | exit: | |
1263 | dev_kfree_skb_any(skb); | |
8feceb67 | 1264 | return 0; |
f078f209 LR |
1265 | } |
1266 | ||
8feceb67 | 1267 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1268 | { |
bce048d7 JM |
1269 | struct ath_wiphy *aphy = hw->priv; |
1270 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1271 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1272 | struct ath_common *common = ath9k_hw_common(ah); |
447a42c2 | 1273 | int i; |
f078f209 | 1274 | |
4c483817 S |
1275 | mutex_lock(&sc->mutex); |
1276 | ||
9580a222 JM |
1277 | aphy->state = ATH_WIPHY_INACTIVE; |
1278 | ||
9a75c2ff VN |
1279 | if (led_blink) |
1280 | cancel_delayed_work_sync(&sc->ath_led_blink_work); | |
1281 | ||
c94dbff7 | 1282 | cancel_delayed_work_sync(&sc->tx_complete_work); |
9f42c2b6 | 1283 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1284 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1285 | |
447a42c2 RM |
1286 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1287 | if (sc->sec_wiphy[i]) | |
1288 | break; | |
1289 | } | |
1290 | ||
1291 | if (i == sc->num_sec_wiphy) { | |
c94dbff7 LR |
1292 | cancel_delayed_work_sync(&sc->wiphy_work); |
1293 | cancel_work_sync(&sc->chan_work); | |
1294 | } | |
1295 | ||
9c84b797 | 1296 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1297 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1298 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1299 | return; |
1300 | } | |
8feceb67 | 1301 | |
9580a222 JM |
1302 | if (ath9k_wiphy_started(sc)) { |
1303 | mutex_unlock(&sc->mutex); | |
1304 | return; /* another wiphy still in use */ | |
1305 | } | |
1306 | ||
3867cf6a S |
1307 | /* Ensure HW is awake when we try to shut it down. */ |
1308 | ath9k_ps_wakeup(sc); | |
1309 | ||
766ec4a9 | 1310 | if (ah->btcoex_hw.enabled) { |
af03abec | 1311 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1312 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1313 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1314 | } |
1315 | ||
ff37e337 S |
1316 | /* make sure h/w will not generate any interrupt |
1317 | * before setting the invalid flag. */ | |
af03abec | 1318 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
1319 | |
1320 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1321 | ath_drain_all_txq(sc, false); |
ff37e337 | 1322 | ath_stoprecv(sc); |
af03abec | 1323 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1324 | } else |
b77f483f | 1325 | sc->rx.rxlink = NULL; |
ff37e337 | 1326 | |
ff37e337 | 1327 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1328 | ath9k_hw_disable(ah); |
1329 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1330 | ath9k_ps_restore(sc); |
1331 | ||
1332 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1333 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1334 | |
1335 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1336 | |
141b38b6 S |
1337 | mutex_unlock(&sc->mutex); |
1338 | ||
c46917bb | 1339 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1340 | } |
1341 | ||
8feceb67 | 1342 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1343 | struct ieee80211_vif *vif) |
f078f209 | 1344 | { |
bce048d7 JM |
1345 | struct ath_wiphy *aphy = hw->priv; |
1346 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1347 | struct ath_hw *ah = sc->sc_ah; |
1348 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1349 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1350 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1351 | int ret = 0; |
8feceb67 | 1352 | |
141b38b6 S |
1353 | mutex_lock(&sc->mutex); |
1354 | ||
3069168c | 1355 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
8ca21f01 JM |
1356 | sc->nvifs > 0) { |
1357 | ret = -ENOBUFS; | |
1358 | goto out; | |
1359 | } | |
1360 | ||
1ed32e4f | 1361 | switch (vif->type) { |
05c914fe | 1362 | case NL80211_IFTYPE_STATION: |
d97809db | 1363 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1364 | break; |
05c914fe | 1365 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1366 | case NL80211_IFTYPE_AP: |
9cb5412b | 1367 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1368 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1369 | ret = -ENOBUFS; | |
1370 | goto out; | |
1371 | } | |
1ed32e4f | 1372 | ic_opmode = vif->type; |
f078f209 LR |
1373 | break; |
1374 | default: | |
c46917bb | 1375 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1376 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1377 | ret = -EOPNOTSUPP; |
1378 | goto out; | |
f078f209 LR |
1379 | } |
1380 | ||
c46917bb LR |
1381 | ath_print(common, ATH_DBG_CONFIG, |
1382 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1383 | |
17d7904d | 1384 | /* Set the VIF opmode */ |
5640b08e S |
1385 | avp->av_opmode = ic_opmode; |
1386 | avp->av_bslot = -1; | |
1387 | ||
2c3db3d5 | 1388 | sc->nvifs++; |
8ca21f01 | 1389 | |
3069168c | 1390 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
8ca21f01 JM |
1391 | ath9k_set_bssid_mask(hw); |
1392 | ||
2c3db3d5 JM |
1393 | if (sc->nvifs > 1) |
1394 | goto out; /* skip global settings for secondary vif */ | |
1395 | ||
b238e90e | 1396 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1397 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1398 | sc->sc_flags |= SC_OP_TSF_RESET; |
1399 | } | |
5640b08e | 1400 | |
5640b08e | 1401 | /* Set the device opmode */ |
3069168c | 1402 | ah->opmode = ic_opmode; |
5640b08e | 1403 | |
4e30ffa2 VN |
1404 | /* |
1405 | * Enable MIB interrupts when there are hardware phy counters. | |
1406 | * Note we only do this (at the moment) for station mode. | |
1407 | */ | |
1ed32e4f JB |
1408 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1409 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1410 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1411 | if (ah->config.enable_ani) |
1412 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1413 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1414 | } |
1415 | ||
3069168c | 1416 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1417 | |
1ed32e4f JB |
1418 | if (vif->type == NL80211_IFTYPE_AP || |
1419 | vif->type == NL80211_IFTYPE_ADHOC || | |
6c3118e2 VT |
1420 | vif->type == NL80211_IFTYPE_MONITOR) { |
1421 | sc->sc_flags |= SC_OP_ANI_RUN; | |
3d536acf | 1422 | ath_start_ani(common); |
6c3118e2 | 1423 | } |
6f255425 | 1424 | |
2c3db3d5 | 1425 | out: |
141b38b6 | 1426 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1427 | return ret; |
f078f209 LR |
1428 | } |
1429 | ||
8feceb67 | 1430 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1431 | struct ieee80211_vif *vif) |
f078f209 | 1432 | { |
bce048d7 JM |
1433 | struct ath_wiphy *aphy = hw->priv; |
1434 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1435 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1436 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1437 | int i; |
f078f209 | 1438 | |
c46917bb | 1439 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1440 | |
141b38b6 S |
1441 | mutex_lock(&sc->mutex); |
1442 | ||
6f255425 | 1443 | /* Stop ANI */ |
6c3118e2 | 1444 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 1445 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1446 | |
8feceb67 | 1447 | /* Reclaim beacon resources */ |
9cb5412b PE |
1448 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1449 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1450 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1451 | ath9k_ps_wakeup(sc); |
b77f483f | 1452 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1453 | ath9k_ps_restore(sc); |
580f0b8a | 1454 | } |
f078f209 | 1455 | |
74401773 | 1456 | ath_beacon_return(sc, avp); |
8feceb67 | 1457 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1458 | |
2c3db3d5 | 1459 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1460 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1461 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1462 | "slot\n", __func__); | |
1463 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1464 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1465 | } |
1466 | } | |
1467 | ||
17d7904d | 1468 | sc->nvifs--; |
141b38b6 S |
1469 | |
1470 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1471 | } |
1472 | ||
3f7c5c10 SB |
1473 | void ath9k_enable_ps(struct ath_softc *sc) |
1474 | { | |
3069168c PR |
1475 | struct ath_hw *ah = sc->sc_ah; |
1476 | ||
3f7c5c10 | 1477 | sc->ps_enabled = true; |
3069168c PR |
1478 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1479 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1480 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1481 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1482 | } |
fdf76622 | 1483 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1484 | } |
3f7c5c10 SB |
1485 | } |
1486 | ||
e8975581 | 1487 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1488 | { |
bce048d7 JM |
1489 | struct ath_wiphy *aphy = hw->priv; |
1490 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1491 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8975581 | 1492 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 1493 | struct ath_hw *ah = sc->sc_ah; |
194b7c13 | 1494 | bool disable_radio; |
f078f209 | 1495 | |
aa33de09 | 1496 | mutex_lock(&sc->mutex); |
141b38b6 | 1497 | |
194b7c13 LR |
1498 | /* |
1499 | * Leave this as the first check because we need to turn on the | |
1500 | * radio if it was disabled before prior to processing the rest | |
1501 | * of the changes. Likewise we must only disable the radio towards | |
1502 | * the end. | |
1503 | */ | |
64839170 | 1504 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1505 | bool enable_radio; |
1506 | bool all_wiphys_idle; | |
1507 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1508 | |
1509 | spin_lock_bh(&sc->wiphy_lock); | |
1510 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1511 | ath9k_set_wiphy_idle(aphy, idle); |
1512 | ||
11446011 | 1513 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1514 | |
1515 | /* | |
1516 | * After we unlock here its possible another wiphy | |
1517 | * can be re-renabled so to account for that we will | |
1518 | * only disable the radio toward the end of this routine | |
1519 | * if by then all wiphys are still idle. | |
1520 | */ | |
64839170 LR |
1521 | spin_unlock_bh(&sc->wiphy_lock); |
1522 | ||
194b7c13 | 1523 | if (enable_radio) { |
1dbfd9d4 | 1524 | sc->ps_idle = false; |
68a89116 | 1525 | ath_radio_enable(sc, hw); |
c46917bb LR |
1526 | ath_print(common, ATH_DBG_CONFIG, |
1527 | "not-idle: enabling radio\n"); | |
64839170 LR |
1528 | } |
1529 | } | |
1530 | ||
e7824a50 LR |
1531 | /* |
1532 | * We just prepare to enable PS. We have to wait until our AP has | |
1533 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1534 | * those ACKs and end up retransmitting the same null data frames. | |
1535 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1536 | */ | |
3cbb5dd7 VN |
1537 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
1538 | if (conf->flags & IEEE80211_CONF_PS) { | |
1b04b930 | 1539 | sc->ps_flags |= PS_ENABLED; |
e7824a50 LR |
1540 | /* |
1541 | * At this point we know hardware has received an ACK | |
1542 | * of a previously sent null data frame. | |
1543 | */ | |
1b04b930 S |
1544 | if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { |
1545 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; | |
3f7c5c10 | 1546 | ath9k_enable_ps(sc); |
e7824a50 | 1547 | } |
3cbb5dd7 | 1548 | } else { |
96148326 | 1549 | sc->ps_enabled = false; |
1b04b930 S |
1550 | sc->ps_flags &= ~(PS_ENABLED | |
1551 | PS_NULLFUNC_COMPLETED); | |
9ecdef4b | 1552 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8782b41d VN |
1553 | if (!(ah->caps.hw_caps & |
1554 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
1555 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1b04b930 S |
1556 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | |
1557 | PS_WAIT_FOR_CAB | | |
1558 | PS_WAIT_FOR_PSPOLL_DATA | | |
1559 | PS_WAIT_FOR_TX_ACK); | |
3069168c PR |
1560 | if (ah->imask & ATH9K_INT_TIM_TIMER) { |
1561 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
8782b41d | 1562 | ath9k_hw_set_interrupts(sc->sc_ah, |
3069168c | 1563 | ah->imask); |
8782b41d | 1564 | } |
3cbb5dd7 VN |
1565 | } |
1566 | } | |
1567 | } | |
1568 | ||
199afd9d S |
1569 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1570 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1571 | ath_print(common, ATH_DBG_CONFIG, | |
1572 | "HW opmode set to Monitor mode\n"); | |
1573 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; | |
1574 | } | |
1575 | } | |
1576 | ||
4797938c | 1577 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1578 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1579 | int pos = curchan->hw_value; |
ae5eb026 | 1580 | |
0e2dedf9 JM |
1581 | aphy->chan_idx = pos; |
1582 | aphy->chan_is_ht = conf_is_ht(conf); | |
1583 | ||
8089cc47 JM |
1584 | if (aphy->state == ATH_WIPHY_SCAN || |
1585 | aphy->state == ATH_WIPHY_ACTIVE) | |
1586 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1587 | else { | |
1588 | /* | |
1589 | * Do not change operational channel based on a paused | |
1590 | * wiphy changes. | |
1591 | */ | |
1592 | goto skip_chan_change; | |
1593 | } | |
0e2dedf9 | 1594 | |
c46917bb LR |
1595 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1596 | curchan->center_freq); | |
f078f209 | 1597 | |
5f8e077c | 1598 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1599 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1600 | |
ecf70441 | 1601 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1602 | |
0e2dedf9 | 1603 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1604 | ath_print(common, ATH_DBG_FATAL, |
1605 | "Unable to set channel\n"); | |
aa33de09 | 1606 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1607 | return -EINVAL; |
1608 | } | |
094d05dc | 1609 | } |
f078f209 | 1610 | |
8089cc47 | 1611 | skip_chan_change: |
c9f6a656 | 1612 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1613 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1614 | ath_update_txpow(sc); |
1615 | } | |
f078f209 | 1616 | |
194b7c13 LR |
1617 | spin_lock_bh(&sc->wiphy_lock); |
1618 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1619 | spin_unlock_bh(&sc->wiphy_lock); | |
1620 | ||
64839170 | 1621 | if (disable_radio) { |
c46917bb | 1622 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1623 | sc->ps_idle = true; |
68a89116 | 1624 | ath_radio_disable(sc, hw); |
64839170 LR |
1625 | } |
1626 | ||
aa33de09 | 1627 | mutex_unlock(&sc->mutex); |
141b38b6 | 1628 | |
f078f209 LR |
1629 | return 0; |
1630 | } | |
1631 | ||
8feceb67 VT |
1632 | #define SUPPORTED_FILTERS \ |
1633 | (FIF_PROMISC_IN_BSS | \ | |
1634 | FIF_ALLMULTI | \ | |
1635 | FIF_CONTROL | \ | |
af6a3fc7 | 1636 | FIF_PSPOLL | \ |
8feceb67 VT |
1637 | FIF_OTHER_BSS | \ |
1638 | FIF_BCN_PRBRESP_PROMISC | \ | |
1639 | FIF_FCSFAIL) | |
c83be688 | 1640 | |
8feceb67 VT |
1641 | /* FIXME: sc->sc_full_reset ? */ |
1642 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1643 | unsigned int changed_flags, | |
1644 | unsigned int *total_flags, | |
3ac64bee | 1645 | u64 multicast) |
8feceb67 | 1646 | { |
bce048d7 JM |
1647 | struct ath_wiphy *aphy = hw->priv; |
1648 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1649 | u32 rfilt; |
f078f209 | 1650 | |
8feceb67 VT |
1651 | changed_flags &= SUPPORTED_FILTERS; |
1652 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1653 | |
b77f483f | 1654 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1655 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1656 | rfilt = ath_calcrxfilter(sc); |
1657 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1658 | ath9k_ps_restore(sc); |
f078f209 | 1659 | |
c46917bb LR |
1660 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1661 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1662 | } |
f078f209 | 1663 | |
4ca77860 JB |
1664 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1665 | struct ieee80211_vif *vif, | |
1666 | struct ieee80211_sta *sta) | |
8feceb67 | 1667 | { |
bce048d7 JM |
1668 | struct ath_wiphy *aphy = hw->priv; |
1669 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1670 | |
4ca77860 JB |
1671 | ath_node_attach(sc, sta); |
1672 | ||
1673 | return 0; | |
1674 | } | |
1675 | ||
1676 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1677 | struct ieee80211_vif *vif, | |
1678 | struct ieee80211_sta *sta) | |
1679 | { | |
1680 | struct ath_wiphy *aphy = hw->priv; | |
1681 | struct ath_softc *sc = aphy->sc; | |
1682 | ||
1683 | ath_node_detach(sc, sta); | |
1684 | ||
1685 | return 0; | |
f078f209 LR |
1686 | } |
1687 | ||
141b38b6 | 1688 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1689 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1690 | { |
bce048d7 JM |
1691 | struct ath_wiphy *aphy = hw->priv; |
1692 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1693 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1694 | struct ath9k_tx_queue_info qi; |
1695 | int ret = 0, qnum; | |
f078f209 | 1696 | |
8feceb67 VT |
1697 | if (queue >= WME_NUM_AC) |
1698 | return 0; | |
f078f209 | 1699 | |
141b38b6 S |
1700 | mutex_lock(&sc->mutex); |
1701 | ||
1ffb0610 S |
1702 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1703 | ||
8feceb67 VT |
1704 | qi.tqi_aifs = params->aifs; |
1705 | qi.tqi_cwmin = params->cw_min; | |
1706 | qi.tqi_cwmax = params->cw_max; | |
1707 | qi.tqi_burstTime = params->txop; | |
1708 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1709 | |
c46917bb LR |
1710 | ath_print(common, ATH_DBG_CONFIG, |
1711 | "Configure tx [queue/halq] [%d/%d], " | |
1712 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1713 | queue, qnum, params->aifs, params->cw_min, | |
1714 | params->cw_max, params->txop); | |
f078f209 | 1715 | |
8feceb67 VT |
1716 | ret = ath_txq_update(sc, qnum, &qi); |
1717 | if (ret) | |
c46917bb | 1718 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1719 | |
94db2936 | 1720 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1d2231e2 | 1721 | if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret) |
94db2936 VN |
1722 | ath_beaconq_config(sc); |
1723 | ||
141b38b6 S |
1724 | mutex_unlock(&sc->mutex); |
1725 | ||
8feceb67 VT |
1726 | return ret; |
1727 | } | |
f078f209 | 1728 | |
8feceb67 VT |
1729 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1730 | enum set_key_cmd cmd, | |
dc822b5d JB |
1731 | struct ieee80211_vif *vif, |
1732 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1733 | struct ieee80211_key_conf *key) |
1734 | { | |
bce048d7 JM |
1735 | struct ath_wiphy *aphy = hw->priv; |
1736 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1737 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1738 | int ret = 0; |
f078f209 | 1739 | |
b3bd89ce JM |
1740 | if (modparam_nohwcrypt) |
1741 | return -ENOSPC; | |
1742 | ||
141b38b6 | 1743 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1744 | ath9k_ps_wakeup(sc); |
c46917bb | 1745 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1746 | |
8feceb67 VT |
1747 | switch (cmd) { |
1748 | case SET_KEY: | |
1f03baad | 1749 | ret = ath9k_cmn_key_config(common, vif, sta, key); |
6ace2891 JM |
1750 | if (ret >= 0) { |
1751 | key->hw_key_idx = ret; | |
8feceb67 VT |
1752 | /* push IV and Michael MIC generation to stack */ |
1753 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1754 | if (key->alg == ALG_TKIP) | |
1755 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
1756 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
1757 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 1758 | ret = 0; |
8feceb67 VT |
1759 | } |
1760 | break; | |
1761 | case DISABLE_KEY: | |
1f03baad | 1762 | ath9k_cmn_key_delete(common, key); |
8feceb67 VT |
1763 | break; |
1764 | default: | |
1765 | ret = -EINVAL; | |
1766 | } | |
f078f209 | 1767 | |
3cbb5dd7 | 1768 | ath9k_ps_restore(sc); |
141b38b6 S |
1769 | mutex_unlock(&sc->mutex); |
1770 | ||
8feceb67 VT |
1771 | return ret; |
1772 | } | |
f078f209 | 1773 | |
8feceb67 VT |
1774 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1775 | struct ieee80211_vif *vif, | |
1776 | struct ieee80211_bss_conf *bss_conf, | |
1777 | u32 changed) | |
1778 | { | |
bce048d7 JM |
1779 | struct ath_wiphy *aphy = hw->priv; |
1780 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1781 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1782 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1783 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1784 | int slottime; |
c6089ccc | 1785 | int error; |
f078f209 | 1786 | |
141b38b6 S |
1787 | mutex_lock(&sc->mutex); |
1788 | ||
c6089ccc S |
1789 | if (changed & BSS_CHANGED_BSSID) { |
1790 | /* Set BSSID */ | |
1791 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1792 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1793 | common->curaid = 0; |
f2b2143e | 1794 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1795 | |
c6089ccc S |
1796 | /* Set aggregation protection mode parameters */ |
1797 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1798 | |
c6089ccc S |
1799 | /* Only legacy IBSS for now */ |
1800 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1801 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1802 | |
c6089ccc S |
1803 | ath_print(common, ATH_DBG_CONFIG, |
1804 | "BSSID: %pM aid: 0x%x\n", | |
1805 | common->curbssid, common->curaid); | |
2d0ddec5 | 1806 | |
c6089ccc S |
1807 | /* need to reconfigure the beacon */ |
1808 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1809 | } | |
2d0ddec5 | 1810 | |
c6089ccc S |
1811 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1812 | if ((changed & BSS_CHANGED_BEACON) || | |
1813 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1814 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1815 | error = ath_beacon_alloc(aphy, vif); | |
1816 | if (!error) | |
1817 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1818 | } |
1819 | ||
1820 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1821 | if (bss_conf->use_short_slot) | |
1822 | slottime = 9; | |
1823 | else | |
1824 | slottime = 20; | |
1825 | if (vif->type == NL80211_IFTYPE_AP) { | |
1826 | /* | |
1827 | * Defer update, so that connected stations can adjust | |
1828 | * their settings at the same time. | |
1829 | * See beacon.c for more details | |
1830 | */ | |
1831 | sc->beacon.slottime = slottime; | |
1832 | sc->beacon.updateslot = UPDATE; | |
1833 | } else { | |
1834 | ah->slottime = slottime; | |
1835 | ath9k_hw_init_global_settings(ah); | |
1836 | } | |
2d0ddec5 JB |
1837 | } |
1838 | ||
c6089ccc S |
1839 | /* Disable transmission of beacons */ |
1840 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1841 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1842 | |
c6089ccc S |
1843 | if (changed & BSS_CHANGED_BEACON_INT) { |
1844 | sc->beacon_interval = bss_conf->beacon_int; | |
1845 | /* | |
1846 | * In case of AP mode, the HW TSF has to be reset | |
1847 | * when the beacon interval changes. | |
1848 | */ | |
1849 | if (vif->type == NL80211_IFTYPE_AP) { | |
1850 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1851 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1852 | error = ath_beacon_alloc(aphy, vif); |
1853 | if (!error) | |
1854 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1855 | } else { |
1856 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1857 | } |
1858 | } | |
1859 | ||
8feceb67 | 1860 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1861 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1862 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1863 | if (bss_conf->use_short_preamble) |
1864 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1865 | else | |
1866 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1867 | } | |
f078f209 | 1868 | |
8feceb67 | 1869 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1870 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1871 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1872 | if (bss_conf->use_cts_prot && |
1873 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1874 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1875 | else | |
1876 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1877 | } | |
f078f209 | 1878 | |
8feceb67 | 1879 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1880 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1881 | bss_conf->assoc); |
5640b08e | 1882 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 1883 | } |
141b38b6 S |
1884 | |
1885 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1886 | } |
f078f209 | 1887 | |
8feceb67 VT |
1888 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1889 | { | |
1890 | u64 tsf; | |
bce048d7 JM |
1891 | struct ath_wiphy *aphy = hw->priv; |
1892 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1893 | |
141b38b6 S |
1894 | mutex_lock(&sc->mutex); |
1895 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
1896 | mutex_unlock(&sc->mutex); | |
f078f209 | 1897 | |
8feceb67 VT |
1898 | return tsf; |
1899 | } | |
f078f209 | 1900 | |
3b5d665b AF |
1901 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1902 | { | |
bce048d7 JM |
1903 | struct ath_wiphy *aphy = hw->priv; |
1904 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1905 | |
141b38b6 S |
1906 | mutex_lock(&sc->mutex); |
1907 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
1908 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
1909 | } |
1910 | ||
8feceb67 VT |
1911 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1912 | { | |
bce048d7 JM |
1913 | struct ath_wiphy *aphy = hw->priv; |
1914 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 1915 | |
141b38b6 | 1916 | mutex_lock(&sc->mutex); |
21526d57 LR |
1917 | |
1918 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1919 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1920 | ath9k_ps_restore(sc); |
1921 | ||
141b38b6 | 1922 | mutex_unlock(&sc->mutex); |
8feceb67 | 1923 | } |
f078f209 | 1924 | |
8feceb67 | 1925 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1926 | struct ieee80211_vif *vif, |
141b38b6 S |
1927 | enum ieee80211_ampdu_mlme_action action, |
1928 | struct ieee80211_sta *sta, | |
1929 | u16 tid, u16 *ssn) | |
8feceb67 | 1930 | { |
bce048d7 JM |
1931 | struct ath_wiphy *aphy = hw->priv; |
1932 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1933 | int ret = 0; |
f078f209 | 1934 | |
85ad181e JB |
1935 | local_bh_disable(); |
1936 | ||
8feceb67 VT |
1937 | switch (action) { |
1938 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
1939 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
1940 | ret = -ENOTSUPP; | |
8feceb67 VT |
1941 | break; |
1942 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1943 | break; |
1944 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1945 | ath9k_ps_wakeup(sc); |
f83da965 | 1946 | ath_tx_aggr_start(sc, sta, tid, ssn); |
c951ad35 | 1947 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1948 | ath9k_ps_restore(sc); |
8feceb67 VT |
1949 | break; |
1950 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1951 | ath9k_ps_wakeup(sc); |
f83da965 | 1952 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1953 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1954 | ath9k_ps_restore(sc); |
8feceb67 | 1955 | break; |
b1720231 | 1956 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1957 | ath9k_ps_wakeup(sc); |
8469cdef | 1958 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1959 | ath9k_ps_restore(sc); |
8469cdef | 1960 | break; |
8feceb67 | 1961 | default: |
c46917bb LR |
1962 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1963 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
1964 | } |
1965 | ||
85ad181e JB |
1966 | local_bh_enable(); |
1967 | ||
8feceb67 | 1968 | return ret; |
f078f209 LR |
1969 | } |
1970 | ||
62dad5b0 BP |
1971 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1972 | struct survey_info *survey) | |
1973 | { | |
1974 | struct ath_wiphy *aphy = hw->priv; | |
1975 | struct ath_softc *sc = aphy->sc; | |
1976 | struct ath_hw *ah = sc->sc_ah; | |
1977 | struct ath_common *common = ath9k_hw_common(ah); | |
1978 | struct ieee80211_conf *conf = &hw->conf; | |
1979 | ||
1980 | if (idx != 0) | |
1981 | return -ENOENT; | |
1982 | ||
1983 | survey->channel = conf->channel; | |
1984 | survey->filled = SURVEY_INFO_NOISE_DBM; | |
1985 | survey->noise = common->ani.noise_floor; | |
1986 | ||
1987 | return 0; | |
1988 | } | |
1989 | ||
0c98de65 S |
1990 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
1991 | { | |
bce048d7 JM |
1992 | struct ath_wiphy *aphy = hw->priv; |
1993 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1994 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1995 | |
3d832611 | 1996 | mutex_lock(&sc->mutex); |
8089cc47 | 1997 | if (ath9k_wiphy_scanning(sc)) { |
8089cc47 | 1998 | /* |
30888338 LR |
1999 | * There is a race here in mac80211 but fixing it requires |
2000 | * we revisit how we handle the scan complete callback. | |
2001 | * After mac80211 fixes we will not have configured hardware | |
2002 | * to the home channel nor would we have configured the RX | |
2003 | * filter yet. | |
8089cc47 | 2004 | */ |
3d832611 | 2005 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
2006 | return; |
2007 | } | |
2008 | ||
2009 | aphy->state = ATH_WIPHY_SCAN; | |
2010 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
0c98de65 | 2011 | sc->sc_flags |= SC_OP_SCANNING; |
05c78d6d | 2012 | del_timer_sync(&common->ani.timer); |
9f42c2b6 | 2013 | cancel_work_sync(&sc->paprd_work); |
347809fc | 2014 | cancel_work_sync(&sc->hw_check_work); |
b6ce5c33 | 2015 | cancel_delayed_work_sync(&sc->tx_complete_work); |
3d832611 | 2016 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2017 | } |
2018 | ||
30888338 LR |
2019 | /* |
2020 | * XXX: this requires a revisit after the driver | |
2021 | * scan_complete gets moved to another place/removed in mac80211. | |
2022 | */ | |
0c98de65 S |
2023 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) |
2024 | { | |
bce048d7 JM |
2025 | struct ath_wiphy *aphy = hw->priv; |
2026 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 2027 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 2028 | |
3d832611 | 2029 | mutex_lock(&sc->mutex); |
8089cc47 | 2030 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 2031 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 2032 | sc->sc_flags |= SC_OP_FULL_RESET; |
05c78d6d | 2033 | ath_start_ani(common); |
b6ce5c33 | 2034 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
d0bec342 | 2035 | ath_beacon_config(sc, NULL); |
3d832611 | 2036 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2037 | } |
2038 | ||
e239d859 FF |
2039 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2040 | { | |
2041 | struct ath_wiphy *aphy = hw->priv; | |
2042 | struct ath_softc *sc = aphy->sc; | |
2043 | struct ath_hw *ah = sc->sc_ah; | |
2044 | ||
2045 | mutex_lock(&sc->mutex); | |
2046 | ah->coverage_class = coverage_class; | |
2047 | ath9k_hw_init_global_settings(ah); | |
2048 | mutex_unlock(&sc->mutex); | |
2049 | } | |
2050 | ||
6baff7f9 | 2051 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2052 | .tx = ath9k_tx, |
2053 | .start = ath9k_start, | |
2054 | .stop = ath9k_stop, | |
2055 | .add_interface = ath9k_add_interface, | |
2056 | .remove_interface = ath9k_remove_interface, | |
2057 | .config = ath9k_config, | |
8feceb67 | 2058 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2059 | .sta_add = ath9k_sta_add, |
2060 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2061 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2062 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2063 | .set_key = ath9k_set_key, |
8feceb67 | 2064 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2065 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2066 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2067 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2068 | .get_survey = ath9k_get_survey, |
0c98de65 S |
2069 | .sw_scan_start = ath9k_sw_scan_start, |
2070 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2071 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2072 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2073 | }; |