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Merge branch 'master' of ssh://master.kernel.org/pub/scm/linux/kernel/git/rusty/linux...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209 19
f078f209
LR		 20static char *dev_info = "ath9k";
21
22MODULE_AUTHOR("Atheros Communications");
23MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25MODULE_LICENSE("Dual BSD/GPL");
26
b3bd89ce
JM		 27static int modparam_nohwcrypt;
28module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
5f8e077c
LR		 31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
eeddfd9d 36 .max_power = 20, \
5f8e077c
LR		 37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
eeddfd9d 43 .max_power = 20, \
5f8e077c
LR		 44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
ce111bad
LR		 102static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
ff37e337 104{
030bb495
LR		 105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 116 else
030bb495
LR		 117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
96742256
LR		 131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 133 break;
134 default:
ce111bad 135 BUG_ON(1);
030bb495
LR		 136 break;
137 }
ff37e337
S		 138}
139
140static void ath_update_txpow(struct ath_softc *sc)
141{
cbe61d8a 142 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 143 u32 txpow;
144
17d7904d
S		 145 if (sc->curtxpow != sc->config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 149 sc->curtxpow = txpow;
ff37e337
S		 150 }
151}
152
153static u8 parse_mpdudensity(u8 mpdudensity)
154{
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186}
187
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
4f0fc7c3 190 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
ff37e337 225 sband->n_bitrates++;
f46730d1 226
04bd4638
S		 227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 229 }
230}
231
82880a7c
VT		 232static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233 struct ieee80211_hw *hw)
234{
235 struct ieee80211_channel *curchan = hw->conf.channel;
236 struct ath9k_channel *channel;
237 u8 chan_idx;
238
239 chan_idx = curchan->hw_value;
240 channel = &sc->sc_ah->channels[chan_idx];
241 ath9k_update_ichannel(sc, hw, channel);
242 return channel;
243}
244
ff37e337
S		 245/*
246 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending
248 * DMA, then restart stuff.
249*/
0e2dedf9
JM		 250int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan)
ff37e337 252{
cbe61d8a 253 struct ath_hw *ah = sc->sc_ah;
ff37e337 254 bool fastcc = true, stopped;
ae8d2858
LR		 255 struct ieee80211_channel *channel = hw->conf.channel;
256 int r;
ff37e337
S		 257
258 if (sc->sc_flags & SC_OP_INVALID)
259 return -EIO;
260
3cbb5dd7
VN		 261 ath9k_ps_wakeup(sc);
262
c0d7c7af
LR		 263 /*
264 * This is only performed if the channel settings have
265 * actually changed.
266 *
267 * To switch channels clear any pending DMA operations;
268 * wait long enough for the RX fifo to drain, reset the
269 * hardware at the new frequency, and then re-enable
270 * the relevant bits of the h/w.
271 */
272 ath9k_hw_set_interrupts(ah, 0);
043a0405 273 ath_drain_all_txq(sc, false);
c0d7c7af 274 stopped = ath_stoprecv(sc);
ff37e337 275
c0d7c7af
LR		 276 /* XXX: do not flush receive queue here. We don't want
277 * to flush data frames already in queue because of
278 * changing channel. */
ff37e337 279
c0d7c7af
LR		 280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false;
282
283 DPRINTF(sc, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 285 sc->sc_ah->curchan->channel,
c0d7c7af 286 channel->center_freq, sc->tx_chan_width);
ff37e337 287
c0d7c7af
LR		 288 spin_lock_bh(&sc->sc_resetlock);
289
290 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) "
6b45784f 294 "reset status %d\n",
c0d7c7af
LR		 295 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock);
3989279c 297 goto ps_restore;
ff37e337 298 }
c0d7c7af
LR		 299 spin_unlock_bh(&sc->sc_resetlock);
300
c0d7c7af
LR		 301 sc->sc_flags &= ~SC_OP_FULL_RESET;
302
303 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n");
3989279c
GJ		 306 r = -EIO;
307 goto ps_restore;
c0d7c7af
LR		 308 }
309
310 ath_cache_conf_rate(sc, &hw->conf);
311 ath_update_txpow(sc);
17d7904d 312 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 313
314 ps_restore:
3cbb5dd7 315 ath9k_ps_restore(sc);
3989279c 316 return r;
ff37e337
S		 317}
318
319/*
320 * This routine performs the periodic noise floor calibration function
321 * that is used to adjust and optimize the chip performance. This
322 * takes environmental changes (location, temperature) into account.
323 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated.
325 */
326static void ath_ani_calibrate(unsigned long data)
327{
20977d3e
S		 328 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 330 bool longcal = false;
331 bool shortcal = false;
332 bool aniflag = false;
333 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 334 u32 cal_interval, short_cal_interval;
ff37e337 335
20977d3e
S		 336 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 338
339 /*
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
342 */
e5f0921a 343 spin_lock(&sc->ani_lock);
0c98de65 344 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 345 goto set_timer;
ff37e337 346
1ffc1c61
JM		 347 /* Only calibrate if awake */
348 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349 goto set_timer;
350
351 ath9k_ps_wakeup(sc);
352
ff37e337 353 /* Long calibration runs independently of short calibration. */
17d7904d 354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 355 longcal = true;
04bd4638 356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 357 sc->ani.longcal_timer = timestamp;
ff37e337
S		 358 }
359
17d7904d
S		 360 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) {
20977d3e 362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 363 shortcal = true;
04bd4638 364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 365 sc->ani.shortcal_timer = timestamp;
366 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 367 }
368 } else {
17d7904d 369 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 370 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone)
373 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 374 }
375 }
376
377 /* Verify whether we must check ANI */
20977d3e 378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 379 aniflag = true;
17d7904d 380 sc->ani.checkani_timer = timestamp;
ff37e337
S		 381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
22e66a4c 387 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 388
389 /* Perform calibration if necessary */
390 if (longcal || shortcal) {
379f0440
S		 391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
392 sc->rx_chainmask, longcal);
393
394 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan);
397
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399 ah->curchan->channel, ah->curchan->channelFlags,
400 sc->ani.noise_floor);
ff37e337
S		 401 }
402 }
403
1ffc1c61
JM		 404 ath9k_ps_restore(sc);
405
20977d3e 406set_timer:
e5f0921a 407 spin_unlock(&sc->ani_lock);
ff37e337
S		 408 /*
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
412 */
aac9207e 413 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 414 if (sc->sc_ah->config.enable_ani)
aac9207e 415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 416 if (!sc->ani.caldone)
20977d3e 417 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 418
17d7904d 419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 420}
421
415f738e
S		 422static void ath_start_ani(struct ath_softc *sc)
423{
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
429
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432}
433
ff37e337
S		 434/*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
ff37e337 439 */
0e2dedf9 440void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 441{
3d832611 442 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
81fa16fb 443 (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE)) {
2660b81a
S		 444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 446 } else {
17d7904d
S		 447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
ff37e337
S		 449 }
450
04bd4638 451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 452 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 453}
454
455static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456{
457 struct ath_node *an;
458
459 an = (struct ath_node *)sta->drv_priv;
460
87792efc 461 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 462 ath_tx_node_init(sc, an);
9e98ac65 463 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 466 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 467 }
ff37e337
S		 468}
469
470static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471{
472 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474 if (sc->sc_flags & SC_OP_TXAGGR)
475 ath_tx_node_cleanup(sc, an);
476}
477
478static void ath9k_tasklet(unsigned long data)
479{
480 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 481 u32 status = sc->intrstatus;
ff37e337 482
153e080d
VT		 483 ath9k_ps_wakeup(sc);
484
ff37e337 485 if (status & ATH9K_INT_FATAL) {
ff37e337 486 ath_reset(sc, false);
153e080d 487 ath9k_ps_restore(sc);
ff37e337 488 return;
063d8be3 489 }
ff37e337 490
063d8be3
S		 491 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
492 spin_lock_bh(&sc->rx.rxflushlock);
493 ath_rx_tasklet(sc, 0);
494 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 495 }
496
063d8be3
S		 497 if (status & ATH9K_INT_TX)
498 ath_tx_tasklet(sc);
499
96148326 500 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 501 /*
502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon.
504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 507 }
508
ebb8e1d7
VT		 509 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
510 if (status & ATH9K_INT_GENTIMER)
511 ath_gen_timer_isr(sc->sc_ah);
512
ff37e337 513 /* re-enable hardware interrupt */
17d7904d 514 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 515 ath9k_ps_restore(sc);
ff37e337
S		 516}
517
6baff7f9 518irqreturn_t ath_isr(int irq, void *dev)
ff37e337 519{
063d8be3
S		 520#define SCHED_INTR ( \
521 ATH9K_INT_FATAL | \
522 ATH9K_INT_RXORN | \
523 ATH9K_INT_RXEOL | \
524 ATH9K_INT_RX | \
525 ATH9K_INT_TX | \
526 ATH9K_INT_BMISS | \
527 ATH9K_INT_CST | \
ebb8e1d7
VT		 528 ATH9K_INT_TSFOOR | \
529 ATH9K_INT_GENTIMER)
063d8be3 530
ff37e337 531 struct ath_softc *sc = dev;
cbe61d8a 532 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 533 enum ath9k_int status;
534 bool sched = false;
535
063d8be3
S		 536 /*
537 * The hardware is not ready/present, don't
538 * touch anything. Note this can happen early
539 * on if the IRQ is shared.
540 */
541 if (sc->sc_flags & SC_OP_INVALID)
542 return IRQ_NONE;
ff37e337 543
063d8be3
S		 544
545 /* shared irq, not for us */
546
153e080d 547 if (!ath9k_hw_intrpend(ah))
063d8be3 548 return IRQ_NONE;
063d8be3
S		 549
550 /*
551 * Figure out the reason(s) for the interrupt. Note
552 * that the hal returns a pseudo-ISR that may include
553 * bits we haven't explicitly enabled so we mask the
554 * value to insure we only process bits we requested.
555 */
556 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
557 status &= sc->imask; /* discard unasked-for bits */
ff37e337 558
063d8be3
S		 559 /*
560 * If there are no status bits set, then this interrupt was not
561 * for me (should have been caught above).
562 */
153e080d 563 if (!status)
063d8be3 564 return IRQ_NONE;
ff37e337 565
063d8be3
S		 566 /* Cache the status */
567 sc->intrstatus = status;
568
569 if (status & SCHED_INTR)
570 sched = true;
571
572 /*
573 * If a FATAL or RXORN interrupt is received, we have to reset the
574 * chip immediately.
575 */
576 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
577 goto chip_reset;
578
579 if (status & ATH9K_INT_SWBA)
580 tasklet_schedule(&sc->bcon_tasklet);
581
582 if (status & ATH9K_INT_TXURN)
583 ath9k_hw_updatetxtriglevel(ah, true);
584
585 if (status & ATH9K_INT_MIB) {
ff37e337 586 /*
063d8be3
S		 587 * Disable interrupts until we service the MIB
588 * interrupt; otherwise it will continue to
589 * fire.
ff37e337 590 */
063d8be3
S		 591 ath9k_hw_set_interrupts(ah, 0);
592 /*
593 * Let the hal handle the event. We assume
594 * it will clear whatever condition caused
595 * the interrupt.
596 */
22e66a4c 597 ath9k_hw_procmibevent(ah);
063d8be3
S		 598 ath9k_hw_set_interrupts(ah, sc->imask);
599 }
ff37e337 600
153e080d
VT		 601 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
602 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 603 /* Clear RxAbort bit so that we can
604 * receive frames */
605 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 606 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 607 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 608 }
063d8be3
S		 609
610chip_reset:
ff37e337 611
817e11de
S		 612 ath_debug_stat_interrupt(sc, status);
613
ff37e337
S		 614 if (sched) {
615 /* turn off every interrupt except SWBA */
17d7904d 616 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 617 tasklet_schedule(&sc->intr_tq);
618 }
619
620 return IRQ_HANDLED;
063d8be3
S		 621
622#undef SCHED_INTR
ff37e337
S		 623}
624
f078f209 625static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 626 struct ieee80211_channel *chan,
094d05dc 627 enum nl80211_channel_type channel_type)
f078f209
LR		 628{
629 u32 chanmode = 0;
f078f209
LR		 630
631 switch (chan->band) {
632 case IEEE80211_BAND_2GHZ:
094d05dc
S		 633 switch(channel_type) {
634 case NL80211_CHAN_NO_HT:
635 case NL80211_CHAN_HT20:
f078f209 636 chanmode = CHANNEL_G_HT20;
094d05dc
S		 637 break;
638 case NL80211_CHAN_HT40PLUS:
f078f209 639 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 640 break;
641 case NL80211_CHAN_HT40MINUS:
f078f209 642 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 643 break;
644 }
f078f209
LR		 645 break;
646 case IEEE80211_BAND_5GHZ:
094d05dc
S		 647 switch(channel_type) {
648 case NL80211_CHAN_NO_HT:
649 case NL80211_CHAN_HT20:
f078f209 650 chanmode = CHANNEL_A_HT20;
094d05dc
S		 651 break;
652 case NL80211_CHAN_HT40PLUS:
f078f209 653 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 654 break;
655 case NL80211_CHAN_HT40MINUS:
f078f209 656 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 657 break;
658 }
f078f209
LR		 659 break;
660 default:
661 break;
662 }
663
664 return chanmode;
665}
666
6ace2891 667static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 668 struct ath9k_keyval *hk, const u8 *addr,
669 bool authenticator)
f078f209 670{
6ace2891
JM		 671 const u8 *key_rxmic;
672 const u8 *key_txmic;
f078f209 673
6ace2891
JM		 674 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
675 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 676
677 if (addr == NULL) {
d216aaa6
JM		 678 /*
679 * Group key installation - only two key cache entries are used
680 * regardless of splitmic capability since group key is only
681 * used either for TX or RX.
682 */
3f53dd64
JM		 683 if (authenticator) {
684 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
685 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
686 } else {
687 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
688 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
689 }
d216aaa6 690 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 691 }
17d7904d 692 if (!sc->splitmic) {
d216aaa6 693 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 694 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
695 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 696 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 697 }
d216aaa6
JM		 698
699 /* Separate key cache entries for TX and RX */
700
701 /* TX key goes at first index, RX key at +32. */
f078f209 702 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 703 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
704 /* TX MIC entry failed. No need to proceed further */
d8baa939 705 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 706 "Setting TX MIC Key Failed\n");
f078f209
LR		 707 return 0;
708 }
709
710 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
711 /* XXX delete tx key on failure? */
d216aaa6 712 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 713}
714
715static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
716{
717 int i;
718
17d7904d
S		 719 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
720 if (test_bit(i, sc->keymap) ||
721 test_bit(i + 64, sc->keymap))
6ace2891 722 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 723 if (sc->splitmic &&
724 (test_bit(i + 32, sc->keymap) ||
725 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 726 continue; /* At least one part of TKIP key allocated */
727
728 /* Found a free slot for a TKIP key */
729 return i;
730 }
731 return -1;
732}
733
734static int ath_reserve_key_cache_slot(struct ath_softc *sc)
735{
736 int i;
737
738 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 739 if (sc->splitmic) {
740 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
741 if (!test_bit(i, sc->keymap) &&
742 (test_bit(i + 32, sc->keymap) ||
743 test_bit(i + 64, sc->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 745 return i;
17d7904d
S		 746 if (!test_bit(i + 32, sc->keymap) &&
747 (test_bit(i, sc->keymap) ||
748 test_bit(i + 64, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 750 return i + 32;
17d7904d
S		 751 if (!test_bit(i + 64, sc->keymap) &&
752 (test_bit(i , sc->keymap) ||
753 test_bit(i + 32, sc->keymap) ||
754 test_bit(i + 64 + 32, sc->keymap)))
ea612132 755 return i + 64;
17d7904d
S		 756 if (!test_bit(i + 64 + 32, sc->keymap) &&
757 (test_bit(i, sc->keymap) ||
758 test_bit(i + 32, sc->keymap) ||
759 test_bit(i + 64, sc->keymap)))
ea612132 760 return i + 64 + 32;
6ace2891
JM		 761 }
762 } else {
17d7904d
S		 763 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
764 if (!test_bit(i, sc->keymap) &&
765 test_bit(i + 64, sc->keymap))
6ace2891 766 return i;
17d7904d
S		 767 if (test_bit(i, sc->keymap) &&
768 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 769 return i + 64;
770 }
771 }
772
773 /* No partially used TKIP slots, pick any available slot */
17d7904d 774 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 775 /* Do not allow slots that could be needed for TKIP group keys
776 * to be used. This limitation could be removed if we know that
777 * TKIP will not be used. */
778 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
779 continue;
17d7904d 780 if (sc->splitmic) {
be2864cf
JM		 781 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
782 continue;
783 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
784 continue;
785 }
786
17d7904d 787 if (!test_bit(i, sc->keymap))
6ace2891
JM		 788 return i; /* Found a free slot for a key */
789 }
790
791 /* No free slot found */
792 return -1;
f078f209
LR		 793}
794
795static int ath_key_config(struct ath_softc *sc,
3f53dd64 796 struct ieee80211_vif *vif,
dc822b5d 797 struct ieee80211_sta *sta,
f078f209
LR		 798 struct ieee80211_key_conf *key)
799{
f078f209
LR		 800 struct ath9k_keyval hk;
801 const u8 *mac = NULL;
802 int ret = 0;
6ace2891 803 int idx;
f078f209
LR		 804
805 memset(&hk, 0, sizeof(hk));
806
807 switch (key->alg) {
808 case ALG_WEP:
809 hk.kv_type = ATH9K_CIPHER_WEP;
810 break;
811 case ALG_TKIP:
812 hk.kv_type = ATH9K_CIPHER_TKIP;
813 break;
814 case ALG_CCMP:
815 hk.kv_type = ATH9K_CIPHER_AES_CCM;
816 break;
817 default:
ca470b29 818 return -EOPNOTSUPP;
f078f209
LR		 819 }
820
6ace2891 821 hk.kv_len = key->keylen;
f078f209
LR		 822 memcpy(hk.kv_val, key->key, key->keylen);
823
6ace2891
JM		 824 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
825 /* For now, use the default keys for broadcast keys. This may
826 * need to change with virtual interfaces. */
827 idx = key->keyidx;
828 } else if (key->keyidx) {
dc822b5d
JB		 829 if (WARN_ON(!sta))
830 return -EOPNOTSUPP;
831 mac = sta->addr;
832
6ace2891
JM		 833 if (vif->type != NL80211_IFTYPE_AP) {
834 /* Only keyidx 0 should be used with unicast key, but
835 * allow this for client mode for now. */
836 idx = key->keyidx;
837 } else
838 return -EIO;
f078f209 839 } else {
dc822b5d
JB		 840 if (WARN_ON(!sta))
841 return -EOPNOTSUPP;
842 mac = sta->addr;
843
6ace2891
JM		 844 if (key->alg == ALG_TKIP)
845 idx = ath_reserve_key_cache_slot_tkip(sc);
846 else
847 idx = ath_reserve_key_cache_slot(sc);
848 if (idx < 0)
ca470b29 849 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 850 }
851
852 if (key->alg == ALG_TKIP)
3f53dd64
JM		 853 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
854 vif->type == NL80211_IFTYPE_AP);
f078f209 855 else
d216aaa6 856 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 857
858 if (!ret)
859 return -EIO;
860
17d7904d 861 set_bit(idx, sc->keymap);
6ace2891 862 if (key->alg == ALG_TKIP) {
17d7904d
S		 863 set_bit(idx + 64, sc->keymap);
864 if (sc->splitmic) {
865 set_bit(idx + 32, sc->keymap);
866 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 867 }
868 }
869
870 return idx;
f078f209
LR		 871}
872
873static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
874{
6ace2891
JM		 875 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
876 if (key->hw_key_idx < IEEE80211_WEP_NKID)
877 return;
878
17d7904d 879 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 880 if (key->alg != ALG_TKIP)
881 return;
f078f209 882
17d7904d
S		 883 clear_bit(key->hw_key_idx + 64, sc->keymap);
884 if (sc->splitmic) {
885 clear_bit(key->hw_key_idx + 32, sc->keymap);
886 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 887 }
f078f209
LR		 888}
889
eb2599ca
S		 890static void setup_ht_cap(struct ath_softc *sc,
891 struct ieee80211_sta_ht_cap *ht_info)
f078f209 892{
140add21 893 u8 tx_streams, rx_streams;
f078f209 894
d9fe60de
JB		 895 ht_info->ht_supported = true;
896 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
897 IEEE80211_HT_CAP_SM_PS |
898 IEEE80211_HT_CAP_SGI_40 |
899 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 900
9e98ac65
S		 901 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
902 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 903
d9fe60de
JB		 904 /* set up supported mcs set */
905 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 906 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
908
909 if (tx_streams != rx_streams) {
910 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
911 tx_streams, rx_streams);
912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
913 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
914 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
915 }
eb2599ca 916
140add21
SB		 917 ht_info->mcs.rx_mask[0] = 0xff;
918 if (rx_streams >= 2)
eb2599ca 919 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 920
140add21 921 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 922}
923
8feceb67 924static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 925 struct ieee80211_vif *vif,
8feceb67 926 struct ieee80211_bss_conf *bss_conf)
f078f209 927{
f078f209 928
8feceb67 929 if (bss_conf->assoc) {
094d05dc 930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 931 bss_conf->aid, sc->curbssid);
f078f209 932
8feceb67 933 /* New association, store aid */
2664f201
SB		 934 sc->curaid = bss_conf->aid;
935 ath9k_hw_write_associd(sc);
936
937 /*
938 * Request a re-configuration of Beacon related timers
939 * on the receipt of the first Beacon frame (i.e.,
940 * after time sync with the AP).
941 */
942 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 943
8feceb67 944 /* Configure the beacon */
2c3db3d5 945 ath_beacon_config(sc, vif);
f078f209 946
8feceb67 947 /* Reset rssi stats */
22e66a4c 948 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 949
415f738e 950 ath_start_ani(sc);
8feceb67 951 } else {
1ffb0610 952 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 953 sc->curaid = 0;
f38faa31
SB		 954 /* Stop ANI */
955 del_timer_sync(&sc->ani.timer);
f078f209 956 }
8feceb67 957}
f078f209 958
8feceb67
VT		 959/********************************/
960/* LED functions */
961/********************************/
f078f209 962
f2bffa7e
VT		 963static void ath_led_blink_work(struct work_struct *work)
964{
965 struct ath_softc *sc = container_of(work, struct ath_softc,
966 ath_led_blink_work.work);
967
968 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
969 return;
85067c06
VT		 970
971 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
972 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 973 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 974 else
08fc5c1b 975 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 976 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 977
42935eca
LR		 978 ieee80211_queue_delayed_work(sc->hw,
979 &sc->ath_led_blink_work,
980 (sc->sc_flags & SC_OP_LED_ON) ?
981 msecs_to_jiffies(sc->led_off_duration) :
982 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 983
85067c06
VT		 984 sc->led_on_duration = sc->led_on_cnt ?
985 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
986 ATH_LED_ON_DURATION_IDLE;
987 sc->led_off_duration = sc->led_off_cnt ?
988 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
989 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 990 sc->led_on_cnt = sc->led_off_cnt = 0;
991 if (sc->sc_flags & SC_OP_LED_ON)
992 sc->sc_flags &= ~SC_OP_LED_ON;
993 else
994 sc->sc_flags |= SC_OP_LED_ON;
995}
996
8feceb67
VT		 997static void ath_led_brightness(struct led_classdev *led_cdev,
998 enum led_brightness brightness)
999{
1000 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1001 struct ath_softc *sc = led->sc;
f078f209 1002
8feceb67
VT		 1003 switch (brightness) {
1004 case LED_OFF:
1005 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1006 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1007 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1008 (led->led_type == ATH_LED_RADIO));
8feceb67 1009 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1010 if (led->led_type == ATH_LED_RADIO)
1011 sc->sc_flags &= ~SC_OP_LED_ON;
1012 } else {
1013 sc->led_off_cnt++;
1014 }
8feceb67
VT		 1015 break;
1016 case LED_FULL:
f2bffa7e 1017 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1018 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1019 ieee80211_queue_delayed_work(sc->hw,
1020 &sc->ath_led_blink_work, 0);
f2bffa7e 1021 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1022 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1023 sc->sc_flags |= SC_OP_LED_ON;
1024 } else {
1025 sc->led_on_cnt++;
1026 }
8feceb67
VT		 1027 break;
1028 default:
1029 break;
f078f209 1030 }
8feceb67 1031}
f078f209 1032
8feceb67
VT		 1033static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1034 char *trigger)
1035{
1036 int ret;
f078f209 1037
8feceb67
VT		 1038 led->sc = sc;
1039 led->led_cdev.name = led->name;
1040 led->led_cdev.default_trigger = trigger;
1041 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1042
8feceb67
VT		 1043 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1044 if (ret)
1045 DPRINTF(sc, ATH_DBG_FATAL,
1046 "Failed to register led:%s", led->name);
1047 else
1048 led->registered = 1;
1049 return ret;
1050}
f078f209 1051
8feceb67
VT		 1052static void ath_unregister_led(struct ath_led *led)
1053{
1054 if (led->registered) {
1055 led_classdev_unregister(&led->led_cdev);
1056 led->registered = 0;
f078f209 1057 }
f078f209
LR		 1058}
1059
8feceb67 1060static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1061{
8feceb67
VT		 1062 ath_unregister_led(&sc->assoc_led);
1063 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1064 ath_unregister_led(&sc->tx_led);
1065 ath_unregister_led(&sc->rx_led);
1066 ath_unregister_led(&sc->radio_led);
08fc5c1b 1067 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1068}
f078f209 1069
8feceb67
VT		 1070static void ath_init_leds(struct ath_softc *sc)
1071{
1072 char *trigger;
1073 int ret;
f078f209 1074
08fc5c1b
VN		 1075 if (AR_SREV_9287(sc->sc_ah))
1076 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1077 else
1078 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1079
8feceb67 1080 /* Configure gpio 1 for output */
08fc5c1b 1081 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1082 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1083 /* LED off, active low */
08fc5c1b 1084 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1085
f2bffa7e
VT		 1086 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1087
8feceb67
VT		 1088 trigger = ieee80211_get_radio_led_name(sc->hw);
1089 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1090 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1091 ret = ath_register_led(sc, &sc->radio_led, trigger);
1092 sc->radio_led.led_type = ATH_LED_RADIO;
1093 if (ret)
1094 goto fail;
7dcfdcd9 1095
8feceb67
VT		 1096 trigger = ieee80211_get_assoc_led_name(sc->hw);
1097 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1098 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1099 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1100 sc->assoc_led.led_type = ATH_LED_ASSOC;
1101 if (ret)
1102 goto fail;
f078f209 1103
8feceb67
VT		 1104 trigger = ieee80211_get_tx_led_name(sc->hw);
1105 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1106 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1107 ret = ath_register_led(sc, &sc->tx_led, trigger);
1108 sc->tx_led.led_type = ATH_LED_TX;
1109 if (ret)
1110 goto fail;
f078f209 1111
8feceb67
VT		 1112 trigger = ieee80211_get_rx_led_name(sc->hw);
1113 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1114 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1115 ret = ath_register_led(sc, &sc->rx_led, trigger);
1116 sc->rx_led.led_type = ATH_LED_RX;
1117 if (ret)
1118 goto fail;
f078f209 1119
8feceb67
VT		 1120 return;
1121
1122fail:
35c95ab9 1123 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1124 ath_deinit_leds(sc);
f078f209
LR		 1125}
1126
7ec3e514 1127void ath_radio_enable(struct ath_softc *sc)
500c064d 1128{
cbe61d8a 1129 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1130 struct ieee80211_channel *channel = sc->hw->conf.channel;
1131 int r;
500c064d 1132
3cbb5dd7 1133 ath9k_ps_wakeup(sc);
93b1b37f 1134 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1135
159cd468
VT		 1136 if (!ah->curchan)
1137 ah->curchan = ath_get_curchannel(sc, sc->hw);
1138
d2f5b3a6 1139 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1140 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1141 if (r) {
500c064d 1142 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1143 "Unable to reset channel %u (%uMhz) ",
6b45784f 1144 "reset status %d\n",
ae8d2858 1145 channel->center_freq, r);
500c064d
VT		 1146 }
1147 spin_unlock_bh(&sc->sc_resetlock);
1148
1149 ath_update_txpow(sc);
1150 if (ath_startrecv(sc) != 0) {
1151 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1152 "Unable to restart recv logic\n");
500c064d
VT		 1153 return;
1154 }
1155
1156 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1157 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1158
1159 /* Re-Enable interrupts */
17d7904d 1160 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1161
1162 /* Enable LED */
08fc5c1b 1163 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1164 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1165 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d
VT		 1166
1167 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1168 ath9k_ps_restore(sc);
500c064d
VT		 1169}
1170
7ec3e514 1171void ath_radio_disable(struct ath_softc *sc)
500c064d 1172{
cbe61d8a 1173 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1174 struct ieee80211_channel *channel = sc->hw->conf.channel;
1175 int r;
500c064d 1176
3cbb5dd7 1177 ath9k_ps_wakeup(sc);
500c064d
VT		 1178 ieee80211_stop_queues(sc->hw);
1179
1180 /* Disable LED */
08fc5c1b
VN		 1181 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1182 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1183
1184 /* Disable interrupts */
1185 ath9k_hw_set_interrupts(ah, 0);
1186
043a0405 1187 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1188 ath_stoprecv(sc); /* turn off frame recv */
1189 ath_flushrecv(sc); /* flush recv queue */
1190
159cd468
VT		 1191 if (!ah->curchan)
1192 ah->curchan = ath_get_curchannel(sc, sc->hw);
1193
500c064d 1194 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1195 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1196 if (r) {
500c064d 1197 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1198 "Unable to reset channel %u (%uMhz) "
6b45784f 1199 "reset status %d\n",
ae8d2858 1200 channel->center_freq, r);
500c064d
VT		 1201 }
1202 spin_unlock_bh(&sc->sc_resetlock);
1203
1204 ath9k_hw_phy_disable(ah);
93b1b37f 1205 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1206 ath9k_ps_restore(sc);
38ab422e 1207 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1208}
1209
5077fd35
GJ		 1210/*******************/
1211/* Rfkill */
1212/*******************/
1213
500c064d
VT		 1214static bool ath_is_rfkill_set(struct ath_softc *sc)
1215{
cbe61d8a 1216 struct ath_hw *ah = sc->sc_ah;
500c064d 1217
2660b81a
S		 1218 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1219 ah->rfkill_polarity;
500c064d
VT		 1220}
1221
3b319aae 1222static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1223{
3b319aae
JB		 1224 struct ath_wiphy *aphy = hw->priv;
1225 struct ath_softc *sc = aphy->sc;
19d337df 1226 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1227
3b319aae 1228 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1229}
1230
3b319aae 1231static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1232{
3b319aae 1233 struct ath_hw *ah = sc->sc_ah;
9c84b797 1234
3b319aae
JB		 1235 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1236 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1237}
500c064d 1238
6baff7f9 1239void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1240{
1241 ath_detach(sc);
1242 free_irq(sc->irq, sc);
1243 ath_bus_cleanup(sc);
c52f33d0 1244 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1245 ieee80211_free_hw(sc->hw);
1246}
1247
6baff7f9 1248void ath_detach(struct ath_softc *sc)
f078f209 1249{
8feceb67 1250 struct ieee80211_hw *hw = sc->hw;
9c84b797 1251 int i = 0;
f078f209 1252
3cbb5dd7
VN		 1253 ath9k_ps_wakeup(sc);
1254
04bd4638 1255 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1256
35c95ab9 1257 ath_deinit_leds(sc);
e31f7b96 1258 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1259
c52f33d0
JM		 1260 for (i = 0; i < sc->num_sec_wiphy; i++) {
1261 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1262 if (aphy == NULL)
1263 continue;
1264 sc->sec_wiphy[i] = NULL;
1265 ieee80211_unregister_hw(aphy->hw);
1266 ieee80211_free_hw(aphy->hw);
1267 }
3fcdfb4b 1268 ieee80211_unregister_hw(hw);
8feceb67
VT		 1269 ath_rx_cleanup(sc);
1270 ath_tx_cleanup(sc);
f078f209 1271
9c84b797
S		 1272 tasklet_kill(&sc->intr_tq);
1273 tasklet_kill(&sc->bcon_tasklet);
f078f209 1274
9c84b797
S		 1275 if (!(sc->sc_flags & SC_OP_INVALID))
1276 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1277
9c84b797
S		 1278 /* cleanup tx queues */
1279 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1280 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1281 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1282
1773912b
VT		 1283 if ((sc->btcoex_info.no_stomp_timer) &&
1284 sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
1285 ath_gen_timer_free(sc->sc_ah, sc->btcoex_info.no_stomp_timer);
1286
9c84b797 1287 ath9k_hw_detach(sc->sc_ah);
3ce1b1a9 1288 sc->sc_ah = NULL;
826d2680 1289 ath9k_exit_debug(sc);
f078f209
LR		 1290}
1291
e3bb249b
BC		 1292static int ath9k_reg_notifier(struct wiphy *wiphy,
1293 struct regulatory_request *request)
1294{
1295 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1296 struct ath_wiphy *aphy = hw->priv;
1297 struct ath_softc *sc = aphy->sc;
608b88cb 1298 struct ath_regulatory *reg = &sc->common.regulatory;
e3bb249b
BC		 1299
1300 return ath_reg_notifier_apply(wiphy, request, reg);
1301}
1302
1e40bcfa
LR		 1303/*
1304 * Initialize and fill ath_softc, ath_sofct is the
1305 * "Software Carrier" struct. Historically it has existed
1306 * to allow the separation between hardware specific
1307 * variables (now in ath_hw) and driver specific variables.
1308 */
aeac355d 1309static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
ff37e337 1310{
cbe61d8a 1311 struct ath_hw *ah = NULL;
4f3acf81 1312 int r = 0, i;
ff37e337
S		 1313 int csz = 0;
1314
1315 /* XXX: hardware will not be ready until ath_open() being called */
1316 sc->sc_flags |= SC_OP_INVALID;
88b126af 1317
826d2680
S		 1318 if (ath9k_init_debug(sc) < 0)
1319 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1320
c52f33d0 1321 spin_lock_init(&sc->wiphy_lock);
ff37e337 1322 spin_lock_init(&sc->sc_resetlock);
6158425b 1323 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1324 spin_lock_init(&sc->ani_lock);
04717ccd 1325 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1326 mutex_init(&sc->mutex);
ff37e337 1327 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1328 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1329 (unsigned long)sc);
1330
1331 /*
1332 * Cache line size is used to size and align various
1333 * structures used to communicate with the hardware.
1334 */
88d15707 1335 ath_read_cachesize(sc, &csz);
ff37e337 1336 /* XXX assert csz is non-zero */
d15dd3e5 1337 sc->common.cachelsz = csz << 2; /* convert to bytes */
ff37e337 1338
4f3acf81
LR		 1339 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1340 if (!ah) {
4f3acf81
LR		 1341 r = -ENOMEM;
1342 goto bad_no_ah;
1343 }
1344
1345 ah->ah_sc = sc;
8df5d1b7 1346 ah->hw_version.devid = devid;
aeac355d 1347 ah->hw_version.subsysid = subsysid;
e1e2f93f 1348 sc->sc_ah = ah;
4f3acf81 1349
f637cfd6 1350 r = ath9k_hw_init(ah);
4f3acf81 1351 if (r) {
ff37e337 1352 DPRINTF(sc, ATH_DBG_FATAL,
f637cfd6 1353 "Unable to initialize hardware; "
4f3acf81 1354 "initialization status: %d\n", r);
ff37e337
S		 1355 goto bad;
1356 }
ff37e337
S		 1357
1358 /* Get the hardware key cache size. */
2660b81a 1359 sc->keymax = ah->caps.keycache_size;
17d7904d 1360 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1361 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1362 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1363 ATH_KEYMAX, sc->keymax);
1364 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1365 }
1366
1367 /*
1368 * Reset the key cache since some parts do not
1369 * reset the contents on initial power up.
1370 */
17d7904d 1371 for (i = 0; i < sc->keymax; i++)
ff37e337 1372 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1373
ff37e337 1374 /* default to MONITOR mode */
2660b81a 1375 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1376
ff37e337
S		 1377 /* Setup rate tables */
1378
1379 ath_rate_attach(sc);
1380 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1381 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1382
1383 /*
1384 * Allocate hardware transmit queues: one queue for
1385 * beacon frames and one data queue for each QoS
1386 * priority. Note that the hal handles reseting
1387 * these queues at the needed time.
1388 */
b77f483f
S		 1389 sc->beacon.beaconq = ath_beaconq_setup(ah);
1390 if (sc->beacon.beaconq == -1) {
ff37e337 1391 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1392 "Unable to setup a beacon xmit queue\n");
4f3acf81 1393 r = -EIO;
ff37e337
S		 1394 goto bad2;
1395 }
b77f483f
S		 1396 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1397 if (sc->beacon.cabq == NULL) {
ff37e337 1398 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1399 "Unable to setup CAB xmit queue\n");
4f3acf81 1400 r = -EIO;
ff37e337
S		 1401 goto bad2;
1402 }
1403
17d7904d 1404 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1405 ath_cabq_update(sc);
1406
b77f483f
S		 1407 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1408 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1409
1410 /* Setup data queues */
1411 /* NB: ensure BK queue is the lowest priority h/w queue */
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1413 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1414 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1415 r = -EIO;
ff37e337
S		 1416 goto bad2;
1417 }
1418
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1420 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1421 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1422 r = -EIO;
ff37e337
S		 1423 goto bad2;
1424 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1427 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1428 r = -EIO;
ff37e337
S		 1429 goto bad2;
1430 }
1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1432 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1433 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1434 r = -EIO;
ff37e337
S		 1435 goto bad2;
1436 }
1437
1438 /* Initializes the noise floor to a reasonable default value.
1439 * Later on this will be updated during ANI processing. */
1440
17d7904d
S		 1441 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1442 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1443
1444 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1445 ATH9K_CIPHER_TKIP, NULL)) {
1446 /*
1447 * Whether we should enable h/w TKIP MIC.
1448 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1449 * report WMM capable, so it's always safe to turn on
1450 * TKIP MIC in this case.
1451 */
1452 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1453 0, 1, NULL);
1454 }
1455
1456 /*
1457 * Check whether the separate key cache entries
1458 * are required to handle both tx+rx MIC keys.
1459 * With split mic keys the number of stations is limited
1460 * to 27 otherwise 59.
1461 */
1462 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1463 ATH9K_CIPHER_TKIP, NULL)
1464 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1465 ATH9K_CIPHER_MIC, NULL)
1466 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1467 0, NULL))
17d7904d 1468 sc->splitmic = 1;
ff37e337
S		 1469
1470 /* turn on mcast key search if possible */
1471 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1472 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1473 1, NULL);
1474
17d7904d 1475 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1476
1477 /* 11n Capabilities */
2660b81a 1478 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1479 sc->sc_flags |= SC_OP_TXAGGR;
1480 sc->sc_flags |= SC_OP_RXAGGR;
1481 }
1482
2660b81a
S		 1483 sc->tx_chainmask = ah->caps.tx_chainmask;
1484 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1485
1486 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1487 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1488
8ca21f01 1489 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1490 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1491
b77f483f 1492 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1493
1494 /* initialize beacon slots */
c52f33d0 1495 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1496 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1497 sc->beacon.bslot_aphy[i] = NULL;
1498 }
ff37e337 1499
ff37e337
S		 1500 /* setup channels and rates */
1501
5f8e077c 1502 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1503 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1504 sc->rates[IEEE80211_BAND_2GHZ];
1505 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1506 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1507 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1508
2660b81a 1509 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1510 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1511 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1512 sc->rates[IEEE80211_BAND_5GHZ];
1513 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1514 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1515 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1516 }
1517
1773912b
VT		 1518 if (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) {
1519 r = ath9k_hw_btcoex_init(ah);
1520 if (r)
1521 goto bad2;
1522 }
c97c92d9 1523
ff37e337
S		 1524 return 0;
1525bad2:
1526 /* cleanup tx queues */
1527 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1528 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1529 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337 1530bad:
95fafca2 1531 ath9k_hw_detach(ah);
3ce1b1a9 1532 sc->sc_ah = NULL;
4f3acf81 1533bad_no_ah:
40b130a9 1534 ath9k_exit_debug(sc);
ff37e337 1535
4f3acf81 1536 return r;
ff37e337
S		 1537}
1538
c52f33d0 1539void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1540{
9c84b797
S		 1541 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1542 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1543 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1544 IEEE80211_HW_AMPDU_AGGREGATION |
1545 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1546 IEEE80211_HW_PS_NULLFUNC_STACK |
1547 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1548
b3bd89ce 1549 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1550 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1551
9c84b797
S		 1552 hw->wiphy->interface_modes =
1553 BIT(NL80211_IFTYPE_AP) |
1554 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1555 BIT(NL80211_IFTYPE_ADHOC) |
1556 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1557
8feceb67 1558 hw->queues = 4;
e63835b0 1559 hw->max_rates = 4;
171387ef 1560 hw->channel_change_time = 5000;
465ca84d 1561 hw->max_listen_interval = 10;
dd190183
LR		 1562 /* Hardware supports 10 but we use 4 */
1563 hw->max_rate_tries = 4;
528f0c6b 1564 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1565 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1566
8feceb67 1567 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1568
c52f33d0
JM		 1569 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1570 &sc->sbands[IEEE80211_BAND_2GHZ];
1571 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1572 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1573 &sc->sbands[IEEE80211_BAND_5GHZ];
1574}
1575
1e40bcfa 1576/* Device driver core initialization */
aeac355d 1577int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
c52f33d0
JM		 1578{
1579 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1580 int error = 0, i;
3a702e49 1581 struct ath_regulatory *reg;
c52f33d0
JM		 1582
1583 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1584
aeac355d 1585 error = ath_init_softc(devid, sc, subsysid);
c52f33d0
JM		 1586 if (error != 0)
1587 return error;
1588
1589 /* get mac address from hardware and set in mac80211 */
1590
1591 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1592
1593 ath_set_hw_capab(sc, hw);
1594
608b88cb 1595 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
c26c2e57
LR		 1596 ath9k_reg_notifier);
1597 if (error)
1598 return error;
1599
608b88cb 1600 reg = &sc->common.regulatory;
c26c2e57 1601
2660b81a 1602 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1603 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1604 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1605 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1606 }
1607
db93e7b5
SB		 1608 /* initialize tx/rx engine */
1609 error = ath_tx_init(sc, ATH_TXBUF);
1610 if (error != 0)
40b130a9 1611 goto error_attach;
8feceb67 1612
db93e7b5
SB		 1613 error = ath_rx_init(sc, ATH_RXBUF);
1614 if (error != 0)
40b130a9 1615 goto error_attach;
8feceb67 1616
0e2dedf9 1617 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1618 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1619 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1620
db93e7b5 1621 error = ieee80211_register_hw(hw);
8feceb67 1622
3a702e49 1623 if (!ath_is_world_regd(reg)) {
c02cf373 1624 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1625 if (error)
1626 goto error_attach;
1627 }
5f8e077c 1628
db93e7b5
SB		 1629 /* Initialize LED control */
1630 ath_init_leds(sc);
8feceb67 1631
3b319aae 1632 ath_start_rfkill_poll(sc);
5f8e077c 1633
8feceb67 1634 return 0;
40b130a9
VT		 1635
1636error_attach:
1637 /* cleanup tx queues */
1638 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1639 if (ATH_TXQ_SETUP(sc, i))
1640 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1641
1642 ath9k_hw_detach(sc->sc_ah);
3ce1b1a9 1643 sc->sc_ah = NULL;
40b130a9
VT		 1644 ath9k_exit_debug(sc);
1645
8feceb67 1646 return error;
f078f209
LR		 1647}
1648
ff37e337
S		 1649int ath_reset(struct ath_softc *sc, bool retry_tx)
1650{
cbe61d8a 1651 struct ath_hw *ah = sc->sc_ah;
030bb495 1652 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1653 int r;
ff37e337
S		 1654
1655 ath9k_hw_set_interrupts(ah, 0);
043a0405 1656 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1657 ath_stoprecv(sc);
1658 ath_flushrecv(sc);
1659
1660 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1661 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1662 if (r)
ff37e337 1663 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1664 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1665 spin_unlock_bh(&sc->sc_resetlock);
1666
1667 if (ath_startrecv(sc) != 0)
04bd4638 1668 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1669
1670 /*
1671 * We may be doing a reset in response to a request
1672 * that changes the channel so update any state that
1673 * might change as a result.
1674 */
ce111bad 1675 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1676
1677 ath_update_txpow(sc);
1678
1679 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1680 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1681
17d7904d 1682 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1683
1684 if (retry_tx) {
1685 int i;
1686 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1687 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1688 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1689 ath_txq_schedule(sc, &sc->tx.txq[i]);
1690 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1691 }
1692 }
1693 }
1694
ae8d2858 1695 return r;
ff37e337
S		 1696}
1697
1698/*
1699 * This function will allocate both the DMA descriptor structure, and the
1700 * buffers it contains. These are used to contain the descriptors used
1701 * by the system.
1702*/
1703int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1704 struct list_head *head, const char *name,
1705 int nbuf, int ndesc)
1706{
1707#define DS2PHYS(_dd, _ds) \
1708 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1709#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1710#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1711
1712 struct ath_desc *ds;
1713 struct ath_buf *bf;
1714 int i, bsize, error;
1715
04bd4638
S		 1716 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1717 name, nbuf, ndesc);
ff37e337 1718
b03a9db9 1719 INIT_LIST_HEAD(head);
ff37e337
S		 1720 /* ath_desc must be a multiple of DWORDs */
1721 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1722 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1723 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1724 error = -ENOMEM;
1725 goto fail;
1726 }
1727
ff37e337
S		 1728 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1729
1730 /*
1731 * Need additional DMA memory because we can't use
1732 * descriptors that cross the 4K page boundary. Assume
1733 * one skipped descriptor per 4K page.
1734 */
2660b81a 1735 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1736 u32 ndesc_skipped =
1737 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1738 u32 dma_len;
1739
1740 while (ndesc_skipped) {
1741 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1742 dd->dd_desc_len += dma_len;
1743
1744 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1745 };
1746 }
1747
1748 /* allocate descriptors */
7da3c55c 1749 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1750 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1751 if (dd->dd_desc == NULL) {
1752 error = -ENOMEM;
1753 goto fail;
1754 }
1755 ds = dd->dd_desc;
04bd4638 1756 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1757 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1758 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1759
1760 /* allocate buffers */
1761 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1762 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1763 if (bf == NULL) {
1764 error = -ENOMEM;
1765 goto fail2;
1766 }
ff37e337
S		 1767 dd->dd_bufptr = bf;
1768
ff37e337
S		 1769 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1770 bf->bf_desc = ds;
1771 bf->bf_daddr = DS2PHYS(dd, ds);
1772
2660b81a 1773 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1774 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1775 /*
1776 * Skip descriptor addresses which can cause 4KB
1777 * boundary crossing (addr + length) with a 32 dword
1778 * descriptor fetch.
1779 */
1780 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1781 ASSERT((caddr_t) bf->bf_desc <
1782 ((caddr_t) dd->dd_desc +
1783 dd->dd_desc_len));
1784
1785 ds += ndesc;
1786 bf->bf_desc = ds;
1787 bf->bf_daddr = DS2PHYS(dd, ds);
1788 }
1789 }
1790 list_add_tail(&bf->list, head);
1791 }
1792 return 0;
1793fail2:
7da3c55c
GJ		 1794 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1795 dd->dd_desc_paddr);
ff37e337
S		 1796fail:
1797 memset(dd, 0, sizeof(*dd));
1798 return error;
1799#undef ATH_DESC_4KB_BOUND_CHECK
1800#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1801#undef DS2PHYS
1802}
1803
1804void ath_descdma_cleanup(struct ath_softc *sc,
1805 struct ath_descdma *dd,
1806 struct list_head *head)
1807{
7da3c55c
GJ		 1808 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1809 dd->dd_desc_paddr);
ff37e337
S		 1810
1811 INIT_LIST_HEAD(head);
1812 kfree(dd->dd_bufptr);
1813 memset(dd, 0, sizeof(*dd));
1814}
1815
1816int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1817{
1818 int qnum;
1819
1820 switch (queue) {
1821 case 0:
b77f483f 1822 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1823 break;
1824 case 1:
b77f483f 1825 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1826 break;
1827 case 2:
b77f483f 1828 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1829 break;
1830 case 3:
b77f483f 1831 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1832 break;
1833 default:
b77f483f 1834 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1835 break;
1836 }
1837
1838 return qnum;
1839}
1840
1841int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1842{
1843 int qnum;
1844
1845 switch (queue) {
1846 case ATH9K_WME_AC_VO:
1847 qnum = 0;
1848 break;
1849 case ATH9K_WME_AC_VI:
1850 qnum = 1;
1851 break;
1852 case ATH9K_WME_AC_BE:
1853 qnum = 2;
1854 break;
1855 case ATH9K_WME_AC_BK:
1856 qnum = 3;
1857 break;
1858 default:
1859 qnum = -1;
1860 break;
1861 }
1862
1863 return qnum;
1864}
1865
5f8e077c
LR		 1866/* XXX: Remove me once we don't depend on ath9k_channel for all
1867 * this redundant data */
0e2dedf9
JM		 1868void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1869 struct ath9k_channel *ichan)
5f8e077c 1870{
5f8e077c
LR		 1871 struct ieee80211_channel *chan = hw->conf.channel;
1872 struct ieee80211_conf *conf = &hw->conf;
1873
1874 ichan->channel = chan->center_freq;
1875 ichan->chan = chan;
1876
1877 if (chan->band == IEEE80211_BAND_2GHZ) {
1878 ichan->chanmode = CHANNEL_G;
8813262e 1879 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 1880 } else {
1881 ichan->chanmode = CHANNEL_A;
1882 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1883 }
1884
1885 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1886
1887 if (conf_is_ht(conf)) {
1888 if (conf_is_ht40(conf))
1889 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1890
1891 ichan->chanmode = ath_get_extchanmode(sc, chan,
1892 conf->channel_type);
1893 }
1894}
1895
ff37e337
S		 1896/**********************/
1897/* mac80211 callbacks */
1898/**********************/
1899
8feceb67 1900static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1901{
bce048d7
JM		 1902 struct ath_wiphy *aphy = hw->priv;
1903 struct ath_softc *sc = aphy->sc;
8feceb67 1904 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1905 struct ath9k_channel *init_channel;
82880a7c 1906 int r;
f078f209 1907
04bd4638
S		 1908 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1909 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1910
141b38b6
S		 1911 mutex_lock(&sc->mutex);
1912
9580a222
JM		 1913 if (ath9k_wiphy_started(sc)) {
1914 if (sc->chan_idx == curchan->hw_value) {
1915 /*
1916 * Already on the operational channel, the new wiphy
1917 * can be marked active.
1918 */
1919 aphy->state = ATH_WIPHY_ACTIVE;
1920 ieee80211_wake_queues(hw);
1921 } else {
1922 /*
1923 * Another wiphy is on another channel, start the new
1924 * wiphy in paused state.
1925 */
1926 aphy->state = ATH_WIPHY_PAUSED;
1927 ieee80211_stop_queues(hw);
1928 }
1929 mutex_unlock(&sc->mutex);
1930 return 0;
1931 }
1932 aphy->state = ATH_WIPHY_ACTIVE;
1933
8feceb67 1934 /* setup initial channel */
f078f209 1935
82880a7c 1936 sc->chan_idx = curchan->hw_value;
f078f209 1937
82880a7c 1938 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1939
1940 /* Reset SERDES registers */
93b1b37f 1941 ath9k_hw_configpcipowersave(sc->sc_ah, 0, 0);
ff37e337
S		 1942
1943 /*
1944 * The basic interface to setting the hardware in a good
1945 * state is ``reset''. On return the hardware is known to
1946 * be powered up and with interrupts disabled. This must
1947 * be followed by initialization of the appropriate bits
1948 * and then setup of the interrupt mask.
1949 */
1950 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1951 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1952 if (r) {
ff37e337 1953 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1954 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1955 "(freq %u MHz)\n", r,
1956 curchan->center_freq);
ff37e337 1957 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1958 goto mutex_unlock;
ff37e337
S		 1959 }
1960 spin_unlock_bh(&sc->sc_resetlock);
1961
1962 /*
1963 * This is needed only to setup initial state
1964 * but it's best done after a reset.
1965 */
1966 ath_update_txpow(sc);
8feceb67 1967
ff37e337
S		 1968 /*
1969 * Setup the hardware after reset:
1970 * The receive engine is set going.
1971 * Frame transmit is handled entirely
1972 * in the frame output path; there's nothing to do
1973 * here except setup the interrupt mask.
1974 */
1975 if (ath_startrecv(sc) != 0) {
1ffb0610 1976 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1977 r = -EIO;
1978 goto mutex_unlock;
f078f209 1979 }
8feceb67 1980
ff37e337 1981 /* Setup our intr mask. */
17d7904d 1982 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1983 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1984 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1985
2660b81a 1986 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1987 sc->imask |= ATH9K_INT_GTT;
ff37e337 1988
2660b81a 1989 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1990 sc->imask |= ATH9K_INT_CST;
ff37e337 1991
ce111bad 1992 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1993
1994 sc->sc_flags &= ~SC_OP_INVALID;
1995
1996 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1997 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1998 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 1999
bce048d7 2000 ieee80211_wake_queues(hw);
ff37e337 2001
42935eca 2002 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2003
1773912b
VT		 2004 if ((sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) &&
2005 !(sc->sc_flags & SC_OP_BTCOEX_ENABLED)) {
2006 ath_btcoex_set_weight(&sc->btcoex_info, AR_BT_COEX_WGHT,
2007 AR_STOMP_LOW_WLAN_WGHT);
f985ad12
VT		 2008 ath9k_hw_btcoex_enable(sc->sc_ah);
2009
7b6840ab 2010 ath_pcie_aspm_disable(sc);
1773912b
VT		 2011 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
2012 ath_btcoex_timer_resume(sc, &sc->btcoex_info);
2013 }
2014
141b38b6
S		 2015mutex_unlock:
2016 mutex_unlock(&sc->mutex);
2017
ae8d2858 2018 return r;
f078f209
LR		 2019}
2020
8feceb67
VT		 2021static int ath9k_tx(struct ieee80211_hw *hw,
2022 struct sk_buff *skb)
f078f209 2023{
528f0c6b 2024 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2025 struct ath_wiphy *aphy = hw->priv;
2026 struct ath_softc *sc = aphy->sc;
528f0c6b 2027 struct ath_tx_control txctl;
8feceb67 2028 int hdrlen, padsize;
528f0c6b 2029
8089cc47 2030 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2031 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2032 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2033 goto exit;
2034 }
2035
96148326 2036 if (sc->ps_enabled) {
dc8c4585
JM		 2037 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2038 /*
2039 * mac80211 does not set PM field for normal data frames, so we
2040 * need to update that based on the current PS mode.
2041 */
2042 if (ieee80211_is_data(hdr->frame_control) &&
2043 !ieee80211_is_nullfunc(hdr->frame_control) &&
2044 !ieee80211_has_pm(hdr->frame_control)) {
2045 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2046 "while in PS mode\n");
2047 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2048 }
2049 }
2050
9a23f9ca
JM		 2051 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2052 /*
2053 * We are using PS-Poll and mac80211 can request TX while in
2054 * power save mode. Need to wake up hardware for the TX to be
2055 * completed and if needed, also for RX of buffered frames.
2056 */
2057 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2058 ath9k_ps_wakeup(sc);
2059 ath9k_hw_setrxabort(sc->sc_ah, 0);
2060 if (ieee80211_is_pspoll(hdr->frame_control)) {
2061 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2062 "buffered frame\n");
2063 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2064 } else {
2065 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2066 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2067 }
2068 /*
2069 * The actual restore operation will happen only after
2070 * the sc_flags bit is cleared. We are just dropping
2071 * the ps_usecount here.
2072 */
2073 ath9k_ps_restore(sc);
2074 }
2075
528f0c6b 2076 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2077
8feceb67
VT		 2078 /*
2079 * As a temporary workaround, assign seq# here; this will likely need
2080 * to be cleaned up to work better with Beacon transmission and virtual
2081 * BSSes.
2082 */
2083 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2084 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2085 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2086 sc->tx.seq_no += 0x10;
8feceb67 2087 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2088 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2089 }
f078f209 2090
8feceb67
VT		 2091 /* Add the padding after the header if this is not already done */
2092 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2093 if (hdrlen & 3) {
2094 padsize = hdrlen % 4;
2095 if (skb_headroom(skb) < padsize)
2096 return -1;
2097 skb_push(skb, padsize);
2098 memmove(skb->data, skb->data + padsize, hdrlen);
2099 }
2100
528f0c6b
S		 2101 /* Check if a tx queue is available */
2102
2103 txctl.txq = ath_test_get_txq(sc, skb);
2104 if (!txctl.txq)
2105 goto exit;
2106
04bd4638 2107 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2108
c52f33d0 2109 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2110 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2111 goto exit;
8feceb67
VT		 2112 }
2113
528f0c6b
S		 2114 return 0;
2115exit:
2116 dev_kfree_skb_any(skb);
8feceb67 2117 return 0;
f078f209
LR		 2118}
2119
8feceb67 2120static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2121{
bce048d7
JM		 2122 struct ath_wiphy *aphy = hw->priv;
2123 struct ath_softc *sc = aphy->sc;
f078f209 2124
4c483817
S		 2125 mutex_lock(&sc->mutex);
2126
9580a222
JM		 2127 aphy->state = ATH_WIPHY_INACTIVE;
2128
c94dbff7
LR		 2129 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2130 cancel_delayed_work_sync(&sc->tx_complete_work);
2131
2132 if (!sc->num_sec_wiphy) {
2133 cancel_delayed_work_sync(&sc->wiphy_work);
2134 cancel_work_sync(&sc->chan_work);
2135 }
2136
9c84b797 2137 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2138 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
4c483817 2139 mutex_unlock(&sc->mutex);
9c84b797
S		 2140 return;
2141 }
8feceb67 2142
9580a222
JM		 2143 if (ath9k_wiphy_started(sc)) {
2144 mutex_unlock(&sc->mutex);
2145 return; /* another wiphy still in use */
2146 }
2147
1773912b
VT		 2148 if (sc->sc_flags & SC_OP_BTCOEX_ENABLED) {
2149 ath9k_hw_btcoex_disable(sc->sc_ah);
2150 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
2151 ath_btcoex_timer_pause(sc, &sc->btcoex_info);
2152 }
2153
ff37e337
S		 2154 /* make sure h/w will not generate any interrupt
2155 * before setting the invalid flag. */
2156 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2157
2158 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2159 ath_drain_all_txq(sc, false);
ff37e337
S		 2160 ath_stoprecv(sc);
2161 ath9k_hw_phy_disable(sc->sc_ah);
2162 } else
b77f483f 2163 sc->rx.rxlink = NULL;
ff37e337 2164
ff37e337
S		 2165 /* disable HAL and put h/w to sleep */
2166 ath9k_hw_disable(sc->sc_ah);
93b1b37f 2167 ath9k_hw_configpcipowersave(sc->sc_ah, 1, 1);
eff563cf 2168 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2169
2170 sc->sc_flags |= SC_OP_INVALID;
500c064d 2171
141b38b6
S		 2172 mutex_unlock(&sc->mutex);
2173
04bd4638 2174 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2175}
2176
8feceb67
VT		 2177static int ath9k_add_interface(struct ieee80211_hw *hw,
2178 struct ieee80211_if_init_conf *conf)
f078f209 2179{
bce048d7
JM		 2180 struct ath_wiphy *aphy = hw->priv;
2181 struct ath_softc *sc = aphy->sc;
17d7904d 2182 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2183 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2184 int ret = 0;
8feceb67 2185
141b38b6
S		 2186 mutex_lock(&sc->mutex);
2187
8ca21f01
JM		 2188 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2189 sc->nvifs > 0) {
2190 ret = -ENOBUFS;
2191 goto out;
2192 }
2193
8feceb67 2194 switch (conf->type) {
05c914fe 2195 case NL80211_IFTYPE_STATION:
d97809db 2196 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2197 break;
05c914fe 2198 case NL80211_IFTYPE_ADHOC:
05c914fe 2199 case NL80211_IFTYPE_AP:
9cb5412b 2200 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2201 if (sc->nbcnvifs >= ATH_BCBUF) {
2202 ret = -ENOBUFS;
2203 goto out;
2204 }
9cb5412b 2205 ic_opmode = conf->type;
f078f209
LR		 2206 break;
2207 default:
2208 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2209 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2210 ret = -EOPNOTSUPP;
2211 goto out;
f078f209
LR		 2212 }
2213
17d7904d 2214 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2215
17d7904d 2216 /* Set the VIF opmode */
5640b08e
S		 2217 avp->av_opmode = ic_opmode;
2218 avp->av_bslot = -1;
2219
2c3db3d5 2220 sc->nvifs++;
8ca21f01
JM		 2221
2222 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2223 ath9k_set_bssid_mask(hw);
2224
2c3db3d5
JM		 2225 if (sc->nvifs > 1)
2226 goto out; /* skip global settings for secondary vif */
2227
b238e90e 2228 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2229 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2230 sc->sc_flags |= SC_OP_TSF_RESET;
2231 }
5640b08e 2232
5640b08e 2233 /* Set the device opmode */
2660b81a 2234 sc->sc_ah->opmode = ic_opmode;
5640b08e 2235
4e30ffa2
VN		 2236 /*
2237 * Enable MIB interrupts when there are hardware phy counters.
2238 * Note we only do this (at the moment) for station mode.
2239 */
4af9cf4f 2240 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2241 (conf->type == NL80211_IFTYPE_ADHOC) ||
2242 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2243 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2244 sc->imask |= ATH9K_INT_TSFOOR;
2245 }
2246
17d7904d 2247 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2248
f38faa31
SB		 2249 if (conf->type == NL80211_IFTYPE_AP ||
2250 conf->type == NL80211_IFTYPE_ADHOC ||
2251 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2252 ath_start_ani(sc);
6f255425 2253
2c3db3d5 2254out:
141b38b6 2255 mutex_unlock(&sc->mutex);
2c3db3d5 2256 return ret;
f078f209
LR		 2257}
2258
8feceb67
VT		 2259static void ath9k_remove_interface(struct ieee80211_hw *hw,
2260 struct ieee80211_if_init_conf *conf)
f078f209 2261{
bce048d7
JM		 2262 struct ath_wiphy *aphy = hw->priv;
2263 struct ath_softc *sc = aphy->sc;
17d7904d 2264 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2265 int i;
f078f209 2266
04bd4638 2267 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2268
141b38b6
S		 2269 mutex_lock(&sc->mutex);
2270
6f255425 2271 /* Stop ANI */
17d7904d 2272 del_timer_sync(&sc->ani.timer);
580f0b8a 2273
8feceb67 2274 /* Reclaim beacon resources */
9cb5412b
PE		 2275 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2276 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2277 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2278 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2279 ath_beacon_return(sc, avp);
580f0b8a 2280 }
f078f209 2281
8feceb67 2282 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2283
2c3db3d5
JM		 2284 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2285 if (sc->beacon.bslot[i] == conf->vif) {
2286 printk(KERN_DEBUG "%s: vif had allocated beacon "
2287 "slot\n", __func__);
2288 sc->beacon.bslot[i] = NULL;
c52f33d0 2289 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2290 }
2291 }
2292
17d7904d 2293 sc->nvifs--;
141b38b6
S		 2294
2295 mutex_unlock(&sc->mutex);
f078f209
LR		 2296}
2297
e8975581 2298static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2299{
bce048d7
JM		 2300 struct ath_wiphy *aphy = hw->priv;
2301 struct ath_softc *sc = aphy->sc;
e8975581 2302 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2303 struct ath_hw *ah = sc->sc_ah;
64839170 2304 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2305
aa33de09 2306 mutex_lock(&sc->mutex);
141b38b6 2307
64839170
LR		 2308 /* Leave this as the first check */
2309 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2310
2311 spin_lock_bh(&sc->wiphy_lock);
2312 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2313 spin_unlock_bh(&sc->wiphy_lock);
2314
2315 if (conf->flags & IEEE80211_CONF_IDLE){
2316 if (all_wiphys_idle)
2317 disable_radio = true;
2318 }
2319 else if (all_wiphys_idle) {
2320 ath_radio_enable(sc);
2321 DPRINTF(sc, ATH_DBG_CONFIG,
2322 "not-idle: enabling radio\n");
2323 }
2324 }
2325
3cbb5dd7
VN		 2326 if (changed & IEEE80211_CONF_CHANGE_PS) {
2327 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2328 if (!(ah->caps.hw_caps &
2329 ATH9K_HW_CAP_AUTOSLEEP)) {
2330 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2331 sc->imask |= ATH9K_INT_TIM_TIMER;
2332 ath9k_hw_set_interrupts(sc->sc_ah,
2333 sc->imask);
2334 }
2335 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2336 }
96148326 2337 sc->ps_enabled = true;
3cbb5dd7 2338 } else {
96148326 2339 sc->ps_enabled = false;
3cbb5dd7 2340 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2341 if (!(ah->caps.hw_caps &
2342 ATH9K_HW_CAP_AUTOSLEEP)) {
2343 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2344 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2345 SC_OP_WAIT_FOR_CAB |
2346 SC_OP_WAIT_FOR_PSPOLL_DATA |
2347 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2348 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2349 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2350 ath9k_hw_set_interrupts(sc->sc_ah,
2351 sc->imask);
2352 }
3cbb5dd7
VN		 2353 }
2354 }
2355 }
2356
4797938c 2357 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2358 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2359 int pos = curchan->hw_value;
ae5eb026 2360
0e2dedf9
JM		 2361 aphy->chan_idx = pos;
2362 aphy->chan_is_ht = conf_is_ht(conf);
2363
8089cc47
JM		 2364 if (aphy->state == ATH_WIPHY_SCAN ||
2365 aphy->state == ATH_WIPHY_ACTIVE)
2366 ath9k_wiphy_pause_all_forced(sc, aphy);
2367 else {
2368 /*
2369 * Do not change operational channel based on a paused
2370 * wiphy changes.
2371 */
2372 goto skip_chan_change;
2373 }
0e2dedf9 2374
04bd4638
S		 2375 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2376 curchan->center_freq);
f078f209 2377
5f8e077c 2378 /* XXX: remove me eventualy */
0e2dedf9 2379 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2380
ecf70441 2381 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2382
0e2dedf9 2383 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2384 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2385 mutex_unlock(&sc->mutex);
e11602b7
S		 2386 return -EINVAL;
2387 }
094d05dc 2388 }
f078f209 2389
8089cc47 2390skip_chan_change:
5c020dc6 2391 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2392 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2393
64839170
LR		 2394 if (disable_radio) {
2395 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2396 ath_radio_disable(sc);
2397 }
2398
aa33de09 2399 mutex_unlock(&sc->mutex);
141b38b6 2400
f078f209
LR		 2401 return 0;
2402}
2403
8feceb67
VT		 2404#define SUPPORTED_FILTERS \
2405 (FIF_PROMISC_IN_BSS | \
2406 FIF_ALLMULTI | \
2407 FIF_CONTROL | \
af6a3fc7 2408 FIF_PSPOLL | \
8feceb67
VT		 2409 FIF_OTHER_BSS | \
2410 FIF_BCN_PRBRESP_PROMISC | \
2411 FIF_FCSFAIL)
c83be688 2412
8feceb67
VT		 2413/* FIXME: sc->sc_full_reset ? */
2414static void ath9k_configure_filter(struct ieee80211_hw *hw,
2415 unsigned int changed_flags,
2416 unsigned int *total_flags,
3ac64bee 2417 u64 multicast)
8feceb67 2418{
bce048d7
JM		 2419 struct ath_wiphy *aphy = hw->priv;
2420 struct ath_softc *sc = aphy->sc;
8feceb67 2421 u32 rfilt;
f078f209 2422
8feceb67
VT		 2423 changed_flags &= SUPPORTED_FILTERS;
2424 *total_flags &= SUPPORTED_FILTERS;
f078f209 2425
b77f483f 2426 sc->rx.rxfilter = *total_flags;
aa68aeaa 2427 ath9k_ps_wakeup(sc);
8feceb67
VT		 2428 rfilt = ath_calcrxfilter(sc);
2429 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2430 ath9k_ps_restore(sc);
f078f209 2431
7ea310be 2432 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2433}
f078f209 2434
8feceb67
VT		 2435static void ath9k_sta_notify(struct ieee80211_hw *hw,
2436 struct ieee80211_vif *vif,
2437 enum sta_notify_cmd cmd,
17741cdc 2438 struct ieee80211_sta *sta)
8feceb67 2439{
bce048d7
JM		 2440 struct ath_wiphy *aphy = hw->priv;
2441 struct ath_softc *sc = aphy->sc;
f078f209 2442
8feceb67
VT		 2443 switch (cmd) {
2444 case STA_NOTIFY_ADD:
5640b08e 2445 ath_node_attach(sc, sta);
8feceb67
VT		 2446 break;
2447 case STA_NOTIFY_REMOVE:
b5aa9bf9 2448 ath_node_detach(sc, sta);
8feceb67
VT		 2449 break;
2450 default:
2451 break;
2452 }
f078f209
LR		 2453}
2454
141b38b6 2455static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2456 const struct ieee80211_tx_queue_params *params)
f078f209 2457{
bce048d7
JM		 2458 struct ath_wiphy *aphy = hw->priv;
2459 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2460 struct ath9k_tx_queue_info qi;
2461 int ret = 0, qnum;
f078f209 2462
8feceb67
VT		 2463 if (queue >= WME_NUM_AC)
2464 return 0;
f078f209 2465
141b38b6
S		 2466 mutex_lock(&sc->mutex);
2467
1ffb0610
S		 2468 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2469
8feceb67
VT		 2470 qi.tqi_aifs = params->aifs;
2471 qi.tqi_cwmin = params->cw_min;
2472 qi.tqi_cwmax = params->cw_max;
2473 qi.tqi_burstTime = params->txop;
2474 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2475
8feceb67 2476 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2477 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2478 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2479 queue, qnum, params->aifs, params->cw_min,
2480 params->cw_max, params->txop);
f078f209 2481
8feceb67
VT		 2482 ret = ath_txq_update(sc, qnum, &qi);
2483 if (ret)
04bd4638 2484 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2485
141b38b6
S		 2486 mutex_unlock(&sc->mutex);
2487
8feceb67
VT		 2488 return ret;
2489}
f078f209 2490
8feceb67
VT		 2491static int ath9k_set_key(struct ieee80211_hw *hw,
2492 enum set_key_cmd cmd,
dc822b5d
JB		 2493 struct ieee80211_vif *vif,
2494 struct ieee80211_sta *sta,
8feceb67
VT		 2495 struct ieee80211_key_conf *key)
2496{
bce048d7
JM		 2497 struct ath_wiphy *aphy = hw->priv;
2498 struct ath_softc *sc = aphy->sc;
8feceb67 2499 int ret = 0;
f078f209 2500
b3bd89ce
JM		 2501 if (modparam_nohwcrypt)
2502 return -ENOSPC;
2503
141b38b6 2504 mutex_lock(&sc->mutex);
3cbb5dd7 2505 ath9k_ps_wakeup(sc);
d8baa939 2506 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2507
8feceb67
VT		 2508 switch (cmd) {
2509 case SET_KEY:
3f53dd64 2510 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2511 if (ret >= 0) {
2512 key->hw_key_idx = ret;
8feceb67
VT		 2513 /* push IV and Michael MIC generation to stack */
2514 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2515 if (key->alg == ALG_TKIP)
2516 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2517 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2518 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2519 ret = 0;
8feceb67
VT		 2520 }
2521 break;
2522 case DISABLE_KEY:
2523 ath_key_delete(sc, key);
8feceb67
VT		 2524 break;
2525 default:
2526 ret = -EINVAL;
2527 }
f078f209 2528
3cbb5dd7 2529 ath9k_ps_restore(sc);
141b38b6
S		 2530 mutex_unlock(&sc->mutex);
2531
8feceb67
VT		 2532 return ret;
2533}
f078f209 2534
8feceb67
VT		 2535static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2536 struct ieee80211_vif *vif,
2537 struct ieee80211_bss_conf *bss_conf,
2538 u32 changed)
2539{
bce048d7
JM		 2540 struct ath_wiphy *aphy = hw->priv;
2541 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2542 struct ath_hw *ah = sc->sc_ah;
2543 struct ath_vif *avp = (void *)vif->drv_priv;
2544 u32 rfilt = 0;
2545 int error, i;
f078f209 2546
141b38b6
S		 2547 mutex_lock(&sc->mutex);
2548
2d0ddec5
JB		 2549 /*
2550 * TODO: Need to decide which hw opmode to use for
2551 * multi-interface cases
2552 * XXX: This belongs into add_interface!
2553 */
2554 if (vif->type == NL80211_IFTYPE_AP &&
2555 ah->opmode != NL80211_IFTYPE_AP) {
2556 ah->opmode = NL80211_IFTYPE_STATION;
2557 ath9k_hw_setopmode(ah);
2558 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2559 sc->curaid = 0;
2560 ath9k_hw_write_associd(sc);
2561 /* Request full reset to get hw opmode changed properly */
2562 sc->sc_flags |= SC_OP_FULL_RESET;
2563 }
2564
2565 if ((changed & BSS_CHANGED_BSSID) &&
2566 !is_zero_ether_addr(bss_conf->bssid)) {
2567 switch (vif->type) {
2568 case NL80211_IFTYPE_STATION:
2569 case NL80211_IFTYPE_ADHOC:
2570 case NL80211_IFTYPE_MESH_POINT:
2571 /* Set BSSID */
2572 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2573 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2574 sc->curaid = 0;
2575 ath9k_hw_write_associd(sc);
2576
2577 /* Set aggregation protection mode parameters */
2578 sc->config.ath_aggr_prot = 0;
2579
2580 DPRINTF(sc, ATH_DBG_CONFIG,
2581 "RX filter 0x%x bssid %pM aid 0x%x\n",
2582 rfilt, sc->curbssid, sc->curaid);
2583
2584 /* need to reconfigure the beacon */
2585 sc->sc_flags &= ~SC_OP_BEACONS ;
2586
2587 break;
2588 default:
2589 break;
2590 }
2591 }
2592
2593 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2594 (vif->type == NL80211_IFTYPE_AP) ||
2595 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2596 if ((changed & BSS_CHANGED_BEACON) ||
2597 (changed & BSS_CHANGED_BEACON_ENABLED &&
2598 bss_conf->enable_beacon)) {
2599 /*
2600 * Allocate and setup the beacon frame.
2601 *
2602 * Stop any previous beacon DMA. This may be
2603 * necessary, for example, when an ibss merge
2604 * causes reconfiguration; we may be called
2605 * with beacon transmission active.
2606 */
2607 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2608
2609 error = ath_beacon_alloc(aphy, vif);
2610 if (!error)
2611 ath_beacon_config(sc, vif);
2612 }
2613 }
2614
2615 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2616 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2617 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2618 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2619 ath9k_hw_keysetmac(sc->sc_ah,
2620 (u16)i,
2621 sc->curbssid);
2622 }
2623
2624 /* Only legacy IBSS for now */
2625 if (vif->type == NL80211_IFTYPE_ADHOC)
2626 ath_update_chainmask(sc, 0);
2627
8feceb67 2628 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2629 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2630 bss_conf->use_short_preamble);
2631 if (bss_conf->use_short_preamble)
2632 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2633 else
2634 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2635 }
f078f209 2636
8feceb67 2637 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2638 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2639 bss_conf->use_cts_prot);
2640 if (bss_conf->use_cts_prot &&
2641 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2642 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2643 else
2644 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2645 }
f078f209 2646
8feceb67 2647 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2648 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2649 bss_conf->assoc);
5640b08e 2650 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2651 }
141b38b6 2652
57c4d7b4
JB		 2653 /*
2654 * The HW TSF has to be reset when the beacon interval changes.
2655 * We set the flag here, and ath_beacon_config_ap() would take this
2656 * into account when it gets called through the subsequent
2657 * config_interface() call - with IFCC_BEACON in the changed field.
2658 */
2659
2660 if (changed & BSS_CHANGED_BEACON_INT) {
2661 sc->sc_flags |= SC_OP_TSF_RESET;
2662 sc->beacon_interval = bss_conf->beacon_int;
2663 }
2664
141b38b6 2665 mutex_unlock(&sc->mutex);
8feceb67 2666}
f078f209 2667
8feceb67
VT		 2668static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2669{
2670 u64 tsf;
bce048d7
JM		 2671 struct ath_wiphy *aphy = hw->priv;
2672 struct ath_softc *sc = aphy->sc;
f078f209 2673
141b38b6
S		 2674 mutex_lock(&sc->mutex);
2675 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2676 mutex_unlock(&sc->mutex);
f078f209 2677
8feceb67
VT		 2678 return tsf;
2679}
f078f209 2680
3b5d665b
AF		 2681static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2682{
bce048d7
JM		 2683 struct ath_wiphy *aphy = hw->priv;
2684 struct ath_softc *sc = aphy->sc;
3b5d665b 2685
141b38b6
S		 2686 mutex_lock(&sc->mutex);
2687 ath9k_hw_settsf64(sc->sc_ah, tsf);
2688 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2689}
2690
8feceb67
VT		 2691static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2692{
bce048d7
JM		 2693 struct ath_wiphy *aphy = hw->priv;
2694 struct ath_softc *sc = aphy->sc;
c83be688 2695
141b38b6
S		 2696 mutex_lock(&sc->mutex);
2697 ath9k_hw_reset_tsf(sc->sc_ah);
2698 mutex_unlock(&sc->mutex);
8feceb67 2699}
f078f209 2700
8feceb67 2701static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2702 enum ieee80211_ampdu_mlme_action action,
2703 struct ieee80211_sta *sta,
2704 u16 tid, u16 *ssn)
8feceb67 2705{
bce048d7
JM		 2706 struct ath_wiphy *aphy = hw->priv;
2707 struct ath_softc *sc = aphy->sc;
8feceb67 2708 int ret = 0;
f078f209 2709
8feceb67
VT		 2710 switch (action) {
2711 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2712 if (!(sc->sc_flags & SC_OP_RXAGGR))
2713 ret = -ENOTSUPP;
8feceb67
VT		 2714 break;
2715 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2716 break;
2717 case IEEE80211_AMPDU_TX_START:
f83da965
S		 2718 ath_tx_aggr_start(sc, sta, tid, ssn);
2719 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2720 break;
2721 case IEEE80211_AMPDU_TX_STOP:
f83da965 2722 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 2723 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2724 break;
b1720231 2725 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2726 ath_tx_aggr_resume(sc, sta, tid);
2727 break;
8feceb67 2728 default:
04bd4638 2729 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2730 }
2731
2732 return ret;
f078f209
LR		 2733}
2734
0c98de65
S		 2735static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2736{
bce048d7
JM		 2737 struct ath_wiphy *aphy = hw->priv;
2738 struct ath_softc *sc = aphy->sc;
0c98de65 2739
3d832611 2740 mutex_lock(&sc->mutex);
8089cc47
JM		 2741 if (ath9k_wiphy_scanning(sc)) {
2742 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2743 "same time\n");
2744 /*
2745 * Do not allow the concurrent scanning state for now. This
2746 * could be improved with scanning control moved into ath9k.
2747 */
3d832611 2748 mutex_unlock(&sc->mutex);
8089cc47
JM		 2749 return;
2750 }
2751
2752 aphy->state = ATH_WIPHY_SCAN;
2753 ath9k_wiphy_pause_all_forced(sc, aphy);
2754
e5f0921a 2755 spin_lock_bh(&sc->ani_lock);
0c98de65 2756 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2757 spin_unlock_bh(&sc->ani_lock);
3d832611 2758 mutex_unlock(&sc->mutex);
0c98de65
S		 2759}
2760
2761static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2762{
bce048d7
JM		 2763 struct ath_wiphy *aphy = hw->priv;
2764 struct ath_softc *sc = aphy->sc;
0c98de65 2765
3d832611 2766 mutex_lock(&sc->mutex);
e5f0921a 2767 spin_lock_bh(&sc->ani_lock);
8089cc47 2768 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2769 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2770 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2771 spin_unlock_bh(&sc->ani_lock);
d0bec342 2772 ath_beacon_config(sc, NULL);
3d832611 2773 mutex_unlock(&sc->mutex);
0c98de65
S		 2774}
2775
6baff7f9 2776struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2777 .tx = ath9k_tx,
2778 .start = ath9k_start,
2779 .stop = ath9k_stop,
2780 .add_interface = ath9k_add_interface,
2781 .remove_interface = ath9k_remove_interface,
2782 .config = ath9k_config,
8feceb67 2783 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2784 .sta_notify = ath9k_sta_notify,
2785 .conf_tx = ath9k_conf_tx,
8feceb67 2786 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2787 .set_key = ath9k_set_key,
8feceb67 2788 .get_tsf = ath9k_get_tsf,
3b5d665b 2789 .set_tsf = ath9k_set_tsf,
8feceb67 2790 .reset_tsf = ath9k_reset_tsf,
4233df6b 2791 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2792 .sw_scan_start = ath9k_sw_scan_start,
2793 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2794 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2795};
2796
392dff83
BP		 2797static struct {
2798 u32 version;
2799 const char * name;
2800} ath_mac_bb_names[] = {
2801 { AR_SREV_VERSION_5416_PCI, "5416" },
2802 { AR_SREV_VERSION_5416_PCIE, "5418" },
2803 { AR_SREV_VERSION_9100, "9100" },
2804 { AR_SREV_VERSION_9160, "9160" },
2805 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 2806 { AR_SREV_VERSION_9285, "9285" },
2807 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 2808};
2809
2810static struct {
2811 u16 version;
2812 const char * name;
2813} ath_rf_names[] = {
2814 { 0, "5133" },
2815 { AR_RAD5133_SREV_MAJOR, "5133" },
2816 { AR_RAD5122_SREV_MAJOR, "5122" },
2817 { AR_RAD2133_SREV_MAJOR, "2133" },
2818 { AR_RAD2122_SREV_MAJOR, "2122" }
2819};
2820
2821/*
2822 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2823 */
6baff7f9 2824const char *
392dff83
BP		 2825ath_mac_bb_name(u32 mac_bb_version)
2826{
2827 int i;
2828
2829 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2830 if (ath_mac_bb_names[i].version == mac_bb_version) {
2831 return ath_mac_bb_names[i].name;
2832 }
2833 }
2834
2835 return "????";
2836}
2837
2838/*
2839 * Return the RF name. "????" is returned if the RF is unknown.
2840 */
6baff7f9 2841const char *
392dff83
BP		 2842ath_rf_name(u16 rf_version)
2843{
2844 int i;
2845
2846 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2847 if (ath_rf_names[i].version == rf_version) {
2848 return ath_rf_names[i].name;
2849 }
2850 }
2851
2852 return "????";
2853}
2854
6baff7f9 2855static int __init ath9k_init(void)
f078f209 2856{
ca8a8560
VT		 2857 int error;
2858
ca8a8560
VT		 2859 /* Register rate control algorithm */
2860 error = ath_rate_control_register();
2861 if (error != 0) {
2862 printk(KERN_ERR
b51bb3cd
LR		 2863 "ath9k: Unable to register rate control "
2864 "algorithm: %d\n",
ca8a8560 2865 error);
6baff7f9 2866 goto err_out;
ca8a8560
VT		 2867 }
2868
19d8bc22
GJ		 2869 error = ath9k_debug_create_root();
2870 if (error) {
2871 printk(KERN_ERR
2872 "ath9k: Unable to create debugfs root: %d\n",
2873 error);
2874 goto err_rate_unregister;
2875 }
2876
6baff7f9
GJ		 2877 error = ath_pci_init();
2878 if (error < 0) {
f078f209 2879 printk(KERN_ERR
b51bb3cd 2880 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2881 error = -ENODEV;
19d8bc22 2882 goto err_remove_root;
f078f209
LR		 2883 }
2884
09329d37
GJ		 2885 error = ath_ahb_init();
2886 if (error < 0) {
2887 error = -ENODEV;
2888 goto err_pci_exit;
2889 }
2890
f078f209 2891 return 0;
6baff7f9 2892
09329d37
GJ		 2893 err_pci_exit:
2894 ath_pci_exit();
2895
19d8bc22
GJ		 2896 err_remove_root:
2897 ath9k_debug_remove_root();
6baff7f9
GJ		 2898 err_rate_unregister:
2899 ath_rate_control_unregister();
2900 err_out:
2901 return error;
f078f209 2902}
6baff7f9 2903module_init(ath9k_init);
f078f209 2904
6baff7f9 2905static void __exit ath9k_exit(void)
f078f209 2906{
09329d37 2907 ath_ahb_exit();
6baff7f9 2908 ath_pci_exit();
19d8bc22 2909 ath9k_debug_remove_root();
ca8a8560 2910 ath_rate_control_unregister();
04bd4638 2911 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2912}
6baff7f9 2913module_exit(ath9k_exit);
kernel source for telekom puls (alcatel/mediatek)