Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ce111bad LR |
21 | static void ath_cache_conf_rate(struct ath_softc *sc, |
22 | struct ieee80211_conf *conf) | |
ff37e337 | 23 | { |
030bb495 LR |
24 | switch (conf->channel->band) { |
25 | case IEEE80211_BAND_2GHZ: | |
26 | if (conf_is_ht20(conf)) | |
545750d3 | 27 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; |
030bb495 | 28 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 29 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; |
030bb495 | 30 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 31 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; |
96742256 | 32 | else |
545750d3 | 33 | sc->cur_rate_mode = ATH9K_MODE_11G; |
030bb495 LR |
34 | break; |
35 | case IEEE80211_BAND_5GHZ: | |
36 | if (conf_is_ht20(conf)) | |
545750d3 | 37 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; |
030bb495 | 38 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 39 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; |
030bb495 | 40 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 41 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; |
030bb495 | 42 | else |
545750d3 | 43 | sc->cur_rate_mode = ATH9K_MODE_11A; |
030bb495 LR |
44 | break; |
45 | default: | |
ce111bad | 46 | BUG_ON(1); |
030bb495 LR |
47 | break; |
48 | } | |
ff37e337 S |
49 | } |
50 | ||
51 | static void ath_update_txpow(struct ath_softc *sc) | |
52 | { | |
cbe61d8a | 53 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 54 | |
17d7904d S |
55 | if (sc->curtxpow != sc->config.txpowlimit) { |
56 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 | 57 | /* read back in case value is clamped */ |
9cc3271f | 58 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
ff37e337 S |
59 | } |
60 | } | |
61 | ||
62 | static u8 parse_mpdudensity(u8 mpdudensity) | |
63 | { | |
64 | /* | |
65 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
66 | * 0 for no restriction | |
67 | * 1 for 1/4 us | |
68 | * 2 for 1/2 us | |
69 | * 3 for 1 us | |
70 | * 4 for 2 us | |
71 | * 5 for 4 us | |
72 | * 6 for 8 us | |
73 | * 7 for 16 us | |
74 | */ | |
75 | switch (mpdudensity) { | |
76 | case 0: | |
77 | return 0; | |
78 | case 1: | |
79 | case 2: | |
80 | case 3: | |
81 | /* Our lower layer calculations limit our precision to | |
82 | 1 microsecond */ | |
83 | return 1; | |
84 | case 4: | |
85 | return 2; | |
86 | case 5: | |
87 | return 4; | |
88 | case 6: | |
89 | return 8; | |
90 | case 7: | |
91 | return 16; | |
92 | default: | |
93 | return 0; | |
94 | } | |
95 | } | |
96 | ||
82880a7c VT |
97 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
98 | struct ieee80211_hw *hw) | |
99 | { | |
100 | struct ieee80211_channel *curchan = hw->conf.channel; | |
101 | struct ath9k_channel *channel; | |
102 | u8 chan_idx; | |
103 | ||
104 | chan_idx = curchan->hw_value; | |
105 | channel = &sc->sc_ah->channels[chan_idx]; | |
106 | ath9k_update_ichannel(sc, hw, channel); | |
107 | return channel; | |
108 | } | |
109 | ||
55624204 | 110 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
111 | { |
112 | unsigned long flags; | |
113 | bool ret; | |
114 | ||
9ecdef4b LR |
115 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
116 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
117 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
118 | |
119 | return ret; | |
120 | } | |
121 | ||
a91d75ae LR |
122 | void ath9k_ps_wakeup(struct ath_softc *sc) |
123 | { | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
127 | if (++sc->ps_usecount != 1) | |
128 | goto unlock; | |
129 | ||
9ecdef4b | 130 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
131 | |
132 | unlock: | |
133 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
134 | } | |
135 | ||
136 | void ath9k_ps_restore(struct ath_softc *sc) | |
137 | { | |
138 | unsigned long flags; | |
139 | ||
140 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
141 | if (--sc->ps_usecount != 0) | |
142 | goto unlock; | |
143 | ||
1dbfd9d4 VN |
144 | if (sc->ps_idle) |
145 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
146 | else if (sc->ps_enabled && | |
147 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
148 | PS_WAIT_FOR_CAB | |
149 | PS_WAIT_FOR_PSPOLL_DATA | | |
150 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 151 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
152 | |
153 | unlock: | |
154 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
155 | } | |
156 | ||
5ee08656 FF |
157 | static void ath_start_ani(struct ath_common *common) |
158 | { | |
159 | struct ath_hw *ah = common->ah; | |
160 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
161 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
162 | ||
163 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
164 | return; | |
165 | ||
166 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
167 | return; | |
168 | ||
169 | common->ani.longcal_timer = timestamp; | |
170 | common->ani.shortcal_timer = timestamp; | |
171 | common->ani.checkani_timer = timestamp; | |
172 | ||
173 | mod_timer(&common->ani.timer, | |
174 | jiffies + | |
175 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
176 | } | |
177 | ||
ff37e337 S |
178 | /* |
179 | * Set/change channels. If the channel is really being changed, it's done | |
180 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
181 | * DMA, then restart stuff. | |
182 | */ | |
0e2dedf9 JM |
183 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
184 | struct ath9k_channel *hchan) | |
ff37e337 | 185 | { |
20bd2a09 | 186 | struct ath_wiphy *aphy = hw->priv; |
cbe61d8a | 187 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 188 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 189 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 190 | bool fastcc = true, stopped; |
ae8d2858 | 191 | struct ieee80211_channel *channel = hw->conf.channel; |
20bd2a09 | 192 | struct ath9k_hw_cal_data *caldata = NULL; |
ae8d2858 | 193 | int r; |
ff37e337 S |
194 | |
195 | if (sc->sc_flags & SC_OP_INVALID) | |
196 | return -EIO; | |
197 | ||
5ee08656 FF |
198 | del_timer_sync(&common->ani.timer); |
199 | cancel_work_sync(&sc->paprd_work); | |
200 | cancel_work_sync(&sc->hw_check_work); | |
201 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
202 | ||
3cbb5dd7 VN |
203 | ath9k_ps_wakeup(sc); |
204 | ||
c0d7c7af LR |
205 | /* |
206 | * This is only performed if the channel settings have | |
207 | * actually changed. | |
208 | * | |
209 | * To switch channels clear any pending DMA operations; | |
210 | * wait long enough for the RX fifo to drain, reset the | |
211 | * hardware at the new frequency, and then re-enable | |
212 | * the relevant bits of the h/w. | |
213 | */ | |
214 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 215 | ath_drain_all_txq(sc, false); |
c0d7c7af | 216 | stopped = ath_stoprecv(sc); |
ff37e337 | 217 | |
c0d7c7af LR |
218 | /* XXX: do not flush receive queue here. We don't want |
219 | * to flush data frames already in queue because of | |
220 | * changing channel. */ | |
ff37e337 | 221 | |
5ee08656 | 222 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) |
c0d7c7af LR |
223 | fastcc = false; |
224 | ||
20bd2a09 FF |
225 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
226 | caldata = &aphy->caldata; | |
227 | ||
c46917bb | 228 | ath_print(common, ATH_DBG_CONFIG, |
1e51b2ff | 229 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", |
c46917bb | 230 | sc->sc_ah->curchan->channel, |
1e51b2ff LR |
231 | channel->center_freq, conf_is_ht40(conf), |
232 | fastcc); | |
ff37e337 | 233 | |
c0d7c7af LR |
234 | spin_lock_bh(&sc->sc_resetlock); |
235 | ||
20bd2a09 | 236 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
c0d7c7af | 237 | if (r) { |
c46917bb | 238 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 239 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
240 | "reset status %d\n", |
241 | channel->center_freq, r); | |
c0d7c7af | 242 | spin_unlock_bh(&sc->sc_resetlock); |
3989279c | 243 | goto ps_restore; |
ff37e337 | 244 | } |
c0d7c7af LR |
245 | spin_unlock_bh(&sc->sc_resetlock); |
246 | ||
c0d7c7af | 247 | if (ath_startrecv(sc) != 0) { |
c46917bb LR |
248 | ath_print(common, ATH_DBG_FATAL, |
249 | "Unable to restart recv logic\n"); | |
3989279c GJ |
250 | r = -EIO; |
251 | goto ps_restore; | |
c0d7c7af LR |
252 | } |
253 | ||
254 | ath_cache_conf_rate(sc, &hw->conf); | |
255 | ath_update_txpow(sc); | |
3069168c | 256 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c | 257 | |
48a6a468 LR |
258 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { |
259 | ath_beacon_config(sc, NULL); | |
5ee08656 | 260 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
48a6a468 | 261 | ath_start_ani(common); |
5ee08656 FF |
262 | } |
263 | ||
3989279c | 264 | ps_restore: |
3cbb5dd7 | 265 | ath9k_ps_restore(sc); |
3989279c | 266 | return r; |
ff37e337 S |
267 | } |
268 | ||
9f42c2b6 FF |
269 | static void ath_paprd_activate(struct ath_softc *sc) |
270 | { | |
271 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 272 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 273 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
274 | int chain; |
275 | ||
20bd2a09 | 276 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
277 | return; |
278 | ||
279 | ath9k_ps_wakeup(sc); | |
ddfef792 | 280 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 281 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 282 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
283 | continue; |
284 | ||
20bd2a09 | 285 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
286 | } |
287 | ||
288 | ar9003_paprd_enable(ah, true); | |
289 | ath9k_ps_restore(sc); | |
290 | } | |
291 | ||
292 | void ath_paprd_calibrate(struct work_struct *work) | |
293 | { | |
294 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
295 | struct ieee80211_hw *hw = sc->hw; | |
296 | struct ath_hw *ah = sc->sc_ah; | |
297 | struct ieee80211_hdr *hdr; | |
298 | struct sk_buff *skb = NULL; | |
299 | struct ieee80211_tx_info *tx_info; | |
300 | int band = hw->conf.channel->band; | |
301 | struct ieee80211_supported_band *sband = &sc->sbands[band]; | |
302 | struct ath_tx_control txctl; | |
20bd2a09 | 303 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 304 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
305 | int qnum, ftype; |
306 | int chain_ok = 0; | |
307 | int chain; | |
308 | int len = 1800; | |
309 | int time_left; | |
310 | int i; | |
311 | ||
20bd2a09 FF |
312 | if (!caldata) |
313 | return; | |
314 | ||
9f42c2b6 FF |
315 | skb = alloc_skb(len, GFP_KERNEL); |
316 | if (!skb) | |
317 | return; | |
318 | ||
319 | tx_info = IEEE80211_SKB_CB(skb); | |
320 | ||
321 | skb_put(skb, len); | |
322 | memset(skb->data, 0, len); | |
323 | hdr = (struct ieee80211_hdr *)skb->data; | |
324 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
325 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 326 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
327 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
328 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
329 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
330 | ||
331 | memset(&txctl, 0, sizeof(txctl)); | |
332 | qnum = sc->tx.hwq_map[WME_AC_BE]; | |
333 | txctl.txq = &sc->tx.txq[qnum]; | |
334 | ||
47399f1a | 335 | ath9k_ps_wakeup(sc); |
9f42c2b6 FF |
336 | ar9003_paprd_init_table(ah); |
337 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | |
9094537c | 338 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
339 | continue; |
340 | ||
341 | chain_ok = 0; | |
342 | memset(tx_info, 0, sizeof(*tx_info)); | |
343 | tx_info->band = band; | |
344 | ||
345 | for (i = 0; i < 4; i++) { | |
346 | tx_info->control.rates[i].idx = sband->n_bitrates - 1; | |
347 | tx_info->control.rates[i].count = 6; | |
348 | } | |
349 | ||
350 | init_completion(&sc->paprd_complete); | |
351 | ar9003_paprd_setup_gain_table(ah, chain); | |
352 | txctl.paprd = BIT(chain); | |
353 | if (ath_tx_start(hw, skb, &txctl) != 0) | |
354 | break; | |
355 | ||
356 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
ca369eb4 | 357 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); |
9f42c2b6 FF |
358 | if (!time_left) { |
359 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | |
360 | "Timeout waiting for paprd training on " | |
361 | "TX chain %d\n", | |
362 | chain); | |
ca369eb4 | 363 | goto fail_paprd; |
9f42c2b6 FF |
364 | } |
365 | ||
366 | if (!ar9003_paprd_is_done(ah)) | |
367 | break; | |
368 | ||
20bd2a09 | 369 | if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) |
9f42c2b6 FF |
370 | break; |
371 | ||
372 | chain_ok = 1; | |
373 | } | |
374 | kfree_skb(skb); | |
375 | ||
376 | if (chain_ok) { | |
20bd2a09 | 377 | caldata->paprd_done = true; |
9f42c2b6 FF |
378 | ath_paprd_activate(sc); |
379 | } | |
380 | ||
ca369eb4 | 381 | fail_paprd: |
9f42c2b6 FF |
382 | ath9k_ps_restore(sc); |
383 | } | |
384 | ||
ff37e337 S |
385 | /* |
386 | * This routine performs the periodic noise floor calibration function | |
387 | * that is used to adjust and optimize the chip performance. This | |
388 | * takes environmental changes (location, temperature) into account. | |
389 | * When the task is complete, it reschedules itself depending on the | |
390 | * appropriate interval that was calculated. | |
391 | */ | |
55624204 | 392 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 393 | { |
20977d3e S |
394 | struct ath_softc *sc = (struct ath_softc *)data; |
395 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 396 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
397 | bool longcal = false; |
398 | bool shortcal = false; | |
399 | bool aniflag = false; | |
400 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e FF |
401 | u32 cal_interval, short_cal_interval, long_cal_interval; |
402 | ||
403 | if (ah->caldata && ah->caldata->nfcal_interference) | |
404 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
405 | else | |
406 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 407 | |
20977d3e S |
408 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
409 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 410 | |
1ffc1c61 JM |
411 | /* Only calibrate if awake */ |
412 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
413 | goto set_timer; | |
414 | ||
415 | ath9k_ps_wakeup(sc); | |
416 | ||
ff37e337 | 417 | /* Long calibration runs independently of short calibration. */ |
6044474e | 418 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 419 | longcal = true; |
c46917bb | 420 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 421 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
422 | } |
423 | ||
17d7904d | 424 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
425 | if (!common->ani.caldone) { |
426 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 427 | shortcal = true; |
c46917bb LR |
428 | ath_print(common, ATH_DBG_ANI, |
429 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
430 | common->ani.shortcal_timer = timestamp; |
431 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
432 | } |
433 | } else { | |
3d536acf | 434 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 435 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
436 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
437 | if (common->ani.caldone) | |
438 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
439 | } |
440 | } | |
441 | ||
442 | /* Verify whether we must check ANI */ | |
e36b27af LR |
443 | if ((timestamp - common->ani.checkani_timer) >= |
444 | ah->config.ani_poll_interval) { | |
ff37e337 | 445 | aniflag = true; |
3d536acf | 446 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
447 | } |
448 | ||
449 | /* Skip all processing if there's nothing to do. */ | |
450 | if (longcal || shortcal || aniflag) { | |
451 | /* Call ANI routine if necessary */ | |
452 | if (aniflag) | |
22e66a4c | 453 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
454 | |
455 | /* Perform calibration if necessary */ | |
456 | if (longcal || shortcal) { | |
3d536acf | 457 | common->ani.caldone = |
43c27613 LR |
458 | ath9k_hw_calibrate(ah, |
459 | ah->curchan, | |
460 | common->rx_chainmask, | |
461 | longcal); | |
ff37e337 S |
462 | } |
463 | } | |
464 | ||
1ffc1c61 JM |
465 | ath9k_ps_restore(sc); |
466 | ||
20977d3e | 467 | set_timer: |
ff37e337 S |
468 | /* |
469 | * Set timer interval based on previous results. | |
470 | * The interval must be the shortest necessary to satisfy ANI, | |
471 | * short calibration and long calibration. | |
472 | */ | |
aac9207e | 473 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 474 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
475 | cal_interval = min(cal_interval, |
476 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 477 | if (!common->ani.caldone) |
20977d3e | 478 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 479 | |
3d536acf | 480 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
481 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
482 | if (!ah->caldata->paprd_done) | |
9f42c2b6 FF |
483 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
484 | else | |
485 | ath_paprd_activate(sc); | |
486 | } | |
ff37e337 S |
487 | } |
488 | ||
489 | /* | |
490 | * Update tx/rx chainmask. For legacy association, | |
491 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
492 | * the chainmask configuration, for bt coexistence, use |
493 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 494 | */ |
0e2dedf9 | 495 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 496 | { |
af03abec | 497 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 498 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 499 | |
5ee08656 | 500 | if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht || |
766ec4a9 | 501 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
502 | common->tx_chainmask = ah->caps.tx_chainmask; |
503 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 504 | } else { |
43c27613 LR |
505 | common->tx_chainmask = 1; |
506 | common->rx_chainmask = 1; | |
ff37e337 S |
507 | } |
508 | ||
43c27613 | 509 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 510 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
511 | common->tx_chainmask, |
512 | common->rx_chainmask); | |
ff37e337 S |
513 | } |
514 | ||
515 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
516 | { | |
517 | struct ath_node *an; | |
518 | ||
519 | an = (struct ath_node *)sta->drv_priv; | |
520 | ||
87792efc | 521 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 522 | ath_tx_node_init(sc, an); |
9e98ac65 | 523 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
524 | sta->ht_cap.ampdu_factor); |
525 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 526 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 527 | } |
ff37e337 S |
528 | } |
529 | ||
530 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
531 | { | |
532 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
533 | ||
534 | if (sc->sc_flags & SC_OP_TXAGGR) | |
535 | ath_tx_node_cleanup(sc, an); | |
536 | } | |
537 | ||
347809fc FF |
538 | void ath_hw_check(struct work_struct *work) |
539 | { | |
540 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
541 | int i; | |
542 | ||
543 | ath9k_ps_wakeup(sc); | |
544 | ||
545 | for (i = 0; i < 3; i++) { | |
546 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
547 | goto out; | |
548 | ||
549 | msleep(1); | |
550 | } | |
551 | ath_reset(sc, false); | |
552 | ||
553 | out: | |
554 | ath9k_ps_restore(sc); | |
555 | } | |
556 | ||
55624204 | 557 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
558 | { |
559 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 560 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 561 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 562 | |
17d7904d | 563 | u32 status = sc->intrstatus; |
b5c80475 | 564 | u32 rxmask; |
ff37e337 | 565 | |
153e080d VT |
566 | ath9k_ps_wakeup(sc); |
567 | ||
347809fc | 568 | if (status & ATH9K_INT_FATAL) { |
ff37e337 | 569 | ath_reset(sc, false); |
153e080d | 570 | ath9k_ps_restore(sc); |
ff37e337 | 571 | return; |
063d8be3 | 572 | } |
ff37e337 | 573 | |
347809fc FF |
574 | if (!ath9k_hw_check_alive(ah)) |
575 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); | |
576 | ||
b5c80475 FF |
577 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
578 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
579 | ATH9K_INT_RXORN); | |
580 | else | |
581 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
582 | ||
583 | if (status & rxmask) { | |
063d8be3 | 584 | spin_lock_bh(&sc->rx.rxflushlock); |
b5c80475 FF |
585 | |
586 | /* Check for high priority Rx first */ | |
587 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
588 | (status & ATH9K_INT_RXHP)) | |
589 | ath_rx_tasklet(sc, 0, true); | |
590 | ||
591 | ath_rx_tasklet(sc, 0, false); | |
063d8be3 | 592 | spin_unlock_bh(&sc->rx.rxflushlock); |
ff37e337 S |
593 | } |
594 | ||
e5003249 VT |
595 | if (status & ATH9K_INT_TX) { |
596 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
597 | ath_tx_edma_tasklet(sc); | |
598 | else | |
599 | ath_tx_tasklet(sc); | |
600 | } | |
063d8be3 | 601 | |
96148326 | 602 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
603 | /* |
604 | * TSF sync does not look correct; remain awake to sync with | |
605 | * the next Beacon. | |
606 | */ | |
c46917bb LR |
607 | ath_print(common, ATH_DBG_PS, |
608 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 609 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
610 | } |
611 | ||
766ec4a9 | 612 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
613 | if (status & ATH9K_INT_GENTIMER) |
614 | ath_gen_timer_isr(sc->sc_ah); | |
615 | ||
ff37e337 | 616 | /* re-enable hardware interrupt */ |
3069168c | 617 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 618 | ath9k_ps_restore(sc); |
ff37e337 S |
619 | } |
620 | ||
6baff7f9 | 621 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 622 | { |
063d8be3 S |
623 | #define SCHED_INTR ( \ |
624 | ATH9K_INT_FATAL | \ | |
625 | ATH9K_INT_RXORN | \ | |
626 | ATH9K_INT_RXEOL | \ | |
627 | ATH9K_INT_RX | \ | |
b5c80475 FF |
628 | ATH9K_INT_RXLP | \ |
629 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
630 | ATH9K_INT_TX | \ |
631 | ATH9K_INT_BMISS | \ | |
632 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
633 | ATH9K_INT_TSFOOR | \ |
634 | ATH9K_INT_GENTIMER) | |
063d8be3 | 635 | |
ff37e337 | 636 | struct ath_softc *sc = dev; |
cbe61d8a | 637 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
638 | enum ath9k_int status; |
639 | bool sched = false; | |
640 | ||
063d8be3 S |
641 | /* |
642 | * The hardware is not ready/present, don't | |
643 | * touch anything. Note this can happen early | |
644 | * on if the IRQ is shared. | |
645 | */ | |
646 | if (sc->sc_flags & SC_OP_INVALID) | |
647 | return IRQ_NONE; | |
ff37e337 | 648 | |
063d8be3 S |
649 | |
650 | /* shared irq, not for us */ | |
651 | ||
153e080d | 652 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 653 | return IRQ_NONE; |
063d8be3 S |
654 | |
655 | /* | |
656 | * Figure out the reason(s) for the interrupt. Note | |
657 | * that the hal returns a pseudo-ISR that may include | |
658 | * bits we haven't explicitly enabled so we mask the | |
659 | * value to insure we only process bits we requested. | |
660 | */ | |
661 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 662 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 663 | |
063d8be3 S |
664 | /* |
665 | * If there are no status bits set, then this interrupt was not | |
666 | * for me (should have been caught above). | |
667 | */ | |
153e080d | 668 | if (!status) |
063d8be3 | 669 | return IRQ_NONE; |
ff37e337 | 670 | |
063d8be3 S |
671 | /* Cache the status */ |
672 | sc->intrstatus = status; | |
673 | ||
674 | if (status & SCHED_INTR) | |
675 | sched = true; | |
676 | ||
677 | /* | |
678 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
679 | * chip immediately. | |
680 | */ | |
b5c80475 FF |
681 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
682 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
683 | goto chip_reset; |
684 | ||
08578b8f LR |
685 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
686 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
687 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
688 | goto chip_reset; | |
689 | } | |
690 | ||
063d8be3 S |
691 | if (status & ATH9K_INT_SWBA) |
692 | tasklet_schedule(&sc->bcon_tasklet); | |
693 | ||
694 | if (status & ATH9K_INT_TXURN) | |
695 | ath9k_hw_updatetxtriglevel(ah, true); | |
696 | ||
b5c80475 FF |
697 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
698 | if (status & ATH9K_INT_RXEOL) { | |
699 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
700 | ath9k_hw_set_interrupts(ah, ah->imask); | |
701 | } | |
702 | } | |
703 | ||
063d8be3 | 704 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 705 | /* |
063d8be3 S |
706 | * Disable interrupts until we service the MIB |
707 | * interrupt; otherwise it will continue to | |
708 | * fire. | |
ff37e337 | 709 | */ |
063d8be3 S |
710 | ath9k_hw_set_interrupts(ah, 0); |
711 | /* | |
712 | * Let the hal handle the event. We assume | |
713 | * it will clear whatever condition caused | |
714 | * the interrupt. | |
715 | */ | |
bfc472bb | 716 | ath9k_hw_proc_mib_event(ah); |
3069168c | 717 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 718 | } |
ff37e337 | 719 | |
153e080d VT |
720 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
721 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
722 | /* Clear RxAbort bit so that we can |
723 | * receive frames */ | |
9ecdef4b | 724 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 725 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 726 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 727 | } |
063d8be3 S |
728 | |
729 | chip_reset: | |
ff37e337 | 730 | |
817e11de S |
731 | ath_debug_stat_interrupt(sc, status); |
732 | ||
ff37e337 S |
733 | if (sched) { |
734 | /* turn off every interrupt except SWBA */ | |
3069168c | 735 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
736 | tasklet_schedule(&sc->intr_tq); |
737 | } | |
738 | ||
739 | return IRQ_HANDLED; | |
063d8be3 S |
740 | |
741 | #undef SCHED_INTR | |
ff37e337 S |
742 | } |
743 | ||
f078f209 | 744 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 745 | struct ieee80211_channel *chan, |
094d05dc | 746 | enum nl80211_channel_type channel_type) |
f078f209 LR |
747 | { |
748 | u32 chanmode = 0; | |
f078f209 LR |
749 | |
750 | switch (chan->band) { | |
751 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
752 | switch(channel_type) { |
753 | case NL80211_CHAN_NO_HT: | |
754 | case NL80211_CHAN_HT20: | |
f078f209 | 755 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
756 | break; |
757 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 758 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
759 | break; |
760 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 761 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
762 | break; |
763 | } | |
f078f209 LR |
764 | break; |
765 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
766 | switch(channel_type) { |
767 | case NL80211_CHAN_NO_HT: | |
768 | case NL80211_CHAN_HT20: | |
f078f209 | 769 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
770 | break; |
771 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 772 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
773 | break; |
774 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 775 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
776 | break; |
777 | } | |
f078f209 LR |
778 | break; |
779 | default: | |
780 | break; | |
781 | } | |
782 | ||
783 | return chanmode; | |
784 | } | |
785 | ||
8feceb67 | 786 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 787 | struct ieee80211_vif *vif, |
8feceb67 | 788 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 789 | { |
f2b2143e | 790 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 791 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 792 | |
8feceb67 | 793 | if (bss_conf->assoc) { |
c46917bb LR |
794 | ath_print(common, ATH_DBG_CONFIG, |
795 | "Bss Info ASSOC %d, bssid: %pM\n", | |
796 | bss_conf->aid, common->curbssid); | |
f078f209 | 797 | |
8feceb67 | 798 | /* New association, store aid */ |
1510718d | 799 | common->curaid = bss_conf->aid; |
f2b2143e | 800 | ath9k_hw_write_associd(ah); |
2664f201 SB |
801 | |
802 | /* | |
803 | * Request a re-configuration of Beacon related timers | |
804 | * on the receipt of the first Beacon frame (i.e., | |
805 | * after time sync with the AP). | |
806 | */ | |
1b04b930 | 807 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 808 | |
8feceb67 | 809 | /* Configure the beacon */ |
2c3db3d5 | 810 | ath_beacon_config(sc, vif); |
f078f209 | 811 | |
8feceb67 | 812 | /* Reset rssi stats */ |
22e66a4c | 813 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 814 | |
6c3118e2 | 815 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 816 | ath_start_ani(common); |
8feceb67 | 817 | } else { |
c46917bb | 818 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 819 | common->curaid = 0; |
f38faa31 | 820 | /* Stop ANI */ |
6c3118e2 | 821 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 822 | del_timer_sync(&common->ani.timer); |
f078f209 | 823 | } |
8feceb67 | 824 | } |
f078f209 | 825 | |
68a89116 | 826 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 827 | { |
cbe61d8a | 828 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 829 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 830 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 831 | int r; |
500c064d | 832 | |
3cbb5dd7 | 833 | ath9k_ps_wakeup(sc); |
93b1b37f | 834 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 835 | |
159cd468 VT |
836 | if (!ah->curchan) |
837 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
838 | ||
d2f5b3a6 | 839 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 840 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 841 | if (r) { |
c46917bb | 842 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 843 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
844 | "reset status %d\n", |
845 | channel->center_freq, r); | |
500c064d VT |
846 | } |
847 | spin_unlock_bh(&sc->sc_resetlock); | |
848 | ||
849 | ath_update_txpow(sc); | |
850 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
851 | ath_print(common, ATH_DBG_FATAL, |
852 | "Unable to restart recv logic\n"); | |
500c064d VT |
853 | return; |
854 | } | |
855 | ||
856 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 857 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
858 | |
859 | /* Re-Enable interrupts */ | |
3069168c | 860 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
861 | |
862 | /* Enable LED */ | |
08fc5c1b | 863 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 864 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 865 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 866 | |
68a89116 | 867 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 868 | ath9k_ps_restore(sc); |
500c064d VT |
869 | } |
870 | ||
68a89116 | 871 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 872 | { |
cbe61d8a | 873 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 874 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 875 | int r; |
500c064d | 876 | |
3cbb5dd7 | 877 | ath9k_ps_wakeup(sc); |
68a89116 | 878 | ieee80211_stop_queues(hw); |
500c064d | 879 | |
982723df VN |
880 | /* |
881 | * Keep the LED on when the radio is disabled | |
882 | * during idle unassociated state. | |
883 | */ | |
884 | if (!sc->ps_idle) { | |
885 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
886 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
887 | } | |
500c064d VT |
888 | |
889 | /* Disable interrupts */ | |
890 | ath9k_hw_set_interrupts(ah, 0); | |
891 | ||
043a0405 | 892 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
893 | ath_stoprecv(sc); /* turn off frame recv */ |
894 | ath_flushrecv(sc); /* flush recv queue */ | |
895 | ||
159cd468 | 896 | if (!ah->curchan) |
68a89116 | 897 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 898 | |
500c064d | 899 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 900 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 901 | if (r) { |
c46917bb | 902 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 903 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
904 | "reset status %d\n", |
905 | channel->center_freq, r); | |
500c064d VT |
906 | } |
907 | spin_unlock_bh(&sc->sc_resetlock); | |
908 | ||
909 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 910 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 911 | ath9k_ps_restore(sc); |
9ecdef4b | 912 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
913 | } |
914 | ||
ff37e337 S |
915 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
916 | { | |
cbe61d8a | 917 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 918 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 919 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 920 | int r; |
ff37e337 | 921 | |
2ab81d4a S |
922 | /* Stop ANI */ |
923 | del_timer_sync(&common->ani.timer); | |
924 | ||
cc9c378a S |
925 | ieee80211_stop_queues(hw); |
926 | ||
ff37e337 | 927 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 928 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
929 | ath_stoprecv(sc); |
930 | ath_flushrecv(sc); | |
931 | ||
932 | spin_lock_bh(&sc->sc_resetlock); | |
20bd2a09 | 933 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); |
ae8d2858 | 934 | if (r) |
c46917bb LR |
935 | ath_print(common, ATH_DBG_FATAL, |
936 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
937 | spin_unlock_bh(&sc->sc_resetlock); |
938 | ||
939 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
940 | ath_print(common, ATH_DBG_FATAL, |
941 | "Unable to start recv logic\n"); | |
ff37e337 S |
942 | |
943 | /* | |
944 | * We may be doing a reset in response to a request | |
945 | * that changes the channel so update any state that | |
946 | * might change as a result. | |
947 | */ | |
ce111bad | 948 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
949 | |
950 | ath_update_txpow(sc); | |
951 | ||
52b8ac92 | 952 | if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) |
2c3db3d5 | 953 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 954 | |
3069168c | 955 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
956 | |
957 | if (retry_tx) { | |
958 | int i; | |
959 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
960 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
961 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
962 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
963 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
964 | } |
965 | } | |
966 | } | |
967 | ||
cc9c378a S |
968 | ieee80211_wake_queues(hw); |
969 | ||
2ab81d4a S |
970 | /* Start ANI */ |
971 | ath_start_ani(common); | |
972 | ||
ae8d2858 | 973 | return r; |
ff37e337 S |
974 | } |
975 | ||
ebe297c3 | 976 | static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
ff37e337 S |
977 | { |
978 | int qnum; | |
979 | ||
980 | switch (queue) { | |
981 | case 0: | |
1d2231e2 | 982 | qnum = sc->tx.hwq_map[WME_AC_VO]; |
ff37e337 S |
983 | break; |
984 | case 1: | |
1d2231e2 | 985 | qnum = sc->tx.hwq_map[WME_AC_VI]; |
ff37e337 S |
986 | break; |
987 | case 2: | |
1d2231e2 | 988 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
989 | break; |
990 | case 3: | |
1d2231e2 | 991 | qnum = sc->tx.hwq_map[WME_AC_BK]; |
ff37e337 S |
992 | break; |
993 | default: | |
1d2231e2 | 994 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
995 | break; |
996 | } | |
997 | ||
998 | return qnum; | |
999 | } | |
1000 | ||
1001 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1002 | { | |
1003 | int qnum; | |
1004 | ||
1005 | switch (queue) { | |
1d2231e2 | 1006 | case WME_AC_VO: |
ff37e337 S |
1007 | qnum = 0; |
1008 | break; | |
1d2231e2 | 1009 | case WME_AC_VI: |
ff37e337 S |
1010 | qnum = 1; |
1011 | break; | |
1d2231e2 | 1012 | case WME_AC_BE: |
ff37e337 S |
1013 | qnum = 2; |
1014 | break; | |
1d2231e2 | 1015 | case WME_AC_BK: |
ff37e337 S |
1016 | qnum = 3; |
1017 | break; | |
1018 | default: | |
1019 | qnum = -1; | |
1020 | break; | |
1021 | } | |
1022 | ||
1023 | return qnum; | |
1024 | } | |
1025 | ||
5f8e077c LR |
1026 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1027 | * this redundant data */ | |
0e2dedf9 JM |
1028 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1029 | struct ath9k_channel *ichan) | |
5f8e077c | 1030 | { |
5f8e077c LR |
1031 | struct ieee80211_channel *chan = hw->conf.channel; |
1032 | struct ieee80211_conf *conf = &hw->conf; | |
1033 | ||
1034 | ichan->channel = chan->center_freq; | |
1035 | ichan->chan = chan; | |
1036 | ||
1037 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1038 | ichan->chanmode = CHANNEL_G; | |
8813262e | 1039 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
1040 | } else { |
1041 | ichan->chanmode = CHANNEL_A; | |
1042 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1043 | } | |
1044 | ||
25c56eec | 1045 | if (conf_is_ht(conf)) |
5f8e077c LR |
1046 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
1047 | conf->channel_type); | |
5f8e077c LR |
1048 | } |
1049 | ||
ff37e337 S |
1050 | /**********************/ |
1051 | /* mac80211 callbacks */ | |
1052 | /**********************/ | |
1053 | ||
8feceb67 | 1054 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1055 | { |
bce048d7 JM |
1056 | struct ath_wiphy *aphy = hw->priv; |
1057 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1058 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1059 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1060 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1061 | struct ath9k_channel *init_channel; |
82880a7c | 1062 | int r; |
f078f209 | 1063 | |
c46917bb LR |
1064 | ath_print(common, ATH_DBG_CONFIG, |
1065 | "Starting driver with initial channel: %d MHz\n", | |
1066 | curchan->center_freq); | |
f078f209 | 1067 | |
141b38b6 S |
1068 | mutex_lock(&sc->mutex); |
1069 | ||
9580a222 JM |
1070 | if (ath9k_wiphy_started(sc)) { |
1071 | if (sc->chan_idx == curchan->hw_value) { | |
1072 | /* | |
1073 | * Already on the operational channel, the new wiphy | |
1074 | * can be marked active. | |
1075 | */ | |
1076 | aphy->state = ATH_WIPHY_ACTIVE; | |
1077 | ieee80211_wake_queues(hw); | |
1078 | } else { | |
1079 | /* | |
1080 | * Another wiphy is on another channel, start the new | |
1081 | * wiphy in paused state. | |
1082 | */ | |
1083 | aphy->state = ATH_WIPHY_PAUSED; | |
1084 | ieee80211_stop_queues(hw); | |
1085 | } | |
1086 | mutex_unlock(&sc->mutex); | |
1087 | return 0; | |
1088 | } | |
1089 | aphy->state = ATH_WIPHY_ACTIVE; | |
1090 | ||
8feceb67 | 1091 | /* setup initial channel */ |
f078f209 | 1092 | |
82880a7c | 1093 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1094 | |
82880a7c | 1095 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1096 | |
1097 | /* Reset SERDES registers */ | |
af03abec | 1098 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1099 | |
1100 | /* | |
1101 | * The basic interface to setting the hardware in a good | |
1102 | * state is ``reset''. On return the hardware is known to | |
1103 | * be powered up and with interrupts disabled. This must | |
1104 | * be followed by initialization of the appropriate bits | |
1105 | * and then setup of the interrupt mask. | |
1106 | */ | |
1107 | spin_lock_bh(&sc->sc_resetlock); | |
20bd2a09 | 1108 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1109 | if (r) { |
c46917bb LR |
1110 | ath_print(common, ATH_DBG_FATAL, |
1111 | "Unable to reset hardware; reset status %d " | |
1112 | "(freq %u MHz)\n", r, | |
1113 | curchan->center_freq); | |
ff37e337 | 1114 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 1115 | goto mutex_unlock; |
ff37e337 S |
1116 | } |
1117 | spin_unlock_bh(&sc->sc_resetlock); | |
1118 | ||
1119 | /* | |
1120 | * This is needed only to setup initial state | |
1121 | * but it's best done after a reset. | |
1122 | */ | |
1123 | ath_update_txpow(sc); | |
8feceb67 | 1124 | |
ff37e337 S |
1125 | /* |
1126 | * Setup the hardware after reset: | |
1127 | * The receive engine is set going. | |
1128 | * Frame transmit is handled entirely | |
1129 | * in the frame output path; there's nothing to do | |
1130 | * here except setup the interrupt mask. | |
1131 | */ | |
1132 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
1133 | ath_print(common, ATH_DBG_FATAL, |
1134 | "Unable to start recv logic\n"); | |
141b38b6 S |
1135 | r = -EIO; |
1136 | goto mutex_unlock; | |
f078f209 | 1137 | } |
8feceb67 | 1138 | |
ff37e337 | 1139 | /* Setup our intr mask. */ |
b5c80475 FF |
1140 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1141 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1142 | ATH9K_INT_GLOBAL; | |
1143 | ||
1144 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1145 | ah->imask |= ATH9K_INT_RXHP | |
1146 | ATH9K_INT_RXLP | | |
1147 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1148 | else |
1149 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1150 | |
364734fa | 1151 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1152 | |
af03abec | 1153 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1154 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1155 | |
ce111bad | 1156 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1157 | |
1158 | sc->sc_flags &= ~SC_OP_INVALID; | |
1159 | ||
1160 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1161 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1162 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1163 | |
bce048d7 | 1164 | ieee80211_wake_queues(hw); |
ff37e337 | 1165 | |
42935eca | 1166 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1167 | |
766ec4a9 LR |
1168 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1169 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1170 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1171 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1172 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1173 | |
5bb12791 LR |
1174 | if (common->bus_ops->bt_coex_prep) |
1175 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1176 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1177 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1178 | } |
1179 | ||
141b38b6 S |
1180 | mutex_unlock: |
1181 | mutex_unlock(&sc->mutex); | |
1182 | ||
ae8d2858 | 1183 | return r; |
f078f209 LR |
1184 | } |
1185 | ||
8feceb67 VT |
1186 | static int ath9k_tx(struct ieee80211_hw *hw, |
1187 | struct sk_buff *skb) | |
f078f209 | 1188 | { |
528f0c6b | 1189 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1190 | struct ath_wiphy *aphy = hw->priv; |
1191 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1192 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1193 | struct ath_tx_control txctl; |
1bc14880 BP |
1194 | int padpos, padsize; |
1195 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
84642d6b | 1196 | int qnum; |
528f0c6b | 1197 | |
8089cc47 | 1198 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1199 | ath_print(common, ATH_DBG_XMIT, |
1200 | "ath9k: %s: TX in unexpected wiphy state " | |
1201 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1202 | goto exit; |
1203 | } | |
1204 | ||
96148326 | 1205 | if (sc->ps_enabled) { |
dc8c4585 JM |
1206 | /* |
1207 | * mac80211 does not set PM field for normal data frames, so we | |
1208 | * need to update that based on the current PS mode. | |
1209 | */ | |
1210 | if (ieee80211_is_data(hdr->frame_control) && | |
1211 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1212 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1213 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1214 | "while in PS mode\n"); | |
dc8c4585 JM |
1215 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1216 | } | |
1217 | } | |
1218 | ||
9a23f9ca JM |
1219 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1220 | /* | |
1221 | * We are using PS-Poll and mac80211 can request TX while in | |
1222 | * power save mode. Need to wake up hardware for the TX to be | |
1223 | * completed and if needed, also for RX of buffered frames. | |
1224 | */ | |
9a23f9ca | 1225 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1226 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1227 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1228 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
c46917bb LR |
1229 | ath_print(common, ATH_DBG_PS, |
1230 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1231 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1232 | } else { |
c46917bb LR |
1233 | ath_print(common, ATH_DBG_PS, |
1234 | "Wake up to complete TX\n"); | |
1b04b930 | 1235 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1236 | } |
1237 | /* | |
1238 | * The actual restore operation will happen only after | |
1239 | * the sc_flags bit is cleared. We are just dropping | |
1240 | * the ps_usecount here. | |
1241 | */ | |
1242 | ath9k_ps_restore(sc); | |
1243 | } | |
1244 | ||
528f0c6b | 1245 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1246 | |
8feceb67 VT |
1247 | /* |
1248 | * As a temporary workaround, assign seq# here; this will likely need | |
1249 | * to be cleaned up to work better with Beacon transmission and virtual | |
1250 | * BSSes. | |
1251 | */ | |
1252 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1253 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1254 | sc->tx.seq_no += 0x10; |
8feceb67 | 1255 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1256 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1257 | } |
f078f209 | 1258 | |
8feceb67 | 1259 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1260 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1261 | padsize = padpos & 3; | |
1262 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1263 | if (skb_headroom(skb) < padsize) |
1264 | return -1; | |
1265 | skb_push(skb, padsize); | |
1bc14880 | 1266 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1267 | } |
1268 | ||
84642d6b FF |
1269 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1270 | txctl.txq = &sc->tx.txq[qnum]; | |
528f0c6b | 1271 | |
c46917bb | 1272 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1273 | |
c52f33d0 | 1274 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1275 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1276 | goto exit; |
8feceb67 VT |
1277 | } |
1278 | ||
528f0c6b S |
1279 | return 0; |
1280 | exit: | |
1281 | dev_kfree_skb_any(skb); | |
8feceb67 | 1282 | return 0; |
f078f209 LR |
1283 | } |
1284 | ||
8feceb67 | 1285 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1286 | { |
bce048d7 JM |
1287 | struct ath_wiphy *aphy = hw->priv; |
1288 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1289 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1290 | struct ath_common *common = ath9k_hw_common(ah); |
447a42c2 | 1291 | int i; |
f078f209 | 1292 | |
4c483817 S |
1293 | mutex_lock(&sc->mutex); |
1294 | ||
9580a222 JM |
1295 | aphy->state = ATH_WIPHY_INACTIVE; |
1296 | ||
9a75c2ff VN |
1297 | if (led_blink) |
1298 | cancel_delayed_work_sync(&sc->ath_led_blink_work); | |
1299 | ||
c94dbff7 | 1300 | cancel_delayed_work_sync(&sc->tx_complete_work); |
9f42c2b6 | 1301 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1302 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1303 | |
447a42c2 RM |
1304 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1305 | if (sc->sec_wiphy[i]) | |
1306 | break; | |
1307 | } | |
1308 | ||
1309 | if (i == sc->num_sec_wiphy) { | |
c94dbff7 LR |
1310 | cancel_delayed_work_sync(&sc->wiphy_work); |
1311 | cancel_work_sync(&sc->chan_work); | |
1312 | } | |
1313 | ||
9c84b797 | 1314 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1315 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1316 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1317 | return; |
1318 | } | |
8feceb67 | 1319 | |
9580a222 JM |
1320 | if (ath9k_wiphy_started(sc)) { |
1321 | mutex_unlock(&sc->mutex); | |
1322 | return; /* another wiphy still in use */ | |
1323 | } | |
1324 | ||
3867cf6a S |
1325 | /* Ensure HW is awake when we try to shut it down. */ |
1326 | ath9k_ps_wakeup(sc); | |
1327 | ||
766ec4a9 | 1328 | if (ah->btcoex_hw.enabled) { |
af03abec | 1329 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1330 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1331 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1332 | } |
1333 | ||
ff37e337 S |
1334 | /* make sure h/w will not generate any interrupt |
1335 | * before setting the invalid flag. */ | |
af03abec | 1336 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
1337 | |
1338 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1339 | ath_drain_all_txq(sc, false); |
ff37e337 | 1340 | ath_stoprecv(sc); |
af03abec | 1341 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1342 | } else |
b77f483f | 1343 | sc->rx.rxlink = NULL; |
ff37e337 | 1344 | |
ff37e337 | 1345 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1346 | ath9k_hw_disable(ah); |
1347 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1348 | ath9k_ps_restore(sc); |
1349 | ||
1350 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1351 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1352 | |
1353 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1354 | |
141b38b6 S |
1355 | mutex_unlock(&sc->mutex); |
1356 | ||
c46917bb | 1357 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1358 | } |
1359 | ||
8feceb67 | 1360 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1361 | struct ieee80211_vif *vif) |
f078f209 | 1362 | { |
bce048d7 JM |
1363 | struct ath_wiphy *aphy = hw->priv; |
1364 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1365 | struct ath_hw *ah = sc->sc_ah; |
1366 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1367 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1368 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1369 | int ret = 0; |
8feceb67 | 1370 | |
141b38b6 S |
1371 | mutex_lock(&sc->mutex); |
1372 | ||
1ed32e4f | 1373 | switch (vif->type) { |
05c914fe | 1374 | case NL80211_IFTYPE_STATION: |
d97809db | 1375 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1376 | break; |
e51f3eff BJ |
1377 | case NL80211_IFTYPE_WDS: |
1378 | ic_opmode = NL80211_IFTYPE_WDS; | |
1379 | break; | |
05c914fe | 1380 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1381 | case NL80211_IFTYPE_AP: |
9cb5412b | 1382 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1383 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1384 | ret = -ENOBUFS; | |
1385 | goto out; | |
1386 | } | |
1ed32e4f | 1387 | ic_opmode = vif->type; |
f078f209 LR |
1388 | break; |
1389 | default: | |
c46917bb | 1390 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1391 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1392 | ret = -EOPNOTSUPP; |
1393 | goto out; | |
f078f209 LR |
1394 | } |
1395 | ||
c46917bb LR |
1396 | ath_print(common, ATH_DBG_CONFIG, |
1397 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1398 | |
17d7904d | 1399 | /* Set the VIF opmode */ |
5640b08e S |
1400 | avp->av_opmode = ic_opmode; |
1401 | avp->av_bslot = -1; | |
1402 | ||
2c3db3d5 | 1403 | sc->nvifs++; |
8ca21f01 | 1404 | |
364734fa | 1405 | ath9k_set_bssid_mask(hw, vif); |
8ca21f01 | 1406 | |
2c3db3d5 JM |
1407 | if (sc->nvifs > 1) |
1408 | goto out; /* skip global settings for secondary vif */ | |
1409 | ||
b238e90e | 1410 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1411 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1412 | sc->sc_flags |= SC_OP_TSF_RESET; |
1413 | } | |
5640b08e | 1414 | |
5640b08e | 1415 | /* Set the device opmode */ |
3069168c | 1416 | ah->opmode = ic_opmode; |
5640b08e | 1417 | |
4e30ffa2 VN |
1418 | /* |
1419 | * Enable MIB interrupts when there are hardware phy counters. | |
1420 | * Note we only do this (at the moment) for station mode. | |
1421 | */ | |
1ed32e4f JB |
1422 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1423 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1424 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1425 | if (ah->config.enable_ani) |
1426 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1427 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1428 | } |
1429 | ||
3069168c | 1430 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1431 | |
1ed32e4f JB |
1432 | if (vif->type == NL80211_IFTYPE_AP || |
1433 | vif->type == NL80211_IFTYPE_ADHOC || | |
6c3118e2 VT |
1434 | vif->type == NL80211_IFTYPE_MONITOR) { |
1435 | sc->sc_flags |= SC_OP_ANI_RUN; | |
3d536acf | 1436 | ath_start_ani(common); |
6c3118e2 | 1437 | } |
6f255425 | 1438 | |
2c3db3d5 | 1439 | out: |
141b38b6 | 1440 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1441 | return ret; |
f078f209 LR |
1442 | } |
1443 | ||
8feceb67 | 1444 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1445 | struct ieee80211_vif *vif) |
f078f209 | 1446 | { |
bce048d7 JM |
1447 | struct ath_wiphy *aphy = hw->priv; |
1448 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1449 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1450 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1451 | int i; |
f078f209 | 1452 | |
c46917bb | 1453 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1454 | |
141b38b6 S |
1455 | mutex_lock(&sc->mutex); |
1456 | ||
6f255425 | 1457 | /* Stop ANI */ |
6c3118e2 | 1458 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 1459 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1460 | |
8feceb67 | 1461 | /* Reclaim beacon resources */ |
9cb5412b PE |
1462 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1463 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1464 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1465 | ath9k_ps_wakeup(sc); |
b77f483f | 1466 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1467 | ath9k_ps_restore(sc); |
580f0b8a | 1468 | } |
f078f209 | 1469 | |
74401773 | 1470 | ath_beacon_return(sc, avp); |
8feceb67 | 1471 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1472 | |
2c3db3d5 | 1473 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1474 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1475 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1476 | "slot\n", __func__); | |
1477 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1478 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1479 | } |
1480 | } | |
1481 | ||
17d7904d | 1482 | sc->nvifs--; |
141b38b6 S |
1483 | |
1484 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1485 | } |
1486 | ||
fbab7390 | 1487 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1488 | { |
3069168c PR |
1489 | struct ath_hw *ah = sc->sc_ah; |
1490 | ||
3f7c5c10 | 1491 | sc->ps_enabled = true; |
3069168c PR |
1492 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1493 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1494 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1495 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1496 | } |
fdf76622 | 1497 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1498 | } |
3f7c5c10 SB |
1499 | } |
1500 | ||
845d708e SB |
1501 | static void ath9k_disable_ps(struct ath_softc *sc) |
1502 | { | |
1503 | struct ath_hw *ah = sc->sc_ah; | |
1504 | ||
1505 | sc->ps_enabled = false; | |
1506 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1507 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1508 | ath9k_hw_setrxabort(ah, 0); | |
1509 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1510 | PS_WAIT_FOR_CAB | | |
1511 | PS_WAIT_FOR_PSPOLL_DATA | | |
1512 | PS_WAIT_FOR_TX_ACK); | |
1513 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1514 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1515 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | } | |
1520 | ||
e8975581 | 1521 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1522 | { |
bce048d7 JM |
1523 | struct ath_wiphy *aphy = hw->priv; |
1524 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1525 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8975581 | 1526 | struct ieee80211_conf *conf = &hw->conf; |
194b7c13 | 1527 | bool disable_radio; |
f078f209 | 1528 | |
aa33de09 | 1529 | mutex_lock(&sc->mutex); |
141b38b6 | 1530 | |
194b7c13 LR |
1531 | /* |
1532 | * Leave this as the first check because we need to turn on the | |
1533 | * radio if it was disabled before prior to processing the rest | |
1534 | * of the changes. Likewise we must only disable the radio towards | |
1535 | * the end. | |
1536 | */ | |
64839170 | 1537 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1538 | bool enable_radio; |
1539 | bool all_wiphys_idle; | |
1540 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1541 | |
1542 | spin_lock_bh(&sc->wiphy_lock); | |
1543 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1544 | ath9k_set_wiphy_idle(aphy, idle); |
1545 | ||
11446011 | 1546 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1547 | |
1548 | /* | |
1549 | * After we unlock here its possible another wiphy | |
1550 | * can be re-renabled so to account for that we will | |
1551 | * only disable the radio toward the end of this routine | |
1552 | * if by then all wiphys are still idle. | |
1553 | */ | |
64839170 LR |
1554 | spin_unlock_bh(&sc->wiphy_lock); |
1555 | ||
194b7c13 | 1556 | if (enable_radio) { |
1dbfd9d4 | 1557 | sc->ps_idle = false; |
68a89116 | 1558 | ath_radio_enable(sc, hw); |
c46917bb LR |
1559 | ath_print(common, ATH_DBG_CONFIG, |
1560 | "not-idle: enabling radio\n"); | |
64839170 LR |
1561 | } |
1562 | } | |
1563 | ||
e7824a50 LR |
1564 | /* |
1565 | * We just prepare to enable PS. We have to wait until our AP has | |
1566 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1567 | * those ACKs and end up retransmitting the same null data frames. | |
1568 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1569 | */ | |
3cbb5dd7 | 1570 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1571 | unsigned long flags; |
1572 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1573 | if (conf->flags & IEEE80211_CONF_PS) |
1574 | ath9k_enable_ps(sc); | |
845d708e SB |
1575 | else |
1576 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1577 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1578 | } |
1579 | ||
199afd9d S |
1580 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1581 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1582 | ath_print(common, ATH_DBG_CONFIG, | |
1583 | "HW opmode set to Monitor mode\n"); | |
1584 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; | |
1585 | } | |
1586 | } | |
1587 | ||
4797938c | 1588 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1589 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1590 | int pos = curchan->hw_value; |
ae5eb026 | 1591 | |
0e2dedf9 JM |
1592 | aphy->chan_idx = pos; |
1593 | aphy->chan_is_ht = conf_is_ht(conf); | |
5ee08656 FF |
1594 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1595 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1596 | else | |
1597 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1598 | |
8089cc47 JM |
1599 | if (aphy->state == ATH_WIPHY_SCAN || |
1600 | aphy->state == ATH_WIPHY_ACTIVE) | |
1601 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1602 | else { | |
1603 | /* | |
1604 | * Do not change operational channel based on a paused | |
1605 | * wiphy changes. | |
1606 | */ | |
1607 | goto skip_chan_change; | |
1608 | } | |
0e2dedf9 | 1609 | |
c46917bb LR |
1610 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1611 | curchan->center_freq); | |
f078f209 | 1612 | |
5f8e077c | 1613 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1614 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1615 | |
ecf70441 | 1616 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1617 | |
0e2dedf9 | 1618 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1619 | ath_print(common, ATH_DBG_FATAL, |
1620 | "Unable to set channel\n"); | |
aa33de09 | 1621 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1622 | return -EINVAL; |
1623 | } | |
094d05dc | 1624 | } |
f078f209 | 1625 | |
8089cc47 | 1626 | skip_chan_change: |
c9f6a656 | 1627 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1628 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1629 | ath_update_txpow(sc); |
1630 | } | |
f078f209 | 1631 | |
194b7c13 LR |
1632 | spin_lock_bh(&sc->wiphy_lock); |
1633 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1634 | spin_unlock_bh(&sc->wiphy_lock); | |
1635 | ||
64839170 | 1636 | if (disable_radio) { |
c46917bb | 1637 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1638 | sc->ps_idle = true; |
68a89116 | 1639 | ath_radio_disable(sc, hw); |
64839170 LR |
1640 | } |
1641 | ||
aa33de09 | 1642 | mutex_unlock(&sc->mutex); |
141b38b6 | 1643 | |
f078f209 LR |
1644 | return 0; |
1645 | } | |
1646 | ||
8feceb67 VT |
1647 | #define SUPPORTED_FILTERS \ |
1648 | (FIF_PROMISC_IN_BSS | \ | |
1649 | FIF_ALLMULTI | \ | |
1650 | FIF_CONTROL | \ | |
af6a3fc7 | 1651 | FIF_PSPOLL | \ |
8feceb67 VT |
1652 | FIF_OTHER_BSS | \ |
1653 | FIF_BCN_PRBRESP_PROMISC | \ | |
1654 | FIF_FCSFAIL) | |
c83be688 | 1655 | |
8feceb67 VT |
1656 | /* FIXME: sc->sc_full_reset ? */ |
1657 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1658 | unsigned int changed_flags, | |
1659 | unsigned int *total_flags, | |
3ac64bee | 1660 | u64 multicast) |
8feceb67 | 1661 | { |
bce048d7 JM |
1662 | struct ath_wiphy *aphy = hw->priv; |
1663 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1664 | u32 rfilt; |
f078f209 | 1665 | |
8feceb67 VT |
1666 | changed_flags &= SUPPORTED_FILTERS; |
1667 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1668 | |
b77f483f | 1669 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1670 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1671 | rfilt = ath_calcrxfilter(sc); |
1672 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1673 | ath9k_ps_restore(sc); |
f078f209 | 1674 | |
c46917bb LR |
1675 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1676 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1677 | } |
f078f209 | 1678 | |
4ca77860 JB |
1679 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1680 | struct ieee80211_vif *vif, | |
1681 | struct ieee80211_sta *sta) | |
8feceb67 | 1682 | { |
bce048d7 JM |
1683 | struct ath_wiphy *aphy = hw->priv; |
1684 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1685 | |
4ca77860 JB |
1686 | ath_node_attach(sc, sta); |
1687 | ||
1688 | return 0; | |
1689 | } | |
1690 | ||
1691 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1692 | struct ieee80211_vif *vif, | |
1693 | struct ieee80211_sta *sta) | |
1694 | { | |
1695 | struct ath_wiphy *aphy = hw->priv; | |
1696 | struct ath_softc *sc = aphy->sc; | |
1697 | ||
1698 | ath_node_detach(sc, sta); | |
1699 | ||
1700 | return 0; | |
f078f209 LR |
1701 | } |
1702 | ||
141b38b6 | 1703 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1704 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1705 | { |
bce048d7 JM |
1706 | struct ath_wiphy *aphy = hw->priv; |
1707 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1708 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1709 | struct ath9k_tx_queue_info qi; |
1710 | int ret = 0, qnum; | |
f078f209 | 1711 | |
8feceb67 VT |
1712 | if (queue >= WME_NUM_AC) |
1713 | return 0; | |
f078f209 | 1714 | |
141b38b6 S |
1715 | mutex_lock(&sc->mutex); |
1716 | ||
1ffb0610 S |
1717 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1718 | ||
8feceb67 VT |
1719 | qi.tqi_aifs = params->aifs; |
1720 | qi.tqi_cwmin = params->cw_min; | |
1721 | qi.tqi_cwmax = params->cw_max; | |
1722 | qi.tqi_burstTime = params->txop; | |
1723 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1724 | |
c46917bb LR |
1725 | ath_print(common, ATH_DBG_CONFIG, |
1726 | "Configure tx [queue/halq] [%d/%d], " | |
1727 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1728 | queue, qnum, params->aifs, params->cw_min, | |
1729 | params->cw_max, params->txop); | |
f078f209 | 1730 | |
8feceb67 VT |
1731 | ret = ath_txq_update(sc, qnum, &qi); |
1732 | if (ret) | |
c46917bb | 1733 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1734 | |
94db2936 | 1735 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1d2231e2 | 1736 | if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret) |
94db2936 VN |
1737 | ath_beaconq_config(sc); |
1738 | ||
141b38b6 S |
1739 | mutex_unlock(&sc->mutex); |
1740 | ||
8feceb67 VT |
1741 | return ret; |
1742 | } | |
f078f209 | 1743 | |
8feceb67 VT |
1744 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1745 | enum set_key_cmd cmd, | |
dc822b5d JB |
1746 | struct ieee80211_vif *vif, |
1747 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1748 | struct ieee80211_key_conf *key) |
1749 | { | |
bce048d7 JM |
1750 | struct ath_wiphy *aphy = hw->priv; |
1751 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1752 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1753 | int ret = 0; |
f078f209 | 1754 | |
b3bd89ce JM |
1755 | if (modparam_nohwcrypt) |
1756 | return -ENOSPC; | |
1757 | ||
141b38b6 | 1758 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1759 | ath9k_ps_wakeup(sc); |
c46917bb | 1760 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1761 | |
8feceb67 VT |
1762 | switch (cmd) { |
1763 | case SET_KEY: | |
040e539e | 1764 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1765 | if (ret >= 0) { |
1766 | key->hw_key_idx = ret; | |
8feceb67 VT |
1767 | /* push IV and Michael MIC generation to stack */ |
1768 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1769 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1770 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1771 | if (sc->sc_ah->sw_mgmt_crypto && |
1772 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1773 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1774 | ret = 0; |
8feceb67 VT |
1775 | } |
1776 | break; | |
1777 | case DISABLE_KEY: | |
040e539e | 1778 | ath_key_delete(common, key); |
8feceb67 VT |
1779 | break; |
1780 | default: | |
1781 | ret = -EINVAL; | |
1782 | } | |
f078f209 | 1783 | |
3cbb5dd7 | 1784 | ath9k_ps_restore(sc); |
141b38b6 S |
1785 | mutex_unlock(&sc->mutex); |
1786 | ||
8feceb67 VT |
1787 | return ret; |
1788 | } | |
f078f209 | 1789 | |
8feceb67 VT |
1790 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1791 | struct ieee80211_vif *vif, | |
1792 | struct ieee80211_bss_conf *bss_conf, | |
1793 | u32 changed) | |
1794 | { | |
bce048d7 JM |
1795 | struct ath_wiphy *aphy = hw->priv; |
1796 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1797 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1798 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1799 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1800 | int slottime; |
c6089ccc | 1801 | int error; |
f078f209 | 1802 | |
141b38b6 S |
1803 | mutex_lock(&sc->mutex); |
1804 | ||
c6089ccc S |
1805 | if (changed & BSS_CHANGED_BSSID) { |
1806 | /* Set BSSID */ | |
1807 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1808 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1809 | common->curaid = 0; |
f2b2143e | 1810 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1811 | |
c6089ccc S |
1812 | /* Set aggregation protection mode parameters */ |
1813 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1814 | |
c6089ccc S |
1815 | /* Only legacy IBSS for now */ |
1816 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1817 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1818 | |
c6089ccc S |
1819 | ath_print(common, ATH_DBG_CONFIG, |
1820 | "BSSID: %pM aid: 0x%x\n", | |
1821 | common->curbssid, common->curaid); | |
2d0ddec5 | 1822 | |
c6089ccc S |
1823 | /* need to reconfigure the beacon */ |
1824 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1825 | } | |
2d0ddec5 | 1826 | |
c6089ccc S |
1827 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1828 | if ((changed & BSS_CHANGED_BEACON) || | |
1829 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1830 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1831 | error = ath_beacon_alloc(aphy, vif); | |
1832 | if (!error) | |
1833 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1834 | } |
1835 | ||
1836 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1837 | if (bss_conf->use_short_slot) | |
1838 | slottime = 9; | |
1839 | else | |
1840 | slottime = 20; | |
1841 | if (vif->type == NL80211_IFTYPE_AP) { | |
1842 | /* | |
1843 | * Defer update, so that connected stations can adjust | |
1844 | * their settings at the same time. | |
1845 | * See beacon.c for more details | |
1846 | */ | |
1847 | sc->beacon.slottime = slottime; | |
1848 | sc->beacon.updateslot = UPDATE; | |
1849 | } else { | |
1850 | ah->slottime = slottime; | |
1851 | ath9k_hw_init_global_settings(ah); | |
1852 | } | |
2d0ddec5 JB |
1853 | } |
1854 | ||
c6089ccc S |
1855 | /* Disable transmission of beacons */ |
1856 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1857 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1858 | |
c6089ccc S |
1859 | if (changed & BSS_CHANGED_BEACON_INT) { |
1860 | sc->beacon_interval = bss_conf->beacon_int; | |
1861 | /* | |
1862 | * In case of AP mode, the HW TSF has to be reset | |
1863 | * when the beacon interval changes. | |
1864 | */ | |
1865 | if (vif->type == NL80211_IFTYPE_AP) { | |
1866 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1867 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1868 | error = ath_beacon_alloc(aphy, vif); |
1869 | if (!error) | |
1870 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1871 | } else { |
1872 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1873 | } |
1874 | } | |
1875 | ||
8feceb67 | 1876 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1877 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1878 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1879 | if (bss_conf->use_short_preamble) |
1880 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1881 | else | |
1882 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1883 | } | |
f078f209 | 1884 | |
8feceb67 | 1885 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1886 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1887 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1888 | if (bss_conf->use_cts_prot && |
1889 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1890 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1891 | else | |
1892 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1893 | } | |
f078f209 | 1894 | |
8feceb67 | 1895 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1896 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1897 | bss_conf->assoc); |
5640b08e | 1898 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 1899 | } |
141b38b6 S |
1900 | |
1901 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1902 | } |
f078f209 | 1903 | |
8feceb67 VT |
1904 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1905 | { | |
1906 | u64 tsf; | |
bce048d7 JM |
1907 | struct ath_wiphy *aphy = hw->priv; |
1908 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1909 | |
141b38b6 S |
1910 | mutex_lock(&sc->mutex); |
1911 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
1912 | mutex_unlock(&sc->mutex); | |
f078f209 | 1913 | |
8feceb67 VT |
1914 | return tsf; |
1915 | } | |
f078f209 | 1916 | |
3b5d665b AF |
1917 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1918 | { | |
bce048d7 JM |
1919 | struct ath_wiphy *aphy = hw->priv; |
1920 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1921 | |
141b38b6 S |
1922 | mutex_lock(&sc->mutex); |
1923 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
1924 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
1925 | } |
1926 | ||
8feceb67 VT |
1927 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1928 | { | |
bce048d7 JM |
1929 | struct ath_wiphy *aphy = hw->priv; |
1930 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 1931 | |
141b38b6 | 1932 | mutex_lock(&sc->mutex); |
21526d57 LR |
1933 | |
1934 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1935 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1936 | ath9k_ps_restore(sc); |
1937 | ||
141b38b6 | 1938 | mutex_unlock(&sc->mutex); |
8feceb67 | 1939 | } |
f078f209 | 1940 | |
8feceb67 | 1941 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1942 | struct ieee80211_vif *vif, |
141b38b6 S |
1943 | enum ieee80211_ampdu_mlme_action action, |
1944 | struct ieee80211_sta *sta, | |
1945 | u16 tid, u16 *ssn) | |
8feceb67 | 1946 | { |
bce048d7 JM |
1947 | struct ath_wiphy *aphy = hw->priv; |
1948 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1949 | int ret = 0; |
f078f209 | 1950 | |
85ad181e JB |
1951 | local_bh_disable(); |
1952 | ||
8feceb67 VT |
1953 | switch (action) { |
1954 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
1955 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
1956 | ret = -ENOTSUPP; | |
8feceb67 VT |
1957 | break; |
1958 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1959 | break; |
1960 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1961 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1962 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1963 | if (!ret) | |
1964 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1965 | ath9k_ps_restore(sc); |
8feceb67 VT |
1966 | break; |
1967 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1968 | ath9k_ps_wakeup(sc); |
f83da965 | 1969 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1970 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1971 | ath9k_ps_restore(sc); |
8feceb67 | 1972 | break; |
b1720231 | 1973 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1974 | ath9k_ps_wakeup(sc); |
8469cdef | 1975 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1976 | ath9k_ps_restore(sc); |
8469cdef | 1977 | break; |
8feceb67 | 1978 | default: |
c46917bb LR |
1979 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1980 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
1981 | } |
1982 | ||
85ad181e JB |
1983 | local_bh_enable(); |
1984 | ||
8feceb67 | 1985 | return ret; |
f078f209 LR |
1986 | } |
1987 | ||
62dad5b0 BP |
1988 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1989 | struct survey_info *survey) | |
1990 | { | |
1991 | struct ath_wiphy *aphy = hw->priv; | |
1992 | struct ath_softc *sc = aphy->sc; | |
1993 | struct ath_hw *ah = sc->sc_ah; | |
39162dbe FF |
1994 | struct ieee80211_supported_band *sband; |
1995 | struct ath9k_channel *chan; | |
1996 | ||
1997 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
1998 | if (sband && idx >= sband->n_channels) { | |
1999 | idx -= sband->n_channels; | |
2000 | sband = NULL; | |
2001 | } | |
62dad5b0 | 2002 | |
39162dbe FF |
2003 | if (!sband) |
2004 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2005 | |
39162dbe FF |
2006 | if (!sband || idx >= sband->n_channels) |
2007 | return -ENOENT; | |
2008 | ||
2009 | survey->channel = &sband->channels[idx]; | |
2010 | chan = &ah->channels[survey->channel->hw_value]; | |
4f1a5a4b | 2011 | survey->filled = 0; |
39162dbe FF |
2012 | |
2013 | if (chan == ah->curchan) | |
2014 | survey->filled |= SURVEY_INFO_IN_USE; | |
2015 | ||
2016 | if (chan->noisefloor) { | |
4f1a5a4b | 2017 | survey->filled |= SURVEY_INFO_NOISE_DBM; |
39162dbe | 2018 | survey->noise = chan->noisefloor; |
4f1a5a4b | 2019 | } |
62dad5b0 BP |
2020 | |
2021 | return 0; | |
2022 | } | |
2023 | ||
0c98de65 S |
2024 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2025 | { | |
bce048d7 JM |
2026 | struct ath_wiphy *aphy = hw->priv; |
2027 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2028 | |
3d832611 | 2029 | mutex_lock(&sc->mutex); |
8089cc47 | 2030 | if (ath9k_wiphy_scanning(sc)) { |
8089cc47 | 2031 | /* |
30888338 LR |
2032 | * There is a race here in mac80211 but fixing it requires |
2033 | * we revisit how we handle the scan complete callback. | |
2034 | * After mac80211 fixes we will not have configured hardware | |
2035 | * to the home channel nor would we have configured the RX | |
2036 | * filter yet. | |
8089cc47 | 2037 | */ |
3d832611 | 2038 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
2039 | return; |
2040 | } | |
2041 | ||
2042 | aphy->state = ATH_WIPHY_SCAN; | |
2043 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
3d832611 | 2044 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2045 | } |
2046 | ||
30888338 LR |
2047 | /* |
2048 | * XXX: this requires a revisit after the driver | |
2049 | * scan_complete gets moved to another place/removed in mac80211. | |
2050 | */ | |
0c98de65 S |
2051 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) |
2052 | { | |
bce048d7 JM |
2053 | struct ath_wiphy *aphy = hw->priv; |
2054 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2055 | |
3d832611 | 2056 | mutex_lock(&sc->mutex); |
8089cc47 | 2057 | aphy->state = ATH_WIPHY_ACTIVE; |
3d832611 | 2058 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2059 | } |
2060 | ||
e239d859 FF |
2061 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2062 | { | |
2063 | struct ath_wiphy *aphy = hw->priv; | |
2064 | struct ath_softc *sc = aphy->sc; | |
2065 | struct ath_hw *ah = sc->sc_ah; | |
2066 | ||
2067 | mutex_lock(&sc->mutex); | |
2068 | ah->coverage_class = coverage_class; | |
2069 | ath9k_hw_init_global_settings(ah); | |
2070 | mutex_unlock(&sc->mutex); | |
2071 | } | |
2072 | ||
6baff7f9 | 2073 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2074 | .tx = ath9k_tx, |
2075 | .start = ath9k_start, | |
2076 | .stop = ath9k_stop, | |
2077 | .add_interface = ath9k_add_interface, | |
2078 | .remove_interface = ath9k_remove_interface, | |
2079 | .config = ath9k_config, | |
8feceb67 | 2080 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2081 | .sta_add = ath9k_sta_add, |
2082 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2083 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2084 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2085 | .set_key = ath9k_set_key, |
8feceb67 | 2086 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2087 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2088 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2089 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2090 | .get_survey = ath9k_get_survey, |
0c98de65 S |
2091 | .sw_scan_start = ath9k_sw_scan_start, |
2092 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2093 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2094 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2095 | }; |